Pileus Git - ~andy/linux/blob - drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TYPE_H_
  28 #define _I40E_TYPE_H_
  29
  30 #include "i40e_status.h"
  31 #include "i40e_osdep.h"
  32 #include "i40e_register.h"
  33 #include "i40e_adminq.h"
  34 #include "i40e_hmc.h"
  35 #include "i40e_lan_hmc.h"
  36
  37 /* Device IDs */
  38 #define I40E_DEV_ID_SFP_XL710           0x1572
  39 #define I40E_DEV_ID_SFP_X710            0x1573
  40 #define I40E_DEV_ID_QEMU                0x1574
  41 #define I40E_DEV_ID_KX_A                0x157F
  42 #define I40E_DEV_ID_KX_B                0x1580
  43 #define I40E_DEV_ID_KX_C                0x1581
  44 #define I40E_DEV_ID_KX_D                0x1582
  45 #define I40E_DEV_ID_QSFP_A              0x1583
  46 #define I40E_DEV_ID_QSFP_B              0x1584
  47 #define I40E_DEV_ID_QSFP_C              0x1585
  48 #define I40E_DEV_ID_VF                  0x154C
  49 #define I40E_DEV_ID_VF_HV               0x1571
  50
  51 #define i40e_is_40G_device(d)           ((d) == I40E_DEV_ID_QSFP_A  || \
  52                                          (d) == I40E_DEV_ID_QSFP_B  || \
  53                                          (d) == I40E_DEV_ID_QSFP_C)
  54
  55 #define I40E_MAX_VSI_QP                 16
  56 #define I40E_MAX_VF_VSI                 3
  57 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  58 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  59
  60 /* Max default timeout in ms, */
  61 #define I40E_MAX_NVM_TIMEOUT            18000
  62
  63 /* Switch from mc to the 2usec global time (this is the GTIME resolution) */
  64 #define I40E_MS_TO_GTIME(time)          (((time) * 1000) / 2)
  65
  66 /* forward declaration */
  67 struct i40e_hw;
  68 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  69
  70 /* Data type manipulation macros. */
  71
  72 #define I40E_DESC_UNUSED(R)     \
  73         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  74         (R)->next_to_clean - (R)->next_to_use - 1)
  75
  76 /* bitfields for Tx queue mapping in QTX_CTL */
  77 #define I40E_QTX_CTL_VF_QUEUE   0x0
  78 #define I40E_QTX_CTL_VM_QUEUE   0x1
  79 #define I40E_QTX_CTL_PF_QUEUE   0x2
  80
  81 /* debug masks - set these bits in hw->debug_mask to control output */
  82 enum i40e_debug_mask {
  83         I40E_DEBUG_INIT                 = 0x00000001,
  84         I40E_DEBUG_RELEASE              = 0x00000002,
  85
  86         I40E_DEBUG_LINK                 = 0x00000010,
  87         I40E_DEBUG_PHY                  = 0x00000020,
  88         I40E_DEBUG_HMC                  = 0x00000040,
  89         I40E_DEBUG_NVM                  = 0x00000080,
  90         I40E_DEBUG_LAN                  = 0x00000100,
  91         I40E_DEBUG_FLOW                 = 0x00000200,
  92         I40E_DEBUG_DCB                  = 0x00000400,
  93         I40E_DEBUG_DIAG                 = 0x00000800,
  94
  95         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
  96         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
  97         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
  98         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
  99         I40E_DEBUG_AQ                   = 0x0F000000,
 100
 101         I40E_DEBUG_USER                 = 0xF0000000,
 102
 103         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 104 };
 105
 106 /* These are structs for managing the hardware information and the operations.
 107  * The structures of function pointers are filled out at init time when we
 108  * know for sure exactly which hardware we're working with.  This gives us the
 109  * flexibility of using the same main driver code but adapting to slightly
 110  * different hardware needs as new parts are developed.  For this architecture,
 111  * the Firmware and AdminQ are intended to insulate the driver from most of the
 112  * future changes, but these structures will also do part of the job.
 113  */
 114 enum i40e_mac_type {
 115         I40E_MAC_UNKNOWN = 0,
 116         I40E_MAC_X710,
 117         I40E_MAC_XL710,
 118         I40E_MAC_VF,
 119         I40E_MAC_GENERIC,
 120 };
 121
 122 enum i40e_media_type {
 123         I40E_MEDIA_TYPE_UNKNOWN = 0,
 124         I40E_MEDIA_TYPE_FIBER,
 125         I40E_MEDIA_TYPE_BASET,
 126         I40E_MEDIA_TYPE_BACKPLANE,
 127         I40E_MEDIA_TYPE_CX4,
 128         I40E_MEDIA_TYPE_DA,
 129         I40E_MEDIA_TYPE_VIRTUAL
 130 };
 131
 132 enum i40e_fc_mode {
 133         I40E_FC_NONE = 0,
 134         I40E_FC_RX_PAUSE,
 135         I40E_FC_TX_PAUSE,
 136         I40E_FC_FULL,
 137         I40E_FC_PFC,
 138         I40E_FC_DEFAULT
 139 };
 140
 141 enum i40e_vsi_type {
 142         I40E_VSI_MAIN = 0,
 143         I40E_VSI_VMDQ1,
 144         I40E_VSI_VMDQ2,
 145         I40E_VSI_CTRL,
 146         I40E_VSI_FCOE,
 147         I40E_VSI_MIRROR,
 148         I40E_VSI_SRIOV,
 149         I40E_VSI_FDIR,
 150         I40E_VSI_TYPE_UNKNOWN
 151 };
 152
 153 enum i40e_queue_type {
 154         I40E_QUEUE_TYPE_RX = 0,
 155         I40E_QUEUE_TYPE_TX,
 156         I40E_QUEUE_TYPE_PE_CEQ,
 157         I40E_QUEUE_TYPE_UNKNOWN
 158 };
 159
 160 struct i40e_link_status {
 161         enum i40e_aq_phy_type phy_type;
 162         enum i40e_aq_link_speed link_speed;
 163         u8 link_info;
 164         u8 an_info;
 165         u8 ext_info;
 166         u8 loopback;
 167         /* is Link Status Event notification to SW enabled */
 168         bool lse_enable;
 169 };
 170
 171 struct i40e_phy_info {
 172         struct i40e_link_status link_info;
 173         struct i40e_link_status link_info_old;
 174         u32 autoneg_advertised;
 175         u32 phy_id;
 176         u32 module_type;
 177         bool get_link_info;
 178         enum i40e_media_type media_type;
 179 };
 180
 181 #define I40E_HW_CAP_MAX_GPIO                    30
 182 /* Capabilities of a PF or a VF or the whole device */
 183 struct i40e_hw_capabilities {
 184         u32  switch_mode;
 185 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 186 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 187 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 188
 189         u32  management_mode;
 190         u32  npar_enable;
 191         u32  os2bmc;
 192         u32  valid_functions;
 193         bool sr_iov_1_1;
 194         bool vmdq;
 195         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 196         bool evb_802_1_qbh; /* Bridge Port Extension */
 197         bool dcb;
 198         bool fcoe;
 199         bool mfp_mode_1;
 200         bool mgmt_cem;
 201         bool ieee_1588;
 202         bool iwarp;
 203         bool fd;
 204         u32 fd_filters_guaranteed;
 205         u32 fd_filters_best_effort;
 206         bool rss;
 207         u32 rss_table_size;
 208         u32 rss_table_entry_width;
 209         bool led[I40E_HW_CAP_MAX_GPIO];
 210         bool sdp[I40E_HW_CAP_MAX_GPIO];
 211         u32 nvm_image_type;
 212         u32 num_flow_director_filters;
 213         u32 num_vfs;
 214         u32 vf_base_id;
 215         u32 num_vsis;
 216         u32 num_rx_qp;
 217         u32 num_tx_qp;
 218         u32 base_queue;
 219         u32 num_msix_vectors;
 220         u32 num_msix_vectors_vf;
 221         u32 led_pin_num;
 222         u32 sdp_pin_num;
 223         u32 mdio_port_num;
 224         u32 mdio_port_mode;
 225         u8 rx_buf_chain_len;
 226         u32 enabled_tcmap;
 227         u32 maxtc;
 228 };
 229
 230 struct i40e_mac_info {
 231         enum i40e_mac_type type;
 232         u8 addr[ETH_ALEN];
 233         u8 perm_addr[ETH_ALEN];
 234         u8 san_addr[ETH_ALEN];
 235         u16 max_fcoeq;
 236 };
 237
 238 enum i40e_aq_resources_ids {
 239         I40E_NVM_RESOURCE_ID = 1
 240 };
 241
 242 enum i40e_aq_resource_access_type {
 243         I40E_RESOURCE_READ = 1,
 244         I40E_RESOURCE_WRITE
 245 };
 246
 247 struct i40e_nvm_info {
 248         u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
 249         u64 hw_semaphore_wait;    /* - || - */
 250         u32 timeout;              /* [ms] */
 251         u16 sr_size;              /* Shadow RAM size in words */
 252         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 253         u16 version;              /* NVM package version */
 254         u32 eetrack;              /* NVM data version */
 255 };
 256
 257 /* PCI bus types */
 258 enum i40e_bus_type {
 259         i40e_bus_type_unknown = 0,
 260         i40e_bus_type_pci,
 261         i40e_bus_type_pcix,
 262         i40e_bus_type_pci_express,
 263         i40e_bus_type_reserved
 264 };
 265
 266 /* PCI bus speeds */
 267 enum i40e_bus_speed {
 268         i40e_bus_speed_unknown  = 0,
 269         i40e_bus_speed_33       = 33,
 270         i40e_bus_speed_66       = 66,
 271         i40e_bus_speed_100      = 100,
 272         i40e_bus_speed_120      = 120,
 273         i40e_bus_speed_133      = 133,
 274         i40e_bus_speed_2500     = 2500,
 275         i40e_bus_speed_5000     = 5000,
 276         i40e_bus_speed_8000     = 8000,
 277         i40e_bus_speed_reserved
 278 };
 279
 280 /* PCI bus widths */
 281 enum i40e_bus_width {
 282         i40e_bus_width_unknown  = 0,
 283         i40e_bus_width_pcie_x1  = 1,
 284         i40e_bus_width_pcie_x2  = 2,
 285         i40e_bus_width_pcie_x4  = 4,
 286         i40e_bus_width_pcie_x8  = 8,
 287         i40e_bus_width_32       = 32,
 288         i40e_bus_width_64       = 64,
 289         i40e_bus_width_reserved
 290 };
 291
 292 /* Bus parameters */
 293 struct i40e_bus_info {
 294         enum i40e_bus_speed speed;
 295         enum i40e_bus_width width;
 296         enum i40e_bus_type type;
 297
 298         u16 func;
 299         u16 device;
 300         u16 lan_id;
 301 };
 302
 303 /* Flow control (FC) parameters */
 304 struct i40e_fc_info {
 305         enum i40e_fc_mode current_mode; /* FC mode in effect */
 306         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 307 };
 308
 309 #define I40E_MAX_TRAFFIC_CLASS          8
 310 #define I40E_MAX_USER_PRIORITY          8
 311 #define I40E_DCBX_MAX_APPS              32
 312 #define I40E_LLDPDU_SIZE                1500
 313
 314 /* IEEE 802.1Qaz ETS Configuration data */
 315 struct i40e_ieee_ets_config {
 316         u8 willing;
 317         u8 cbs;
 318         u8 maxtcs;
 319         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 320         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 321         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 322 };
 323
 324 /* IEEE 802.1Qaz ETS Recommendation data */
 325 struct i40e_ieee_ets_recommend {
 326         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 327         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 328         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 329 };
 330
 331 /* IEEE 802.1Qaz PFC Configuration data */
 332 struct i40e_ieee_pfc_config {
 333         u8 willing;
 334         u8 mbc;
 335         u8 pfccap;
 336         u8 pfcenable;
 337 };
 338
 339 /* IEEE 802.1Qaz Application Priority data */
 340 struct i40e_ieee_app_priority_table {
 341         u8  priority;
 342         u8  selector;
 343         u16 protocolid;
 344 };
 345
 346 struct i40e_dcbx_config {
 347         u32 numapps;
 348         struct i40e_ieee_ets_config etscfg;
 349         struct i40e_ieee_ets_recommend etsrec;
 350         struct i40e_ieee_pfc_config pfc;
 351         struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
 352 };
 353
 354 /* Port hardware description */
 355 struct i40e_hw {
 356         u8 __iomem *hw_addr;
 357         void *back;
 358
 359         /* function pointer structs */
 360         struct i40e_phy_info phy;
 361         struct i40e_mac_info mac;
 362         struct i40e_bus_info bus;
 363         struct i40e_nvm_info nvm;
 364         struct i40e_fc_info fc;
 365
 366         /* pci info */
 367         u16 device_id;
 368         u16 vendor_id;
 369         u16 subsystem_device_id;
 370         u16 subsystem_vendor_id;
 371         u8 revision_id;
 372         u8 port;
 373         bool adapter_stopped;
 374
 375         /* capabilities for entire device and PCI func */
 376         struct i40e_hw_capabilities dev_caps;
 377         struct i40e_hw_capabilities func_caps;
 378
 379         /* Flow Director shared filter space */
 380         u16 fdir_shared_filter_count;
 381
 382         /* device profile info */
 383         u8  pf_id;
 384         u16 main_vsi_seid;
 385
 386         /* Closest numa node to the device */
 387         u16 numa_node;
 388
 389         /* Admin Queue info */
 390         struct i40e_adminq_info aq;
 391
 392         /* HMC info */
 393         struct i40e_hmc_info hmc; /* HMC info struct */
 394
 395         /* LLDP/DCBX Status */
 396         u16 dcbx_status;
 397
 398         /* DCBX info */
 399         struct i40e_dcbx_config local_dcbx_config;
 400         struct i40e_dcbx_config remote_dcbx_config;
 401
 402         /* debug mask */
 403         u32 debug_mask;
 404 };
 405
 406 struct i40e_driver_version {
 407         u8 major_version;
 408         u8 minor_version;
 409         u8 build_version;
 410         u8 subbuild_version;
 411 };
 412
 413 /* RX Descriptors */
 414 union i40e_16byte_rx_desc {
 415         struct {
 416                 __le64 pkt_addr; /* Packet buffer address */
 417                 __le64 hdr_addr; /* Header buffer address */
 418         } read;
 419         struct {
 420                 struct {
 421                         struct {
 422                                 union {
 423                                         __le16 mirroring_status;
 424                                         __le16 fcoe_ctx_id;
 425                                 } mirr_fcoe;
 426                                 __le16 l2tag1;
 427                         } lo_dword;
 428                         union {
 429                                 __le32 rss; /* RSS Hash */
 430                                 __le32 fd_id; /* Flow director filter id */
 431                                 __le32 fcoe_param; /* FCoE DDP Context id */
 432                         } hi_dword;
 433                 } qword0;
 434                 struct {
 435                         /* ext status/error/pktype/length */
 436                         __le64 status_error_len;
 437                 } qword1;
 438         } wb;  /* writeback */
 439 };
 440
 441 union i40e_32byte_rx_desc {
 442         struct {
 443                 __le64  pkt_addr; /* Packet buffer address */
 444                 __le64  hdr_addr; /* Header buffer address */
 445                         /* bit 0 of hdr_buffer_addr is DD bit */
 446                 __le64  rsvd1;
 447                 __le64  rsvd2;
 448         } read;
 449         struct {
 450                 struct {
 451                         struct {
 452                                 union {
 453                                         __le16 mirroring_status;
 454                                         __le16 fcoe_ctx_id;
 455                                 } mirr_fcoe;
 456                                 __le16 l2tag1;
 457                         } lo_dword;
 458                         union {
 459                                 __le32 rss; /* RSS Hash */
 460                                 __le32 fcoe_param; /* FCoE DDP Context id */
 461                         } hi_dword;
 462                 } qword0;
 463                 struct {
 464                         /* status/error/pktype/length */
 465                         __le64 status_error_len;
 466                 } qword1;
 467                 struct {
 468                         __le16 ext_status; /* extended status */
 469                         __le16 rsvd;
 470                         __le16 l2tag2_1;
 471                         __le16 l2tag2_2;
 472                 } qword2;
 473                 struct {
 474                         union {
 475                                 __le32 flex_bytes_lo;
 476                                 __le32 pe_status;
 477                         } lo_dword;
 478                         union {
 479                                 __le32 flex_bytes_hi;
 480                                 __le32 fd_id;
 481                         } hi_dword;
 482                 } qword3;
 483         } wb;  /* writeback */
 484 };
 485
 486 #define I40E_RXD_QW1_STATUS_SHIFT       0
 487 #define I40E_RXD_QW1_STATUS_MASK        (0x7FFFUL << I40E_RXD_QW1_STATUS_SHIFT)
 488
 489 enum i40e_rx_desc_status_bits {
 490         /* Note: These are predefined bit offsets */
 491         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 492         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 493         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 494         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 495         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 496         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 497         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 498         I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
 499         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 500         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 501         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 502         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 503         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 504         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 505         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18
 506 };
 507
 508 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 509 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 510                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 511
 512 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 513 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK      (0x1UL << \
 514                                          I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 515
 516 enum i40e_rx_desc_fltstat_values {
 517         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 518         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 519         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 520         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 521 };
 522
 523 #define I40E_RXD_QW1_ERROR_SHIFT        19
 524 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 525
 526 enum i40e_rx_desc_error_bits {
 527         /* Note: These are predefined bit offsets */
 528         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 529         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 530         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 531         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 532         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 533         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 534         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 535         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6
 536 };
 537
 538 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 539         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 540         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 541         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 542         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 543         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 544 };
 545
 546 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 547 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 548
 549 /* Packet type non-ip values */
 550 enum i40e_rx_l2_ptype {
 551         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 552         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 553         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 554         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 555         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 556         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 557         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 558         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 559         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 560         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 561         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 562         I40E_RX_PTYPE_L2_ARP                            = 11,
 563         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 564         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 565         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 566         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 567         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 568         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 569         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 570         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 571         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 572         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 573         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 574         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 575         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 576         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 577 };
 578
 579 struct i40e_rx_ptype_decoded {
 580         u32 ptype:8;
 581         u32 known:1;
 582         u32 outer_ip:1;
 583         u32 outer_ip_ver:1;
 584         u32 outer_frag:1;
 585         u32 tunnel_type:3;
 586         u32 tunnel_end_prot:2;
 587         u32 tunnel_end_frag:1;
 588         u32 inner_prot:4;
 589         u32 payload_layer:3;
 590 };
 591
 592 enum i40e_rx_ptype_outer_ip {
 593         I40E_RX_PTYPE_OUTER_L2  = 0,
 594         I40E_RX_PTYPE_OUTER_IP  = 1
 595 };
 596
 597 enum i40e_rx_ptype_outer_ip_ver {
 598         I40E_RX_PTYPE_OUTER_NONE        = 0,
 599         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 600         I40E_RX_PTYPE_OUTER_IPV6        = 1
 601 };
 602
 603 enum i40e_rx_ptype_outer_fragmented {
 604         I40E_RX_PTYPE_NOT_FRAG  = 0,
 605         I40E_RX_PTYPE_FRAG      = 1
 606 };
 607
 608 enum i40e_rx_ptype_tunnel_type {
 609         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 610         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 611         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 612         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 613         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 614 };
 615
 616 enum i40e_rx_ptype_tunnel_end_prot {
 617         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 618         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 619         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 620 };
 621
 622 enum i40e_rx_ptype_inner_prot {
 623         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 624         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 625         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 626         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 627         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 628         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 629 };
 630
 631 enum i40e_rx_ptype_payload_layer {
 632         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 633         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 634         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 635         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 636 };
 637
 638 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 639 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 640                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 641
 642 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 643 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 644                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 645
 646 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 647 #define I40E_RXD_QW1_LENGTH_SPH_MASK    (0x1ULL << \
 648                                          I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 649
 650 enum i40e_rx_desc_ext_status_bits {
 651         /* Note: These are predefined bit offsets */
 652         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 653         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 654         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 655         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 656         I40E_RX_DESC_EXT_STATUS_FTYPE_SHIFT     = 6, /* 3 BITS */
 657         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 658         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 659         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 660 };
 661
 662 enum i40e_rx_desc_pe_status_bits {
 663         /* Note: These are predefined bit offsets */
 664         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 665         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 666         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 667         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 668         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 669         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 670         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 671         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 672         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 673 };
 674
 675 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 676 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 677
 678 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 679 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 680                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 681
 682 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 683 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 684                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 685
 686 enum i40e_rx_prog_status_desc_status_bits {
 687         /* Note: These are predefined bit offsets */
 688         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 689         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 690 };
 691
 692 enum i40e_rx_prog_status_desc_prog_id_masks {
 693         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 694         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 695         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 696 };
 697
 698 enum i40e_rx_prog_status_desc_error_bits {
 699         /* Note: These are predefined bit offsets */
 700         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 701         I40E_RX_PROG_STATUS_DESC_NO_FD_QUOTA_SHIFT      = 1,
 702         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 703         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 704 };
 705
 706 /* TX Descriptor */
 707 struct i40e_tx_desc {
 708         __le64 buffer_addr; /* Address of descriptor's data buf */
 709         __le64 cmd_type_offset_bsz;
 710 };
 711
 712 #define I40E_TXD_QW1_DTYPE_SHIFT        0
 713 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
 714
 715 enum i40e_tx_desc_dtype_value {
 716         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 717         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 718         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 719         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 720         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 721         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 722         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 723         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 724         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 725         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 726 };
 727
 728 #define I40E_TXD_QW1_CMD_SHIFT  4
 729 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
 730
 731 enum i40e_tx_desc_cmd_bits {
 732         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 733         I40E_TX_DESC_CMD_RS                     = 0x0002,
 734         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 735         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 736         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 737         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 738         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 739         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 740         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 741         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 742         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 743         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 744         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 745         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 746         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 747         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 748         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 749         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 750 };
 751
 752 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 753 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 754                                          I40E_TXD_QW1_OFFSET_SHIFT)
 755
 756 enum i40e_tx_desc_length_fields {
 757         /* Note: These are predefined bit offsets */
 758         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 759         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 760         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 761 };
 762
 763 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 764 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 765                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 766
 767 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 768 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
 769
 770 /* Context descriptors */
 771 struct i40e_tx_context_desc {
 772         __le32 tunneling_params;
 773         __le16 l2tag2;
 774         __le16 rsvd;
 775         __le64 type_cmd_tso_mss;
 776 };
 777
 778 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
 779 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
 780
 781 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 782 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
 783
 784 enum i40e_tx_ctx_desc_cmd_bits {
 785         I40E_TX_CTX_DESC_TSO            = 0x01,
 786         I40E_TX_CTX_DESC_TSYN           = 0x02,
 787         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 788         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 789         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 790         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 791         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 792         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 793         I40E_TX_CTX_DESC_SWPE           = 0x40
 794 };
 795
 796 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 797 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 798                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
 799
 800 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 801 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 802                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
 803
 804 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
 805 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
 806
 807 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
 808 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 809                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
 810
 811 enum i40e_tx_ctx_desc_eipt_offload {
 812         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 813         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 814         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 815         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 816 };
 817
 818 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 819 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 820                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 821
 822 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 823 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 824
 825 #define I40E_TXD_CTX_UDP_TUNNELING      (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 826 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 827
 828 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 829 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
 830                                          I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 831
 832 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
 833
 834 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
 835 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 836                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
 837
 838 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
 839 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 840                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 841
 842 struct i40e_filter_program_desc {
 843         __le32 qindex_flex_ptype_vsi;
 844         __le32 rsvd;
 845         __le32 dtype_cmd_cntindex;
 846         __le32 fd_id;
 847 };
 848 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
 849 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
 850                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
 851 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
 852 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
 853                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
 854 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
 855 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
 856                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
 857
 858 /* Packet Classifier Types for filters */
 859 enum i40e_filter_pctype {
 860         /* Note: Values 0-28 are reserved for future use */
 861         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
 862         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
 863         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 864         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN            = 32,
 865         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 866         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 867         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 868         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 869         /* Note: Values 37-38 are reserved for future use */
 870         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
 871         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
 872         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
 873         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN            = 42,
 874         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
 875         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
 876         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
 877         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
 878         /* Note: Value 47 is reserved for future use */
 879         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
 880         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
 881         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
 882         /* Note: Values 51-62 are reserved for future use */
 883         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
 884 };
 885
 886 enum i40e_filter_program_desc_dest {
 887         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
 888         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
 889         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
 890 };
 891
 892 enum i40e_filter_program_desc_fd_status {
 893         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
 894         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
 895         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
 896         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
 897 };
 898
 899 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
 900 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
 901                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
 902
 903 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
 904 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
 905                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
 906
 907 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 908 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
 909
 910 enum i40e_filter_program_desc_pcmd {
 911         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
 912         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
 913 };
 914
 915 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 916 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
 917
 918 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
 919 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  (0x1ULL << \
 920                                          I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
 921
 922 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
 923                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
 924 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
 925                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
 926
 927 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
 928 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
 929                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
 930
 931 enum i40e_filter_type {
 932         I40E_FLOW_DIRECTOR_FLTR = 0,
 933         I40E_PE_QUAD_HASH_FLTR = 1,
 934         I40E_ETHERTYPE_FLTR,
 935         I40E_FCOE_CTX_FLTR,
 936         I40E_MAC_VLAN_FLTR,
 937         I40E_HASH_FLTR
 938 };
 939
 940 struct i40e_vsi_context {
 941         u16 seid;
 942         u16 uplink_seid;
 943         u16 vsi_number;
 944         u16 vsis_allocated;
 945         u16 vsis_unallocated;
 946         u16 flags;
 947         u8 pf_num;
 948         u8 vf_num;
 949         u8 connection_type;
 950         struct i40e_aqc_vsi_properties_data info;
 951 };
 952
 953 /* Statistics collected by each port, VSI, VEB, and S-channel */
 954 struct i40e_eth_stats {
 955         u64 rx_bytes;                   /* gorc */
 956         u64 rx_unicast;                 /* uprc */
 957         u64 rx_multicast;               /* mprc */
 958         u64 rx_broadcast;               /* bprc */
 959         u64 rx_discards;                /* rdpc */
 960         u64 rx_errors;                  /* repc */
 961         u64 rx_missed;                  /* rmpc */
 962         u64 rx_unknown_protocol;        /* rupp */
 963         u64 tx_bytes;                   /* gotc */
 964         u64 tx_unicast;                 /* uptc */
 965         u64 tx_multicast;               /* mptc */
 966         u64 tx_broadcast;               /* bptc */
 967         u64 tx_discards;                /* tdpc */
 968         u64 tx_errors;                  /* tepc */
 969 };
 970
 971 /* Statistics collected by the MAC */
 972 struct i40e_hw_port_stats {
 973         /* eth stats collected by the port */
 974         struct i40e_eth_stats eth;
 975
 976         /* additional port specific stats */
 977         u64 tx_dropped_link_down;       /* tdold */
 978         u64 crc_errors;                 /* crcerrs */
 979         u64 illegal_bytes;              /* illerrc */
 980         u64 error_bytes;                /* errbc */
 981         u64 mac_local_faults;           /* mlfc */
 982         u64 mac_remote_faults;          /* mrfc */
 983         u64 rx_length_errors;           /* rlec */
 984         u64 link_xon_rx;                /* lxonrxc */
 985         u64 link_xoff_rx;               /* lxoffrxc */
 986         u64 priority_xon_rx[8];         /* pxonrxc[8] */
 987         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
 988         u64 link_xon_tx;                /* lxontxc */
 989         u64 link_xoff_tx;               /* lxofftxc */
 990         u64 priority_xon_tx[8];         /* pxontxc[8] */
 991         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
 992         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
 993         u64 rx_size_64;                 /* prc64 */
 994         u64 rx_size_127;                /* prc127 */
 995         u64 rx_size_255;                /* prc255 */
 996         u64 rx_size_511;                /* prc511 */
 997         u64 rx_size_1023;               /* prc1023 */
 998         u64 rx_size_1522;               /* prc1522 */
 999         u64 rx_size_big;                /* prc9522 */
1000         u64 rx_undersize;               /* ruc */
1001         u64 rx_fragments;               /* rfc */
1002         u64 rx_oversize;                /* roc */
1003         u64 rx_jabber;                  /* rjc */
1004         u64 tx_size_64;                 /* ptc64 */
1005         u64 tx_size_127;                /* ptc127 */
1006         u64 tx_size_255;                /* ptc255 */
1007         u64 tx_size_511;                /* ptc511 */
1008         u64 tx_size_1023;               /* ptc1023 */
1009         u64 tx_size_1522;               /* ptc1522 */
1010         u64 tx_size_big;                /* ptc9522 */
1011         u64 mac_short_packet_dropped;   /* mspdc */
1012         u64 checksum_error;             /* xec */
1013 };
1014
1015 /* Checksum and Shadow RAM pointers */
1016 #define I40E_SR_NVM_CONTROL_WORD                0x00
1017 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1018 #define I40E_SR_NVM_IMAGE_VERSION               0x18
1019 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1020 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1021 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1022 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1023 #define I40E_SR_VPD_PTR                         0x2F
1024 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1025 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1026
1027 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1028 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1029 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1030 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1031 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1032
1033 /* Shadow RAM related */
1034 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1035 #define I40E_SR_WORDS_IN_1KB            512
1036 /* Checksum should be calculated such that after adding all the words,
1037  * including the checksum word itself, the sum should be 0xBABA.
1038  */
1039 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1040
1041 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1042
1043 enum i40e_switch_element_types {
1044         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1045         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1046         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1047         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1048         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1049         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1050         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1051         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1052         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1053 };
1054
1055 /* Supported EtherType filters */
1056 enum i40e_ether_type_index {
1057         I40E_ETHER_TYPE_1588            = 0,
1058         I40E_ETHER_TYPE_FIP             = 1,
1059         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1060         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1061         I40E_ETHER_TYPE_LLDP            = 4,
1062         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1063         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1064         I40E_ETHER_TYPE_QCN_CNM         = 7,
1065         I40E_ETHER_TYPE_8021X           = 8,
1066         I40E_ETHER_TYPE_ARP             = 9,
1067         I40E_ETHER_TYPE_RSV1            = 10,
1068         I40E_ETHER_TYPE_RSV2            = 11,
1069 };
1070
1071 /* Filter context base size is 1K */
1072 #define I40E_HASH_FILTER_BASE_SIZE      1024
1073 /* Supported Hash filter values */
1074 enum i40e_hash_filter_size {
1075         I40E_HASH_FILTER_SIZE_1K        = 0,
1076         I40E_HASH_FILTER_SIZE_2K        = 1,
1077         I40E_HASH_FILTER_SIZE_4K        = 2,
1078         I40E_HASH_FILTER_SIZE_8K        = 3,
1079         I40E_HASH_FILTER_SIZE_16K       = 4,
1080         I40E_HASH_FILTER_SIZE_32K       = 5,
1081         I40E_HASH_FILTER_SIZE_64K       = 6,
1082         I40E_HASH_FILTER_SIZE_128K      = 7,
1083         I40E_HASH_FILTER_SIZE_256K      = 8,
1084         I40E_HASH_FILTER_SIZE_512K      = 9,
1085         I40E_HASH_FILTER_SIZE_1M        = 10,
1086 };
1087
1088 /* DMA context base size is 0.5K */
1089 #define I40E_DMA_CNTX_BASE_SIZE         512
1090 /* Supported DMA context values */
1091 enum i40e_dma_cntx_size {
1092         I40E_DMA_CNTX_SIZE_512          = 0,
1093         I40E_DMA_CNTX_SIZE_1K           = 1,
1094         I40E_DMA_CNTX_SIZE_2K           = 2,
1095         I40E_DMA_CNTX_SIZE_4K           = 3,
1096         I40E_DMA_CNTX_SIZE_8K           = 4,
1097         I40E_DMA_CNTX_SIZE_16K          = 5,
1098         I40E_DMA_CNTX_SIZE_32K          = 6,
1099         I40E_DMA_CNTX_SIZE_64K          = 7,
1100         I40E_DMA_CNTX_SIZE_128K         = 8,
1101         I40E_DMA_CNTX_SIZE_256K         = 9,
1102 };
1103
1104 /* Supported Hash look up table (LUT) sizes */
1105 enum i40e_hash_lut_size {
1106         I40E_HASH_LUT_SIZE_128          = 0,
1107         I40E_HASH_LUT_SIZE_512          = 1,
1108 };
1109
1110 /* Structure to hold a per PF filter control settings */
1111 struct i40e_filter_control_settings {
1112         /* number of PE Quad Hash filter buckets */
1113         enum i40e_hash_filter_size pe_filt_num;
1114         /* number of PE Quad Hash contexts */
1115         enum i40e_dma_cntx_size pe_cntx_num;
1116         /* number of FCoE filter buckets */
1117         enum i40e_hash_filter_size fcoe_filt_num;
1118         /* number of FCoE DDP contexts */
1119         enum i40e_dma_cntx_size fcoe_cntx_num;
1120         /* size of the Hash LUT */
1121         enum i40e_hash_lut_size hash_lut_size;
1122         /* enable FDIR filters for PF and its VFs */
1123         bool enable_fdir;
1124         /* enable Ethertype filters for PF and its VFs */
1125         bool enable_ethtype;
1126         /* enable MAC/VLAN filters for PF and its VFs */
1127         bool enable_macvlan;
1128 };
1129
1130 /* Structure to hold device level control filter counts */
1131 struct i40e_control_filter_stats {
1132         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1133         u16 etype_used;       /* Used perfect EtherType filters */
1134         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1135         u16 etype_free;       /* Un-used perfect EtherType filters */
1136 };
1137
1138 enum i40e_reset_type {
1139         I40E_RESET_POR          = 0,
1140         I40E_RESET_CORER        = 1,
1141         I40E_RESET_GLOBR        = 2,
1142         I40E_RESET_EMPR         = 3,
1143 };
1144 #endif /* _I40E_TYPE_H_ */