Pileus Git - ~andy/linux/blob - drivers/net/ethernet/intel/i40e/i40e_adminq.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * The full GNU General Public License is included in this distribution in
  20  * the file called "COPYING".
  21  *
  22  * Contact Information:
  23  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25  *
  26  ******************************************************************************/
  27
  28 #include "i40e_status.h"
  29 #include "i40e_type.h"
  30 #include "i40e_register.h"
  31 #include "i40e_adminq.h"
  32 #include "i40e_prototype.h"
  33
  34 static void i40e_resume_aq(struct i40e_hw *hw);
  35
  36 /**
  37  *  i40e_adminq_init_regs - Initialize AdminQ registers
  38  *  @hw: pointer to the hardware structure
  39  *
  40  *  This assumes the alloc_asq and alloc_arq functions have already been called
  41  **/
  42 static void i40e_adminq_init_regs(struct i40e_hw *hw)
  43 {
  44         /* set head and tail registers in our local struct */
  45         if (hw->mac.type == I40E_MAC_VF) {
  46                 hw->aq.asq.tail = I40E_VF_ATQT1;
  47                 hw->aq.asq.head = I40E_VF_ATQH1;
  48                 hw->aq.asq.len  = I40E_VF_ATQLEN1;
  49                 hw->aq.arq.tail = I40E_VF_ARQT1;
  50                 hw->aq.arq.head = I40E_VF_ARQH1;
  51                 hw->aq.arq.len  = I40E_VF_ARQLEN1;
  52         } else {
  53                 hw->aq.asq.tail = I40E_PF_ATQT;
  54                 hw->aq.asq.head = I40E_PF_ATQH;
  55                 hw->aq.asq.len  = I40E_PF_ATQLEN;
  56                 hw->aq.arq.tail = I40E_PF_ARQT;
  57                 hw->aq.arq.head = I40E_PF_ARQH;
  58                 hw->aq.arq.len  = I40E_PF_ARQLEN;
  59         }
  60 }
  61
  62 /**
  63  *  i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
  64  *  @hw: pointer to the hardware structure
  65  **/
  66 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
  67 {
  68         i40e_status ret_code;
  69
  70         ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
  71                                          i40e_mem_atq_ring,
  72                                          (hw->aq.num_asq_entries *
  73                                          sizeof(struct i40e_aq_desc)),
  74                                          I40E_ADMINQ_DESC_ALIGNMENT);
  75         if (ret_code)
  76                 return ret_code;
  77
  78         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
  79                                           (hw->aq.num_asq_entries *
  80                                           sizeof(struct i40e_asq_cmd_details)));
  81         if (ret_code) {
  82                 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
  83                 return ret_code;
  84         }
  85
  86         return ret_code;
  87 }
  88
  89 /**
  90  *  i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
  91  *  @hw: pointer to the hardware structure
  92  **/
  93 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
  94 {
  95         i40e_status ret_code;
  96
  97         ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
  98                                          i40e_mem_arq_ring,
  99                                          (hw->aq.num_arq_entries *
 100                                          sizeof(struct i40e_aq_desc)),
 101                                          I40E_ADMINQ_DESC_ALIGNMENT);
 102
 103         return ret_code;
 104 }
 105
 106 /**
 107  *  i40e_free_adminq_asq - Free Admin Queue send rings
 108  *  @hw: pointer to the hardware structure
 109  *
 110  *  This assumes the posted send buffers have already been cleaned
 111  *  and de-allocated
 112  **/
 113 static void i40e_free_adminq_asq(struct i40e_hw *hw)
 114 {
 115         i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
 116 }
 117
 118 /**
 119  *  i40e_free_adminq_arq - Free Admin Queue receive rings
 120  *  @hw: pointer to the hardware structure
 121  *
 122  *  This assumes the posted receive buffers have already been cleaned
 123  *  and de-allocated
 124  **/
 125 static void i40e_free_adminq_arq(struct i40e_hw *hw)
 126 {
 127         i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
 128 }
 129
 130 /**
 131  *  i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
 132  *  @hw:     pointer to the hardware structure
 133  **/
 134 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
 135 {
 136         i40e_status ret_code;
 137         struct i40e_aq_desc *desc;
 138         struct i40e_dma_mem *bi;
 139         int i;
 140
 141         /* We'll be allocating the buffer info memory first, then we can
 142          * allocate the mapped buffers for the event processing
 143          */
 144
 145         /* buffer_info structures do not need alignment */
 146         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
 147                 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
 148         if (ret_code)
 149                 goto alloc_arq_bufs;
 150         hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
 151
 152         /* allocate the mapped buffers */
 153         for (i = 0; i < hw->aq.num_arq_entries; i++) {
 154                 bi = &hw->aq.arq.r.arq_bi[i];
 155                 ret_code = i40e_allocate_dma_mem(hw, bi,
 156                                                  i40e_mem_arq_buf,
 157                                                  hw->aq.arq_buf_size,
 158                                                  I40E_ADMINQ_DESC_ALIGNMENT);
 159                 if (ret_code)
 160                         goto unwind_alloc_arq_bufs;
 161
 162                 /* now configure the descriptors for use */
 163                 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
 164
 165                 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
 166                 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
 167                         desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
 168                 desc->opcode = 0;
 169                 /* This is in accordance with Admin queue design, there is no
 170                  * register for buffer size configuration
 171                  */
 172                 desc->datalen = cpu_to_le16((u16)bi->size);
 173                 desc->retval = 0;
 174                 desc->cookie_high = 0;
 175                 desc->cookie_low = 0;
 176                 desc->params.external.addr_high =
 177                         cpu_to_le32(upper_32_bits(bi->pa));
 178                 desc->params.external.addr_low =
 179                         cpu_to_le32(lower_32_bits(bi->pa));
 180                 desc->params.external.param0 = 0;
 181                 desc->params.external.param1 = 0;
 182         }
 183
 184 alloc_arq_bufs:
 185         return ret_code;
 186
 187 unwind_alloc_arq_bufs:
 188         /* don't try to free the one that failed... */
 189         i--;
 190         for (; i >= 0; i--)
 191                 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
 192         i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
 193
 194         return ret_code;
 195 }
 196
 197 /**
 198  *  i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
 199  *  @hw:     pointer to the hardware structure
 200  **/
 201 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
 202 {
 203         i40e_status ret_code;
 204         struct i40e_dma_mem *bi;
 205         int i;
 206
 207         /* No mapped memory needed yet, just the buffer info structures */
 208         ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
 209                 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
 210         if (ret_code)
 211                 goto alloc_asq_bufs;
 212         hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
 213
 214         /* allocate the mapped buffers */
 215         for (i = 0; i < hw->aq.num_asq_entries; i++) {
 216                 bi = &hw->aq.asq.r.asq_bi[i];
 217                 ret_code = i40e_allocate_dma_mem(hw, bi,
 218                                                  i40e_mem_asq_buf,
 219                                                  hw->aq.asq_buf_size,
 220                                                  I40E_ADMINQ_DESC_ALIGNMENT);
 221                 if (ret_code)
 222                         goto unwind_alloc_asq_bufs;
 223         }
 224 alloc_asq_bufs:
 225         return ret_code;
 226
 227 unwind_alloc_asq_bufs:
 228         /* don't try to free the one that failed... */
 229         i--;
 230         for (; i >= 0; i--)
 231                 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
 232         i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
 233
 234         return ret_code;
 235 }
 236
 237 /**
 238  *  i40e_free_arq_bufs - Free receive queue buffer info elements
 239  *  @hw:     pointer to the hardware structure
 240  **/
 241 static void i40e_free_arq_bufs(struct i40e_hw *hw)
 242 {
 243         int i;
 244
 245         /* free descriptors */
 246         for (i = 0; i < hw->aq.num_arq_entries; i++)
 247                 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
 248
 249         /* free the descriptor memory */
 250         i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
 251
 252         /* free the dma header */
 253         i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
 254 }
 255
 256 /**
 257  *  i40e_free_asq_bufs - Free send queue buffer info elements
 258  *  @hw:     pointer to the hardware structure
 259  **/
 260 static void i40e_free_asq_bufs(struct i40e_hw *hw)
 261 {
 262         int i;
 263
 264         /* only unmap if the address is non-NULL */
 265         for (i = 0; i < hw->aq.num_asq_entries; i++)
 266                 if (hw->aq.asq.r.asq_bi[i].pa)
 267                         i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
 268
 269         /* free the buffer info list */
 270         i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
 271
 272         /* free the descriptor memory */
 273         i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
 274
 275         /* free the dma header */
 276         i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
 277 }
 278
 279 /**
 280  *  i40e_config_asq_regs - configure ASQ registers
 281  *  @hw:     pointer to the hardware structure
 282  *
 283  *  Configure base address and length registers for the transmit queue
 284  **/
 285 static void i40e_config_asq_regs(struct i40e_hw *hw)
 286 {
 287         if (hw->mac.type == I40E_MAC_VF) {
 288                 /* configure the transmit queue */
 289                 wr32(hw, I40E_VF_ATQBAH1,
 290                     upper_32_bits(hw->aq.asq.desc_buf.pa));
 291                 wr32(hw, I40E_VF_ATQBAL1,
 292                     lower_32_bits(hw->aq.asq.desc_buf.pa));
 293                 wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
 294                                           I40E_VF_ATQLEN1_ATQENABLE_MASK));
 295         } else {
 296                 /* configure the transmit queue */
 297                 wr32(hw, I40E_PF_ATQBAH,
 298                     upper_32_bits(hw->aq.asq.desc_buf.pa));
 299                 wr32(hw, I40E_PF_ATQBAL,
 300                     lower_32_bits(hw->aq.asq.desc_buf.pa));
 301                 wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
 302                                           I40E_PF_ATQLEN_ATQENABLE_MASK));
 303         }
 304 }
 305
 306 /**
 307  *  i40e_config_arq_regs - ARQ register configuration
 308  *  @hw:     pointer to the hardware structure
 309  *
 310  * Configure base address and length registers for the receive (event queue)
 311  **/
 312 static void i40e_config_arq_regs(struct i40e_hw *hw)
 313 {
 314         if (hw->mac.type == I40E_MAC_VF) {
 315                 /* configure the receive queue */
 316                 wr32(hw, I40E_VF_ARQBAH1,
 317                     upper_32_bits(hw->aq.arq.desc_buf.pa));
 318                 wr32(hw, I40E_VF_ARQBAL1,
 319                     lower_32_bits(hw->aq.arq.desc_buf.pa));
 320                 wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
 321                                           I40E_VF_ARQLEN1_ARQENABLE_MASK));
 322         } else {
 323                 /* configure the receive queue */
 324                 wr32(hw, I40E_PF_ARQBAH,
 325                     upper_32_bits(hw->aq.arq.desc_buf.pa));
 326                 wr32(hw, I40E_PF_ARQBAL,
 327                     lower_32_bits(hw->aq.arq.desc_buf.pa));
 328                 wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
 329                                           I40E_PF_ARQLEN_ARQENABLE_MASK));
 330         }
 331
 332         /* Update tail in the HW to post pre-allocated buffers */
 333         wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
 334 }
 335
 336 /**
 337  *  i40e_init_asq - main initialization routine for ASQ
 338  *  @hw:     pointer to the hardware structure
 339  *
 340  *  This is the main initialization routine for the Admin Send Queue
 341  *  Prior to calling this function, drivers *MUST* set the following fields
 342  *  in the hw->aq structure:
 343  *     - hw->aq.num_asq_entries
 344  *     - hw->aq.arq_buf_size
 345  *
 346  *  Do *NOT* hold the lock when calling this as the memory allocation routines
 347  *  called are not going to be atomic context safe
 348  **/
 349 static i40e_status i40e_init_asq(struct i40e_hw *hw)
 350 {
 351         i40e_status ret_code = 0;
 352
 353         if (hw->aq.asq.count > 0) {
 354                 /* queue already initialized */
 355                 ret_code = I40E_ERR_NOT_READY;
 356                 goto init_adminq_exit;
 357         }
 358
 359         /* verify input for valid configuration */
 360         if ((hw->aq.num_asq_entries == 0) ||
 361             (hw->aq.asq_buf_size == 0)) {
 362                 ret_code = I40E_ERR_CONFIG;
 363                 goto init_adminq_exit;
 364         }
 365
 366         hw->aq.asq.next_to_use = 0;
 367         hw->aq.asq.next_to_clean = 0;
 368         hw->aq.asq.count = hw->aq.num_asq_entries;
 369
 370         /* allocate the ring memory */
 371         ret_code = i40e_alloc_adminq_asq_ring(hw);
 372         if (ret_code)
 373                 goto init_adminq_exit;
 374
 375         /* allocate buffers in the rings */
 376         ret_code = i40e_alloc_asq_bufs(hw);
 377         if (ret_code)
 378                 goto init_adminq_free_rings;
 379
 380         /* initialize base registers */
 381         i40e_config_asq_regs(hw);
 382
 383         /* success! */
 384         goto init_adminq_exit;
 385
 386 init_adminq_free_rings:
 387         i40e_free_adminq_asq(hw);
 388
 389 init_adminq_exit:
 390         return ret_code;
 391 }
 392
 393 /**
 394  *  i40e_init_arq - initialize ARQ
 395  *  @hw:     pointer to the hardware structure
 396  *
 397  *  The main initialization routine for the Admin Receive (Event) Queue.
 398  *  Prior to calling this function, drivers *MUST* set the following fields
 399  *  in the hw->aq structure:
 400  *     - hw->aq.num_asq_entries
 401  *     - hw->aq.arq_buf_size
 402  *
 403  *  Do *NOT* hold the lock when calling this as the memory allocation routines
 404  *  called are not going to be atomic context safe
 405  **/
 406 static i40e_status i40e_init_arq(struct i40e_hw *hw)
 407 {
 408         i40e_status ret_code = 0;
 409
 410         if (hw->aq.arq.count > 0) {
 411                 /* queue already initialized */
 412                 ret_code = I40E_ERR_NOT_READY;
 413                 goto init_adminq_exit;
 414         }
 415
 416         /* verify input for valid configuration */
 417         if ((hw->aq.num_arq_entries == 0) ||
 418             (hw->aq.arq_buf_size == 0)) {
 419                 ret_code = I40E_ERR_CONFIG;
 420                 goto init_adminq_exit;
 421         }
 422
 423         hw->aq.arq.next_to_use = 0;
 424         hw->aq.arq.next_to_clean = 0;
 425         hw->aq.arq.count = hw->aq.num_arq_entries;
 426
 427         /* allocate the ring memory */
 428         ret_code = i40e_alloc_adminq_arq_ring(hw);
 429         if (ret_code)
 430                 goto init_adminq_exit;
 431
 432         /* allocate buffers in the rings */
 433         ret_code = i40e_alloc_arq_bufs(hw);
 434         if (ret_code)
 435                 goto init_adminq_free_rings;
 436
 437         /* initialize base registers */
 438         i40e_config_arq_regs(hw);
 439
 440         /* success! */
 441         goto init_adminq_exit;
 442
 443 init_adminq_free_rings:
 444         i40e_free_adminq_arq(hw);
 445
 446 init_adminq_exit:
 447         return ret_code;
 448 }
 449
 450 /**
 451  *  i40e_shutdown_asq - shutdown the ASQ
 452  *  @hw:     pointer to the hardware structure
 453  *
 454  *  The main shutdown routine for the Admin Send Queue
 455  **/
 456 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
 457 {
 458         i40e_status ret_code = 0;
 459
 460         if (hw->aq.asq.count == 0)
 461                 return I40E_ERR_NOT_READY;
 462
 463         /* Stop firmware AdminQ processing */
 464         wr32(hw, hw->aq.asq.head, 0);
 465         wr32(hw, hw->aq.asq.tail, 0);
 466         wr32(hw, hw->aq.asq.len, 0);
 467
 468         /* make sure lock is available */
 469         mutex_lock(&hw->aq.asq_mutex);
 470
 471         hw->aq.asq.count = 0; /* to indicate uninitialized queue */
 472
 473         /* free ring buffers */
 474         i40e_free_asq_bufs(hw);
 475
 476         mutex_unlock(&hw->aq.asq_mutex);
 477
 478         return ret_code;
 479 }
 480
 481 /**
 482  *  i40e_shutdown_arq - shutdown ARQ
 483  *  @hw:     pointer to the hardware structure
 484  *
 485  *  The main shutdown routine for the Admin Receive Queue
 486  **/
 487 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
 488 {
 489         i40e_status ret_code = 0;
 490
 491         if (hw->aq.arq.count == 0)
 492                 return I40E_ERR_NOT_READY;
 493
 494         /* Stop firmware AdminQ processing */
 495         wr32(hw, hw->aq.arq.head, 0);
 496         wr32(hw, hw->aq.arq.tail, 0);
 497         wr32(hw, hw->aq.arq.len, 0);
 498
 499         /* make sure lock is available */
 500         mutex_lock(&hw->aq.arq_mutex);
 501
 502         hw->aq.arq.count = 0; /* to indicate uninitialized queue */
 503
 504         /* free ring buffers */
 505         i40e_free_arq_bufs(hw);
 506
 507         mutex_unlock(&hw->aq.arq_mutex);
 508
 509         return ret_code;
 510 }
 511
 512 /**
 513  *  i40e_init_adminq - main initialization routine for Admin Queue
 514  *  @hw:     pointer to the hardware structure
 515  *
 516  *  Prior to calling this function, drivers *MUST* set the following fields
 517  *  in the hw->aq structure:
 518  *     - hw->aq.num_asq_entries
 519  *     - hw->aq.num_arq_entries
 520  *     - hw->aq.arq_buf_size
 521  *     - hw->aq.asq_buf_size
 522  **/
 523 i40e_status i40e_init_adminq(struct i40e_hw *hw)
 524 {
 525         i40e_status ret_code;
 526         u16 eetrack_lo, eetrack_hi;
 527         int retry = 0;
 528
 529         /* verify input for valid configuration */
 530         if ((hw->aq.num_arq_entries == 0) ||
 531             (hw->aq.num_asq_entries == 0) ||
 532             (hw->aq.arq_buf_size == 0) ||
 533             (hw->aq.asq_buf_size == 0)) {
 534                 ret_code = I40E_ERR_CONFIG;
 535                 goto init_adminq_exit;
 536         }
 537
 538         /* initialize locks */
 539         mutex_init(&hw->aq.asq_mutex);
 540         mutex_init(&hw->aq.arq_mutex);
 541
 542         /* Set up register offsets */
 543         i40e_adminq_init_regs(hw);
 544
 545         /* allocate the ASQ */
 546         ret_code = i40e_init_asq(hw);
 547         if (ret_code)
 548                 goto init_adminq_destroy_locks;
 549
 550         /* allocate the ARQ */
 551         ret_code = i40e_init_arq(hw);
 552         if (ret_code)
 553                 goto init_adminq_free_asq;
 554
 555         /* There are some cases where the firmware may not be quite ready
 556          * for AdminQ operations, so we retry the AdminQ setup a few times
 557          * if we see timeouts in this first AQ call.
 558          */
 559         do {
 560                 ret_code = i40e_aq_get_firmware_version(hw,
 561                                                         &hw->aq.fw_maj_ver,
 562                                                         &hw->aq.fw_min_ver,
 563                                                         &hw->aq.api_maj_ver,
 564                                                         &hw->aq.api_min_ver,
 565                                                         NULL);
 566                 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)
 567                         break;
 568                 retry++;
 569                 msleep(100);
 570                 i40e_resume_aq(hw);
 571         } while (retry < 10);
 572         if (ret_code != I40E_SUCCESS)
 573                 goto init_adminq_free_arq;
 574
 575         if (hw->aq.api_maj_ver != I40E_FW_API_VERSION_MAJOR ||
 576             hw->aq.api_min_ver != I40E_FW_API_VERSION_MINOR) {
 577                 ret_code = I40E_ERR_FIRMWARE_API_VERSION;
 578                 goto init_adminq_free_arq;
 579         }
 580         i40e_read_nvm_word(hw, I40E_SR_NVM_IMAGE_VERSION, &hw->nvm.version);
 581         i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
 582         i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
 583         hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
 584
 585         ret_code = i40e_aq_set_hmc_resource_profile(hw,
 586                                                     I40E_HMC_PROFILE_DEFAULT,
 587                                                     0,
 588                                                     NULL);
 589         ret_code = 0;
 590
 591         /* success! */
 592         goto init_adminq_exit;
 593
 594 init_adminq_free_arq:
 595         i40e_shutdown_arq(hw);
 596 init_adminq_free_asq:
 597         i40e_shutdown_asq(hw);
 598 init_adminq_destroy_locks:
 599
 600 init_adminq_exit:
 601         return ret_code;
 602 }
 603
 604 /**
 605  *  i40e_shutdown_adminq - shutdown routine for the Admin Queue
 606  *  @hw:     pointer to the hardware structure
 607  **/
 608 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw)
 609 {
 610         i40e_status ret_code = 0;
 611
 612         i40e_shutdown_asq(hw);
 613         i40e_shutdown_arq(hw);
 614
 615         /* destroy the locks */
 616
 617         return ret_code;
 618 }
 619
 620 /**
 621  *  i40e_clean_asq - cleans Admin send queue
 622  *  @asq: pointer to the adminq send ring
 623  *
 624  *  returns the number of free desc
 625  **/
 626 static u16 i40e_clean_asq(struct i40e_hw *hw)
 627 {
 628         struct i40e_adminq_ring *asq = &(hw->aq.asq);
 629         struct i40e_asq_cmd_details *details;
 630         u16 ntc = asq->next_to_clean;
 631         struct i40e_aq_desc desc_cb;
 632         struct i40e_aq_desc *desc;
 633
 634         desc = I40E_ADMINQ_DESC(*asq, ntc);
 635         details = I40E_ADMINQ_DETAILS(*asq, ntc);
 636         while (rd32(hw, hw->aq.asq.head) != ntc) {
 637                 if (details->callback) {
 638                         I40E_ADMINQ_CALLBACK cb_func =
 639                                         (I40E_ADMINQ_CALLBACK)details->callback;
 640                         desc_cb = *desc;
 641                         cb_func(hw, &desc_cb);
 642                 }
 643                 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
 644                 memset((void *)details, 0,
 645                        sizeof(struct i40e_asq_cmd_details));
 646                 ntc++;
 647                 if (ntc == asq->count)
 648                         ntc = 0;
 649                 desc = I40E_ADMINQ_DESC(*asq, ntc);
 650                 details = I40E_ADMINQ_DETAILS(*asq, ntc);
 651         }
 652
 653         asq->next_to_clean = ntc;
 654
 655         return I40E_DESC_UNUSED(asq);
 656 }
 657
 658 /**
 659  *  i40e_asq_done - check if FW has processed the Admin Send Queue
 660  *  @hw: pointer to the hw struct
 661  *
 662  *  Returns true if the firmware has processed all descriptors on the
 663  *  admin send queue. Returns false if there are still requests pending.
 664  **/
 665 static bool i40e_asq_done(struct i40e_hw *hw)
 666 {
 667         /* AQ designers suggest use of head for better
 668          * timing reliability than DD bit
 669          */
 670         return (rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use);
 671
 672 }
 673
 674 /**
 675  *  i40e_asq_send_command - send command to Admin Queue
 676  *  @hw: pointer to the hw struct
 677  *  @desc: prefilled descriptor describing the command (non DMA mem)
 678  *  @buff: buffer to use for indirect commands
 679  *  @buff_size: size of buffer for indirect commands
 680  *  @opaque: pointer to info to be used in async cleanup
 681  *
 682  *  This is the main send command driver routine for the Admin Queue send
 683  *  queue.  It runs the queue, cleans the queue, etc
 684  **/
 685 i40e_status i40e_asq_send_command(struct i40e_hw *hw,
 686                                 struct i40e_aq_desc *desc,
 687                                 void *buff, /* can be NULL */
 688                                 u16  buff_size,
 689                                 struct i40e_asq_cmd_details *cmd_details)
 690 {
 691         i40e_status status = 0;
 692         struct i40e_dma_mem *dma_buff = NULL;
 693         struct i40e_asq_cmd_details *details;
 694         struct i40e_aq_desc *desc_on_ring;
 695         bool cmd_completed = false;
 696         u16  retval = 0;
 697
 698         if (hw->aq.asq.count == 0) {
 699                 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
 700                            "AQTX: Admin queue not initialized.\n");
 701                 status = I40E_ERR_QUEUE_EMPTY;
 702                 goto asq_send_command_exit;
 703         }
 704
 705         details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
 706         if (cmd_details) {
 707                 *details = *cmd_details;
 708
 709                 /* If the cmd_details are defined copy the cookie.  The
 710                  * cpu_to_le32 is not needed here because the data is ignored
 711                  * by the FW, only used by the driver
 712                  */
 713                 if (details->cookie) {
 714                         desc->cookie_high =
 715                                 cpu_to_le32(upper_32_bits(details->cookie));
 716                         desc->cookie_low =
 717                                 cpu_to_le32(lower_32_bits(details->cookie));
 718                 }
 719         } else {
 720                 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
 721         }
 722
 723         /* clear requested flags and then set additional flags if defined */
 724         desc->flags &= ~cpu_to_le16(details->flags_dis);
 725         desc->flags |= cpu_to_le16(details->flags_ena);
 726
 727         mutex_lock(&hw->aq.asq_mutex);
 728
 729         if (buff_size > hw->aq.asq_buf_size) {
 730                 i40e_debug(hw,
 731                            I40E_DEBUG_AQ_MESSAGE,
 732                            "AQTX: Invalid buffer size: %d.\n",
 733                            buff_size);
 734                 status = I40E_ERR_INVALID_SIZE;
 735                 goto asq_send_command_error;
 736         }
 737
 738         if (details->postpone && !details->async) {
 739                 i40e_debug(hw,
 740                            I40E_DEBUG_AQ_MESSAGE,
 741                            "AQTX: Async flag not set along with postpone flag");
 742                 status = I40E_ERR_PARAM;
 743                 goto asq_send_command_error;
 744         }
 745
 746         /* call clean and check queue available function to reclaim the
 747          * descriptors that were processed by FW, the function returns the
 748          * number of desc available
 749          */
 750         /* the clean function called here could be called in a separate thread
 751          * in case of asynchronous completions
 752          */
 753         if (i40e_clean_asq(hw) == 0) {
 754                 i40e_debug(hw,
 755                            I40E_DEBUG_AQ_MESSAGE,
 756                            "AQTX: Error queue is full.\n");
 757                 status = I40E_ERR_ADMIN_QUEUE_FULL;
 758                 goto asq_send_command_error;
 759         }
 760
 761         /* initialize the temp desc pointer with the right desc */
 762         desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
 763
 764         /* if the desc is available copy the temp desc to the right place */
 765         *desc_on_ring = *desc;
 766
 767         /* if buff is not NULL assume indirect command */
 768         if (buff != NULL) {
 769                 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
 770                 /* copy the user buff into the respective DMA buff */
 771                 memcpy(dma_buff->va, buff, buff_size);
 772                 desc_on_ring->datalen = cpu_to_le16(buff_size);
 773
 774                 /* Update the address values in the desc with the pa value
 775                  * for respective buffer
 776                  */
 777                 desc_on_ring->params.external.addr_high =
 778                                 cpu_to_le32(upper_32_bits(dma_buff->pa));
 779                 desc_on_ring->params.external.addr_low =
 780                                 cpu_to_le32(lower_32_bits(dma_buff->pa));
 781         }
 782
 783         /* bump the tail */
 784         i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
 785         (hw->aq.asq.next_to_use)++;
 786         if (hw->aq.asq.next_to_use == hw->aq.asq.count)
 787                 hw->aq.asq.next_to_use = 0;
 788         if (!details->postpone)
 789                 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
 790
 791         /* if cmd_details are not defined or async flag is not set,
 792          * we need to wait for desc write back
 793          */
 794         if (!details->async && !details->postpone) {
 795                 u32 total_delay = 0;
 796                 u32 delay_len = 10;
 797
 798                 do {
 799                         /* AQ designers suggest use of head for better
 800                          * timing reliability than DD bit
 801                          */
 802                         if (i40e_asq_done(hw))
 803                                 break;
 804                         /* ugh! delay while spin_lock */
 805                         udelay(delay_len);
 806                         total_delay += delay_len;
 807                 } while (total_delay <  I40E_ASQ_CMD_TIMEOUT);
 808         }
 809
 810         /* if ready, copy the desc back to temp */
 811         if (i40e_asq_done(hw)) {
 812                 *desc = *desc_on_ring;
 813                 if (buff != NULL)
 814                         memcpy(buff, dma_buff->va, buff_size);
 815                 retval = le16_to_cpu(desc->retval);
 816                 if (retval != 0) {
 817                         i40e_debug(hw,
 818                                    I40E_DEBUG_AQ_MESSAGE,
 819                                    "AQTX: Command completed with error 0x%X.\n",
 820                                    retval);
 821                         /* strip off FW internal code */
 822                         retval &= 0xff;
 823                 }
 824                 cmd_completed = true;
 825                 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
 826                         status = 0;
 827                 else
 828                         status = I40E_ERR_ADMIN_QUEUE_ERROR;
 829                 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
 830         }
 831
 832         /* update the error if time out occurred */
 833         if ((!cmd_completed) &&
 834             (!details->async && !details->postpone)) {
 835                 i40e_debug(hw,
 836                            I40E_DEBUG_AQ_MESSAGE,
 837                            "AQTX: Writeback timeout.\n");
 838                 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
 839         }
 840
 841 asq_send_command_error:
 842         mutex_unlock(&hw->aq.asq_mutex);
 843 asq_send_command_exit:
 844         return status;
 845 }
 846
 847 /**
 848  *  i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
 849  *  @desc:     pointer to the temp descriptor (non DMA mem)
 850  *  @opcode:   the opcode can be used to decide which flags to turn off or on
 851  *
 852  *  Fill the desc with default values
 853  **/
 854 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
 855                                        u16 opcode)
 856 {
 857         /* zero out the desc */
 858         memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
 859         desc->opcode = cpu_to_le16(opcode);
 860         desc->flags = cpu_to_le16(I40E_AQ_FLAG_EI | I40E_AQ_FLAG_SI);
 861 }
 862
 863 /**
 864  *  i40e_clean_arq_element
 865  *  @hw: pointer to the hw struct
 866  *  @e: event info from the receive descriptor, includes any buffers
 867  *  @pending: number of events that could be left to process
 868  *
 869  *  This function cleans one Admin Receive Queue element and returns
 870  *  the contents through e.  It can also return how many events are
 871  *  left to process through 'pending'
 872  **/
 873 i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
 874                                              struct i40e_arq_event_info *e,
 875                                              u16 *pending)
 876 {
 877         i40e_status ret_code = 0;
 878         u16 ntc = hw->aq.arq.next_to_clean;
 879         struct i40e_aq_desc *desc;
 880         struct i40e_dma_mem *bi;
 881         u16 desc_idx;
 882         u16 datalen;
 883         u16 flags;
 884         u16 ntu;
 885
 886         /* take the lock before we start messing with the ring */
 887         mutex_lock(&hw->aq.arq_mutex);
 888
 889         /* set next_to_use to head */
 890         ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
 891         if (ntu == ntc) {
 892                 /* nothing to do - shouldn't need to update ring's values */
 893                 i40e_debug(hw,
 894                            I40E_DEBUG_AQ_MESSAGE,
 895                            "AQRX: Queue is empty.\n");
 896                 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
 897                 goto clean_arq_element_out;
 898         }
 899
 900         /* now clean the next descriptor */
 901         desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
 902         desc_idx = ntc;
 903         i40e_debug_aq(hw,
 904                       I40E_DEBUG_AQ_COMMAND,
 905                       (void *)desc,
 906                       hw->aq.arq.r.arq_bi[desc_idx].va);
 907
 908         flags = le16_to_cpu(desc->flags);
 909         if (flags & I40E_AQ_FLAG_ERR) {
 910                 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
 911                 hw->aq.arq_last_status =
 912                         (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
 913                 i40e_debug(hw,
 914                            I40E_DEBUG_AQ_MESSAGE,
 915                            "AQRX: Event received with error 0x%X.\n",
 916                            hw->aq.arq_last_status);
 917         } else {
 918                 memcpy(&e->desc, desc, sizeof(struct i40e_aq_desc));
 919                 datalen = le16_to_cpu(desc->datalen);
 920                 e->msg_size = min(datalen, e->msg_size);
 921                 if (e->msg_buf != NULL && (e->msg_size != 0))
 922                         memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
 923                                e->msg_size);
 924         }
 925
 926         /* Restore the original datalen and buffer address in the desc,
 927          * FW updates datalen to indicate the event message
 928          * size
 929          */
 930         bi = &hw->aq.arq.r.arq_bi[ntc];
 931         desc->datalen = cpu_to_le16((u16)bi->size);
 932         desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
 933         desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
 934
 935         /* set tail = the last cleaned desc index. */
 936         wr32(hw, hw->aq.arq.tail, ntc);
 937         /* ntc is updated to tail + 1 */
 938         ntc++;
 939         if (ntc == hw->aq.num_arq_entries)
 940                 ntc = 0;
 941         hw->aq.arq.next_to_clean = ntc;
 942         hw->aq.arq.next_to_use = ntu;
 943
 944 clean_arq_element_out:
 945         /* Set pending if needed, unlock and return */
 946         if (pending != NULL)
 947                 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
 948         mutex_unlock(&hw->aq.arq_mutex);
 949
 950         return ret_code;
 951 }
 952
 953 static void i40e_resume_aq(struct i40e_hw *hw)
 954 {
 955         u32 reg = 0;
 956
 957         /* Registers are reset after PF reset */
 958         hw->aq.asq.next_to_use = 0;
 959         hw->aq.asq.next_to_clean = 0;
 960
 961         i40e_config_asq_regs(hw);
 962         reg = hw->aq.num_asq_entries | I40E_PF_ATQLEN_ATQENABLE_MASK;
 963         wr32(hw, hw->aq.asq.len, reg);
 964
 965         hw->aq.arq.next_to_use = 0;
 966         hw->aq.arq.next_to_clean = 0;
 967
 968         i40e_config_arq_regs(hw);
 969         reg = hw->aq.num_arq_entries | I40E_PF_ATQLEN_ATQENABLE_MASK;
 970         wr32(hw, hw->aq.arq.len, reg);
 971 }