Pileus Git - ~andy/linux/blob - drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 82562G 10/100 Network Connection
  30  * 82562G-2 10/100 Network Connection
  31  * 82562GT 10/100 Network Connection
  32  * 82562GT-2 10/100 Network Connection
  33  * 82562V 10/100 Network Connection
  34  * 82562V-2 10/100 Network Connection
  35  * 82566DC-2 Gigabit Network Connection
  36  * 82566DC Gigabit Network Connection
  37  * 82566DM-2 Gigabit Network Connection
  38  * 82566DM Gigabit Network Connection
  39  * 82566MC Gigabit Network Connection
  40  * 82566MM Gigabit Network Connection
  41  * 82567LM Gigabit Network Connection
  42  * 82567LF Gigabit Network Connection
  43  * 82567V Gigabit Network Connection
  44  * 82567LM-2 Gigabit Network Connection
  45  * 82567LF-2 Gigabit Network Connection
  46  * 82567V-2 Gigabit Network Connection
  47  * 82567LF-3 Gigabit Network Connection
  48  * 82567LM-3 Gigabit Network Connection
  49  * 82567LM-4 Gigabit Network Connection
  50  * 82577LM Gigabit Network Connection
  51  * 82577LC Gigabit Network Connection
  52  * 82578DM Gigabit Network Connection
  53  * 82578DC Gigabit Network Connection
  54  * 82579LM Gigabit Network Connection
  55  * 82579V Gigabit Network Connection
  56  */
  57
  58 #include "e1000.h"
  59
  60 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  61 /* Offset 04h HSFSTS */
  62 union ich8_hws_flash_status {
  63         struct ich8_hsfsts {
  64                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  65                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  66                 u16 dael:1;     /* bit 2 Direct Access error Log */
  67                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  68                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  69                 u16 reserved1:2;        /* bit 13:6 Reserved */
  70                 u16 reserved2:6;        /* bit 13:6 Reserved */
  71                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  72                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  73         } hsf_status;
  74         u16 regval;
  75 };
  76
  77 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  78 /* Offset 06h FLCTL */
  79 union ich8_hws_flash_ctrl {
  80         struct ich8_hsflctl {
  81                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  82                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  83                 u16 reserved:5; /* 7:3 Reserved  */
  84                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  85                 u16 flockdn:6;  /* 15:10 Reserved */
  86         } hsf_ctrl;
  87         u16 regval;
  88 };
  89
  90 /* ICH Flash Region Access Permissions */
  91 union ich8_hws_flash_regacc {
  92         struct ich8_flracc {
  93                 u32 grra:8;     /* 0:7 GbE region Read Access */
  94                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  95                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  96                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  97         } hsf_flregacc;
  98         u16 regval;
  99 };
 100
 101 /* ICH Flash Protected Region */
 102 union ich8_flash_protected_range {
 103         struct ich8_pr {
 104                 u32 base:13;     /* 0:12 Protected Range Base */
 105                 u32 reserved1:2; /* 13:14 Reserved */
 106                 u32 rpe:1;       /* 15 Read Protection Enable */
 107                 u32 limit:13;    /* 16:28 Protected Range Limit */
 108                 u32 reserved2:2; /* 29:30 Reserved */
 109                 u32 wpe:1;       /* 31 Write Protection Enable */
 110         } range;
 111         u32 regval;
 112 };
 113
 114 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 115 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 116 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 117 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 118                                                 u32 offset, u8 byte);
 119 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 120                                          u8 *data);
 121 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 122                                          u16 *data);
 123 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 124                                          u8 size, u16 *data);
 125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 126 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 127 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 128 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 129 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 130 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 131 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 132 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 133 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 134 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 135 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 136 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 137 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 138 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 139 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 140 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 141 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 142 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 143 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 144 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 145
 146 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 147 {
 148         return readw(hw->flash_address + reg);
 149 }
 150
 151 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 152 {
 153         return readl(hw->flash_address + reg);
 154 }
 155
 156 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 157 {
 158         writew(val, hw->flash_address + reg);
 159 }
 160
 161 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 162 {
 163         writel(val, hw->flash_address + reg);
 164 }
 165
 166 #define er16flash(reg)          __er16flash(hw, (reg))
 167 #define er32flash(reg)          __er32flash(hw, (reg))
 168 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 169 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 170
 171 /**
 172  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 173  *  @hw: pointer to the HW structure
 174  *
 175  *  Test access to the PHY registers by reading the PHY ID registers.  If
 176  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 177  *  otherwise assume the read PHY ID is correct if it is valid.
 178  *
 179  *  Assumes the sw/fw/hw semaphore is already acquired.
 180  **/
 181 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 182 {
 183         u16 phy_reg = 0;
 184         u32 phy_id = 0;
 185         s32 ret_val;
 186         u16 retry_count;
 187
 188         for (retry_count = 0; retry_count < 2; retry_count++) {
 189                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 190                 if (ret_val || (phy_reg == 0xFFFF))
 191                         continue;
 192                 phy_id = (u32)(phy_reg << 16);
 193
 194                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 195                 if (ret_val || (phy_reg == 0xFFFF)) {
 196                         phy_id = 0;
 197                         continue;
 198                 }
 199                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 200                 break;
 201         }
 202
 203         if (hw->phy.id) {
 204                 if (hw->phy.id == phy_id)
 205                         return true;
 206         } else if (phy_id) {
 207                 hw->phy.id = phy_id;
 208                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 209                 return true;
 210         }
 211
 212         /* In case the PHY needs to be in mdio slow mode,
 213          * set slow mode and try to get the PHY id again.
 214          */
 215         hw->phy.ops.release(hw);
 216         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 217         if (!ret_val)
 218                 ret_val = e1000e_get_phy_id(hw);
 219         hw->phy.ops.acquire(hw);
 220
 221         return !ret_val;
 222 }
 223
 224 /**
 225  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 226  *  @hw: pointer to the HW structure
 227  *
 228  *  Workarounds/flow necessary for PHY initialization during driver load
 229  *  and resume paths.
 230  **/
 231 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 232 {
 233         u32 mac_reg, fwsm = er32(FWSM);
 234         s32 ret_val;
 235         u16 phy_reg;
 236
 237         /* Gate automatic PHY configuration by hardware on managed and
 238          * non-managed 82579 and newer adapters.
 239          */
 240         e1000_gate_hw_phy_config_ich8lan(hw, true);
 241
 242         ret_val = hw->phy.ops.acquire(hw);
 243         if (ret_val) {
 244                 e_dbg("Failed to initialize PHY flow\n");
 245                 goto out;
 246         }
 247
 248         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 249          * inaccessible and resetting the PHY is not blocked, toggle the
 250          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 251          */
 252         switch (hw->mac.type) {
 253         case e1000_pch_lpt:
 254                 if (e1000_phy_is_accessible_pchlan(hw))
 255                         break;
 256
 257                 /* Before toggling LANPHYPC, see if PHY is accessible by
 258                  * forcing MAC to SMBus mode first.
 259                  */
 260                 mac_reg = er32(CTRL_EXT);
 261                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 262                 ew32(CTRL_EXT, mac_reg);
 263
 264                 /* fall-through */
 265         case e1000_pch2lan:
 266                 if (e1000_phy_is_accessible_pchlan(hw)) {
 267                         if (hw->mac.type == e1000_pch_lpt) {
 268                                 /* Unforce SMBus mode in PHY */
 269                                 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 270                                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 271                                 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 272
 273                                 /* Unforce SMBus mode in MAC */
 274                                 mac_reg = er32(CTRL_EXT);
 275                                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 276                                 ew32(CTRL_EXT, mac_reg);
 277                         }
 278                         break;
 279                 }
 280
 281                 /* fall-through */
 282         case e1000_pchlan:
 283                 if ((hw->mac.type == e1000_pchlan) &&
 284                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 285                         break;
 286
 287                 if (hw->phy.ops.check_reset_block(hw)) {
 288                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 289                         break;
 290                 }
 291
 292                 e_dbg("Toggling LANPHYPC\n");
 293
 294                 /* Set Phy Config Counter to 50msec */
 295                 mac_reg = er32(FEXTNVM3);
 296                 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 297                 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 298                 ew32(FEXTNVM3, mac_reg);
 299
 300                 if (hw->mac.type == e1000_pch_lpt) {
 301                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 302                          * So ensure that the MAC is also out of SMBus mode
 303                          */
 304                         mac_reg = er32(CTRL_EXT);
 305                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 306                         ew32(CTRL_EXT, mac_reg);
 307                 }
 308
 309                 /* Toggle LANPHYPC Value bit */
 310                 mac_reg = er32(CTRL);
 311                 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 312                 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 313                 ew32(CTRL, mac_reg);
 314                 e1e_flush();
 315                 usleep_range(10, 20);
 316                 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 317                 ew32(CTRL, mac_reg);
 318                 e1e_flush();
 319                 if (hw->mac.type < e1000_pch_lpt) {
 320                         msleep(50);
 321                 } else {
 322                         u16 count = 20;
 323                         do {
 324                                 usleep_range(5000, 10000);
 325                         } while (!(er32(CTRL_EXT) &
 326                                    E1000_CTRL_EXT_LPCD) && count--);
 327                 }
 328                 break;
 329         default:
 330                 break;
 331         }
 332
 333         hw->phy.ops.release(hw);
 334
 335         /* Reset the PHY before any access to it.  Doing so, ensures
 336          * that the PHY is in a known good state before we read/write
 337          * PHY registers.  The generic reset is sufficient here,
 338          * because we haven't determined the PHY type yet.
 339          */
 340         ret_val = e1000e_phy_hw_reset_generic(hw);
 341
 342 out:
 343         /* Ungate automatic PHY configuration on non-managed 82579 */
 344         if ((hw->mac.type == e1000_pch2lan) &&
 345             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 346                 usleep_range(10000, 20000);
 347                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 348         }
 349
 350         return ret_val;
 351 }
 352
 353 /**
 354  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 355  *  @hw: pointer to the HW structure
 356  *
 357  *  Initialize family-specific PHY parameters and function pointers.
 358  **/
 359 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 360 {
 361         struct e1000_phy_info *phy = &hw->phy;
 362         s32 ret_val;
 363
 364         phy->addr                     = 1;
 365         phy->reset_delay_us           = 100;
 366
 367         phy->ops.set_page             = e1000_set_page_igp;
 368         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 369         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 370         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 371         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 372         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 373         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 374         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 375         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 376         phy->ops.power_up             = e1000_power_up_phy_copper;
 377         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 378         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 379
 380         phy->id = e1000_phy_unknown;
 381
 382         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 383         if (ret_val)
 384                 return ret_val;
 385
 386         if (phy->id == e1000_phy_unknown)
 387                 switch (hw->mac.type) {
 388                 default:
 389                         ret_val = e1000e_get_phy_id(hw);
 390                         if (ret_val)
 391                                 return ret_val;
 392                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 393                                 break;
 394                         /* fall-through */
 395                 case e1000_pch2lan:
 396                 case e1000_pch_lpt:
 397                         /* In case the PHY needs to be in mdio slow mode,
 398                          * set slow mode and try to get the PHY id again.
 399                          */
 400                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 401                         if (ret_val)
 402                                 return ret_val;
 403                         ret_val = e1000e_get_phy_id(hw);
 404                         if (ret_val)
 405                                 return ret_val;
 406                         break;
 407                 }
 408         phy->type = e1000e_get_phy_type_from_id(phy->id);
 409
 410         switch (phy->type) {
 411         case e1000_phy_82577:
 412         case e1000_phy_82579:
 413         case e1000_phy_i217:
 414                 phy->ops.check_polarity = e1000_check_polarity_82577;
 415                 phy->ops.force_speed_duplex =
 416                     e1000_phy_force_speed_duplex_82577;
 417                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 418                 phy->ops.get_info = e1000_get_phy_info_82577;
 419                 phy->ops.commit = e1000e_phy_sw_reset;
 420                 break;
 421         case e1000_phy_82578:
 422                 phy->ops.check_polarity = e1000_check_polarity_m88;
 423                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 424                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 425                 phy->ops.get_info = e1000e_get_phy_info_m88;
 426                 break;
 427         default:
 428                 ret_val = -E1000_ERR_PHY;
 429                 break;
 430         }
 431
 432         return ret_val;
 433 }
 434
 435 /**
 436  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 437  *  @hw: pointer to the HW structure
 438  *
 439  *  Initialize family-specific PHY parameters and function pointers.
 440  **/
 441 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 442 {
 443         struct e1000_phy_info *phy = &hw->phy;
 444         s32 ret_val;
 445         u16 i = 0;
 446
 447         phy->addr                       = 1;
 448         phy->reset_delay_us             = 100;
 449
 450         phy->ops.power_up               = e1000_power_up_phy_copper;
 451         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 452
 453         /* We may need to do this twice - once for IGP and if that fails,
 454          * we'll set BM func pointers and try again
 455          */
 456         ret_val = e1000e_determine_phy_address(hw);
 457         if (ret_val) {
 458                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 459                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 460                 ret_val = e1000e_determine_phy_address(hw);
 461                 if (ret_val) {
 462                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 463                         return ret_val;
 464                 }
 465         }
 466
 467         phy->id = 0;
 468         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 469                (i++ < 100)) {
 470                 usleep_range(1000, 2000);
 471                 ret_val = e1000e_get_phy_id(hw);
 472                 if (ret_val)
 473                         return ret_val;
 474         }
 475
 476         /* Verify phy id */
 477         switch (phy->id) {
 478         case IGP03E1000_E_PHY_ID:
 479                 phy->type = e1000_phy_igp_3;
 480                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 481                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 482                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 483                 phy->ops.get_info = e1000e_get_phy_info_igp;
 484                 phy->ops.check_polarity = e1000_check_polarity_igp;
 485                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 486                 break;
 487         case IFE_E_PHY_ID:
 488         case IFE_PLUS_E_PHY_ID:
 489         case IFE_C_E_PHY_ID:
 490                 phy->type = e1000_phy_ife;
 491                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 492                 phy->ops.get_info = e1000_get_phy_info_ife;
 493                 phy->ops.check_polarity = e1000_check_polarity_ife;
 494                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 495                 break;
 496         case BME1000_E_PHY_ID:
 497                 phy->type = e1000_phy_bm;
 498                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 499                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 500                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 501                 phy->ops.commit = e1000e_phy_sw_reset;
 502                 phy->ops.get_info = e1000e_get_phy_info_m88;
 503                 phy->ops.check_polarity = e1000_check_polarity_m88;
 504                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 505                 break;
 506         default:
 507                 return -E1000_ERR_PHY;
 508                 break;
 509         }
 510
 511         return 0;
 512 }
 513
 514 /**
 515  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 516  *  @hw: pointer to the HW structure
 517  *
 518  *  Initialize family-specific NVM parameters and function
 519  *  pointers.
 520  **/
 521 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 522 {
 523         struct e1000_nvm_info *nvm = &hw->nvm;
 524         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 525         u32 gfpreg, sector_base_addr, sector_end_addr;
 526         u16 i;
 527
 528         /* Can't read flash registers if the register set isn't mapped. */
 529         if (!hw->flash_address) {
 530                 e_dbg("ERROR: Flash registers not mapped\n");
 531                 return -E1000_ERR_CONFIG;
 532         }
 533
 534         nvm->type = e1000_nvm_flash_sw;
 535
 536         gfpreg = er32flash(ICH_FLASH_GFPREG);
 537
 538         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 539          * Add 1 to sector_end_addr since this sector is included in
 540          * the overall size.
 541          */
 542         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 543         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 544
 545         /* flash_base_addr is byte-aligned */
 546         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 547
 548         /* find total size of the NVM, then cut in half since the total
 549          * size represents two separate NVM banks.
 550          */
 551         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 552                                 << FLASH_SECTOR_ADDR_SHIFT);
 553         nvm->flash_bank_size /= 2;
 554         /* Adjust to word count */
 555         nvm->flash_bank_size /= sizeof(u16);
 556
 557         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 558
 559         /* Clear shadow ram */
 560         for (i = 0; i < nvm->word_size; i++) {
 561                 dev_spec->shadow_ram[i].modified = false;
 562                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 563         }
 564
 565         return 0;
 566 }
 567
 568 /**
 569  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 570  *  @hw: pointer to the HW structure
 571  *
 572  *  Initialize family-specific MAC parameters and function
 573  *  pointers.
 574  **/
 575 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 576 {
 577         struct e1000_mac_info *mac = &hw->mac;
 578
 579         /* Set media type function pointer */
 580         hw->phy.media_type = e1000_media_type_copper;
 581
 582         /* Set mta register count */
 583         mac->mta_reg_count = 32;
 584         /* Set rar entry count */
 585         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 586         if (mac->type == e1000_ich8lan)
 587                 mac->rar_entry_count--;
 588         /* FWSM register */
 589         mac->has_fwsm = true;
 590         /* ARC subsystem not supported */
 591         mac->arc_subsystem_valid = false;
 592         /* Adaptive IFS supported */
 593         mac->adaptive_ifs = true;
 594
 595         /* LED and other operations */
 596         switch (mac->type) {
 597         case e1000_ich8lan:
 598         case e1000_ich9lan:
 599         case e1000_ich10lan:
 600                 /* check management mode */
 601                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 602                 /* ID LED init */
 603                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 604                 /* blink LED */
 605                 mac->ops.blink_led = e1000e_blink_led_generic;
 606                 /* setup LED */
 607                 mac->ops.setup_led = e1000e_setup_led_generic;
 608                 /* cleanup LED */
 609                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 610                 /* turn on/off LED */
 611                 mac->ops.led_on = e1000_led_on_ich8lan;
 612                 mac->ops.led_off = e1000_led_off_ich8lan;
 613                 break;
 614         case e1000_pch2lan:
 615                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 616                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 617                 /* fall-through */
 618         case e1000_pch_lpt:
 619         case e1000_pchlan:
 620                 /* check management mode */
 621                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 622                 /* ID LED init */
 623                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 624                 /* setup LED */
 625                 mac->ops.setup_led = e1000_setup_led_pchlan;
 626                 /* cleanup LED */
 627                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 628                 /* turn on/off LED */
 629                 mac->ops.led_on = e1000_led_on_pchlan;
 630                 mac->ops.led_off = e1000_led_off_pchlan;
 631                 break;
 632         default:
 633                 break;
 634         }
 635
 636         if (mac->type == e1000_pch_lpt) {
 637                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 638                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 639         }
 640
 641         /* Enable PCS Lock-loss workaround for ICH8 */
 642         if (mac->type == e1000_ich8lan)
 643                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 644
 645         return 0;
 646 }
 647
 648 /**
 649  *  __e1000_access_emi_reg_locked - Read/write EMI register
 650  *  @hw: pointer to the HW structure
 651  *  @addr: EMI address to program
 652  *  @data: pointer to value to read/write from/to the EMI address
 653  *  @read: boolean flag to indicate read or write
 654  *
 655  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 656  **/
 657 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 658                                          u16 *data, bool read)
 659 {
 660         s32 ret_val;
 661
 662         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 663         if (ret_val)
 664                 return ret_val;
 665
 666         if (read)
 667                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 668         else
 669                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 670
 671         return ret_val;
 672 }
 673
 674 /**
 675  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 676  *  @hw: pointer to the HW structure
 677  *  @addr: EMI address to program
 678  *  @data: value to be read from the EMI address
 679  *
 680  *  Assumes the SW/FW/HW Semaphore is already acquired.
 681  **/
 682 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 683 {
 684         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 685 }
 686
 687 /**
 688  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 689  *  @hw: pointer to the HW structure
 690  *  @addr: EMI address to program
 691  *  @data: value to be written to the EMI address
 692  *
 693  *  Assumes the SW/FW/HW Semaphore is already acquired.
 694  **/
 695 static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 696 {
 697         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 698 }
 699
 700 /**
 701  *  e1000_set_eee_pchlan - Enable/disable EEE support
 702  *  @hw: pointer to the HW structure
 703  *
 704  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 705  *  the link and the EEE capabilities of the link partner.  The LPI Control
 706  *  register bits will remain set only if/when link is up.
 707  **/
 708 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 709 {
 710         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 711         s32 ret_val;
 712         u16 lpi_ctrl;
 713
 714         if ((hw->phy.type != e1000_phy_82579) &&
 715             (hw->phy.type != e1000_phy_i217))
 716                 return 0;
 717
 718         ret_val = hw->phy.ops.acquire(hw);
 719         if (ret_val)
 720                 return ret_val;
 721
 722         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 723         if (ret_val)
 724                 goto release;
 725
 726         /* Clear bits that enable EEE in various speeds */
 727         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 728
 729         /* Enable EEE if not disabled by user */
 730         if (!dev_spec->eee_disable) {
 731                 u16 lpa, pcs_status, data;
 732
 733                 /* Save off link partner's EEE ability */
 734                 switch (hw->phy.type) {
 735                 case e1000_phy_82579:
 736                         lpa = I82579_EEE_LP_ABILITY;
 737                         pcs_status = I82579_EEE_PCS_STATUS;
 738                         break;
 739                 case e1000_phy_i217:
 740                         lpa = I217_EEE_LP_ABILITY;
 741                         pcs_status = I217_EEE_PCS_STATUS;
 742                         break;
 743                 default:
 744                         ret_val = -E1000_ERR_PHY;
 745                         goto release;
 746                 }
 747                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 748                                                     &dev_spec->eee_lp_ability);
 749                 if (ret_val)
 750                         goto release;
 751
 752                 /* Enable EEE only for speeds in which the link partner is
 753                  * EEE capable.
 754                  */
 755                 if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 756                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 757
 758                 if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 759                         e1e_rphy_locked(hw, MII_LPA, &data);
 760                         if (data & LPA_100FULL)
 761                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 762                         else
 763                                 /* EEE is not supported in 100Half, so ignore
 764                                  * partner's EEE in 100 ability if full-duplex
 765                                  * is not advertised.
 766                                  */
 767                                 dev_spec->eee_lp_ability &=
 768                                     ~I82579_EEE_100_SUPPORTED;
 769                 }
 770
 771                 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 772                 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 773                 if (ret_val)
 774                         goto release;
 775         }
 776
 777         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 778 release:
 779         hw->phy.ops.release(hw);
 780
 781         return ret_val;
 782 }
 783
 784 /**
 785  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 786  *  @hw:   pointer to the HW structure
 787  *  @link: link up bool flag
 788  *
 789  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 790  *  preventing further DMA write requests.  Workaround the issue by disabling
 791  *  the de-assertion of the clock request when in 1Gpbs mode.
 792  **/
 793 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 794 {
 795         u32 fextnvm6 = er32(FEXTNVM6);
 796         s32 ret_val = 0;
 797
 798         if (link && (er32(STATUS) & E1000_STATUS_SPEED_1000)) {
 799                 u16 kmrn_reg;
 800
 801                 ret_val = hw->phy.ops.acquire(hw);
 802                 if (ret_val)
 803                         return ret_val;
 804
 805                 ret_val =
 806                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 807                                                 &kmrn_reg);
 808                 if (ret_val)
 809                         goto release;
 810
 811                 ret_val =
 812                     e1000e_write_kmrn_reg_locked(hw,
 813                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 814                                                  kmrn_reg &
 815                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 816                 if (ret_val)
 817                         goto release;
 818
 819                 usleep_range(10, 20);
 820
 821                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 822
 823                 ret_val =
 824                     e1000e_write_kmrn_reg_locked(hw,
 825                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 826                                                  kmrn_reg);
 827 release:
 828                 hw->phy.ops.release(hw);
 829         } else {
 830                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 831                 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
 832         }
 833
 834         return ret_val;
 835 }
 836
 837 /**
 838  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 839  *  @hw: pointer to the HW structure
 840  *
 841  *  Checks to see of the link status of the hardware has changed.  If a
 842  *  change in link status has been detected, then we read the PHY registers
 843  *  to get the current speed/duplex if link exists.
 844  **/
 845 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 846 {
 847         struct e1000_mac_info *mac = &hw->mac;
 848         s32 ret_val;
 849         bool link;
 850         u16 phy_reg;
 851
 852         /* We only want to go out to the PHY registers to see if Auto-Neg
 853          * has completed and/or if our link status has changed.  The
 854          * get_link_status flag is set upon receiving a Link Status
 855          * Change or Rx Sequence Error interrupt.
 856          */
 857         if (!mac->get_link_status)
 858                 return 0;
 859
 860         /* First we want to see if the MII Status Register reports
 861          * link.  If so, then we want to get the current speed/duplex
 862          * of the PHY.
 863          */
 864         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 865         if (ret_val)
 866                 return ret_val;
 867
 868         if (hw->mac.type == e1000_pchlan) {
 869                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 870                 if (ret_val)
 871                         return ret_val;
 872         }
 873
 874         /* Work-around I218 hang issue */
 875         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
 876             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
 877                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
 878                 if (ret_val)
 879                         return ret_val;
 880         }
 881
 882         /* Clear link partner's EEE ability */
 883         hw->dev_spec.ich8lan.eee_lp_ability = 0;
 884
 885         if (!link)
 886                 return 0; /* No link detected */
 887
 888         mac->get_link_status = false;
 889
 890         switch (hw->mac.type) {
 891         case e1000_pch2lan:
 892                 ret_val = e1000_k1_workaround_lv(hw);
 893                 if (ret_val)
 894                         return ret_val;
 895                 /* fall-thru */
 896         case e1000_pchlan:
 897                 if (hw->phy.type == e1000_phy_82578) {
 898                         ret_val = e1000_link_stall_workaround_hv(hw);
 899                         if (ret_val)
 900                                 return ret_val;
 901                 }
 902
 903                 /* Workaround for PCHx parts in half-duplex:
 904                  * Set the number of preambles removed from the packet
 905                  * when it is passed from the PHY to the MAC to prevent
 906                  * the MAC from misinterpreting the packet type.
 907                  */
 908                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 909                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 910
 911                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
 912                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 913
 914                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 915                 break;
 916         default:
 917                 break;
 918         }
 919
 920         /* Check if there was DownShift, must be checked
 921          * immediately after link-up
 922          */
 923         e1000e_check_downshift(hw);
 924
 925         /* Enable/Disable EEE after link up */
 926         ret_val = e1000_set_eee_pchlan(hw);
 927         if (ret_val)
 928                 return ret_val;
 929
 930         /* If we are forcing speed/duplex, then we simply return since
 931          * we have already determined whether we have link or not.
 932          */
 933         if (!mac->autoneg)
 934                 return -E1000_ERR_CONFIG;
 935
 936         /* Auto-Neg is enabled.  Auto Speed Detection takes care
 937          * of MAC speed/duplex configuration.  So we only need to
 938          * configure Collision Distance in the MAC.
 939          */
 940         mac->ops.config_collision_dist(hw);
 941
 942         /* Configure Flow Control now that Auto-Neg has completed.
 943          * First, we need to restore the desired flow control
 944          * settings because we may have had to re-autoneg with a
 945          * different link partner.
 946          */
 947         ret_val = e1000e_config_fc_after_link_up(hw);
 948         if (ret_val)
 949                 e_dbg("Error configuring flow control\n");
 950
 951         return ret_val;
 952 }
 953
 954 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 955 {
 956         struct e1000_hw *hw = &adapter->hw;
 957         s32 rc;
 958
 959         rc = e1000_init_mac_params_ich8lan(hw);
 960         if (rc)
 961                 return rc;
 962
 963         rc = e1000_init_nvm_params_ich8lan(hw);
 964         if (rc)
 965                 return rc;
 966
 967         switch (hw->mac.type) {
 968         case e1000_ich8lan:
 969         case e1000_ich9lan:
 970         case e1000_ich10lan:
 971                 rc = e1000_init_phy_params_ich8lan(hw);
 972                 break;
 973         case e1000_pchlan:
 974         case e1000_pch2lan:
 975         case e1000_pch_lpt:
 976                 rc = e1000_init_phy_params_pchlan(hw);
 977                 break;
 978         default:
 979                 break;
 980         }
 981         if (rc)
 982                 return rc;
 983
 984         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 985          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 986          */
 987         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 988             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 989              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 990                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 991                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 992
 993                 hw->mac.ops.blink_led = NULL;
 994         }
 995
 996         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 997             (adapter->hw.phy.type != e1000_phy_ife))
 998                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 999
1000         /* Enable workaround for 82579 w/ ME enabled */
1001         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1002             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1003                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1004
1005         /* Disable EEE by default until IEEE802.3az spec is finalized */
1006         if (adapter->flags2 & FLAG2_HAS_EEE)
1007                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
1008
1009         return 0;
1010 }
1011
1012 static DEFINE_MUTEX(nvm_mutex);
1013
1014 /**
1015  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1016  *  @hw: pointer to the HW structure
1017  *
1018  *  Acquires the mutex for performing NVM operations.
1019  **/
1020 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1021 {
1022         mutex_lock(&nvm_mutex);
1023
1024         return 0;
1025 }
1026
1027 /**
1028  *  e1000_release_nvm_ich8lan - Release NVM mutex
1029  *  @hw: pointer to the HW structure
1030  *
1031  *  Releases the mutex used while performing NVM operations.
1032  **/
1033 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1034 {
1035         mutex_unlock(&nvm_mutex);
1036 }
1037
1038 /**
1039  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1040  *  @hw: pointer to the HW structure
1041  *
1042  *  Acquires the software control flag for performing PHY and select
1043  *  MAC CSR accesses.
1044  **/
1045 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1046 {
1047         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1048         s32 ret_val = 0;
1049
1050         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1051                              &hw->adapter->state)) {
1052                 e_dbg("contention for Phy access\n");
1053                 return -E1000_ERR_PHY;
1054         }
1055
1056         while (timeout) {
1057                 extcnf_ctrl = er32(EXTCNF_CTRL);
1058                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1059                         break;
1060
1061                 mdelay(1);
1062                 timeout--;
1063         }
1064
1065         if (!timeout) {
1066                 e_dbg("SW has already locked the resource.\n");
1067                 ret_val = -E1000_ERR_CONFIG;
1068                 goto out;
1069         }
1070
1071         timeout = SW_FLAG_TIMEOUT;
1072
1073         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1074         ew32(EXTCNF_CTRL, extcnf_ctrl);
1075
1076         while (timeout) {
1077                 extcnf_ctrl = er32(EXTCNF_CTRL);
1078                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1079                         break;
1080
1081                 mdelay(1);
1082                 timeout--;
1083         }
1084
1085         if (!timeout) {
1086                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1087                       er32(FWSM), extcnf_ctrl);
1088                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1089                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1090                 ret_val = -E1000_ERR_CONFIG;
1091                 goto out;
1092         }
1093
1094 out:
1095         if (ret_val)
1096                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1097
1098         return ret_val;
1099 }
1100
1101 /**
1102  *  e1000_release_swflag_ich8lan - Release software control flag
1103  *  @hw: pointer to the HW structure
1104  *
1105  *  Releases the software control flag for performing PHY and select
1106  *  MAC CSR accesses.
1107  **/
1108 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1109 {
1110         u32 extcnf_ctrl;
1111
1112         extcnf_ctrl = er32(EXTCNF_CTRL);
1113
1114         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1115                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1116                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1117         } else {
1118                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1119         }
1120
1121         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1122 }
1123
1124 /**
1125  *  e1000_check_mng_mode_ich8lan - Checks management mode
1126  *  @hw: pointer to the HW structure
1127  *
1128  *  This checks if the adapter has any manageability enabled.
1129  *  This is a function pointer entry point only called by read/write
1130  *  routines for the PHY and NVM parts.
1131  **/
1132 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1133 {
1134         u32 fwsm;
1135
1136         fwsm = er32(FWSM);
1137         return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1138                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1139                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
1140 }
1141
1142 /**
1143  *  e1000_check_mng_mode_pchlan - Checks management mode
1144  *  @hw: pointer to the HW structure
1145  *
1146  *  This checks if the adapter has iAMT enabled.
1147  *  This is a function pointer entry point only called by read/write
1148  *  routines for the PHY and NVM parts.
1149  **/
1150 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1151 {
1152         u32 fwsm;
1153
1154         fwsm = er32(FWSM);
1155         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1156             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1157 }
1158
1159 /**
1160  *  e1000_rar_set_pch2lan - Set receive address register
1161  *  @hw: pointer to the HW structure
1162  *  @addr: pointer to the receive address
1163  *  @index: receive address array register
1164  *
1165  *  Sets the receive address array register at index to the address passed
1166  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1167  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1168  *  Use SHRA[0-3] in place of those reserved for ME.
1169  **/
1170 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1171 {
1172         u32 rar_low, rar_high;
1173
1174         /* HW expects these in little endian so we reverse the byte order
1175          * from network order (big endian) to little endian
1176          */
1177         rar_low = ((u32)addr[0] |
1178                    ((u32)addr[1] << 8) |
1179                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1180
1181         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1182
1183         /* If MAC address zero, no need to set the AV bit */
1184         if (rar_low || rar_high)
1185                 rar_high |= E1000_RAH_AV;
1186
1187         if (index == 0) {
1188                 ew32(RAL(index), rar_low);
1189                 e1e_flush();
1190                 ew32(RAH(index), rar_high);
1191                 e1e_flush();
1192                 return;
1193         }
1194
1195         if (index < hw->mac.rar_entry_count) {
1196                 s32 ret_val;
1197
1198                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1199                 if (ret_val)
1200                         goto out;
1201
1202                 ew32(SHRAL(index - 1), rar_low);
1203                 e1e_flush();
1204                 ew32(SHRAH(index - 1), rar_high);
1205                 e1e_flush();
1206
1207                 e1000_release_swflag_ich8lan(hw);
1208
1209                 /* verify the register updates */
1210                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1211                     (er32(SHRAH(index - 1)) == rar_high))
1212                         return;
1213
1214                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1215                       (index - 1), er32(FWSM));
1216         }
1217
1218 out:
1219         e_dbg("Failed to write receive address at index %d\n", index);
1220 }
1221
1222 /**
1223  *  e1000_rar_set_pch_lpt - Set receive address registers
1224  *  @hw: pointer to the HW structure
1225  *  @addr: pointer to the receive address
1226  *  @index: receive address array register
1227  *
1228  *  Sets the receive address register array at index to the address passed
1229  *  in by addr. For LPT, RAR[0] is the base address register that is to
1230  *  contain the MAC address. SHRA[0-10] are the shared receive address
1231  *  registers that are shared between the Host and manageability engine (ME).
1232  **/
1233 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1234 {
1235         u32 rar_low, rar_high;
1236         u32 wlock_mac;
1237
1238         /* HW expects these in little endian so we reverse the byte order
1239          * from network order (big endian) to little endian
1240          */
1241         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1242                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1243
1244         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1245
1246         /* If MAC address zero, no need to set the AV bit */
1247         if (rar_low || rar_high)
1248                 rar_high |= E1000_RAH_AV;
1249
1250         if (index == 0) {
1251                 ew32(RAL(index), rar_low);
1252                 e1e_flush();
1253                 ew32(RAH(index), rar_high);
1254                 e1e_flush();
1255                 return;
1256         }
1257
1258         /* The manageability engine (ME) can lock certain SHRAR registers that
1259          * it is using - those registers are unavailable for use.
1260          */
1261         if (index < hw->mac.rar_entry_count) {
1262                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1263                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1264
1265                 /* Check if all SHRAR registers are locked */
1266                 if (wlock_mac == 1)
1267                         goto out;
1268
1269                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1270                         s32 ret_val;
1271
1272                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1273
1274                         if (ret_val)
1275                                 goto out;
1276
1277                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1278                         e1e_flush();
1279                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1280                         e1e_flush();
1281
1282                         e1000_release_swflag_ich8lan(hw);
1283
1284                         /* verify the register updates */
1285                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1286                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1287                                 return;
1288                 }
1289         }
1290
1291 out:
1292         e_dbg("Failed to write receive address at index %d\n", index);
1293 }
1294
1295 /**
1296  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1297  *  @hw: pointer to the HW structure
1298  *
1299  *  Checks if firmware is blocking the reset of the PHY.
1300  *  This is a function pointer entry point only called by
1301  *  reset routines.
1302  **/
1303 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1304 {
1305         u32 fwsm;
1306
1307         fwsm = er32(FWSM);
1308
1309         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1310 }
1311
1312 /**
1313  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1314  *  @hw: pointer to the HW structure
1315  *
1316  *  Assumes semaphore already acquired.
1317  *
1318  **/
1319 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1320 {
1321         u16 phy_data;
1322         u32 strap = er32(STRAP);
1323         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1324             E1000_STRAP_SMT_FREQ_SHIFT;
1325         s32 ret_val;
1326
1327         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1328
1329         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1330         if (ret_val)
1331                 return ret_val;
1332
1333         phy_data &= ~HV_SMB_ADDR_MASK;
1334         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1335         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1336
1337         if (hw->phy.type == e1000_phy_i217) {
1338                 /* Restore SMBus frequency */
1339                 if (freq--) {
1340                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1341                         phy_data |= (freq & (1 << 0)) <<
1342                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
1343                         phy_data |= (freq & (1 << 1)) <<
1344                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1345                 } else {
1346                         e_dbg("Unsupported SMB frequency in PHY\n");
1347                 }
1348         }
1349
1350         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1351 }
1352
1353 /**
1354  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1355  *  @hw:   pointer to the HW structure
1356  *
1357  *  SW should configure the LCD from the NVM extended configuration region
1358  *  as a workaround for certain parts.
1359  **/
1360 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1361 {
1362         struct e1000_phy_info *phy = &hw->phy;
1363         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1364         s32 ret_val = 0;
1365         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1366
1367         /* Initialize the PHY from the NVM on ICH platforms.  This
1368          * is needed due to an issue where the NVM configuration is
1369          * not properly autoloaded after power transitions.
1370          * Therefore, after each PHY reset, we will load the
1371          * configuration data out of the NVM manually.
1372          */
1373         switch (hw->mac.type) {
1374         case e1000_ich8lan:
1375                 if (phy->type != e1000_phy_igp_3)
1376                         return ret_val;
1377
1378                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1379                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1380                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1381                         break;
1382                 }
1383                 /* Fall-thru */
1384         case e1000_pchlan:
1385         case e1000_pch2lan:
1386         case e1000_pch_lpt:
1387                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1388                 break;
1389         default:
1390                 return ret_val;
1391         }
1392
1393         ret_val = hw->phy.ops.acquire(hw);
1394         if (ret_val)
1395                 return ret_val;
1396
1397         data = er32(FEXTNVM);
1398         if (!(data & sw_cfg_mask))
1399                 goto release;
1400
1401         /* Make sure HW does not configure LCD from PHY
1402          * extended configuration before SW configuration
1403          */
1404         data = er32(EXTCNF_CTRL);
1405         if ((hw->mac.type < e1000_pch2lan) &&
1406             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1407                 goto release;
1408
1409         cnf_size = er32(EXTCNF_SIZE);
1410         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1411         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1412         if (!cnf_size)
1413                 goto release;
1414
1415         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1416         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1417
1418         if (((hw->mac.type == e1000_pchlan) &&
1419              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1420             (hw->mac.type > e1000_pchlan)) {
1421                 /* HW configures the SMBus address and LEDs when the
1422                  * OEM and LCD Write Enable bits are set in the NVM.
1423                  * When both NVM bits are cleared, SW will configure
1424                  * them instead.
1425                  */
1426                 ret_val = e1000_write_smbus_addr(hw);
1427                 if (ret_val)
1428                         goto release;
1429
1430                 data = er32(LEDCTL);
1431                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1432                                                         (u16)data);
1433                 if (ret_val)
1434                         goto release;
1435         }
1436
1437         /* Configure LCD from extended configuration region. */
1438
1439         /* cnf_base_addr is in DWORD */
1440         word_addr = (u16)(cnf_base_addr << 1);
1441
1442         for (i = 0; i < cnf_size; i++) {
1443                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
1444                 if (ret_val)
1445                         goto release;
1446
1447                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1448                                          1, &reg_addr);
1449                 if (ret_val)
1450                         goto release;
1451
1452                 /* Save off the PHY page for future writes. */
1453                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1454                         phy_page = reg_data;
1455                         continue;
1456                 }
1457
1458                 reg_addr &= PHY_REG_MASK;
1459                 reg_addr |= phy_page;
1460
1461                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1462                 if (ret_val)
1463                         goto release;
1464         }
1465
1466 release:
1467         hw->phy.ops.release(hw);
1468         return ret_val;
1469 }
1470
1471 /**
1472  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1473  *  @hw:   pointer to the HW structure
1474  *  @link: link up bool flag
1475  *
1476  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1477  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1478  *  If link is down, the function will restore the default K1 setting located
1479  *  in the NVM.
1480  **/
1481 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1482 {
1483         s32 ret_val = 0;
1484         u16 status_reg = 0;
1485         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1486
1487         if (hw->mac.type != e1000_pchlan)
1488                 return 0;
1489
1490         /* Wrap the whole flow with the sw flag */
1491         ret_val = hw->phy.ops.acquire(hw);
1492         if (ret_val)
1493                 return ret_val;
1494
1495         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1496         if (link) {
1497                 if (hw->phy.type == e1000_phy_82578) {
1498                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1499                                                   &status_reg);
1500                         if (ret_val)
1501                                 goto release;
1502
1503                         status_reg &= (BM_CS_STATUS_LINK_UP |
1504                                        BM_CS_STATUS_RESOLVED |
1505                                        BM_CS_STATUS_SPEED_MASK);
1506
1507                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1508                                            BM_CS_STATUS_RESOLVED |
1509                                            BM_CS_STATUS_SPEED_1000))
1510                                 k1_enable = false;
1511                 }
1512
1513                 if (hw->phy.type == e1000_phy_82577) {
1514                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1515                         if (ret_val)
1516                                 goto release;
1517
1518                         status_reg &= (HV_M_STATUS_LINK_UP |
1519                                        HV_M_STATUS_AUTONEG_COMPLETE |
1520                                        HV_M_STATUS_SPEED_MASK);
1521
1522                         if (status_reg == (HV_M_STATUS_LINK_UP |
1523                                            HV_M_STATUS_AUTONEG_COMPLETE |
1524                                            HV_M_STATUS_SPEED_1000))
1525                                 k1_enable = false;
1526                 }
1527
1528                 /* Link stall fix for link up */
1529                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1530                 if (ret_val)
1531                         goto release;
1532
1533         } else {
1534                 /* Link stall fix for link down */
1535                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1536                 if (ret_val)
1537                         goto release;
1538         }
1539
1540         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1541
1542 release:
1543         hw->phy.ops.release(hw);
1544
1545         return ret_val;
1546 }
1547
1548 /**
1549  *  e1000_configure_k1_ich8lan - Configure K1 power state
1550  *  @hw: pointer to the HW structure
1551  *  @enable: K1 state to configure
1552  *
1553  *  Configure the K1 power state based on the provided parameter.
1554  *  Assumes semaphore already acquired.
1555  *
1556  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1557  **/
1558 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1559 {
1560         s32 ret_val;
1561         u32 ctrl_reg = 0;
1562         u32 ctrl_ext = 0;
1563         u32 reg = 0;
1564         u16 kmrn_reg = 0;
1565
1566         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1567                                               &kmrn_reg);
1568         if (ret_val)
1569                 return ret_val;
1570
1571         if (k1_enable)
1572                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1573         else
1574                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1575
1576         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1577                                                kmrn_reg);
1578         if (ret_val)
1579                 return ret_val;
1580
1581         usleep_range(20, 40);
1582         ctrl_ext = er32(CTRL_EXT);
1583         ctrl_reg = er32(CTRL);
1584
1585         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1586         reg |= E1000_CTRL_FRCSPD;
1587         ew32(CTRL, reg);
1588
1589         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1590         e1e_flush();
1591         usleep_range(20, 40);
1592         ew32(CTRL, ctrl_reg);
1593         ew32(CTRL_EXT, ctrl_ext);
1594         e1e_flush();
1595         usleep_range(20, 40);
1596
1597         return 0;
1598 }
1599
1600 /**
1601  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1602  *  @hw:       pointer to the HW structure
1603  *  @d0_state: boolean if entering d0 or d3 device state
1604  *
1605  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1606  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1607  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1608  **/
1609 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1610 {
1611         s32 ret_val = 0;
1612         u32 mac_reg;
1613         u16 oem_reg;
1614
1615         if (hw->mac.type < e1000_pchlan)
1616                 return ret_val;
1617
1618         ret_val = hw->phy.ops.acquire(hw);
1619         if (ret_val)
1620                 return ret_val;
1621
1622         if (hw->mac.type == e1000_pchlan) {
1623                 mac_reg = er32(EXTCNF_CTRL);
1624                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1625                         goto release;
1626         }
1627
1628         mac_reg = er32(FEXTNVM);
1629         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1630                 goto release;
1631
1632         mac_reg = er32(PHY_CTRL);
1633
1634         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
1635         if (ret_val)
1636                 goto release;
1637
1638         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1639
1640         if (d0_state) {
1641                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1642                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1643
1644                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1645                         oem_reg |= HV_OEM_BITS_LPLU;
1646         } else {
1647                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1648                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1649                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1650
1651                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1652                                E1000_PHY_CTRL_NOND0A_LPLU))
1653                         oem_reg |= HV_OEM_BITS_LPLU;
1654         }
1655
1656         /* Set Restart auto-neg to activate the bits */
1657         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1658             !hw->phy.ops.check_reset_block(hw))
1659                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1660
1661         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
1662
1663 release:
1664         hw->phy.ops.release(hw);
1665
1666         return ret_val;
1667 }
1668
1669 /**
1670  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1671  *  @hw:   pointer to the HW structure
1672  **/
1673 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1674 {
1675         s32 ret_val;
1676         u16 data;
1677
1678         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1679         if (ret_val)
1680                 return ret_val;
1681
1682         data |= HV_KMRN_MDIO_SLOW;
1683
1684         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1685
1686         return ret_val;
1687 }
1688
1689 /**
1690  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1691  *  done after every PHY reset.
1692  **/
1693 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1694 {
1695         s32 ret_val = 0;
1696         u16 phy_data;
1697
1698         if (hw->mac.type != e1000_pchlan)
1699                 return 0;
1700
1701         /* Set MDIO slow mode before any other MDIO access */
1702         if (hw->phy.type == e1000_phy_82577) {
1703                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1704                 if (ret_val)
1705                         return ret_val;
1706         }
1707
1708         if (((hw->phy.type == e1000_phy_82577) &&
1709              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1710             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1711                 /* Disable generation of early preamble */
1712                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1713                 if (ret_val)
1714                         return ret_val;
1715
1716                 /* Preamble tuning for SSC */
1717                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1718                 if (ret_val)
1719                         return ret_val;
1720         }
1721
1722         if (hw->phy.type == e1000_phy_82578) {
1723                 /* Return registers to default by doing a soft reset then
1724                  * writing 0x3140 to the control register.
1725                  */
1726                 if (hw->phy.revision < 2) {
1727                         e1000e_phy_sw_reset(hw);
1728                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
1729                 }
1730         }
1731
1732         /* Select page 0 */
1733         ret_val = hw->phy.ops.acquire(hw);
1734         if (ret_val)
1735                 return ret_val;
1736
1737         hw->phy.addr = 1;
1738         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1739         hw->phy.ops.release(hw);
1740         if (ret_val)
1741                 return ret_val;
1742
1743         /* Configure the K1 Si workaround during phy reset assuming there is
1744          * link so that it disables K1 if link is in 1Gbps.
1745          */
1746         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1747         if (ret_val)
1748                 return ret_val;
1749
1750         /* Workaround for link disconnects on a busy hub in half duplex */
1751         ret_val = hw->phy.ops.acquire(hw);
1752         if (ret_val)
1753                 return ret_val;
1754         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1755         if (ret_val)
1756                 goto release;
1757         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
1758         if (ret_val)
1759                 goto release;
1760
1761         /* set MSE higher to enable link to stay up when noise is high */
1762         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
1763 release:
1764         hw->phy.ops.release(hw);
1765
1766         return ret_val;
1767 }
1768
1769 /**
1770  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1771  *  @hw:   pointer to the HW structure
1772  **/
1773 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1774 {
1775         u32 mac_reg;
1776         u16 i, phy_reg = 0;
1777         s32 ret_val;
1778
1779         ret_val = hw->phy.ops.acquire(hw);
1780         if (ret_val)
1781                 return;
1782         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1783         if (ret_val)
1784                 goto release;
1785
1786         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1787         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1788                 mac_reg = er32(RAL(i));
1789                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1790                                            (u16)(mac_reg & 0xFFFF));
1791                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1792                                            (u16)((mac_reg >> 16) & 0xFFFF));
1793
1794                 mac_reg = er32(RAH(i));
1795                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1796                                            (u16)(mac_reg & 0xFFFF));
1797                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1798                                            (u16)((mac_reg & E1000_RAH_AV)
1799                                                  >> 16));
1800         }
1801
1802         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1803
1804 release:
1805         hw->phy.ops.release(hw);
1806 }
1807
1808 /**
1809  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1810  *  with 82579 PHY
1811  *  @hw: pointer to the HW structure
1812  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1813  **/
1814 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1815 {
1816         s32 ret_val = 0;
1817         u16 phy_reg, data;
1818         u32 mac_reg;
1819         u16 i;
1820
1821         if (hw->mac.type < e1000_pch2lan)
1822                 return 0;
1823
1824         /* disable Rx path while enabling/disabling workaround */
1825         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1826         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1827         if (ret_val)
1828                 return ret_val;
1829
1830         if (enable) {
1831                 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
1832                  * SHRAL/H) and initial CRC values to the MAC
1833                  */
1834                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1835                         u8 mac_addr[ETH_ALEN] = { 0 };
1836                         u32 addr_high, addr_low;
1837
1838                         addr_high = er32(RAH(i));
1839                         if (!(addr_high & E1000_RAH_AV))
1840                                 continue;
1841                         addr_low = er32(RAL(i));
1842                         mac_addr[0] = (addr_low & 0xFF);
1843                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1844                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1845                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1846                         mac_addr[4] = (addr_high & 0xFF);
1847                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1848
1849                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1850                 }
1851
1852                 /* Write Rx addresses to the PHY */
1853                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1854
1855                 /* Enable jumbo frame workaround in the MAC */
1856                 mac_reg = er32(FFLT_DBG);
1857                 mac_reg &= ~(1 << 14);
1858                 mac_reg |= (7 << 15);
1859                 ew32(FFLT_DBG, mac_reg);
1860
1861                 mac_reg = er32(RCTL);
1862                 mac_reg |= E1000_RCTL_SECRC;
1863                 ew32(RCTL, mac_reg);
1864
1865                 ret_val = e1000e_read_kmrn_reg(hw,
1866                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
1867                                                &data);
1868                 if (ret_val)
1869                         return ret_val;
1870                 ret_val = e1000e_write_kmrn_reg(hw,
1871                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1872                                                 data | (1 << 0));
1873                 if (ret_val)
1874                         return ret_val;
1875                 ret_val = e1000e_read_kmrn_reg(hw,
1876                                                E1000_KMRNCTRLSTA_HD_CTRL,
1877                                                &data);
1878                 if (ret_val)
1879                         return ret_val;
1880                 data &= ~(0xF << 8);
1881                 data |= (0xB << 8);
1882                 ret_val = e1000e_write_kmrn_reg(hw,
1883                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1884                                                 data);
1885                 if (ret_val)
1886                         return ret_val;
1887
1888                 /* Enable jumbo frame workaround in the PHY */
1889                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1890                 data &= ~(0x7F << 5);
1891                 data |= (0x37 << 5);
1892                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1893                 if (ret_val)
1894                         return ret_val;
1895                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1896                 data &= ~(1 << 13);
1897                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1898                 if (ret_val)
1899                         return ret_val;
1900                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1901                 data &= ~(0x3FF << 2);
1902                 data |= (0x1A << 2);
1903                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1904                 if (ret_val)
1905                         return ret_val;
1906                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1907                 if (ret_val)
1908                         return ret_val;
1909                 e1e_rphy(hw, HV_PM_CTRL, &data);
1910                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1911                 if (ret_val)
1912                         return ret_val;
1913         } else {
1914                 /* Write MAC register values back to h/w defaults */
1915                 mac_reg = er32(FFLT_DBG);
1916                 mac_reg &= ~(0xF << 14);
1917                 ew32(FFLT_DBG, mac_reg);
1918
1919                 mac_reg = er32(RCTL);
1920                 mac_reg &= ~E1000_RCTL_SECRC;
1921                 ew32(RCTL, mac_reg);
1922
1923                 ret_val = e1000e_read_kmrn_reg(hw,
1924                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
1925                                                &data);
1926                 if (ret_val)
1927                         return ret_val;
1928                 ret_val = e1000e_write_kmrn_reg(hw,
1929                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1930                                                 data & ~(1 << 0));
1931                 if (ret_val)
1932                         return ret_val;
1933                 ret_val = e1000e_read_kmrn_reg(hw,
1934                                                E1000_KMRNCTRLSTA_HD_CTRL,
1935                                                &data);
1936                 if (ret_val)
1937                         return ret_val;
1938                 data &= ~(0xF << 8);
1939                 data |= (0xB << 8);
1940                 ret_val = e1000e_write_kmrn_reg(hw,
1941                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1942                                                 data);
1943                 if (ret_val)
1944                         return ret_val;
1945
1946                 /* Write PHY register values back to h/w defaults */
1947                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1948                 data &= ~(0x7F << 5);
1949                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1950                 if (ret_val)
1951                         return ret_val;
1952                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1953                 data |= (1 << 13);
1954                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1955                 if (ret_val)
1956                         return ret_val;
1957                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1958                 data &= ~(0x3FF << 2);
1959                 data |= (0x8 << 2);
1960                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1961                 if (ret_val)
1962                         return ret_val;
1963                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1964                 if (ret_val)
1965                         return ret_val;
1966                 e1e_rphy(hw, HV_PM_CTRL, &data);
1967                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1968                 if (ret_val)
1969                         return ret_val;
1970         }
1971
1972         /* re-enable Rx path after enabling/disabling workaround */
1973         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1974 }
1975
1976 /**
1977  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1978  *  done after every PHY reset.
1979  **/
1980 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1981 {
1982         s32 ret_val = 0;
1983
1984         if (hw->mac.type != e1000_pch2lan)
1985                 return 0;
1986
1987         /* Set MDIO slow mode before any other MDIO access */
1988         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1989         if (ret_val)
1990                 return ret_val;
1991
1992         ret_val = hw->phy.ops.acquire(hw);
1993         if (ret_val)
1994                 return ret_val;
1995         /* set MSE higher to enable link to stay up when noise is high */
1996         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
1997         if (ret_val)
1998                 goto release;
1999         /* drop link after 5 times MSE threshold was reached */
2000         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2001 release:
2002         hw->phy.ops.release(hw);
2003
2004         return ret_val;
2005 }
2006
2007 /**
2008  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2009  *  @hw:   pointer to the HW structure
2010  *
2011  *  Workaround to set the K1 beacon duration for 82579 parts
2012  **/
2013 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2014 {
2015         s32 ret_val = 0;
2016         u16 status_reg = 0;
2017         u32 mac_reg;
2018         u16 phy_reg;
2019
2020         if (hw->mac.type != e1000_pch2lan)
2021                 return 0;
2022
2023         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2024         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2025         if (ret_val)
2026                 return ret_val;
2027
2028         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2029             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2030                 mac_reg = er32(FEXTNVM4);
2031                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2032
2033                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2034                 if (ret_val)
2035                         return ret_val;
2036
2037                 if (status_reg & HV_M_STATUS_SPEED_1000) {
2038                         u16 pm_phy_reg;
2039
2040                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2041                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2042                         /* LV 1G Packet drop issue wa  */
2043                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2044                         if (ret_val)
2045                                 return ret_val;
2046                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2047                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2048                         if (ret_val)
2049                                 return ret_val;
2050                 } else {
2051                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2052                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2053                 }
2054                 ew32(FEXTNVM4, mac_reg);
2055                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2056         }
2057
2058         return ret_val;
2059 }
2060
2061 /**
2062  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2063  *  @hw:   pointer to the HW structure
2064  *  @gate: boolean set to true to gate, false to ungate
2065  *
2066  *  Gate/ungate the automatic PHY configuration via hardware; perform
2067  *  the configuration via software instead.
2068  **/
2069 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2070 {
2071         u32 extcnf_ctrl;
2072
2073         if (hw->mac.type < e1000_pch2lan)
2074                 return;
2075
2076         extcnf_ctrl = er32(EXTCNF_CTRL);
2077
2078         if (gate)
2079                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2080         else
2081                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2082
2083         ew32(EXTCNF_CTRL, extcnf_ctrl);
2084 }
2085
2086 /**
2087  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2088  *  @hw: pointer to the HW structure
2089  *
2090  *  Check the appropriate indication the MAC has finished configuring the
2091  *  PHY after a software reset.
2092  **/
2093 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2094 {
2095         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2096
2097         /* Wait for basic configuration completes before proceeding */
2098         do {
2099                 data = er32(STATUS);
2100                 data &= E1000_STATUS_LAN_INIT_DONE;
2101                 usleep_range(100, 200);
2102         } while ((!data) && --loop);
2103
2104         /* If basic configuration is incomplete before the above loop
2105          * count reaches 0, loading the configuration from NVM will
2106          * leave the PHY in a bad state possibly resulting in no link.
2107          */
2108         if (loop == 0)
2109                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2110
2111         /* Clear the Init Done bit for the next init event */
2112         data = er32(STATUS);
2113         data &= ~E1000_STATUS_LAN_INIT_DONE;
2114         ew32(STATUS, data);
2115 }
2116
2117 /**
2118  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2119  *  @hw: pointer to the HW structure
2120  **/
2121 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2122 {
2123         s32 ret_val = 0;
2124         u16 reg;
2125
2126         if (hw->phy.ops.check_reset_block(hw))
2127                 return 0;
2128
2129         /* Allow time for h/w to get to quiescent state after reset */
2130         usleep_range(10000, 20000);
2131
2132         /* Perform any necessary post-reset workarounds */
2133         switch (hw->mac.type) {
2134         case e1000_pchlan:
2135                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2136                 if (ret_val)
2137                         return ret_val;
2138                 break;
2139         case e1000_pch2lan:
2140                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2141                 if (ret_val)
2142                         return ret_val;
2143                 break;
2144         default:
2145                 break;
2146         }
2147
2148         /* Clear the host wakeup bit after lcd reset */
2149         if (hw->mac.type >= e1000_pchlan) {
2150                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2151                 reg &= ~BM_WUC_HOST_WU_BIT;
2152                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2153         }
2154
2155         /* Configure the LCD with the extended configuration region in NVM */
2156         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2157         if (ret_val)
2158                 return ret_val;
2159
2160         /* Configure the LCD with the OEM bits in NVM */
2161         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2162
2163         if (hw->mac.type == e1000_pch2lan) {
2164                 /* Ungate automatic PHY configuration on non-managed 82579 */
2165                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2166                         usleep_range(10000, 20000);
2167                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2168                 }
2169
2170                 /* Set EEE LPI Update Timer to 200usec */
2171                 ret_val = hw->phy.ops.acquire(hw);
2172                 if (ret_val)
2173                         return ret_val;
2174                 ret_val = e1000_write_emi_reg_locked(hw,
2175                                                      I82579_LPI_UPDATE_TIMER,
2176                                                      0x1387);
2177                 hw->phy.ops.release(hw);
2178         }
2179
2180         return ret_val;
2181 }
2182
2183 /**
2184  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2185  *  @hw: pointer to the HW structure
2186  *
2187  *  Resets the PHY
2188  *  This is a function pointer entry point called by drivers
2189  *  or other shared routines.
2190  **/
2191 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2192 {
2193         s32 ret_val = 0;
2194
2195         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2196         if ((hw->mac.type == e1000_pch2lan) &&
2197             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2198                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2199
2200         ret_val = e1000e_phy_hw_reset_generic(hw);
2201         if (ret_val)
2202                 return ret_val;
2203
2204         return e1000_post_phy_reset_ich8lan(hw);
2205 }
2206
2207 /**
2208  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2209  *  @hw: pointer to the HW structure
2210  *  @active: true to enable LPLU, false to disable
2211  *
2212  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2213  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2214  *  the phy speed. This function will manually set the LPLU bit and restart
2215  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2216  *  since it configures the same bit.
2217  **/
2218 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2219 {
2220         s32 ret_val;
2221         u16 oem_reg;
2222
2223         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2224         if (ret_val)
2225                 return ret_val;
2226
2227         if (active)
2228                 oem_reg |= HV_OEM_BITS_LPLU;
2229         else
2230                 oem_reg &= ~HV_OEM_BITS_LPLU;
2231
2232         if (!hw->phy.ops.check_reset_block(hw))
2233                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2234
2235         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2236 }
2237
2238 /**
2239  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2240  *  @hw: pointer to the HW structure
2241  *  @active: true to enable LPLU, false to disable
2242  *
2243  *  Sets the LPLU D0 state according to the active flag.  When
2244  *  activating LPLU this function also disables smart speed
2245  *  and vice versa.  LPLU will not be activated unless the
2246  *  device autonegotiation advertisement meets standards of
2247  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2248  *  This is a function pointer entry point only called by
2249  *  PHY setup routines.
2250  **/
2251 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2252 {
2253         struct e1000_phy_info *phy = &hw->phy;
2254         u32 phy_ctrl;
2255         s32 ret_val = 0;
2256         u16 data;
2257
2258         if (phy->type == e1000_phy_ife)
2259                 return 0;
2260
2261         phy_ctrl = er32(PHY_CTRL);
2262
2263         if (active) {
2264                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2265                 ew32(PHY_CTRL, phy_ctrl);
2266
2267                 if (phy->type != e1000_phy_igp_3)
2268                         return 0;
2269
2270                 /* Call gig speed drop workaround on LPLU before accessing
2271                  * any PHY registers
2272                  */
2273                 if (hw->mac.type == e1000_ich8lan)
2274                         e1000e_gig_downshift_workaround_ich8lan(hw);
2275
2276                 /* When LPLU is enabled, we should disable SmartSpeed */
2277                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2278                 if (ret_val)
2279                         return ret_val;
2280                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2281                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2282                 if (ret_val)
2283                         return ret_val;
2284         } else {
2285                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2286                 ew32(PHY_CTRL, phy_ctrl);
2287
2288                 if (phy->type != e1000_phy_igp_3)
2289                         return 0;
2290
2291                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2292                  * during Dx states where the power conservation is most
2293                  * important.  During driver activity we should enable
2294                  * SmartSpeed, so performance is maintained.
2295                  */
2296                 if (phy->smart_speed == e1000_smart_speed_on) {
2297                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2298                                            &data);
2299                         if (ret_val)
2300                                 return ret_val;
2301
2302                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2303                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2304                                            data);
2305                         if (ret_val)
2306                                 return ret_val;
2307                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2308                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2309                                            &data);
2310                         if (ret_val)
2311                                 return ret_val;
2312
2313                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2314                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2315                                            data);
2316                         if (ret_val)
2317                                 return ret_val;
2318                 }
2319         }
2320
2321         return 0;
2322 }
2323
2324 /**
2325  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2326  *  @hw: pointer to the HW structure
2327  *  @active: true to enable LPLU, false to disable
2328  *
2329  *  Sets the LPLU D3 state according to the active flag.  When
2330  *  activating LPLU this function also disables smart speed
2331  *  and vice versa.  LPLU will not be activated unless the
2332  *  device autonegotiation advertisement meets standards of
2333  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2334  *  This is a function pointer entry point only called by
2335  *  PHY setup routines.
2336  **/
2337 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2338 {
2339         struct e1000_phy_info *phy = &hw->phy;
2340         u32 phy_ctrl;
2341         s32 ret_val = 0;
2342         u16 data;
2343
2344         phy_ctrl = er32(PHY_CTRL);
2345
2346         if (!active) {
2347                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2348                 ew32(PHY_CTRL, phy_ctrl);
2349
2350                 if (phy->type != e1000_phy_igp_3)
2351                         return 0;
2352
2353                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2354                  * during Dx states where the power conservation is most
2355                  * important.  During driver activity we should enable
2356                  * SmartSpeed, so performance is maintained.
2357                  */
2358                 if (phy->smart_speed == e1000_smart_speed_on) {
2359                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2360                                            &data);
2361                         if (ret_val)
2362                                 return ret_val;
2363
2364                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2365                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2366                                            data);
2367                         if (ret_val)
2368                                 return ret_val;
2369                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2370                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2371                                            &data);
2372                         if (ret_val)
2373                                 return ret_val;
2374
2375                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2376                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2377                                            data);
2378                         if (ret_val)
2379                                 return ret_val;
2380                 }
2381         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2382                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2383                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2384                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2385                 ew32(PHY_CTRL, phy_ctrl);
2386
2387                 if (phy->type != e1000_phy_igp_3)
2388                         return 0;
2389
2390                 /* Call gig speed drop workaround on LPLU before accessing
2391                  * any PHY registers
2392                  */
2393                 if (hw->mac.type == e1000_ich8lan)
2394                         e1000e_gig_downshift_workaround_ich8lan(hw);
2395
2396                 /* When LPLU is enabled, we should disable SmartSpeed */
2397                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2398                 if (ret_val)
2399                         return ret_val;
2400
2401                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2402                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2403         }
2404
2405         return ret_val;
2406 }
2407
2408 /**
2409  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2410  *  @hw: pointer to the HW structure
2411  *  @bank:  pointer to the variable that returns the active bank
2412  *
2413  *  Reads signature byte from the NVM using the flash access registers.
2414  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2415  **/
2416 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2417 {
2418         u32 eecd;
2419         struct e1000_nvm_info *nvm = &hw->nvm;
2420         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2421         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2422         u8 sig_byte = 0;
2423         s32 ret_val;
2424
2425         switch (hw->mac.type) {
2426         case e1000_ich8lan:
2427         case e1000_ich9lan:
2428                 eecd = er32(EECD);
2429                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2430                     E1000_EECD_SEC1VAL_VALID_MASK) {
2431                         if (eecd & E1000_EECD_SEC1VAL)
2432                                 *bank = 1;
2433                         else
2434                                 *bank = 0;
2435
2436                         return 0;
2437                 }
2438                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2439                 /* fall-thru */
2440         default:
2441                 /* set bank to 0 in case flash read fails */
2442                 *bank = 0;
2443
2444                 /* Check bank 0 */
2445                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2446                                                         &sig_byte);
2447                 if (ret_val)
2448                         return ret_val;
2449                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2450                     E1000_ICH_NVM_SIG_VALUE) {
2451                         *bank = 0;
2452                         return 0;
2453                 }
2454
2455                 /* Check bank 1 */
2456                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2457                                                         bank1_offset,
2458                                                         &sig_byte);
2459                 if (ret_val)
2460                         return ret_val;
2461                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2462                     E1000_ICH_NVM_SIG_VALUE) {
2463                         *bank = 1;
2464                         return 0;
2465                 }
2466
2467                 e_dbg("ERROR: No valid NVM bank present\n");
2468                 return -E1000_ERR_NVM;
2469         }
2470 }
2471
2472 /**
2473  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2474  *  @hw: pointer to the HW structure
2475  *  @offset: The offset (in bytes) of the word(s) to read.
2476  *  @words: Size of data to read in words
2477  *  @data: Pointer to the word(s) to read at offset.
2478  *
2479  *  Reads a word(s) from the NVM using the flash access registers.
2480  **/
2481 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2482                                   u16 *data)
2483 {
2484         struct e1000_nvm_info *nvm = &hw->nvm;
2485         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2486         u32 act_offset;
2487         s32 ret_val = 0;
2488         u32 bank = 0;
2489         u16 i, word;
2490
2491         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2492             (words == 0)) {
2493                 e_dbg("nvm parameter(s) out of bounds\n");
2494                 ret_val = -E1000_ERR_NVM;
2495                 goto out;
2496         }
2497
2498         nvm->ops.acquire(hw);
2499
2500         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2501         if (ret_val) {
2502                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2503                 bank = 0;
2504         }
2505
2506         act_offset = (bank) ? nvm->flash_bank_size : 0;
2507         act_offset += offset;
2508
2509         ret_val = 0;
2510         for (i = 0; i < words; i++) {
2511                 if (dev_spec->shadow_ram[offset + i].modified) {
2512                         data[i] = dev_spec->shadow_ram[offset + i].value;
2513                 } else {
2514                         ret_val = e1000_read_flash_word_ich8lan(hw,
2515                                                                 act_offset + i,
2516                                                                 &word);
2517                         if (ret_val)
2518                                 break;
2519                         data[i] = word;
2520                 }
2521         }
2522
2523         nvm->ops.release(hw);
2524
2525 out:
2526         if (ret_val)
2527                 e_dbg("NVM read error: %d\n", ret_val);
2528
2529         return ret_val;
2530 }
2531
2532 /**
2533  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2534  *  @hw: pointer to the HW structure
2535  *
2536  *  This function does initial flash setup so that a new read/write/erase cycle
2537  *  can be started.
2538  **/
2539 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2540 {
2541         union ich8_hws_flash_status hsfsts;
2542         s32 ret_val = -E1000_ERR_NVM;
2543
2544         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2545
2546         /* Check if the flash descriptor is valid */
2547         if (!hsfsts.hsf_status.fldesvalid) {
2548                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
2549                 return -E1000_ERR_NVM;
2550         }
2551
2552         /* Clear FCERR and DAEL in hw status by writing 1 */
2553         hsfsts.hsf_status.flcerr = 1;
2554         hsfsts.hsf_status.dael = 1;
2555
2556         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2557
2558         /* Either we should have a hardware SPI cycle in progress
2559          * bit to check against, in order to start a new cycle or
2560          * FDONE bit should be changed in the hardware so that it
2561          * is 1 after hardware reset, which can then be used as an
2562          * indication whether a cycle is in progress or has been
2563          * completed.
2564          */
2565
2566         if (!hsfsts.hsf_status.flcinprog) {
2567                 /* There is no cycle running at present,
2568                  * so we can start a cycle.
2569                  * Begin by setting Flash Cycle Done.
2570                  */
2571                 hsfsts.hsf_status.flcdone = 1;
2572                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2573                 ret_val = 0;
2574         } else {
2575                 s32 i;
2576
2577                 /* Otherwise poll for sometime so the current
2578                  * cycle has a chance to end before giving up.
2579                  */
2580                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2581                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2582                         if (!hsfsts.hsf_status.flcinprog) {
2583                                 ret_val = 0;
2584                                 break;
2585                         }
2586                         udelay(1);
2587                 }
2588                 if (!ret_val) {
2589                         /* Successful in waiting for previous cycle to timeout,
2590                          * now set the Flash Cycle Done.
2591                          */
2592                         hsfsts.hsf_status.flcdone = 1;
2593                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2594                 } else {
2595                         e_dbg("Flash controller busy, cannot get access\n");
2596                 }
2597         }
2598
2599         return ret_val;
2600 }
2601
2602 /**
2603  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2604  *  @hw: pointer to the HW structure
2605  *  @timeout: maximum time to wait for completion
2606  *
2607  *  This function starts a flash cycle and waits for its completion.
2608  **/
2609 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2610 {
2611         union ich8_hws_flash_ctrl hsflctl;
2612         union ich8_hws_flash_status hsfsts;
2613         u32 i = 0;
2614
2615         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2616         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2617         hsflctl.hsf_ctrl.flcgo = 1;
2618         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2619
2620         /* wait till FDONE bit is set to 1 */
2621         do {
2622                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2623                 if (hsfsts.hsf_status.flcdone)
2624                         break;
2625                 udelay(1);
2626         } while (i++ < timeout);
2627
2628         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2629                 return 0;
2630
2631         return -E1000_ERR_NVM;
2632 }
2633
2634 /**
2635  *  e1000_read_flash_word_ich8lan - Read word from flash
2636  *  @hw: pointer to the HW structure
2637  *  @offset: offset to data location
2638  *  @data: pointer to the location for storing the data
2639  *
2640  *  Reads the flash word at offset into data.  Offset is converted
2641  *  to bytes before read.
2642  **/
2643 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2644                                          u16 *data)
2645 {
2646         /* Must convert offset into bytes. */
2647         offset <<= 1;
2648
2649         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2650 }
2651
2652 /**
2653  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2654  *  @hw: pointer to the HW structure
2655  *  @offset: The offset of the byte to read.
2656  *  @data: Pointer to a byte to store the value read.
2657  *
2658  *  Reads a single byte from the NVM using the flash access registers.
2659  **/
2660 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2661                                          u8 *data)
2662 {
2663         s32 ret_val;
2664         u16 word = 0;
2665
2666         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2667         if (ret_val)
2668                 return ret_val;
2669
2670         *data = (u8)word;
2671
2672         return 0;
2673 }
2674
2675 /**
2676  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2677  *  @hw: pointer to the HW structure
2678  *  @offset: The offset (in bytes) of the byte or word to read.
2679  *  @size: Size of data to read, 1=byte 2=word
2680  *  @data: Pointer to the word to store the value read.
2681  *
2682  *  Reads a byte or word from the NVM using the flash access registers.
2683  **/
2684 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2685                                          u8 size, u16 *data)
2686 {
2687         union ich8_hws_flash_status hsfsts;
2688         union ich8_hws_flash_ctrl hsflctl;
2689         u32 flash_linear_addr;
2690         u32 flash_data = 0;
2691         s32 ret_val = -E1000_ERR_NVM;
2692         u8 count = 0;
2693
2694         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2695                 return -E1000_ERR_NVM;
2696
2697         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2698                              hw->nvm.flash_base_addr);
2699
2700         do {
2701                 udelay(1);
2702                 /* Steps */
2703                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2704                 if (ret_val)
2705                         break;
2706
2707                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2708                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2709                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2710                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2711                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2712
2713                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2714
2715                 ret_val =
2716                     e1000_flash_cycle_ich8lan(hw,
2717                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
2718
2719                 /* Check if FCERR is set to 1, if set to 1, clear it
2720                  * and try the whole sequence a few more times, else
2721                  * read in (shift in) the Flash Data0, the order is
2722                  * least significant byte first msb to lsb
2723                  */
2724                 if (!ret_val) {
2725                         flash_data = er32flash(ICH_FLASH_FDATA0);
2726                         if (size == 1)
2727                                 *data = (u8)(flash_data & 0x000000FF);
2728                         else if (size == 2)
2729                                 *data = (u16)(flash_data & 0x0000FFFF);
2730                         break;
2731                 } else {
2732                         /* If we've gotten here, then things are probably
2733                          * completely hosed, but if the error condition is
2734                          * detected, it won't hurt to give it another try...
2735                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2736                          */
2737                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2738                         if (hsfsts.hsf_status.flcerr) {
2739                                 /* Repeat for some time before giving up. */
2740                                 continue;
2741                         } else if (!hsfsts.hsf_status.flcdone) {
2742                                 e_dbg("Timeout error - flash cycle did not complete.\n");
2743                                 break;
2744                         }
2745                 }
2746         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2747
2748         return ret_val;
2749 }
2750
2751 /**
2752  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2753  *  @hw: pointer to the HW structure
2754  *  @offset: The offset (in bytes) of the word(s) to write.
2755  *  @words: Size of data to write in words
2756  *  @data: Pointer to the word(s) to write at offset.
2757  *
2758  *  Writes a byte or word to the NVM using the flash access registers.
2759  **/
2760 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2761                                    u16 *data)
2762 {
2763         struct e1000_nvm_info *nvm = &hw->nvm;
2764         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2765         u16 i;
2766
2767         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2768             (words == 0)) {
2769                 e_dbg("nvm parameter(s) out of bounds\n");
2770                 return -E1000_ERR_NVM;
2771         }
2772
2773         nvm->ops.acquire(hw);
2774
2775         for (i = 0; i < words; i++) {
2776                 dev_spec->shadow_ram[offset + i].modified = true;
2777                 dev_spec->shadow_ram[offset + i].value = data[i];
2778         }
2779
2780         nvm->ops.release(hw);
2781
2782         return 0;
2783 }
2784
2785 /**
2786  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2787  *  @hw: pointer to the HW structure
2788  *
2789  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2790  *  which writes the checksum to the shadow ram.  The changes in the shadow
2791  *  ram are then committed to the EEPROM by processing each bank at a time
2792  *  checking for the modified bit and writing only the pending changes.
2793  *  After a successful commit, the shadow ram is cleared and is ready for
2794  *  future writes.
2795  **/
2796 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2797 {
2798         struct e1000_nvm_info *nvm = &hw->nvm;
2799         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2800         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2801         s32 ret_val;
2802         u16 data;
2803
2804         ret_val = e1000e_update_nvm_checksum_generic(hw);
2805         if (ret_val)
2806                 goto out;
2807
2808         if (nvm->type != e1000_nvm_flash_sw)
2809                 goto out;
2810
2811         nvm->ops.acquire(hw);
2812
2813         /* We're writing to the opposite bank so if we're on bank 1,
2814          * write to bank 0 etc.  We also need to erase the segment that
2815          * is going to be written
2816          */
2817         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2818         if (ret_val) {
2819                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2820                 bank = 0;
2821         }
2822
2823         if (bank == 0) {
2824                 new_bank_offset = nvm->flash_bank_size;
2825                 old_bank_offset = 0;
2826                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2827                 if (ret_val)
2828                         goto release;
2829         } else {
2830                 old_bank_offset = nvm->flash_bank_size;
2831                 new_bank_offset = 0;
2832                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2833                 if (ret_val)
2834                         goto release;
2835         }
2836
2837         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2838                 /* Determine whether to write the value stored
2839                  * in the other NVM bank or a modified value stored
2840                  * in the shadow RAM
2841                  */
2842                 if (dev_spec->shadow_ram[i].modified) {
2843                         data = dev_spec->shadow_ram[i].value;
2844                 } else {
2845                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2846                                                                 old_bank_offset,
2847                                                                 &data);
2848                         if (ret_val)
2849                                 break;
2850                 }
2851
2852                 /* If the word is 0x13, then make sure the signature bits
2853                  * (15:14) are 11b until the commit has completed.
2854                  * This will allow us to write 10b which indicates the
2855                  * signature is valid.  We want to do this after the write
2856                  * has completed so that we don't mark the segment valid
2857                  * while the write is still in progress
2858                  */
2859                 if (i == E1000_ICH_NVM_SIG_WORD)
2860                         data |= E1000_ICH_NVM_SIG_MASK;
2861
2862                 /* Convert offset to bytes. */
2863                 act_offset = (i + new_bank_offset) << 1;
2864
2865                 usleep_range(100, 200);
2866                 /* Write the bytes to the new bank. */
2867                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2868                                                                act_offset,
2869                                                                (u8)data);
2870                 if (ret_val)
2871                         break;
2872
2873                 usleep_range(100, 200);
2874                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2875                                                                act_offset + 1,
2876                                                                (u8)(data >> 8));
2877                 if (ret_val)
2878                         break;
2879         }
2880
2881         /* Don't bother writing the segment valid bits if sector
2882          * programming failed.
2883          */
2884         if (ret_val) {
2885                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2886                 e_dbg("Flash commit failed.\n");
2887                 goto release;
2888         }
2889
2890         /* Finally validate the new segment by setting bit 15:14
2891          * to 10b in word 0x13 , this can be done without an
2892          * erase as well since these bits are 11 to start with
2893          * and we need to change bit 14 to 0b
2894          */
2895         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2896         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2897         if (ret_val)
2898                 goto release;
2899
2900         data &= 0xBFFF;
2901         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2902                                                        act_offset * 2 + 1,
2903                                                        (u8)(data >> 8));
2904         if (ret_val)
2905                 goto release;
2906
2907         /* And invalidate the previously valid segment by setting
2908          * its signature word (0x13) high_byte to 0b. This can be
2909          * done without an erase because flash erase sets all bits
2910          * to 1's. We can write 1's to 0's without an erase
2911          */
2912         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2913         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2914         if (ret_val)
2915                 goto release;
2916
2917         /* Great!  Everything worked, we can now clear the cached entries. */
2918         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2919                 dev_spec->shadow_ram[i].modified = false;
2920                 dev_spec->shadow_ram[i].value = 0xFFFF;
2921         }
2922
2923 release:
2924         nvm->ops.release(hw);
2925
2926         /* Reload the EEPROM, or else modifications will not appear
2927          * until after the next adapter reset.
2928          */
2929         if (!ret_val) {
2930                 nvm->ops.reload(hw);
2931                 usleep_range(10000, 20000);
2932         }
2933
2934 out:
2935         if (ret_val)
2936                 e_dbg("NVM update error: %d\n", ret_val);
2937
2938         return ret_val;
2939 }
2940
2941 /**
2942  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2943  *  @hw: pointer to the HW structure
2944  *
2945  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2946  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2947  *  calculated, in which case we need to calculate the checksum and set bit 6.
2948  **/
2949 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2950 {
2951         s32 ret_val;
2952         u16 data;
2953         u16 word;
2954         u16 valid_csum_mask;
2955
2956         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
2957          * the checksum needs to be fixed.  This bit is an indication that
2958          * the NVM was prepared by OEM software and did not calculate
2959          * the checksum...a likely scenario.
2960          */
2961         switch (hw->mac.type) {
2962         case e1000_pch_lpt:
2963                 word = NVM_COMPAT;
2964                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
2965                 break;
2966         default:
2967                 word = NVM_FUTURE_INIT_WORD1;
2968                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
2969                 break;
2970         }
2971
2972         ret_val = e1000_read_nvm(hw, word, 1, &data);
2973         if (ret_val)
2974                 return ret_val;
2975
2976         if (!(data & valid_csum_mask)) {
2977                 data |= valid_csum_mask;
2978                 ret_val = e1000_write_nvm(hw, word, 1, &data);
2979                 if (ret_val)
2980                         return ret_val;
2981                 ret_val = e1000e_update_nvm_checksum(hw);
2982                 if (ret_val)
2983                         return ret_val;
2984         }
2985
2986         return e1000e_validate_nvm_checksum_generic(hw);
2987 }
2988
2989 /**
2990  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2991  *  @hw: pointer to the HW structure
2992  *
2993  *  To prevent malicious write/erase of the NVM, set it to be read-only
2994  *  so that the hardware ignores all write/erase cycles of the NVM via
2995  *  the flash control registers.  The shadow-ram copy of the NVM will
2996  *  still be updated, however any updates to this copy will not stick
2997  *  across driver reloads.
2998  **/
2999 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3000 {
3001         struct e1000_nvm_info *nvm = &hw->nvm;
3002         union ich8_flash_protected_range pr0;
3003         union ich8_hws_flash_status hsfsts;
3004         u32 gfpreg;
3005
3006         nvm->ops.acquire(hw);
3007
3008         gfpreg = er32flash(ICH_FLASH_GFPREG);
3009
3010         /* Write-protect GbE Sector of NVM */
3011         pr0.regval = er32flash(ICH_FLASH_PR0);
3012         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3013         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3014         pr0.range.wpe = true;
3015         ew32flash(ICH_FLASH_PR0, pr0.regval);
3016
3017         /* Lock down a subset of GbE Flash Control Registers, e.g.
3018          * PR0 to prevent the write-protection from being lifted.
3019          * Once FLOCKDN is set, the registers protected by it cannot
3020          * be written until FLOCKDN is cleared by a hardware reset.
3021          */
3022         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3023         hsfsts.hsf_status.flockdn = true;
3024         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3025
3026         nvm->ops.release(hw);
3027 }
3028
3029 /**
3030  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3031  *  @hw: pointer to the HW structure
3032  *  @offset: The offset (in bytes) of the byte/word to read.
3033  *  @size: Size of data to read, 1=byte 2=word
3034  *  @data: The byte(s) to write to the NVM.
3035  *
3036  *  Writes one/two bytes to the NVM using the flash access registers.
3037  **/
3038 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3039                                           u8 size, u16 data)
3040 {
3041         union ich8_hws_flash_status hsfsts;
3042         union ich8_hws_flash_ctrl hsflctl;
3043         u32 flash_linear_addr;
3044         u32 flash_data = 0;
3045         s32 ret_val;
3046         u8 count = 0;
3047
3048         if (size < 1 || size > 2 || data > size * 0xff ||
3049             offset > ICH_FLASH_LINEAR_ADDR_MASK)
3050                 return -E1000_ERR_NVM;
3051
3052         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3053                              hw->nvm.flash_base_addr);
3054
3055         do {
3056                 udelay(1);
3057                 /* Steps */
3058                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3059                 if (ret_val)
3060                         break;
3061
3062                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3063                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3064                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3065                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3066                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3067
3068                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3069
3070                 if (size == 1)
3071                         flash_data = (u32)data & 0x00FF;
3072                 else
3073                         flash_data = (u32)data;
3074
3075                 ew32flash(ICH_FLASH_FDATA0, flash_data);
3076
3077                 /* check if FCERR is set to 1 , if set to 1, clear it
3078                  * and try the whole sequence a few more times else done
3079                  */
3080                 ret_val =
3081                     e1000_flash_cycle_ich8lan(hw,
3082                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3083                 if (!ret_val)
3084                         break;
3085
3086                 /* If we're here, then things are most likely
3087                  * completely hosed, but if the error condition
3088                  * is detected, it won't hurt to give it another
3089                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3090                  */
3091                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3092                 if (hsfsts.hsf_status.flcerr)
3093                         /* Repeat for some time before giving up. */
3094                         continue;
3095                 if (!hsfsts.hsf_status.flcdone) {
3096                         e_dbg("Timeout error - flash cycle did not complete.\n");
3097                         break;
3098                 }
3099         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3100
3101         return ret_val;
3102 }
3103
3104 /**
3105  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3106  *  @hw: pointer to the HW structure
3107  *  @offset: The index of the byte to read.
3108  *  @data: The byte to write to the NVM.
3109  *
3110  *  Writes a single byte to the NVM using the flash access registers.
3111  **/
3112 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3113                                           u8 data)
3114 {
3115         u16 word = (u16)data;
3116
3117         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3118 }
3119
3120 /**
3121  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3122  *  @hw: pointer to the HW structure
3123  *  @offset: The offset of the byte to write.
3124  *  @byte: The byte to write to the NVM.
3125  *
3126  *  Writes a single byte to the NVM using the flash access registers.
3127  *  Goes through a retry algorithm before giving up.
3128  **/
3129 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3130                                                 u32 offset, u8 byte)
3131 {
3132         s32 ret_val;
3133         u16 program_retries;
3134
3135         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3136         if (!ret_val)
3137                 return ret_val;
3138
3139         for (program_retries = 0; program_retries < 100; program_retries++) {
3140                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3141                 usleep_range(100, 200);
3142                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3143                 if (!ret_val)
3144                         break;
3145         }
3146         if (program_retries == 100)
3147                 return -E1000_ERR_NVM;
3148
3149         return 0;
3150 }
3151
3152 /**
3153  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3154  *  @hw: pointer to the HW structure
3155  *  @bank: 0 for first bank, 1 for second bank, etc.
3156  *
3157  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3158  *  bank N is 4096 * N + flash_reg_addr.
3159  **/
3160 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3161 {
3162         struct e1000_nvm_info *nvm = &hw->nvm;
3163         union ich8_hws_flash_status hsfsts;
3164         union ich8_hws_flash_ctrl hsflctl;
3165         u32 flash_linear_addr;
3166         /* bank size is in 16bit words - adjust to bytes */
3167         u32 flash_bank_size = nvm->flash_bank_size * 2;
3168         s32 ret_val;
3169         s32 count = 0;
3170         s32 j, iteration, sector_size;
3171
3172         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3173
3174         /* Determine HW Sector size: Read BERASE bits of hw flash status
3175          * register
3176          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3177          *     consecutive sectors.  The start index for the nth Hw sector
3178          *     can be calculated as = bank * 4096 + n * 256
3179          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3180          *     The start index for the nth Hw sector can be calculated
3181          *     as = bank * 4096
3182          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3183          *     (ich9 only, otherwise error condition)
3184          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3185          */
3186         switch (hsfsts.hsf_status.berasesz) {
3187         case 0:
3188                 /* Hw sector size 256 */
3189                 sector_size = ICH_FLASH_SEG_SIZE_256;
3190                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3191                 break;
3192         case 1:
3193                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3194                 iteration = 1;
3195                 break;
3196         case 2:
3197                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3198                 iteration = 1;
3199                 break;
3200         case 3:
3201                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3202                 iteration = 1;
3203                 break;
3204         default:
3205                 return -E1000_ERR_NVM;
3206         }
3207
3208         /* Start with the base address, then add the sector offset. */
3209         flash_linear_addr = hw->nvm.flash_base_addr;
3210         flash_linear_addr += (bank) ? flash_bank_size : 0;
3211
3212         for (j = 0; j < iteration; j++) {
3213                 do {
3214                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3215
3216                         /* Steps */
3217                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3218                         if (ret_val)
3219                                 return ret_val;
3220
3221                         /* Write a value 11 (block Erase) in Flash
3222                          * Cycle field in hw flash control
3223                          */
3224                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3225                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3226                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3227
3228                         /* Write the last 24 bits of an index within the
3229                          * block into Flash Linear address field in Flash
3230                          * Address.
3231                          */
3232                         flash_linear_addr += (j * sector_size);
3233                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3234
3235                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3236                         if (!ret_val)
3237                                 break;
3238
3239                         /* Check if FCERR is set to 1.  If 1,
3240                          * clear it and try the whole sequence
3241                          * a few more times else Done
3242                          */
3243                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3244                         if (hsfsts.hsf_status.flcerr)
3245                                 /* repeat for some time before giving up */
3246                                 continue;
3247                         else if (!hsfsts.hsf_status.flcdone)
3248                                 return ret_val;
3249                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3250         }
3251
3252         return 0;
3253 }
3254
3255 /**
3256  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3257  *  @hw: pointer to the HW structure
3258  *  @data: Pointer to the LED settings
3259  *
3260  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3261  *  settings is all 0's or F's, set the LED default to a valid LED default
3262  *  setting.
3263  **/
3264 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3265 {
3266         s32 ret_val;
3267
3268         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3269         if (ret_val) {
3270                 e_dbg("NVM Read Error\n");
3271                 return ret_val;
3272         }
3273
3274         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3275                 *data = ID_LED_DEFAULT_ICH8LAN;
3276
3277         return 0;
3278 }
3279
3280 /**
3281  *  e1000_id_led_init_pchlan - store LED configurations
3282  *  @hw: pointer to the HW structure
3283  *
3284  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3285  *  the PHY LED configuration register.
3286  *
3287  *  PCH also does not have an "always on" or "always off" mode which
3288  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3289  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3290  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3291  *  link based on logic in e1000_led_[on|off]_pchlan().
3292  **/
3293 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3294 {
3295         struct e1000_mac_info *mac = &hw->mac;
3296         s32 ret_val;
3297         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3298         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3299         u16 data, i, temp, shift;
3300
3301         /* Get default ID LED modes */
3302         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3303         if (ret_val)
3304                 return ret_val;
3305
3306         mac->ledctl_default = er32(LEDCTL);
3307         mac->ledctl_mode1 = mac->ledctl_default;
3308         mac->ledctl_mode2 = mac->ledctl_default;
3309
3310         for (i = 0; i < 4; i++) {
3311                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3312                 shift = (i * 5);
3313                 switch (temp) {
3314                 case ID_LED_ON1_DEF2:
3315                 case ID_LED_ON1_ON2:
3316                 case ID_LED_ON1_OFF2:
3317                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3318                         mac->ledctl_mode1 |= (ledctl_on << shift);
3319                         break;
3320                 case ID_LED_OFF1_DEF2:
3321                 case ID_LED_OFF1_ON2:
3322                 case ID_LED_OFF1_OFF2:
3323                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3324                         mac->ledctl_mode1 |= (ledctl_off << shift);
3325                         break;
3326                 default:
3327                         /* Do nothing */
3328                         break;
3329                 }
3330                 switch (temp) {
3331                 case ID_LED_DEF1_ON2:
3332                 case ID_LED_ON1_ON2:
3333                 case ID_LED_OFF1_ON2:
3334                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3335                         mac->ledctl_mode2 |= (ledctl_on << shift);
3336                         break;
3337                 case ID_LED_DEF1_OFF2:
3338                 case ID_LED_ON1_OFF2:
3339                 case ID_LED_OFF1_OFF2:
3340                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3341                         mac->ledctl_mode2 |= (ledctl_off << shift);
3342                         break;
3343                 default:
3344                         /* Do nothing */
3345                         break;
3346                 }
3347         }
3348
3349         return 0;
3350 }
3351
3352 /**
3353  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3354  *  @hw: pointer to the HW structure
3355  *
3356  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3357  *  register, so the the bus width is hard coded.
3358  **/
3359 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3360 {
3361         struct e1000_bus_info *bus = &hw->bus;
3362         s32 ret_val;
3363
3364         ret_val = e1000e_get_bus_info_pcie(hw);
3365
3366         /* ICH devices are "PCI Express"-ish.  They have
3367          * a configuration space, but do not contain
3368          * PCI Express Capability registers, so bus width
3369          * must be hardcoded.
3370          */
3371         if (bus->width == e1000_bus_width_unknown)
3372                 bus->width = e1000_bus_width_pcie_x1;
3373
3374         return ret_val;
3375 }
3376
3377 /**
3378  *  e1000_reset_hw_ich8lan - Reset the hardware
3379  *  @hw: pointer to the HW structure
3380  *
3381  *  Does a full reset of the hardware which includes a reset of the PHY and
3382  *  MAC.
3383  **/
3384 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3385 {
3386         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3387         u16 kum_cfg;
3388         u32 ctrl, reg;
3389         s32 ret_val;
3390
3391         /* Prevent the PCI-E bus from sticking if there is no TLP connection
3392          * on the last TLP read/write transaction when MAC is reset.
3393          */
3394         ret_val = e1000e_disable_pcie_master(hw);
3395         if (ret_val)
3396                 e_dbg("PCI-E Master disable polling has failed.\n");
3397
3398         e_dbg("Masking off all interrupts\n");
3399         ew32(IMC, 0xffffffff);
3400
3401         /* Disable the Transmit and Receive units.  Then delay to allow
3402          * any pending transactions to complete before we hit the MAC
3403          * with the global reset.
3404          */
3405         ew32(RCTL, 0);
3406         ew32(TCTL, E1000_TCTL_PSP);
3407         e1e_flush();
3408
3409         usleep_range(10000, 20000);
3410
3411         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3412         if (hw->mac.type == e1000_ich8lan) {
3413                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3414                 ew32(PBA, E1000_PBA_8K);
3415                 /* Set Packet Buffer Size to 16k. */
3416                 ew32(PBS, E1000_PBS_16K);
3417         }
3418
3419         if (hw->mac.type == e1000_pchlan) {
3420                 /* Save the NVM K1 bit setting */
3421                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3422                 if (ret_val)
3423                         return ret_val;
3424
3425                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3426                         dev_spec->nvm_k1_enabled = true;
3427                 else
3428                         dev_spec->nvm_k1_enabled = false;
3429         }
3430
3431         ctrl = er32(CTRL);
3432
3433         if (!hw->phy.ops.check_reset_block(hw)) {
3434                 /* Full-chip reset requires MAC and PHY reset at the same
3435                  * time to make sure the interface between MAC and the
3436                  * external PHY is reset.
3437                  */
3438                 ctrl |= E1000_CTRL_PHY_RST;
3439
3440                 /* Gate automatic PHY configuration by hardware on
3441                  * non-managed 82579
3442                  */
3443                 if ((hw->mac.type == e1000_pch2lan) &&
3444                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3445                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3446         }
3447         ret_val = e1000_acquire_swflag_ich8lan(hw);
3448         e_dbg("Issuing a global reset to ich8lan\n");
3449         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3450         /* cannot issue a flush here because it hangs the hardware */
3451         msleep(20);
3452
3453         /* Set Phy Config Counter to 50msec */
3454         if (hw->mac.type == e1000_pch2lan) {
3455                 reg = er32(FEXTNVM3);
3456                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3457                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3458                 ew32(FEXTNVM3, reg);
3459         }
3460
3461         if (!ret_val)
3462                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3463
3464         if (ctrl & E1000_CTRL_PHY_RST) {
3465                 ret_val = hw->phy.ops.get_cfg_done(hw);
3466                 if (ret_val)
3467                         return ret_val;
3468
3469                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3470                 if (ret_val)
3471                         return ret_val;
3472         }
3473
3474         /* For PCH, this write will make sure that any noise
3475          * will be detected as a CRC error and be dropped rather than show up
3476          * as a bad packet to the DMA engine.
3477          */
3478         if (hw->mac.type == e1000_pchlan)
3479                 ew32(CRC_OFFSET, 0x65656565);
3480
3481         ew32(IMC, 0xffffffff);
3482         er32(ICR);
3483
3484         reg = er32(KABGTXD);
3485         reg |= E1000_KABGTXD_BGSQLBIAS;
3486         ew32(KABGTXD, reg);
3487
3488         return 0;
3489 }
3490
3491 /**
3492  *  e1000_init_hw_ich8lan - Initialize the hardware
3493  *  @hw: pointer to the HW structure
3494  *
3495  *  Prepares the hardware for transmit and receive by doing the following:
3496  *   - initialize hardware bits
3497  *   - initialize LED identification
3498  *   - setup receive address registers
3499  *   - setup flow control
3500  *   - setup transmit descriptors
3501  *   - clear statistics
3502  **/
3503 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3504 {
3505         struct e1000_mac_info *mac = &hw->mac;
3506         u32 ctrl_ext, txdctl, snoop;
3507         s32 ret_val;
3508         u16 i;
3509
3510         e1000_initialize_hw_bits_ich8lan(hw);
3511
3512         /* Initialize identification LED */
3513         ret_val = mac->ops.id_led_init(hw);
3514         /* An error is not fatal and we should not stop init due to this */
3515         if (ret_val)
3516                 e_dbg("Error initializing identification LED\n");
3517
3518         /* Setup the receive address. */
3519         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3520
3521         /* Zero out the Multicast HASH table */
3522         e_dbg("Zeroing the MTA\n");
3523         for (i = 0; i < mac->mta_reg_count; i++)
3524                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3525
3526         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3527          * the ME.  Disable wakeup by clearing the host wakeup bit.
3528          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3529          */
3530         if (hw->phy.type == e1000_phy_82578) {
3531                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3532                 i &= ~BM_WUC_HOST_WU_BIT;
3533                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3534                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3535                 if (ret_val)
3536                         return ret_val;
3537         }
3538
3539         /* Setup link and flow control */
3540         ret_val = mac->ops.setup_link(hw);
3541
3542         /* Set the transmit descriptor write-back policy for both queues */
3543         txdctl = er32(TXDCTL(0));
3544         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3545                   E1000_TXDCTL_FULL_TX_DESC_WB);
3546         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3547                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3548         ew32(TXDCTL(0), txdctl);
3549         txdctl = er32(TXDCTL(1));
3550         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3551                   E1000_TXDCTL_FULL_TX_DESC_WB);
3552         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3553                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3554         ew32(TXDCTL(1), txdctl);
3555
3556         /* ICH8 has opposite polarity of no_snoop bits.
3557          * By default, we should use snoop behavior.
3558          */
3559         if (mac->type == e1000_ich8lan)
3560                 snoop = PCIE_ICH8_SNOOP_ALL;
3561         else
3562                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
3563         e1000e_set_pcie_no_snoop(hw, snoop);
3564
3565         ctrl_ext = er32(CTRL_EXT);
3566         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3567         ew32(CTRL_EXT, ctrl_ext);
3568
3569         /* Clear all of the statistics registers (clear on read).  It is
3570          * important that we do this after we have tried to establish link
3571          * because the symbol error count will increment wildly if there
3572          * is no link.
3573          */
3574         e1000_clear_hw_cntrs_ich8lan(hw);
3575
3576         return ret_val;
3577 }
3578
3579 /**
3580  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3581  *  @hw: pointer to the HW structure
3582  *
3583  *  Sets/Clears required hardware bits necessary for correctly setting up the
3584  *  hardware for transmit and receive.
3585  **/
3586 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3587 {
3588         u32 reg;
3589
3590         /* Extended Device Control */
3591         reg = er32(CTRL_EXT);
3592         reg |= (1 << 22);
3593         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3594         if (hw->mac.type >= e1000_pchlan)
3595                 reg |= E1000_CTRL_EXT_PHYPDEN;
3596         ew32(CTRL_EXT, reg);
3597
3598         /* Transmit Descriptor Control 0 */
3599         reg = er32(TXDCTL(0));
3600         reg |= (1 << 22);
3601         ew32(TXDCTL(0), reg);
3602
3603         /* Transmit Descriptor Control 1 */
3604         reg = er32(TXDCTL(1));
3605         reg |= (1 << 22);
3606         ew32(TXDCTL(1), reg);
3607
3608         /* Transmit Arbitration Control 0 */
3609         reg = er32(TARC(0));
3610         if (hw->mac.type == e1000_ich8lan)
3611                 reg |= (1 << 28) | (1 << 29);
3612         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3613         ew32(TARC(0), reg);
3614
3615         /* Transmit Arbitration Control 1 */
3616         reg = er32(TARC(1));
3617         if (er32(TCTL) & E1000_TCTL_MULR)
3618                 reg &= ~(1 << 28);
3619         else
3620                 reg |= (1 << 28);
3621         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3622         ew32(TARC(1), reg);
3623
3624         /* Device Status */
3625         if (hw->mac.type == e1000_ich8lan) {
3626                 reg = er32(STATUS);
3627                 reg &= ~(1 << 31);
3628                 ew32(STATUS, reg);
3629         }
3630
3631         /* work-around descriptor data corruption issue during nfs v2 udp
3632          * traffic, just disable the nfs filtering capability
3633          */
3634         reg = er32(RFCTL);
3635         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3636
3637         /* Disable IPv6 extension header parsing because some malformed
3638          * IPv6 headers can hang the Rx.
3639          */
3640         if (hw->mac.type == e1000_ich8lan)
3641                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3642         ew32(RFCTL, reg);
3643
3644         /* Enable ECC on Lynxpoint */
3645         if (hw->mac.type == e1000_pch_lpt) {
3646                 reg = er32(PBECCSTS);
3647                 reg |= E1000_PBECCSTS_ECC_ENABLE;
3648                 ew32(PBECCSTS, reg);
3649
3650                 reg = er32(CTRL);
3651                 reg |= E1000_CTRL_MEHE;
3652                 ew32(CTRL, reg);
3653         }
3654 }
3655
3656 /**
3657  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3658  *  @hw: pointer to the HW structure
3659  *
3660  *  Determines which flow control settings to use, then configures flow
3661  *  control.  Calls the appropriate media-specific link configuration
3662  *  function.  Assuming the adapter has a valid link partner, a valid link
3663  *  should be established.  Assumes the hardware has previously been reset
3664  *  and the transmitter and receiver are not enabled.
3665  **/
3666 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3667 {
3668         s32 ret_val;
3669
3670         if (hw->phy.ops.check_reset_block(hw))
3671                 return 0;
3672
3673         /* ICH parts do not have a word in the NVM to determine
3674          * the default flow control setting, so we explicitly
3675          * set it to full.
3676          */
3677         if (hw->fc.requested_mode == e1000_fc_default) {
3678                 /* Workaround h/w hang when Tx flow control enabled */
3679                 if (hw->mac.type == e1000_pchlan)
3680                         hw->fc.requested_mode = e1000_fc_rx_pause;
3681                 else
3682                         hw->fc.requested_mode = e1000_fc_full;
3683         }
3684
3685         /* Save off the requested flow control mode for use later.  Depending
3686          * on the link partner's capabilities, we may or may not use this mode.
3687          */
3688         hw->fc.current_mode = hw->fc.requested_mode;
3689
3690         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
3691
3692         /* Continue to configure the copper link. */
3693         ret_val = hw->mac.ops.setup_physical_interface(hw);
3694         if (ret_val)
3695                 return ret_val;
3696
3697         ew32(FCTTV, hw->fc.pause_time);
3698         if ((hw->phy.type == e1000_phy_82578) ||
3699             (hw->phy.type == e1000_phy_82579) ||
3700             (hw->phy.type == e1000_phy_i217) ||
3701             (hw->phy.type == e1000_phy_82577)) {
3702                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3703
3704                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3705                                    hw->fc.pause_time);
3706                 if (ret_val)
3707                         return ret_val;
3708         }
3709
3710         return e1000e_set_fc_watermarks(hw);
3711 }
3712
3713 /**
3714  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3715  *  @hw: pointer to the HW structure
3716  *
3717  *  Configures the kumeran interface to the PHY to wait the appropriate time
3718  *  when polling the PHY, then call the generic setup_copper_link to finish
3719  *  configuring the copper link.
3720  **/
3721 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3722 {
3723         u32 ctrl;
3724         s32 ret_val;
3725         u16 reg_data;
3726
3727         ctrl = er32(CTRL);
3728         ctrl |= E1000_CTRL_SLU;
3729         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3730         ew32(CTRL, ctrl);
3731
3732         /* Set the mac to wait the maximum time between each iteration
3733          * and increase the max iterations when polling the phy;
3734          * this fixes erroneous timeouts at 10Mbps.
3735          */
3736         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3737         if (ret_val)
3738                 return ret_val;
3739         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3740                                        &reg_data);
3741         if (ret_val)
3742                 return ret_val;
3743         reg_data |= 0x3F;
3744         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3745                                         reg_data);
3746         if (ret_val)
3747                 return ret_val;
3748
3749         switch (hw->phy.type) {
3750         case e1000_phy_igp_3:
3751                 ret_val = e1000e_copper_link_setup_igp(hw);
3752                 if (ret_val)
3753                         return ret_val;
3754                 break;
3755         case e1000_phy_bm:
3756         case e1000_phy_82578:
3757                 ret_val = e1000e_copper_link_setup_m88(hw);
3758                 if (ret_val)
3759                         return ret_val;
3760                 break;
3761         case e1000_phy_82577:
3762         case e1000_phy_82579:
3763         case e1000_phy_i217:
3764                 ret_val = e1000_copper_link_setup_82577(hw);
3765                 if (ret_val)
3766                         return ret_val;
3767                 break;
3768         case e1000_phy_ife:
3769                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3770                 if (ret_val)
3771                         return ret_val;
3772
3773                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3774
3775                 switch (hw->phy.mdix) {
3776                 case 1:
3777                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3778                         break;
3779                 case 2:
3780                         reg_data |= IFE_PMC_FORCE_MDIX;
3781                         break;
3782                 case 0:
3783                 default:
3784                         reg_data |= IFE_PMC_AUTO_MDIX;
3785                         break;
3786                 }
3787                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3788                 if (ret_val)
3789                         return ret_val;
3790                 break;
3791         default:
3792                 break;
3793         }
3794
3795         return e1000e_setup_copper_link(hw);
3796 }
3797
3798 /**
3799  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3800  *  @hw: pointer to the HW structure
3801  *  @speed: pointer to store current link speed
3802  *  @duplex: pointer to store the current link duplex
3803  *
3804  *  Calls the generic get_speed_and_duplex to retrieve the current link
3805  *  information and then calls the Kumeran lock loss workaround for links at
3806  *  gigabit speeds.
3807  **/
3808 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3809                                           u16 *duplex)
3810 {
3811         s32 ret_val;
3812
3813         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3814         if (ret_val)
3815                 return ret_val;
3816
3817         if ((hw->mac.type == e1000_ich8lan) &&
3818             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3819                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3820         }
3821
3822         return ret_val;
3823 }
3824
3825 /**
3826  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3827  *  @hw: pointer to the HW structure
3828  *
3829  *  Work-around for 82566 Kumeran PCS lock loss:
3830  *  On link status change (i.e. PCI reset, speed change) and link is up and
3831  *  speed is gigabit-
3832  *    0) if workaround is optionally disabled do nothing
3833  *    1) wait 1ms for Kumeran link to come up
3834  *    2) check Kumeran Diagnostic register PCS lock loss bit
3835  *    3) if not set the link is locked (all is good), otherwise...
3836  *    4) reset the PHY
3837  *    5) repeat up to 10 times
3838  *  Note: this is only called for IGP3 copper when speed is 1gb.
3839  **/
3840 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3841 {
3842         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3843         u32 phy_ctrl;
3844         s32 ret_val;
3845         u16 i, data;
3846         bool link;
3847
3848         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3849                 return 0;
3850
3851         /* Make sure link is up before proceeding.  If not just return.
3852          * Attempting this while link is negotiating fouled up link
3853          * stability
3854          */
3855         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3856         if (!link)
3857                 return 0;
3858
3859         for (i = 0; i < 10; i++) {
3860                 /* read once to clear */
3861                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3862                 if (ret_val)
3863                         return ret_val;
3864                 /* and again to get new status */
3865                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3866                 if (ret_val)
3867                         return ret_val;
3868
3869                 /* check for PCS lock */
3870                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3871                         return 0;
3872
3873                 /* Issue PHY reset */
3874                 e1000_phy_hw_reset(hw);
3875                 mdelay(5);
3876         }
3877         /* Disable GigE link negotiation */
3878         phy_ctrl = er32(PHY_CTRL);
3879         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3880                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3881         ew32(PHY_CTRL, phy_ctrl);
3882
3883         /* Call gig speed drop workaround on Gig disable before accessing
3884          * any PHY registers
3885          */
3886         e1000e_gig_downshift_workaround_ich8lan(hw);
3887
3888         /* unable to acquire PCS lock */
3889         return -E1000_ERR_PHY;
3890 }
3891
3892 /**
3893  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3894  *  @hw: pointer to the HW structure
3895  *  @state: boolean value used to set the current Kumeran workaround state
3896  *
3897  *  If ICH8, set the current Kumeran workaround state (enabled - true
3898  *  /disabled - false).
3899  **/
3900 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3901                                                   bool state)
3902 {
3903         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3904
3905         if (hw->mac.type != e1000_ich8lan) {
3906                 e_dbg("Workaround applies to ICH8 only.\n");
3907                 return;
3908         }
3909
3910         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3911 }
3912
3913 /**
3914  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3915  *  @hw: pointer to the HW structure
3916  *
3917  *  Workaround for 82566 power-down on D3 entry:
3918  *    1) disable gigabit link
3919  *    2) write VR power-down enable
3920  *    3) read it back
3921  *  Continue if successful, else issue LCD reset and repeat
3922  **/
3923 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3924 {
3925         u32 reg;
3926         u16 data;
3927         u8  retry = 0;
3928
3929         if (hw->phy.type != e1000_phy_igp_3)
3930                 return;
3931
3932         /* Try the workaround twice (if needed) */
3933         do {
3934                 /* Disable link */
3935                 reg = er32(PHY_CTRL);
3936                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3937                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3938                 ew32(PHY_CTRL, reg);
3939
3940                 /* Call gig speed drop workaround on Gig disable before
3941                  * accessing any PHY registers
3942                  */
3943                 if (hw->mac.type == e1000_ich8lan)
3944                         e1000e_gig_downshift_workaround_ich8lan(hw);
3945
3946                 /* Write VR power-down enable */
3947                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3948                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3949                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3950
3951                 /* Read it back and test */
3952                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3953                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3954                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3955                         break;
3956
3957                 /* Issue PHY reset and repeat at most one more time */
3958                 reg = er32(CTRL);
3959                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3960                 retry++;
3961         } while (retry);
3962 }
3963
3964 /**
3965  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3966  *  @hw: pointer to the HW structure
3967  *
3968  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3969  *  LPLU, Gig disable, MDIC PHY reset):
3970  *    1) Set Kumeran Near-end loopback
3971  *    2) Clear Kumeran Near-end loopback
3972  *  Should only be called for ICH8[m] devices with any 1G Phy.
3973  **/
3974 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3975 {
3976         s32 ret_val;
3977         u16 reg_data;
3978
3979         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
3980                 return;
3981
3982         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3983                                        &reg_data);
3984         if (ret_val)
3985                 return;
3986         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3987         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3988                                         reg_data);
3989         if (ret_val)
3990                 return;
3991         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3992         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
3993 }
3994
3995 /**
3996  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3997  *  @hw: pointer to the HW structure
3998  *
3999  *  During S0 to Sx transition, it is possible the link remains at gig
4000  *  instead of negotiating to a lower speed.  Before going to Sx, set
4001  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4002  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4003  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4004  *  needs to be written.
4005  *  Parts that support (and are linked to a partner which support) EEE in
4006  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4007  *  than 10Mbps w/o EEE.
4008  **/
4009 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4010 {
4011         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4012         u32 phy_ctrl;
4013         s32 ret_val;
4014
4015         phy_ctrl = er32(PHY_CTRL);
4016         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4017
4018         if (hw->phy.type == e1000_phy_i217) {
4019                 u16 phy_reg, device_id = hw->adapter->pdev->device;
4020
4021                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4022                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {
4023                         u32 fextnvm6 = er32(FEXTNVM6);
4024
4025                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4026                 }
4027
4028                 ret_val = hw->phy.ops.acquire(hw);
4029                 if (ret_val)
4030                         goto out;
4031
4032                 if (!dev_spec->eee_disable) {
4033                         u16 eee_advert;
4034
4035                         ret_val =
4036                             e1000_read_emi_reg_locked(hw,
4037                                                       I217_EEE_ADVERTISEMENT,
4038                                                       &eee_advert);
4039                         if (ret_val)
4040                                 goto release;
4041
4042                         /* Disable LPLU if both link partners support 100BaseT
4043                          * EEE and 100Full is advertised on both ends of the
4044                          * link.
4045                          */
4046                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4047                             (dev_spec->eee_lp_ability &
4048                              I82579_EEE_100_SUPPORTED) &&
4049                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4050                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4051                                               E1000_PHY_CTRL_NOND0A_LPLU);
4052                 }
4053
4054                 /* For i217 Intel Rapid Start Technology support,
4055                  * when the system is going into Sx and no manageability engine
4056                  * is present, the driver must configure proxy to reset only on
4057                  * power good.  LPI (Low Power Idle) state must also reset only
4058                  * on power good, as well as the MTA (Multicast table array).
4059                  * The SMBus release must also be disabled on LCD reset.
4060                  */
4061                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4062                         /* Enable proxy to reset only on power good. */
4063                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4064                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4065                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4066
4067                         /* Set bit enable LPI (EEE) to reset only on
4068                          * power good.
4069                          */
4070                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4071                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4072                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4073
4074                         /* Disable the SMB release on LCD reset. */
4075                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4076                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4077                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4078                 }
4079
4080                 /* Enable MTA to reset for Intel Rapid Start Technology
4081                  * Support
4082                  */
4083                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4084                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4085                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4086
4087 release:
4088                 hw->phy.ops.release(hw);
4089         }
4090 out:
4091         ew32(PHY_CTRL, phy_ctrl);
4092
4093         if (hw->mac.type == e1000_ich8lan)
4094                 e1000e_gig_downshift_workaround_ich8lan(hw);
4095
4096         if (hw->mac.type >= e1000_pchlan) {
4097                 e1000_oem_bits_config_ich8lan(hw, false);
4098
4099                 /* Reset PHY to activate OEM bits on 82577/8 */
4100                 if (hw->mac.type == e1000_pchlan)
4101                         e1000e_phy_hw_reset_generic(hw);
4102
4103                 ret_val = hw->phy.ops.acquire(hw);
4104                 if (ret_val)
4105                         return;
4106                 e1000_write_smbus_addr(hw);
4107                 hw->phy.ops.release(hw);
4108         }
4109 }
4110
4111 /**
4112  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4113  *  @hw: pointer to the HW structure
4114  *
4115  *  During Sx to S0 transitions on non-managed devices or managed devices
4116  *  on which PHY resets are not blocked, if the PHY registers cannot be
4117  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4118  *  the PHY.
4119  *  On i217, setup Intel Rapid Start Technology.
4120  **/
4121 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4122 {
4123         s32 ret_val;
4124
4125         if (hw->mac.type < e1000_pch2lan)
4126                 return;
4127
4128         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4129         if (ret_val) {
4130                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4131                 return;
4132         }
4133
4134         /* For i217 Intel Rapid Start Technology support when the system
4135          * is transitioning from Sx and no manageability engine is present
4136          * configure SMBus to restore on reset, disable proxy, and enable
4137          * the reset on MTA (Multicast table array).
4138          */
4139         if (hw->phy.type == e1000_phy_i217) {
4140                 u16 phy_reg;
4141
4142                 ret_val = hw->phy.ops.acquire(hw);
4143                 if (ret_val) {
4144                         e_dbg("Failed to setup iRST\n");
4145                         return;
4146                 }
4147
4148                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4149                         /* Restore clear on SMB if no manageability engine
4150                          * is present
4151                          */
4152                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4153                         if (ret_val)
4154                                 goto release;
4155                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4156                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4157
4158                         /* Disable Proxy */
4159                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4160                 }
4161                 /* Enable reset on MTA */
4162                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4163                 if (ret_val)
4164                         goto release;
4165                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4166                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4167 release:
4168                 if (ret_val)
4169                         e_dbg("Error %d in resume workarounds\n", ret_val);
4170                 hw->phy.ops.release(hw);
4171         }
4172 }
4173
4174 /**
4175  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4176  *  @hw: pointer to the HW structure
4177  *
4178  *  Return the LED back to the default configuration.
4179  **/
4180 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4181 {
4182         if (hw->phy.type == e1000_phy_ife)
4183                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4184
4185         ew32(LEDCTL, hw->mac.ledctl_default);
4186         return 0;
4187 }
4188
4189 /**
4190  *  e1000_led_on_ich8lan - Turn LEDs on
4191  *  @hw: pointer to the HW structure
4192  *
4193  *  Turn on the LEDs.
4194  **/
4195 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4196 {
4197         if (hw->phy.type == e1000_phy_ife)
4198                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4199                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4200
4201         ew32(LEDCTL, hw->mac.ledctl_mode2);
4202         return 0;
4203 }
4204
4205 /**
4206  *  e1000_led_off_ich8lan - Turn LEDs off
4207  *  @hw: pointer to the HW structure
4208  *
4209  *  Turn off the LEDs.
4210  **/
4211 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4212 {
4213         if (hw->phy.type == e1000_phy_ife)
4214                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4215                                 (IFE_PSCL_PROBE_MODE |
4216                                  IFE_PSCL_PROBE_LEDS_OFF));
4217
4218         ew32(LEDCTL, hw->mac.ledctl_mode1);
4219         return 0;
4220 }
4221
4222 /**
4223  *  e1000_setup_led_pchlan - Configures SW controllable LED
4224  *  @hw: pointer to the HW structure
4225  *
4226  *  This prepares the SW controllable LED for use.
4227  **/
4228 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4229 {
4230         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4231 }
4232
4233 /**
4234  *  e1000_cleanup_led_pchlan - Restore the default LED operation
4235  *  @hw: pointer to the HW structure
4236  *
4237  *  Return the LED back to the default configuration.
4238  **/
4239 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4240 {
4241         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4242 }
4243
4244 /**
4245  *  e1000_led_on_pchlan - Turn LEDs on
4246  *  @hw: pointer to the HW structure
4247  *
4248  *  Turn on the LEDs.
4249  **/
4250 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4251 {
4252         u16 data = (u16)hw->mac.ledctl_mode2;
4253         u32 i, led;
4254
4255         /* If no link, then turn LED on by setting the invert bit
4256          * for each LED that's mode is "link_up" in ledctl_mode2.
4257          */
4258         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4259                 for (i = 0; i < 3; i++) {
4260                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4261                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4262                             E1000_LEDCTL_MODE_LINK_UP)
4263                                 continue;
4264                         if (led & E1000_PHY_LED0_IVRT)
4265                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4266                         else
4267                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4268                 }
4269         }
4270
4271         return e1e_wphy(hw, HV_LED_CONFIG, data);
4272 }
4273
4274 /**
4275  *  e1000_led_off_pchlan - Turn LEDs off
4276  *  @hw: pointer to the HW structure
4277  *
4278  *  Turn off the LEDs.
4279  **/
4280 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4281 {
4282         u16 data = (u16)hw->mac.ledctl_mode1;
4283         u32 i, led;
4284
4285         /* If no link, then turn LED off by clearing the invert bit
4286          * for each LED that's mode is "link_up" in ledctl_mode1.
4287          */
4288         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4289                 for (i = 0; i < 3; i++) {
4290                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4291                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4292                             E1000_LEDCTL_MODE_LINK_UP)
4293                                 continue;
4294                         if (led & E1000_PHY_LED0_IVRT)
4295                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4296                         else
4297                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4298                 }
4299         }
4300
4301         return e1e_wphy(hw, HV_LED_CONFIG, data);
4302 }
4303
4304 /**
4305  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4306  *  @hw: pointer to the HW structure
4307  *
4308  *  Read appropriate register for the config done bit for completion status
4309  *  and configure the PHY through s/w for EEPROM-less parts.
4310  *
4311  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4312  *  config done bit, so only an error is logged and continues.  If we were
4313  *  to return with error, EEPROM-less silicon would not be able to be reset
4314  *  or change link.
4315  **/
4316 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4317 {
4318         s32 ret_val = 0;
4319         u32 bank = 0;
4320         u32 status;
4321
4322         e1000e_get_cfg_done_generic(hw);
4323
4324         /* Wait for indication from h/w that it has completed basic config */
4325         if (hw->mac.type >= e1000_ich10lan) {
4326                 e1000_lan_init_done_ich8lan(hw);
4327         } else {
4328                 ret_val = e1000e_get_auto_rd_done(hw);
4329                 if (ret_val) {
4330                         /* When auto config read does not complete, do not
4331                          * return with an error. This can happen in situations
4332                          * where there is no eeprom and prevents getting link.
4333                          */
4334                         e_dbg("Auto Read Done did not complete\n");
4335                         ret_val = 0;
4336                 }
4337         }
4338
4339         /* Clear PHY Reset Asserted bit */
4340         status = er32(STATUS);
4341         if (status & E1000_STATUS_PHYRA)
4342                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4343         else
4344                 e_dbg("PHY Reset Asserted not set - needs delay\n");
4345
4346         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4347         if (hw->mac.type <= e1000_ich9lan) {
4348                 if (!(er32(EECD) & E1000_EECD_PRES) &&
4349                     (hw->phy.type == e1000_phy_igp_3)) {
4350                         e1000e_phy_init_script_igp3(hw);
4351                 }
4352         } else {
4353                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4354                         /* Maybe we should do a basic PHY config */
4355                         e_dbg("EEPROM not present\n");
4356                         ret_val = -E1000_ERR_CONFIG;
4357                 }
4358         }
4359
4360         return ret_val;
4361 }
4362
4363 /**
4364  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4365  * @hw: pointer to the HW structure
4366  *
4367  * In the case of a PHY power down to save power, or to turn off link during a
4368  * driver unload, or wake on lan is not enabled, remove the link.
4369  **/
4370 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4371 {
4372         /* If the management interface is not enabled, then power down */
4373         if (!(hw->mac.ops.check_mng_mode(hw) ||
4374               hw->phy.ops.check_reset_block(hw)))
4375                 e1000_power_down_phy_copper(hw);
4376 }
4377
4378 /**
4379  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4380  *  @hw: pointer to the HW structure
4381  *
4382  *  Clears hardware counters specific to the silicon family and calls
4383  *  clear_hw_cntrs_generic to clear all general purpose counters.
4384  **/
4385 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4386 {
4387         u16 phy_data;
4388         s32 ret_val;
4389
4390         e1000e_clear_hw_cntrs_base(hw);
4391
4392         er32(ALGNERRC);
4393         er32(RXERRC);
4394         er32(TNCRS);
4395         er32(CEXTERR);
4396         er32(TSCTC);
4397         er32(TSCTFC);
4398
4399         er32(MGTPRC);
4400         er32(MGTPDC);
4401         er32(MGTPTC);
4402
4403         er32(IAC);
4404         er32(ICRXOC);
4405
4406         /* Clear PHY statistics registers */
4407         if ((hw->phy.type == e1000_phy_82578) ||
4408             (hw->phy.type == e1000_phy_82579) ||
4409             (hw->phy.type == e1000_phy_i217) ||
4410             (hw->phy.type == e1000_phy_82577)) {
4411                 ret_val = hw->phy.ops.acquire(hw);
4412                 if (ret_val)
4413                         return;
4414                 ret_val = hw->phy.ops.set_page(hw,
4415                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4416                 if (ret_val)
4417                         goto release;
4418                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4419                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4420                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4421                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4422                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4423                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4424                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4425                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4426                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4427                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4428                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4429                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4430                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4431                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4432 release:
4433                 hw->phy.ops.release(hw);
4434         }
4435 }
4436
4437 static const struct e1000_mac_operations ich8_mac_ops = {
4438         /* check_mng_mode dependent on mac type */
4439         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4440         /* cleanup_led dependent on mac type */
4441         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4442         .get_bus_info           = e1000_get_bus_info_ich8lan,
4443         .set_lan_id             = e1000_set_lan_id_single_port,
4444         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4445         /* led_on dependent on mac type */
4446         /* led_off dependent on mac type */
4447         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4448         .reset_hw               = e1000_reset_hw_ich8lan,
4449         .init_hw                = e1000_init_hw_ich8lan,
4450         .setup_link             = e1000_setup_link_ich8lan,
4451         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
4452         /* id_led_init dependent on mac type */
4453         .config_collision_dist  = e1000e_config_collision_dist_generic,
4454         .rar_set                = e1000e_rar_set_generic,
4455 };
4456
4457 static const struct e1000_phy_operations ich8_phy_ops = {
4458         .acquire                = e1000_acquire_swflag_ich8lan,
4459         .check_reset_block      = e1000_check_reset_block_ich8lan,
4460         .commit                 = NULL,
4461         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4462         .get_cable_length       = e1000e_get_cable_length_igp_2,
4463         .read_reg               = e1000e_read_phy_reg_igp,
4464         .release                = e1000_release_swflag_ich8lan,
4465         .reset                  = e1000_phy_hw_reset_ich8lan,
4466         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4467         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4468         .write_reg              = e1000e_write_phy_reg_igp,
4469 };
4470
4471 static const struct e1000_nvm_operations ich8_nvm_ops = {
4472         .acquire                = e1000_acquire_nvm_ich8lan,
4473         .read                   = e1000_read_nvm_ich8lan,
4474         .release                = e1000_release_nvm_ich8lan,
4475         .reload                 = e1000e_reload_nvm_generic,
4476         .update                 = e1000_update_nvm_checksum_ich8lan,
4477         .valid_led_default      = e1000_valid_led_default_ich8lan,
4478         .validate               = e1000_validate_nvm_checksum_ich8lan,
4479         .write                  = e1000_write_nvm_ich8lan,
4480 };
4481
4482 const struct e1000_info e1000_ich8_info = {
4483         .mac                    = e1000_ich8lan,
4484         .flags                  = FLAG_HAS_WOL
4485                                   | FLAG_IS_ICH
4486                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4487                                   | FLAG_HAS_AMT
4488                                   | FLAG_HAS_FLASH
4489                                   | FLAG_APME_IN_WUC,
4490         .pba                    = 8,
4491         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4492         .get_variants           = e1000_get_variants_ich8lan,
4493         .mac_ops                = &ich8_mac_ops,
4494         .phy_ops                = &ich8_phy_ops,
4495         .nvm_ops                = &ich8_nvm_ops,
4496 };
4497
4498 const struct e1000_info e1000_ich9_info = {
4499         .mac                    = e1000_ich9lan,
4500         .flags                  = FLAG_HAS_JUMBO_FRAMES
4501                                   | FLAG_IS_ICH
4502                                   | FLAG_HAS_WOL
4503                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4504                                   | FLAG_HAS_AMT
4505                                   | FLAG_HAS_FLASH
4506                                   | FLAG_APME_IN_WUC,
4507         .pba                    = 18,
4508         .max_hw_frame_size      = DEFAULT_JUMBO,
4509         .get_variants           = e1000_get_variants_ich8lan,
4510         .mac_ops                = &ich8_mac_ops,
4511         .phy_ops                = &ich8_phy_ops,
4512         .nvm_ops                = &ich8_nvm_ops,
4513 };
4514
4515 const struct e1000_info e1000_ich10_info = {
4516         .mac                    = e1000_ich10lan,
4517         .flags                  = FLAG_HAS_JUMBO_FRAMES
4518                                   | FLAG_IS_ICH
4519                                   | FLAG_HAS_WOL
4520                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4521                                   | FLAG_HAS_AMT
4522                                   | FLAG_HAS_FLASH
4523                                   | FLAG_APME_IN_WUC,
4524         .pba                    = 18,
4525         .max_hw_frame_size      = DEFAULT_JUMBO,
4526         .get_variants           = e1000_get_variants_ich8lan,
4527         .mac_ops                = &ich8_mac_ops,
4528         .phy_ops                = &ich8_phy_ops,
4529         .nvm_ops                = &ich8_nvm_ops,
4530 };
4531
4532 const struct e1000_info e1000_pch_info = {
4533         .mac                    = e1000_pchlan,
4534         .flags                  = FLAG_IS_ICH
4535                                   | FLAG_HAS_WOL
4536                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4537                                   | FLAG_HAS_AMT
4538                                   | FLAG_HAS_FLASH
4539                                   | FLAG_HAS_JUMBO_FRAMES
4540                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4541                                   | FLAG_APME_IN_WUC,
4542         .flags2                 = FLAG2_HAS_PHY_STATS,
4543         .pba                    = 26,
4544         .max_hw_frame_size      = 4096,
4545         .get_variants           = e1000_get_variants_ich8lan,
4546         .mac_ops                = &ich8_mac_ops,
4547         .phy_ops                = &ich8_phy_ops,
4548         .nvm_ops                = &ich8_nvm_ops,
4549 };
4550
4551 const struct e1000_info e1000_pch2_info = {
4552         .mac                    = e1000_pch2lan,
4553         .flags                  = FLAG_IS_ICH
4554                                   | FLAG_HAS_WOL
4555                                   | FLAG_HAS_HW_TIMESTAMP
4556                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4557                                   | FLAG_HAS_AMT
4558                                   | FLAG_HAS_FLASH
4559                                   | FLAG_HAS_JUMBO_FRAMES
4560                                   | FLAG_APME_IN_WUC,
4561         .flags2                 = FLAG2_HAS_PHY_STATS
4562                                   | FLAG2_HAS_EEE,
4563         .pba                    = 26,
4564         .max_hw_frame_size      = 9018,
4565         .get_variants           = e1000_get_variants_ich8lan,
4566         .mac_ops                = &ich8_mac_ops,
4567         .phy_ops                = &ich8_phy_ops,
4568         .nvm_ops                = &ich8_nvm_ops,
4569 };
4570
4571 const struct e1000_info e1000_pch_lpt_info = {
4572         .mac                    = e1000_pch_lpt,
4573         .flags                  = FLAG_IS_ICH
4574                                   | FLAG_HAS_WOL
4575                                   | FLAG_HAS_HW_TIMESTAMP
4576                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4577                                   | FLAG_HAS_AMT
4578                                   | FLAG_HAS_FLASH
4579                                   | FLAG_HAS_JUMBO_FRAMES
4580                                   | FLAG_APME_IN_WUC,
4581         .flags2                 = FLAG2_HAS_PHY_STATS
4582                                   | FLAG2_HAS_EEE,
4583         .pba                    = 26,
4584         .max_hw_frame_size      = 9018,
4585         .get_variants           = e1000_get_variants_ich8lan,
4586         .mac_ops                = &ich8_mac_ops,
4587         .phy_ops                = &ich8_phy_ops,
4588         .nvm_ops                = &ich8_nvm_ops,
4589 };