Pileus Git - ~andy/linux/blob - drivers/net/ethernet/freescale/ucc_geth.c

   1 /*
   2  * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *         Li Yang <leoli@freescale.com>
   6  *
   7  * Description:
   8  * QE UCC Gigabit Ethernet Driver
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/slab.h>
  22 #include <linux/stddef.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/mm.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/mii.h>
  32 #include <linux/phy.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/of_address.h>
  35 #include <linux/of_irq.h>
  36 #include <linux/of_mdio.h>
  37 #include <linux/of_net.h>
  38 #include <linux/of_platform.h>
  39
  40 #include <asm/uaccess.h>
  41 #include <asm/irq.h>
  42 #include <asm/io.h>
  43 #include <asm/immap_qe.h>
  44 #include <asm/qe.h>
  45 #include <asm/ucc.h>
  46 #include <asm/ucc_fast.h>
  47 #include <asm/machdep.h>
  48
  49 #include "ucc_geth.h"
  50
  51 #undef DEBUG
  52
  53 #define ugeth_printk(level, format, arg...)  \
  54         printk(level format "\n", ## arg)
  55
  56 #define ugeth_dbg(format, arg...)            \
  57         ugeth_printk(KERN_DEBUG , format , ## arg)
  58
  59 #ifdef UGETH_VERBOSE_DEBUG
  60 #define ugeth_vdbg ugeth_dbg
  61 #else
  62 #define ugeth_vdbg(fmt, args...) do { } while (0)
  63 #endif                          /* UGETH_VERBOSE_DEBUG */
  64 #define UGETH_MSG_DEFAULT       (NETIF_MSG_IFUP << 1 ) - 1
  65
  66
  67 static DEFINE_SPINLOCK(ugeth_lock);
  68
  69 static struct {
  70         u32 msg_enable;
  71 } debug = { -1 };
  72
  73 module_param_named(debug, debug.msg_enable, int, 0);
  74 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
  75
  76 static struct ucc_geth_info ugeth_primary_info = {
  77         .uf_info = {
  78                     .bd_mem_part = MEM_PART_SYSTEM,
  79                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
  80                     .max_rx_buf_length = 1536,
  81                     /* adjusted at startup if max-speed 1000 */
  82                     .urfs = UCC_GETH_URFS_INIT,
  83                     .urfet = UCC_GETH_URFET_INIT,
  84                     .urfset = UCC_GETH_URFSET_INIT,
  85                     .utfs = UCC_GETH_UTFS_INIT,
  86                     .utfet = UCC_GETH_UTFET_INIT,
  87                     .utftt = UCC_GETH_UTFTT_INIT,
  88                     .ufpt = 256,
  89                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
  90                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
  91                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
  92                     .renc = UCC_FAST_RX_ENCODING_NRZ,
  93                     .tcrc = UCC_FAST_16_BIT_CRC,
  94                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
  95                     },
  96         .numQueuesTx = 1,
  97         .numQueuesRx = 1,
  98         .extendedFilteringChainPointer = ((uint32_t) NULL),
  99         .typeorlen = 3072 /*1536 */ ,
 100         .nonBackToBackIfgPart1 = 0x40,
 101         .nonBackToBackIfgPart2 = 0x60,
 102         .miminumInterFrameGapEnforcement = 0x50,
 103         .backToBackInterFrameGap = 0x60,
 104         .mblinterval = 128,
 105         .nortsrbytetime = 5,
 106         .fracsiz = 1,
 107         .strictpriorityq = 0xff,
 108         .altBebTruncation = 0xa,
 109         .excessDefer = 1,
 110         .maxRetransmission = 0xf,
 111         .collisionWindow = 0x37,
 112         .receiveFlowControl = 1,
 113         .transmitFlowControl = 1,
 114         .maxGroupAddrInHash = 4,
 115         .maxIndAddrInHash = 4,
 116         .prel = 7,
 117         .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */
 118         .minFrameLength = 64,
 119         .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */
 120         .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */
 121         .vlantype = 0x8100,
 122         .ecamptr = ((uint32_t) NULL),
 123         .eventRegMask = UCCE_OTHER,
 124         .pausePeriod = 0xf000,
 125         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
 126         .bdRingLenTx = {
 127                         TX_BD_RING_LEN,
 128                         TX_BD_RING_LEN,
 129                         TX_BD_RING_LEN,
 130                         TX_BD_RING_LEN,
 131                         TX_BD_RING_LEN,
 132                         TX_BD_RING_LEN,
 133                         TX_BD_RING_LEN,
 134                         TX_BD_RING_LEN},
 135
 136         .bdRingLenRx = {
 137                         RX_BD_RING_LEN,
 138                         RX_BD_RING_LEN,
 139                         RX_BD_RING_LEN,
 140                         RX_BD_RING_LEN,
 141                         RX_BD_RING_LEN,
 142                         RX_BD_RING_LEN,
 143                         RX_BD_RING_LEN,
 144                         RX_BD_RING_LEN},
 145
 146         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
 147         .largestexternallookupkeysize =
 148             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
 149         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
 150                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
 151                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
 152         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
 153         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
 154         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
 155         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
 156         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
 157         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
 158         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
 159         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 160         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 161 };
 162
 163 static struct ucc_geth_info ugeth_info[8];
 164
 165 #ifdef DEBUG
 166 static void mem_disp(u8 *addr, int size)
 167 {
 168         u8 *i;
 169         int size16Aling = (size >> 4) << 4;
 170         int size4Aling = (size >> 2) << 2;
 171         int notAlign = 0;
 172         if (size % 16)
 173                 notAlign = 1;
 174
 175         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
 176                 printk("0x%08x: %08x %08x %08x %08x\r\n",
 177                        (u32) i,
 178                        *((u32 *) (i)),
 179                        *((u32 *) (i + 4)),
 180                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
 181         if (notAlign == 1)
 182                 printk("0x%08x: ", (u32) i);
 183         for (; (u32) i < (u32) addr + size4Aling; i += 4)
 184                 printk("%08x ", *((u32 *) (i)));
 185         for (; (u32) i < (u32) addr + size; i++)
 186                 printk("%02x", *((i)));
 187         if (notAlign == 1)
 188                 printk("\r\n");
 189 }
 190 #endif /* DEBUG */
 191
 192 static struct list_head *dequeue(struct list_head *lh)
 193 {
 194         unsigned long flags;
 195
 196         spin_lock_irqsave(&ugeth_lock, flags);
 197         if (!list_empty(lh)) {
 198                 struct list_head *node = lh->next;
 199                 list_del(node);
 200                 spin_unlock_irqrestore(&ugeth_lock, flags);
 201                 return node;
 202         } else {
 203                 spin_unlock_irqrestore(&ugeth_lock, flags);
 204                 return NULL;
 205         }
 206 }
 207
 208 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
 209                 u8 __iomem *bd)
 210 {
 211         struct sk_buff *skb;
 212
 213         skb = netdev_alloc_skb(ugeth->ndev,
 214                                ugeth->ug_info->uf_info.max_rx_buf_length +
 215                                UCC_GETH_RX_DATA_BUF_ALIGNMENT);
 216         if (!skb)
 217                 return NULL;
 218
 219         /* We need the data buffer to be aligned properly.  We will reserve
 220          * as many bytes as needed to align the data properly
 221          */
 222         skb_reserve(skb,
 223                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 224                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 225                                               1)));
 226
 227         out_be32(&((struct qe_bd __iomem *)bd)->buf,
 228                       dma_map_single(ugeth->dev,
 229                                      skb->data,
 230                                      ugeth->ug_info->uf_info.max_rx_buf_length +
 231                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
 232                                      DMA_FROM_DEVICE));
 233
 234         out_be32((u32 __iomem *)bd,
 235                         (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
 236
 237         return skb;
 238 }
 239
 240 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
 241 {
 242         u8 __iomem *bd;
 243         u32 bd_status;
 244         struct sk_buff *skb;
 245         int i;
 246
 247         bd = ugeth->p_rx_bd_ring[rxQ];
 248         i = 0;
 249
 250         do {
 251                 bd_status = in_be32((u32 __iomem *)bd);
 252                 skb = get_new_skb(ugeth, bd);
 253
 254                 if (!skb)       /* If can not allocate data buffer,
 255                                 abort. Cleanup will be elsewhere */
 256                         return -ENOMEM;
 257
 258                 ugeth->rx_skbuff[rxQ][i] = skb;
 259
 260                 /* advance the BD pointer */
 261                 bd += sizeof(struct qe_bd);
 262                 i++;
 263         } while (!(bd_status & R_W));
 264
 265         return 0;
 266 }
 267
 268 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
 269                                   u32 *p_start,
 270                                   u8 num_entries,
 271                                   u32 thread_size,
 272                                   u32 thread_alignment,
 273                                   unsigned int risc,
 274                                   int skip_page_for_first_entry)
 275 {
 276         u32 init_enet_offset;
 277         u8 i;
 278         int snum;
 279
 280         for (i = 0; i < num_entries; i++) {
 281                 if ((snum = qe_get_snum()) < 0) {
 282                         if (netif_msg_ifup(ugeth))
 283                                 pr_err("Can not get SNUM\n");
 284                         return snum;
 285                 }
 286                 if ((i == 0) && skip_page_for_first_entry)
 287                 /* First entry of Rx does not have page */
 288                         init_enet_offset = 0;
 289                 else {
 290                         init_enet_offset =
 291                             qe_muram_alloc(thread_size, thread_alignment);
 292                         if (IS_ERR_VALUE(init_enet_offset)) {
 293                                 if (netif_msg_ifup(ugeth))
 294                                         pr_err("Can not allocate DPRAM memory\n");
 295                                 qe_put_snum((u8) snum);
 296                                 return -ENOMEM;
 297                         }
 298                 }
 299                 *(p_start++) =
 300                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
 301                     | risc;
 302         }
 303
 304         return 0;
 305 }
 306
 307 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
 308                                     u32 *p_start,
 309                                     u8 num_entries,
 310                                     unsigned int risc,
 311                                     int skip_page_for_first_entry)
 312 {
 313         u32 init_enet_offset;
 314         u8 i;
 315         int snum;
 316
 317         for (i = 0; i < num_entries; i++) {
 318                 u32 val = *p_start;
 319
 320                 /* Check that this entry was actually valid --
 321                 needed in case failed in allocations */
 322                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
 323                         snum =
 324                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
 325                             ENET_INIT_PARAM_SNUM_SHIFT;
 326                         qe_put_snum((u8) snum);
 327                         if (!((i == 0) && skip_page_for_first_entry)) {
 328                         /* First entry of Rx does not have page */
 329                                 init_enet_offset =
 330                                     (val & ENET_INIT_PARAM_PTR_MASK);
 331                                 qe_muram_free(init_enet_offset);
 332                         }
 333                         *p_start++ = 0;
 334                 }
 335         }
 336
 337         return 0;
 338 }
 339
 340 #ifdef DEBUG
 341 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
 342                                   u32 __iomem *p_start,
 343                                   u8 num_entries,
 344                                   u32 thread_size,
 345                                   unsigned int risc,
 346                                   int skip_page_for_first_entry)
 347 {
 348         u32 init_enet_offset;
 349         u8 i;
 350         int snum;
 351
 352         for (i = 0; i < num_entries; i++) {
 353                 u32 val = in_be32(p_start);
 354
 355                 /* Check that this entry was actually valid --
 356                 needed in case failed in allocations */
 357                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
 358                         snum =
 359                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
 360                             ENET_INIT_PARAM_SNUM_SHIFT;
 361                         qe_put_snum((u8) snum);
 362                         if (!((i == 0) && skip_page_for_first_entry)) {
 363                         /* First entry of Rx does not have page */
 364                                 init_enet_offset =
 365                                     (in_be32(p_start) &
 366                                      ENET_INIT_PARAM_PTR_MASK);
 367                                 pr_info("Init enet entry %d:\n", i);
 368                                 pr_info("Base address: 0x%08x\n",
 369                                         (u32)qe_muram_addr(init_enet_offset));
 370                                 mem_disp(qe_muram_addr(init_enet_offset),
 371                                          thread_size);
 372                         }
 373                         p_start++;
 374                 }
 375         }
 376
 377         return 0;
 378 }
 379 #endif
 380
 381 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
 382 {
 383         kfree(enet_addr_cont);
 384 }
 385
 386 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
 387 {
 388         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
 389         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
 390         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
 391 }
 392
 393 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
 394 {
 395         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
 396
 397         if (paddr_num >= NUM_OF_PADDRS) {
 398                 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num);
 399                 return -EINVAL;
 400         }
 401
 402         p_82xx_addr_filt =
 403             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
 404             addressfiltering;
 405
 406         /* Writing address ff.ff.ff.ff.ff.ff disables address
 407         recognition for this register */
 408         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
 409         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
 410         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
 411
 412         return 0;
 413 }
 414
 415 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
 416                                 u8 *p_enet_addr)
 417 {
 418         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
 419         u32 cecr_subblock;
 420
 421         p_82xx_addr_filt =
 422             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
 423             addressfiltering;
 424
 425         cecr_subblock =
 426             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
 427
 428         /* Ethernet frames are defined in Little Endian mode,
 429         therefore to insert */
 430         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
 431
 432         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
 433
 434         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
 435                      QE_CR_PROTOCOL_ETHERNET, 0);
 436 }
 437
 438 #ifdef DEBUG
 439 static void get_statistics(struct ucc_geth_private *ugeth,
 440                            struct ucc_geth_tx_firmware_statistics *
 441                            tx_firmware_statistics,
 442                            struct ucc_geth_rx_firmware_statistics *
 443                            rx_firmware_statistics,
 444                            struct ucc_geth_hardware_statistics *hardware_statistics)
 445 {
 446         struct ucc_fast __iomem *uf_regs;
 447         struct ucc_geth __iomem *ug_regs;
 448         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
 449         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
 450
 451         ug_regs = ugeth->ug_regs;
 452         uf_regs = (struct ucc_fast __iomem *) ug_regs;
 453         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
 454         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
 455
 456         /* Tx firmware only if user handed pointer and driver actually
 457         gathers Tx firmware statistics */
 458         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
 459                 tx_firmware_statistics->sicoltx =
 460                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
 461                 tx_firmware_statistics->mulcoltx =
 462                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
 463                 tx_firmware_statistics->latecoltxfr =
 464                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
 465                 tx_firmware_statistics->frabortduecol =
 466                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
 467                 tx_firmware_statistics->frlostinmactxer =
 468                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
 469                 tx_firmware_statistics->carriersenseertx =
 470                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
 471                 tx_firmware_statistics->frtxok =
 472                     in_be32(&p_tx_fw_statistics_pram->frtxok);
 473                 tx_firmware_statistics->txfrexcessivedefer =
 474                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
 475                 tx_firmware_statistics->txpkts256 =
 476                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
 477                 tx_firmware_statistics->txpkts512 =
 478                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
 479                 tx_firmware_statistics->txpkts1024 =
 480                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
 481                 tx_firmware_statistics->txpktsjumbo =
 482                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
 483         }
 484
 485         /* Rx firmware only if user handed pointer and driver actually
 486          * gathers Rx firmware statistics */
 487         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
 488                 int i;
 489                 rx_firmware_statistics->frrxfcser =
 490                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
 491                 rx_firmware_statistics->fraligner =
 492                     in_be32(&p_rx_fw_statistics_pram->fraligner);
 493                 rx_firmware_statistics->inrangelenrxer =
 494                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
 495                 rx_firmware_statistics->outrangelenrxer =
 496                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
 497                 rx_firmware_statistics->frtoolong =
 498                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
 499                 rx_firmware_statistics->runt =
 500                     in_be32(&p_rx_fw_statistics_pram->runt);
 501                 rx_firmware_statistics->verylongevent =
 502                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
 503                 rx_firmware_statistics->symbolerror =
 504                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
 505                 rx_firmware_statistics->dropbsy =
 506                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
 507                 for (i = 0; i < 0x8; i++)
 508                         rx_firmware_statistics->res0[i] =
 509                             p_rx_fw_statistics_pram->res0[i];
 510                 rx_firmware_statistics->mismatchdrop =
 511                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
 512                 rx_firmware_statistics->underpkts =
 513                     in_be32(&p_rx_fw_statistics_pram->underpkts);
 514                 rx_firmware_statistics->pkts256 =
 515                     in_be32(&p_rx_fw_statistics_pram->pkts256);
 516                 rx_firmware_statistics->pkts512 =
 517                     in_be32(&p_rx_fw_statistics_pram->pkts512);
 518                 rx_firmware_statistics->pkts1024 =
 519                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
 520                 rx_firmware_statistics->pktsjumbo =
 521                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
 522                 rx_firmware_statistics->frlossinmacer =
 523                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
 524                 rx_firmware_statistics->pausefr =
 525                     in_be32(&p_rx_fw_statistics_pram->pausefr);
 526                 for (i = 0; i < 0x4; i++)
 527                         rx_firmware_statistics->res1[i] =
 528                             p_rx_fw_statistics_pram->res1[i];
 529                 rx_firmware_statistics->removevlan =
 530                     in_be32(&p_rx_fw_statistics_pram->removevlan);
 531                 rx_firmware_statistics->replacevlan =
 532                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
 533                 rx_firmware_statistics->insertvlan =
 534                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
 535         }
 536
 537         /* Hardware only if user handed pointer and driver actually
 538         gathers hardware statistics */
 539         if (hardware_statistics &&
 540             (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
 541                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
 542                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
 543                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
 544                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
 545                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
 546                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
 547                 hardware_statistics->txok = in_be32(&ug_regs->txok);
 548                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
 549                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
 550                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
 551                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
 552                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
 553                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
 554                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
 555                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
 556         }
 557 }
 558
 559 static void dump_bds(struct ucc_geth_private *ugeth)
 560 {
 561         int i;
 562         int length;
 563
 564         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 565                 if (ugeth->p_tx_bd_ring[i]) {
 566                         length =
 567                             (ugeth->ug_info->bdRingLenTx[i] *
 568                              sizeof(struct qe_bd));
 569                         pr_info("TX BDs[%d]\n", i);
 570                         mem_disp(ugeth->p_tx_bd_ring[i], length);
 571                 }
 572         }
 573         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 574                 if (ugeth->p_rx_bd_ring[i]) {
 575                         length =
 576                             (ugeth->ug_info->bdRingLenRx[i] *
 577                              sizeof(struct qe_bd));
 578                         pr_info("RX BDs[%d]\n", i);
 579                         mem_disp(ugeth->p_rx_bd_ring[i], length);
 580                 }
 581         }
 582 }
 583
 584 static void dump_regs(struct ucc_geth_private *ugeth)
 585 {
 586         int i;
 587
 588         pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1);
 589         pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs);
 590
 591         pr_info("maccfg1    : addr - 0x%08x, val - 0x%08x\n",
 592                 (u32)&ugeth->ug_regs->maccfg1,
 593                 in_be32(&ugeth->ug_regs->maccfg1));
 594         pr_info("maccfg2    : addr - 0x%08x, val - 0x%08x\n",
 595                 (u32)&ugeth->ug_regs->maccfg2,
 596                 in_be32(&ugeth->ug_regs->maccfg2));
 597         pr_info("ipgifg     : addr - 0x%08x, val - 0x%08x\n",
 598                 (u32)&ugeth->ug_regs->ipgifg,
 599                 in_be32(&ugeth->ug_regs->ipgifg));
 600         pr_info("hafdup     : addr - 0x%08x, val - 0x%08x\n",
 601                 (u32)&ugeth->ug_regs->hafdup,
 602                 in_be32(&ugeth->ug_regs->hafdup));
 603         pr_info("ifctl      : addr - 0x%08x, val - 0x%08x\n",
 604                 (u32)&ugeth->ug_regs->ifctl,
 605                 in_be32(&ugeth->ug_regs->ifctl));
 606         pr_info("ifstat     : addr - 0x%08x, val - 0x%08x\n",
 607                 (u32)&ugeth->ug_regs->ifstat,
 608                 in_be32(&ugeth->ug_regs->ifstat));
 609         pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n",
 610                 (u32)&ugeth->ug_regs->macstnaddr1,
 611                 in_be32(&ugeth->ug_regs->macstnaddr1));
 612         pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n",
 613                 (u32)&ugeth->ug_regs->macstnaddr2,
 614                 in_be32(&ugeth->ug_regs->macstnaddr2));
 615         pr_info("uempr      : addr - 0x%08x, val - 0x%08x\n",
 616                 (u32)&ugeth->ug_regs->uempr,
 617                 in_be32(&ugeth->ug_regs->uempr));
 618         pr_info("utbipar    : addr - 0x%08x, val - 0x%08x\n",
 619                 (u32)&ugeth->ug_regs->utbipar,
 620                 in_be32(&ugeth->ug_regs->utbipar));
 621         pr_info("uescr      : addr - 0x%08x, val - 0x%04x\n",
 622                 (u32)&ugeth->ug_regs->uescr,
 623                 in_be16(&ugeth->ug_regs->uescr));
 624         pr_info("tx64       : addr - 0x%08x, val - 0x%08x\n",
 625                 (u32)&ugeth->ug_regs->tx64,
 626                 in_be32(&ugeth->ug_regs->tx64));
 627         pr_info("tx127      : addr - 0x%08x, val - 0x%08x\n",
 628                 (u32)&ugeth->ug_regs->tx127,
 629                 in_be32(&ugeth->ug_regs->tx127));
 630         pr_info("tx255      : addr - 0x%08x, val - 0x%08x\n",
 631                 (u32)&ugeth->ug_regs->tx255,
 632                 in_be32(&ugeth->ug_regs->tx255));
 633         pr_info("rx64       : addr - 0x%08x, val - 0x%08x\n",
 634                 (u32)&ugeth->ug_regs->rx64,
 635                 in_be32(&ugeth->ug_regs->rx64));
 636         pr_info("rx127      : addr - 0x%08x, val - 0x%08x\n",
 637                 (u32)&ugeth->ug_regs->rx127,
 638                 in_be32(&ugeth->ug_regs->rx127));
 639         pr_info("rx255      : addr - 0x%08x, val - 0x%08x\n",
 640                 (u32)&ugeth->ug_regs->rx255,
 641                 in_be32(&ugeth->ug_regs->rx255));
 642         pr_info("txok       : addr - 0x%08x, val - 0x%08x\n",
 643                 (u32)&ugeth->ug_regs->txok,
 644                 in_be32(&ugeth->ug_regs->txok));
 645         pr_info("txcf       : addr - 0x%08x, val - 0x%04x\n",
 646                 (u32)&ugeth->ug_regs->txcf,
 647                 in_be16(&ugeth->ug_regs->txcf));
 648         pr_info("tmca       : addr - 0x%08x, val - 0x%08x\n",
 649                 (u32)&ugeth->ug_regs->tmca,
 650                 in_be32(&ugeth->ug_regs->tmca));
 651         pr_info("tbca       : addr - 0x%08x, val - 0x%08x\n",
 652                 (u32)&ugeth->ug_regs->tbca,
 653                 in_be32(&ugeth->ug_regs->tbca));
 654         pr_info("rxfok      : addr - 0x%08x, val - 0x%08x\n",
 655                 (u32)&ugeth->ug_regs->rxfok,
 656                 in_be32(&ugeth->ug_regs->rxfok));
 657         pr_info("rxbok      : addr - 0x%08x, val - 0x%08x\n",
 658                 (u32)&ugeth->ug_regs->rxbok,
 659                 in_be32(&ugeth->ug_regs->rxbok));
 660         pr_info("rbyt       : addr - 0x%08x, val - 0x%08x\n",
 661                 (u32)&ugeth->ug_regs->rbyt,
 662                 in_be32(&ugeth->ug_regs->rbyt));
 663         pr_info("rmca       : addr - 0x%08x, val - 0x%08x\n",
 664                 (u32)&ugeth->ug_regs->rmca,
 665                 in_be32(&ugeth->ug_regs->rmca));
 666         pr_info("rbca       : addr - 0x%08x, val - 0x%08x\n",
 667                 (u32)&ugeth->ug_regs->rbca,
 668                 in_be32(&ugeth->ug_regs->rbca));
 669         pr_info("scar       : addr - 0x%08x, val - 0x%08x\n",
 670                 (u32)&ugeth->ug_regs->scar,
 671                 in_be32(&ugeth->ug_regs->scar));
 672         pr_info("scam       : addr - 0x%08x, val - 0x%08x\n",
 673                 (u32)&ugeth->ug_regs->scam,
 674                 in_be32(&ugeth->ug_regs->scam));
 675
 676         if (ugeth->p_thread_data_tx) {
 677                 int numThreadsTxNumerical;
 678                 switch (ugeth->ug_info->numThreadsTx) {
 679                 case UCC_GETH_NUM_OF_THREADS_1:
 680                         numThreadsTxNumerical = 1;
 681                         break;
 682                 case UCC_GETH_NUM_OF_THREADS_2:
 683                         numThreadsTxNumerical = 2;
 684                         break;
 685                 case UCC_GETH_NUM_OF_THREADS_4:
 686                         numThreadsTxNumerical = 4;
 687                         break;
 688                 case UCC_GETH_NUM_OF_THREADS_6:
 689                         numThreadsTxNumerical = 6;
 690                         break;
 691                 case UCC_GETH_NUM_OF_THREADS_8:
 692                         numThreadsTxNumerical = 8;
 693                         break;
 694                 default:
 695                         numThreadsTxNumerical = 0;
 696                         break;
 697                 }
 698
 699                 pr_info("Thread data TXs:\n");
 700                 pr_info("Base address: 0x%08x\n",
 701                         (u32)ugeth->p_thread_data_tx);
 702                 for (i = 0; i < numThreadsTxNumerical; i++) {
 703                         pr_info("Thread data TX[%d]:\n", i);
 704                         pr_info("Base address: 0x%08x\n",
 705                                 (u32)&ugeth->p_thread_data_tx[i]);
 706                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
 707                                  sizeof(struct ucc_geth_thread_data_tx));
 708                 }
 709         }
 710         if (ugeth->p_thread_data_rx) {
 711                 int numThreadsRxNumerical;
 712                 switch (ugeth->ug_info->numThreadsRx) {
 713                 case UCC_GETH_NUM_OF_THREADS_1:
 714                         numThreadsRxNumerical = 1;
 715                         break;
 716                 case UCC_GETH_NUM_OF_THREADS_2:
 717                         numThreadsRxNumerical = 2;
 718                         break;
 719                 case UCC_GETH_NUM_OF_THREADS_4:
 720                         numThreadsRxNumerical = 4;
 721                         break;
 722                 case UCC_GETH_NUM_OF_THREADS_6:
 723                         numThreadsRxNumerical = 6;
 724                         break;
 725                 case UCC_GETH_NUM_OF_THREADS_8:
 726                         numThreadsRxNumerical = 8;
 727                         break;
 728                 default:
 729                         numThreadsRxNumerical = 0;
 730                         break;
 731                 }
 732
 733                 pr_info("Thread data RX:\n");
 734                 pr_info("Base address: 0x%08x\n",
 735                         (u32)ugeth->p_thread_data_rx);
 736                 for (i = 0; i < numThreadsRxNumerical; i++) {
 737                         pr_info("Thread data RX[%d]:\n", i);
 738                         pr_info("Base address: 0x%08x\n",
 739                                 (u32)&ugeth->p_thread_data_rx[i]);
 740                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
 741                                  sizeof(struct ucc_geth_thread_data_rx));
 742                 }
 743         }
 744         if (ugeth->p_exf_glbl_param) {
 745                 pr_info("EXF global param:\n");
 746                 pr_info("Base address: 0x%08x\n",
 747                         (u32)ugeth->p_exf_glbl_param);
 748                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
 749                          sizeof(*ugeth->p_exf_glbl_param));
 750         }
 751         if (ugeth->p_tx_glbl_pram) {
 752                 pr_info("TX global param:\n");
 753                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram);
 754                 pr_info("temoder      : addr - 0x%08x, val - 0x%04x\n",
 755                         (u32)&ugeth->p_tx_glbl_pram->temoder,
 756                         in_be16(&ugeth->p_tx_glbl_pram->temoder));
 757                pr_info("sqptr        : addr - 0x%08x, val - 0x%08x\n",
 758                         (u32)&ugeth->p_tx_glbl_pram->sqptr,
 759                         in_be32(&ugeth->p_tx_glbl_pram->sqptr));
 760                 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n",
 761                         (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer,
 762                         in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer));
 763                 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n",
 764                         (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr,
 765                         in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
 766                 pr_info("tstate       : addr - 0x%08x, val - 0x%08x\n",
 767                         (u32)&ugeth->p_tx_glbl_pram->tstate,
 768                         in_be32(&ugeth->p_tx_glbl_pram->tstate));
 769                 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n",
 770                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[0],
 771                         ugeth->p_tx_glbl_pram->iphoffset[0]);
 772                 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n",
 773                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[1],
 774                         ugeth->p_tx_glbl_pram->iphoffset[1]);
 775                 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n",
 776                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[2],
 777                         ugeth->p_tx_glbl_pram->iphoffset[2]);
 778                 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n",
 779                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[3],
 780                         ugeth->p_tx_glbl_pram->iphoffset[3]);
 781                 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n",
 782                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[4],
 783                         ugeth->p_tx_glbl_pram->iphoffset[4]);
 784                 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n",
 785                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[5],
 786                         ugeth->p_tx_glbl_pram->iphoffset[5]);
 787                 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n",
 788                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[6],
 789                         ugeth->p_tx_glbl_pram->iphoffset[6]);
 790                 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n",
 791                         (u32)&ugeth->p_tx_glbl_pram->iphoffset[7],
 792                         ugeth->p_tx_glbl_pram->iphoffset[7]);
 793                 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n",
 794                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[0],
 795                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
 796                 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n",
 797                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[1],
 798                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
 799                 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n",
 800                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[2],
 801                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
 802                 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n",
 803                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[3],
 804                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
 805                 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n",
 806                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[4],
 807                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
 808                 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n",
 809                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[5],
 810                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
 811                 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n",
 812                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[6],
 813                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
 814                 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n",
 815                         (u32)&ugeth->p_tx_glbl_pram->vtagtable[7],
 816                         in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
 817                 pr_info("tqptr        : addr - 0x%08x, val - 0x%08x\n",
 818                         (u32)&ugeth->p_tx_glbl_pram->tqptr,
 819                         in_be32(&ugeth->p_tx_glbl_pram->tqptr));
 820         }
 821         if (ugeth->p_rx_glbl_pram) {
 822                 pr_info("RX global param:\n");
 823                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram);
 824                 pr_info("remoder         : addr - 0x%08x, val - 0x%08x\n",
 825                         (u32)&ugeth->p_rx_glbl_pram->remoder,
 826                         in_be32(&ugeth->p_rx_glbl_pram->remoder));
 827                 pr_info("rqptr           : addr - 0x%08x, val - 0x%08x\n",
 828                         (u32)&ugeth->p_rx_glbl_pram->rqptr,
 829                         in_be32(&ugeth->p_rx_glbl_pram->rqptr));
 830                 pr_info("typeorlen       : addr - 0x%08x, val - 0x%04x\n",
 831                         (u32)&ugeth->p_rx_glbl_pram->typeorlen,
 832                         in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
 833                 pr_info("rxgstpack       : addr - 0x%08x, val - 0x%02x\n",
 834                         (u32)&ugeth->p_rx_glbl_pram->rxgstpack,
 835                         ugeth->p_rx_glbl_pram->rxgstpack);
 836                 pr_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x\n",
 837                         (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
 838                         in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
 839                 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n",
 840                         (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr,
 841                         in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
 842                 pr_info("rstate          : addr - 0x%08x, val - 0x%02x\n",
 843                         (u32)&ugeth->p_rx_glbl_pram->rstate,
 844                         ugeth->p_rx_glbl_pram->rstate);
 845                 pr_info("mrblr           : addr - 0x%08x, val - 0x%04x\n",
 846                         (u32)&ugeth->p_rx_glbl_pram->mrblr,
 847                         in_be16(&ugeth->p_rx_glbl_pram->mrblr));
 848                 pr_info("rbdqptr         : addr - 0x%08x, val - 0x%08x\n",
 849                         (u32)&ugeth->p_rx_glbl_pram->rbdqptr,
 850                         in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
 851                 pr_info("mflr            : addr - 0x%08x, val - 0x%04x\n",
 852                         (u32)&ugeth->p_rx_glbl_pram->mflr,
 853                         in_be16(&ugeth->p_rx_glbl_pram->mflr));
 854                 pr_info("minflr          : addr - 0x%08x, val - 0x%04x\n",
 855                         (u32)&ugeth->p_rx_glbl_pram->minflr,
 856                         in_be16(&ugeth->p_rx_glbl_pram->minflr));
 857                 pr_info("maxd1           : addr - 0x%08x, val - 0x%04x\n",
 858                         (u32)&ugeth->p_rx_glbl_pram->maxd1,
 859                         in_be16(&ugeth->p_rx_glbl_pram->maxd1));
 860                 pr_info("maxd2           : addr - 0x%08x, val - 0x%04x\n",
 861                         (u32)&ugeth->p_rx_glbl_pram->maxd2,
 862                         in_be16(&ugeth->p_rx_glbl_pram->maxd2));
 863                 pr_info("ecamptr         : addr - 0x%08x, val - 0x%08x\n",
 864                         (u32)&ugeth->p_rx_glbl_pram->ecamptr,
 865                         in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
 866                 pr_info("l2qt            : addr - 0x%08x, val - 0x%08x\n",
 867                         (u32)&ugeth->p_rx_glbl_pram->l2qt,
 868                         in_be32(&ugeth->p_rx_glbl_pram->l2qt));
 869                 pr_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x\n",
 870                         (u32)&ugeth->p_rx_glbl_pram->l3qt[0],
 871                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
 872                 pr_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x\n",
 873                         (u32)&ugeth->p_rx_glbl_pram->l3qt[1],
 874                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
 875                 pr_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x\n",
 876                         (u32)&ugeth->p_rx_glbl_pram->l3qt[2],
 877                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
 878                 pr_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x\n",
 879                         (u32)&ugeth->p_rx_glbl_pram->l3qt[3],
 880                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
 881                 pr_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x\n",
 882                         (u32)&ugeth->p_rx_glbl_pram->l3qt[4],
 883                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
 884                 pr_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x\n",
 885                         (u32)&ugeth->p_rx_glbl_pram->l3qt[5],
 886                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
 887                 pr_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x\n",
 888                         (u32)&ugeth->p_rx_glbl_pram->l3qt[6],
 889                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
 890                 pr_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x\n",
 891                         (u32)&ugeth->p_rx_glbl_pram->l3qt[7],
 892                         in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
 893                 pr_info("vlantype        : addr - 0x%08x, val - 0x%04x\n",
 894                         (u32)&ugeth->p_rx_glbl_pram->vlantype,
 895                         in_be16(&ugeth->p_rx_glbl_pram->vlantype));
 896                 pr_info("vlantci         : addr - 0x%08x, val - 0x%04x\n",
 897                         (u32)&ugeth->p_rx_glbl_pram->vlantci,
 898                         in_be16(&ugeth->p_rx_glbl_pram->vlantci));
 899                 for (i = 0; i < 64; i++)
 900                         pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n",
 901                                 i,
 902                                 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i],
 903                                 ugeth->p_rx_glbl_pram->addressfiltering[i]);
 904                 pr_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x\n",
 905                         (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam,
 906                         in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
 907         }
 908         if (ugeth->p_send_q_mem_reg) {
 909                 pr_info("Send Q memory registers:\n");
 910                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg);
 911                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 912                         pr_info("SQQD[%d]:\n", i);
 913                         pr_info("Base address: 0x%08x\n",
 914                                 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]);
 915                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
 916                                  sizeof(struct ucc_geth_send_queue_qd));
 917                 }
 918         }
 919         if (ugeth->p_scheduler) {
 920                 pr_info("Scheduler:\n");
 921                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler);
 922                 mem_disp((u8 *) ugeth->p_scheduler,
 923                          sizeof(*ugeth->p_scheduler));
 924         }
 925         if (ugeth->p_tx_fw_statistics_pram) {
 926                 pr_info("TX FW statistics pram:\n");
 927                 pr_info("Base address: 0x%08x\n",
 928                         (u32)ugeth->p_tx_fw_statistics_pram);
 929                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
 930                          sizeof(*ugeth->p_tx_fw_statistics_pram));
 931         }
 932         if (ugeth->p_rx_fw_statistics_pram) {
 933                 pr_info("RX FW statistics pram:\n");
 934                 pr_info("Base address: 0x%08x\n",
 935                         (u32)ugeth->p_rx_fw_statistics_pram);
 936                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
 937                          sizeof(*ugeth->p_rx_fw_statistics_pram));
 938         }
 939         if (ugeth->p_rx_irq_coalescing_tbl) {
 940                 pr_info("RX IRQ coalescing tables:\n");
 941                 pr_info("Base address: 0x%08x\n",
 942                         (u32)ugeth->p_rx_irq_coalescing_tbl);
 943                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 944                         pr_info("RX IRQ coalescing table entry[%d]:\n", i);
 945                         pr_info("Base address: 0x%08x\n",
 946                                 (u32)&ugeth->p_rx_irq_coalescing_tbl->
 947                                 coalescingentry[i]);
 948                         pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n",
 949                                 (u32)&ugeth->p_rx_irq_coalescing_tbl->
 950                                 coalescingentry[i].interruptcoalescingmaxvalue,
 951                                 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
 952                                         coalescingentry[i].
 953                                         interruptcoalescingmaxvalue));
 954                         pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n",
 955                                 (u32)&ugeth->p_rx_irq_coalescing_tbl->
 956                                 coalescingentry[i].interruptcoalescingcounter,
 957                                 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
 958                                         coalescingentry[i].
 959                                         interruptcoalescingcounter));
 960                 }
 961         }
 962         if (ugeth->p_rx_bd_qs_tbl) {
 963                 pr_info("RX BD QS tables:\n");
 964                 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl);
 965                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 966                         pr_info("RX BD QS table[%d]:\n", i);
 967                         pr_info("Base address: 0x%08x\n",
 968                                 (u32)&ugeth->p_rx_bd_qs_tbl[i]);
 969                         pr_info("bdbaseptr        : addr - 0x%08x, val - 0x%08x\n",
 970                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
 971                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
 972                         pr_info("bdptr            : addr - 0x%08x, val - 0x%08x\n",
 973                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr,
 974                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
 975                         pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n",
 976                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
 977                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
 978                                         externalbdbaseptr));
 979                         pr_info("externalbdptr    : addr - 0x%08x, val - 0x%08x\n",
 980                                 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
 981                                 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
 982                         pr_info("ucode RX Prefetched BDs:\n");
 983                         pr_info("Base address: 0x%08x\n",
 984                                 (u32)qe_muram_addr(in_be32
 985                                                    (&ugeth->p_rx_bd_qs_tbl[i].
 986                                                     bdbaseptr)));
 987                         mem_disp((u8 *)
 988                                  qe_muram_addr(in_be32
 989                                                (&ugeth->p_rx_bd_qs_tbl[i].
 990                                                 bdbaseptr)),
 991                                  sizeof(struct ucc_geth_rx_prefetched_bds));
 992                 }
 993         }
 994         if (ugeth->p_init_enet_param_shadow) {
 995                 int size;
 996                 pr_info("Init enet param shadow:\n");
 997                 pr_info("Base address: 0x%08x\n",
 998                         (u32) ugeth->p_init_enet_param_shadow);
 999                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1000                          sizeof(*ugeth->p_init_enet_param_shadow));
1001
1002                 size = sizeof(struct ucc_geth_thread_rx_pram);
1003                 if (ugeth->ug_info->rxExtendedFiltering) {
1004                         size +=
1005                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1006                         if (ugeth->ug_info->largestexternallookupkeysize ==
1007                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1008                                 size +=
1009                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1010                         if (ugeth->ug_info->largestexternallookupkeysize ==
1011                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1012                                 size +=
1013                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1014                 }
1015
1016                 dump_init_enet_entries(ugeth,
1017                                        &(ugeth->p_init_enet_param_shadow->
1018                                          txthread[0]),
1019                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1020                                        sizeof(struct ucc_geth_thread_tx_pram),
1021                                        ugeth->ug_info->riscTx, 0);
1022                 dump_init_enet_entries(ugeth,
1023                                        &(ugeth->p_init_enet_param_shadow->
1024                                          rxthread[0]),
1025                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1026                                        ugeth->ug_info->riscRx, 1);
1027         }
1028 }
1029 #endif /* DEBUG */
1030
1031 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1032                                   u32 __iomem *maccfg1_register,
1033                                   u32 __iomem *maccfg2_register)
1034 {
1035         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1036         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1037         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1038 }
1039
1040 static int init_half_duplex_params(int alt_beb,
1041                                    int back_pressure_no_backoff,
1042                                    int no_backoff,
1043                                    int excess_defer,
1044                                    u8 alt_beb_truncation,
1045                                    u8 max_retransmissions,
1046                                    u8 collision_window,
1047                                    u32 __iomem *hafdup_register)
1048 {
1049         u32 value = 0;
1050
1051         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1052             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1053             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1054                 return -EINVAL;
1055
1056         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1057
1058         if (alt_beb)
1059                 value |= HALFDUP_ALT_BEB;
1060         if (back_pressure_no_backoff)
1061                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1062         if (no_backoff)
1063                 value |= HALFDUP_NO_BACKOFF;
1064         if (excess_defer)
1065                 value |= HALFDUP_EXCESSIVE_DEFER;
1066
1067         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1068
1069         value |= collision_window;
1070
1071         out_be32(hafdup_register, value);
1072         return 0;
1073 }
1074
1075 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1076                                        u8 non_btb_ipg,
1077                                        u8 min_ifg,
1078                                        u8 btb_ipg,
1079                                        u32 __iomem *ipgifg_register)
1080 {
1081         u32 value = 0;
1082
1083         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1084         IPG part 2 */
1085         if (non_btb_cs_ipg > non_btb_ipg)
1086                 return -EINVAL;
1087
1088         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1089             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1090             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1091             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1092                 return -EINVAL;
1093
1094         value |=
1095             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1096              IPGIFG_NBTB_CS_IPG_MASK);
1097         value |=
1098             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1099              IPGIFG_NBTB_IPG_MASK);
1100         value |=
1101             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1102              IPGIFG_MIN_IFG_MASK);
1103         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1104
1105         out_be32(ipgifg_register, value);
1106         return 0;
1107 }
1108
1109 int init_flow_control_params(u32 automatic_flow_control_mode,
1110                                     int rx_flow_control_enable,
1111                                     int tx_flow_control_enable,
1112                                     u16 pause_period,
1113                                     u16 extension_field,
1114                                     u32 __iomem *upsmr_register,
1115                                     u32 __iomem *uempr_register,
1116                                     u32 __iomem *maccfg1_register)
1117 {
1118         u32 value = 0;
1119
1120         /* Set UEMPR register */
1121         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1122         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1123         out_be32(uempr_register, value);
1124
1125         /* Set UPSMR register */
1126         setbits32(upsmr_register, automatic_flow_control_mode);
1127
1128         value = in_be32(maccfg1_register);
1129         if (rx_flow_control_enable)
1130                 value |= MACCFG1_FLOW_RX;
1131         if (tx_flow_control_enable)
1132                 value |= MACCFG1_FLOW_TX;
1133         out_be32(maccfg1_register, value);
1134
1135         return 0;
1136 }
1137
1138 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1139                                              int auto_zero_hardware_statistics,
1140                                              u32 __iomem *upsmr_register,
1141                                              u16 __iomem *uescr_register)
1142 {
1143         u16 uescr_value = 0;
1144
1145         /* Enable hardware statistics gathering if requested */
1146         if (enable_hardware_statistics)
1147                 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1148
1149         /* Clear hardware statistics counters */
1150         uescr_value = in_be16(uescr_register);
1151         uescr_value |= UESCR_CLRCNT;
1152         /* Automatically zero hardware statistics counters on read,
1153         if requested */
1154         if (auto_zero_hardware_statistics)
1155                 uescr_value |= UESCR_AUTOZ;
1156         out_be16(uescr_register, uescr_value);
1157
1158         return 0;
1159 }
1160
1161 static int init_firmware_statistics_gathering_mode(int
1162                 enable_tx_firmware_statistics,
1163                 int enable_rx_firmware_statistics,
1164                 u32 __iomem *tx_rmon_base_ptr,
1165                 u32 tx_firmware_statistics_structure_address,
1166                 u32 __iomem *rx_rmon_base_ptr,
1167                 u32 rx_firmware_statistics_structure_address,
1168                 u16 __iomem *temoder_register,
1169                 u32 __iomem *remoder_register)
1170 {
1171         /* Note: this function does not check if */
1172         /* the parameters it receives are NULL   */
1173
1174         if (enable_tx_firmware_statistics) {
1175                 out_be32(tx_rmon_base_ptr,
1176                          tx_firmware_statistics_structure_address);
1177                 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1178         }
1179
1180         if (enable_rx_firmware_statistics) {
1181                 out_be32(rx_rmon_base_ptr,
1182                          rx_firmware_statistics_structure_address);
1183                 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int init_mac_station_addr_regs(u8 address_byte_0,
1190                                       u8 address_byte_1,
1191                                       u8 address_byte_2,
1192                                       u8 address_byte_3,
1193                                       u8 address_byte_4,
1194                                       u8 address_byte_5,
1195                                       u32 __iomem *macstnaddr1_register,
1196                                       u32 __iomem *macstnaddr2_register)
1197 {
1198         u32 value = 0;
1199
1200         /* Example: for a station address of 0x12345678ABCD, */
1201         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1202
1203         /* MACSTNADDR1 Register: */
1204
1205         /* 0                      7   8                      15  */
1206         /* station address byte 5     station address byte 4     */
1207         /* 16                     23  24                     31  */
1208         /* station address byte 3     station address byte 2     */
1209         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1210         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1211         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1212         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1213
1214         out_be32(macstnaddr1_register, value);
1215
1216         /* MACSTNADDR2 Register: */
1217
1218         /* 0                      7   8                      15  */
1219         /* station address byte 1     station address byte 0     */
1220         /* 16                     23  24                     31  */
1221         /*         reserved                   reserved           */
1222         value = 0;
1223         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1224         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1225
1226         out_be32(macstnaddr2_register, value);
1227
1228         return 0;
1229 }
1230
1231 static int init_check_frame_length_mode(int length_check,
1232                                         u32 __iomem *maccfg2_register)
1233 {
1234         u32 value = 0;
1235
1236         value = in_be32(maccfg2_register);
1237
1238         if (length_check)
1239                 value |= MACCFG2_LC;
1240         else
1241                 value &= ~MACCFG2_LC;
1242
1243         out_be32(maccfg2_register, value);
1244         return 0;
1245 }
1246
1247 static int init_preamble_length(u8 preamble_length,
1248                                 u32 __iomem *maccfg2_register)
1249 {
1250         if ((preamble_length < 3) || (preamble_length > 7))
1251                 return -EINVAL;
1252
1253         clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1254                         preamble_length << MACCFG2_PREL_SHIFT);
1255
1256         return 0;
1257 }
1258
1259 static int init_rx_parameters(int reject_broadcast,
1260                               int receive_short_frames,
1261                               int promiscuous, u32 __iomem *upsmr_register)
1262 {
1263         u32 value = 0;
1264
1265         value = in_be32(upsmr_register);
1266
1267         if (reject_broadcast)
1268                 value |= UCC_GETH_UPSMR_BRO;
1269         else
1270                 value &= ~UCC_GETH_UPSMR_BRO;
1271
1272         if (receive_short_frames)
1273                 value |= UCC_GETH_UPSMR_RSH;
1274         else
1275                 value &= ~UCC_GETH_UPSMR_RSH;
1276
1277         if (promiscuous)
1278                 value |= UCC_GETH_UPSMR_PRO;
1279         else
1280                 value &= ~UCC_GETH_UPSMR_PRO;
1281
1282         out_be32(upsmr_register, value);
1283
1284         return 0;
1285 }
1286
1287 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1288                                 u16 __iomem *mrblr_register)
1289 {
1290         /* max_rx_buf_len value must be a multiple of 128 */
1291         if ((max_rx_buf_len == 0) ||
1292             (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1293                 return -EINVAL;
1294
1295         out_be16(mrblr_register, max_rx_buf_len);
1296         return 0;
1297 }
1298
1299 static int init_min_frame_len(u16 min_frame_length,
1300                               u16 __iomem *minflr_register,
1301                               u16 __iomem *mrblr_register)
1302 {
1303         u16 mrblr_value = 0;
1304
1305         mrblr_value = in_be16(mrblr_register);
1306         if (min_frame_length >= (mrblr_value - 4))
1307                 return -EINVAL;
1308
1309         out_be16(minflr_register, min_frame_length);
1310         return 0;
1311 }
1312
1313 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1314 {
1315         struct ucc_geth_info *ug_info;
1316         struct ucc_geth __iomem *ug_regs;
1317         struct ucc_fast __iomem *uf_regs;
1318         int ret_val;
1319         u32 upsmr, maccfg2;
1320         u16 value;
1321
1322         ugeth_vdbg("%s: IN", __func__);
1323
1324         ug_info = ugeth->ug_info;
1325         ug_regs = ugeth->ug_regs;
1326         uf_regs = ugeth->uccf->uf_regs;
1327
1328         /*                    Set MACCFG2                    */
1329         maccfg2 = in_be32(&ug_regs->maccfg2);
1330         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1331         if ((ugeth->max_speed == SPEED_10) ||
1332             (ugeth->max_speed == SPEED_100))
1333                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1334         else if (ugeth->max_speed == SPEED_1000)
1335                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1336         maccfg2 |= ug_info->padAndCrc;
1337         out_be32(&ug_regs->maccfg2, maccfg2);
1338
1339         /*                    Set UPSMR                      */
1340         upsmr = in_be32(&uf_regs->upsmr);
1341         upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1342                    UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1343         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1344             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1345             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1346             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1347             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1348             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1349                 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1350                         upsmr |= UCC_GETH_UPSMR_RPM;
1351                 switch (ugeth->max_speed) {
1352                 case SPEED_10:
1353                         upsmr |= UCC_GETH_UPSMR_R10M;
1354                         /* FALLTHROUGH */
1355                 case SPEED_100:
1356                         if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1357                                 upsmr |= UCC_GETH_UPSMR_RMM;
1358                 }
1359         }
1360         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1361             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1362                 upsmr |= UCC_GETH_UPSMR_TBIM;
1363         }
1364         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1365                 upsmr |= UCC_GETH_UPSMR_SGMM;
1366
1367         out_be32(&uf_regs->upsmr, upsmr);
1368
1369         /* Disable autonegotiation in tbi mode, because by default it
1370         comes up in autonegotiation mode. */
1371         /* Note that this depends on proper setting in utbipar register. */
1372         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1373             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1374                 struct ucc_geth_info *ug_info = ugeth->ug_info;
1375                 struct phy_device *tbiphy;
1376
1377                 if (!ug_info->tbi_node)
1378                         pr_warn("TBI mode requires that the device tree specify a tbi-handle\n");
1379
1380                 tbiphy = of_phy_find_device(ug_info->tbi_node);
1381                 if (!tbiphy)
1382                         pr_warn("Could not get TBI device\n");
1383
1384                 value = phy_read(tbiphy, ENET_TBI_MII_CR);
1385                 value &= ~0x1000;       /* Turn off autonegotiation */
1386                 phy_write(tbiphy, ENET_TBI_MII_CR, value);
1387         }
1388
1389         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1390
1391         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1392         if (ret_val != 0) {
1393                 if (netif_msg_probe(ugeth))
1394                         pr_err("Preamble length must be between 3 and 7 inclusive\n");
1395                 return ret_val;
1396         }
1397
1398         return 0;
1399 }
1400
1401 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1402 {
1403         struct ucc_fast_private *uccf;
1404         u32 cecr_subblock;
1405         u32 temp;
1406         int i = 10;
1407
1408         uccf = ugeth->uccf;
1409
1410         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1411         clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1412         out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA);  /* clear by writing 1 */
1413
1414         /* Issue host command */
1415         cecr_subblock =
1416             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1417         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1418                      QE_CR_PROTOCOL_ETHERNET, 0);
1419
1420         /* Wait for command to complete */
1421         do {
1422                 msleep(10);
1423                 temp = in_be32(uccf->p_ucce);
1424         } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1425
1426         uccf->stopped_tx = 1;
1427
1428         return 0;
1429 }
1430
1431 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1432 {
1433         struct ucc_fast_private *uccf;
1434         u32 cecr_subblock;
1435         u8 temp;
1436         int i = 10;
1437
1438         uccf = ugeth->uccf;
1439
1440         /* Clear acknowledge bit */
1441         temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1442         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1443         out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1444
1445         /* Keep issuing command and checking acknowledge bit until
1446         it is asserted, according to spec */
1447         do {
1448                 /* Issue host command */
1449                 cecr_subblock =
1450                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1451                                                 ucc_num);
1452                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1453                              QE_CR_PROTOCOL_ETHERNET, 0);
1454                 msleep(10);
1455                 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1456         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1457
1458         uccf->stopped_rx = 1;
1459
1460         return 0;
1461 }
1462
1463 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1464 {
1465         struct ucc_fast_private *uccf;
1466         u32 cecr_subblock;
1467
1468         uccf = ugeth->uccf;
1469
1470         cecr_subblock =
1471             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1472         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1473         uccf->stopped_tx = 0;
1474
1475         return 0;
1476 }
1477
1478 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1479 {
1480         struct ucc_fast_private *uccf;
1481         u32 cecr_subblock;
1482
1483         uccf = ugeth->uccf;
1484
1485         cecr_subblock =
1486             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1487         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1488                      0);
1489         uccf->stopped_rx = 0;
1490
1491         return 0;
1492 }
1493
1494 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1495 {
1496         struct ucc_fast_private *uccf;
1497         int enabled_tx, enabled_rx;
1498
1499         uccf = ugeth->uccf;
1500
1501         /* check if the UCC number is in range. */
1502         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1503                 if (netif_msg_probe(ugeth))
1504                         pr_err("ucc_num out of range\n");
1505                 return -EINVAL;
1506         }
1507
1508         enabled_tx = uccf->enabled_tx;
1509         enabled_rx = uccf->enabled_rx;
1510
1511         /* Get Tx and Rx going again, in case this channel was actively
1512         disabled. */
1513         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1514                 ugeth_restart_tx(ugeth);
1515         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1516                 ugeth_restart_rx(ugeth);
1517
1518         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
1519
1520         return 0;
1521
1522 }
1523
1524 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1525 {
1526         struct ucc_fast_private *uccf;
1527
1528         uccf = ugeth->uccf;
1529
1530         /* check if the UCC number is in range. */
1531         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1532                 if (netif_msg_probe(ugeth))
1533                         pr_err("ucc_num out of range\n");
1534                 return -EINVAL;
1535         }
1536
1537         /* Stop any transmissions */
1538         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1539                 ugeth_graceful_stop_tx(ugeth);
1540
1541         /* Stop any receptions */
1542         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1543                 ugeth_graceful_stop_rx(ugeth);
1544
1545         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1546
1547         return 0;
1548 }
1549
1550 static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1551 {
1552         /* Prevent any further xmits, plus detach the device. */
1553         netif_device_detach(ugeth->ndev);
1554
1555         /* Wait for any current xmits to finish. */
1556         netif_tx_disable(ugeth->ndev);
1557
1558         /* Disable the interrupt to avoid NAPI rescheduling. */
1559         disable_irq(ugeth->ug_info->uf_info.irq);
1560
1561         /* Stop NAPI, and possibly wait for its completion. */
1562         napi_disable(&ugeth->napi);
1563 }
1564
1565 static void ugeth_activate(struct ucc_geth_private *ugeth)
1566 {
1567         napi_enable(&ugeth->napi);
1568         enable_irq(ugeth->ug_info->uf_info.irq);
1569         netif_device_attach(ugeth->ndev);
1570 }
1571
1572 /* Called every time the controller might need to be made
1573  * aware of new link state.  The PHY code conveys this
1574  * information through variables in the ugeth structure, and this
1575  * function converts those variables into the appropriate
1576  * register values, and can bring down the device if needed.
1577  */
1578
1579 static void adjust_link(struct net_device *dev)
1580 {
1581         struct ucc_geth_private *ugeth = netdev_priv(dev);
1582         struct ucc_geth __iomem *ug_regs;
1583         struct ucc_fast __iomem *uf_regs;
1584         struct phy_device *phydev = ugeth->phydev;
1585         int new_state = 0;
1586
1587         ug_regs = ugeth->ug_regs;
1588         uf_regs = ugeth->uccf->uf_regs;
1589
1590         if (phydev->link) {
1591                 u32 tempval = in_be32(&ug_regs->maccfg2);
1592                 u32 upsmr = in_be32(&uf_regs->upsmr);
1593                 /* Now we make sure that we can be in full duplex mode.
1594                  * If not, we operate in half-duplex mode. */
1595                 if (phydev->duplex != ugeth->oldduplex) {
1596                         new_state = 1;
1597                         if (!(phydev->duplex))
1598                                 tempval &= ~(MACCFG2_FDX);
1599                         else
1600                                 tempval |= MACCFG2_FDX;
1601                         ugeth->oldduplex = phydev->duplex;
1602                 }
1603
1604                 if (phydev->speed != ugeth->oldspeed) {
1605                         new_state = 1;
1606                         switch (phydev->speed) {
1607                         case SPEED_1000:
1608                                 tempval = ((tempval &
1609                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1610                                             MACCFG2_INTERFACE_MODE_BYTE);
1611                                 break;
1612                         case SPEED_100:
1613                         case SPEED_10:
1614                                 tempval = ((tempval &
1615                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1616                                             MACCFG2_INTERFACE_MODE_NIBBLE);
1617                                 /* if reduced mode, re-set UPSMR.R10M */
1618                                 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1619                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1620                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1621                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1622                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1623                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1624                                         if (phydev->speed == SPEED_10)
1625                                                 upsmr |= UCC_GETH_UPSMR_R10M;
1626                                         else
1627                                                 upsmr &= ~UCC_GETH_UPSMR_R10M;
1628                                 }
1629                                 break;
1630                         default:
1631                                 if (netif_msg_link(ugeth))
1632                                         pr_warn(
1633                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!",
1634                                                 dev->name, phydev->speed);
1635                                 break;
1636                         }
1637                         ugeth->oldspeed = phydev->speed;
1638                 }
1639
1640                 if (!ugeth->oldlink) {
1641                         new_state = 1;
1642                         ugeth->oldlink = 1;
1643                 }
1644
1645                 if (new_state) {
1646                         /*
1647                          * To change the MAC configuration we need to disable
1648                          * the controller. To do so, we have to either grab
1649                          * ugeth->lock, which is a bad idea since 'graceful
1650                          * stop' commands might take quite a while, or we can
1651                          * quiesce driver's activity.
1652                          */
1653                         ugeth_quiesce(ugeth);
1654                         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1655
1656                         out_be32(&ug_regs->maccfg2, tempval);
1657                         out_be32(&uf_regs->upsmr, upsmr);
1658
1659                         ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1660                         ugeth_activate(ugeth);
1661                 }
1662         } else if (ugeth->oldlink) {
1663                         new_state = 1;
1664                         ugeth->oldlink = 0;
1665                         ugeth->oldspeed = 0;
1666                         ugeth->oldduplex = -1;
1667         }
1668
1669         if (new_state && netif_msg_link(ugeth))
1670                 phy_print_status(phydev);
1671 }
1672
1673 /* Initialize TBI PHY interface for communicating with the
1674  * SERDES lynx PHY on the chip.  We communicate with this PHY
1675  * through the MDIO bus on each controller, treating it as a
1676  * "normal" PHY at the address found in the UTBIPA register.  We assume
1677  * that the UTBIPA register is valid.  Either the MDIO bus code will set
1678  * it to a value that doesn't conflict with other PHYs on the bus, or the
1679  * value doesn't matter, as there are no other PHYs on the bus.
1680  */
1681 static void uec_configure_serdes(struct net_device *dev)
1682 {
1683         struct ucc_geth_private *ugeth = netdev_priv(dev);
1684         struct ucc_geth_info *ug_info = ugeth->ug_info;
1685         struct phy_device *tbiphy;
1686
1687         if (!ug_info->tbi_node) {
1688                 dev_warn(&dev->dev, "SGMII mode requires that the device "
1689                         "tree specify a tbi-handle\n");
1690                 return;
1691         }
1692
1693         tbiphy = of_phy_find_device(ug_info->tbi_node);
1694         if (!tbiphy) {
1695                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1696                 return;
1697         }
1698
1699         /*
1700          * If the link is already up, we must already be ok, and don't need to
1701          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1702          * everything for us?  Resetting it takes the link down and requires
1703          * several seconds for it to come back.
1704          */
1705         if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1706                 return;
1707
1708         /* Single clk mode, mii mode off(for serdes communication) */
1709         phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1710
1711         phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1712
1713         phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1714 }
1715
1716 /* Configure the PHY for dev.
1717  * returns 0 if success.  -1 if failure
1718  */
1719 static int init_phy(struct net_device *dev)
1720 {
1721         struct ucc_geth_private *priv = netdev_priv(dev);
1722         struct ucc_geth_info *ug_info = priv->ug_info;
1723         struct phy_device *phydev;
1724
1725         priv->oldlink = 0;
1726         priv->oldspeed = 0;
1727         priv->oldduplex = -1;
1728
1729         phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1730                                 priv->phy_interface);
1731         if (!phydev)
1732                 phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1733                                                    priv->phy_interface);
1734         if (!phydev) {
1735                 dev_err(&dev->dev, "Could not attach to PHY\n");
1736                 return -ENODEV;
1737         }
1738
1739         if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1740                 uec_configure_serdes(dev);
1741
1742         phydev->supported &= (SUPPORTED_MII |
1743                               SUPPORTED_Autoneg |
1744                               ADVERTISED_10baseT_Half |
1745                               ADVERTISED_10baseT_Full |
1746                               ADVERTISED_100baseT_Half |
1747                               ADVERTISED_100baseT_Full);
1748
1749         if (priv->max_speed == SPEED_1000)
1750                 phydev->supported |= ADVERTISED_1000baseT_Full;
1751
1752         phydev->advertising = phydev->supported;
1753
1754         priv->phydev = phydev;
1755
1756         return 0;
1757 }
1758
1759 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1760 {
1761 #ifdef DEBUG
1762         ucc_fast_dump_regs(ugeth->uccf);
1763         dump_regs(ugeth);
1764         dump_bds(ugeth);
1765 #endif
1766 }
1767
1768 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1769                                                        ugeth,
1770                                                        enum enet_addr_type
1771                                                        enet_addr_type)
1772 {
1773         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1774         struct ucc_fast_private *uccf;
1775         enum comm_dir comm_dir;
1776         struct list_head *p_lh;
1777         u16 i, num;
1778         u32 __iomem *addr_h;
1779         u32 __iomem *addr_l;
1780         u8 *p_counter;
1781
1782         uccf = ugeth->uccf;
1783
1784         p_82xx_addr_filt =
1785             (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1786             ugeth->p_rx_glbl_pram->addressfiltering;
1787
1788         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1789                 addr_h = &(p_82xx_addr_filt->gaddr_h);
1790                 addr_l = &(p_82xx_addr_filt->gaddr_l);
1791                 p_lh = &ugeth->group_hash_q;
1792                 p_counter = &(ugeth->numGroupAddrInHash);
1793         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1794                 addr_h = &(p_82xx_addr_filt->iaddr_h);
1795                 addr_l = &(p_82xx_addr_filt->iaddr_l);
1796                 p_lh = &ugeth->ind_hash_q;
1797                 p_counter = &(ugeth->numIndAddrInHash);
1798         } else
1799                 return -EINVAL;
1800
1801         comm_dir = 0;
1802         if (uccf->enabled_tx)
1803                 comm_dir |= COMM_DIR_TX;
1804         if (uccf->enabled_rx)
1805                 comm_dir |= COMM_DIR_RX;
1806         if (comm_dir)
1807                 ugeth_disable(ugeth, comm_dir);
1808
1809         /* Clear the hash table. */
1810         out_be32(addr_h, 0x00000000);
1811         out_be32(addr_l, 0x00000000);
1812
1813         if (!p_lh)
1814                 return 0;
1815
1816         num = *p_counter;
1817
1818         /* Delete all remaining CQ elements */
1819         for (i = 0; i < num; i++)
1820                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1821
1822         *p_counter = 0;
1823
1824         if (comm_dir)
1825                 ugeth_enable(ugeth, comm_dir);
1826
1827         return 0;
1828 }
1829
1830 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1831                                                     u8 paddr_num)
1832 {
1833         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1834         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1835 }
1836
1837 static void ucc_geth_free_rx(struct ucc_geth_private *ugeth)
1838 {
1839         struct ucc_geth_info *ug_info;
1840         struct ucc_fast_info *uf_info;
1841         u16 i, j;
1842         u8 __iomem *bd;
1843
1844
1845         ug_info = ugeth->ug_info;
1846         uf_info = &ug_info->uf_info;
1847
1848         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1849                 if (ugeth->p_rx_bd_ring[i]) {
1850                         /* Return existing data buffers in ring */
1851                         bd = ugeth->p_rx_bd_ring[i];
1852                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1853                                 if (ugeth->rx_skbuff[i][j]) {
1854                                         dma_unmap_single(ugeth->dev,
1855                                                 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1856                                                 ugeth->ug_info->
1857                                                 uf_info.max_rx_buf_length +
1858                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1859                                                 DMA_FROM_DEVICE);
1860                                         dev_kfree_skb_any(
1861                                                 ugeth->rx_skbuff[i][j]);
1862                                         ugeth->rx_skbuff[i][j] = NULL;
1863                                 }
1864                                 bd += sizeof(struct qe_bd);
1865                         }
1866
1867                         kfree(ugeth->rx_skbuff[i]);
1868
1869                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1870                             MEM_PART_SYSTEM)
1871                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1872                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1873                                  MEM_PART_MURAM)
1874                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1875                         ugeth->p_rx_bd_ring[i] = NULL;
1876                 }
1877         }
1878
1879 }
1880
1881 static void ucc_geth_free_tx(struct ucc_geth_private *ugeth)
1882 {
1883         struct ucc_geth_info *ug_info;
1884         struct ucc_fast_info *uf_info;
1885         u16 i, j;
1886         u8 __iomem *bd;
1887
1888         ug_info = ugeth->ug_info;
1889         uf_info = &ug_info->uf_info;
1890
1891         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1892                 bd = ugeth->p_tx_bd_ring[i];
1893                 if (!bd)
1894                         continue;
1895                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1896                         if (ugeth->tx_skbuff[i][j]) {
1897                                 dma_unmap_single(ugeth->dev,
1898                                                  in_be32(&((struct qe_bd __iomem *)bd)->buf),
1899                                                  (in_be32((u32 __iomem *)bd) &
1900                                                   BD_LENGTH_MASK),
1901                                                  DMA_TO_DEVICE);
1902                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1903                                 ugeth->tx_skbuff[i][j] = NULL;
1904                         }
1905                 }
1906
1907                 kfree(ugeth->tx_skbuff[i]);
1908
1909                 if (ugeth->p_tx_bd_ring[i]) {
1910                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1911                             MEM_PART_SYSTEM)
1912                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1913                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1914                                  MEM_PART_MURAM)
1915                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1916                         ugeth->p_tx_bd_ring[i] = NULL;
1917                 }
1918         }
1919
1920 }
1921
1922 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1923 {
1924         if (!ugeth)
1925                 return;
1926
1927         if (ugeth->uccf) {
1928                 ucc_fast_free(ugeth->uccf);
1929                 ugeth->uccf = NULL;
1930         }
1931
1932         if (ugeth->p_thread_data_tx) {
1933                 qe_muram_free(ugeth->thread_dat_tx_offset);
1934                 ugeth->p_thread_data_tx = NULL;
1935         }
1936         if (ugeth->p_thread_data_rx) {
1937                 qe_muram_free(ugeth->thread_dat_rx_offset);
1938                 ugeth->p_thread_data_rx = NULL;
1939         }
1940         if (ugeth->p_exf_glbl_param) {
1941                 qe_muram_free(ugeth->exf_glbl_param_offset);
1942                 ugeth->p_exf_glbl_param = NULL;
1943         }
1944         if (ugeth->p_rx_glbl_pram) {
1945                 qe_muram_free(ugeth->rx_glbl_pram_offset);
1946                 ugeth->p_rx_glbl_pram = NULL;
1947         }
1948         if (ugeth->p_tx_glbl_pram) {
1949                 qe_muram_free(ugeth->tx_glbl_pram_offset);
1950                 ugeth->p_tx_glbl_pram = NULL;
1951         }
1952         if (ugeth->p_send_q_mem_reg) {
1953                 qe_muram_free(ugeth->send_q_mem_reg_offset);
1954                 ugeth->p_send_q_mem_reg = NULL;
1955         }
1956         if (ugeth->p_scheduler) {
1957                 qe_muram_free(ugeth->scheduler_offset);
1958                 ugeth->p_scheduler = NULL;
1959         }
1960         if (ugeth->p_tx_fw_statistics_pram) {
1961                 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1962                 ugeth->p_tx_fw_statistics_pram = NULL;
1963         }
1964         if (ugeth->p_rx_fw_statistics_pram) {
1965                 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1966                 ugeth->p_rx_fw_statistics_pram = NULL;
1967         }
1968         if (ugeth->p_rx_irq_coalescing_tbl) {
1969                 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1970                 ugeth->p_rx_irq_coalescing_tbl = NULL;
1971         }
1972         if (ugeth->p_rx_bd_qs_tbl) {
1973                 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1974                 ugeth->p_rx_bd_qs_tbl = NULL;
1975         }
1976         if (ugeth->p_init_enet_param_shadow) {
1977                 return_init_enet_entries(ugeth,
1978                                          &(ugeth->p_init_enet_param_shadow->
1979                                            rxthread[0]),
1980                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
1981                                          ugeth->ug_info->riscRx, 1);
1982                 return_init_enet_entries(ugeth,
1983                                          &(ugeth->p_init_enet_param_shadow->
1984                                            txthread[0]),
1985                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
1986                                          ugeth->ug_info->riscTx, 0);
1987                 kfree(ugeth->p_init_enet_param_shadow);
1988                 ugeth->p_init_enet_param_shadow = NULL;
1989         }
1990         ucc_geth_free_tx(ugeth);
1991         ucc_geth_free_rx(ugeth);
1992         while (!list_empty(&ugeth->group_hash_q))
1993                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1994                                         (dequeue(&ugeth->group_hash_q)));
1995         while (!list_empty(&ugeth->ind_hash_q))
1996                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1997                                         (dequeue(&ugeth->ind_hash_q)));
1998         if (ugeth->ug_regs) {
1999                 iounmap(ugeth->ug_regs);
2000                 ugeth->ug_regs = NULL;
2001         }
2002 }
2003
2004 static void ucc_geth_set_multi(struct net_device *dev)
2005 {
2006         struct ucc_geth_private *ugeth;
2007         struct netdev_hw_addr *ha;
2008         struct ucc_fast __iomem *uf_regs;
2009         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2010
2011         ugeth = netdev_priv(dev);
2012
2013         uf_regs = ugeth->uccf->uf_regs;
2014
2015         if (dev->flags & IFF_PROMISC) {
2016                 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2017         } else {
2018                 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2019
2020                 p_82xx_addr_filt =
2021                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2022                     p_rx_glbl_pram->addressfiltering;
2023
2024                 if (dev->flags & IFF_ALLMULTI) {
2025                         /* Catch all multicast addresses, so set the
2026                          * filter to all 1's.
2027                          */
2028                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2029                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2030                 } else {
2031                         /* Clear filter and add the addresses in the list.
2032                          */
2033                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2034                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2035
2036                         netdev_for_each_mc_addr(ha, dev) {
2037                                 /* Ask CPM to run CRC and set bit in
2038                                  * filter mask.
2039                                  */
2040                                 hw_add_addr_in_hash(ugeth, ha->addr);
2041                         }
2042                 }
2043         }
2044 }
2045
2046 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2047 {
2048         struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2049         struct phy_device *phydev = ugeth->phydev;
2050
2051         ugeth_vdbg("%s: IN", __func__);
2052
2053         /*
2054          * Tell the kernel the link is down.
2055          * Must be done before disabling the controller
2056          * or deadlock may happen.
2057          */
2058         phy_stop(phydev);
2059
2060         /* Disable the controller */
2061         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2062
2063         /* Mask all interrupts */
2064         out_be32(ugeth->uccf->p_uccm, 0x00000000);
2065
2066         /* Clear all interrupts */
2067         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2068
2069         /* Disable Rx and Tx */
2070         clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2071
2072         ucc_geth_memclean(ugeth);
2073 }
2074
2075 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2076 {
2077         struct ucc_geth_info *ug_info;
2078         struct ucc_fast_info *uf_info;
2079         int i;
2080
2081         ug_info = ugeth->ug_info;
2082         uf_info = &ug_info->uf_info;
2083
2084         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2085               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2086                 if (netif_msg_probe(ugeth))
2087                         pr_err("Bad memory partition value\n");
2088                 return -EINVAL;
2089         }
2090
2091         /* Rx BD lengths */
2092         for (i = 0; i < ug_info->numQueuesRx; i++) {
2093                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2094                     (ug_info->bdRingLenRx[i] %
2095                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2096                         if (netif_msg_probe(ugeth))
2097                                 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n");
2098                         return -EINVAL;
2099                 }
2100         }
2101
2102         /* Tx BD lengths */
2103         for (i = 0; i < ug_info->numQueuesTx; i++) {
2104                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2105                         if (netif_msg_probe(ugeth))
2106                                 pr_err("Tx BD ring length must be no smaller than 2\n");
2107                         return -EINVAL;
2108                 }
2109         }
2110
2111         /* mrblr */
2112         if ((uf_info->max_rx_buf_length == 0) ||
2113             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2114                 if (netif_msg_probe(ugeth))
2115                         pr_err("max_rx_buf_length must be non-zero multiple of 128\n");
2116                 return -EINVAL;
2117         }
2118
2119         /* num Tx queues */
2120         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2121                 if (netif_msg_probe(ugeth))
2122                         pr_err("number of tx queues too large\n");
2123                 return -EINVAL;
2124         }
2125
2126         /* num Rx queues */
2127         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2128                 if (netif_msg_probe(ugeth))
2129                         pr_err("number of rx queues too large\n");
2130                 return -EINVAL;
2131         }
2132
2133         /* l2qt */
2134         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2135                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2136                         if (netif_msg_probe(ugeth))
2137                                 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n");
2138                         return -EINVAL;
2139                 }
2140         }
2141
2142         /* l3qt */
2143         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2144                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2145                         if (netif_msg_probe(ugeth))
2146                                 pr_err("IP priority table entry must not be larger than number of Rx queues\n");
2147                         return -EINVAL;
2148                 }
2149         }
2150
2151         if (ug_info->cam && !ug_info->ecamptr) {
2152                 if (netif_msg_probe(ugeth))
2153                         pr_err("If cam mode is chosen, must supply cam ptr\n");
2154                 return -EINVAL;
2155         }
2156
2157         if ((ug_info->numStationAddresses !=
2158              UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2159             ug_info->rxExtendedFiltering) {
2160                 if (netif_msg_probe(ugeth))
2161                         pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n");
2162                 return -EINVAL;
2163         }
2164
2165         /* Generate uccm_mask for receive */
2166         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2167         for (i = 0; i < ug_info->numQueuesRx; i++)
2168                 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2169
2170         for (i = 0; i < ug_info->numQueuesTx; i++)
2171                 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2172         /* Initialize the general fast UCC block. */
2173         if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2174                 if (netif_msg_probe(ugeth))
2175                         pr_err("Failed to init uccf\n");
2176                 return -ENOMEM;
2177         }
2178
2179         /* read the number of risc engines, update the riscTx and riscRx
2180          * if there are 4 riscs in QE
2181          */
2182         if (qe_get_num_of_risc() == 4) {
2183                 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2184                 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2185         }
2186
2187         ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2188         if (!ugeth->ug_regs) {
2189                 if (netif_msg_probe(ugeth))
2190                         pr_err("Failed to ioremap regs\n");
2191                 return -ENOMEM;
2192         }
2193
2194         return 0;
2195 }
2196
2197 static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth)
2198 {
2199         struct ucc_geth_info *ug_info;
2200         struct ucc_fast_info *uf_info;
2201         int length;
2202         u16 i, j;
2203         u8 __iomem *bd;
2204
2205         ug_info = ugeth->ug_info;
2206         uf_info = &ug_info->uf_info;
2207
2208         /* Allocate Tx bds */
2209         for (j = 0; j < ug_info->numQueuesTx; j++) {
2210                 /* Allocate in multiple of
2211                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2212                    according to spec */
2213                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2214                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2215                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2216                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2217                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2218                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2219                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2220                         u32 align = 4;
2221                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2222                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2223                         ugeth->tx_bd_ring_offset[j] =
2224                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2225
2226                         if (ugeth->tx_bd_ring_offset[j] != 0)
2227                                 ugeth->p_tx_bd_ring[j] =
2228                                         (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2229                                         align) & ~(align - 1));
2230                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2231                         ugeth->tx_bd_ring_offset[j] =
2232                             qe_muram_alloc(length,
2233                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2234                         if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2235                                 ugeth->p_tx_bd_ring[j] =
2236                                     (u8 __iomem *) qe_muram_addr(ugeth->
2237                                                          tx_bd_ring_offset[j]);
2238                 }
2239                 if (!ugeth->p_tx_bd_ring[j]) {
2240                         if (netif_msg_ifup(ugeth))
2241                                 pr_err("Can not allocate memory for Tx bd rings\n");
2242                         return -ENOMEM;
2243                 }
2244                 /* Zero unused end of bd ring, according to spec */
2245                 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2246                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2247                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2248         }
2249
2250         /* Init Tx bds */
2251         for (j = 0; j < ug_info->numQueuesTx; j++) {
2252                 /* Setup the skbuff rings */
2253                 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2254                                               ugeth->ug_info->bdRingLenTx[j],
2255                                               GFP_KERNEL);
2256
2257                 if (ugeth->tx_skbuff[j] == NULL) {
2258                         if (netif_msg_ifup(ugeth))
2259                                 pr_err("Could not allocate tx_skbuff\n");
2260                         return -ENOMEM;
2261                 }
2262
2263                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2264                         ugeth->tx_skbuff[j][i] = NULL;
2265
2266                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2267                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2268                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2269                         /* clear bd buffer */
2270                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2271                         /* set bd status and length */
2272                         out_be32((u32 __iomem *)bd, 0);
2273                         bd += sizeof(struct qe_bd);
2274                 }
2275                 bd -= sizeof(struct qe_bd);
2276                 /* set bd status and length */
2277                 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2278         }
2279
2280         return 0;
2281 }
2282
2283 static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth)
2284 {
2285         struct ucc_geth_info *ug_info;
2286         struct ucc_fast_info *uf_info;
2287         int length;
2288         u16 i, j;
2289         u8 __iomem *bd;
2290
2291         ug_info = ugeth->ug_info;
2292         uf_info = &ug_info->uf_info;
2293
2294         /* Allocate Rx bds */
2295         for (j = 0; j < ug_info->numQueuesRx; j++) {
2296                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2297                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2298                         u32 align = 4;
2299                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2300                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2301                         ugeth->rx_bd_ring_offset[j] =
2302                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2303                         if (ugeth->rx_bd_ring_offset[j] != 0)
2304                                 ugeth->p_rx_bd_ring[j] =
2305                                         (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2306                                         align) & ~(align - 1));
2307                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2308                         ugeth->rx_bd_ring_offset[j] =
2309                             qe_muram_alloc(length,
2310                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2311                         if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2312                                 ugeth->p_rx_bd_ring[j] =
2313                                     (u8 __iomem *) qe_muram_addr(ugeth->
2314                                                          rx_bd_ring_offset[j]);
2315                 }
2316                 if (!ugeth->p_rx_bd_ring[j]) {
2317                         if (netif_msg_ifup(ugeth))
2318                                 pr_err("Can not allocate memory for Rx bd rings\n");
2319                         return -ENOMEM;
2320                 }
2321         }
2322
2323         /* Init Rx bds */
2324         for (j = 0; j < ug_info->numQueuesRx; j++) {
2325                 /* Setup the skbuff rings */
2326                 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2327                                               ugeth->ug_info->bdRingLenRx[j],
2328                                               GFP_KERNEL);
2329
2330                 if (ugeth->rx_skbuff[j] == NULL) {
2331                         if (netif_msg_ifup(ugeth))
2332                                 pr_err("Could not allocate rx_skbuff\n");
2333                         return -ENOMEM;
2334                 }
2335
2336                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2337                         ugeth->rx_skbuff[j][i] = NULL;
2338
2339                 ugeth->skb_currx[j] = 0;
2340                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2341                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2342                         /* set bd status and length */
2343                         out_be32((u32 __iomem *)bd, R_I);
2344                         /* clear bd buffer */
2345                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2346                         bd += sizeof(struct qe_bd);
2347                 }
2348                 bd -= sizeof(struct qe_bd);
2349                 /* set bd status and length */
2350                 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2351         }
2352
2353         return 0;
2354 }
2355
2356 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2357 {
2358         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2359         struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2360         struct ucc_fast_private *uccf;
2361         struct ucc_geth_info *ug_info;
2362         struct ucc_fast_info *uf_info;
2363         struct ucc_fast __iomem *uf_regs;
2364         struct ucc_geth __iomem *ug_regs;
2365         int ret_val = -EINVAL;
2366         u32 remoder = UCC_GETH_REMODER_INIT;
2367         u32 init_enet_pram_offset, cecr_subblock, command;
2368         u32 ifstat, i, j, size, l2qt, l3qt;
2369         u16 temoder = UCC_GETH_TEMODER_INIT;
2370         u16 test;
2371         u8 function_code = 0;
2372         u8 __iomem *endOfRing;
2373         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2374
2375         ugeth_vdbg("%s: IN", __func__);
2376         uccf = ugeth->uccf;
2377         ug_info = ugeth->ug_info;
2378         uf_info = &ug_info->uf_info;
2379         uf_regs = uccf->uf_regs;
2380         ug_regs = ugeth->ug_regs;
2381
2382         switch (ug_info->numThreadsRx) {
2383         case UCC_GETH_NUM_OF_THREADS_1:
2384                 numThreadsRxNumerical = 1;
2385                 break;
2386         case UCC_GETH_NUM_OF_THREADS_2:
2387                 numThreadsRxNumerical = 2;
2388                 break;
2389         case UCC_GETH_NUM_OF_THREADS_4:
2390                 numThreadsRxNumerical = 4;
2391                 break;
2392         case UCC_GETH_NUM_OF_THREADS_6:
2393                 numThreadsRxNumerical = 6;
2394                 break;
2395         case UCC_GETH_NUM_OF_THREADS_8:
2396                 numThreadsRxNumerical = 8;
2397                 break;
2398         default:
2399                 if (netif_msg_ifup(ugeth))
2400                         pr_err("Bad number of Rx threads value\n");
2401                 return -EINVAL;
2402                 break;
2403         }
2404
2405         switch (ug_info->numThreadsTx) {
2406         case UCC_GETH_NUM_OF_THREADS_1:
2407                 numThreadsTxNumerical = 1;
2408                 break;
2409         case UCC_GETH_NUM_OF_THREADS_2:
2410                 numThreadsTxNumerical = 2;
2411                 break;
2412         case UCC_GETH_NUM_OF_THREADS_4:
2413                 numThreadsTxNumerical = 4;
2414                 break;
2415         case UCC_GETH_NUM_OF_THREADS_6:
2416                 numThreadsTxNumerical = 6;
2417                 break;
2418         case UCC_GETH_NUM_OF_THREADS_8:
2419                 numThreadsTxNumerical = 8;
2420                 break;
2421         default:
2422                 if (netif_msg_ifup(ugeth))
2423                         pr_err("Bad number of Tx threads value\n");
2424                 return -EINVAL;
2425                 break;
2426         }
2427
2428         /* Calculate rx_extended_features */
2429         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2430             ug_info->ipAddressAlignment ||
2431             (ug_info->numStationAddresses !=
2432              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2433
2434         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2435                 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2436                 (ug_info->vlanOperationNonTagged !=
2437                  UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2438
2439         init_default_reg_vals(&uf_regs->upsmr,
2440                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2441
2442         /*                    Set UPSMR                      */
2443         /* For more details see the hardware spec.           */
2444         init_rx_parameters(ug_info->bro,
2445                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2446
2447         /* We're going to ignore other registers for now, */
2448         /* except as needed to get up and running         */
2449
2450         /*                    Set MACCFG1                    */
2451         /* For more details see the hardware spec.           */
2452         init_flow_control_params(ug_info->aufc,
2453                                  ug_info->receiveFlowControl,
2454                                  ug_info->transmitFlowControl,
2455                                  ug_info->pausePeriod,
2456                                  ug_info->extensionField,
2457                                  &uf_regs->upsmr,
2458                                  &ug_regs->uempr, &ug_regs->maccfg1);
2459
2460         setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2461
2462         /*                    Set IPGIFG                     */
2463         /* For more details see the hardware spec.           */
2464         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2465                                               ug_info->nonBackToBackIfgPart2,
2466                                               ug_info->
2467                                               miminumInterFrameGapEnforcement,
2468                                               ug_info->backToBackInterFrameGap,
2469                                               &ug_regs->ipgifg);
2470         if (ret_val != 0) {
2471                 if (netif_msg_ifup(ugeth))
2472                         pr_err("IPGIFG initialization parameter too large\n");
2473                 return ret_val;
2474         }
2475
2476         /*                    Set HAFDUP                     */
2477         /* For more details see the hardware spec.           */
2478         ret_val = init_half_duplex_params(ug_info->altBeb,
2479                                           ug_info->backPressureNoBackoff,
2480                                           ug_info->noBackoff,
2481                                           ug_info->excessDefer,
2482                                           ug_info->altBebTruncation,
2483                                           ug_info->maxRetransmission,
2484                                           ug_info->collisionWindow,
2485                                           &ug_regs->hafdup);
2486         if (ret_val != 0) {
2487                 if (netif_msg_ifup(ugeth))
2488                         pr_err("Half Duplex initialization parameter too large\n");
2489                 return ret_val;
2490         }
2491
2492         /*                    Set IFSTAT                     */
2493         /* For more details see the hardware spec.           */
2494         /* Read only - resets upon read                      */
2495         ifstat = in_be32(&ug_regs->ifstat);
2496
2497         /*                    Clear UEMPR                    */
2498         /* For more details see the hardware spec.           */
2499         out_be32(&ug_regs->uempr, 0);
2500
2501         /*                    Set UESCR                      */
2502         /* For more details see the hardware spec.           */
2503         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2504                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2505                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2506
2507         ret_val = ucc_geth_alloc_tx(ugeth);
2508         if (ret_val != 0)
2509                 return ret_val;
2510
2511         ret_val = ucc_geth_alloc_rx(ugeth);
2512         if (ret_val != 0)
2513                 return ret_val;
2514
2515         /*
2516          * Global PRAM
2517          */
2518         /* Tx global PRAM */
2519         /* Allocate global tx parameter RAM page */
2520         ugeth->tx_glbl_pram_offset =
2521             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2522                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2523         if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2524                 if (netif_msg_ifup(ugeth))
2525                         pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n");
2526                 return -ENOMEM;
2527         }
2528         ugeth->p_tx_glbl_pram =
2529             (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2530                                                         tx_glbl_pram_offset);
2531         /* Zero out p_tx_glbl_pram */
2532         memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2533
2534         /* Fill global PRAM */
2535
2536         /* TQPTR */
2537         /* Size varies with number of Tx threads */
2538         ugeth->thread_dat_tx_offset =
2539             qe_muram_alloc(numThreadsTxNumerical *
2540                            sizeof(struct ucc_geth_thread_data_tx) +
2541                            32 * (numThreadsTxNumerical == 1),
2542                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2543         if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2544                 if (netif_msg_ifup(ugeth))
2545                         pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n");
2546                 return -ENOMEM;
2547         }
2548
2549         ugeth->p_thread_data_tx =
2550             (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2551                                                         thread_dat_tx_offset);
2552         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2553
2554         /* vtagtable */
2555         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2556                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2557                          ug_info->vtagtable[i]);
2558
2559         /* iphoffset */
2560         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2561                 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2562                                 ug_info->iphoffset[i]);
2563
2564         /* SQPTR */
2565         /* Size varies with number of Tx queues */
2566         ugeth->send_q_mem_reg_offset =
2567             qe_muram_alloc(ug_info->numQueuesTx *
2568                            sizeof(struct ucc_geth_send_queue_qd),
2569                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2570         if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2571                 if (netif_msg_ifup(ugeth))
2572                         pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n");
2573                 return -ENOMEM;
2574         }
2575
2576         ugeth->p_send_q_mem_reg =
2577             (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2578                         send_q_mem_reg_offset);
2579         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2580
2581         /* Setup the table */
2582         /* Assume BD rings are already established */
2583         for (i = 0; i < ug_info->numQueuesTx; i++) {
2584                 endOfRing =
2585                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2586                                               1) * sizeof(struct qe_bd);
2587                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2588                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2589                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2590                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2591                                  last_bd_completed_address,
2592                                  (u32) virt_to_phys(endOfRing));
2593                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2594                            MEM_PART_MURAM) {
2595                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2596                                  (u32) immrbar_virt_to_phys(ugeth->
2597                                                             p_tx_bd_ring[i]));
2598                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2599                                  last_bd_completed_address,
2600                                  (u32) immrbar_virt_to_phys(endOfRing));
2601                 }
2602         }
2603
2604         /* schedulerbasepointer */
2605
2606         if (ug_info->numQueuesTx > 1) {
2607         /* scheduler exists only if more than 1 tx queue */
2608                 ugeth->scheduler_offset =
2609                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2610                                    UCC_GETH_SCHEDULER_ALIGNMENT);
2611                 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2612                         if (netif_msg_ifup(ugeth))
2613                                 pr_err("Can not allocate DPRAM memory for p_scheduler\n");
2614                         return -ENOMEM;
2615                 }
2616
2617                 ugeth->p_scheduler =
2618                     (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2619                                                            scheduler_offset);
2620                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2621                          ugeth->scheduler_offset);
2622                 /* Zero out p_scheduler */
2623                 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2624
2625                 /* Set values in scheduler */
2626                 out_be32(&ugeth->p_scheduler->mblinterval,
2627                          ug_info->mblinterval);
2628                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2629                          ug_info->nortsrbytetime);
2630                 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2631                 out_8(&ugeth->p_scheduler->strictpriorityq,
2632                                 ug_info->strictpriorityq);
2633                 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2634                 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2635                 for (i = 0; i < NUM_TX_QUEUES; i++)
2636                         out_8(&ugeth->p_scheduler->weightfactor[i],
2637                             ug_info->weightfactor[i]);
2638
2639                 /* Set pointers to cpucount registers in scheduler */
2640                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2641                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2642                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2643                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2644                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2645                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2646                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2647                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2648         }
2649
2650         /* schedulerbasepointer */
2651         /* TxRMON_PTR (statistics) */
2652         if (ug_info->
2653             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2654                 ugeth->tx_fw_statistics_pram_offset =
2655                     qe_muram_alloc(sizeof
2656                                    (struct ucc_geth_tx_firmware_statistics_pram),
2657                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
2658                 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2659                         if (netif_msg_ifup(ugeth))
2660                                 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n");
2661                         return -ENOMEM;
2662                 }
2663                 ugeth->p_tx_fw_statistics_pram =
2664                     (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2665                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2666                 /* Zero out p_tx_fw_statistics_pram */
2667                 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2668                        0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2669         }
2670
2671         /* temoder */
2672         /* Already has speed set */
2673
2674         if (ug_info->numQueuesTx > 1)
2675                 temoder |= TEMODER_SCHEDULER_ENABLE;
2676         if (ug_info->ipCheckSumGenerate)
2677                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2678         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2679         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2680
2681         test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2682
2683         /* Function code register value to be used later */
2684         function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2685         /* Required for QE */
2686
2687         /* function code register */
2688         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2689
2690         /* Rx global PRAM */
2691         /* Allocate global rx parameter RAM page */
2692         ugeth->rx_glbl_pram_offset =
2693             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2694                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2695         if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2696                 if (netif_msg_ifup(ugeth))
2697                         pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n");
2698                 return -ENOMEM;
2699         }
2700         ugeth->p_rx_glbl_pram =
2701             (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2702                                                         rx_glbl_pram_offset);
2703         /* Zero out p_rx_glbl_pram */
2704         memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2705
2706         /* Fill global PRAM */
2707
2708         /* RQPTR */
2709         /* Size varies with number of Rx threads */
2710         ugeth->thread_dat_rx_offset =
2711             qe_muram_alloc(numThreadsRxNumerical *
2712                            sizeof(struct ucc_geth_thread_data_rx),
2713                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2714         if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2715                 if (netif_msg_ifup(ugeth))
2716                         pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n");
2717                 return -ENOMEM;
2718         }
2719
2720         ugeth->p_thread_data_rx =
2721             (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2722                                                         thread_dat_rx_offset);
2723         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2724
2725         /* typeorlen */
2726         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2727
2728         /* rxrmonbaseptr (statistics) */
2729         if (ug_info->
2730             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2731                 ugeth->rx_fw_statistics_pram_offset =
2732                     qe_muram_alloc(sizeof
2733                                    (struct ucc_geth_rx_firmware_statistics_pram),
2734                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
2735                 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2736                         if (netif_msg_ifup(ugeth))
2737                                 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n");
2738                         return -ENOMEM;
2739                 }
2740                 ugeth->p_rx_fw_statistics_pram =
2741                     (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2742                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2743                 /* Zero out p_rx_fw_statistics_pram */
2744                 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2745                        sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2746         }
2747
2748         /* intCoalescingPtr */
2749
2750         /* Size varies with number of Rx queues */
2751         ugeth->rx_irq_coalescing_tbl_offset =
2752             qe_muram_alloc(ug_info->numQueuesRx *
2753                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2754                            + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2755         if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2756                 if (netif_msg_ifup(ugeth))
2757                         pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n");
2758                 return -ENOMEM;
2759         }
2760
2761         ugeth->p_rx_irq_coalescing_tbl =
2762             (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2763             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2764         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2765                  ugeth->rx_irq_coalescing_tbl_offset);
2766
2767         /* Fill interrupt coalescing table */
2768         for (i = 0; i < ug_info->numQueuesRx; i++) {
2769                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2770                          interruptcoalescingmaxvalue,
2771                          ug_info->interruptcoalescingmaxvalue[i]);
2772                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2773                          interruptcoalescingcounter,
2774                          ug_info->interruptcoalescingmaxvalue[i]);
2775         }
2776
2777         /* MRBLR */
2778         init_max_rx_buff_len(uf_info->max_rx_buf_length,
2779                              &ugeth->p_rx_glbl_pram->mrblr);
2780         /* MFLR */
2781         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2782         /* MINFLR */
2783         init_min_frame_len(ug_info->minFrameLength,
2784                            &ugeth->p_rx_glbl_pram->minflr,
2785                            &ugeth->p_rx_glbl_pram->mrblr);
2786         /* MAXD1 */
2787         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2788         /* MAXD2 */
2789         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2790
2791         /* l2qt */
2792         l2qt = 0;
2793         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2794                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2795         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2796
2797         /* l3qt */
2798         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2799                 l3qt = 0;
2800                 for (i = 0; i < 8; i++)
2801                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2802                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2803         }
2804
2805         /* vlantype */
2806         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2807
2808         /* vlantci */
2809         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2810
2811         /* ecamptr */
2812         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2813
2814         /* RBDQPTR */
2815         /* Size varies with number of Rx queues */
2816         ugeth->rx_bd_qs_tbl_offset =
2817             qe_muram_alloc(ug_info->numQueuesRx *
2818                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2819                             sizeof(struct ucc_geth_rx_prefetched_bds)),
2820                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2821         if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2822                 if (netif_msg_ifup(ugeth))
2823                         pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n");
2824                 return -ENOMEM;
2825         }
2826
2827         ugeth->p_rx_bd_qs_tbl =
2828             (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2829                                     rx_bd_qs_tbl_offset);
2830         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2831         /* Zero out p_rx_bd_qs_tbl */
2832         memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2833                0,
2834                ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2835                                        sizeof(struct ucc_geth_rx_prefetched_bds)));
2836
2837         /* Setup the table */
2838         /* Assume BD rings are already established */
2839         for (i = 0; i < ug_info->numQueuesRx; i++) {
2840                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2841                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2842                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2843                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2844                            MEM_PART_MURAM) {
2845                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2846                                  (u32) immrbar_virt_to_phys(ugeth->
2847                                                             p_rx_bd_ring[i]));
2848                 }
2849                 /* rest of fields handled by QE */
2850         }
2851
2852         /* remoder */
2853         /* Already has speed set */
2854
2855         if (ugeth->rx_extended_features)
2856                 remoder |= REMODER_RX_EXTENDED_FEATURES;
2857         if (ug_info->rxExtendedFiltering)
2858                 remoder |= REMODER_RX_EXTENDED_FILTERING;
2859         if (ug_info->dynamicMaxFrameLength)
2860                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2861         if (ug_info->dynamicMinFrameLength)
2862                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2863         remoder |=
2864             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2865         remoder |=
2866             ug_info->
2867             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2868         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2869         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2870         if (ug_info->ipCheckSumCheck)
2871                 remoder |= REMODER_IP_CHECKSUM_CHECK;
2872         if (ug_info->ipAddressAlignment)
2873                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2874         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2875
2876         /* Note that this function must be called */
2877         /* ONLY AFTER p_tx_fw_statistics_pram */
2878         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2879         init_firmware_statistics_gathering_mode((ug_info->
2880                 statisticsMode &
2881                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2882                 (ug_info->statisticsMode &
2883                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2884                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2885                 ugeth->tx_fw_statistics_pram_offset,
2886                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2887                 ugeth->rx_fw_statistics_pram_offset,
2888                 &ugeth->p_tx_glbl_pram->temoder,
2889                 &ugeth->p_rx_glbl_pram->remoder);
2890
2891         /* function code register */
2892         out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2893
2894         /* initialize extended filtering */
2895         if (ug_info->rxExtendedFiltering) {
2896                 if (!ug_info->extendedFilteringChainPointer) {
2897                         if (netif_msg_ifup(ugeth))
2898                                 pr_err("Null Extended Filtering Chain Pointer\n");
2899                         return -EINVAL;
2900                 }
2901
2902                 /* Allocate memory for extended filtering Mode Global
2903                 Parameters */
2904                 ugeth->exf_glbl_param_offset =
2905                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2906                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2907                 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2908                         if (netif_msg_ifup(ugeth))
2909                                 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n");
2910                         return -ENOMEM;
2911                 }
2912
2913                 ugeth->p_exf_glbl_param =
2914                     (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2915                                  exf_glbl_param_offset);
2916                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2917                          ugeth->exf_glbl_param_offset);
2918                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2919                          (u32) ug_info->extendedFilteringChainPointer);
2920
2921         } else {                /* initialize 82xx style address filtering */
2922
2923                 /* Init individual address recognition registers to disabled */
2924
2925                 for (j = 0; j < NUM_OF_PADDRS; j++)
2926                         ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2927
2928                 p_82xx_addr_filt =
2929                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2930                     p_rx_glbl_pram->addressfiltering;
2931
2932                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2933                         ENET_ADDR_TYPE_GROUP);
2934                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2935                         ENET_ADDR_TYPE_INDIVIDUAL);
2936         }
2937
2938         /*
2939          * Initialize UCC at QE level
2940          */
2941
2942         command = QE_INIT_TX_RX;
2943
2944         /* Allocate shadow InitEnet command parameter structure.
2945          * This is needed because after the InitEnet command is executed,
2946          * the structure in DPRAM is released, because DPRAM is a premium
2947          * resource.
2948          * This shadow structure keeps a copy of what was done so that the
2949          * allocated resources can be released when the channel is freed.
2950          */
2951         if (!(ugeth->p_init_enet_param_shadow =
2952               kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2953                 if (netif_msg_ifup(ugeth))
2954                         pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n");
2955                 return -ENOMEM;
2956         }
2957         /* Zero out *p_init_enet_param_shadow */
2958         memset((char *)ugeth->p_init_enet_param_shadow,
2959                0, sizeof(struct ucc_geth_init_pram));
2960
2961         /* Fill shadow InitEnet command parameter structure */
2962
2963         ugeth->p_init_enet_param_shadow->resinit1 =
2964             ENET_INIT_PARAM_MAGIC_RES_INIT1;
2965         ugeth->p_init_enet_param_shadow->resinit2 =
2966             ENET_INIT_PARAM_MAGIC_RES_INIT2;
2967         ugeth->p_init_enet_param_shadow->resinit3 =
2968             ENET_INIT_PARAM_MAGIC_RES_INIT3;
2969         ugeth->p_init_enet_param_shadow->resinit4 =
2970             ENET_INIT_PARAM_MAGIC_RES_INIT4;
2971         ugeth->p_init_enet_param_shadow->resinit5 =
2972             ENET_INIT_PARAM_MAGIC_RES_INIT5;
2973         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2974             ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2975         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2976             ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2977
2978         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2979             ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2980         if ((ug_info->largestexternallookupkeysize !=
2981              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2982             (ug_info->largestexternallookupkeysize !=
2983              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
2984             (ug_info->largestexternallookupkeysize !=
2985              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2986                 if (netif_msg_ifup(ugeth))
2987                         pr_err("Invalid largest External Lookup Key Size\n");
2988                 return -EINVAL;
2989         }
2990         ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2991             ug_info->largestexternallookupkeysize;
2992         size = sizeof(struct ucc_geth_thread_rx_pram);
2993         if (ug_info->rxExtendedFiltering) {
2994                 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2995                 if (ug_info->largestexternallookupkeysize ==
2996                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2997                         size +=
2998                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2999                 if (ug_info->largestexternallookupkeysize ==
3000                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3001                         size +=
3002                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3003         }
3004
3005         if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3006                 p_init_enet_param_shadow->rxthread[0]),
3007                 (u8) (numThreadsRxNumerical + 1)
3008                 /* Rx needs one extra for terminator */
3009                 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3010                 ug_info->riscRx, 1)) != 0) {
3011                 if (netif_msg_ifup(ugeth))
3012                         pr_err("Can not fill p_init_enet_param_shadow\n");
3013                 return ret_val;
3014         }
3015
3016         ugeth->p_init_enet_param_shadow->txglobal =
3017             ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3018         if ((ret_val =
3019              fill_init_enet_entries(ugeth,
3020                                     &(ugeth->p_init_enet_param_shadow->
3021                                       txthread[0]), numThreadsTxNumerical,
3022                                     sizeof(struct ucc_geth_thread_tx_pram),
3023                                     UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3024                                     ug_info->riscTx, 0)) != 0) {
3025                 if (netif_msg_ifup(ugeth))
3026                         pr_err("Can not fill p_init_enet_param_shadow\n");
3027                 return ret_val;
3028         }
3029
3030         /* Load Rx bds with buffers */
3031         for (i = 0; i < ug_info->numQueuesRx; i++) {
3032                 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3033                         if (netif_msg_ifup(ugeth))
3034                                 pr_err("Can not fill Rx bds with buffers\n");
3035                         return ret_val;
3036                 }
3037         }
3038
3039         /* Allocate InitEnet command parameter structure */
3040         init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3041         if (IS_ERR_VALUE(init_enet_pram_offset)) {
3042                 if (netif_msg_ifup(ugeth))
3043                         pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n");
3044                 return -ENOMEM;
3045         }
3046         p_init_enet_pram =
3047             (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3048
3049         /* Copy shadow InitEnet command parameter structure into PRAM */
3050         out_8(&p_init_enet_pram->resinit1,
3051                         ugeth->p_init_enet_param_shadow->resinit1);
3052         out_8(&p_init_enet_pram->resinit2,
3053                         ugeth->p_init_enet_param_shadow->resinit2);
3054         out_8(&p_init_enet_pram->resinit3,
3055                         ugeth->p_init_enet_param_shadow->resinit3);
3056         out_8(&p_init_enet_pram->resinit4,
3057                         ugeth->p_init_enet_param_shadow->resinit4);
3058         out_be16(&p_init_enet_pram->resinit5,
3059                  ugeth->p_init_enet_param_shadow->resinit5);
3060         out_8(&p_init_enet_pram->largestexternallookupkeysize,
3061             ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3062         out_be32(&p_init_enet_pram->rgftgfrxglobal,
3063                  ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3064         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3065                 out_be32(&p_init_enet_pram->rxthread[i],
3066                          ugeth->p_init_enet_param_shadow->rxthread[i]);
3067         out_be32(&p_init_enet_pram->txglobal,
3068                  ugeth->p_init_enet_param_shadow->txglobal);
3069         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3070                 out_be32(&p_init_enet_pram->txthread[i],
3071                          ugeth->p_init_enet_param_shadow->txthread[i]);
3072
3073         /* Issue QE command */
3074         cecr_subblock =
3075             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3076         qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3077                      init_enet_pram_offset);
3078
3079         /* Free InitEnet command parameter */
3080         qe_muram_free(init_enet_pram_offset);
3081
3082         return 0;
3083 }
3084
3085 /* This is called by the kernel when a frame is ready for transmission. */
3086 /* It is pointed to by the dev->hard_start_xmit function pointer */
3087 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3088 {
3089         struct ucc_geth_private *ugeth = netdev_priv(dev);
3090 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3091         struct ucc_fast_private *uccf;
3092 #endif
3093         u8 __iomem *bd;                 /* BD pointer */
3094         u32 bd_status;
3095         u8 txQ = 0;
3096         unsigned long flags;
3097
3098         ugeth_vdbg("%s: IN", __func__);
3099
3100         spin_lock_irqsave(&ugeth->lock, flags);
3101
3102         dev->stats.tx_bytes += skb->len;
3103
3104         /* Start from the next BD that should be filled */
3105         bd = ugeth->txBd[txQ];
3106         bd_status = in_be32((u32 __iomem *)bd);
3107         /* Save the skb pointer so we can free it later */
3108         ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3109
3110         /* Update the current skb pointer (wrapping if this was the last) */
3111         ugeth->skb_curtx[txQ] =
3112             (ugeth->skb_curtx[txQ] +
3113              1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3114
3115         /* set up the buffer descriptor */
3116         out_be32(&((struct qe_bd __iomem *)bd)->buf,
3117                       dma_map_single(ugeth->dev, skb->data,
3118                               skb->len, DMA_TO_DEVICE));
3119
3120         /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3121
3122         bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3123
3124         /* set bd status and length */
3125         out_be32((u32 __iomem *)bd, bd_status);
3126
3127         /* Move to next BD in the ring */
3128         if (!(bd_status & T_W))
3129                 bd += sizeof(struct qe_bd);
3130         else
3131                 bd = ugeth->p_tx_bd_ring[txQ];
3132
3133         /* If the next BD still needs to be cleaned up, then the bds
3134            are full.  We need to tell the kernel to stop sending us stuff. */
3135         if (bd == ugeth->confBd[txQ]) {
3136                 if (!netif_queue_stopped(dev))
3137                         netif_stop_queue(dev);
3138         }
3139
3140         ugeth->txBd[txQ] = bd;
3141
3142         skb_tx_timestamp(skb);
3143
3144         if (ugeth->p_scheduler) {
3145                 ugeth->cpucount[txQ]++;
3146                 /* Indicate to QE that there are more Tx bds ready for
3147                 transmission */
3148                 /* This is done by writing a running counter of the bd
3149                 count to the scheduler PRAM. */
3150                 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3151         }
3152
3153 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3154         uccf = ugeth->uccf;
3155         out_be16(uccf->p_utodr, UCC_FAST_TOD);
3156 #endif
3157         spin_unlock_irqrestore(&ugeth->lock, flags);
3158
3159         return NETDEV_TX_OK;
3160 }
3161
3162 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3163 {
3164         struct sk_buff *skb;
3165         u8 __iomem *bd;
3166         u16 length, howmany = 0;
3167         u32 bd_status;
3168         u8 *bdBuffer;
3169         struct net_device *dev;
3170
3171         ugeth_vdbg("%s: IN", __func__);
3172
3173         dev = ugeth->ndev;
3174
3175         /* collect received buffers */
3176         bd = ugeth->rxBd[rxQ];
3177
3178         bd_status = in_be32((u32 __iomem *)bd);
3179
3180         /* while there are received buffers and BD is full (~R_E) */
3181         while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3182                 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3183                 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3184                 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3185
3186                 /* determine whether buffer is first, last, first and last
3187                 (single buffer frame) or middle (not first and not last) */
3188                 if (!skb ||
3189                     (!(bd_status & (R_F | R_L))) ||
3190                     (bd_status & R_ERRORS_FATAL)) {
3191                         if (netif_msg_rx_err(ugeth))
3192                                 pr_err("%d: ERROR!!! skb - 0x%08x\n",
3193                                        __LINE__, (u32)skb);
3194                         dev_kfree_skb(skb);
3195
3196                         ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3197                         dev->stats.rx_dropped++;
3198                 } else {
3199                         dev->stats.rx_packets++;
3200                         howmany++;
3201
3202                         /* Prep the skb for the packet */
3203                         skb_put(skb, length);
3204
3205                         /* Tell the skb what kind of packet this is */
3206                         skb->protocol = eth_type_trans(skb, ugeth->ndev);
3207
3208                         dev->stats.rx_bytes += length;
3209                         /* Send the packet up the stack */
3210                         netif_receive_skb(skb);
3211                 }
3212
3213                 skb = get_new_skb(ugeth, bd);
3214                 if (!skb) {
3215                         if (netif_msg_rx_err(ugeth))
3216                                 pr_warn("No Rx Data Buffer\n");
3217                         dev->stats.rx_dropped++;
3218                         break;
3219                 }
3220
3221                 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3222
3223                 /* update to point at the next skb */
3224                 ugeth->skb_currx[rxQ] =
3225                     (ugeth->skb_currx[rxQ] +
3226                      1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3227
3228                 if (bd_status & R_W)
3229                         bd = ugeth->p_rx_bd_ring[rxQ];
3230                 else
3231                         bd += sizeof(struct qe_bd);
3232
3233                 bd_status = in_be32((u32 __iomem *)bd);
3234         }
3235
3236         ugeth->rxBd[rxQ] = bd;
3237         return howmany;
3238 }
3239
3240 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3241 {
3242         /* Start from the next BD that should be filled */
3243         struct ucc_geth_private *ugeth = netdev_priv(dev);
3244         u8 __iomem *bd;         /* BD pointer */
3245         u32 bd_status;
3246
3247         bd = ugeth->confBd[txQ];
3248         bd_status = in_be32((u32 __iomem *)bd);
3249
3250         /* Normal processing. */
3251         while ((bd_status & T_R) == 0) {
3252                 struct sk_buff *skb;
3253
3254                 /* BD contains already transmitted buffer.   */
3255                 /* Handle the transmitted buffer and release */
3256                 /* the BD to be used with the current frame  */
3257
3258                 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3259                 if (!skb)
3260                         break;
3261
3262                 dev->stats.tx_packets++;
3263
3264                 dev_kfree_skb(skb);
3265
3266                 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3267                 ugeth->skb_dirtytx[txQ] =
3268                     (ugeth->skb_dirtytx[txQ] +
3269                      1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3270
3271                 /* We freed a buffer, so now we can restart transmission */
3272                 if (netif_queue_stopped(dev))
3273                         netif_wake_queue(dev);
3274
3275                 /* Advance the confirmation BD pointer */
3276                 if (!(bd_status & T_W))
3277                         bd += sizeof(struct qe_bd);
3278                 else
3279                         bd = ugeth->p_tx_bd_ring[txQ];
3280                 bd_status = in_be32((u32 __iomem *)bd);
3281         }
3282         ugeth->confBd[txQ] = bd;
3283         return 0;
3284 }
3285
3286 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3287 {
3288         struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3289         struct ucc_geth_info *ug_info;
3290         int howmany, i;
3291
3292         ug_info = ugeth->ug_info;
3293
3294         /* Tx event processing */
3295         spin_lock(&ugeth->lock);
3296         for (i = 0; i < ug_info->numQueuesTx; i++)
3297                 ucc_geth_tx(ugeth->ndev, i);
3298         spin_unlock(&ugeth->lock);
3299
3300         howmany = 0;
3301         for (i = 0; i < ug_info->numQueuesRx; i++)
3302                 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3303
3304         if (howmany < budget) {
3305                 napi_complete(napi);
3306                 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3307         }
3308
3309         return howmany;
3310 }
3311
3312 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3313 {
3314         struct net_device *dev = info;
3315         struct ucc_geth_private *ugeth = netdev_priv(dev);
3316         struct ucc_fast_private *uccf;
3317         struct ucc_geth_info *ug_info;
3318         register u32 ucce;
3319         register u32 uccm;
3320
3321         ugeth_vdbg("%s: IN", __func__);
3322
3323         uccf = ugeth->uccf;
3324         ug_info = ugeth->ug_info;
3325
3326         /* read and clear events */
3327         ucce = (u32) in_be32(uccf->p_ucce);
3328         uccm = (u32) in_be32(uccf->p_uccm);
3329         ucce &= uccm;
3330         out_be32(uccf->p_ucce, ucce);
3331
3332         /* check for receive events that require processing */
3333         if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3334                 if (napi_schedule_prep(&ugeth->napi)) {
3335                         uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3336                         out_be32(uccf->p_uccm, uccm);
3337                         __napi_schedule(&ugeth->napi);
3338                 }
3339         }
3340
3341         /* Errors and other events */
3342         if (ucce & UCCE_OTHER) {
3343                 if (ucce & UCC_GETH_UCCE_BSY)
3344                         dev->stats.rx_errors++;
3345                 if (ucce & UCC_GETH_UCCE_TXE)
3346                         dev->stats.tx_errors++;
3347         }
3348
3349         return IRQ_HANDLED;
3350 }
3351
3352 #ifdef CONFIG_NET_POLL_CONTROLLER
3353 /*
3354  * Polling 'interrupt' - used by things like netconsole to send skbs
3355  * without having to re-enable interrupts. It's not called while
3356  * the interrupt routine is executing.
3357  */
3358 static void ucc_netpoll(struct net_device *dev)
3359 {
3360         struct ucc_geth_private *ugeth = netdev_priv(dev);
3361         int irq = ugeth->ug_info->uf_info.irq;
3362
3363         disable_irq(irq);
3364         ucc_geth_irq_handler(irq, dev);
3365         enable_irq(irq);
3366 }
3367 #endif /* CONFIG_NET_POLL_CONTROLLER */
3368
3369 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3370 {
3371         struct ucc_geth_private *ugeth = netdev_priv(dev);
3372         struct sockaddr *addr = p;
3373
3374         if (!is_valid_ether_addr(addr->sa_data))
3375                 return -EADDRNOTAVAIL;
3376
3377         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3378
3379         /*
3380          * If device is not running, we will set mac addr register
3381          * when opening the device.
3382          */
3383         if (!netif_running(dev))
3384                 return 0;
3385
3386         spin_lock_irq(&ugeth->lock);
3387         init_mac_station_addr_regs(dev->dev_addr[0],
3388                                    dev->dev_addr[1],
3389                                    dev->dev_addr[2],
3390                                    dev->dev_addr[3],
3391                                    dev->dev_addr[4],
3392                                    dev->dev_addr[5],
3393                                    &ugeth->ug_regs->macstnaddr1,
3394                                    &ugeth->ug_regs->macstnaddr2);
3395         spin_unlock_irq(&ugeth->lock);
3396
3397         return 0;
3398 }
3399
3400 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3401 {
3402         struct net_device *dev = ugeth->ndev;
3403         int err;
3404
3405         err = ucc_struct_init(ugeth);
3406         if (err) {
3407                 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n");
3408                 goto err;
3409         }
3410
3411         err = ucc_geth_startup(ugeth);
3412         if (err) {
3413                 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3414                 goto err;
3415         }
3416
3417         err = adjust_enet_interface(ugeth);
3418         if (err) {
3419                 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3420                 goto err;
3421         }
3422
3423         /*       Set MACSTNADDR1, MACSTNADDR2                */
3424         /* For more details see the hardware spec.           */
3425         init_mac_station_addr_regs(dev->dev_addr[0],
3426                                    dev->dev_addr[1],
3427                                    dev->dev_addr[2],
3428                                    dev->dev_addr[3],
3429                                    dev->dev_addr[4],
3430                                    dev->dev_addr[5],
3431                                    &ugeth->ug_regs->macstnaddr1,
3432                                    &ugeth->ug_regs->macstnaddr2);
3433
3434         err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3435         if (err) {
3436                 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n");
3437                 goto err;
3438         }
3439
3440         return 0;
3441 err:
3442         ucc_geth_stop(ugeth);
3443         return err;
3444 }
3445
3446 /* Called when something needs to use the ethernet device */
3447 /* Returns 0 for success. */
3448 static int ucc_geth_open(struct net_device *dev)
3449 {
3450         struct ucc_geth_private *ugeth = netdev_priv(dev);
3451         int err;
3452
3453         ugeth_vdbg("%s: IN", __func__);
3454
3455         /* Test station address */
3456         if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3457                 netif_err(ugeth, ifup, dev,
3458                           "Multicast address used for station address - is this what you wanted?\n");
3459                 return -EINVAL;
3460         }
3461
3462         err = init_phy(dev);
3463         if (err) {
3464                 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n");
3465                 return err;
3466         }
3467
3468         err = ucc_geth_init_mac(ugeth);
3469         if (err) {
3470                 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n");
3471                 goto err;
3472         }
3473
3474         err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3475                           0, "UCC Geth", dev);
3476         if (err) {
3477                 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n");
3478                 goto err;
3479         }
3480
3481         phy_start(ugeth->phydev);
3482         napi_enable(&ugeth->napi);
3483         netif_start_queue(dev);
3484
3485         device_set_wakeup_capable(&dev->dev,
3486                         qe_alive_during_sleep() || ugeth->phydev->irq);
3487         device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3488
3489         return err;
3490
3491 err:
3492         ucc_geth_stop(ugeth);
3493         return err;
3494 }
3495
3496 /* Stops the kernel queue, and halts the controller */
3497 static int ucc_geth_close(struct net_device *dev)
3498 {
3499         struct ucc_geth_private *ugeth = netdev_priv(dev);
3500
3501         ugeth_vdbg("%s: IN", __func__);
3502
3503         napi_disable(&ugeth->napi);
3504
3505         cancel_work_sync(&ugeth->timeout_work);
3506         ucc_geth_stop(ugeth);
3507         phy_disconnect(ugeth->phydev);
3508         ugeth->phydev = NULL;
3509
3510         free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3511
3512         netif_stop_queue(dev);
3513
3514         return 0;
3515 }
3516
3517 /* Reopen device. This will reset the MAC and PHY. */
3518 static void ucc_geth_timeout_work(struct work_struct *work)
3519 {
3520         struct ucc_geth_private *ugeth;
3521         struct net_device *dev;
3522
3523         ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3524         dev = ugeth->ndev;
3525
3526         ugeth_vdbg("%s: IN", __func__);
3527
3528         dev->stats.tx_errors++;
3529
3530         ugeth_dump_regs(ugeth);
3531
3532         if (dev->flags & IFF_UP) {
3533                 /*
3534                  * Must reset MAC *and* PHY. This is done by reopening
3535                  * the device.
3536                  */
3537                 netif_tx_stop_all_queues(dev);
3538                 ucc_geth_stop(ugeth);
3539                 ucc_geth_init_mac(ugeth);
3540                 /* Must start PHY here */
3541                 phy_start(ugeth->phydev);
3542                 netif_tx_start_all_queues(dev);
3543         }
3544
3545         netif_tx_schedule_all(dev);
3546 }
3547
3548 /*
3549  * ucc_geth_timeout gets called when a packet has not been
3550  * transmitted after a set amount of time.
3551  */
3552 static void ucc_geth_timeout(struct net_device *dev)
3553 {
3554         struct ucc_geth_private *ugeth = netdev_priv(dev);
3555
3556         schedule_work(&ugeth->timeout_work);
3557 }
3558
3559
3560 #ifdef CONFIG_PM
3561
3562 static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
3563 {
3564         struct net_device *ndev = platform_get_drvdata(ofdev);
3565         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3566
3567         if (!netif_running(ndev))
3568                 return 0;
3569
3570         netif_device_detach(ndev);
3571         napi_disable(&ugeth->napi);
3572
3573         /*
3574          * Disable the controller, otherwise we'll wakeup on any network
3575          * activity.
3576          */
3577         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3578
3579         if (ugeth->wol_en & WAKE_MAGIC) {
3580                 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3581                 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3582                 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3583         } else if (!(ugeth->wol_en & WAKE_PHY)) {
3584                 phy_stop(ugeth->phydev);
3585         }
3586
3587         return 0;
3588 }
3589
3590 static int ucc_geth_resume(struct platform_device *ofdev)
3591 {
3592         struct net_device *ndev = platform_get_drvdata(ofdev);
3593         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3594         int err;
3595
3596         if (!netif_running(ndev))
3597                 return 0;
3598
3599         if (qe_alive_during_sleep()) {
3600                 if (ugeth->wol_en & WAKE_MAGIC) {
3601                         ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3602                         clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3603                         clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3604                 }
3605                 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3606         } else {
3607                 /*
3608                  * Full reinitialization is required if QE shuts down
3609                  * during sleep.
3610                  */
3611                 ucc_geth_memclean(ugeth);
3612
3613                 err = ucc_geth_init_mac(ugeth);
3614                 if (err) {
3615                         netdev_err(ndev, "Cannot initialize MAC, aborting\n");
3616                         return err;
3617                 }
3618         }
3619
3620         ugeth->oldlink = 0;
3621         ugeth->oldspeed = 0;
3622         ugeth->oldduplex = -1;
3623
3624         phy_stop(ugeth->phydev);
3625         phy_start(ugeth->phydev);
3626
3627         napi_enable(&ugeth->napi);
3628         netif_device_attach(ndev);
3629
3630         return 0;
3631 }
3632
3633 #else
3634 #define ucc_geth_suspend NULL
3635 #define ucc_geth_resume NULL
3636 #endif
3637
3638 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3639 {
3640         if (strcasecmp(phy_connection_type, "mii") == 0)
3641                 return PHY_INTERFACE_MODE_MII;
3642         if (strcasecmp(phy_connection_type, "gmii") == 0)
3643                 return PHY_INTERFACE_MODE_GMII;
3644         if (strcasecmp(phy_connection_type, "tbi") == 0)
3645                 return PHY_INTERFACE_MODE_TBI;
3646         if (strcasecmp(phy_connection_type, "rmii") == 0)
3647                 return PHY_INTERFACE_MODE_RMII;
3648         if (strcasecmp(phy_connection_type, "rgmii") == 0)
3649                 return PHY_INTERFACE_MODE_RGMII;
3650         if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3651                 return PHY_INTERFACE_MODE_RGMII_ID;
3652         if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3653                 return PHY_INTERFACE_MODE_RGMII_TXID;
3654         if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3655                 return PHY_INTERFACE_MODE_RGMII_RXID;
3656         if (strcasecmp(phy_connection_type, "rtbi") == 0)
3657                 return PHY_INTERFACE_MODE_RTBI;
3658         if (strcasecmp(phy_connection_type, "sgmii") == 0)
3659                 return PHY_INTERFACE_MODE_SGMII;
3660
3661         return PHY_INTERFACE_MODE_MII;
3662 }
3663
3664 static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3665 {
3666         struct ucc_geth_private *ugeth = netdev_priv(dev);
3667
3668         if (!netif_running(dev))
3669                 return -EINVAL;
3670
3671         if (!ugeth->phydev)
3672                 return -ENODEV;
3673
3674         return phy_mii_ioctl(ugeth->phydev, rq, cmd);
3675 }
3676
3677 static const struct net_device_ops ucc_geth_netdev_ops = {
3678         .ndo_open               = ucc_geth_open,
3679         .ndo_stop               = ucc_geth_close,
3680         .ndo_start_xmit         = ucc_geth_start_xmit,
3681         .ndo_validate_addr      = eth_validate_addr,
3682         .ndo_set_mac_address    = ucc_geth_set_mac_addr,
3683         .ndo_change_mtu         = eth_change_mtu,
3684         .ndo_set_rx_mode        = ucc_geth_set_multi,
3685         .ndo_tx_timeout         = ucc_geth_timeout,
3686         .ndo_do_ioctl           = ucc_geth_ioctl,
3687 #ifdef CONFIG_NET_POLL_CONTROLLER
3688         .ndo_poll_controller    = ucc_netpoll,
3689 #endif
3690 };
3691
3692 static int ucc_geth_probe(struct platform_device* ofdev)
3693 {
3694         struct device *device = &ofdev->dev;
3695         struct device_node *np = ofdev->dev.of_node;
3696         struct net_device *dev = NULL;
3697         struct ucc_geth_private *ugeth = NULL;
3698         struct ucc_geth_info *ug_info;
3699         struct resource res;
3700         int err, ucc_num, max_speed = 0;
3701         const unsigned int *prop;
3702         const char *sprop;
3703         const void *mac_addr;
3704         phy_interface_t phy_interface;
3705         static const int enet_to_speed[] = {
3706                 SPEED_10, SPEED_10, SPEED_10,
3707                 SPEED_100, SPEED_100, SPEED_100,
3708                 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3709         };
3710         static const phy_interface_t enet_to_phy_interface[] = {
3711                 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3712                 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3713                 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3714                 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3715                 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3716                 PHY_INTERFACE_MODE_SGMII,
3717         };
3718
3719         ugeth_vdbg("%s: IN", __func__);
3720
3721         prop = of_get_property(np, "cell-index", NULL);
3722         if (!prop) {
3723                 prop = of_get_property(np, "device-id", NULL);
3724                 if (!prop)
3725                         return -ENODEV;
3726         }
3727
3728         ucc_num = *prop - 1;
3729         if ((ucc_num < 0) || (ucc_num > 7))
3730                 return -ENODEV;
3731
3732         ug_info = &ugeth_info[ucc_num];
3733         if (ug_info == NULL) {
3734                 if (netif_msg_probe(&debug))
3735                         pr_err("[%d] Missing additional data!\n", ucc_num);
3736                 return -ENODEV;
3737         }
3738
3739         ug_info->uf_info.ucc_num = ucc_num;
3740
3741         sprop = of_get_property(np, "rx-clock-name", NULL);
3742         if (sprop) {
3743                 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3744                 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3745                     (ug_info->uf_info.rx_clock > QE_CLK24)) {
3746                         pr_err("invalid rx-clock-name property\n");
3747                         return -EINVAL;
3748                 }
3749         } else {
3750                 prop = of_get_property(np, "rx-clock", NULL);
3751                 if (!prop) {
3752                         /* If both rx-clock-name and rx-clock are missing,
3753                            we want to tell people to use rx-clock-name. */
3754                         pr_err("missing rx-clock-name property\n");
3755                         return -EINVAL;
3756                 }
3757                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3758                         pr_err("invalid rx-clock propperty\n");
3759                         return -EINVAL;
3760                 }
3761                 ug_info->uf_info.rx_clock = *prop;
3762         }
3763
3764         sprop = of_get_property(np, "tx-clock-name", NULL);
3765         if (sprop) {
3766                 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3767                 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3768                     (ug_info->uf_info.tx_clock > QE_CLK24)) {
3769                         pr_err("invalid tx-clock-name property\n");
3770                         return -EINVAL;
3771                 }
3772         } else {
3773                 prop = of_get_property(np, "tx-clock", NULL);
3774                 if (!prop) {
3775                         pr_err("missing tx-clock-name property\n");
3776                         return -EINVAL;
3777                 }
3778                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3779                         pr_err("invalid tx-clock property\n");
3780                         return -EINVAL;
3781                 }
3782                 ug_info->uf_info.tx_clock = *prop;
3783         }
3784
3785         err = of_address_to_resource(np, 0, &res);
3786         if (err)
3787                 return -EINVAL;
3788
3789         ug_info->uf_info.regs = res.start;
3790         ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3791
3792         ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3793
3794         /* Find the TBI PHY node.  If it's not there, we don't support SGMII */
3795         ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3796
3797         /* get the phy interface type, or default to MII */
3798         prop = of_get_property(np, "phy-connection-type", NULL);
3799         if (!prop) {
3800                 /* handle interface property present in old trees */
3801                 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3802                 if (prop != NULL) {
3803                         phy_interface = enet_to_phy_interface[*prop];
3804                         max_speed = enet_to_speed[*prop];
3805                 } else
3806                         phy_interface = PHY_INTERFACE_MODE_MII;
3807         } else {
3808                 phy_interface = to_phy_interface((const char *)prop);
3809         }
3810
3811         /* get speed, or derive from PHY interface */
3812         if (max_speed == 0)
3813                 switch (phy_interface) {
3814                 case PHY_INTERFACE_MODE_GMII:
3815                 case PHY_INTERFACE_MODE_RGMII:
3816                 case PHY_INTERFACE_MODE_RGMII_ID:
3817                 case PHY_INTERFACE_MODE_RGMII_RXID:
3818                 case PHY_INTERFACE_MODE_RGMII_TXID:
3819                 case PHY_INTERFACE_MODE_TBI:
3820                 case PHY_INTERFACE_MODE_RTBI:
3821                 case PHY_INTERFACE_MODE_SGMII:
3822                         max_speed = SPEED_1000;
3823                         break;
3824                 default:
3825                         max_speed = SPEED_100;
3826                         break;
3827                 }
3828
3829         if (max_speed == SPEED_1000) {
3830                 unsigned int snums = qe_get_num_of_snums();
3831
3832                 /* configure muram FIFOs for gigabit operation */
3833                 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3834                 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3835                 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3836                 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3837                 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3838                 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3839                 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3840
3841                 /* If QE's snum number is 46/76 which means we need to support
3842                  * 4 UECs at 1000Base-T simultaneously, we need to allocate
3843                  * more Threads to Rx.
3844                  */
3845                 if ((snums == 76) || (snums == 46))
3846                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3847                 else
3848                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3849         }
3850
3851         if (netif_msg_probe(&debug))
3852                 pr_info("UCC%1d at 0x%8x (irq = %d)\n",
3853                         ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3854                         ug_info->uf_info.irq);
3855
3856         /* Create an ethernet device instance */
3857         dev = alloc_etherdev(sizeof(*ugeth));
3858
3859         if (dev == NULL)
3860                 return -ENOMEM;
3861
3862         ugeth = netdev_priv(dev);
3863         spin_lock_init(&ugeth->lock);
3864
3865         /* Create CQs for hash tables */
3866         INIT_LIST_HEAD(&ugeth->group_hash_q);
3867         INIT_LIST_HEAD(&ugeth->ind_hash_q);
3868
3869         dev_set_drvdata(device, dev);
3870
3871         /* Set the dev->base_addr to the gfar reg region */
3872         dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3873
3874         SET_NETDEV_DEV(dev, device);
3875
3876         /* Fill in the dev structure */
3877         uec_set_ethtool_ops(dev);
3878         dev->netdev_ops = &ucc_geth_netdev_ops;
3879         dev->watchdog_timeo = TX_TIMEOUT;
3880         INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3881         netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3882         dev->mtu = 1500;
3883
3884         ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3885         ugeth->phy_interface = phy_interface;
3886         ugeth->max_speed = max_speed;
3887
3888         err = register_netdev(dev);
3889         if (err) {
3890                 if (netif_msg_probe(ugeth))
3891                         pr_err("%s: Cannot register net device, aborting\n",
3892                                dev->name);
3893                 free_netdev(dev);
3894                 return err;
3895         }
3896
3897         mac_addr = of_get_mac_address(np);
3898         if (mac_addr)
3899                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
3900
3901         ugeth->ug_info = ug_info;
3902         ugeth->dev = device;
3903         ugeth->ndev = dev;
3904         ugeth->node = np;
3905
3906         return 0;
3907 }
3908
3909 static int ucc_geth_remove(struct platform_device* ofdev)
3910 {
3911         struct net_device *dev = platform_get_drvdata(ofdev);
3912         struct ucc_geth_private *ugeth = netdev_priv(dev);
3913
3914         unregister_netdev(dev);
3915         free_netdev(dev);
3916         ucc_geth_memclean(ugeth);
3917
3918         return 0;
3919 }
3920
3921 static struct of_device_id ucc_geth_match[] = {
3922         {
3923                 .type = "network",
3924                 .compatible = "ucc_geth",
3925         },
3926         {},
3927 };
3928
3929 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3930
3931 static struct platform_driver ucc_geth_driver = {
3932         .driver = {
3933                 .name = DRV_NAME,
3934                 .owner = THIS_MODULE,
3935                 .of_match_table = ucc_geth_match,
3936         },
3937         .probe          = ucc_geth_probe,
3938         .remove         = ucc_geth_remove,
3939         .suspend        = ucc_geth_suspend,
3940         .resume         = ucc_geth_resume,
3941 };
3942
3943 static int __init ucc_geth_init(void)
3944 {
3945         int i, ret;
3946
3947         if (netif_msg_drv(&debug))
3948                 pr_info(DRV_DESC "\n");
3949         for (i = 0; i < 8; i++)
3950                 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3951                        sizeof(ugeth_primary_info));
3952
3953         ret = platform_driver_register(&ucc_geth_driver);
3954
3955         return ret;
3956 }
3957
3958 static void __exit ucc_geth_exit(void)
3959 {
3960         platform_driver_unregister(&ucc_geth_driver);
3961 }
3962
3963 module_init(ucc_geth_init);
3964 module_exit(ucc_geth_exit);
3965
3966 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3967 MODULE_DESCRIPTION(DRV_DESC);
3968 MODULE_VERSION(DRV_VERSION);
3969 MODULE_LICENSE("GPL");