2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/regulator/consumer.h>
57 #include <linux/if_vlan.h>
59 #include <asm/cacheflush.h>
63 static void set_multicast_list(struct net_device *ndev);
65 #if defined(CONFIG_ARM)
66 #define FEC_ALIGNMENT 0xf
68 #define FEC_ALIGNMENT 0x3
71 #define DRIVER_NAME "fec"
72 #define FEC_NAPI_WEIGHT 64
74 /* Pause frame feild and FIFO threshold */
75 #define FEC_ENET_FCE (1 << 5)
76 #define FEC_ENET_RSEM_V 0x84
77 #define FEC_ENET_RSFL_V 16
78 #define FEC_ENET_RAEM_V 0x8
79 #define FEC_ENET_RAFL_V 0x8
80 #define FEC_ENET_OPD_V 0xFFF0
82 /* Controller is ENET-MAC */
83 #define FEC_QUIRK_ENET_MAC (1 << 0)
84 /* Controller needs driver to swap frame */
85 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
86 /* Controller uses gasket */
87 #define FEC_QUIRK_USE_GASKET (1 << 2)
88 /* Controller has GBIT support */
89 #define FEC_QUIRK_HAS_GBIT (1 << 3)
90 /* Controller has extend desc buffer */
91 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
92 /* Controller has hardware checksum support */
93 #define FEC_QUIRK_HAS_CSUM (1 << 5)
94 /* Controller has hardware vlan support */
95 #define FEC_QUIRK_HAS_VLAN (1 << 6)
96 /* ENET IP errata ERR006358
98 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
99 * detected as not set during a prior frame transmission, then the
100 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
101 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
102 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
103 * detected as not set during a prior frame transmission, then the
104 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
105 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
106 * frames not being transmitted until there is a 0-to-1 transition on
109 #define FEC_QUIRK_ERR006358 (1 << 7)
111 static struct platform_device_id fec_devtype[] = {
113 /* keep it for coldfire */
118 .driver_data = FEC_QUIRK_USE_GASKET,
124 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
127 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
128 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
129 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
131 .name = "mvf600-fec",
132 .driver_data = FEC_QUIRK_ENET_MAC,
137 MODULE_DEVICE_TABLE(platform, fec_devtype);
140 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
141 IMX27_FEC, /* runs on i.mx27/35/51 */
147 static const struct of_device_id fec_dt_ids[] = {
148 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
149 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
150 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
151 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
152 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
155 MODULE_DEVICE_TABLE(of, fec_dt_ids);
157 static unsigned char macaddr[ETH_ALEN];
158 module_param_array(macaddr, byte, NULL, 0);
159 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
161 #if defined(CONFIG_M5272)
163 * Some hardware gets it MAC address out of local flash memory.
164 * if this is non-zero then assume it is the address to get MAC from.
166 #if defined(CONFIG_NETtel)
167 #define FEC_FLASHMAC 0xf0006006
168 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
169 #define FEC_FLASHMAC 0xf0006000
170 #elif defined(CONFIG_CANCam)
171 #define FEC_FLASHMAC 0xf0020000
172 #elif defined (CONFIG_M5272C3)
173 #define FEC_FLASHMAC (0xffe04000 + 4)
174 #elif defined(CONFIG_MOD5272)
175 #define FEC_FLASHMAC 0xffc0406b
177 #define FEC_FLASHMAC 0
179 #endif /* CONFIG_M5272 */
181 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
182 #error "FEC: descriptor ring size constants too large"
185 /* Interrupt events/masks. */
186 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
187 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
188 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
189 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
190 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
191 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
192 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
193 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
194 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
195 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
197 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
198 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
200 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
202 #define PKT_MAXBUF_SIZE 1522
203 #define PKT_MINBUF_SIZE 64
204 #define PKT_MAXBLR_SIZE 1536
206 /* FEC receive acceleration */
207 #define FEC_RACC_IPDIS (1 << 1)
208 #define FEC_RACC_PRODIS (1 << 2)
209 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
212 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
213 * size bits. Other FEC hardware does not, so we need to take that into
214 * account when setting it.
216 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
217 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
218 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
220 #define OPT_FRAME_SIZE 0
223 /* FEC MII MMFR bits definition */
224 #define FEC_MMFR_ST (1 << 30)
225 #define FEC_MMFR_OP_READ (2 << 28)
226 #define FEC_MMFR_OP_WRITE (1 << 28)
227 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
228 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
229 #define FEC_MMFR_TA (2 << 16)
230 #define FEC_MMFR_DATA(v) (v & 0xffff)
232 #define FEC_MII_TIMEOUT 30000 /* us */
234 /* Transmitter timeout */
235 #define TX_TIMEOUT (2 * HZ)
237 #define FEC_PAUSE_FLAG_AUTONEG 0x1
238 #define FEC_PAUSE_FLAG_ENABLE 0x2
242 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
244 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
246 return (struct bufdesc *)(ex + 1);
251 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
253 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
255 return (struct bufdesc *)(ex - 1);
260 static void *swap_buffer(void *bufaddr, int len)
263 unsigned int *buf = bufaddr;
265 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
266 *buf = cpu_to_be32(*buf);
272 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
274 /* Only run for packets requiring a checksum. */
275 if (skb->ip_summed != CHECKSUM_PARTIAL)
278 if (unlikely(skb_cow_head(skb, 0)))
281 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
287 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
289 struct fec_enet_private *fep = netdev_priv(ndev);
290 const struct platform_device_id *id_entry =
291 platform_get_device_id(fep->pdev);
292 struct bufdesc *bdp, *bdp_pre;
294 unsigned short status;
298 /* Link is down or auto-negotiation is in progress. */
299 return NETDEV_TX_BUSY;
302 /* Fill in a Tx ring entry */
305 status = bdp->cbd_sc;
307 if (status & BD_ENET_TX_READY) {
308 /* Ooops. All transmit buffers are full. Bail out.
309 * This should not happen, since ndev->tbusy should be set.
311 netdev_err(ndev, "tx queue full!\n");
312 return NETDEV_TX_BUSY;
315 /* Protocol checksum off-load for TCP and UDP. */
316 if (fec_enet_clear_csum(skb, ndev)) {
321 /* Clear all of the status flags */
322 status &= ~BD_ENET_TX_STATS;
324 /* Set buffer length and buffer pointer */
326 bdp->cbd_datlen = skb->len;
329 * On some FEC implementations data must be aligned on
330 * 4-byte boundaries. Use bounce buffers to copy data
331 * and get it aligned. Ugh.
334 index = (struct bufdesc_ex *)bdp -
335 (struct bufdesc_ex *)fep->tx_bd_base;
337 index = bdp - fep->tx_bd_base;
339 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
340 memcpy(fep->tx_bounce[index], skb->data, skb->len);
341 bufaddr = fep->tx_bounce[index];
345 * Some design made an incorrect assumption on endian mode of
346 * the system that it's running on. As the result, driver has to
347 * swap every frame going to and coming from the controller.
349 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
350 swap_buffer(bufaddr, skb->len);
352 /* Save skb pointer */
353 fep->tx_skbuff[index] = skb;
355 /* Push the data cache so the CPM does not get stale memory
358 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
359 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
361 /* Send it on its way. Tell FEC it's ready, interrupt when done,
362 * it's the last BD of the frame, and to put the CRC on the end.
364 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
365 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
366 bdp->cbd_sc = status;
368 if (fep->bufdesc_ex) {
370 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
372 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
374 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
375 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
377 ebdp->cbd_esc = BD_ENET_TX_INT;
379 /* Enable protocol checksum flags
380 * We do not bother with the IP Checksum bits as they
381 * are done by the kernel
383 if (skb->ip_summed == CHECKSUM_PARTIAL)
384 ebdp->cbd_esc |= BD_ENET_TX_PINS;
388 bdp_pre = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
389 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
390 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
391 fep->delay_work.trig_tx = true;
392 schedule_delayed_work(&(fep->delay_work.delay_work),
393 msecs_to_jiffies(1));
396 /* If this was the last BD in the ring, start at the beginning again. */
397 if (status & BD_ENET_TX_WRAP)
398 bdp = fep->tx_bd_base;
400 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
404 if (fep->cur_tx == fep->dirty_tx)
405 netif_stop_queue(ndev);
407 /* Trigger transmission start */
408 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
410 skb_tx_timestamp(skb);
415 /* Init RX & TX buffer descriptors
417 static void fec_enet_bd_init(struct net_device *dev)
419 struct fec_enet_private *fep = netdev_priv(dev);
423 /* Initialize the receive buffer descriptors. */
424 bdp = fep->rx_bd_base;
425 for (i = 0; i < RX_RING_SIZE; i++) {
427 /* Initialize the BD for every fragment in the page. */
428 if (bdp->cbd_bufaddr)
429 bdp->cbd_sc = BD_ENET_RX_EMPTY;
432 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
435 /* Set the last buffer to wrap */
436 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
437 bdp->cbd_sc |= BD_SC_WRAP;
439 fep->cur_rx = fep->rx_bd_base;
441 /* ...and the same for transmit */
442 bdp = fep->tx_bd_base;
444 for (i = 0; i < TX_RING_SIZE; i++) {
446 /* Initialize the BD for every fragment in the page. */
448 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
449 dev_kfree_skb_any(fep->tx_skbuff[i]);
450 fep->tx_skbuff[i] = NULL;
452 bdp->cbd_bufaddr = 0;
453 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
456 /* Set the last buffer to wrap */
457 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
458 bdp->cbd_sc |= BD_SC_WRAP;
462 /* This function is called to start or restart the FEC during a link
463 * change. This only happens when switching between half and full
467 fec_restart(struct net_device *ndev, int duplex)
469 struct fec_enet_private *fep = netdev_priv(ndev);
470 const struct platform_device_id *id_entry =
471 platform_get_device_id(fep->pdev);
475 u32 rcntl = OPT_FRAME_SIZE | 0x04;
476 u32 ecntl = 0x2; /* ETHEREN */
478 if (netif_running(ndev)) {
479 netif_device_detach(ndev);
480 napi_disable(&fep->napi);
481 netif_stop_queue(ndev);
482 netif_tx_lock_bh(ndev);
485 /* Whack a reset. We should wait for this. */
486 writel(1, fep->hwp + FEC_ECNTRL);
490 * enet-mac reset will reset mac address registers too,
491 * so need to reconfigure it.
493 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
494 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
495 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
496 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
499 /* Clear any outstanding interrupt. */
500 writel(0xffc00000, fep->hwp + FEC_IEVENT);
502 /* Setup multicast filter. */
503 set_multicast_list(ndev);
505 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
506 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
509 /* Set maximum receive buffer size. */
510 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
512 fec_enet_bd_init(ndev);
514 /* Set receive and transmit descriptor base. */
515 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
517 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
518 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
520 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
521 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
524 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
525 if (fep->tx_skbuff[i]) {
526 dev_kfree_skb_any(fep->tx_skbuff[i]);
527 fep->tx_skbuff[i] = NULL;
531 /* Enable MII mode */
534 writel(0x04, fep->hwp + FEC_X_CNTRL);
538 writel(0x0, fep->hwp + FEC_X_CNTRL);
541 fep->full_duplex = duplex;
544 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
546 #if !defined(CONFIG_M5272)
547 /* set RX checksum */
548 val = readl(fep->hwp + FEC_RACC);
549 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
550 val |= FEC_RACC_OPTIONS;
552 val &= ~FEC_RACC_OPTIONS;
553 writel(val, fep->hwp + FEC_RACC);
557 * The phy interface and speed need to get configured
558 * differently on enet-mac.
560 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
561 /* Enable flow control and length check */
562 rcntl |= 0x40000000 | 0x00000020;
564 /* RGMII, RMII or MII */
565 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
567 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
572 /* 1G, 100M or 10M */
574 if (fep->phy_dev->speed == SPEED_1000)
576 else if (fep->phy_dev->speed == SPEED_100)
582 #ifdef FEC_MIIGSK_ENR
583 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
585 /* disable the gasket and wait */
586 writel(0, fep->hwp + FEC_MIIGSK_ENR);
587 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
591 * configure the gasket:
592 * RMII, 50 MHz, no loopback, no echo
593 * MII, 25 MHz, no loopback, no echo
595 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
596 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
597 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
598 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
599 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
601 /* re-enable the gasket */
602 writel(2, fep->hwp + FEC_MIIGSK_ENR);
607 #if !defined(CONFIG_M5272)
608 /* enable pause frame*/
609 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
610 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
611 fep->phy_dev && fep->phy_dev->pause)) {
612 rcntl |= FEC_ENET_FCE;
614 /* set FIFO threshold parameter to reduce overrun */
615 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
616 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
617 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
618 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
621 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
623 rcntl &= ~FEC_ENET_FCE;
625 #endif /* !defined(CONFIG_M5272) */
627 writel(rcntl, fep->hwp + FEC_R_CNTRL);
629 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
630 /* enable ENET endian swap */
632 /* enable ENET store and forward mode */
633 writel(1 << 8, fep->hwp + FEC_X_WMRK);
640 /* Enable the MIB statistic event counters */
641 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
644 /* And last, enable the transmit and receive processing */
645 writel(ecntl, fep->hwp + FEC_ECNTRL);
646 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
649 fec_ptp_start_cyclecounter(ndev);
651 /* Enable interrupts we wish to service */
652 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
654 if (netif_running(ndev)) {
655 netif_tx_unlock_bh(ndev);
656 netif_wake_queue(ndev);
657 napi_enable(&fep->napi);
658 netif_device_attach(ndev);
663 fec_stop(struct net_device *ndev)
665 struct fec_enet_private *fep = netdev_priv(ndev);
666 const struct platform_device_id *id_entry =
667 platform_get_device_id(fep->pdev);
668 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
670 /* We cannot expect a graceful transmit stop without link !!! */
672 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
674 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
675 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
678 /* Whack a reset. We should wait for this. */
679 writel(1, fep->hwp + FEC_ECNTRL);
681 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
682 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
684 /* We have to keep ENET enabled to have MII interrupt stay working */
685 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
686 writel(2, fep->hwp + FEC_ECNTRL);
687 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
693 fec_timeout(struct net_device *ndev)
695 struct fec_enet_private *fep = netdev_priv(ndev);
697 ndev->stats.tx_errors++;
699 fep->delay_work.timeout = true;
700 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
703 static void fec_enet_work(struct work_struct *work)
705 struct fec_enet_private *fep =
707 struct fec_enet_private,
708 delay_work.delay_work.work);
710 if (fep->delay_work.timeout) {
711 fep->delay_work.timeout = false;
712 fec_restart(fep->netdev, fep->full_duplex);
713 netif_wake_queue(fep->netdev);
716 if (fep->delay_work.trig_tx) {
717 fep->delay_work.trig_tx = false;
718 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
723 fec_enet_tx(struct net_device *ndev)
725 struct fec_enet_private *fep;
727 unsigned short status;
731 fep = netdev_priv(ndev);
734 /* get next bdp of dirty_tx */
735 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
736 bdp = fep->tx_bd_base;
738 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
740 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
742 /* current queue is empty */
743 if (bdp == fep->cur_tx)
747 index = (struct bufdesc_ex *)bdp -
748 (struct bufdesc_ex *)fep->tx_bd_base;
750 index = bdp - fep->tx_bd_base;
752 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
753 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
754 bdp->cbd_bufaddr = 0;
756 skb = fep->tx_skbuff[index];
758 /* Check for errors. */
759 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
760 BD_ENET_TX_RL | BD_ENET_TX_UN |
762 ndev->stats.tx_errors++;
763 if (status & BD_ENET_TX_HB) /* No heartbeat */
764 ndev->stats.tx_heartbeat_errors++;
765 if (status & BD_ENET_TX_LC) /* Late collision */
766 ndev->stats.tx_window_errors++;
767 if (status & BD_ENET_TX_RL) /* Retrans limit */
768 ndev->stats.tx_aborted_errors++;
769 if (status & BD_ENET_TX_UN) /* Underrun */
770 ndev->stats.tx_fifo_errors++;
771 if (status & BD_ENET_TX_CSL) /* Carrier lost */
772 ndev->stats.tx_carrier_errors++;
774 ndev->stats.tx_packets++;
775 ndev->stats.tx_bytes += bdp->cbd_datlen;
778 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
780 struct skb_shared_hwtstamps shhwtstamps;
782 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
784 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
785 spin_lock_irqsave(&fep->tmreg_lock, flags);
786 shhwtstamps.hwtstamp = ns_to_ktime(
787 timecounter_cyc2time(&fep->tc, ebdp->ts));
788 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
789 skb_tstamp_tx(skb, &shhwtstamps);
792 if (status & BD_ENET_TX_READY)
793 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
795 /* Deferred means some collisions occurred during transmit,
796 * but we eventually sent the packet OK.
798 if (status & BD_ENET_TX_DEF)
799 ndev->stats.collisions++;
801 /* Free the sk buffer associated with this last transmit */
802 dev_kfree_skb_any(skb);
803 fep->tx_skbuff[index] = NULL;
807 /* Update pointer to next buffer descriptor to be transmitted */
808 if (status & BD_ENET_TX_WRAP)
809 bdp = fep->tx_bd_base;
811 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
813 /* Since we have freed up a buffer, the ring is no longer full
815 if (fep->dirty_tx != fep->cur_tx) {
816 if (netif_queue_stopped(ndev))
817 netif_wake_queue(ndev);
824 /* During a receive, the cur_rx points to the current incoming buffer.
825 * When we update through the ring, if the next incoming buffer has
826 * not been given to the system, we just set the empty indicator,
827 * effectively tossing the packet.
830 fec_enet_rx(struct net_device *ndev, int budget)
832 struct fec_enet_private *fep = netdev_priv(ndev);
833 const struct platform_device_id *id_entry =
834 platform_get_device_id(fep->pdev);
836 unsigned short status;
840 int pkt_received = 0;
841 struct bufdesc_ex *ebdp = NULL;
842 bool vlan_packet_rcvd = false;
849 /* First, grab all of the stats for the incoming packet.
850 * These get messed up if we get called due to a busy condition.
854 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
856 if (pkt_received >= budget)
860 /* Since we have allocated space to hold a complete frame,
861 * the last indicator should be set.
863 if ((status & BD_ENET_RX_LAST) == 0)
864 netdev_err(ndev, "rcv is not +last\n");
867 goto rx_processing_done;
869 /* Check for errors. */
870 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
871 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
872 ndev->stats.rx_errors++;
873 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
874 /* Frame too long or too short. */
875 ndev->stats.rx_length_errors++;
877 if (status & BD_ENET_RX_NO) /* Frame alignment */
878 ndev->stats.rx_frame_errors++;
879 if (status & BD_ENET_RX_CR) /* CRC Error */
880 ndev->stats.rx_crc_errors++;
881 if (status & BD_ENET_RX_OV) /* FIFO overrun */
882 ndev->stats.rx_fifo_errors++;
885 /* Report late collisions as a frame error.
886 * On this error, the BD is closed, but we don't know what we
887 * have in the buffer. So, just drop this frame on the floor.
889 if (status & BD_ENET_RX_CL) {
890 ndev->stats.rx_errors++;
891 ndev->stats.rx_frame_errors++;
892 goto rx_processing_done;
895 /* Process the incoming frame. */
896 ndev->stats.rx_packets++;
897 pkt_len = bdp->cbd_datlen;
898 ndev->stats.rx_bytes += pkt_len;
899 data = (__u8*)__va(bdp->cbd_bufaddr);
901 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
902 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
904 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
905 swap_buffer(data, pkt_len);
907 /* Extract the enhanced buffer descriptor */
910 ebdp = (struct bufdesc_ex *)bdp;
912 /* If this is a VLAN packet remove the VLAN Tag */
913 vlan_packet_rcvd = false;
914 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
915 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
916 /* Push and remove the vlan tag */
917 struct vlan_hdr *vlan_header =
918 (struct vlan_hdr *) (data + ETH_HLEN);
919 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
920 pkt_len -= VLAN_HLEN;
922 vlan_packet_rcvd = true;
925 /* This does 16 byte alignment, exactly what we need.
926 * The packet length includes FCS, but we don't want to
927 * include that when passing upstream as it messes up
928 * bridging applications.
930 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
932 if (unlikely(!skb)) {
933 ndev->stats.rx_dropped++;
935 int payload_offset = (2 * ETH_ALEN);
936 skb_reserve(skb, NET_IP_ALIGN);
937 skb_put(skb, pkt_len - 4); /* Make room */
939 /* Extract the frame data without the VLAN header. */
940 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
941 if (vlan_packet_rcvd)
942 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
943 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
944 data + payload_offset,
945 pkt_len - 4 - (2 * ETH_ALEN));
947 skb->protocol = eth_type_trans(skb, ndev);
949 /* Get receive timestamp from the skb */
950 if (fep->hwts_rx_en && fep->bufdesc_ex) {
951 struct skb_shared_hwtstamps *shhwtstamps =
955 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
957 spin_lock_irqsave(&fep->tmreg_lock, flags);
958 shhwtstamps->hwtstamp = ns_to_ktime(
959 timecounter_cyc2time(&fep->tc, ebdp->ts));
960 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
963 if (fep->bufdesc_ex &&
964 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
965 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
967 skb->ip_summed = CHECKSUM_UNNECESSARY;
969 skb_checksum_none_assert(skb);
973 /* Handle received VLAN packets */
974 if (vlan_packet_rcvd)
975 __vlan_hwaccel_put_tag(skb,
979 if (!skb_defer_rx_timestamp(skb))
980 napi_gro_receive(&fep->napi, skb);
983 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
984 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
986 /* Clear the status flags for this buffer */
987 status &= ~BD_ENET_RX_STATS;
989 /* Mark the buffer empty */
990 status |= BD_ENET_RX_EMPTY;
991 bdp->cbd_sc = status;
993 if (fep->bufdesc_ex) {
994 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
996 ebdp->cbd_esc = BD_ENET_RX_INT;
1001 /* Update BD pointer to next entry */
1002 if (status & BD_ENET_RX_WRAP)
1003 bdp = fep->rx_bd_base;
1005 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1006 /* Doing this here will keep the FEC running while we process
1007 * incoming frames. On a heavily loaded network, we should be
1008 * able to keep up at the expense of system resources.
1010 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1014 return pkt_received;
1018 fec_enet_interrupt(int irq, void *dev_id)
1020 struct net_device *ndev = dev_id;
1021 struct fec_enet_private *fep = netdev_priv(ndev);
1023 irqreturn_t ret = IRQ_NONE;
1026 int_events = readl(fep->hwp + FEC_IEVENT);
1027 writel(int_events, fep->hwp + FEC_IEVENT);
1029 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1032 /* Disable the RX interrupt */
1033 if (napi_schedule_prep(&fep->napi)) {
1034 writel(FEC_RX_DISABLED_IMASK,
1035 fep->hwp + FEC_IMASK);
1036 __napi_schedule(&fep->napi);
1040 if (int_events & FEC_ENET_MII) {
1042 complete(&fep->mdio_done);
1044 } while (int_events);
1049 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1051 struct net_device *ndev = napi->dev;
1052 int pkts = fec_enet_rx(ndev, budget);
1053 struct fec_enet_private *fep = netdev_priv(ndev);
1057 if (pkts < budget) {
1058 napi_complete(napi);
1059 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1064 /* ------------------------------------------------------------------------- */
1065 static void fec_get_mac(struct net_device *ndev)
1067 struct fec_enet_private *fep = netdev_priv(ndev);
1068 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1069 unsigned char *iap, tmpaddr[ETH_ALEN];
1072 * try to get mac address in following order:
1074 * 1) module parameter via kernel command line in form
1075 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1080 * 2) from device tree data
1082 if (!is_valid_ether_addr(iap)) {
1083 struct device_node *np = fep->pdev->dev.of_node;
1085 const char *mac = of_get_mac_address(np);
1087 iap = (unsigned char *) mac;
1092 * 3) from flash or fuse (via platform data)
1094 if (!is_valid_ether_addr(iap)) {
1097 iap = (unsigned char *)FEC_FLASHMAC;
1100 iap = (unsigned char *)&pdata->mac;
1105 * 4) FEC mac registers set by bootloader
1107 if (!is_valid_ether_addr(iap)) {
1108 *((unsigned long *) &tmpaddr[0]) =
1109 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
1110 *((unsigned short *) &tmpaddr[4]) =
1111 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1116 * 5) random mac address
1118 if (!is_valid_ether_addr(iap)) {
1119 /* Report it and use a random ethernet address instead */
1120 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1121 eth_hw_addr_random(ndev);
1122 netdev_info(ndev, "Using random MAC address: %pM\n",
1127 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1129 /* Adjust MAC if using macaddr */
1131 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1134 /* ------------------------------------------------------------------------- */
1139 static void fec_enet_adjust_link(struct net_device *ndev)
1141 struct fec_enet_private *fep = netdev_priv(ndev);
1142 struct phy_device *phy_dev = fep->phy_dev;
1143 int status_change = 0;
1145 /* Prevent a state halted on mii error */
1146 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1147 phy_dev->state = PHY_RESUMING;
1151 if (phy_dev->link) {
1153 fep->link = phy_dev->link;
1157 if (fep->full_duplex != phy_dev->duplex)
1160 if (phy_dev->speed != fep->speed) {
1161 fep->speed = phy_dev->speed;
1165 /* if any of the above changed restart the FEC */
1167 fec_restart(ndev, phy_dev->duplex);
1171 fep->link = phy_dev->link;
1177 phy_print_status(phy_dev);
1180 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1182 struct fec_enet_private *fep = bus->priv;
1183 unsigned long time_left;
1185 fep->mii_timeout = 0;
1186 init_completion(&fep->mdio_done);
1188 /* start a read op */
1189 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1190 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1191 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1193 /* wait for end of transfer */
1194 time_left = wait_for_completion_timeout(&fep->mdio_done,
1195 usecs_to_jiffies(FEC_MII_TIMEOUT));
1196 if (time_left == 0) {
1197 fep->mii_timeout = 1;
1198 netdev_err(fep->netdev, "MDIO read timeout\n");
1203 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1206 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1209 struct fec_enet_private *fep = bus->priv;
1210 unsigned long time_left;
1212 fep->mii_timeout = 0;
1213 init_completion(&fep->mdio_done);
1215 /* start a write op */
1216 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1217 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1218 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1219 fep->hwp + FEC_MII_DATA);
1221 /* wait for end of transfer */
1222 time_left = wait_for_completion_timeout(&fep->mdio_done,
1223 usecs_to_jiffies(FEC_MII_TIMEOUT));
1224 if (time_left == 0) {
1225 fep->mii_timeout = 1;
1226 netdev_err(fep->netdev, "MDIO write timeout\n");
1233 static int fec_enet_mdio_reset(struct mii_bus *bus)
1238 static int fec_enet_mii_probe(struct net_device *ndev)
1240 struct fec_enet_private *fep = netdev_priv(ndev);
1241 const struct platform_device_id *id_entry =
1242 platform_get_device_id(fep->pdev);
1243 struct phy_device *phy_dev = NULL;
1244 char mdio_bus_id[MII_BUS_ID_SIZE];
1245 char phy_name[MII_BUS_ID_SIZE + 3];
1247 int dev_id = fep->dev_id;
1249 fep->phy_dev = NULL;
1251 /* check for attached phy */
1252 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1253 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1255 if (fep->mii_bus->phy_map[phy_id] == NULL)
1257 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1261 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1265 if (phy_id >= PHY_MAX_ADDR) {
1266 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1267 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1271 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1272 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1273 fep->phy_interface);
1274 if (IS_ERR(phy_dev)) {
1275 netdev_err(ndev, "could not attach to PHY\n");
1276 return PTR_ERR(phy_dev);
1279 /* mask with MAC supported features */
1280 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1281 phy_dev->supported &= PHY_GBIT_FEATURES;
1282 #if !defined(CONFIG_M5272)
1283 phy_dev->supported |= SUPPORTED_Pause;
1287 phy_dev->supported &= PHY_BASIC_FEATURES;
1289 phy_dev->advertising = phy_dev->supported;
1291 fep->phy_dev = phy_dev;
1293 fep->full_duplex = 0;
1295 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1296 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1302 static int fec_enet_mii_init(struct platform_device *pdev)
1304 static struct mii_bus *fec0_mii_bus;
1305 struct net_device *ndev = platform_get_drvdata(pdev);
1306 struct fec_enet_private *fep = netdev_priv(ndev);
1307 const struct platform_device_id *id_entry =
1308 platform_get_device_id(fep->pdev);
1309 int err = -ENXIO, i;
1312 * The dual fec interfaces are not equivalent with enet-mac.
1313 * Here are the differences:
1315 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1316 * - fec0 acts as the 1588 time master while fec1 is slave
1317 * - external phys can only be configured by fec0
1319 * That is to say fec1 can not work independently. It only works
1320 * when fec0 is working. The reason behind this design is that the
1321 * second interface is added primarily for Switch mode.
1323 * Because of the last point above, both phys are attached on fec0
1324 * mdio interface in board design, and need to be configured by
1327 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1328 /* fec1 uses fec0 mii_bus */
1329 if (mii_cnt && fec0_mii_bus) {
1330 fep->mii_bus = fec0_mii_bus;
1337 fep->mii_timeout = 0;
1340 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1342 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1343 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1344 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1347 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1348 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1350 fep->phy_speed <<= 1;
1351 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1353 fep->mii_bus = mdiobus_alloc();
1354 if (fep->mii_bus == NULL) {
1359 fep->mii_bus->name = "fec_enet_mii_bus";
1360 fep->mii_bus->read = fec_enet_mdio_read;
1361 fep->mii_bus->write = fec_enet_mdio_write;
1362 fep->mii_bus->reset = fec_enet_mdio_reset;
1363 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1364 pdev->name, fep->dev_id + 1);
1365 fep->mii_bus->priv = fep;
1366 fep->mii_bus->parent = &pdev->dev;
1368 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1369 if (!fep->mii_bus->irq) {
1371 goto err_out_free_mdiobus;
1374 for (i = 0; i < PHY_MAX_ADDR; i++)
1375 fep->mii_bus->irq[i] = PHY_POLL;
1377 if (mdiobus_register(fep->mii_bus))
1378 goto err_out_free_mdio_irq;
1382 /* save fec0 mii_bus */
1383 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1384 fec0_mii_bus = fep->mii_bus;
1388 err_out_free_mdio_irq:
1389 kfree(fep->mii_bus->irq);
1390 err_out_free_mdiobus:
1391 mdiobus_free(fep->mii_bus);
1396 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1398 if (--mii_cnt == 0) {
1399 mdiobus_unregister(fep->mii_bus);
1400 kfree(fep->mii_bus->irq);
1401 mdiobus_free(fep->mii_bus);
1405 static int fec_enet_get_settings(struct net_device *ndev,
1406 struct ethtool_cmd *cmd)
1408 struct fec_enet_private *fep = netdev_priv(ndev);
1409 struct phy_device *phydev = fep->phy_dev;
1414 return phy_ethtool_gset(phydev, cmd);
1417 static int fec_enet_set_settings(struct net_device *ndev,
1418 struct ethtool_cmd *cmd)
1420 struct fec_enet_private *fep = netdev_priv(ndev);
1421 struct phy_device *phydev = fep->phy_dev;
1426 return phy_ethtool_sset(phydev, cmd);
1429 static void fec_enet_get_drvinfo(struct net_device *ndev,
1430 struct ethtool_drvinfo *info)
1432 struct fec_enet_private *fep = netdev_priv(ndev);
1434 strlcpy(info->driver, fep->pdev->dev.driver->name,
1435 sizeof(info->driver));
1436 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1437 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1440 static int fec_enet_get_ts_info(struct net_device *ndev,
1441 struct ethtool_ts_info *info)
1443 struct fec_enet_private *fep = netdev_priv(ndev);
1445 if (fep->bufdesc_ex) {
1447 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1448 SOF_TIMESTAMPING_RX_SOFTWARE |
1449 SOF_TIMESTAMPING_SOFTWARE |
1450 SOF_TIMESTAMPING_TX_HARDWARE |
1451 SOF_TIMESTAMPING_RX_HARDWARE |
1452 SOF_TIMESTAMPING_RAW_HARDWARE;
1454 info->phc_index = ptp_clock_index(fep->ptp_clock);
1456 info->phc_index = -1;
1458 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1459 (1 << HWTSTAMP_TX_ON);
1461 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1462 (1 << HWTSTAMP_FILTER_ALL);
1465 return ethtool_op_get_ts_info(ndev, info);
1469 #if !defined(CONFIG_M5272)
1471 static void fec_enet_get_pauseparam(struct net_device *ndev,
1472 struct ethtool_pauseparam *pause)
1474 struct fec_enet_private *fep = netdev_priv(ndev);
1476 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1477 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1478 pause->rx_pause = pause->tx_pause;
1481 static int fec_enet_set_pauseparam(struct net_device *ndev,
1482 struct ethtool_pauseparam *pause)
1484 struct fec_enet_private *fep = netdev_priv(ndev);
1486 if (pause->tx_pause != pause->rx_pause) {
1488 "hardware only support enable/disable both tx and rx");
1492 fep->pause_flag = 0;
1494 /* tx pause must be same as rx pause */
1495 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1496 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1498 if (pause->rx_pause || pause->autoneg) {
1499 fep->phy_dev->supported |= ADVERTISED_Pause;
1500 fep->phy_dev->advertising |= ADVERTISED_Pause;
1502 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1503 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1506 if (pause->autoneg) {
1507 if (netif_running(ndev))
1509 phy_start_aneg(fep->phy_dev);
1511 if (netif_running(ndev))
1512 fec_restart(ndev, 0);
1517 static const struct fec_stat {
1518 char name[ETH_GSTRING_LEN];
1522 { "tx_dropped", RMON_T_DROP },
1523 { "tx_packets", RMON_T_PACKETS },
1524 { "tx_broadcast", RMON_T_BC_PKT },
1525 { "tx_multicast", RMON_T_MC_PKT },
1526 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1527 { "tx_undersize", RMON_T_UNDERSIZE },
1528 { "tx_oversize", RMON_T_OVERSIZE },
1529 { "tx_fragment", RMON_T_FRAG },
1530 { "tx_jabber", RMON_T_JAB },
1531 { "tx_collision", RMON_T_COL },
1532 { "tx_64byte", RMON_T_P64 },
1533 { "tx_65to127byte", RMON_T_P65TO127 },
1534 { "tx_128to255byte", RMON_T_P128TO255 },
1535 { "tx_256to511byte", RMON_T_P256TO511 },
1536 { "tx_512to1023byte", RMON_T_P512TO1023 },
1537 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1538 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1539 { "tx_octets", RMON_T_OCTETS },
1542 { "IEEE_tx_drop", IEEE_T_DROP },
1543 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1544 { "IEEE_tx_1col", IEEE_T_1COL },
1545 { "IEEE_tx_mcol", IEEE_T_MCOL },
1546 { "IEEE_tx_def", IEEE_T_DEF },
1547 { "IEEE_tx_lcol", IEEE_T_LCOL },
1548 { "IEEE_tx_excol", IEEE_T_EXCOL },
1549 { "IEEE_tx_macerr", IEEE_T_MACERR },
1550 { "IEEE_tx_cserr", IEEE_T_CSERR },
1551 { "IEEE_tx_sqe", IEEE_T_SQE },
1552 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1553 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1556 { "rx_packets", RMON_R_PACKETS },
1557 { "rx_broadcast", RMON_R_BC_PKT },
1558 { "rx_multicast", RMON_R_MC_PKT },
1559 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1560 { "rx_undersize", RMON_R_UNDERSIZE },
1561 { "rx_oversize", RMON_R_OVERSIZE },
1562 { "rx_fragment", RMON_R_FRAG },
1563 { "rx_jabber", RMON_R_JAB },
1564 { "rx_64byte", RMON_R_P64 },
1565 { "rx_65to127byte", RMON_R_P65TO127 },
1566 { "rx_128to255byte", RMON_R_P128TO255 },
1567 { "rx_256to511byte", RMON_R_P256TO511 },
1568 { "rx_512to1023byte", RMON_R_P512TO1023 },
1569 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1570 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1571 { "rx_octets", RMON_R_OCTETS },
1574 { "IEEE_rx_drop", IEEE_R_DROP },
1575 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1576 { "IEEE_rx_crc", IEEE_R_CRC },
1577 { "IEEE_rx_align", IEEE_R_ALIGN },
1578 { "IEEE_rx_macerr", IEEE_R_MACERR },
1579 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1580 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1583 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1584 struct ethtool_stats *stats, u64 *data)
1586 struct fec_enet_private *fep = netdev_priv(dev);
1589 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1590 data[i] = readl(fep->hwp + fec_stats[i].offset);
1593 static void fec_enet_get_strings(struct net_device *netdev,
1594 u32 stringset, u8 *data)
1597 switch (stringset) {
1599 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1600 memcpy(data + i * ETH_GSTRING_LEN,
1601 fec_stats[i].name, ETH_GSTRING_LEN);
1606 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1610 return ARRAY_SIZE(fec_stats);
1615 #endif /* !defined(CONFIG_M5272) */
1617 static int fec_enet_nway_reset(struct net_device *dev)
1619 struct fec_enet_private *fep = netdev_priv(dev);
1620 struct phy_device *phydev = fep->phy_dev;
1625 return genphy_restart_aneg(phydev);
1628 static const struct ethtool_ops fec_enet_ethtool_ops = {
1629 #if !defined(CONFIG_M5272)
1630 .get_pauseparam = fec_enet_get_pauseparam,
1631 .set_pauseparam = fec_enet_set_pauseparam,
1633 .get_settings = fec_enet_get_settings,
1634 .set_settings = fec_enet_set_settings,
1635 .get_drvinfo = fec_enet_get_drvinfo,
1636 .get_link = ethtool_op_get_link,
1637 .get_ts_info = fec_enet_get_ts_info,
1638 .nway_reset = fec_enet_nway_reset,
1639 #ifndef CONFIG_M5272
1640 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1641 .get_strings = fec_enet_get_strings,
1642 .get_sset_count = fec_enet_get_sset_count,
1646 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1648 struct fec_enet_private *fep = netdev_priv(ndev);
1649 struct phy_device *phydev = fep->phy_dev;
1651 if (!netif_running(ndev))
1657 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1658 return fec_ptp_ioctl(ndev, rq, cmd);
1660 return phy_mii_ioctl(phydev, rq, cmd);
1663 static void fec_enet_free_buffers(struct net_device *ndev)
1665 struct fec_enet_private *fep = netdev_priv(ndev);
1667 struct sk_buff *skb;
1668 struct bufdesc *bdp;
1670 bdp = fep->rx_bd_base;
1671 for (i = 0; i < RX_RING_SIZE; i++) {
1672 skb = fep->rx_skbuff[i];
1674 if (bdp->cbd_bufaddr)
1675 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1676 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1679 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1682 bdp = fep->tx_bd_base;
1683 for (i = 0; i < TX_RING_SIZE; i++)
1684 kfree(fep->tx_bounce[i]);
1687 static int fec_enet_alloc_buffers(struct net_device *ndev)
1689 struct fec_enet_private *fep = netdev_priv(ndev);
1691 struct sk_buff *skb;
1692 struct bufdesc *bdp;
1694 bdp = fep->rx_bd_base;
1695 for (i = 0; i < RX_RING_SIZE; i++) {
1696 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1698 fec_enet_free_buffers(ndev);
1701 fep->rx_skbuff[i] = skb;
1703 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1704 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1705 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1707 if (fep->bufdesc_ex) {
1708 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1709 ebdp->cbd_esc = BD_ENET_RX_INT;
1712 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1715 /* Set the last buffer to wrap. */
1716 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1717 bdp->cbd_sc |= BD_SC_WRAP;
1719 bdp = fep->tx_bd_base;
1720 for (i = 0; i < TX_RING_SIZE; i++) {
1721 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1724 bdp->cbd_bufaddr = 0;
1726 if (fep->bufdesc_ex) {
1727 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1728 ebdp->cbd_esc = BD_ENET_TX_INT;
1731 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1734 /* Set the last buffer to wrap. */
1735 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1736 bdp->cbd_sc |= BD_SC_WRAP;
1742 fec_enet_open(struct net_device *ndev)
1744 struct fec_enet_private *fep = netdev_priv(ndev);
1747 napi_enable(&fep->napi);
1749 /* I should reset the ring buffers here, but I don't yet know
1750 * a simple way to do that.
1753 ret = fec_enet_alloc_buffers(ndev);
1757 /* Probe and connect to PHY when open the interface */
1758 ret = fec_enet_mii_probe(ndev);
1760 fec_enet_free_buffers(ndev);
1763 phy_start(fep->phy_dev);
1764 netif_start_queue(ndev);
1770 fec_enet_close(struct net_device *ndev)
1772 struct fec_enet_private *fep = netdev_priv(ndev);
1774 /* Don't know what to do yet. */
1775 napi_disable(&fep->napi);
1777 netif_stop_queue(ndev);
1781 phy_stop(fep->phy_dev);
1782 phy_disconnect(fep->phy_dev);
1785 fec_enet_free_buffers(ndev);
1790 /* Set or clear the multicast filter for this adaptor.
1791 * Skeleton taken from sunlance driver.
1792 * The CPM Ethernet implementation allows Multicast as well as individual
1793 * MAC address filtering. Some of the drivers check to make sure it is
1794 * a group multicast address, and discard those that are not. I guess I
1795 * will do the same for now, but just remove the test if you want
1796 * individual filtering as well (do the upper net layers want or support
1797 * this kind of feature?).
1800 #define HASH_BITS 6 /* #bits in hash */
1801 #define CRC32_POLY 0xEDB88320
1803 static void set_multicast_list(struct net_device *ndev)
1805 struct fec_enet_private *fep = netdev_priv(ndev);
1806 struct netdev_hw_addr *ha;
1807 unsigned int i, bit, data, crc, tmp;
1810 if (ndev->flags & IFF_PROMISC) {
1811 tmp = readl(fep->hwp + FEC_R_CNTRL);
1813 writel(tmp, fep->hwp + FEC_R_CNTRL);
1817 tmp = readl(fep->hwp + FEC_R_CNTRL);
1819 writel(tmp, fep->hwp + FEC_R_CNTRL);
1821 if (ndev->flags & IFF_ALLMULTI) {
1822 /* Catch all multicast addresses, so set the
1825 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1826 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1831 /* Clear filter and add the addresses in hash register
1833 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1834 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1836 netdev_for_each_mc_addr(ha, ndev) {
1837 /* calculate crc32 value of mac address */
1840 for (i = 0; i < ndev->addr_len; i++) {
1842 for (bit = 0; bit < 8; bit++, data >>= 1) {
1844 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1848 /* only upper 6 bits (HASH_BITS) are used
1849 * which point to specific bit in he hash registers
1851 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1854 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1855 tmp |= 1 << (hash - 32);
1856 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1858 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1860 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1865 /* Set a MAC change in hardware. */
1867 fec_set_mac_address(struct net_device *ndev, void *p)
1869 struct fec_enet_private *fep = netdev_priv(ndev);
1870 struct sockaddr *addr = p;
1872 if (!is_valid_ether_addr(addr->sa_data))
1873 return -EADDRNOTAVAIL;
1875 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1877 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1878 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1879 fep->hwp + FEC_ADDR_LOW);
1880 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1881 fep->hwp + FEC_ADDR_HIGH);
1885 #ifdef CONFIG_NET_POLL_CONTROLLER
1887 * fec_poll_controller - FEC Poll controller function
1888 * @dev: The FEC network adapter
1890 * Polled functionality used by netconsole and others in non interrupt mode
1893 static void fec_poll_controller(struct net_device *dev)
1896 struct fec_enet_private *fep = netdev_priv(dev);
1898 for (i = 0; i < FEC_IRQ_NUM; i++) {
1899 if (fep->irq[i] > 0) {
1900 disable_irq(fep->irq[i]);
1901 fec_enet_interrupt(fep->irq[i], dev);
1902 enable_irq(fep->irq[i]);
1908 static int fec_set_features(struct net_device *netdev,
1909 netdev_features_t features)
1911 struct fec_enet_private *fep = netdev_priv(netdev);
1912 netdev_features_t changed = features ^ netdev->features;
1914 netdev->features = features;
1916 /* Receive checksum has been changed */
1917 if (changed & NETIF_F_RXCSUM) {
1918 if (features & NETIF_F_RXCSUM)
1919 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1921 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
1923 if (netif_running(netdev)) {
1925 fec_restart(netdev, fep->phy_dev->duplex);
1926 netif_wake_queue(netdev);
1928 fec_restart(netdev, fep->phy_dev->duplex);
1935 static const struct net_device_ops fec_netdev_ops = {
1936 .ndo_open = fec_enet_open,
1937 .ndo_stop = fec_enet_close,
1938 .ndo_start_xmit = fec_enet_start_xmit,
1939 .ndo_set_rx_mode = set_multicast_list,
1940 .ndo_change_mtu = eth_change_mtu,
1941 .ndo_validate_addr = eth_validate_addr,
1942 .ndo_tx_timeout = fec_timeout,
1943 .ndo_set_mac_address = fec_set_mac_address,
1944 .ndo_do_ioctl = fec_enet_ioctl,
1945 #ifdef CONFIG_NET_POLL_CONTROLLER
1946 .ndo_poll_controller = fec_poll_controller,
1948 .ndo_set_features = fec_set_features,
1952 * XXX: We need to clean up on failure exits here.
1955 static int fec_enet_init(struct net_device *ndev)
1957 struct fec_enet_private *fep = netdev_priv(ndev);
1958 const struct platform_device_id *id_entry =
1959 platform_get_device_id(fep->pdev);
1960 struct bufdesc *cbd_base;
1962 /* Allocate memory for buffer descriptors. */
1963 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1968 memset(cbd_base, 0, PAGE_SIZE);
1972 /* Get the Ethernet address */
1975 /* Set receive and transmit descriptor base. */
1976 fep->rx_bd_base = cbd_base;
1977 if (fep->bufdesc_ex)
1978 fep->tx_bd_base = (struct bufdesc *)
1979 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1981 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1983 /* The FEC Ethernet specific entries in the device structure */
1984 ndev->watchdog_timeo = TX_TIMEOUT;
1985 ndev->netdev_ops = &fec_netdev_ops;
1986 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1988 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1989 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1991 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
1992 /* enable hw VLAN support */
1993 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1994 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1997 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
1998 /* enable hw accelerator */
1999 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2001 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2003 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2006 fec_restart(ndev, 0);
2012 static void fec_reset_phy(struct platform_device *pdev)
2016 struct device_node *np = pdev->dev.of_node;
2021 of_property_read_u32(np, "phy-reset-duration", &msec);
2022 /* A sane reset duration should not be longer than 1s */
2026 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2027 if (!gpio_is_valid(phy_reset))
2030 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2031 GPIOF_OUT_INIT_LOW, "phy-reset");
2033 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2037 gpio_set_value(phy_reset, 1);
2039 #else /* CONFIG_OF */
2040 static void fec_reset_phy(struct platform_device *pdev)
2043 * In case of platform probe, the reset has been done
2047 #endif /* CONFIG_OF */
2050 fec_probe(struct platform_device *pdev)
2052 struct fec_enet_private *fep;
2053 struct fec_platform_data *pdata;
2054 struct net_device *ndev;
2055 int i, irq, ret = 0;
2057 const struct of_device_id *of_id;
2060 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2062 pdev->id_entry = of_id->data;
2064 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2068 /* Init network device */
2069 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2073 SET_NETDEV_DEV(ndev, &pdev->dev);
2075 /* setup board info structure */
2076 fep = netdev_priv(ndev);
2078 #if !defined(CONFIG_M5272)
2079 /* default enable pause frame auto negotiation */
2080 if (pdev->id_entry &&
2081 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2082 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2085 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2086 if (IS_ERR(fep->hwp)) {
2087 ret = PTR_ERR(fep->hwp);
2088 goto failed_ioremap;
2092 fep->dev_id = dev_id++;
2094 fep->bufdesc_ex = 0;
2096 platform_set_drvdata(pdev, ndev);
2098 ret = of_get_phy_mode(pdev->dev.of_node);
2100 pdata = pdev->dev.platform_data;
2102 fep->phy_interface = pdata->phy;
2104 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2106 fep->phy_interface = ret;
2109 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2110 if (IS_ERR(fep->clk_ipg)) {
2111 ret = PTR_ERR(fep->clk_ipg);
2115 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2116 if (IS_ERR(fep->clk_ahb)) {
2117 ret = PTR_ERR(fep->clk_ahb);
2121 /* enet_out is optional, depends on board */
2122 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2123 if (IS_ERR(fep->clk_enet_out))
2124 fep->clk_enet_out = NULL;
2126 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2128 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2129 if (IS_ERR(fep->clk_ptp)) {
2130 fep->clk_ptp = NULL;
2131 fep->bufdesc_ex = 0;
2134 clk_prepare_enable(fep->clk_ahb);
2135 clk_prepare_enable(fep->clk_ipg);
2136 clk_prepare_enable(fep->clk_enet_out);
2137 clk_prepare_enable(fep->clk_ptp);
2139 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2140 if (!IS_ERR(fep->reg_phy)) {
2141 ret = regulator_enable(fep->reg_phy);
2144 "Failed to enable phy regulator: %d\n", ret);
2145 goto failed_regulator;
2148 fep->reg_phy = NULL;
2151 fec_reset_phy(pdev);
2153 if (fep->bufdesc_ex)
2156 ret = fec_enet_init(ndev);
2160 for (i = 0; i < FEC_IRQ_NUM; i++) {
2161 irq = platform_get_irq(pdev, i);
2168 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
2171 irq = platform_get_irq(pdev, i);
2172 free_irq(irq, ndev);
2178 ret = fec_enet_mii_init(pdev);
2180 goto failed_mii_init;
2182 /* Carrier starts down, phylib will bring it up */
2183 netif_carrier_off(ndev);
2185 ret = register_netdev(ndev);
2187 goto failed_register;
2189 if (fep->bufdesc_ex && fep->ptp_clock)
2190 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2192 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2196 fec_enet_mii_remove(fep);
2199 for (i = 0; i < FEC_IRQ_NUM; i++) {
2200 irq = platform_get_irq(pdev, i);
2202 free_irq(irq, ndev);
2206 regulator_disable(fep->reg_phy);
2208 clk_disable_unprepare(fep->clk_ahb);
2209 clk_disable_unprepare(fep->clk_ipg);
2210 clk_disable_unprepare(fep->clk_enet_out);
2211 clk_disable_unprepare(fep->clk_ptp);
2220 fec_drv_remove(struct platform_device *pdev)
2222 struct net_device *ndev = platform_get_drvdata(pdev);
2223 struct fec_enet_private *fep = netdev_priv(ndev);
2226 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2227 unregister_netdev(ndev);
2228 fec_enet_mii_remove(fep);
2229 del_timer_sync(&fep->time_keep);
2230 for (i = 0; i < FEC_IRQ_NUM; i++) {
2231 int irq = platform_get_irq(pdev, i);
2233 free_irq(irq, ndev);
2236 regulator_disable(fep->reg_phy);
2237 clk_disable_unprepare(fep->clk_ptp);
2239 ptp_clock_unregister(fep->ptp_clock);
2240 clk_disable_unprepare(fep->clk_enet_out);
2241 clk_disable_unprepare(fep->clk_ahb);
2242 clk_disable_unprepare(fep->clk_ipg);
2248 #ifdef CONFIG_PM_SLEEP
2250 fec_suspend(struct device *dev)
2252 struct net_device *ndev = dev_get_drvdata(dev);
2253 struct fec_enet_private *fep = netdev_priv(ndev);
2255 if (netif_running(ndev)) {
2257 netif_device_detach(ndev);
2259 clk_disable_unprepare(fep->clk_enet_out);
2260 clk_disable_unprepare(fep->clk_ahb);
2261 clk_disable_unprepare(fep->clk_ipg);
2264 regulator_disable(fep->reg_phy);
2270 fec_resume(struct device *dev)
2272 struct net_device *ndev = dev_get_drvdata(dev);
2273 struct fec_enet_private *fep = netdev_priv(ndev);
2277 ret = regulator_enable(fep->reg_phy);
2282 clk_prepare_enable(fep->clk_enet_out);
2283 clk_prepare_enable(fep->clk_ahb);
2284 clk_prepare_enable(fep->clk_ipg);
2285 if (netif_running(ndev)) {
2286 fec_restart(ndev, fep->full_duplex);
2287 netif_device_attach(ndev);
2292 #endif /* CONFIG_PM_SLEEP */
2294 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2296 static struct platform_driver fec_driver = {
2298 .name = DRIVER_NAME,
2299 .owner = THIS_MODULE,
2301 .of_match_table = fec_dt_ids,
2303 .id_table = fec_devtype,
2305 .remove = fec_drv_remove,
2308 module_platform_driver(fec_driver);
2310 MODULE_ALIAS("platform:"DRIVER_NAME);
2311 MODULE_LICENSE("GPL");