Pileus Git - ~andy/linux/blob - drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
  56                            u8 subsystem)
  57 {
  58         int i;
  59         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  60         u32 cmd_privileges = adapter->cmd_privileges;
  61
  62         for (i = 0; i < num_entries; i++)
  63                 if (opcode == cmd_priv_map[i].opcode &&
  64                     subsystem == cmd_priv_map[i].subsystem)
  65                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  66                                 return false;
  67
  68         return true;
  69 }
  70
  71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  72 {
  73         return wrb->payload.embedded_payload;
  74 }
  75
  76 static void be_mcc_notify(struct be_adapter *adapter)
  77 {
  78         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  79         u32 val = 0;
  80
  81         if (be_error(adapter))
  82                 return;
  83
  84         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  85         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  86
  87         wmb();
  88         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  89 }
  90
  91 /* To check if valid bit is set, check the entire word as we don't know
  92  * the endianness of the data (old entry is host endian while a new entry is
  93  * little endian) */
  94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  95 {
  96         u32 flags;
  97
  98         if (compl->flags != 0) {
  99                 flags = le32_to_cpu(compl->flags);
 100                 if (flags & CQE_FLAGS_VALID_MASK) {
 101                         compl->flags = flags;
 102                         return true;
 103                 }
 104         }
 105         return false;
 106 }
 107
 108 /* Need to reset the entire word that houses the valid bit */
 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 110 {
 111         compl->flags = 0;
 112 }
 113
 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 115 {
 116         unsigned long addr;
 117
 118         addr = tag1;
 119         addr = ((addr << 16) << 16) | tag0;
 120         return (void *)addr;
 121 }
 122
 123 static int be_mcc_compl_process(struct be_adapter *adapter,
 124                                 struct be_mcc_compl *compl)
 125 {
 126         u16 compl_status, extd_status;
 127         struct be_cmd_resp_hdr *resp_hdr;
 128         u8 opcode = 0, subsystem = 0;
 129
 130         /* Just swap the status to host endian; mcc tag is opaquely copied
 131          * from mcc_wrb */
 132         be_dws_le_to_cpu(compl, 4);
 133
 134         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 135                                 CQE_STATUS_COMPL_MASK;
 136
 137         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 138
 139         if (resp_hdr) {
 140                 opcode = resp_hdr->opcode;
 141                 subsystem = resp_hdr->subsystem;
 142         }
 143
 144         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 145              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 146             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 147                 adapter->flash_status = compl_status;
 148                 complete(&adapter->flash_compl);
 149         }
 150
 151         if (compl_status == MCC_STATUS_SUCCESS) {
 152                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 153                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 154                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 155                         be_parse_stats(adapter);
 156                         adapter->stats_cmd_sent = false;
 157                 }
 158                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 159                     subsystem == CMD_SUBSYSTEM_COMMON) {
 160                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 161                                 (void *)resp_hdr;
 162                         adapter->drv_stats.be_on_die_temperature =
 163                                 resp->on_die_temperature;
 164                 }
 165         } else {
 166                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 167                         adapter->be_get_temp_freq = 0;
 168
 169                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 170                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 171                         goto done;
 172
 173                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 174                         dev_warn(&adapter->pdev->dev,
 175                                  "VF is not privileged to issue opcode %d-%d\n",
 176                                  opcode, subsystem);
 177                 } else {
 178                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 179                                         CQE_STATUS_EXTD_MASK;
 180                         dev_err(&adapter->pdev->dev,
 181                                 "opcode %d-%d failed:status %d-%d\n",
 182                                 opcode, subsystem, compl_status, extd_status);
 183                 }
 184         }
 185 done:
 186         return compl_status;
 187 }
 188
 189 /* Link state evt is a string of bytes; no need for endian swapping */
 190 static void be_async_link_state_process(struct be_adapter *adapter,
 191                 struct be_async_event_link_state *evt)
 192 {
 193         /* When link status changes, link speed must be re-queried from FW */
 194         adapter->phy.link_speed = -1;
 195
 196         /* Ignore physical link event */
 197         if (lancer_chip(adapter) &&
 198             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 199                 return;
 200
 201         /* For the initial link status do not rely on the ASYNC event as
 202          * it may not be received in some cases.
 203          */
 204         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 205                 be_link_status_update(adapter, evt->port_link_status);
 206 }
 207
 208 /* Grp5 CoS Priority evt */
 209 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 210                 struct be_async_event_grp5_cos_priority *evt)
 211 {
 212         if (evt->valid) {
 213                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 214                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 215                 adapter->recommended_prio =
 216                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 217         }
 218 }
 219
 220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 221 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 222                 struct be_async_event_grp5_qos_link_speed *evt)
 223 {
 224         if (adapter->phy.link_speed >= 0 &&
 225             evt->physical_port == adapter->port_num)
 226                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 227 }
 228
 229 /*Grp5 PVID evt*/
 230 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 231                 struct be_async_event_grp5_pvid_state *evt)
 232 {
 233         if (evt->enabled)
 234                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 235         else
 236                 adapter->pvid = 0;
 237 }
 238
 239 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 240                 u32 trailer, struct be_mcc_compl *evt)
 241 {
 242         u8 event_type = 0;
 243
 244         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 245                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 246
 247         switch (event_type) {
 248         case ASYNC_EVENT_COS_PRIORITY:
 249                 be_async_grp5_cos_priority_process(adapter,
 250                 (struct be_async_event_grp5_cos_priority *)evt);
 251         break;
 252         case ASYNC_EVENT_QOS_SPEED:
 253                 be_async_grp5_qos_speed_process(adapter,
 254                 (struct be_async_event_grp5_qos_link_speed *)evt);
 255         break;
 256         case ASYNC_EVENT_PVID_STATE:
 257                 be_async_grp5_pvid_state_process(adapter,
 258                 (struct be_async_event_grp5_pvid_state *)evt);
 259         break;
 260         default:
 261                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 262                 break;
 263         }
 264 }
 265
 266 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 267                 u32 trailer, struct be_mcc_compl *cmp)
 268 {
 269         u8 event_type = 0;
 270         struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
 271
 272         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 273                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 274
 275         switch (event_type) {
 276         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 277                 if (evt->valid)
 278                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 279                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 280         break;
 281         default:
 282                 dev_warn(&adapter->pdev->dev, "Unknown debug event\n");
 283         break;
 284         }
 285 }
 286
 287 static inline bool is_link_state_evt(u32 trailer)
 288 {
 289         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 290                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 291                                 ASYNC_EVENT_CODE_LINK_STATE;
 292 }
 293
 294 static inline bool is_grp5_evt(u32 trailer)
 295 {
 296         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 297                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 298                                 ASYNC_EVENT_CODE_GRP_5);
 299 }
 300
 301 static inline bool is_dbg_evt(u32 trailer)
 302 {
 303         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 304                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 305                                 ASYNC_EVENT_CODE_QNQ);
 306 }
 307
 308 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 309 {
 310         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 311         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 312
 313         if (be_mcc_compl_is_new(compl)) {
 314                 queue_tail_inc(mcc_cq);
 315                 return compl;
 316         }
 317         return NULL;
 318 }
 319
 320 void be_async_mcc_enable(struct be_adapter *adapter)
 321 {
 322         spin_lock_bh(&adapter->mcc_cq_lock);
 323
 324         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 325         adapter->mcc_obj.rearm_cq = true;
 326
 327         spin_unlock_bh(&adapter->mcc_cq_lock);
 328 }
 329
 330 void be_async_mcc_disable(struct be_adapter *adapter)
 331 {
 332         spin_lock_bh(&adapter->mcc_cq_lock);
 333
 334         adapter->mcc_obj.rearm_cq = false;
 335         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 336
 337         spin_unlock_bh(&adapter->mcc_cq_lock);
 338 }
 339
 340 int be_process_mcc(struct be_adapter *adapter)
 341 {
 342         struct be_mcc_compl *compl;
 343         int num = 0, status = 0;
 344         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 345
 346         spin_lock(&adapter->mcc_cq_lock);
 347         while ((compl = be_mcc_compl_get(adapter))) {
 348                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 349                         /* Interpret flags as an async trailer */
 350                         if (is_link_state_evt(compl->flags))
 351                                 be_async_link_state_process(adapter,
 352                                 (struct be_async_event_link_state *) compl);
 353                         else if (is_grp5_evt(compl->flags))
 354                                 be_async_grp5_evt_process(adapter,
 355                                 compl->flags, compl);
 356                         else if (is_dbg_evt(compl->flags))
 357                                 be_async_dbg_evt_process(adapter,
 358                                 compl->flags, compl);
 359                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 360                                 status = be_mcc_compl_process(adapter, compl);
 361                                 atomic_dec(&mcc_obj->q.used);
 362                 }
 363                 be_mcc_compl_use(compl);
 364                 num++;
 365         }
 366
 367         if (num)
 368                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 369
 370         spin_unlock(&adapter->mcc_cq_lock);
 371         return status;
 372 }
 373
 374 /* Wait till no more pending mcc requests are present */
 375 static int be_mcc_wait_compl(struct be_adapter *adapter)
 376 {
 377 #define mcc_timeout             120000 /* 12s timeout */
 378         int i, status = 0;
 379         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 380
 381         for (i = 0; i < mcc_timeout; i++) {
 382                 if (be_error(adapter))
 383                         return -EIO;
 384
 385                 local_bh_disable();
 386                 status = be_process_mcc(adapter);
 387                 local_bh_enable();
 388
 389                 if (atomic_read(&mcc_obj->q.used) == 0)
 390                         break;
 391                 udelay(100);
 392         }
 393         if (i == mcc_timeout) {
 394                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 395                 adapter->fw_timeout = true;
 396                 return -EIO;
 397         }
 398         return status;
 399 }
 400
 401 /* Notify MCC requests and wait for completion */
 402 static int be_mcc_notify_wait(struct be_adapter *adapter)
 403 {
 404         int status;
 405         struct be_mcc_wrb *wrb;
 406         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 407         u16 index = mcc_obj->q.head;
 408         struct be_cmd_resp_hdr *resp;
 409
 410         index_dec(&index, mcc_obj->q.len);
 411         wrb = queue_index_node(&mcc_obj->q, index);
 412
 413         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 414
 415         be_mcc_notify(adapter);
 416
 417         status = be_mcc_wait_compl(adapter);
 418         if (status == -EIO)
 419                 goto out;
 420
 421         status = resp->status;
 422 out:
 423         return status;
 424 }
 425
 426 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 427 {
 428         int msecs = 0;
 429         u32 ready;
 430
 431         do {
 432                 if (be_error(adapter))
 433                         return -EIO;
 434
 435                 ready = ioread32(db);
 436                 if (ready == 0xffffffff)
 437                         return -1;
 438
 439                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 440                 if (ready)
 441                         break;
 442
 443                 if (msecs > 4000) {
 444                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 445                         adapter->fw_timeout = true;
 446                         be_detect_error(adapter);
 447                         return -1;
 448                 }
 449
 450                 msleep(1);
 451                 msecs++;
 452         } while (true);
 453
 454         return 0;
 455 }
 456
 457 /*
 458  * Insert the mailbox address into the doorbell in two steps
 459  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 460  */
 461 static int be_mbox_notify_wait(struct be_adapter *adapter)
 462 {
 463         int status;
 464         u32 val = 0;
 465         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 466         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 467         struct be_mcc_mailbox *mbox = mbox_mem->va;
 468         struct be_mcc_compl *compl = &mbox->compl;
 469
 470         /* wait for ready to be set */
 471         status = be_mbox_db_ready_wait(adapter, db);
 472         if (status != 0)
 473                 return status;
 474
 475         val |= MPU_MAILBOX_DB_HI_MASK;
 476         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 477         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 478         iowrite32(val, db);
 479
 480         /* wait for ready to be set */
 481         status = be_mbox_db_ready_wait(adapter, db);
 482         if (status != 0)
 483                 return status;
 484
 485         val = 0;
 486         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 487         val |= (u32)(mbox_mem->dma >> 4) << 2;
 488         iowrite32(val, db);
 489
 490         status = be_mbox_db_ready_wait(adapter, db);
 491         if (status != 0)
 492                 return status;
 493
 494         /* A cq entry has been made now */
 495         if (be_mcc_compl_is_new(compl)) {
 496                 status = be_mcc_compl_process(adapter, &mbox->compl);
 497                 be_mcc_compl_use(compl);
 498                 if (status)
 499                         return status;
 500         } else {
 501                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 502                 return -1;
 503         }
 504         return 0;
 505 }
 506
 507 static u16 be_POST_stage_get(struct be_adapter *adapter)
 508 {
 509         u32 sem;
 510
 511         if (BEx_chip(adapter))
 512                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 513         else
 514                 pci_read_config_dword(adapter->pdev,
 515                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 516
 517         return sem & POST_STAGE_MASK;
 518 }
 519
 520 int lancer_wait_ready(struct be_adapter *adapter)
 521 {
 522 #define SLIPORT_READY_TIMEOUT 30
 523         u32 sliport_status;
 524         int status = 0, i;
 525
 526         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 527                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 528                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 529                         break;
 530
 531                 msleep(1000);
 532         }
 533
 534         if (i == SLIPORT_READY_TIMEOUT)
 535                 status = -1;
 536
 537         return status;
 538 }
 539
 540 static bool lancer_provisioning_error(struct be_adapter *adapter)
 541 {
 542         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 543         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 544         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 545                 sliport_err1 = ioread32(adapter->db +
 546                                         SLIPORT_ERROR1_OFFSET);
 547                 sliport_err2 = ioread32(adapter->db +
 548                                         SLIPORT_ERROR2_OFFSET);
 549
 550                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 551                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 552                         return true;
 553         }
 554         return false;
 555 }
 556
 557 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 558 {
 559         int status;
 560         u32 sliport_status, err, reset_needed;
 561         bool resource_error;
 562
 563         resource_error = lancer_provisioning_error(adapter);
 564         if (resource_error)
 565                 return -EAGAIN;
 566
 567         status = lancer_wait_ready(adapter);
 568         if (!status) {
 569                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 570                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 571                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 572                 if (err && reset_needed) {
 573                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 574                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 575
 576                         /* check adapter has corrected the error */
 577                         status = lancer_wait_ready(adapter);
 578                         sliport_status = ioread32(adapter->db +
 579                                                   SLIPORT_STATUS_OFFSET);
 580                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 581                                                 SLIPORT_STATUS_RN_MASK);
 582                         if (status || sliport_status)
 583                                 status = -1;
 584                 } else if (err || reset_needed) {
 585                         status = -1;
 586                 }
 587         }
 588         /* Stop error recovery if error is not recoverable.
 589          * No resource error is temporary errors and will go away
 590          * when PF provisions resources.
 591          */
 592         resource_error = lancer_provisioning_error(adapter);
 593         if (resource_error)
 594                 status = -EAGAIN;
 595
 596         return status;
 597 }
 598
 599 int be_fw_wait_ready(struct be_adapter *adapter)
 600 {
 601         u16 stage;
 602         int status, timeout = 0;
 603         struct device *dev = &adapter->pdev->dev;
 604
 605         if (lancer_chip(adapter)) {
 606                 status = lancer_wait_ready(adapter);
 607                 return status;
 608         }
 609
 610         do {
 611                 stage = be_POST_stage_get(adapter);
 612                 if (stage == POST_STAGE_ARMFW_RDY)
 613                         return 0;
 614
 615                 dev_info(dev, "Waiting for POST, %ds elapsed\n",
 616                          timeout);
 617                 if (msleep_interruptible(2000)) {
 618                         dev_err(dev, "Waiting for POST aborted\n");
 619                         return -EINTR;
 620                 }
 621                 timeout += 2;
 622         } while (timeout < 60);
 623
 624         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 625         return -1;
 626 }
 627
 628
 629 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 630 {
 631         return &wrb->payload.sgl[0];
 632 }
 633
 634
 635 /* Don't touch the hdr after it's prepared */
 636 /* mem will be NULL for embedded commands */
 637 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 638                                 u8 subsystem, u8 opcode, int cmd_len,
 639                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 640 {
 641         struct be_sge *sge;
 642         unsigned long addr = (unsigned long)req_hdr;
 643         u64 req_addr = addr;
 644
 645         req_hdr->opcode = opcode;
 646         req_hdr->subsystem = subsystem;
 647         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 648         req_hdr->version = 0;
 649
 650         wrb->tag0 = req_addr & 0xFFFFFFFF;
 651         wrb->tag1 = upper_32_bits(req_addr);
 652
 653         wrb->payload_length = cmd_len;
 654         if (mem) {
 655                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 656                         MCC_WRB_SGE_CNT_SHIFT;
 657                 sge = nonembedded_sgl(wrb);
 658                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 659                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 660                 sge->len = cpu_to_le32(mem->size);
 661         } else
 662                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 663         be_dws_cpu_to_le(wrb, 8);
 664 }
 665
 666 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 667                         struct be_dma_mem *mem)
 668 {
 669         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 670         u64 dma = (u64)mem->dma;
 671
 672         for (i = 0; i < buf_pages; i++) {
 673                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 674                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 675                 dma += PAGE_SIZE_4K;
 676         }
 677 }
 678
 679 /* Converts interrupt delay in microseconds to multiplier value */
 680 static u32 eq_delay_to_mult(u32 usec_delay)
 681 {
 682 #define MAX_INTR_RATE                   651042
 683         const u32 round = 10;
 684         u32 multiplier;
 685
 686         if (usec_delay == 0)
 687                 multiplier = 0;
 688         else {
 689                 u32 interrupt_rate = 1000000 / usec_delay;
 690                 /* Max delay, corresponding to the lowest interrupt rate */
 691                 if (interrupt_rate == 0)
 692                         multiplier = 1023;
 693                 else {
 694                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 695                         multiplier /= interrupt_rate;
 696                         /* Round the multiplier to the closest value.*/
 697                         multiplier = (multiplier + round/2) / round;
 698                         multiplier = min(multiplier, (u32)1023);
 699                 }
 700         }
 701         return multiplier;
 702 }
 703
 704 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 705 {
 706         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 707         struct be_mcc_wrb *wrb
 708                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 709         memset(wrb, 0, sizeof(*wrb));
 710         return wrb;
 711 }
 712
 713 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 714 {
 715         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 716         struct be_mcc_wrb *wrb;
 717
 718         if (!mccq->created)
 719                 return NULL;
 720
 721         if (atomic_read(&mccq->used) >= mccq->len)
 722                 return NULL;
 723
 724         wrb = queue_head_node(mccq);
 725         queue_head_inc(mccq);
 726         atomic_inc(&mccq->used);
 727         memset(wrb, 0, sizeof(*wrb));
 728         return wrb;
 729 }
 730
 731 /* Tell fw we're about to start firing cmds by writing a
 732  * special pattern across the wrb hdr; uses mbox
 733  */
 734 int be_cmd_fw_init(struct be_adapter *adapter)
 735 {
 736         u8 *wrb;
 737         int status;
 738
 739         if (lancer_chip(adapter))
 740                 return 0;
 741
 742         if (mutex_lock_interruptible(&adapter->mbox_lock))
 743                 return -1;
 744
 745         wrb = (u8 *)wrb_from_mbox(adapter);
 746         *wrb++ = 0xFF;
 747         *wrb++ = 0x12;
 748         *wrb++ = 0x34;
 749         *wrb++ = 0xFF;
 750         *wrb++ = 0xFF;
 751         *wrb++ = 0x56;
 752         *wrb++ = 0x78;
 753         *wrb = 0xFF;
 754
 755         status = be_mbox_notify_wait(adapter);
 756
 757         mutex_unlock(&adapter->mbox_lock);
 758         return status;
 759 }
 760
 761 /* Tell fw we're done with firing cmds by writing a
 762  * special pattern across the wrb hdr; uses mbox
 763  */
 764 int be_cmd_fw_clean(struct be_adapter *adapter)
 765 {
 766         u8 *wrb;
 767         int status;
 768
 769         if (lancer_chip(adapter))
 770                 return 0;
 771
 772         if (mutex_lock_interruptible(&adapter->mbox_lock))
 773                 return -1;
 774
 775         wrb = (u8 *)wrb_from_mbox(adapter);
 776         *wrb++ = 0xFF;
 777         *wrb++ = 0xAA;
 778         *wrb++ = 0xBB;
 779         *wrb++ = 0xFF;
 780         *wrb++ = 0xFF;
 781         *wrb++ = 0xCC;
 782         *wrb++ = 0xDD;
 783         *wrb = 0xFF;
 784
 785         status = be_mbox_notify_wait(adapter);
 786
 787         mutex_unlock(&adapter->mbox_lock);
 788         return status;
 789 }
 790
 791 int be_cmd_eq_create(struct be_adapter *adapter,
 792                 struct be_queue_info *eq, int eq_delay)
 793 {
 794         struct be_mcc_wrb *wrb;
 795         struct be_cmd_req_eq_create *req;
 796         struct be_dma_mem *q_mem = &eq->dma_mem;
 797         int status;
 798
 799         if (mutex_lock_interruptible(&adapter->mbox_lock))
 800                 return -1;
 801
 802         wrb = wrb_from_mbox(adapter);
 803         req = embedded_payload(wrb);
 804
 805         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 806                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 807
 808         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 809
 810         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 811         /* 4byte eqe*/
 812         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 813         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 814                         __ilog2_u32(eq->len/256));
 815         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 816                         eq_delay_to_mult(eq_delay));
 817         be_dws_cpu_to_le(req->context, sizeof(req->context));
 818
 819         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 820
 821         status = be_mbox_notify_wait(adapter);
 822         if (!status) {
 823                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 824                 eq->id = le16_to_cpu(resp->eq_id);
 825                 eq->created = true;
 826         }
 827
 828         mutex_unlock(&adapter->mbox_lock);
 829         return status;
 830 }
 831
 832 /* Use MCC */
 833 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 834                           bool permanent, u32 if_handle, u32 pmac_id)
 835 {
 836         struct be_mcc_wrb *wrb;
 837         struct be_cmd_req_mac_query *req;
 838         int status;
 839
 840         spin_lock_bh(&adapter->mcc_lock);
 841
 842         wrb = wrb_from_mccq(adapter);
 843         if (!wrb) {
 844                 status = -EBUSY;
 845                 goto err;
 846         }
 847         req = embedded_payload(wrb);
 848
 849         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 850                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 851         req->type = MAC_ADDRESS_TYPE_NETWORK;
 852         if (permanent) {
 853                 req->permanent = 1;
 854         } else {
 855                 req->if_id = cpu_to_le16((u16) if_handle);
 856                 req->pmac_id = cpu_to_le32(pmac_id);
 857                 req->permanent = 0;
 858         }
 859
 860         status = be_mcc_notify_wait(adapter);
 861         if (!status) {
 862                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 863                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 864         }
 865
 866 err:
 867         spin_unlock_bh(&adapter->mcc_lock);
 868         return status;
 869 }
 870
 871 /* Uses synchronous MCCQ */
 872 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 873                 u32 if_id, u32 *pmac_id, u32 domain)
 874 {
 875         struct be_mcc_wrb *wrb;
 876         struct be_cmd_req_pmac_add *req;
 877         int status;
 878
 879         spin_lock_bh(&adapter->mcc_lock);
 880
 881         wrb = wrb_from_mccq(adapter);
 882         if (!wrb) {
 883                 status = -EBUSY;
 884                 goto err;
 885         }
 886         req = embedded_payload(wrb);
 887
 888         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 889                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 890
 891         req->hdr.domain = domain;
 892         req->if_id = cpu_to_le32(if_id);
 893         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 894
 895         status = be_mcc_notify_wait(adapter);
 896         if (!status) {
 897                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 898                 *pmac_id = le32_to_cpu(resp->pmac_id);
 899         }
 900
 901 err:
 902         spin_unlock_bh(&adapter->mcc_lock);
 903
 904          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 905                 status = -EPERM;
 906
 907         return status;
 908 }
 909
 910 /* Uses synchronous MCCQ */
 911 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 912 {
 913         struct be_mcc_wrb *wrb;
 914         struct be_cmd_req_pmac_del *req;
 915         int status;
 916
 917         if (pmac_id == -1)
 918                 return 0;
 919
 920         spin_lock_bh(&adapter->mcc_lock);
 921
 922         wrb = wrb_from_mccq(adapter);
 923         if (!wrb) {
 924                 status = -EBUSY;
 925                 goto err;
 926         }
 927         req = embedded_payload(wrb);
 928
 929         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 930                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 931
 932         req->hdr.domain = dom;
 933         req->if_id = cpu_to_le32(if_id);
 934         req->pmac_id = cpu_to_le32(pmac_id);
 935
 936         status = be_mcc_notify_wait(adapter);
 937
 938 err:
 939         spin_unlock_bh(&adapter->mcc_lock);
 940         return status;
 941 }
 942
 943 /* Uses Mbox */
 944 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
 945                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
 946 {
 947         struct be_mcc_wrb *wrb;
 948         struct be_cmd_req_cq_create *req;
 949         struct be_dma_mem *q_mem = &cq->dma_mem;
 950         void *ctxt;
 951         int status;
 952
 953         if (mutex_lock_interruptible(&adapter->mbox_lock))
 954                 return -1;
 955
 956         wrb = wrb_from_mbox(adapter);
 957         req = embedded_payload(wrb);
 958         ctxt = &req->context;
 959
 960         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 961                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 962
 963         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 964
 965         if (BEx_chip(adapter)) {
 966                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 967                                                                 coalesce_wm);
 968                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 969                                                                 ctxt, no_delay);
 970                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 971                                                 __ilog2_u32(cq->len/256));
 972                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 973                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 974                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 975         } else {
 976                 req->hdr.version = 2;
 977                 req->page_size = 1; /* 1 for 4K */
 978                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
 979                                                                 no_delay);
 980                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
 981                                                 __ilog2_u32(cq->len/256));
 982                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
 983                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable,
 984                                                                 ctxt, 1);
 985                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid,
 986                                                                 ctxt, eq->id);
 987         }
 988
 989         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 990
 991         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 992
 993         status = be_mbox_notify_wait(adapter);
 994         if (!status) {
 995                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 996                 cq->id = le16_to_cpu(resp->cq_id);
 997                 cq->created = true;
 998         }
 999
1000         mutex_unlock(&adapter->mbox_lock);
1001
1002         return status;
1003 }
1004
1005 static u32 be_encoded_q_len(int q_len)
1006 {
1007         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1008         if (len_encoded == 16)
1009                 len_encoded = 0;
1010         return len_encoded;
1011 }
1012
1013 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1014                                 struct be_queue_info *mccq,
1015                                 struct be_queue_info *cq)
1016 {
1017         struct be_mcc_wrb *wrb;
1018         struct be_cmd_req_mcc_ext_create *req;
1019         struct be_dma_mem *q_mem = &mccq->dma_mem;
1020         void *ctxt;
1021         int status;
1022
1023         if (mutex_lock_interruptible(&adapter->mbox_lock))
1024                 return -1;
1025
1026         wrb = wrb_from_mbox(adapter);
1027         req = embedded_payload(wrb);
1028         ctxt = &req->context;
1029
1030         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1031                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1032
1033         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1034         if (lancer_chip(adapter)) {
1035                 req->hdr.version = 1;
1036                 req->cq_id = cpu_to_le16(cq->id);
1037
1038                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1039                                                 be_encoded_q_len(mccq->len));
1040                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1041                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1042                                                                 ctxt, cq->id);
1043                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1044                                                                  ctxt, 1);
1045
1046         } else {
1047                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1048                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1049                                                 be_encoded_q_len(mccq->len));
1050                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1051         }
1052
1053         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1054         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1055         req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1056         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1057
1058         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1059
1060         status = be_mbox_notify_wait(adapter);
1061         if (!status) {
1062                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1063                 mccq->id = le16_to_cpu(resp->id);
1064                 mccq->created = true;
1065         }
1066         mutex_unlock(&adapter->mbox_lock);
1067
1068         return status;
1069 }
1070
1071 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1072                                 struct be_queue_info *mccq,
1073                                 struct be_queue_info *cq)
1074 {
1075         struct be_mcc_wrb *wrb;
1076         struct be_cmd_req_mcc_create *req;
1077         struct be_dma_mem *q_mem = &mccq->dma_mem;
1078         void *ctxt;
1079         int status;
1080
1081         if (mutex_lock_interruptible(&adapter->mbox_lock))
1082                 return -1;
1083
1084         wrb = wrb_from_mbox(adapter);
1085         req = embedded_payload(wrb);
1086         ctxt = &req->context;
1087
1088         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1089                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1090
1091         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1092
1093         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1094         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1095                         be_encoded_q_len(mccq->len));
1096         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1097
1098         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1099
1100         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1101
1102         status = be_mbox_notify_wait(adapter);
1103         if (!status) {
1104                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1105                 mccq->id = le16_to_cpu(resp->id);
1106                 mccq->created = true;
1107         }
1108
1109         mutex_unlock(&adapter->mbox_lock);
1110         return status;
1111 }
1112
1113 int be_cmd_mccq_create(struct be_adapter *adapter,
1114                         struct be_queue_info *mccq,
1115                         struct be_queue_info *cq)
1116 {
1117         int status;
1118
1119         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1120         if (status && !lancer_chip(adapter)) {
1121                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1122                         "or newer to avoid conflicting priorities between NIC "
1123                         "and FCoE traffic");
1124                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1125         }
1126         return status;
1127 }
1128
1129 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1130 {
1131         struct be_mcc_wrb *wrb;
1132         struct be_cmd_req_eth_tx_create *req;
1133         struct be_queue_info *txq = &txo->q;
1134         struct be_queue_info *cq = &txo->cq;
1135         struct be_dma_mem *q_mem = &txq->dma_mem;
1136         int status, ver = 0;
1137
1138         spin_lock_bh(&adapter->mcc_lock);
1139
1140         wrb = wrb_from_mccq(adapter);
1141         if (!wrb) {
1142                 status = -EBUSY;
1143                 goto err;
1144         }
1145
1146         req = embedded_payload(wrb);
1147
1148         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1149                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1150
1151         if (lancer_chip(adapter)) {
1152                 req->hdr.version = 1;
1153                 req->if_id = cpu_to_le16(adapter->if_handle);
1154         } else if (BEx_chip(adapter)) {
1155                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1156                         req->hdr.version = 2;
1157         } else { /* For SH */
1158                 req->hdr.version = 2;
1159         }
1160
1161         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1162         req->ulp_num = BE_ULP1_NUM;
1163         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1164         req->cq_id = cpu_to_le16(cq->id);
1165         req->queue_size = be_encoded_q_len(txq->len);
1166         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1167
1168         ver = req->hdr.version;
1169
1170         status = be_mcc_notify_wait(adapter);
1171         if (!status) {
1172                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1173                 txq->id = le16_to_cpu(resp->cid);
1174                 if (ver == 2)
1175                         txo->db_offset = le32_to_cpu(resp->db_offset);
1176                 else
1177                         txo->db_offset = DB_TXULP1_OFFSET;
1178                 txq->created = true;
1179         }
1180
1181 err:
1182         spin_unlock_bh(&adapter->mcc_lock);
1183
1184         return status;
1185 }
1186
1187 /* Uses MCC */
1188 int be_cmd_rxq_create(struct be_adapter *adapter,
1189                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1190                 u32 if_id, u32 rss, u8 *rss_id)
1191 {
1192         struct be_mcc_wrb *wrb;
1193         struct be_cmd_req_eth_rx_create *req;
1194         struct be_dma_mem *q_mem = &rxq->dma_mem;
1195         int status;
1196
1197         spin_lock_bh(&adapter->mcc_lock);
1198
1199         wrb = wrb_from_mccq(adapter);
1200         if (!wrb) {
1201                 status = -EBUSY;
1202                 goto err;
1203         }
1204         req = embedded_payload(wrb);
1205
1206         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1207                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1208
1209         req->cq_id = cpu_to_le16(cq_id);
1210         req->frag_size = fls(frag_size) - 1;
1211         req->num_pages = 2;
1212         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1213         req->interface_id = cpu_to_le32(if_id);
1214         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1215         req->rss_queue = cpu_to_le32(rss);
1216
1217         status = be_mcc_notify_wait(adapter);
1218         if (!status) {
1219                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1220                 rxq->id = le16_to_cpu(resp->id);
1221                 rxq->created = true;
1222                 *rss_id = resp->rss_id;
1223         }
1224
1225 err:
1226         spin_unlock_bh(&adapter->mcc_lock);
1227         return status;
1228 }
1229
1230 /* Generic destroyer function for all types of queues
1231  * Uses Mbox
1232  */
1233 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1234                 int queue_type)
1235 {
1236         struct be_mcc_wrb *wrb;
1237         struct be_cmd_req_q_destroy *req;
1238         u8 subsys = 0, opcode = 0;
1239         int status;
1240
1241         if (mutex_lock_interruptible(&adapter->mbox_lock))
1242                 return -1;
1243
1244         wrb = wrb_from_mbox(adapter);
1245         req = embedded_payload(wrb);
1246
1247         switch (queue_type) {
1248         case QTYPE_EQ:
1249                 subsys = CMD_SUBSYSTEM_COMMON;
1250                 opcode = OPCODE_COMMON_EQ_DESTROY;
1251                 break;
1252         case QTYPE_CQ:
1253                 subsys = CMD_SUBSYSTEM_COMMON;
1254                 opcode = OPCODE_COMMON_CQ_DESTROY;
1255                 break;
1256         case QTYPE_TXQ:
1257                 subsys = CMD_SUBSYSTEM_ETH;
1258                 opcode = OPCODE_ETH_TX_DESTROY;
1259                 break;
1260         case QTYPE_RXQ:
1261                 subsys = CMD_SUBSYSTEM_ETH;
1262                 opcode = OPCODE_ETH_RX_DESTROY;
1263                 break;
1264         case QTYPE_MCCQ:
1265                 subsys = CMD_SUBSYSTEM_COMMON;
1266                 opcode = OPCODE_COMMON_MCC_DESTROY;
1267                 break;
1268         default:
1269                 BUG();
1270         }
1271
1272         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1273                                 NULL);
1274         req->id = cpu_to_le16(q->id);
1275
1276         status = be_mbox_notify_wait(adapter);
1277         q->created = false;
1278
1279         mutex_unlock(&adapter->mbox_lock);
1280         return status;
1281 }
1282
1283 /* Uses MCC */
1284 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1285 {
1286         struct be_mcc_wrb *wrb;
1287         struct be_cmd_req_q_destroy *req;
1288         int status;
1289
1290         spin_lock_bh(&adapter->mcc_lock);
1291
1292         wrb = wrb_from_mccq(adapter);
1293         if (!wrb) {
1294                 status = -EBUSY;
1295                 goto err;
1296         }
1297         req = embedded_payload(wrb);
1298
1299         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1300                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1301         req->id = cpu_to_le16(q->id);
1302
1303         status = be_mcc_notify_wait(adapter);
1304         q->created = false;
1305
1306 err:
1307         spin_unlock_bh(&adapter->mcc_lock);
1308         return status;
1309 }
1310
1311 /* Create an rx filtering policy configuration on an i/f
1312  * Uses MCCQ
1313  */
1314 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1315                      u32 *if_handle, u32 domain)
1316 {
1317         struct be_mcc_wrb *wrb;
1318         struct be_cmd_req_if_create *req;
1319         int status;
1320
1321         spin_lock_bh(&adapter->mcc_lock);
1322
1323         wrb = wrb_from_mccq(adapter);
1324         if (!wrb) {
1325                 status = -EBUSY;
1326                 goto err;
1327         }
1328         req = embedded_payload(wrb);
1329
1330         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1331                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1332         req->hdr.domain = domain;
1333         req->capability_flags = cpu_to_le32(cap_flags);
1334         req->enable_flags = cpu_to_le32(en_flags);
1335
1336         req->pmac_invalid = true;
1337
1338         status = be_mcc_notify_wait(adapter);
1339         if (!status) {
1340                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1341                 *if_handle = le32_to_cpu(resp->interface_id);
1342
1343                 /* Hack to retrieve VF's pmac-id on BE3 */
1344                 if (BE3_chip(adapter) && !be_physfn(adapter))
1345                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1346         }
1347
1348 err:
1349         spin_unlock_bh(&adapter->mcc_lock);
1350         return status;
1351 }
1352
1353 /* Uses MCCQ */
1354 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1355 {
1356         struct be_mcc_wrb *wrb;
1357         struct be_cmd_req_if_destroy *req;
1358         int status;
1359
1360         if (interface_id == -1)
1361                 return 0;
1362
1363         spin_lock_bh(&adapter->mcc_lock);
1364
1365         wrb = wrb_from_mccq(adapter);
1366         if (!wrb) {
1367                 status = -EBUSY;
1368                 goto err;
1369         }
1370         req = embedded_payload(wrb);
1371
1372         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1373                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1374         req->hdr.domain = domain;
1375         req->interface_id = cpu_to_le32(interface_id);
1376
1377         status = be_mcc_notify_wait(adapter);
1378 err:
1379         spin_unlock_bh(&adapter->mcc_lock);
1380         return status;
1381 }
1382
1383 /* Get stats is a non embedded command: the request is not embedded inside
1384  * WRB but is a separate dma memory block
1385  * Uses asynchronous MCC
1386  */
1387 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1388 {
1389         struct be_mcc_wrb *wrb;
1390         struct be_cmd_req_hdr *hdr;
1391         int status = 0;
1392
1393         spin_lock_bh(&adapter->mcc_lock);
1394
1395         wrb = wrb_from_mccq(adapter);
1396         if (!wrb) {
1397                 status = -EBUSY;
1398                 goto err;
1399         }
1400         hdr = nonemb_cmd->va;
1401
1402         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1403                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1404
1405         /* version 1 of the cmd is not supported only by BE2 */
1406         if (!BE2_chip(adapter))
1407                 hdr->version = 1;
1408
1409         be_mcc_notify(adapter);
1410         adapter->stats_cmd_sent = true;
1411
1412 err:
1413         spin_unlock_bh(&adapter->mcc_lock);
1414         return status;
1415 }
1416
1417 /* Lancer Stats */
1418 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1419                                 struct be_dma_mem *nonemb_cmd)
1420 {
1421
1422         struct be_mcc_wrb *wrb;
1423         struct lancer_cmd_req_pport_stats *req;
1424         int status = 0;
1425
1426         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1427                             CMD_SUBSYSTEM_ETH))
1428                 return -EPERM;
1429
1430         spin_lock_bh(&adapter->mcc_lock);
1431
1432         wrb = wrb_from_mccq(adapter);
1433         if (!wrb) {
1434                 status = -EBUSY;
1435                 goto err;
1436         }
1437         req = nonemb_cmd->va;
1438
1439         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1440                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1441                         nonemb_cmd);
1442
1443         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1444         req->cmd_params.params.reset_stats = 0;
1445
1446         be_mcc_notify(adapter);
1447         adapter->stats_cmd_sent = true;
1448
1449 err:
1450         spin_unlock_bh(&adapter->mcc_lock);
1451         return status;
1452 }
1453
1454 static int be_mac_to_link_speed(int mac_speed)
1455 {
1456         switch (mac_speed) {
1457         case PHY_LINK_SPEED_ZERO:
1458                 return 0;
1459         case PHY_LINK_SPEED_10MBPS:
1460                 return 10;
1461         case PHY_LINK_SPEED_100MBPS:
1462                 return 100;
1463         case PHY_LINK_SPEED_1GBPS:
1464                 return 1000;
1465         case PHY_LINK_SPEED_10GBPS:
1466                 return 10000;
1467         case PHY_LINK_SPEED_20GBPS:
1468                 return 20000;
1469         case PHY_LINK_SPEED_25GBPS:
1470                 return 25000;
1471         case PHY_LINK_SPEED_40GBPS:
1472                 return 40000;
1473         }
1474         return 0;
1475 }
1476
1477 /* Uses synchronous mcc
1478  * Returns link_speed in Mbps
1479  */
1480 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1481                              u8 *link_status, u32 dom)
1482 {
1483         struct be_mcc_wrb *wrb;
1484         struct be_cmd_req_link_status *req;
1485         int status;
1486
1487         spin_lock_bh(&adapter->mcc_lock);
1488
1489         if (link_status)
1490                 *link_status = LINK_DOWN;
1491
1492         wrb = wrb_from_mccq(adapter);
1493         if (!wrb) {
1494                 status = -EBUSY;
1495                 goto err;
1496         }
1497         req = embedded_payload(wrb);
1498
1499         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1500                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1501
1502         /* version 1 of the cmd is not supported only by BE2 */
1503         if (!BE2_chip(adapter))
1504                 req->hdr.version = 1;
1505
1506         req->hdr.domain = dom;
1507
1508         status = be_mcc_notify_wait(adapter);
1509         if (!status) {
1510                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1511                 if (link_speed) {
1512                         *link_speed = resp->link_speed ?
1513                                       le16_to_cpu(resp->link_speed) * 10 :
1514                                       be_mac_to_link_speed(resp->mac_speed);
1515
1516                         if (!resp->logical_link_status)
1517                                 *link_speed = 0;
1518                 }
1519                 if (link_status)
1520                         *link_status = resp->logical_link_status;
1521         }
1522
1523 err:
1524         spin_unlock_bh(&adapter->mcc_lock);
1525         return status;
1526 }
1527
1528 /* Uses synchronous mcc */
1529 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1530 {
1531         struct be_mcc_wrb *wrb;
1532         struct be_cmd_req_get_cntl_addnl_attribs *req;
1533         int status;
1534
1535         spin_lock_bh(&adapter->mcc_lock);
1536
1537         wrb = wrb_from_mccq(adapter);
1538         if (!wrb) {
1539                 status = -EBUSY;
1540                 goto err;
1541         }
1542         req = embedded_payload(wrb);
1543
1544         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1545                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1546                 wrb, NULL);
1547
1548         be_mcc_notify(adapter);
1549
1550 err:
1551         spin_unlock_bh(&adapter->mcc_lock);
1552         return status;
1553 }
1554
1555 /* Uses synchronous mcc */
1556 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1557 {
1558         struct be_mcc_wrb *wrb;
1559         struct be_cmd_req_get_fat *req;
1560         int status;
1561
1562         spin_lock_bh(&adapter->mcc_lock);
1563
1564         wrb = wrb_from_mccq(adapter);
1565         if (!wrb) {
1566                 status = -EBUSY;
1567                 goto err;
1568         }
1569         req = embedded_payload(wrb);
1570
1571         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1572                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1573         req->fat_operation = cpu_to_le32(QUERY_FAT);
1574         status = be_mcc_notify_wait(adapter);
1575         if (!status) {
1576                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1577                 if (log_size && resp->log_size)
1578                         *log_size = le32_to_cpu(resp->log_size) -
1579                                         sizeof(u32);
1580         }
1581 err:
1582         spin_unlock_bh(&adapter->mcc_lock);
1583         return status;
1584 }
1585
1586 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1587 {
1588         struct be_dma_mem get_fat_cmd;
1589         struct be_mcc_wrb *wrb;
1590         struct be_cmd_req_get_fat *req;
1591         u32 offset = 0, total_size, buf_size,
1592                                 log_offset = sizeof(u32), payload_len;
1593         int status;
1594
1595         if (buf_len == 0)
1596                 return;
1597
1598         total_size = buf_len;
1599
1600         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1601         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1602                         get_fat_cmd.size,
1603                         &get_fat_cmd.dma);
1604         if (!get_fat_cmd.va) {
1605                 status = -ENOMEM;
1606                 dev_err(&adapter->pdev->dev,
1607                 "Memory allocation failure while retrieving FAT data\n");
1608                 return;
1609         }
1610
1611         spin_lock_bh(&adapter->mcc_lock);
1612
1613         while (total_size) {
1614                 buf_size = min(total_size, (u32)60*1024);
1615                 total_size -= buf_size;
1616
1617                 wrb = wrb_from_mccq(adapter);
1618                 if (!wrb) {
1619                         status = -EBUSY;
1620                         goto err;
1621                 }
1622                 req = get_fat_cmd.va;
1623
1624                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1625                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1626                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1627                                 &get_fat_cmd);
1628
1629                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1630                 req->read_log_offset = cpu_to_le32(log_offset);
1631                 req->read_log_length = cpu_to_le32(buf_size);
1632                 req->data_buffer_size = cpu_to_le32(buf_size);
1633
1634                 status = be_mcc_notify_wait(adapter);
1635                 if (!status) {
1636                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1637                         memcpy(buf + offset,
1638                                 resp->data_buffer,
1639                                 le32_to_cpu(resp->read_log_length));
1640                 } else {
1641                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1642                         goto err;
1643                 }
1644                 offset += buf_size;
1645                 log_offset += buf_size;
1646         }
1647 err:
1648         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1649                         get_fat_cmd.va,
1650                         get_fat_cmd.dma);
1651         spin_unlock_bh(&adapter->mcc_lock);
1652 }
1653
1654 /* Uses synchronous mcc */
1655 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1656                         char *fw_on_flash)
1657 {
1658         struct be_mcc_wrb *wrb;
1659         struct be_cmd_req_get_fw_version *req;
1660         int status;
1661
1662         spin_lock_bh(&adapter->mcc_lock);
1663
1664         wrb = wrb_from_mccq(adapter);
1665         if (!wrb) {
1666                 status = -EBUSY;
1667                 goto err;
1668         }
1669
1670         req = embedded_payload(wrb);
1671
1672         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1673                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1674         status = be_mcc_notify_wait(adapter);
1675         if (!status) {
1676                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1677                 strcpy(fw_ver, resp->firmware_version_string);
1678                 if (fw_on_flash)
1679                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1680         }
1681 err:
1682         spin_unlock_bh(&adapter->mcc_lock);
1683         return status;
1684 }
1685
1686 /* set the EQ delay interval of an EQ to specified value
1687  * Uses async mcc
1688  */
1689 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1690 {
1691         struct be_mcc_wrb *wrb;
1692         struct be_cmd_req_modify_eq_delay *req;
1693         int status = 0;
1694
1695         spin_lock_bh(&adapter->mcc_lock);
1696
1697         wrb = wrb_from_mccq(adapter);
1698         if (!wrb) {
1699                 status = -EBUSY;
1700                 goto err;
1701         }
1702         req = embedded_payload(wrb);
1703
1704         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1705                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1706
1707         req->num_eq = cpu_to_le32(1);
1708         req->delay[0].eq_id = cpu_to_le32(eq_id);
1709         req->delay[0].phase = 0;
1710         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1711
1712         be_mcc_notify(adapter);
1713
1714 err:
1715         spin_unlock_bh(&adapter->mcc_lock);
1716         return status;
1717 }
1718
1719 /* Uses sycnhronous mcc */
1720 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1721                         u32 num, bool untagged, bool promiscuous)
1722 {
1723         struct be_mcc_wrb *wrb;
1724         struct be_cmd_req_vlan_config *req;
1725         int status;
1726
1727         spin_lock_bh(&adapter->mcc_lock);
1728
1729         wrb = wrb_from_mccq(adapter);
1730         if (!wrb) {
1731                 status = -EBUSY;
1732                 goto err;
1733         }
1734         req = embedded_payload(wrb);
1735
1736         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1737                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1738
1739         req->interface_id = if_id;
1740         req->promiscuous = promiscuous;
1741         req->untagged = untagged;
1742         req->num_vlan = num;
1743         if (!promiscuous) {
1744                 memcpy(req->normal_vlan, vtag_array,
1745                         req->num_vlan * sizeof(vtag_array[0]));
1746         }
1747
1748         status = be_mcc_notify_wait(adapter);
1749
1750 err:
1751         spin_unlock_bh(&adapter->mcc_lock);
1752         return status;
1753 }
1754
1755 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1756 {
1757         struct be_mcc_wrb *wrb;
1758         struct be_dma_mem *mem = &adapter->rx_filter;
1759         struct be_cmd_req_rx_filter *req = mem->va;
1760         int status;
1761
1762         spin_lock_bh(&adapter->mcc_lock);
1763
1764         wrb = wrb_from_mccq(adapter);
1765         if (!wrb) {
1766                 status = -EBUSY;
1767                 goto err;
1768         }
1769         memset(req, 0, sizeof(*req));
1770         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1771                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1772                                 wrb, mem);
1773
1774         req->if_id = cpu_to_le32(adapter->if_handle);
1775         if (flags & IFF_PROMISC) {
1776                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1777                                         BE_IF_FLAGS_VLAN_PROMISCUOUS |
1778                                         BE_IF_FLAGS_MCAST_PROMISCUOUS);
1779                 if (value == ON)
1780                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1781                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1782                                                 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1783         } else if (flags & IFF_ALLMULTI) {
1784                 req->if_flags_mask = req->if_flags =
1785                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1786         } else {
1787                 struct netdev_hw_addr *ha;
1788                 int i = 0;
1789
1790                 req->if_flags_mask = req->if_flags =
1791                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1792
1793                 /* Reset mcast promisc mode if already set by setting mask
1794                  * and not setting flags field
1795                  */
1796                 req->if_flags_mask |=
1797                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1798                                     adapter->if_cap_flags);
1799
1800                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1801                 netdev_for_each_mc_addr(ha, adapter->netdev)
1802                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1803         }
1804
1805         status = be_mcc_notify_wait(adapter);
1806 err:
1807         spin_unlock_bh(&adapter->mcc_lock);
1808         return status;
1809 }
1810
1811 /* Uses synchrounous mcc */
1812 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1813 {
1814         struct be_mcc_wrb *wrb;
1815         struct be_cmd_req_set_flow_control *req;
1816         int status;
1817
1818         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1819                             CMD_SUBSYSTEM_COMMON))
1820                 return -EPERM;
1821
1822         spin_lock_bh(&adapter->mcc_lock);
1823
1824         wrb = wrb_from_mccq(adapter);
1825         if (!wrb) {
1826                 status = -EBUSY;
1827                 goto err;
1828         }
1829         req = embedded_payload(wrb);
1830
1831         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1832                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1833
1834         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1835         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1836
1837         status = be_mcc_notify_wait(adapter);
1838
1839 err:
1840         spin_unlock_bh(&adapter->mcc_lock);
1841         return status;
1842 }
1843
1844 /* Uses sycn mcc */
1845 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1846 {
1847         struct be_mcc_wrb *wrb;
1848         struct be_cmd_req_get_flow_control *req;
1849         int status;
1850
1851         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1852                             CMD_SUBSYSTEM_COMMON))
1853                 return -EPERM;
1854
1855         spin_lock_bh(&adapter->mcc_lock);
1856
1857         wrb = wrb_from_mccq(adapter);
1858         if (!wrb) {
1859                 status = -EBUSY;
1860                 goto err;
1861         }
1862         req = embedded_payload(wrb);
1863
1864         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1865                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1866
1867         status = be_mcc_notify_wait(adapter);
1868         if (!status) {
1869                 struct be_cmd_resp_get_flow_control *resp =
1870                                                 embedded_payload(wrb);
1871                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1872                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1873         }
1874
1875 err:
1876         spin_unlock_bh(&adapter->mcc_lock);
1877         return status;
1878 }
1879
1880 /* Uses mbox */
1881 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1882                         u32 *mode, u32 *caps, u16 *asic_rev)
1883 {
1884         struct be_mcc_wrb *wrb;
1885         struct be_cmd_req_query_fw_cfg *req;
1886         int status;
1887
1888         if (mutex_lock_interruptible(&adapter->mbox_lock))
1889                 return -1;
1890
1891         wrb = wrb_from_mbox(adapter);
1892         req = embedded_payload(wrb);
1893
1894         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1895                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1896
1897         status = be_mbox_notify_wait(adapter);
1898         if (!status) {
1899                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1900                 *port_num = le32_to_cpu(resp->phys_port);
1901                 *mode = le32_to_cpu(resp->function_mode);
1902                 *caps = le32_to_cpu(resp->function_caps);
1903                 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1904         }
1905
1906         mutex_unlock(&adapter->mbox_lock);
1907         return status;
1908 }
1909
1910 /* Uses mbox */
1911 int be_cmd_reset_function(struct be_adapter *adapter)
1912 {
1913         struct be_mcc_wrb *wrb;
1914         struct be_cmd_req_hdr *req;
1915         int status;
1916
1917         if (lancer_chip(adapter)) {
1918                 status = lancer_wait_ready(adapter);
1919                 if (!status) {
1920                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1921                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1922                         status = lancer_test_and_set_rdy_state(adapter);
1923                 }
1924                 if (status) {
1925                         dev_err(&adapter->pdev->dev,
1926                                 "Adapter in non recoverable error\n");
1927                 }
1928                 return status;
1929         }
1930
1931         if (mutex_lock_interruptible(&adapter->mbox_lock))
1932                 return -1;
1933
1934         wrb = wrb_from_mbox(adapter);
1935         req = embedded_payload(wrb);
1936
1937         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1938                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1939
1940         status = be_mbox_notify_wait(adapter);
1941
1942         mutex_unlock(&adapter->mbox_lock);
1943         return status;
1944 }
1945
1946 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1947                         u32 rss_hash_opts, u16 table_size)
1948 {
1949         struct be_mcc_wrb *wrb;
1950         struct be_cmd_req_rss_config *req;
1951         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1952                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1953                         0x3ea83c02, 0x4a110304};
1954         int status;
1955
1956         if (mutex_lock_interruptible(&adapter->mbox_lock))
1957                 return -1;
1958
1959         wrb = wrb_from_mbox(adapter);
1960         req = embedded_payload(wrb);
1961
1962         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1963                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1964
1965         req->if_id = cpu_to_le32(adapter->if_handle);
1966         req->enable_rss = cpu_to_le16(rss_hash_opts);
1967         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1968
1969         if (lancer_chip(adapter) || skyhawk_chip(adapter))
1970                 req->hdr.version = 1;
1971
1972         memcpy(req->cpu_table, rsstable, table_size);
1973         memcpy(req->hash, myhash, sizeof(myhash));
1974         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1975
1976         status = be_mbox_notify_wait(adapter);
1977
1978         mutex_unlock(&adapter->mbox_lock);
1979         return status;
1980 }
1981
1982 /* Uses sync mcc */
1983 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1984                         u8 bcn, u8 sts, u8 state)
1985 {
1986         struct be_mcc_wrb *wrb;
1987         struct be_cmd_req_enable_disable_beacon *req;
1988         int status;
1989
1990         spin_lock_bh(&adapter->mcc_lock);
1991
1992         wrb = wrb_from_mccq(adapter);
1993         if (!wrb) {
1994                 status = -EBUSY;
1995                 goto err;
1996         }
1997         req = embedded_payload(wrb);
1998
1999         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2000                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
2001
2002         req->port_num = port_num;
2003         req->beacon_state = state;
2004         req->beacon_duration = bcn;
2005         req->status_duration = sts;
2006
2007         status = be_mcc_notify_wait(adapter);
2008
2009 err:
2010         spin_unlock_bh(&adapter->mcc_lock);
2011         return status;
2012 }
2013
2014 /* Uses sync mcc */
2015 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2016 {
2017         struct be_mcc_wrb *wrb;
2018         struct be_cmd_req_get_beacon_state *req;
2019         int status;
2020
2021         spin_lock_bh(&adapter->mcc_lock);
2022
2023         wrb = wrb_from_mccq(adapter);
2024         if (!wrb) {
2025                 status = -EBUSY;
2026                 goto err;
2027         }
2028         req = embedded_payload(wrb);
2029
2030         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2031                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
2032
2033         req->port_num = port_num;
2034
2035         status = be_mcc_notify_wait(adapter);
2036         if (!status) {
2037                 struct be_cmd_resp_get_beacon_state *resp =
2038                                                 embedded_payload(wrb);
2039                 *state = resp->beacon_state;
2040         }
2041
2042 err:
2043         spin_unlock_bh(&adapter->mcc_lock);
2044         return status;
2045 }
2046
2047 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2048                             u32 data_size, u32 data_offset,
2049                             const char *obj_name, u32 *data_written,
2050                             u8 *change_status, u8 *addn_status)
2051 {
2052         struct be_mcc_wrb *wrb;
2053         struct lancer_cmd_req_write_object *req;
2054         struct lancer_cmd_resp_write_object *resp;
2055         void *ctxt = NULL;
2056         int status;
2057
2058         spin_lock_bh(&adapter->mcc_lock);
2059         adapter->flash_status = 0;
2060
2061         wrb = wrb_from_mccq(adapter);
2062         if (!wrb) {
2063                 status = -EBUSY;
2064                 goto err_unlock;
2065         }
2066
2067         req = embedded_payload(wrb);
2068
2069         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2070                                 OPCODE_COMMON_WRITE_OBJECT,
2071                                 sizeof(struct lancer_cmd_req_write_object), wrb,
2072                                 NULL);
2073
2074         ctxt = &req->context;
2075         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2076                         write_length, ctxt, data_size);
2077
2078         if (data_size == 0)
2079                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2080                                 eof, ctxt, 1);
2081         else
2082                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2083                                 eof, ctxt, 0);
2084
2085         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2086         req->write_offset = cpu_to_le32(data_offset);
2087         strcpy(req->object_name, obj_name);
2088         req->descriptor_count = cpu_to_le32(1);
2089         req->buf_len = cpu_to_le32(data_size);
2090         req->addr_low = cpu_to_le32((cmd->dma +
2091                                 sizeof(struct lancer_cmd_req_write_object))
2092                                 & 0xFFFFFFFF);
2093         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2094                                 sizeof(struct lancer_cmd_req_write_object)));
2095
2096         be_mcc_notify(adapter);
2097         spin_unlock_bh(&adapter->mcc_lock);
2098
2099         if (!wait_for_completion_timeout(&adapter->flash_compl,
2100                                          msecs_to_jiffies(60000)))
2101                 status = -1;
2102         else
2103                 status = adapter->flash_status;
2104
2105         resp = embedded_payload(wrb);
2106         if (!status) {
2107                 *data_written = le32_to_cpu(resp->actual_write_len);
2108                 *change_status = resp->change_status;
2109         } else {
2110                 *addn_status = resp->additional_status;
2111         }
2112
2113         return status;
2114
2115 err_unlock:
2116         spin_unlock_bh(&adapter->mcc_lock);
2117         return status;
2118 }
2119
2120 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2121                 u32 data_size, u32 data_offset, const char *obj_name,
2122                 u32 *data_read, u32 *eof, u8 *addn_status)
2123 {
2124         struct be_mcc_wrb *wrb;
2125         struct lancer_cmd_req_read_object *req;
2126         struct lancer_cmd_resp_read_object *resp;
2127         int status;
2128
2129         spin_lock_bh(&adapter->mcc_lock);
2130
2131         wrb = wrb_from_mccq(adapter);
2132         if (!wrb) {
2133                 status = -EBUSY;
2134                 goto err_unlock;
2135         }
2136
2137         req = embedded_payload(wrb);
2138
2139         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2140                         OPCODE_COMMON_READ_OBJECT,
2141                         sizeof(struct lancer_cmd_req_read_object), wrb,
2142                         NULL);
2143
2144         req->desired_read_len = cpu_to_le32(data_size);
2145         req->read_offset = cpu_to_le32(data_offset);
2146         strcpy(req->object_name, obj_name);
2147         req->descriptor_count = cpu_to_le32(1);
2148         req->buf_len = cpu_to_le32(data_size);
2149         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2150         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2151
2152         status = be_mcc_notify_wait(adapter);
2153
2154         resp = embedded_payload(wrb);
2155         if (!status) {
2156                 *data_read = le32_to_cpu(resp->actual_read_len);
2157                 *eof = le32_to_cpu(resp->eof);
2158         } else {
2159                 *addn_status = resp->additional_status;
2160         }
2161
2162 err_unlock:
2163         spin_unlock_bh(&adapter->mcc_lock);
2164         return status;
2165 }
2166
2167 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2168                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2169 {
2170         struct be_mcc_wrb *wrb;
2171         struct be_cmd_write_flashrom *req;
2172         int status;
2173
2174         spin_lock_bh(&adapter->mcc_lock);
2175         adapter->flash_status = 0;
2176
2177         wrb = wrb_from_mccq(adapter);
2178         if (!wrb) {
2179                 status = -EBUSY;
2180                 goto err_unlock;
2181         }
2182         req = cmd->va;
2183
2184         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2185                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2186
2187         req->params.op_type = cpu_to_le32(flash_type);
2188         req->params.op_code = cpu_to_le32(flash_opcode);
2189         req->params.data_buf_size = cpu_to_le32(buf_size);
2190
2191         be_mcc_notify(adapter);
2192         spin_unlock_bh(&adapter->mcc_lock);
2193
2194         if (!wait_for_completion_timeout(&adapter->flash_compl,
2195                         msecs_to_jiffies(40000)))
2196                 status = -1;
2197         else
2198                 status = adapter->flash_status;
2199
2200         return status;
2201
2202 err_unlock:
2203         spin_unlock_bh(&adapter->mcc_lock);
2204         return status;
2205 }
2206
2207 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2208                          int offset)
2209 {
2210         struct be_mcc_wrb *wrb;
2211         struct be_cmd_read_flash_crc *req;
2212         int status;
2213
2214         spin_lock_bh(&adapter->mcc_lock);
2215
2216         wrb = wrb_from_mccq(adapter);
2217         if (!wrb) {
2218                 status = -EBUSY;
2219                 goto err;
2220         }
2221         req = embedded_payload(wrb);
2222
2223         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2224                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2225                                wrb, NULL);
2226
2227         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2228         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2229         req->params.offset = cpu_to_le32(offset);
2230         req->params.data_buf_size = cpu_to_le32(0x4);
2231
2232         status = be_mcc_notify_wait(adapter);
2233         if (!status)
2234                 memcpy(flashed_crc, req->crc, 4);
2235
2236 err:
2237         spin_unlock_bh(&adapter->mcc_lock);
2238         return status;
2239 }
2240
2241 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2242                                 struct be_dma_mem *nonemb_cmd)
2243 {
2244         struct be_mcc_wrb *wrb;
2245         struct be_cmd_req_acpi_wol_magic_config *req;
2246         int status;
2247
2248         spin_lock_bh(&adapter->mcc_lock);
2249
2250         wrb = wrb_from_mccq(adapter);
2251         if (!wrb) {
2252                 status = -EBUSY;
2253                 goto err;
2254         }
2255         req = nonemb_cmd->va;
2256
2257         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2258                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2259                 nonemb_cmd);
2260         memcpy(req->magic_mac, mac, ETH_ALEN);
2261
2262         status = be_mcc_notify_wait(adapter);
2263
2264 err:
2265         spin_unlock_bh(&adapter->mcc_lock);
2266         return status;
2267 }
2268
2269 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2270                         u8 loopback_type, u8 enable)
2271 {
2272         struct be_mcc_wrb *wrb;
2273         struct be_cmd_req_set_lmode *req;
2274         int status;
2275
2276         spin_lock_bh(&adapter->mcc_lock);
2277
2278         wrb = wrb_from_mccq(adapter);
2279         if (!wrb) {
2280                 status = -EBUSY;
2281                 goto err;
2282         }
2283
2284         req = embedded_payload(wrb);
2285
2286         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2287                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2288                         NULL);
2289
2290         req->src_port = port_num;
2291         req->dest_port = port_num;
2292         req->loopback_type = loopback_type;
2293         req->loopback_state = enable;
2294
2295         status = be_mcc_notify_wait(adapter);
2296 err:
2297         spin_unlock_bh(&adapter->mcc_lock);
2298         return status;
2299 }
2300
2301 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2302                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2303 {
2304         struct be_mcc_wrb *wrb;
2305         struct be_cmd_req_loopback_test *req;
2306         int status;
2307
2308         spin_lock_bh(&adapter->mcc_lock);
2309
2310         wrb = wrb_from_mccq(adapter);
2311         if (!wrb) {
2312                 status = -EBUSY;
2313                 goto err;
2314         }
2315
2316         req = embedded_payload(wrb);
2317
2318         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2319                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2320         req->hdr.timeout = cpu_to_le32(4);
2321
2322         req->pattern = cpu_to_le64(pattern);
2323         req->src_port = cpu_to_le32(port_num);
2324         req->dest_port = cpu_to_le32(port_num);
2325         req->pkt_size = cpu_to_le32(pkt_size);
2326         req->num_pkts = cpu_to_le32(num_pkts);
2327         req->loopback_type = cpu_to_le32(loopback_type);
2328
2329         status = be_mcc_notify_wait(adapter);
2330         if (!status) {
2331                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2332                 status = le32_to_cpu(resp->status);
2333         }
2334
2335 err:
2336         spin_unlock_bh(&adapter->mcc_lock);
2337         return status;
2338 }
2339
2340 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2341                                 u32 byte_cnt, struct be_dma_mem *cmd)
2342 {
2343         struct be_mcc_wrb *wrb;
2344         struct be_cmd_req_ddrdma_test *req;
2345         int status;
2346         int i, j = 0;
2347
2348         spin_lock_bh(&adapter->mcc_lock);
2349
2350         wrb = wrb_from_mccq(adapter);
2351         if (!wrb) {
2352                 status = -EBUSY;
2353                 goto err;
2354         }
2355         req = cmd->va;
2356         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2357                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2358
2359         req->pattern = cpu_to_le64(pattern);
2360         req->byte_count = cpu_to_le32(byte_cnt);
2361         for (i = 0; i < byte_cnt; i++) {
2362                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2363                 j++;
2364                 if (j > 7)
2365                         j = 0;
2366         }
2367
2368         status = be_mcc_notify_wait(adapter);
2369
2370         if (!status) {
2371                 struct be_cmd_resp_ddrdma_test *resp;
2372                 resp = cmd->va;
2373                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2374                                 resp->snd_err) {
2375                         status = -1;
2376                 }
2377         }
2378
2379 err:
2380         spin_unlock_bh(&adapter->mcc_lock);
2381         return status;
2382 }
2383
2384 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2385                                 struct be_dma_mem *nonemb_cmd)
2386 {
2387         struct be_mcc_wrb *wrb;
2388         struct be_cmd_req_seeprom_read *req;
2389         int status;
2390
2391         spin_lock_bh(&adapter->mcc_lock);
2392
2393         wrb = wrb_from_mccq(adapter);
2394         if (!wrb) {
2395                 status = -EBUSY;
2396                 goto err;
2397         }
2398         req = nonemb_cmd->va;
2399
2400         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2401                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2402                         nonemb_cmd);
2403
2404         status = be_mcc_notify_wait(adapter);
2405
2406 err:
2407         spin_unlock_bh(&adapter->mcc_lock);
2408         return status;
2409 }
2410
2411 int be_cmd_get_phy_info(struct be_adapter *adapter)
2412 {
2413         struct be_mcc_wrb *wrb;
2414         struct be_cmd_req_get_phy_info *req;
2415         struct be_dma_mem cmd;
2416         int status;
2417
2418         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2419                             CMD_SUBSYSTEM_COMMON))
2420                 return -EPERM;
2421
2422         spin_lock_bh(&adapter->mcc_lock);
2423
2424         wrb = wrb_from_mccq(adapter);
2425         if (!wrb) {
2426                 status = -EBUSY;
2427                 goto err;
2428         }
2429         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2430         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2431                                         &cmd.dma);
2432         if (!cmd.va) {
2433                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2434                 status = -ENOMEM;
2435                 goto err;
2436         }
2437
2438         req = cmd.va;
2439
2440         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2441                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2442                         wrb, &cmd);
2443
2444         status = be_mcc_notify_wait(adapter);
2445         if (!status) {
2446                 struct be_phy_info *resp_phy_info =
2447                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2448                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2449                 adapter->phy.interface_type =
2450                         le16_to_cpu(resp_phy_info->interface_type);
2451                 adapter->phy.auto_speeds_supported =
2452                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2453                 adapter->phy.fixed_speeds_supported =
2454                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2455                 adapter->phy.misc_params =
2456                         le32_to_cpu(resp_phy_info->misc_params);
2457         }
2458         pci_free_consistent(adapter->pdev, cmd.size,
2459                                 cmd.va, cmd.dma);
2460 err:
2461         spin_unlock_bh(&adapter->mcc_lock);
2462         return status;
2463 }
2464
2465 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2466 {
2467         struct be_mcc_wrb *wrb;
2468         struct be_cmd_req_set_qos *req;
2469         int status;
2470
2471         spin_lock_bh(&adapter->mcc_lock);
2472
2473         wrb = wrb_from_mccq(adapter);
2474         if (!wrb) {
2475                 status = -EBUSY;
2476                 goto err;
2477         }
2478
2479         req = embedded_payload(wrb);
2480
2481         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2482                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2483
2484         req->hdr.domain = domain;
2485         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2486         req->max_bps_nic = cpu_to_le32(bps);
2487
2488         status = be_mcc_notify_wait(adapter);
2489
2490 err:
2491         spin_unlock_bh(&adapter->mcc_lock);
2492         return status;
2493 }
2494
2495 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2496 {
2497         struct be_mcc_wrb *wrb;
2498         struct be_cmd_req_cntl_attribs *req;
2499         struct be_cmd_resp_cntl_attribs *resp;
2500         int status;
2501         int payload_len = max(sizeof(*req), sizeof(*resp));
2502         struct mgmt_controller_attrib *attribs;
2503         struct be_dma_mem attribs_cmd;
2504
2505         if (mutex_lock_interruptible(&adapter->mbox_lock))
2506                 return -1;
2507
2508         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2509         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2510         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2511                                                 &attribs_cmd.dma);
2512         if (!attribs_cmd.va) {
2513                 dev_err(&adapter->pdev->dev,
2514                                 "Memory allocation failure\n");
2515                 status = -ENOMEM;
2516                 goto err;
2517         }
2518
2519         wrb = wrb_from_mbox(adapter);
2520         if (!wrb) {
2521                 status = -EBUSY;
2522                 goto err;
2523         }
2524         req = attribs_cmd.va;
2525
2526         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2527                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2528                         &attribs_cmd);
2529
2530         status = be_mbox_notify_wait(adapter);
2531         if (!status) {
2532                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2533                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2534         }
2535
2536 err:
2537         mutex_unlock(&adapter->mbox_lock);
2538         if (attribs_cmd.va)
2539                 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2540                                     attribs_cmd.va, attribs_cmd.dma);
2541         return status;
2542 }
2543
2544 /* Uses mbox */
2545 int be_cmd_req_native_mode(struct be_adapter *adapter)
2546 {
2547         struct be_mcc_wrb *wrb;
2548         struct be_cmd_req_set_func_cap *req;
2549         int status;
2550
2551         if (mutex_lock_interruptible(&adapter->mbox_lock))
2552                 return -1;
2553
2554         wrb = wrb_from_mbox(adapter);
2555         if (!wrb) {
2556                 status = -EBUSY;
2557                 goto err;
2558         }
2559
2560         req = embedded_payload(wrb);
2561
2562         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2563                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2564
2565         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2566                                 CAPABILITY_BE3_NATIVE_ERX_API);
2567         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2568
2569         status = be_mbox_notify_wait(adapter);
2570         if (!status) {
2571                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2572                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2573                                         CAPABILITY_BE3_NATIVE_ERX_API;
2574                 if (!adapter->be3_native)
2575                         dev_warn(&adapter->pdev->dev,
2576                                  "adapter not in advanced mode\n");
2577         }
2578 err:
2579         mutex_unlock(&adapter->mbox_lock);
2580         return status;
2581 }
2582
2583 /* Get privilege(s) for a function */
2584 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2585                              u32 domain)
2586 {
2587         struct be_mcc_wrb *wrb;
2588         struct be_cmd_req_get_fn_privileges *req;
2589         int status;
2590
2591         spin_lock_bh(&adapter->mcc_lock);
2592
2593         wrb = wrb_from_mccq(adapter);
2594         if (!wrb) {
2595                 status = -EBUSY;
2596                 goto err;
2597         }
2598
2599         req = embedded_payload(wrb);
2600
2601         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2602                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2603                                wrb, NULL);
2604
2605         req->hdr.domain = domain;
2606
2607         status = be_mcc_notify_wait(adapter);
2608         if (!status) {
2609                 struct be_cmd_resp_get_fn_privileges *resp =
2610                                                 embedded_payload(wrb);
2611                 *privilege = le32_to_cpu(resp->privilege_mask);
2612         }
2613
2614 err:
2615         spin_unlock_bh(&adapter->mcc_lock);
2616         return status;
2617 }
2618
2619 /* Set privilege(s) for a function */
2620 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2621                              u32 domain)
2622 {
2623         struct be_mcc_wrb *wrb;
2624         struct be_cmd_req_set_fn_privileges *req;
2625         int status;
2626
2627         spin_lock_bh(&adapter->mcc_lock);
2628
2629         wrb = wrb_from_mccq(adapter);
2630         if (!wrb) {
2631                 status = -EBUSY;
2632                 goto err;
2633         }
2634
2635         req = embedded_payload(wrb);
2636         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2637                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
2638                                wrb, NULL);
2639         req->hdr.domain = domain;
2640         if (lancer_chip(adapter))
2641                 req->privileges_lancer = cpu_to_le32(privileges);
2642         else
2643                 req->privileges = cpu_to_le32(privileges);
2644
2645         status = be_mcc_notify_wait(adapter);
2646 err:
2647         spin_unlock_bh(&adapter->mcc_lock);
2648         return status;
2649 }
2650
2651 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
2652  * pmac_id_valid: false => pmac_id or MAC address is requested.
2653  *                If pmac_id is returned, pmac_id_valid is returned as true
2654  */
2655 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2656                              bool *pmac_id_valid, u32 *pmac_id, u8 domain)
2657 {
2658         struct be_mcc_wrb *wrb;
2659         struct be_cmd_req_get_mac_list *req;
2660         int status;
2661         int mac_count;
2662         struct be_dma_mem get_mac_list_cmd;
2663         int i;
2664
2665         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2666         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2667         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2668                         get_mac_list_cmd.size,
2669                         &get_mac_list_cmd.dma);
2670
2671         if (!get_mac_list_cmd.va) {
2672                 dev_err(&adapter->pdev->dev,
2673                                 "Memory allocation failure during GET_MAC_LIST\n");
2674                 return -ENOMEM;
2675         }
2676
2677         spin_lock_bh(&adapter->mcc_lock);
2678
2679         wrb = wrb_from_mccq(adapter);
2680         if (!wrb) {
2681                 status = -EBUSY;
2682                 goto out;
2683         }
2684
2685         req = get_mac_list_cmd.va;
2686
2687         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2688                                OPCODE_COMMON_GET_MAC_LIST,
2689                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
2690         req->hdr.domain = domain;
2691         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2692         if (*pmac_id_valid) {
2693                 req->mac_id = cpu_to_le32(*pmac_id);
2694                 req->iface_id = cpu_to_le16(adapter->if_handle);
2695                 req->perm_override = 0;
2696         } else {
2697                 req->perm_override = 1;
2698         }
2699
2700         status = be_mcc_notify_wait(adapter);
2701         if (!status) {
2702                 struct be_cmd_resp_get_mac_list *resp =
2703                                                 get_mac_list_cmd.va;
2704
2705                 if (*pmac_id_valid) {
2706                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
2707                                ETH_ALEN);
2708                         goto out;
2709                 }
2710
2711                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2712                 /* Mac list returned could contain one or more active mac_ids
2713                  * or one or more true or pseudo permanant mac addresses.
2714                  * If an active mac_id is present, return first active mac_id
2715                  * found.
2716                  */
2717                 for (i = 0; i < mac_count; i++) {
2718                         struct get_list_macaddr *mac_entry;
2719                         u16 mac_addr_size;
2720                         u32 mac_id;
2721
2722                         mac_entry = &resp->macaddr_list[i];
2723                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2724                         /* mac_id is a 32 bit value and mac_addr size
2725                          * is 6 bytes
2726                          */
2727                         if (mac_addr_size == sizeof(u32)) {
2728                                 *pmac_id_valid = true;
2729                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2730                                 *pmac_id = le32_to_cpu(mac_id);
2731                                 goto out;
2732                         }
2733                 }
2734                 /* If no active mac_id found, return first mac addr */
2735                 *pmac_id_valid = false;
2736                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2737                                                                 ETH_ALEN);
2738         }
2739
2740 out:
2741         spin_unlock_bh(&adapter->mcc_lock);
2742         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2743                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2744         return status;
2745 }
2746
2747 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id, u8 *mac)
2748 {
2749         bool active = true;
2750
2751         if (BEx_chip(adapter))
2752                 return be_cmd_mac_addr_query(adapter, mac, false,
2753                                              adapter->if_handle, curr_pmac_id);
2754         else
2755                 /* Fetch the MAC address using pmac_id */
2756                 return be_cmd_get_mac_from_list(adapter, mac, &active,
2757                                                 &curr_pmac_id, 0);
2758 }
2759
2760 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
2761 {
2762         int status;
2763         bool pmac_valid = false;
2764
2765         memset(mac, 0, ETH_ALEN);
2766
2767         if (BEx_chip(adapter)) {
2768                 if (be_physfn(adapter))
2769                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
2770                                                        0);
2771                 else
2772                         status = be_cmd_mac_addr_query(adapter, mac, false,
2773                                                        adapter->if_handle, 0);
2774         } else {
2775                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
2776                                                   NULL, 0);
2777         }
2778
2779         return status;
2780 }
2781
2782 /* Uses synchronous MCCQ */
2783 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2784                         u8 mac_count, u32 domain)
2785 {
2786         struct be_mcc_wrb *wrb;
2787         struct be_cmd_req_set_mac_list *req;
2788         int status;
2789         struct be_dma_mem cmd;
2790
2791         memset(&cmd, 0, sizeof(struct be_dma_mem));
2792         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2793         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2794                         &cmd.dma, GFP_KERNEL);
2795         if (!cmd.va)
2796                 return -ENOMEM;
2797
2798         spin_lock_bh(&adapter->mcc_lock);
2799
2800         wrb = wrb_from_mccq(adapter);
2801         if (!wrb) {
2802                 status = -EBUSY;
2803                 goto err;
2804         }
2805
2806         req = cmd.va;
2807         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2808                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2809                                 wrb, &cmd);
2810
2811         req->hdr.domain = domain;
2812         req->mac_count = mac_count;
2813         if (mac_count)
2814                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2815
2816         status = be_mcc_notify_wait(adapter);
2817
2818 err:
2819         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2820                                 cmd.va, cmd.dma);
2821         spin_unlock_bh(&adapter->mcc_lock);
2822         return status;
2823 }
2824
2825 /* Wrapper to delete any active MACs and provision the new mac.
2826  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
2827  * current list are active.
2828  */
2829 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
2830 {
2831         bool active_mac = false;
2832         u8 old_mac[ETH_ALEN];
2833         u32 pmac_id;
2834         int status;
2835
2836         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
2837                                           &pmac_id, dom);
2838         if (!status && active_mac)
2839                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
2840
2841         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
2842 }
2843
2844 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2845                         u32 domain, u16 intf_id)
2846 {
2847         struct be_mcc_wrb *wrb;
2848         struct be_cmd_req_set_hsw_config *req;
2849         void *ctxt;
2850         int status;
2851
2852         spin_lock_bh(&adapter->mcc_lock);
2853
2854         wrb = wrb_from_mccq(adapter);
2855         if (!wrb) {
2856                 status = -EBUSY;
2857                 goto err;
2858         }
2859
2860         req = embedded_payload(wrb);
2861         ctxt = &req->context;
2862
2863         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2864                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2865
2866         req->hdr.domain = domain;
2867         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2868         if (pvid) {
2869                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2870                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2871         }
2872
2873         be_dws_cpu_to_le(req->context, sizeof(req->context));
2874         status = be_mcc_notify_wait(adapter);
2875
2876 err:
2877         spin_unlock_bh(&adapter->mcc_lock);
2878         return status;
2879 }
2880
2881 /* Get Hyper switch config */
2882 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2883                         u32 domain, u16 intf_id)
2884 {
2885         struct be_mcc_wrb *wrb;
2886         struct be_cmd_req_get_hsw_config *req;
2887         void *ctxt;
2888         int status;
2889         u16 vid;
2890
2891         spin_lock_bh(&adapter->mcc_lock);
2892
2893         wrb = wrb_from_mccq(adapter);
2894         if (!wrb) {
2895                 status = -EBUSY;
2896                 goto err;
2897         }
2898
2899         req = embedded_payload(wrb);
2900         ctxt = &req->context;
2901
2902         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2903                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2904
2905         req->hdr.domain = domain;
2906         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2907                                                                 intf_id);
2908         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2909         be_dws_cpu_to_le(req->context, sizeof(req->context));
2910
2911         status = be_mcc_notify_wait(adapter);
2912         if (!status) {
2913                 struct be_cmd_resp_get_hsw_config *resp =
2914                                                 embedded_payload(wrb);
2915                 be_dws_le_to_cpu(&resp->context,
2916                                                 sizeof(resp->context));
2917                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2918                                                         pvid, &resp->context);
2919                 *pvid = le16_to_cpu(vid);
2920         }
2921
2922 err:
2923         spin_unlock_bh(&adapter->mcc_lock);
2924         return status;
2925 }
2926
2927 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2928 {
2929         struct be_mcc_wrb *wrb;
2930         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2931         int status;
2932         int payload_len = sizeof(*req);
2933         struct be_dma_mem cmd;
2934
2935         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2936                             CMD_SUBSYSTEM_ETH))
2937                 return -EPERM;
2938
2939         if (mutex_lock_interruptible(&adapter->mbox_lock))
2940                 return -1;
2941
2942         memset(&cmd, 0, sizeof(struct be_dma_mem));
2943         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2944         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2945                                                &cmd.dma);
2946         if (!cmd.va) {
2947                 dev_err(&adapter->pdev->dev,
2948                                 "Memory allocation failure\n");
2949                 status = -ENOMEM;
2950                 goto err;
2951         }
2952
2953         wrb = wrb_from_mbox(adapter);
2954         if (!wrb) {
2955                 status = -EBUSY;
2956                 goto err;
2957         }
2958
2959         req = cmd.va;
2960
2961         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2962                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2963                                payload_len, wrb, &cmd);
2964
2965         req->hdr.version = 1;
2966         req->query_options = BE_GET_WOL_CAP;
2967
2968         status = be_mbox_notify_wait(adapter);
2969         if (!status) {
2970                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2971                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2972
2973                 /* the command could succeed misleadingly on old f/w
2974                  * which is not aware of the V1 version. fake an error. */
2975                 if (resp->hdr.response_length < payload_len) {
2976                         status = -1;
2977                         goto err;
2978                 }
2979                 adapter->wol_cap = resp->wol_settings;
2980         }
2981 err:
2982         mutex_unlock(&adapter->mbox_lock);
2983         if (cmd.va)
2984                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2985         return status;
2986
2987 }
2988 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2989                                    struct be_dma_mem *cmd)
2990 {
2991         struct be_mcc_wrb *wrb;
2992         struct be_cmd_req_get_ext_fat_caps *req;
2993         int status;
2994
2995         if (mutex_lock_interruptible(&adapter->mbox_lock))
2996                 return -1;
2997
2998         wrb = wrb_from_mbox(adapter);
2999         if (!wrb) {
3000                 status = -EBUSY;
3001                 goto err;
3002         }
3003
3004         req = cmd->va;
3005         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3006                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3007                                cmd->size, wrb, cmd);
3008         req->parameter_type = cpu_to_le32(1);
3009
3010         status = be_mbox_notify_wait(adapter);
3011 err:
3012         mutex_unlock(&adapter->mbox_lock);
3013         return status;
3014 }
3015
3016 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3017                                    struct be_dma_mem *cmd,
3018                                    struct be_fat_conf_params *configs)
3019 {
3020         struct be_mcc_wrb *wrb;
3021         struct be_cmd_req_set_ext_fat_caps *req;
3022         int status;
3023
3024         spin_lock_bh(&adapter->mcc_lock);
3025
3026         wrb = wrb_from_mccq(adapter);
3027         if (!wrb) {
3028                 status = -EBUSY;
3029                 goto err;
3030         }
3031
3032         req = cmd->va;
3033         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3034         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3035                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3036                                cmd->size, wrb, cmd);
3037
3038         status = be_mcc_notify_wait(adapter);
3039 err:
3040         spin_unlock_bh(&adapter->mcc_lock);
3041         return status;
3042 }
3043
3044 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
3045 {
3046         struct be_mcc_wrb *wrb;
3047         struct be_cmd_req_get_port_name *req;
3048         int status;
3049
3050         if (!lancer_chip(adapter)) {
3051                 *port_name = adapter->hba_port_num + '0';
3052                 return 0;
3053         }
3054
3055         spin_lock_bh(&adapter->mcc_lock);
3056
3057         wrb = wrb_from_mccq(adapter);
3058         if (!wrb) {
3059                 status = -EBUSY;
3060                 goto err;
3061         }
3062
3063         req = embedded_payload(wrb);
3064
3065         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3066                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3067                                NULL);
3068         req->hdr.version = 1;
3069
3070         status = be_mcc_notify_wait(adapter);
3071         if (!status) {
3072                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3073                 *port_name = resp->port_name[adapter->hba_port_num];
3074         } else {
3075                 *port_name = adapter->hba_port_num + '0';
3076         }
3077 err:
3078         spin_unlock_bh(&adapter->mcc_lock);
3079         return status;
3080 }
3081
3082 static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3083                                                     u32 max_buf_size)
3084 {
3085         struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf;
3086         int i;
3087
3088         for (i = 0; i < desc_count; i++) {
3089                 desc->desc_len = desc->desc_len ? : RESOURCE_DESC_SIZE;
3090                 if (((void *)desc + desc->desc_len) >
3091                     (void *)(buf + max_buf_size))
3092                         return NULL;
3093
3094                 if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3095                     desc->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
3096                         return desc;
3097
3098                 desc = (void *)desc + desc->desc_len;
3099         }
3100
3101         return NULL;
3102 }
3103
3104 /* Uses Mbox */
3105 int be_cmd_get_func_config(struct be_adapter *adapter)
3106 {
3107         struct be_mcc_wrb *wrb;
3108         struct be_cmd_req_get_func_config *req;
3109         int status;
3110         struct be_dma_mem cmd;
3111
3112         if (mutex_lock_interruptible(&adapter->mbox_lock))
3113                 return -1;
3114
3115         memset(&cmd, 0, sizeof(struct be_dma_mem));
3116         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3117         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3118                                       &cmd.dma);
3119         if (!cmd.va) {
3120                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3121                 status = -ENOMEM;
3122                 goto err;
3123         }
3124
3125         wrb = wrb_from_mbox(adapter);
3126         if (!wrb) {
3127                 status = -EBUSY;
3128                 goto err;
3129         }
3130
3131         req = cmd.va;
3132
3133         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3134                                OPCODE_COMMON_GET_FUNC_CONFIG,
3135                                cmd.size, wrb, &cmd);
3136
3137         if (skyhawk_chip(adapter))
3138                 req->hdr.version = 1;
3139
3140         status = be_mbox_notify_wait(adapter);
3141         if (!status) {
3142                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3143                 u32 desc_count = le32_to_cpu(resp->desc_count);
3144                 struct be_nic_resource_desc *desc;
3145
3146                 desc = be_get_nic_desc(resp->func_param, desc_count,
3147                                        sizeof(resp->func_param));
3148                 if (!desc) {
3149                         status = -EINVAL;
3150                         goto err;
3151                 }
3152
3153                 adapter->pf_number = desc->pf_num;
3154                 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count);
3155                 adapter->max_vlans = le16_to_cpu(desc->vlan_count);
3156                 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3157                 adapter->max_tx_queues = le16_to_cpu(desc->txq_count);
3158                 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count);
3159                 adapter->max_rx_queues = le16_to_cpu(desc->rq_count);
3160
3161                 adapter->max_event_queues = le16_to_cpu(desc->eq_count);
3162                 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags);
3163         }
3164 err:
3165         mutex_unlock(&adapter->mbox_lock);
3166         if (cmd.va)
3167                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3168         return status;
3169 }
3170
3171 /* Uses mbox */
3172 static int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3173                                         u8 domain, struct be_dma_mem *cmd)
3174 {
3175         struct be_mcc_wrb *wrb;
3176         struct be_cmd_req_get_profile_config *req;
3177         int status;
3178
3179         if (mutex_lock_interruptible(&adapter->mbox_lock))
3180                 return -1;
3181         wrb = wrb_from_mbox(adapter);
3182
3183         req = cmd->va;
3184         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3185                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3186                                cmd->size, wrb, cmd);
3187
3188         req->type = ACTIVE_PROFILE_TYPE;
3189         req->hdr.domain = domain;
3190         if (!lancer_chip(adapter))
3191                 req->hdr.version = 1;
3192
3193         status = be_mbox_notify_wait(adapter);
3194
3195         mutex_unlock(&adapter->mbox_lock);
3196         return status;
3197 }
3198
3199 /* Uses sync mcc */
3200 static int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3201                                         u8 domain, struct be_dma_mem *cmd)
3202 {
3203         struct be_mcc_wrb *wrb;
3204         struct be_cmd_req_get_profile_config *req;
3205         int status;
3206
3207         spin_lock_bh(&adapter->mcc_lock);
3208
3209         wrb = wrb_from_mccq(adapter);
3210         if (!wrb) {
3211                 status = -EBUSY;
3212                 goto err;
3213         }
3214
3215         req = cmd->va;
3216         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3217                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3218                                cmd->size, wrb, cmd);
3219
3220         req->type = ACTIVE_PROFILE_TYPE;
3221         req->hdr.domain = domain;
3222         if (!lancer_chip(adapter))
3223                 req->hdr.version = 1;
3224
3225         status = be_mcc_notify_wait(adapter);
3226
3227 err:
3228         spin_unlock_bh(&adapter->mcc_lock);
3229         return status;
3230 }
3231
3232 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3233 int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
3234                               u16 *txq_count, u8 domain)
3235 {
3236         struct be_queue_info *mccq = &adapter->mcc_obj.q;
3237         struct be_dma_mem cmd;
3238         int status;
3239
3240         memset(&cmd, 0, sizeof(struct be_dma_mem));
3241         if (!lancer_chip(adapter))
3242                 cmd.size = sizeof(struct be_cmd_resp_get_profile_config_v1);
3243         else
3244                 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3245         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3246                                       &cmd.dma);
3247         if (!cmd.va) {
3248                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3249                 return -ENOMEM;
3250         }
3251
3252         if (!mccq->created)
3253                 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3254         else
3255                 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3256         if (!status) {
3257                 struct be_cmd_resp_get_profile_config *resp = cmd.va;
3258                 u32 desc_count = le32_to_cpu(resp->desc_count);
3259                 struct be_nic_resource_desc *desc;
3260
3261                 desc = be_get_nic_desc(resp->func_param, desc_count,
3262                                        sizeof(resp->func_param));
3263
3264                 if (!desc) {
3265                         status = -EINVAL;
3266                         goto err;
3267                 }
3268                 if (cap_flags)
3269                         *cap_flags = le32_to_cpu(desc->cap_flags);
3270                 if (txq_count)
3271                         *txq_count = le32_to_cpu(desc->txq_count);
3272         }
3273 err:
3274         if (cmd.va)
3275                 pci_free_consistent(adapter->pdev, cmd.size,
3276                                     cmd.va, cmd.dma);
3277         return status;
3278 }
3279
3280 /* Uses sync mcc */
3281 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3282                               u8 domain)
3283 {
3284         struct be_mcc_wrb *wrb;
3285         struct be_cmd_req_set_profile_config *req;
3286         int status;
3287
3288         spin_lock_bh(&adapter->mcc_lock);
3289
3290         wrb = wrb_from_mccq(adapter);
3291         if (!wrb) {
3292                 status = -EBUSY;
3293                 goto err;
3294         }
3295
3296         req = embedded_payload(wrb);
3297
3298         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3299                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3300                                wrb, NULL);
3301
3302         req->hdr.domain = domain;
3303         req->desc_count = cpu_to_le32(1);
3304
3305         req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3306         req->nic_desc.desc_len = RESOURCE_DESC_SIZE;
3307         req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3308         req->nic_desc.pf_num = adapter->pf_number;
3309         req->nic_desc.vf_num = domain;
3310
3311         /* Mark fields invalid */
3312         req->nic_desc.unicast_mac_count = 0xFFFF;
3313         req->nic_desc.mcc_count = 0xFFFF;
3314         req->nic_desc.vlan_count = 0xFFFF;
3315         req->nic_desc.mcast_mac_count = 0xFFFF;
3316         req->nic_desc.txq_count = 0xFFFF;
3317         req->nic_desc.rq_count = 0xFFFF;
3318         req->nic_desc.rssq_count = 0xFFFF;
3319         req->nic_desc.lro_count = 0xFFFF;
3320         req->nic_desc.cq_count = 0xFFFF;
3321         req->nic_desc.toe_conn_count = 0xFFFF;
3322         req->nic_desc.eq_count = 0xFFFF;
3323         req->nic_desc.link_param = 0xFF;
3324         req->nic_desc.bw_min = 0xFFFFFFFF;
3325         req->nic_desc.acpi_params = 0xFF;
3326         req->nic_desc.wol_param = 0x0F;
3327
3328         /* Change BW */
3329         req->nic_desc.bw_min = cpu_to_le32(bps);
3330         req->nic_desc.bw_max = cpu_to_le32(bps);
3331         status = be_mcc_notify_wait(adapter);
3332 err:
3333         spin_unlock_bh(&adapter->mcc_lock);
3334         return status;
3335 }
3336
3337 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3338                      int vf_num)
3339 {
3340         struct be_mcc_wrb *wrb;
3341         struct be_cmd_req_get_iface_list *req;
3342         struct be_cmd_resp_get_iface_list *resp;
3343         int status;
3344
3345         spin_lock_bh(&adapter->mcc_lock);
3346
3347         wrb = wrb_from_mccq(adapter);
3348         if (!wrb) {
3349                 status = -EBUSY;
3350                 goto err;
3351         }
3352         req = embedded_payload(wrb);
3353
3354         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3355                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3356                                wrb, NULL);
3357         req->hdr.domain = vf_num + 1;
3358
3359         status = be_mcc_notify_wait(adapter);
3360         if (!status) {
3361                 resp = (struct be_cmd_resp_get_iface_list *)req;
3362                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3363         }
3364
3365 err:
3366         spin_unlock_bh(&adapter->mcc_lock);
3367         return status;
3368 }
3369
3370 static int lancer_wait_idle(struct be_adapter *adapter)
3371 {
3372 #define SLIPORT_IDLE_TIMEOUT 30
3373         u32 reg_val;
3374         int status = 0, i;
3375
3376         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
3377                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
3378                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
3379                         break;
3380
3381                 ssleep(1);
3382         }
3383
3384         if (i == SLIPORT_IDLE_TIMEOUT)
3385                 status = -1;
3386
3387         return status;
3388 }
3389
3390 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
3391 {
3392         int status = 0;
3393
3394         status = lancer_wait_idle(adapter);
3395         if (status)
3396                 return status;
3397
3398         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
3399
3400         return status;
3401 }
3402
3403 /* Routine to check whether dump image is present or not */
3404 bool dump_present(struct be_adapter *adapter)
3405 {
3406         u32 sliport_status = 0;
3407
3408         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
3409         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
3410 }
3411
3412 int lancer_initiate_dump(struct be_adapter *adapter)
3413 {
3414         int status;
3415
3416         /* give firmware reset and diagnostic dump */
3417         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
3418                                      PHYSDEV_CONTROL_DD_MASK);
3419         if (status < 0) {
3420                 dev_err(&adapter->pdev->dev, "Firmware reset failed\n");
3421                 return status;
3422         }
3423
3424         status = lancer_wait_idle(adapter);
3425         if (status)
3426                 return status;
3427
3428         if (!dump_present(adapter)) {
3429                 dev_err(&adapter->pdev->dev, "Dump image not present\n");
3430                 return -1;
3431         }
3432
3433         return 0;
3434 }
3435
3436 /* Uses sync mcc */
3437 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3438 {
3439         struct be_mcc_wrb *wrb;
3440         struct be_cmd_enable_disable_vf *req;
3441         int status;
3442
3443         if (!lancer_chip(adapter))
3444                 return 0;
3445
3446         spin_lock_bh(&adapter->mcc_lock);
3447
3448         wrb = wrb_from_mccq(adapter);
3449         if (!wrb) {
3450                 status = -EBUSY;
3451                 goto err;
3452         }
3453
3454         req = embedded_payload(wrb);
3455
3456         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3457                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3458                                wrb, NULL);
3459
3460         req->hdr.domain = domain;
3461         req->enable = 1;
3462         status = be_mcc_notify_wait(adapter);
3463 err:
3464         spin_unlock_bh(&adapter->mcc_lock);
3465         return status;
3466 }
3467
3468 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3469 {
3470         struct be_mcc_wrb *wrb;
3471         struct be_cmd_req_intr_set *req;
3472         int status;
3473
3474         if (mutex_lock_interruptible(&adapter->mbox_lock))
3475                 return -1;
3476
3477         wrb = wrb_from_mbox(adapter);
3478
3479         req = embedded_payload(wrb);
3480
3481         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3482                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3483                                wrb, NULL);
3484
3485         req->intr_enabled = intr_enable;
3486
3487         status = be_mbox_notify_wait(adapter);
3488
3489         mutex_unlock(&adapter->mbox_lock);
3490         return status;
3491 }
3492
3493 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3494                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3495 {
3496         struct be_adapter *adapter = netdev_priv(netdev_handle);
3497         struct be_mcc_wrb *wrb;
3498         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3499         struct be_cmd_req_hdr *req;
3500         struct be_cmd_resp_hdr *resp;
3501         int status;
3502
3503         spin_lock_bh(&adapter->mcc_lock);
3504
3505         wrb = wrb_from_mccq(adapter);
3506         if (!wrb) {
3507                 status = -EBUSY;
3508                 goto err;
3509         }
3510         req = embedded_payload(wrb);
3511         resp = embedded_payload(wrb);
3512
3513         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3514                                hdr->opcode, wrb_payload_size, wrb, NULL);
3515         memcpy(req, wrb_payload, wrb_payload_size);
3516         be_dws_cpu_to_le(req, wrb_payload_size);
3517
3518         status = be_mcc_notify_wait(adapter);
3519         if (cmd_status)
3520                 *cmd_status = (status & 0xffff);
3521         if (ext_status)
3522                 *ext_status = 0;
3523         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3524         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3525 err:
3526         spin_unlock_bh(&adapter->mcc_lock);
3527         return status;
3528 }
3529 EXPORT_SYMBOL(be_roce_mcc_cmd);