Pileus Git - ~andy/linux/blob - drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
  56                            u8 subsystem)
  57 {
  58         int i;
  59         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  60         u32 cmd_privileges = adapter->cmd_privileges;
  61
  62         for (i = 0; i < num_entries; i++)
  63                 if (opcode == cmd_priv_map[i].opcode &&
  64                     subsystem == cmd_priv_map[i].subsystem)
  65                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  66                                 return false;
  67
  68         return true;
  69 }
  70
  71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  72 {
  73         return wrb->payload.embedded_payload;
  74 }
  75
  76 static void be_mcc_notify(struct be_adapter *adapter)
  77 {
  78         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  79         u32 val = 0;
  80
  81         if (be_error(adapter))
  82                 return;
  83
  84         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  85         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  86
  87         wmb();
  88         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  89 }
  90
  91 /* To check if valid bit is set, check the entire word as we don't know
  92  * the endianness of the data (old entry is host endian while a new entry is
  93  * little endian) */
  94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  95 {
  96         if (compl->flags != 0) {
  97                 compl->flags = le32_to_cpu(compl->flags);
  98                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  99                 return true;
 100         } else {
 101                 return false;
 102         }
 103 }
 104
 105 /* Need to reset the entire word that houses the valid bit */
 106 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 107 {
 108         compl->flags = 0;
 109 }
 110
 111 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 112 {
 113         unsigned long addr;
 114
 115         addr = tag1;
 116         addr = ((addr << 16) << 16) | tag0;
 117         return (void *)addr;
 118 }
 119
 120 static int be_mcc_compl_process(struct be_adapter *adapter,
 121                                 struct be_mcc_compl *compl)
 122 {
 123         u16 compl_status, extd_status;
 124         struct be_cmd_resp_hdr *resp_hdr;
 125         u8 opcode = 0, subsystem = 0;
 126
 127         /* Just swap the status to host endian; mcc tag is opaquely copied
 128          * from mcc_wrb */
 129         be_dws_le_to_cpu(compl, 4);
 130
 131         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 132                                 CQE_STATUS_COMPL_MASK;
 133
 134         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 135
 136         if (resp_hdr) {
 137                 opcode = resp_hdr->opcode;
 138                 subsystem = resp_hdr->subsystem;
 139         }
 140
 141         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 142              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 143             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 144                 adapter->flash_status = compl_status;
 145                 complete(&adapter->flash_compl);
 146         }
 147
 148         if (compl_status == MCC_STATUS_SUCCESS) {
 149                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 150                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 151                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 152                         be_parse_stats(adapter);
 153                         adapter->stats_cmd_sent = false;
 154                 }
 155                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 156                     subsystem == CMD_SUBSYSTEM_COMMON) {
 157                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 158                                 (void *)resp_hdr;
 159                         adapter->drv_stats.be_on_die_temperature =
 160                                 resp->on_die_temperature;
 161                 }
 162         } else {
 163                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 164                         adapter->be_get_temp_freq = 0;
 165
 166                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 167                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 168                         goto done;
 169
 170                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 171                         dev_warn(&adapter->pdev->dev,
 172                                  "VF is not privileged to issue opcode %d-%d\n",
 173                                  opcode, subsystem);
 174                 } else {
 175                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 176                                         CQE_STATUS_EXTD_MASK;
 177                         dev_err(&adapter->pdev->dev,
 178                                 "opcode %d-%d failed:status %d-%d\n",
 179                                 opcode, subsystem, compl_status, extd_status);
 180                 }
 181         }
 182 done:
 183         return compl_status;
 184 }
 185
 186 /* Link state evt is a string of bytes; no need for endian swapping */
 187 static void be_async_link_state_process(struct be_adapter *adapter,
 188                 struct be_async_event_link_state *evt)
 189 {
 190         /* When link status changes, link speed must be re-queried from FW */
 191         adapter->phy.link_speed = -1;
 192
 193         /* Ignore physical link event */
 194         if (lancer_chip(adapter) &&
 195             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 196                 return;
 197
 198         /* For the initial link status do not rely on the ASYNC event as
 199          * it may not be received in some cases.
 200          */
 201         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 202                 be_link_status_update(adapter, evt->port_link_status);
 203 }
 204
 205 /* Grp5 CoS Priority evt */
 206 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 207                 struct be_async_event_grp5_cos_priority *evt)
 208 {
 209         if (evt->valid) {
 210                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 211                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 212                 adapter->recommended_prio =
 213                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 214         }
 215 }
 216
 217 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 218 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 219                 struct be_async_event_grp5_qos_link_speed *evt)
 220 {
 221         if (adapter->phy.link_speed >= 0 &&
 222             evt->physical_port == adapter->port_num)
 223                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 224 }
 225
 226 /*Grp5 PVID evt*/
 227 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 228                 struct be_async_event_grp5_pvid_state *evt)
 229 {
 230         if (evt->enabled)
 231                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 232         else
 233                 adapter->pvid = 0;
 234 }
 235
 236 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 237                 u32 trailer, struct be_mcc_compl *evt)
 238 {
 239         u8 event_type = 0;
 240
 241         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 242                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 243
 244         switch (event_type) {
 245         case ASYNC_EVENT_COS_PRIORITY:
 246                 be_async_grp5_cos_priority_process(adapter,
 247                 (struct be_async_event_grp5_cos_priority *)evt);
 248         break;
 249         case ASYNC_EVENT_QOS_SPEED:
 250                 be_async_grp5_qos_speed_process(adapter,
 251                 (struct be_async_event_grp5_qos_link_speed *)evt);
 252         break;
 253         case ASYNC_EVENT_PVID_STATE:
 254                 be_async_grp5_pvid_state_process(adapter,
 255                 (struct be_async_event_grp5_pvid_state *)evt);
 256         break;
 257         default:
 258                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 259                 break;
 260         }
 261 }
 262
 263 static inline bool is_link_state_evt(u32 trailer)
 264 {
 265         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 266                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 267                                 ASYNC_EVENT_CODE_LINK_STATE;
 268 }
 269
 270 static inline bool is_grp5_evt(u32 trailer)
 271 {
 272         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 273                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 274                                 ASYNC_EVENT_CODE_GRP_5);
 275 }
 276
 277 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 278 {
 279         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 280         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 281
 282         if (be_mcc_compl_is_new(compl)) {
 283                 queue_tail_inc(mcc_cq);
 284                 return compl;
 285         }
 286         return NULL;
 287 }
 288
 289 void be_async_mcc_enable(struct be_adapter *adapter)
 290 {
 291         spin_lock_bh(&adapter->mcc_cq_lock);
 292
 293         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 294         adapter->mcc_obj.rearm_cq = true;
 295
 296         spin_unlock_bh(&adapter->mcc_cq_lock);
 297 }
 298
 299 void be_async_mcc_disable(struct be_adapter *adapter)
 300 {
 301         adapter->mcc_obj.rearm_cq = false;
 302 }
 303
 304 int be_process_mcc(struct be_adapter *adapter)
 305 {
 306         struct be_mcc_compl *compl;
 307         int num = 0, status = 0;
 308         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 309
 310         spin_lock(&adapter->mcc_cq_lock);
 311         while ((compl = be_mcc_compl_get(adapter))) {
 312                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 313                         /* Interpret flags as an async trailer */
 314                         if (is_link_state_evt(compl->flags))
 315                                 be_async_link_state_process(adapter,
 316                                 (struct be_async_event_link_state *) compl);
 317                         else if (is_grp5_evt(compl->flags))
 318                                 be_async_grp5_evt_process(adapter,
 319                                 compl->flags, compl);
 320                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 321                                 status = be_mcc_compl_process(adapter, compl);
 322                                 atomic_dec(&mcc_obj->q.used);
 323                 }
 324                 be_mcc_compl_use(compl);
 325                 num++;
 326         }
 327
 328         if (num)
 329                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 330
 331         spin_unlock(&adapter->mcc_cq_lock);
 332         return status;
 333 }
 334
 335 /* Wait till no more pending mcc requests are present */
 336 static int be_mcc_wait_compl(struct be_adapter *adapter)
 337 {
 338 #define mcc_timeout             120000 /* 12s timeout */
 339         int i, status = 0;
 340         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 341
 342         for (i = 0; i < mcc_timeout; i++) {
 343                 if (be_error(adapter))
 344                         return -EIO;
 345
 346                 local_bh_disable();
 347                 status = be_process_mcc(adapter);
 348                 local_bh_enable();
 349
 350                 if (atomic_read(&mcc_obj->q.used) == 0)
 351                         break;
 352                 udelay(100);
 353         }
 354         if (i == mcc_timeout) {
 355                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 356                 adapter->fw_timeout = true;
 357                 return -EIO;
 358         }
 359         return status;
 360 }
 361
 362 /* Notify MCC requests and wait for completion */
 363 static int be_mcc_notify_wait(struct be_adapter *adapter)
 364 {
 365         int status;
 366         struct be_mcc_wrb *wrb;
 367         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 368         u16 index = mcc_obj->q.head;
 369         struct be_cmd_resp_hdr *resp;
 370
 371         index_dec(&index, mcc_obj->q.len);
 372         wrb = queue_index_node(&mcc_obj->q, index);
 373
 374         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 375
 376         be_mcc_notify(adapter);
 377
 378         status = be_mcc_wait_compl(adapter);
 379         if (status == -EIO)
 380                 goto out;
 381
 382         status = resp->status;
 383 out:
 384         return status;
 385 }
 386
 387 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 388 {
 389         int msecs = 0;
 390         u32 ready;
 391
 392         do {
 393                 if (be_error(adapter))
 394                         return -EIO;
 395
 396                 ready = ioread32(db);
 397                 if (ready == 0xffffffff)
 398                         return -1;
 399
 400                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 401                 if (ready)
 402                         break;
 403
 404                 if (msecs > 4000) {
 405                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 406                         adapter->fw_timeout = true;
 407                         be_detect_error(adapter);
 408                         return -1;
 409                 }
 410
 411                 msleep(1);
 412                 msecs++;
 413         } while (true);
 414
 415         return 0;
 416 }
 417
 418 /*
 419  * Insert the mailbox address into the doorbell in two steps
 420  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 421  */
 422 static int be_mbox_notify_wait(struct be_adapter *adapter)
 423 {
 424         int status;
 425         u32 val = 0;
 426         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 427         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 428         struct be_mcc_mailbox *mbox = mbox_mem->va;
 429         struct be_mcc_compl *compl = &mbox->compl;
 430
 431         /* wait for ready to be set */
 432         status = be_mbox_db_ready_wait(adapter, db);
 433         if (status != 0)
 434                 return status;
 435
 436         val |= MPU_MAILBOX_DB_HI_MASK;
 437         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 438         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 439         iowrite32(val, db);
 440
 441         /* wait for ready to be set */
 442         status = be_mbox_db_ready_wait(adapter, db);
 443         if (status != 0)
 444                 return status;
 445
 446         val = 0;
 447         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 448         val |= (u32)(mbox_mem->dma >> 4) << 2;
 449         iowrite32(val, db);
 450
 451         status = be_mbox_db_ready_wait(adapter, db);
 452         if (status != 0)
 453                 return status;
 454
 455         /* A cq entry has been made now */
 456         if (be_mcc_compl_is_new(compl)) {
 457                 status = be_mcc_compl_process(adapter, &mbox->compl);
 458                 be_mcc_compl_use(compl);
 459                 if (status)
 460                         return status;
 461         } else {
 462                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 463                 return -1;
 464         }
 465         return 0;
 466 }
 467
 468 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 469 {
 470         u32 sem;
 471
 472         if (lancer_chip(adapter))
 473                 sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
 474         else
 475                 sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 476
 477         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 478         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 479                 return -1;
 480         else
 481                 return 0;
 482 }
 483
 484 int lancer_wait_ready(struct be_adapter *adapter)
 485 {
 486 #define SLIPORT_READY_TIMEOUT 30
 487         u32 sliport_status;
 488         int status = 0, i;
 489
 490         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 491                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 492                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 493                         break;
 494
 495                 msleep(1000);
 496         }
 497
 498         if (i == SLIPORT_READY_TIMEOUT)
 499                 status = -1;
 500
 501         return status;
 502 }
 503
 504 static bool lancer_provisioning_error(struct be_adapter *adapter)
 505 {
 506         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 507         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 508         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 509                 sliport_err1 = ioread32(adapter->db +
 510                                         SLIPORT_ERROR1_OFFSET);
 511                 sliport_err2 = ioread32(adapter->db +
 512                                         SLIPORT_ERROR2_OFFSET);
 513
 514                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 515                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 516                         return true;
 517         }
 518         return false;
 519 }
 520
 521 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 522 {
 523         int status;
 524         u32 sliport_status, err, reset_needed;
 525         bool resource_error;
 526
 527         resource_error = lancer_provisioning_error(adapter);
 528         if (resource_error)
 529                 return -1;
 530
 531         status = lancer_wait_ready(adapter);
 532         if (!status) {
 533                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 534                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 535                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 536                 if (err && reset_needed) {
 537                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 538                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 539
 540                         /* check adapter has corrected the error */
 541                         status = lancer_wait_ready(adapter);
 542                         sliport_status = ioread32(adapter->db +
 543                                                   SLIPORT_STATUS_OFFSET);
 544                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 545                                                 SLIPORT_STATUS_RN_MASK);
 546                         if (status || sliport_status)
 547                                 status = -1;
 548                 } else if (err || reset_needed) {
 549                         status = -1;
 550                 }
 551         }
 552         /* Stop error recovery if error is not recoverable.
 553          * No resource error is temporary errors and will go away
 554          * when PF provisions resources.
 555          */
 556         resource_error = lancer_provisioning_error(adapter);
 557         if (status == -1 && !resource_error)
 558                 adapter->eeh_error = true;
 559
 560         return status;
 561 }
 562
 563 int be_fw_wait_ready(struct be_adapter *adapter)
 564 {
 565         u16 stage;
 566         int status, timeout = 0;
 567         struct device *dev = &adapter->pdev->dev;
 568
 569         if (lancer_chip(adapter)) {
 570                 status = lancer_wait_ready(adapter);
 571                 return status;
 572         }
 573
 574         do {
 575                 status = be_POST_stage_get(adapter, &stage);
 576                 if (status) {
 577                         dev_err(dev, "POST error; stage=0x%x\n", stage);
 578                         return -1;
 579                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 580                         if (msleep_interruptible(2000)) {
 581                                 dev_err(dev, "Waiting for POST aborted\n");
 582                                 return -EINTR;
 583                         }
 584                         timeout += 2;
 585                 } else {
 586                         return 0;
 587                 }
 588         } while (timeout < 60);
 589
 590         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 591         return -1;
 592 }
 593
 594
 595 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 596 {
 597         return &wrb->payload.sgl[0];
 598 }
 599
 600
 601 /* Don't touch the hdr after it's prepared */
 602 /* mem will be NULL for embedded commands */
 603 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 604                                 u8 subsystem, u8 opcode, int cmd_len,
 605                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 606 {
 607         struct be_sge *sge;
 608         unsigned long addr = (unsigned long)req_hdr;
 609         u64 req_addr = addr;
 610
 611         req_hdr->opcode = opcode;
 612         req_hdr->subsystem = subsystem;
 613         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 614         req_hdr->version = 0;
 615
 616         wrb->tag0 = req_addr & 0xFFFFFFFF;
 617         wrb->tag1 = upper_32_bits(req_addr);
 618
 619         wrb->payload_length = cmd_len;
 620         if (mem) {
 621                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 622                         MCC_WRB_SGE_CNT_SHIFT;
 623                 sge = nonembedded_sgl(wrb);
 624                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 625                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 626                 sge->len = cpu_to_le32(mem->size);
 627         } else
 628                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 629         be_dws_cpu_to_le(wrb, 8);
 630 }
 631
 632 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 633                         struct be_dma_mem *mem)
 634 {
 635         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 636         u64 dma = (u64)mem->dma;
 637
 638         for (i = 0; i < buf_pages; i++) {
 639                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 640                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 641                 dma += PAGE_SIZE_4K;
 642         }
 643 }
 644
 645 /* Converts interrupt delay in microseconds to multiplier value */
 646 static u32 eq_delay_to_mult(u32 usec_delay)
 647 {
 648 #define MAX_INTR_RATE                   651042
 649         const u32 round = 10;
 650         u32 multiplier;
 651
 652         if (usec_delay == 0)
 653                 multiplier = 0;
 654         else {
 655                 u32 interrupt_rate = 1000000 / usec_delay;
 656                 /* Max delay, corresponding to the lowest interrupt rate */
 657                 if (interrupt_rate == 0)
 658                         multiplier = 1023;
 659                 else {
 660                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 661                         multiplier /= interrupt_rate;
 662                         /* Round the multiplier to the closest value.*/
 663                         multiplier = (multiplier + round/2) / round;
 664                         multiplier = min(multiplier, (u32)1023);
 665                 }
 666         }
 667         return multiplier;
 668 }
 669
 670 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 671 {
 672         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 673         struct be_mcc_wrb *wrb
 674                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 675         memset(wrb, 0, sizeof(*wrb));
 676         return wrb;
 677 }
 678
 679 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 680 {
 681         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 682         struct be_mcc_wrb *wrb;
 683
 684         if (!mccq->created)
 685                 return NULL;
 686
 687         if (atomic_read(&mccq->used) >= mccq->len) {
 688                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 689                 return NULL;
 690         }
 691
 692         wrb = queue_head_node(mccq);
 693         queue_head_inc(mccq);
 694         atomic_inc(&mccq->used);
 695         memset(wrb, 0, sizeof(*wrb));
 696         return wrb;
 697 }
 698
 699 /* Tell fw we're about to start firing cmds by writing a
 700  * special pattern across the wrb hdr; uses mbox
 701  */
 702 int be_cmd_fw_init(struct be_adapter *adapter)
 703 {
 704         u8 *wrb;
 705         int status;
 706
 707         if (lancer_chip(adapter))
 708                 return 0;
 709
 710         if (mutex_lock_interruptible(&adapter->mbox_lock))
 711                 return -1;
 712
 713         wrb = (u8 *)wrb_from_mbox(adapter);
 714         *wrb++ = 0xFF;
 715         *wrb++ = 0x12;
 716         *wrb++ = 0x34;
 717         *wrb++ = 0xFF;
 718         *wrb++ = 0xFF;
 719         *wrb++ = 0x56;
 720         *wrb++ = 0x78;
 721         *wrb = 0xFF;
 722
 723         status = be_mbox_notify_wait(adapter);
 724
 725         mutex_unlock(&adapter->mbox_lock);
 726         return status;
 727 }
 728
 729 /* Tell fw we're done with firing cmds by writing a
 730  * special pattern across the wrb hdr; uses mbox
 731  */
 732 int be_cmd_fw_clean(struct be_adapter *adapter)
 733 {
 734         u8 *wrb;
 735         int status;
 736
 737         if (lancer_chip(adapter))
 738                 return 0;
 739
 740         if (mutex_lock_interruptible(&adapter->mbox_lock))
 741                 return -1;
 742
 743         wrb = (u8 *)wrb_from_mbox(adapter);
 744         *wrb++ = 0xFF;
 745         *wrb++ = 0xAA;
 746         *wrb++ = 0xBB;
 747         *wrb++ = 0xFF;
 748         *wrb++ = 0xFF;
 749         *wrb++ = 0xCC;
 750         *wrb++ = 0xDD;
 751         *wrb = 0xFF;
 752
 753         status = be_mbox_notify_wait(adapter);
 754
 755         mutex_unlock(&adapter->mbox_lock);
 756         return status;
 757 }
 758
 759 int be_cmd_eq_create(struct be_adapter *adapter,
 760                 struct be_queue_info *eq, int eq_delay)
 761 {
 762         struct be_mcc_wrb *wrb;
 763         struct be_cmd_req_eq_create *req;
 764         struct be_dma_mem *q_mem = &eq->dma_mem;
 765         int status;
 766
 767         if (mutex_lock_interruptible(&adapter->mbox_lock))
 768                 return -1;
 769
 770         wrb = wrb_from_mbox(adapter);
 771         req = embedded_payload(wrb);
 772
 773         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 774                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 775
 776         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 777
 778         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 779         /* 4byte eqe*/
 780         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 781         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 782                         __ilog2_u32(eq->len/256));
 783         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 784                         eq_delay_to_mult(eq_delay));
 785         be_dws_cpu_to_le(req->context, sizeof(req->context));
 786
 787         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 788
 789         status = be_mbox_notify_wait(adapter);
 790         if (!status) {
 791                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 792                 eq->id = le16_to_cpu(resp->eq_id);
 793                 eq->created = true;
 794         }
 795
 796         mutex_unlock(&adapter->mbox_lock);
 797         return status;
 798 }
 799
 800 /* Use MCC */
 801 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 802                           bool permanent, u32 if_handle, u32 pmac_id)
 803 {
 804         struct be_mcc_wrb *wrb;
 805         struct be_cmd_req_mac_query *req;
 806         int status;
 807
 808         spin_lock_bh(&adapter->mcc_lock);
 809
 810         wrb = wrb_from_mccq(adapter);
 811         if (!wrb) {
 812                 status = -EBUSY;
 813                 goto err;
 814         }
 815         req = embedded_payload(wrb);
 816
 817         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 818                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 819         req->type = MAC_ADDRESS_TYPE_NETWORK;
 820         if (permanent) {
 821                 req->permanent = 1;
 822         } else {
 823                 req->if_id = cpu_to_le16((u16) if_handle);
 824                 req->pmac_id = cpu_to_le32(pmac_id);
 825                 req->permanent = 0;
 826         }
 827
 828         status = be_mcc_notify_wait(adapter);
 829         if (!status) {
 830                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 831                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 832         }
 833
 834 err:
 835         spin_unlock_bh(&adapter->mcc_lock);
 836         return status;
 837 }
 838
 839 /* Uses synchronous MCCQ */
 840 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 841                 u32 if_id, u32 *pmac_id, u32 domain)
 842 {
 843         struct be_mcc_wrb *wrb;
 844         struct be_cmd_req_pmac_add *req;
 845         int status;
 846
 847         spin_lock_bh(&adapter->mcc_lock);
 848
 849         wrb = wrb_from_mccq(adapter);
 850         if (!wrb) {
 851                 status = -EBUSY;
 852                 goto err;
 853         }
 854         req = embedded_payload(wrb);
 855
 856         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 857                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 858
 859         req->hdr.domain = domain;
 860         req->if_id = cpu_to_le32(if_id);
 861         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 862
 863         status = be_mcc_notify_wait(adapter);
 864         if (!status) {
 865                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 866                 *pmac_id = le32_to_cpu(resp->pmac_id);
 867         }
 868
 869 err:
 870         spin_unlock_bh(&adapter->mcc_lock);
 871
 872          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 873                 status = -EPERM;
 874
 875         return status;
 876 }
 877
 878 /* Uses synchronous MCCQ */
 879 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 880 {
 881         struct be_mcc_wrb *wrb;
 882         struct be_cmd_req_pmac_del *req;
 883         int status;
 884
 885         if (pmac_id == -1)
 886                 return 0;
 887
 888         spin_lock_bh(&adapter->mcc_lock);
 889
 890         wrb = wrb_from_mccq(adapter);
 891         if (!wrb) {
 892                 status = -EBUSY;
 893                 goto err;
 894         }
 895         req = embedded_payload(wrb);
 896
 897         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 898                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 899
 900         req->hdr.domain = dom;
 901         req->if_id = cpu_to_le32(if_id);
 902         req->pmac_id = cpu_to_le32(pmac_id);
 903
 904         status = be_mcc_notify_wait(adapter);
 905
 906 err:
 907         spin_unlock_bh(&adapter->mcc_lock);
 908         return status;
 909 }
 910
 911 /* Uses Mbox */
 912 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
 913                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
 914 {
 915         struct be_mcc_wrb *wrb;
 916         struct be_cmd_req_cq_create *req;
 917         struct be_dma_mem *q_mem = &cq->dma_mem;
 918         void *ctxt;
 919         int status;
 920
 921         if (mutex_lock_interruptible(&adapter->mbox_lock))
 922                 return -1;
 923
 924         wrb = wrb_from_mbox(adapter);
 925         req = embedded_payload(wrb);
 926         ctxt = &req->context;
 927
 928         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 929                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 930
 931         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 932         if (lancer_chip(adapter)) {
 933                 req->hdr.version = 2;
 934                 req->page_size = 1; /* 1 for 4K */
 935                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 936                                                                 no_delay);
 937                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 938                                                 __ilog2_u32(cq->len/256));
 939                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 940                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 941                                                                 ctxt, 1);
 942                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 943                                                                 ctxt, eq->id);
 944         } else {
 945                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 946                                                                 coalesce_wm);
 947                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 948                                                                 ctxt, no_delay);
 949                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 950                                                 __ilog2_u32(cq->len/256));
 951                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 952                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 953                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 954         }
 955
 956         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 957
 958         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 959
 960         status = be_mbox_notify_wait(adapter);
 961         if (!status) {
 962                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 963                 cq->id = le16_to_cpu(resp->cq_id);
 964                 cq->created = true;
 965         }
 966
 967         mutex_unlock(&adapter->mbox_lock);
 968
 969         return status;
 970 }
 971
 972 static u32 be_encoded_q_len(int q_len)
 973 {
 974         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 975         if (len_encoded == 16)
 976                 len_encoded = 0;
 977         return len_encoded;
 978 }
 979
 980 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
 981                         struct be_queue_info *mccq,
 982                         struct be_queue_info *cq)
 983 {
 984         struct be_mcc_wrb *wrb;
 985         struct be_cmd_req_mcc_ext_create *req;
 986         struct be_dma_mem *q_mem = &mccq->dma_mem;
 987         void *ctxt;
 988         int status;
 989
 990         if (mutex_lock_interruptible(&adapter->mbox_lock))
 991                 return -1;
 992
 993         wrb = wrb_from_mbox(adapter);
 994         req = embedded_payload(wrb);
 995         ctxt = &req->context;
 996
 997         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 998                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
 999
1000         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1001         if (lancer_chip(adapter)) {
1002                 req->hdr.version = 1;
1003                 req->cq_id = cpu_to_le16(cq->id);
1004
1005                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1006                                                 be_encoded_q_len(mccq->len));
1007                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1008                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1009                                                                 ctxt, cq->id);
1010                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1011                                                                  ctxt, 1);
1012
1013         } else {
1014                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1015                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1016                                                 be_encoded_q_len(mccq->len));
1017                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1018         }
1019
1020         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1021         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1022         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1023
1024         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1025
1026         status = be_mbox_notify_wait(adapter);
1027         if (!status) {
1028                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1029                 mccq->id = le16_to_cpu(resp->id);
1030                 mccq->created = true;
1031         }
1032         mutex_unlock(&adapter->mbox_lock);
1033
1034         return status;
1035 }
1036
1037 int be_cmd_mccq_org_create(struct be_adapter *adapter,
1038                         struct be_queue_info *mccq,
1039                         struct be_queue_info *cq)
1040 {
1041         struct be_mcc_wrb *wrb;
1042         struct be_cmd_req_mcc_create *req;
1043         struct be_dma_mem *q_mem = &mccq->dma_mem;
1044         void *ctxt;
1045         int status;
1046
1047         if (mutex_lock_interruptible(&adapter->mbox_lock))
1048                 return -1;
1049
1050         wrb = wrb_from_mbox(adapter);
1051         req = embedded_payload(wrb);
1052         ctxt = &req->context;
1053
1054         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1055                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1056
1057         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1058
1059         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1060         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1061                         be_encoded_q_len(mccq->len));
1062         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1063
1064         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1065
1066         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1067
1068         status = be_mbox_notify_wait(adapter);
1069         if (!status) {
1070                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1071                 mccq->id = le16_to_cpu(resp->id);
1072                 mccq->created = true;
1073         }
1074
1075         mutex_unlock(&adapter->mbox_lock);
1076         return status;
1077 }
1078
1079 int be_cmd_mccq_create(struct be_adapter *adapter,
1080                         struct be_queue_info *mccq,
1081                         struct be_queue_info *cq)
1082 {
1083         int status;
1084
1085         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1086         if (status && !lancer_chip(adapter)) {
1087                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1088                         "or newer to avoid conflicting priorities between NIC "
1089                         "and FCoE traffic");
1090                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1091         }
1092         return status;
1093 }
1094
1095 int be_cmd_txq_create(struct be_adapter *adapter,
1096                         struct be_queue_info *txq,
1097                         struct be_queue_info *cq)
1098 {
1099         struct be_mcc_wrb *wrb;
1100         struct be_cmd_req_eth_tx_create *req;
1101         struct be_dma_mem *q_mem = &txq->dma_mem;
1102         void *ctxt;
1103         int status;
1104
1105         spin_lock_bh(&adapter->mcc_lock);
1106
1107         wrb = wrb_from_mccq(adapter);
1108         if (!wrb) {
1109                 status = -EBUSY;
1110                 goto err;
1111         }
1112
1113         req = embedded_payload(wrb);
1114         ctxt = &req->context;
1115
1116         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1117                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1118
1119         if (lancer_chip(adapter)) {
1120                 req->hdr.version = 1;
1121                 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
1122                                         adapter->if_handle);
1123         }
1124
1125         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1126         req->ulp_num = BE_ULP1_NUM;
1127         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1128
1129         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
1130                 be_encoded_q_len(txq->len));
1131         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
1132         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
1133
1134         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1135
1136         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1137
1138         status = be_mcc_notify_wait(adapter);
1139         if (!status) {
1140                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1141                 txq->id = le16_to_cpu(resp->cid);
1142                 txq->created = true;
1143         }
1144
1145 err:
1146         spin_unlock_bh(&adapter->mcc_lock);
1147
1148         return status;
1149 }
1150
1151 /* Uses MCC */
1152 int be_cmd_rxq_create(struct be_adapter *adapter,
1153                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1154                 u32 if_id, u32 rss, u8 *rss_id)
1155 {
1156         struct be_mcc_wrb *wrb;
1157         struct be_cmd_req_eth_rx_create *req;
1158         struct be_dma_mem *q_mem = &rxq->dma_mem;
1159         int status;
1160
1161         spin_lock_bh(&adapter->mcc_lock);
1162
1163         wrb = wrb_from_mccq(adapter);
1164         if (!wrb) {
1165                 status = -EBUSY;
1166                 goto err;
1167         }
1168         req = embedded_payload(wrb);
1169
1170         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1171                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1172
1173         req->cq_id = cpu_to_le16(cq_id);
1174         req->frag_size = fls(frag_size) - 1;
1175         req->num_pages = 2;
1176         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1177         req->interface_id = cpu_to_le32(if_id);
1178         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1179         req->rss_queue = cpu_to_le32(rss);
1180
1181         status = be_mcc_notify_wait(adapter);
1182         if (!status) {
1183                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1184                 rxq->id = le16_to_cpu(resp->id);
1185                 rxq->created = true;
1186                 *rss_id = resp->rss_id;
1187         }
1188
1189 err:
1190         spin_unlock_bh(&adapter->mcc_lock);
1191         return status;
1192 }
1193
1194 /* Generic destroyer function for all types of queues
1195  * Uses Mbox
1196  */
1197 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1198                 int queue_type)
1199 {
1200         struct be_mcc_wrb *wrb;
1201         struct be_cmd_req_q_destroy *req;
1202         u8 subsys = 0, opcode = 0;
1203         int status;
1204
1205         if (mutex_lock_interruptible(&adapter->mbox_lock))
1206                 return -1;
1207
1208         wrb = wrb_from_mbox(adapter);
1209         req = embedded_payload(wrb);
1210
1211         switch (queue_type) {
1212         case QTYPE_EQ:
1213                 subsys = CMD_SUBSYSTEM_COMMON;
1214                 opcode = OPCODE_COMMON_EQ_DESTROY;
1215                 break;
1216         case QTYPE_CQ:
1217                 subsys = CMD_SUBSYSTEM_COMMON;
1218                 opcode = OPCODE_COMMON_CQ_DESTROY;
1219                 break;
1220         case QTYPE_TXQ:
1221                 subsys = CMD_SUBSYSTEM_ETH;
1222                 opcode = OPCODE_ETH_TX_DESTROY;
1223                 break;
1224         case QTYPE_RXQ:
1225                 subsys = CMD_SUBSYSTEM_ETH;
1226                 opcode = OPCODE_ETH_RX_DESTROY;
1227                 break;
1228         case QTYPE_MCCQ:
1229                 subsys = CMD_SUBSYSTEM_COMMON;
1230                 opcode = OPCODE_COMMON_MCC_DESTROY;
1231                 break;
1232         default:
1233                 BUG();
1234         }
1235
1236         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1237                                 NULL);
1238         req->id = cpu_to_le16(q->id);
1239
1240         status = be_mbox_notify_wait(adapter);
1241         q->created = false;
1242
1243         mutex_unlock(&adapter->mbox_lock);
1244         return status;
1245 }
1246
1247 /* Uses MCC */
1248 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1249 {
1250         struct be_mcc_wrb *wrb;
1251         struct be_cmd_req_q_destroy *req;
1252         int status;
1253
1254         spin_lock_bh(&adapter->mcc_lock);
1255
1256         wrb = wrb_from_mccq(adapter);
1257         if (!wrb) {
1258                 status = -EBUSY;
1259                 goto err;
1260         }
1261         req = embedded_payload(wrb);
1262
1263         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1264                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1265         req->id = cpu_to_le16(q->id);
1266
1267         status = be_mcc_notify_wait(adapter);
1268         q->created = false;
1269
1270 err:
1271         spin_unlock_bh(&adapter->mcc_lock);
1272         return status;
1273 }
1274
1275 /* Create an rx filtering policy configuration on an i/f
1276  * Uses MCCQ
1277  */
1278 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1279                      u32 *if_handle, u32 domain)
1280 {
1281         struct be_mcc_wrb *wrb;
1282         struct be_cmd_req_if_create *req;
1283         int status;
1284
1285         spin_lock_bh(&adapter->mcc_lock);
1286
1287         wrb = wrb_from_mccq(adapter);
1288         if (!wrb) {
1289                 status = -EBUSY;
1290                 goto err;
1291         }
1292         req = embedded_payload(wrb);
1293
1294         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1295                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1296         req->hdr.domain = domain;
1297         req->capability_flags = cpu_to_le32(cap_flags);
1298         req->enable_flags = cpu_to_le32(en_flags);
1299
1300         req->pmac_invalid = true;
1301
1302         status = be_mcc_notify_wait(adapter);
1303         if (!status) {
1304                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1305                 *if_handle = le32_to_cpu(resp->interface_id);
1306         }
1307
1308 err:
1309         spin_unlock_bh(&adapter->mcc_lock);
1310         return status;
1311 }
1312
1313 /* Uses MCCQ */
1314 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1315 {
1316         struct be_mcc_wrb *wrb;
1317         struct be_cmd_req_if_destroy *req;
1318         int status;
1319
1320         if (interface_id == -1)
1321                 return 0;
1322
1323         spin_lock_bh(&adapter->mcc_lock);
1324
1325         wrb = wrb_from_mccq(adapter);
1326         if (!wrb) {
1327                 status = -EBUSY;
1328                 goto err;
1329         }
1330         req = embedded_payload(wrb);
1331
1332         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1333                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1334         req->hdr.domain = domain;
1335         req->interface_id = cpu_to_le32(interface_id);
1336
1337         status = be_mcc_notify_wait(adapter);
1338 err:
1339         spin_unlock_bh(&adapter->mcc_lock);
1340         return status;
1341 }
1342
1343 /* Get stats is a non embedded command: the request is not embedded inside
1344  * WRB but is a separate dma memory block
1345  * Uses asynchronous MCC
1346  */
1347 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1348 {
1349         struct be_mcc_wrb *wrb;
1350         struct be_cmd_req_hdr *hdr;
1351         int status = 0;
1352
1353         spin_lock_bh(&adapter->mcc_lock);
1354
1355         wrb = wrb_from_mccq(adapter);
1356         if (!wrb) {
1357                 status = -EBUSY;
1358                 goto err;
1359         }
1360         hdr = nonemb_cmd->va;
1361
1362         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1363                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1364
1365         if (adapter->generation == BE_GEN3)
1366                 hdr->version = 1;
1367
1368         be_mcc_notify(adapter);
1369         adapter->stats_cmd_sent = true;
1370
1371 err:
1372         spin_unlock_bh(&adapter->mcc_lock);
1373         return status;
1374 }
1375
1376 /* Lancer Stats */
1377 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1378                                 struct be_dma_mem *nonemb_cmd)
1379 {
1380
1381         struct be_mcc_wrb *wrb;
1382         struct lancer_cmd_req_pport_stats *req;
1383         int status = 0;
1384
1385         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1386                             CMD_SUBSYSTEM_ETH))
1387                 return -EPERM;
1388
1389         spin_lock_bh(&adapter->mcc_lock);
1390
1391         wrb = wrb_from_mccq(adapter);
1392         if (!wrb) {
1393                 status = -EBUSY;
1394                 goto err;
1395         }
1396         req = nonemb_cmd->va;
1397
1398         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1399                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1400                         nonemb_cmd);
1401
1402         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1403         req->cmd_params.params.reset_stats = 0;
1404
1405         be_mcc_notify(adapter);
1406         adapter->stats_cmd_sent = true;
1407
1408 err:
1409         spin_unlock_bh(&adapter->mcc_lock);
1410         return status;
1411 }
1412
1413 static int be_mac_to_link_speed(int mac_speed)
1414 {
1415         switch (mac_speed) {
1416         case PHY_LINK_SPEED_ZERO:
1417                 return 0;
1418         case PHY_LINK_SPEED_10MBPS:
1419                 return 10;
1420         case PHY_LINK_SPEED_100MBPS:
1421                 return 100;
1422         case PHY_LINK_SPEED_1GBPS:
1423                 return 1000;
1424         case PHY_LINK_SPEED_10GBPS:
1425                 return 10000;
1426         }
1427         return 0;
1428 }
1429
1430 /* Uses synchronous mcc
1431  * Returns link_speed in Mbps
1432  */
1433 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1434                              u8 *link_status, u32 dom)
1435 {
1436         struct be_mcc_wrb *wrb;
1437         struct be_cmd_req_link_status *req;
1438         int status;
1439
1440         spin_lock_bh(&adapter->mcc_lock);
1441
1442         if (link_status)
1443                 *link_status = LINK_DOWN;
1444
1445         wrb = wrb_from_mccq(adapter);
1446         if (!wrb) {
1447                 status = -EBUSY;
1448                 goto err;
1449         }
1450         req = embedded_payload(wrb);
1451
1452         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1453                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1454
1455         if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
1456                 req->hdr.version = 1;
1457
1458         req->hdr.domain = dom;
1459
1460         status = be_mcc_notify_wait(adapter);
1461         if (!status) {
1462                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1463                 if (link_speed) {
1464                         *link_speed = resp->link_speed ?
1465                                       le16_to_cpu(resp->link_speed) * 10 :
1466                                       be_mac_to_link_speed(resp->mac_speed);
1467
1468                         if (!resp->logical_link_status)
1469                                 *link_speed = 0;
1470                 }
1471                 if (link_status)
1472                         *link_status = resp->logical_link_status;
1473         }
1474
1475 err:
1476         spin_unlock_bh(&adapter->mcc_lock);
1477         return status;
1478 }
1479
1480 /* Uses synchronous mcc */
1481 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1482 {
1483         struct be_mcc_wrb *wrb;
1484         struct be_cmd_req_get_cntl_addnl_attribs *req;
1485         int status;
1486
1487         spin_lock_bh(&adapter->mcc_lock);
1488
1489         wrb = wrb_from_mccq(adapter);
1490         if (!wrb) {
1491                 status = -EBUSY;
1492                 goto err;
1493         }
1494         req = embedded_payload(wrb);
1495
1496         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1497                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1498                 wrb, NULL);
1499
1500         be_mcc_notify(adapter);
1501
1502 err:
1503         spin_unlock_bh(&adapter->mcc_lock);
1504         return status;
1505 }
1506
1507 /* Uses synchronous mcc */
1508 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1509 {
1510         struct be_mcc_wrb *wrb;
1511         struct be_cmd_req_get_fat *req;
1512         int status;
1513
1514         spin_lock_bh(&adapter->mcc_lock);
1515
1516         wrb = wrb_from_mccq(adapter);
1517         if (!wrb) {
1518                 status = -EBUSY;
1519                 goto err;
1520         }
1521         req = embedded_payload(wrb);
1522
1523         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1524                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1525         req->fat_operation = cpu_to_le32(QUERY_FAT);
1526         status = be_mcc_notify_wait(adapter);
1527         if (!status) {
1528                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1529                 if (log_size && resp->log_size)
1530                         *log_size = le32_to_cpu(resp->log_size) -
1531                                         sizeof(u32);
1532         }
1533 err:
1534         spin_unlock_bh(&adapter->mcc_lock);
1535         return status;
1536 }
1537
1538 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1539 {
1540         struct be_dma_mem get_fat_cmd;
1541         struct be_mcc_wrb *wrb;
1542         struct be_cmd_req_get_fat *req;
1543         u32 offset = 0, total_size, buf_size,
1544                                 log_offset = sizeof(u32), payload_len;
1545         int status;
1546
1547         if (buf_len == 0)
1548                 return;
1549
1550         total_size = buf_len;
1551
1552         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1553         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1554                         get_fat_cmd.size,
1555                         &get_fat_cmd.dma);
1556         if (!get_fat_cmd.va) {
1557                 status = -ENOMEM;
1558                 dev_err(&adapter->pdev->dev,
1559                 "Memory allocation failure while retrieving FAT data\n");
1560                 return;
1561         }
1562
1563         spin_lock_bh(&adapter->mcc_lock);
1564
1565         while (total_size) {
1566                 buf_size = min(total_size, (u32)60*1024);
1567                 total_size -= buf_size;
1568
1569                 wrb = wrb_from_mccq(adapter);
1570                 if (!wrb) {
1571                         status = -EBUSY;
1572                         goto err;
1573                 }
1574                 req = get_fat_cmd.va;
1575
1576                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1577                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1578                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1579                                 &get_fat_cmd);
1580
1581                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1582                 req->read_log_offset = cpu_to_le32(log_offset);
1583                 req->read_log_length = cpu_to_le32(buf_size);
1584                 req->data_buffer_size = cpu_to_le32(buf_size);
1585
1586                 status = be_mcc_notify_wait(adapter);
1587                 if (!status) {
1588                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1589                         memcpy(buf + offset,
1590                                 resp->data_buffer,
1591                                 le32_to_cpu(resp->read_log_length));
1592                 } else {
1593                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1594                         goto err;
1595                 }
1596                 offset += buf_size;
1597                 log_offset += buf_size;
1598         }
1599 err:
1600         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1601                         get_fat_cmd.va,
1602                         get_fat_cmd.dma);
1603         spin_unlock_bh(&adapter->mcc_lock);
1604 }
1605
1606 /* Uses synchronous mcc */
1607 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1608                         char *fw_on_flash)
1609 {
1610         struct be_mcc_wrb *wrb;
1611         struct be_cmd_req_get_fw_version *req;
1612         int status;
1613
1614         spin_lock_bh(&adapter->mcc_lock);
1615
1616         wrb = wrb_from_mccq(adapter);
1617         if (!wrb) {
1618                 status = -EBUSY;
1619                 goto err;
1620         }
1621
1622         req = embedded_payload(wrb);
1623
1624         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1625                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1626         status = be_mcc_notify_wait(adapter);
1627         if (!status) {
1628                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1629                 strcpy(fw_ver, resp->firmware_version_string);
1630                 if (fw_on_flash)
1631                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1632         }
1633 err:
1634         spin_unlock_bh(&adapter->mcc_lock);
1635         return status;
1636 }
1637
1638 /* set the EQ delay interval of an EQ to specified value
1639  * Uses async mcc
1640  */
1641 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1642 {
1643         struct be_mcc_wrb *wrb;
1644         struct be_cmd_req_modify_eq_delay *req;
1645         int status = 0;
1646
1647         spin_lock_bh(&adapter->mcc_lock);
1648
1649         wrb = wrb_from_mccq(adapter);
1650         if (!wrb) {
1651                 status = -EBUSY;
1652                 goto err;
1653         }
1654         req = embedded_payload(wrb);
1655
1656         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1657                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1658
1659         req->num_eq = cpu_to_le32(1);
1660         req->delay[0].eq_id = cpu_to_le32(eq_id);
1661         req->delay[0].phase = 0;
1662         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1663
1664         be_mcc_notify(adapter);
1665
1666 err:
1667         spin_unlock_bh(&adapter->mcc_lock);
1668         return status;
1669 }
1670
1671 /* Uses sycnhronous mcc */
1672 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1673                         u32 num, bool untagged, bool promiscuous)
1674 {
1675         struct be_mcc_wrb *wrb;
1676         struct be_cmd_req_vlan_config *req;
1677         int status;
1678
1679         spin_lock_bh(&adapter->mcc_lock);
1680
1681         wrb = wrb_from_mccq(adapter);
1682         if (!wrb) {
1683                 status = -EBUSY;
1684                 goto err;
1685         }
1686         req = embedded_payload(wrb);
1687
1688         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1689                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1690
1691         req->interface_id = if_id;
1692         req->promiscuous = promiscuous;
1693         req->untagged = untagged;
1694         req->num_vlan = num;
1695         if (!promiscuous) {
1696                 memcpy(req->normal_vlan, vtag_array,
1697                         req->num_vlan * sizeof(vtag_array[0]));
1698         }
1699
1700         status = be_mcc_notify_wait(adapter);
1701
1702 err:
1703         spin_unlock_bh(&adapter->mcc_lock);
1704         return status;
1705 }
1706
1707 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1708 {
1709         struct be_mcc_wrb *wrb;
1710         struct be_dma_mem *mem = &adapter->rx_filter;
1711         struct be_cmd_req_rx_filter *req = mem->va;
1712         int status;
1713
1714         spin_lock_bh(&adapter->mcc_lock);
1715
1716         wrb = wrb_from_mccq(adapter);
1717         if (!wrb) {
1718                 status = -EBUSY;
1719                 goto err;
1720         }
1721         memset(req, 0, sizeof(*req));
1722         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1723                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1724                                 wrb, mem);
1725
1726         req->if_id = cpu_to_le32(adapter->if_handle);
1727         if (flags & IFF_PROMISC) {
1728                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1729                                         BE_IF_FLAGS_VLAN_PROMISCUOUS);
1730                 if (value == ON)
1731                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1732                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1733         } else if (flags & IFF_ALLMULTI) {
1734                 req->if_flags_mask = req->if_flags =
1735                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1736         } else {
1737                 struct netdev_hw_addr *ha;
1738                 int i = 0;
1739
1740                 req->if_flags_mask = req->if_flags =
1741                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1742
1743                 /* Reset mcast promisc mode if already set by setting mask
1744                  * and not setting flags field
1745                  */
1746                 req->if_flags_mask |=
1747                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1748                                     adapter->if_cap_flags);
1749
1750                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1751                 netdev_for_each_mc_addr(ha, adapter->netdev)
1752                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1753         }
1754
1755         status = be_mcc_notify_wait(adapter);
1756 err:
1757         spin_unlock_bh(&adapter->mcc_lock);
1758         return status;
1759 }
1760
1761 /* Uses synchrounous mcc */
1762 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1763 {
1764         struct be_mcc_wrb *wrb;
1765         struct be_cmd_req_set_flow_control *req;
1766         int status;
1767
1768         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1769                             CMD_SUBSYSTEM_COMMON))
1770                 return -EPERM;
1771
1772         spin_lock_bh(&adapter->mcc_lock);
1773
1774         wrb = wrb_from_mccq(adapter);
1775         if (!wrb) {
1776                 status = -EBUSY;
1777                 goto err;
1778         }
1779         req = embedded_payload(wrb);
1780
1781         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1782                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1783
1784         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1785         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1786
1787         status = be_mcc_notify_wait(adapter);
1788
1789 err:
1790         spin_unlock_bh(&adapter->mcc_lock);
1791         return status;
1792 }
1793
1794 /* Uses sycn mcc */
1795 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1796 {
1797         struct be_mcc_wrb *wrb;
1798         struct be_cmd_req_get_flow_control *req;
1799         int status;
1800
1801         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1802                             CMD_SUBSYSTEM_COMMON))
1803                 return -EPERM;
1804
1805         spin_lock_bh(&adapter->mcc_lock);
1806
1807         wrb = wrb_from_mccq(adapter);
1808         if (!wrb) {
1809                 status = -EBUSY;
1810                 goto err;
1811         }
1812         req = embedded_payload(wrb);
1813
1814         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1815                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1816
1817         status = be_mcc_notify_wait(adapter);
1818         if (!status) {
1819                 struct be_cmd_resp_get_flow_control *resp =
1820                                                 embedded_payload(wrb);
1821                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1822                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1823         }
1824
1825 err:
1826         spin_unlock_bh(&adapter->mcc_lock);
1827         return status;
1828 }
1829
1830 /* Uses mbox */
1831 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1832                 u32 *mode, u32 *caps)
1833 {
1834         struct be_mcc_wrb *wrb;
1835         struct be_cmd_req_query_fw_cfg *req;
1836         int status;
1837
1838         if (mutex_lock_interruptible(&adapter->mbox_lock))
1839                 return -1;
1840
1841         wrb = wrb_from_mbox(adapter);
1842         req = embedded_payload(wrb);
1843
1844         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1845                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1846
1847         status = be_mbox_notify_wait(adapter);
1848         if (!status) {
1849                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1850                 *port_num = le32_to_cpu(resp->phys_port);
1851                 *mode = le32_to_cpu(resp->function_mode);
1852                 *caps = le32_to_cpu(resp->function_caps);
1853         }
1854
1855         mutex_unlock(&adapter->mbox_lock);
1856         return status;
1857 }
1858
1859 /* Uses mbox */
1860 int be_cmd_reset_function(struct be_adapter *adapter)
1861 {
1862         struct be_mcc_wrb *wrb;
1863         struct be_cmd_req_hdr *req;
1864         int status;
1865
1866         if (lancer_chip(adapter)) {
1867                 status = lancer_wait_ready(adapter);
1868                 if (!status) {
1869                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1870                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1871                         status = lancer_test_and_set_rdy_state(adapter);
1872                 }
1873                 if (status) {
1874                         dev_err(&adapter->pdev->dev,
1875                                 "Adapter in non recoverable error\n");
1876                 }
1877                 return status;
1878         }
1879
1880         if (mutex_lock_interruptible(&adapter->mbox_lock))
1881                 return -1;
1882
1883         wrb = wrb_from_mbox(adapter);
1884         req = embedded_payload(wrb);
1885
1886         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1887                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1888
1889         status = be_mbox_notify_wait(adapter);
1890
1891         mutex_unlock(&adapter->mbox_lock);
1892         return status;
1893 }
1894
1895 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1896 {
1897         struct be_mcc_wrb *wrb;
1898         struct be_cmd_req_rss_config *req;
1899         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1900                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1901                         0x3ea83c02, 0x4a110304};
1902         int status;
1903
1904         if (mutex_lock_interruptible(&adapter->mbox_lock))
1905                 return -1;
1906
1907         wrb = wrb_from_mbox(adapter);
1908         req = embedded_payload(wrb);
1909
1910         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1911                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1912
1913         req->if_id = cpu_to_le32(adapter->if_handle);
1914         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1915                                       RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
1916
1917         if (lancer_chip(adapter) || skyhawk_chip(adapter)) {
1918                 req->hdr.version = 1;
1919                 req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 |
1920                                                RSS_ENABLE_UDP_IPV6);
1921         }
1922
1923         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1924         memcpy(req->cpu_table, rsstable, table_size);
1925         memcpy(req->hash, myhash, sizeof(myhash));
1926         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1927
1928         status = be_mbox_notify_wait(adapter);
1929
1930         mutex_unlock(&adapter->mbox_lock);
1931         return status;
1932 }
1933
1934 /* Uses sync mcc */
1935 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1936                         u8 bcn, u8 sts, u8 state)
1937 {
1938         struct be_mcc_wrb *wrb;
1939         struct be_cmd_req_enable_disable_beacon *req;
1940         int status;
1941
1942         spin_lock_bh(&adapter->mcc_lock);
1943
1944         wrb = wrb_from_mccq(adapter);
1945         if (!wrb) {
1946                 status = -EBUSY;
1947                 goto err;
1948         }
1949         req = embedded_payload(wrb);
1950
1951         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1952                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1953
1954         req->port_num = port_num;
1955         req->beacon_state = state;
1956         req->beacon_duration = bcn;
1957         req->status_duration = sts;
1958
1959         status = be_mcc_notify_wait(adapter);
1960
1961 err:
1962         spin_unlock_bh(&adapter->mcc_lock);
1963         return status;
1964 }
1965
1966 /* Uses sync mcc */
1967 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1968 {
1969         struct be_mcc_wrb *wrb;
1970         struct be_cmd_req_get_beacon_state *req;
1971         int status;
1972
1973         spin_lock_bh(&adapter->mcc_lock);
1974
1975         wrb = wrb_from_mccq(adapter);
1976         if (!wrb) {
1977                 status = -EBUSY;
1978                 goto err;
1979         }
1980         req = embedded_payload(wrb);
1981
1982         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1983                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1984
1985         req->port_num = port_num;
1986
1987         status = be_mcc_notify_wait(adapter);
1988         if (!status) {
1989                 struct be_cmd_resp_get_beacon_state *resp =
1990                                                 embedded_payload(wrb);
1991                 *state = resp->beacon_state;
1992         }
1993
1994 err:
1995         spin_unlock_bh(&adapter->mcc_lock);
1996         return status;
1997 }
1998
1999 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2000                             u32 data_size, u32 data_offset,
2001                             const char *obj_name, u32 *data_written,
2002                             u8 *change_status, u8 *addn_status)
2003 {
2004         struct be_mcc_wrb *wrb;
2005         struct lancer_cmd_req_write_object *req;
2006         struct lancer_cmd_resp_write_object *resp;
2007         void *ctxt = NULL;
2008         int status;
2009
2010         spin_lock_bh(&adapter->mcc_lock);
2011         adapter->flash_status = 0;
2012
2013         wrb = wrb_from_mccq(adapter);
2014         if (!wrb) {
2015                 status = -EBUSY;
2016                 goto err_unlock;
2017         }
2018
2019         req = embedded_payload(wrb);
2020
2021         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2022                                 OPCODE_COMMON_WRITE_OBJECT,
2023                                 sizeof(struct lancer_cmd_req_write_object), wrb,
2024                                 NULL);
2025
2026         ctxt = &req->context;
2027         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2028                         write_length, ctxt, data_size);
2029
2030         if (data_size == 0)
2031                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2032                                 eof, ctxt, 1);
2033         else
2034                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2035                                 eof, ctxt, 0);
2036
2037         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2038         req->write_offset = cpu_to_le32(data_offset);
2039         strcpy(req->object_name, obj_name);
2040         req->descriptor_count = cpu_to_le32(1);
2041         req->buf_len = cpu_to_le32(data_size);
2042         req->addr_low = cpu_to_le32((cmd->dma +
2043                                 sizeof(struct lancer_cmd_req_write_object))
2044                                 & 0xFFFFFFFF);
2045         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2046                                 sizeof(struct lancer_cmd_req_write_object)));
2047
2048         be_mcc_notify(adapter);
2049         spin_unlock_bh(&adapter->mcc_lock);
2050
2051         if (!wait_for_completion_timeout(&adapter->flash_compl,
2052                                          msecs_to_jiffies(30000)))
2053                 status = -1;
2054         else
2055                 status = adapter->flash_status;
2056
2057         resp = embedded_payload(wrb);
2058         if (!status) {
2059                 *data_written = le32_to_cpu(resp->actual_write_len);
2060                 *change_status = resp->change_status;
2061         } else {
2062                 *addn_status = resp->additional_status;
2063         }
2064
2065         return status;
2066
2067 err_unlock:
2068         spin_unlock_bh(&adapter->mcc_lock);
2069         return status;
2070 }
2071
2072 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2073                 u32 data_size, u32 data_offset, const char *obj_name,
2074                 u32 *data_read, u32 *eof, u8 *addn_status)
2075 {
2076         struct be_mcc_wrb *wrb;
2077         struct lancer_cmd_req_read_object *req;
2078         struct lancer_cmd_resp_read_object *resp;
2079         int status;
2080
2081         spin_lock_bh(&adapter->mcc_lock);
2082
2083         wrb = wrb_from_mccq(adapter);
2084         if (!wrb) {
2085                 status = -EBUSY;
2086                 goto err_unlock;
2087         }
2088
2089         req = embedded_payload(wrb);
2090
2091         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2092                         OPCODE_COMMON_READ_OBJECT,
2093                         sizeof(struct lancer_cmd_req_read_object), wrb,
2094                         NULL);
2095
2096         req->desired_read_len = cpu_to_le32(data_size);
2097         req->read_offset = cpu_to_le32(data_offset);
2098         strcpy(req->object_name, obj_name);
2099         req->descriptor_count = cpu_to_le32(1);
2100         req->buf_len = cpu_to_le32(data_size);
2101         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2102         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2103
2104         status = be_mcc_notify_wait(adapter);
2105
2106         resp = embedded_payload(wrb);
2107         if (!status) {
2108                 *data_read = le32_to_cpu(resp->actual_read_len);
2109                 *eof = le32_to_cpu(resp->eof);
2110         } else {
2111                 *addn_status = resp->additional_status;
2112         }
2113
2114 err_unlock:
2115         spin_unlock_bh(&adapter->mcc_lock);
2116         return status;
2117 }
2118
2119 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2120                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2121 {
2122         struct be_mcc_wrb *wrb;
2123         struct be_cmd_write_flashrom *req;
2124         int status;
2125
2126         spin_lock_bh(&adapter->mcc_lock);
2127         adapter->flash_status = 0;
2128
2129         wrb = wrb_from_mccq(adapter);
2130         if (!wrb) {
2131                 status = -EBUSY;
2132                 goto err_unlock;
2133         }
2134         req = cmd->va;
2135
2136         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2137                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2138
2139         req->params.op_type = cpu_to_le32(flash_type);
2140         req->params.op_code = cpu_to_le32(flash_opcode);
2141         req->params.data_buf_size = cpu_to_le32(buf_size);
2142
2143         be_mcc_notify(adapter);
2144         spin_unlock_bh(&adapter->mcc_lock);
2145
2146         if (!wait_for_completion_timeout(&adapter->flash_compl,
2147                         msecs_to_jiffies(40000)))
2148                 status = -1;
2149         else
2150                 status = adapter->flash_status;
2151
2152         return status;
2153
2154 err_unlock:
2155         spin_unlock_bh(&adapter->mcc_lock);
2156         return status;
2157 }
2158
2159 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2160                          int offset)
2161 {
2162         struct be_mcc_wrb *wrb;
2163         struct be_cmd_read_flash_crc *req;
2164         int status;
2165
2166         spin_lock_bh(&adapter->mcc_lock);
2167
2168         wrb = wrb_from_mccq(adapter);
2169         if (!wrb) {
2170                 status = -EBUSY;
2171                 goto err;
2172         }
2173         req = embedded_payload(wrb);
2174
2175         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2176                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2177                                wrb, NULL);
2178
2179         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2180         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2181         req->params.offset = cpu_to_le32(offset);
2182         req->params.data_buf_size = cpu_to_le32(0x4);
2183
2184         status = be_mcc_notify_wait(adapter);
2185         if (!status)
2186                 memcpy(flashed_crc, req->crc, 4);
2187
2188 err:
2189         spin_unlock_bh(&adapter->mcc_lock);
2190         return status;
2191 }
2192
2193 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2194                                 struct be_dma_mem *nonemb_cmd)
2195 {
2196         struct be_mcc_wrb *wrb;
2197         struct be_cmd_req_acpi_wol_magic_config *req;
2198         int status;
2199
2200         spin_lock_bh(&adapter->mcc_lock);
2201
2202         wrb = wrb_from_mccq(adapter);
2203         if (!wrb) {
2204                 status = -EBUSY;
2205                 goto err;
2206         }
2207         req = nonemb_cmd->va;
2208
2209         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2210                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2211                 nonemb_cmd);
2212         memcpy(req->magic_mac, mac, ETH_ALEN);
2213
2214         status = be_mcc_notify_wait(adapter);
2215
2216 err:
2217         spin_unlock_bh(&adapter->mcc_lock);
2218         return status;
2219 }
2220
2221 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2222                         u8 loopback_type, u8 enable)
2223 {
2224         struct be_mcc_wrb *wrb;
2225         struct be_cmd_req_set_lmode *req;
2226         int status;
2227
2228         spin_lock_bh(&adapter->mcc_lock);
2229
2230         wrb = wrb_from_mccq(adapter);
2231         if (!wrb) {
2232                 status = -EBUSY;
2233                 goto err;
2234         }
2235
2236         req = embedded_payload(wrb);
2237
2238         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2239                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2240                         NULL);
2241
2242         req->src_port = port_num;
2243         req->dest_port = port_num;
2244         req->loopback_type = loopback_type;
2245         req->loopback_state = enable;
2246
2247         status = be_mcc_notify_wait(adapter);
2248 err:
2249         spin_unlock_bh(&adapter->mcc_lock);
2250         return status;
2251 }
2252
2253 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2254                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2255 {
2256         struct be_mcc_wrb *wrb;
2257         struct be_cmd_req_loopback_test *req;
2258         int status;
2259
2260         spin_lock_bh(&adapter->mcc_lock);
2261
2262         wrb = wrb_from_mccq(adapter);
2263         if (!wrb) {
2264                 status = -EBUSY;
2265                 goto err;
2266         }
2267
2268         req = embedded_payload(wrb);
2269
2270         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2271                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2272         req->hdr.timeout = cpu_to_le32(4);
2273
2274         req->pattern = cpu_to_le64(pattern);
2275         req->src_port = cpu_to_le32(port_num);
2276         req->dest_port = cpu_to_le32(port_num);
2277         req->pkt_size = cpu_to_le32(pkt_size);
2278         req->num_pkts = cpu_to_le32(num_pkts);
2279         req->loopback_type = cpu_to_le32(loopback_type);
2280
2281         status = be_mcc_notify_wait(adapter);
2282         if (!status) {
2283                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2284                 status = le32_to_cpu(resp->status);
2285         }
2286
2287 err:
2288         spin_unlock_bh(&adapter->mcc_lock);
2289         return status;
2290 }
2291
2292 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2293                                 u32 byte_cnt, struct be_dma_mem *cmd)
2294 {
2295         struct be_mcc_wrb *wrb;
2296         struct be_cmd_req_ddrdma_test *req;
2297         int status;
2298         int i, j = 0;
2299
2300         spin_lock_bh(&adapter->mcc_lock);
2301
2302         wrb = wrb_from_mccq(adapter);
2303         if (!wrb) {
2304                 status = -EBUSY;
2305                 goto err;
2306         }
2307         req = cmd->va;
2308         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2309                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2310
2311         req->pattern = cpu_to_le64(pattern);
2312         req->byte_count = cpu_to_le32(byte_cnt);
2313         for (i = 0; i < byte_cnt; i++) {
2314                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2315                 j++;
2316                 if (j > 7)
2317                         j = 0;
2318         }
2319
2320         status = be_mcc_notify_wait(adapter);
2321
2322         if (!status) {
2323                 struct be_cmd_resp_ddrdma_test *resp;
2324                 resp = cmd->va;
2325                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2326                                 resp->snd_err) {
2327                         status = -1;
2328                 }
2329         }
2330
2331 err:
2332         spin_unlock_bh(&adapter->mcc_lock);
2333         return status;
2334 }
2335
2336 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2337                                 struct be_dma_mem *nonemb_cmd)
2338 {
2339         struct be_mcc_wrb *wrb;
2340         struct be_cmd_req_seeprom_read *req;
2341         struct be_sge *sge;
2342         int status;
2343
2344         spin_lock_bh(&adapter->mcc_lock);
2345
2346         wrb = wrb_from_mccq(adapter);
2347         if (!wrb) {
2348                 status = -EBUSY;
2349                 goto err;
2350         }
2351         req = nonemb_cmd->va;
2352         sge = nonembedded_sgl(wrb);
2353
2354         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2355                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2356                         nonemb_cmd);
2357
2358         status = be_mcc_notify_wait(adapter);
2359
2360 err:
2361         spin_unlock_bh(&adapter->mcc_lock);
2362         return status;
2363 }
2364
2365 int be_cmd_get_phy_info(struct be_adapter *adapter)
2366 {
2367         struct be_mcc_wrb *wrb;
2368         struct be_cmd_req_get_phy_info *req;
2369         struct be_dma_mem cmd;
2370         int status;
2371
2372         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2373                             CMD_SUBSYSTEM_COMMON))
2374                 return -EPERM;
2375
2376         spin_lock_bh(&adapter->mcc_lock);
2377
2378         wrb = wrb_from_mccq(adapter);
2379         if (!wrb) {
2380                 status = -EBUSY;
2381                 goto err;
2382         }
2383         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2384         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2385                                         &cmd.dma);
2386         if (!cmd.va) {
2387                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2388                 status = -ENOMEM;
2389                 goto err;
2390         }
2391
2392         req = cmd.va;
2393
2394         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2395                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2396                         wrb, &cmd);
2397
2398         status = be_mcc_notify_wait(adapter);
2399         if (!status) {
2400                 struct be_phy_info *resp_phy_info =
2401                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2402                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2403                 adapter->phy.interface_type =
2404                         le16_to_cpu(resp_phy_info->interface_type);
2405                 adapter->phy.auto_speeds_supported =
2406                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2407                 adapter->phy.fixed_speeds_supported =
2408                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2409                 adapter->phy.misc_params =
2410                         le32_to_cpu(resp_phy_info->misc_params);
2411         }
2412         pci_free_consistent(adapter->pdev, cmd.size,
2413                                 cmd.va, cmd.dma);
2414 err:
2415         spin_unlock_bh(&adapter->mcc_lock);
2416         return status;
2417 }
2418
2419 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2420 {
2421         struct be_mcc_wrb *wrb;
2422         struct be_cmd_req_set_qos *req;
2423         int status;
2424
2425         spin_lock_bh(&adapter->mcc_lock);
2426
2427         wrb = wrb_from_mccq(adapter);
2428         if (!wrb) {
2429                 status = -EBUSY;
2430                 goto err;
2431         }
2432
2433         req = embedded_payload(wrb);
2434
2435         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2436                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2437
2438         req->hdr.domain = domain;
2439         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2440         req->max_bps_nic = cpu_to_le32(bps);
2441
2442         status = be_mcc_notify_wait(adapter);
2443
2444 err:
2445         spin_unlock_bh(&adapter->mcc_lock);
2446         return status;
2447 }
2448
2449 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2450 {
2451         struct be_mcc_wrb *wrb;
2452         struct be_cmd_req_cntl_attribs *req;
2453         struct be_cmd_resp_cntl_attribs *resp;
2454         int status;
2455         int payload_len = max(sizeof(*req), sizeof(*resp));
2456         struct mgmt_controller_attrib *attribs;
2457         struct be_dma_mem attribs_cmd;
2458
2459         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2460         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2461         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2462                                                 &attribs_cmd.dma);
2463         if (!attribs_cmd.va) {
2464                 dev_err(&adapter->pdev->dev,
2465                                 "Memory allocation failure\n");
2466                 return -ENOMEM;
2467         }
2468
2469         if (mutex_lock_interruptible(&adapter->mbox_lock))
2470                 return -1;
2471
2472         wrb = wrb_from_mbox(adapter);
2473         if (!wrb) {
2474                 status = -EBUSY;
2475                 goto err;
2476         }
2477         req = attribs_cmd.va;
2478
2479         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2480                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2481                         &attribs_cmd);
2482
2483         status = be_mbox_notify_wait(adapter);
2484         if (!status) {
2485                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2486                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2487         }
2488
2489 err:
2490         mutex_unlock(&adapter->mbox_lock);
2491         pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2492                                         attribs_cmd.dma);
2493         return status;
2494 }
2495
2496 /* Uses mbox */
2497 int be_cmd_req_native_mode(struct be_adapter *adapter)
2498 {
2499         struct be_mcc_wrb *wrb;
2500         struct be_cmd_req_set_func_cap *req;
2501         int status;
2502
2503         if (mutex_lock_interruptible(&adapter->mbox_lock))
2504                 return -1;
2505
2506         wrb = wrb_from_mbox(adapter);
2507         if (!wrb) {
2508                 status = -EBUSY;
2509                 goto err;
2510         }
2511
2512         req = embedded_payload(wrb);
2513
2514         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2515                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2516
2517         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2518                                 CAPABILITY_BE3_NATIVE_ERX_API);
2519         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2520
2521         status = be_mbox_notify_wait(adapter);
2522         if (!status) {
2523                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2524                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2525                                         CAPABILITY_BE3_NATIVE_ERX_API;
2526                 if (!adapter->be3_native)
2527                         dev_warn(&adapter->pdev->dev,
2528                                  "adapter not in advanced mode\n");
2529         }
2530 err:
2531         mutex_unlock(&adapter->mbox_lock);
2532         return status;
2533 }
2534
2535 /* Get privilege(s) for a function */
2536 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2537                              u32 domain)
2538 {
2539         struct be_mcc_wrb *wrb;
2540         struct be_cmd_req_get_fn_privileges *req;
2541         int status;
2542
2543         spin_lock_bh(&adapter->mcc_lock);
2544
2545         wrb = wrb_from_mccq(adapter);
2546         if (!wrb) {
2547                 status = -EBUSY;
2548                 goto err;
2549         }
2550
2551         req = embedded_payload(wrb);
2552
2553         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2554                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2555                                wrb, NULL);
2556
2557         req->hdr.domain = domain;
2558
2559         status = be_mcc_notify_wait(adapter);
2560         if (!status) {
2561                 struct be_cmd_resp_get_fn_privileges *resp =
2562                                                 embedded_payload(wrb);
2563                 *privilege = le32_to_cpu(resp->privilege_mask);
2564         }
2565
2566 err:
2567         spin_unlock_bh(&adapter->mcc_lock);
2568         return status;
2569 }
2570
2571 /* Uses synchronous MCCQ */
2572 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2573                              bool *pmac_id_active, u32 *pmac_id, u8 domain)
2574 {
2575         struct be_mcc_wrb *wrb;
2576         struct be_cmd_req_get_mac_list *req;
2577         int status;
2578         int mac_count;
2579         struct be_dma_mem get_mac_list_cmd;
2580         int i;
2581
2582         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2583         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2584         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2585                         get_mac_list_cmd.size,
2586                         &get_mac_list_cmd.dma);
2587
2588         if (!get_mac_list_cmd.va) {
2589                 dev_err(&adapter->pdev->dev,
2590                                 "Memory allocation failure during GET_MAC_LIST\n");
2591                 return -ENOMEM;
2592         }
2593
2594         spin_lock_bh(&adapter->mcc_lock);
2595
2596         wrb = wrb_from_mccq(adapter);
2597         if (!wrb) {
2598                 status = -EBUSY;
2599                 goto out;
2600         }
2601
2602         req = get_mac_list_cmd.va;
2603
2604         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2605                                 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2606                                 wrb, &get_mac_list_cmd);
2607
2608         req->hdr.domain = domain;
2609         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2610         req->perm_override = 1;
2611
2612         status = be_mcc_notify_wait(adapter);
2613         if (!status) {
2614                 struct be_cmd_resp_get_mac_list *resp =
2615                                                 get_mac_list_cmd.va;
2616                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2617                 /* Mac list returned could contain one or more active mac_ids
2618                  * or one or more true or pseudo permanant mac addresses.
2619                  * If an active mac_id is present, return first active mac_id
2620                  * found.
2621                  */
2622                 for (i = 0; i < mac_count; i++) {
2623                         struct get_list_macaddr *mac_entry;
2624                         u16 mac_addr_size;
2625                         u32 mac_id;
2626
2627                         mac_entry = &resp->macaddr_list[i];
2628                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2629                         /* mac_id is a 32 bit value and mac_addr size
2630                          * is 6 bytes
2631                          */
2632                         if (mac_addr_size == sizeof(u32)) {
2633                                 *pmac_id_active = true;
2634                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2635                                 *pmac_id = le32_to_cpu(mac_id);
2636                                 goto out;
2637                         }
2638                 }
2639                 /* If no active mac_id found, return first mac addr */
2640                 *pmac_id_active = false;
2641                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2642                                                                 ETH_ALEN);
2643         }
2644
2645 out:
2646         spin_unlock_bh(&adapter->mcc_lock);
2647         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2648                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2649         return status;
2650 }
2651
2652 /* Uses synchronous MCCQ */
2653 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2654                         u8 mac_count, u32 domain)
2655 {
2656         struct be_mcc_wrb *wrb;
2657         struct be_cmd_req_set_mac_list *req;
2658         int status;
2659         struct be_dma_mem cmd;
2660
2661         memset(&cmd, 0, sizeof(struct be_dma_mem));
2662         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2663         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2664                         &cmd.dma, GFP_KERNEL);
2665         if (!cmd.va) {
2666                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2667                 return -ENOMEM;
2668         }
2669
2670         spin_lock_bh(&adapter->mcc_lock);
2671
2672         wrb = wrb_from_mccq(adapter);
2673         if (!wrb) {
2674                 status = -EBUSY;
2675                 goto err;
2676         }
2677
2678         req = cmd.va;
2679         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2680                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2681                                 wrb, &cmd);
2682
2683         req->hdr.domain = domain;
2684         req->mac_count = mac_count;
2685         if (mac_count)
2686                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2687
2688         status = be_mcc_notify_wait(adapter);
2689
2690 err:
2691         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2692                                 cmd.va, cmd.dma);
2693         spin_unlock_bh(&adapter->mcc_lock);
2694         return status;
2695 }
2696
2697 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2698                         u32 domain, u16 intf_id)
2699 {
2700         struct be_mcc_wrb *wrb;
2701         struct be_cmd_req_set_hsw_config *req;
2702         void *ctxt;
2703         int status;
2704
2705         spin_lock_bh(&adapter->mcc_lock);
2706
2707         wrb = wrb_from_mccq(adapter);
2708         if (!wrb) {
2709                 status = -EBUSY;
2710                 goto err;
2711         }
2712
2713         req = embedded_payload(wrb);
2714         ctxt = &req->context;
2715
2716         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2717                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2718
2719         req->hdr.domain = domain;
2720         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2721         if (pvid) {
2722                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2723                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2724         }
2725
2726         be_dws_cpu_to_le(req->context, sizeof(req->context));
2727         status = be_mcc_notify_wait(adapter);
2728
2729 err:
2730         spin_unlock_bh(&adapter->mcc_lock);
2731         return status;
2732 }
2733
2734 /* Get Hyper switch config */
2735 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2736                         u32 domain, u16 intf_id)
2737 {
2738         struct be_mcc_wrb *wrb;
2739         struct be_cmd_req_get_hsw_config *req;
2740         void *ctxt;
2741         int status;
2742         u16 vid;
2743
2744         spin_lock_bh(&adapter->mcc_lock);
2745
2746         wrb = wrb_from_mccq(adapter);
2747         if (!wrb) {
2748                 status = -EBUSY;
2749                 goto err;
2750         }
2751
2752         req = embedded_payload(wrb);
2753         ctxt = &req->context;
2754
2755         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2756                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2757
2758         req->hdr.domain = domain;
2759         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2760                                                                 intf_id);
2761         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2762         be_dws_cpu_to_le(req->context, sizeof(req->context));
2763
2764         status = be_mcc_notify_wait(adapter);
2765         if (!status) {
2766                 struct be_cmd_resp_get_hsw_config *resp =
2767                                                 embedded_payload(wrb);
2768                 be_dws_le_to_cpu(&resp->context,
2769                                                 sizeof(resp->context));
2770                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2771                                                         pvid, &resp->context);
2772                 *pvid = le16_to_cpu(vid);
2773         }
2774
2775 err:
2776         spin_unlock_bh(&adapter->mcc_lock);
2777         return status;
2778 }
2779
2780 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2781 {
2782         struct be_mcc_wrb *wrb;
2783         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2784         int status;
2785         int payload_len = sizeof(*req);
2786         struct be_dma_mem cmd;
2787
2788         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2789                             CMD_SUBSYSTEM_ETH))
2790                 return -EPERM;
2791
2792         memset(&cmd, 0, sizeof(struct be_dma_mem));
2793         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2794         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2795                                                &cmd.dma);
2796         if (!cmd.va) {
2797                 dev_err(&adapter->pdev->dev,
2798                                 "Memory allocation failure\n");
2799                 return -ENOMEM;
2800         }
2801
2802         if (mutex_lock_interruptible(&adapter->mbox_lock))
2803                 return -1;
2804
2805         wrb = wrb_from_mbox(adapter);
2806         if (!wrb) {
2807                 status = -EBUSY;
2808                 goto err;
2809         }
2810
2811         req = cmd.va;
2812
2813         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2814                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2815                                payload_len, wrb, &cmd);
2816
2817         req->hdr.version = 1;
2818         req->query_options = BE_GET_WOL_CAP;
2819
2820         status = be_mbox_notify_wait(adapter);
2821         if (!status) {
2822                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2823                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2824
2825                 /* the command could succeed misleadingly on old f/w
2826                  * which is not aware of the V1 version. fake an error. */
2827                 if (resp->hdr.response_length < payload_len) {
2828                         status = -1;
2829                         goto err;
2830                 }
2831                 adapter->wol_cap = resp->wol_settings;
2832         }
2833 err:
2834         mutex_unlock(&adapter->mbox_lock);
2835         pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2836         return status;
2837
2838 }
2839 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2840                                    struct be_dma_mem *cmd)
2841 {
2842         struct be_mcc_wrb *wrb;
2843         struct be_cmd_req_get_ext_fat_caps *req;
2844         int status;
2845
2846         if (mutex_lock_interruptible(&adapter->mbox_lock))
2847                 return -1;
2848
2849         wrb = wrb_from_mbox(adapter);
2850         if (!wrb) {
2851                 status = -EBUSY;
2852                 goto err;
2853         }
2854
2855         req = cmd->va;
2856         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2857                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2858                                cmd->size, wrb, cmd);
2859         req->parameter_type = cpu_to_le32(1);
2860
2861         status = be_mbox_notify_wait(adapter);
2862 err:
2863         mutex_unlock(&adapter->mbox_lock);
2864         return status;
2865 }
2866
2867 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2868                                    struct be_dma_mem *cmd,
2869                                    struct be_fat_conf_params *configs)
2870 {
2871         struct be_mcc_wrb *wrb;
2872         struct be_cmd_req_set_ext_fat_caps *req;
2873         int status;
2874
2875         spin_lock_bh(&adapter->mcc_lock);
2876
2877         wrb = wrb_from_mccq(adapter);
2878         if (!wrb) {
2879                 status = -EBUSY;
2880                 goto err;
2881         }
2882
2883         req = cmd->va;
2884         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2885         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2886                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2887                                cmd->size, wrb, cmd);
2888
2889         status = be_mcc_notify_wait(adapter);
2890 err:
2891         spin_unlock_bh(&adapter->mcc_lock);
2892         return status;
2893 }
2894
2895 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2896 {
2897         struct be_mcc_wrb *wrb;
2898         struct be_cmd_req_get_port_name *req;
2899         int status;
2900
2901         if (!lancer_chip(adapter)) {
2902                 *port_name = adapter->hba_port_num + '0';
2903                 return 0;
2904         }
2905
2906         spin_lock_bh(&adapter->mcc_lock);
2907
2908         wrb = wrb_from_mccq(adapter);
2909         if (!wrb) {
2910                 status = -EBUSY;
2911                 goto err;
2912         }
2913
2914         req = embedded_payload(wrb);
2915
2916         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2917                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2918                                NULL);
2919         req->hdr.version = 1;
2920
2921         status = be_mcc_notify_wait(adapter);
2922         if (!status) {
2923                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2924                 *port_name = resp->port_name[adapter->hba_port_num];
2925         } else {
2926                 *port_name = adapter->hba_port_num + '0';
2927         }
2928 err:
2929         spin_unlock_bh(&adapter->mcc_lock);
2930         return status;
2931 }
2932
2933 static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
2934                                                     u32 max_buf_size)
2935 {
2936         struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf;
2937         int i;
2938
2939         for (i = 0; i < desc_count; i++) {
2940                 desc->desc_len = RESOURCE_DESC_SIZE;
2941                 if (((void *)desc + desc->desc_len) >
2942                     (void *)(buf + max_buf_size)) {
2943                         desc = NULL;
2944                         break;
2945                 }
2946
2947                 if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_ID)
2948                         break;
2949
2950                 desc = (void *)desc + desc->desc_len;
2951         }
2952
2953         if (!desc || i == MAX_RESOURCE_DESC)
2954                 return NULL;
2955
2956         return desc;
2957 }
2958
2959 /* Uses Mbox */
2960 int be_cmd_get_func_config(struct be_adapter *adapter)
2961 {
2962         struct be_mcc_wrb *wrb;
2963         struct be_cmd_req_get_func_config *req;
2964         int status;
2965         struct be_dma_mem cmd;
2966
2967         memset(&cmd, 0, sizeof(struct be_dma_mem));
2968         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
2969         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2970                                       &cmd.dma);
2971         if (!cmd.va) {
2972                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2973                 return -ENOMEM;
2974         }
2975         if (mutex_lock_interruptible(&adapter->mbox_lock))
2976                 return -1;
2977
2978         wrb = wrb_from_mbox(adapter);
2979         if (!wrb) {
2980                 status = -EBUSY;
2981                 goto err;
2982         }
2983
2984         req = cmd.va;
2985
2986         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2987                                OPCODE_COMMON_GET_FUNC_CONFIG,
2988                                cmd.size, wrb, &cmd);
2989
2990         status = be_mbox_notify_wait(adapter);
2991         if (!status) {
2992                 struct be_cmd_resp_get_func_config *resp = cmd.va;
2993                 u32 desc_count = le32_to_cpu(resp->desc_count);
2994                 struct be_nic_resource_desc *desc;
2995
2996                 desc = be_get_nic_desc(resp->func_param, desc_count,
2997                                        sizeof(resp->func_param));
2998                 if (!desc) {
2999                         status = -EINVAL;
3000                         goto err;
3001                 }
3002
3003                 adapter->pf_number = desc->pf_num;
3004                 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count);
3005                 adapter->max_vlans = le16_to_cpu(desc->vlan_count);
3006                 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3007                 adapter->max_tx_queues = le16_to_cpu(desc->txq_count);
3008                 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count);
3009                 adapter->max_rx_queues = le16_to_cpu(desc->rq_count);
3010
3011                 adapter->max_event_queues = le16_to_cpu(desc->eq_count);
3012                 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags);
3013         }
3014 err:
3015         mutex_unlock(&adapter->mbox_lock);
3016         pci_free_consistent(adapter->pdev, cmd.size,
3017                             cmd.va, cmd.dma);
3018         return status;
3019 }
3020
3021  /* Uses sync mcc */
3022 int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
3023                               u8 domain)
3024 {
3025         struct be_mcc_wrb *wrb;
3026         struct be_cmd_req_get_profile_config *req;
3027         int status;
3028         struct be_dma_mem cmd;
3029
3030         memset(&cmd, 0, sizeof(struct be_dma_mem));
3031         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3032         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3033                                       &cmd.dma);
3034         if (!cmd.va) {
3035                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3036                 return -ENOMEM;
3037         }
3038
3039         spin_lock_bh(&adapter->mcc_lock);
3040
3041         wrb = wrb_from_mccq(adapter);
3042         if (!wrb) {
3043                 status = -EBUSY;
3044                 goto err;
3045         }
3046
3047         req = cmd.va;
3048
3049         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3050                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3051                                cmd.size, wrb, &cmd);
3052
3053         req->type = ACTIVE_PROFILE_TYPE;
3054         req->hdr.domain = domain;
3055
3056         status = be_mcc_notify_wait(adapter);
3057         if (!status) {
3058                 struct be_cmd_resp_get_profile_config *resp = cmd.va;
3059                 u32 desc_count = le32_to_cpu(resp->desc_count);
3060                 struct be_nic_resource_desc *desc;
3061
3062                 desc = be_get_nic_desc(resp->func_param, desc_count,
3063                                        sizeof(resp->func_param));
3064
3065                 if (!desc) {
3066                         status = -EINVAL;
3067                         goto err;
3068                 }
3069                 *cap_flags = le32_to_cpu(desc->cap_flags);
3070         }
3071 err:
3072         spin_unlock_bh(&adapter->mcc_lock);
3073         pci_free_consistent(adapter->pdev, cmd.size,
3074                             cmd.va, cmd.dma);
3075         return status;
3076 }
3077
3078 /* Uses sync mcc */
3079 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3080                               u8 domain)
3081 {
3082         struct be_mcc_wrb *wrb;
3083         struct be_cmd_req_set_profile_config *req;
3084         int status;
3085
3086         spin_lock_bh(&adapter->mcc_lock);
3087
3088         wrb = wrb_from_mccq(adapter);
3089         if (!wrb) {
3090                 status = -EBUSY;
3091                 goto err;
3092         }
3093
3094         req = embedded_payload(wrb);
3095
3096         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3097                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3098                                wrb, NULL);
3099
3100         req->hdr.domain = domain;
3101         req->desc_count = cpu_to_le32(1);
3102
3103         req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_ID;
3104         req->nic_desc.desc_len = RESOURCE_DESC_SIZE;
3105         req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3106         req->nic_desc.pf_num = adapter->pf_number;
3107         req->nic_desc.vf_num = domain;
3108
3109         /* Mark fields invalid */
3110         req->nic_desc.unicast_mac_count = 0xFFFF;
3111         req->nic_desc.mcc_count = 0xFFFF;
3112         req->nic_desc.vlan_count = 0xFFFF;
3113         req->nic_desc.mcast_mac_count = 0xFFFF;
3114         req->nic_desc.txq_count = 0xFFFF;
3115         req->nic_desc.rq_count = 0xFFFF;
3116         req->nic_desc.rssq_count = 0xFFFF;
3117         req->nic_desc.lro_count = 0xFFFF;
3118         req->nic_desc.cq_count = 0xFFFF;
3119         req->nic_desc.toe_conn_count = 0xFFFF;
3120         req->nic_desc.eq_count = 0xFFFF;
3121         req->nic_desc.link_param = 0xFF;
3122         req->nic_desc.bw_min = 0xFFFFFFFF;
3123         req->nic_desc.acpi_params = 0xFF;
3124         req->nic_desc.wol_param = 0x0F;
3125
3126         /* Change BW */
3127         req->nic_desc.bw_min = cpu_to_le32(bps);
3128         req->nic_desc.bw_max = cpu_to_le32(bps);
3129         status = be_mcc_notify_wait(adapter);
3130 err:
3131         spin_unlock_bh(&adapter->mcc_lock);
3132         return status;
3133 }
3134
3135 /* Uses sync mcc */
3136 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3137 {
3138         struct be_mcc_wrb *wrb;
3139         struct be_cmd_enable_disable_vf *req;
3140         int status;
3141
3142         if (!lancer_chip(adapter))
3143                 return 0;
3144
3145         spin_lock_bh(&adapter->mcc_lock);
3146
3147         wrb = wrb_from_mccq(adapter);
3148         if (!wrb) {
3149                 status = -EBUSY;
3150                 goto err;
3151         }
3152
3153         req = embedded_payload(wrb);
3154
3155         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3156                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3157                                wrb, NULL);
3158
3159         req->hdr.domain = domain;
3160         req->enable = 1;
3161         status = be_mcc_notify_wait(adapter);
3162 err:
3163         spin_unlock_bh(&adapter->mcc_lock);
3164         return status;
3165 }
3166
3167 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3168                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3169 {
3170         struct be_adapter *adapter = netdev_priv(netdev_handle);
3171         struct be_mcc_wrb *wrb;
3172         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3173         struct be_cmd_req_hdr *req;
3174         struct be_cmd_resp_hdr *resp;
3175         int status;
3176
3177         spin_lock_bh(&adapter->mcc_lock);
3178
3179         wrb = wrb_from_mccq(adapter);
3180         if (!wrb) {
3181                 status = -EBUSY;
3182                 goto err;
3183         }
3184         req = embedded_payload(wrb);
3185         resp = embedded_payload(wrb);
3186
3187         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3188                                hdr->opcode, wrb_payload_size, wrb, NULL);
3189         memcpy(req, wrb_payload, wrb_payload_size);
3190         be_dws_cpu_to_le(req, wrb_payload_size);
3191
3192         status = be_mcc_notify_wait(adapter);
3193         if (cmd_status)
3194                 *cmd_status = (status & 0xffff);
3195         if (ext_status)
3196                 *ext_status = 0;
3197         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3198         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3199 err:
3200         spin_unlock_bh(&adapter->mcc_lock);
3201         return status;
3202 }
3203 EXPORT_SYMBOL(be_roce_mcc_cmd);