Pileus Git - ~andy/linux/blob - drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
  56                            u8 subsystem)
  57 {
  58         int i;
  59         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  60         u32 cmd_privileges = adapter->cmd_privileges;
  61
  62         for (i = 0; i < num_entries; i++)
  63                 if (opcode == cmd_priv_map[i].opcode &&
  64                     subsystem == cmd_priv_map[i].subsystem)
  65                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  66                                 return false;
  67
  68         return true;
  69 }
  70
  71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  72 {
  73         return wrb->payload.embedded_payload;
  74 }
  75
  76 static void be_mcc_notify(struct be_adapter *adapter)
  77 {
  78         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  79         u32 val = 0;
  80
  81         if (be_error(adapter))
  82                 return;
  83
  84         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  85         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  86
  87         wmb();
  88         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  89 }
  90
  91 /* To check if valid bit is set, check the entire word as we don't know
  92  * the endianness of the data (old entry is host endian while a new entry is
  93  * little endian) */
  94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  95 {
  96         u32 flags;
  97
  98         if (compl->flags != 0) {
  99                 flags = le32_to_cpu(compl->flags);
 100                 if (flags & CQE_FLAGS_VALID_MASK) {
 101                         compl->flags = flags;
 102                         return true;
 103                 }
 104         }
 105         return false;
 106 }
 107
 108 /* Need to reset the entire word that houses the valid bit */
 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 110 {
 111         compl->flags = 0;
 112 }
 113
 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 115 {
 116         unsigned long addr;
 117
 118         addr = tag1;
 119         addr = ((addr << 16) << 16) | tag0;
 120         return (void *)addr;
 121 }
 122
 123 static int be_mcc_compl_process(struct be_adapter *adapter,
 124                                 struct be_mcc_compl *compl)
 125 {
 126         u16 compl_status, extd_status;
 127         struct be_cmd_resp_hdr *resp_hdr;
 128         u8 opcode = 0, subsystem = 0;
 129
 130         /* Just swap the status to host endian; mcc tag is opaquely copied
 131          * from mcc_wrb */
 132         be_dws_le_to_cpu(compl, 4);
 133
 134         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 135                                 CQE_STATUS_COMPL_MASK;
 136
 137         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 138
 139         if (resp_hdr) {
 140                 opcode = resp_hdr->opcode;
 141                 subsystem = resp_hdr->subsystem;
 142         }
 143
 144         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 145              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 146             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 147                 adapter->flash_status = compl_status;
 148                 complete(&adapter->flash_compl);
 149         }
 150
 151         if (compl_status == MCC_STATUS_SUCCESS) {
 152                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 153                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 154                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 155                         be_parse_stats(adapter);
 156                         adapter->stats_cmd_sent = false;
 157                 }
 158                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 159                     subsystem == CMD_SUBSYSTEM_COMMON) {
 160                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 161                                 (void *)resp_hdr;
 162                         adapter->drv_stats.be_on_die_temperature =
 163                                 resp->on_die_temperature;
 164                 }
 165         } else {
 166                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 167                         adapter->be_get_temp_freq = 0;
 168
 169                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 170                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 171                         goto done;
 172
 173                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 174                         dev_warn(&adapter->pdev->dev,
 175                                  "VF is not privileged to issue opcode %d-%d\n",
 176                                  opcode, subsystem);
 177                 } else {
 178                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 179                                         CQE_STATUS_EXTD_MASK;
 180                         dev_err(&adapter->pdev->dev,
 181                                 "opcode %d-%d failed:status %d-%d\n",
 182                                 opcode, subsystem, compl_status, extd_status);
 183                 }
 184         }
 185 done:
 186         return compl_status;
 187 }
 188
 189 /* Link state evt is a string of bytes; no need for endian swapping */
 190 static void be_async_link_state_process(struct be_adapter *adapter,
 191                 struct be_async_event_link_state *evt)
 192 {
 193         /* When link status changes, link speed must be re-queried from FW */
 194         adapter->phy.link_speed = -1;
 195
 196         /* Ignore physical link event */
 197         if (lancer_chip(adapter) &&
 198             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 199                 return;
 200
 201         /* For the initial link status do not rely on the ASYNC event as
 202          * it may not be received in some cases.
 203          */
 204         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 205                 be_link_status_update(adapter, evt->port_link_status);
 206 }
 207
 208 /* Grp5 CoS Priority evt */
 209 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 210                 struct be_async_event_grp5_cos_priority *evt)
 211 {
 212         if (evt->valid) {
 213                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 214                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 215                 adapter->recommended_prio =
 216                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 217         }
 218 }
 219
 220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 221 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 222                 struct be_async_event_grp5_qos_link_speed *evt)
 223 {
 224         if (adapter->phy.link_speed >= 0 &&
 225             evt->physical_port == adapter->port_num)
 226                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 227 }
 228
 229 /*Grp5 PVID evt*/
 230 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 231                 struct be_async_event_grp5_pvid_state *evt)
 232 {
 233         if (evt->enabled)
 234                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 235         else
 236                 adapter->pvid = 0;
 237 }
 238
 239 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 240                 u32 trailer, struct be_mcc_compl *evt)
 241 {
 242         u8 event_type = 0;
 243
 244         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 245                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 246
 247         switch (event_type) {
 248         case ASYNC_EVENT_COS_PRIORITY:
 249                 be_async_grp5_cos_priority_process(adapter,
 250                 (struct be_async_event_grp5_cos_priority *)evt);
 251         break;
 252         case ASYNC_EVENT_QOS_SPEED:
 253                 be_async_grp5_qos_speed_process(adapter,
 254                 (struct be_async_event_grp5_qos_link_speed *)evt);
 255         break;
 256         case ASYNC_EVENT_PVID_STATE:
 257                 be_async_grp5_pvid_state_process(adapter,
 258                 (struct be_async_event_grp5_pvid_state *)evt);
 259         break;
 260         default:
 261                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 262                 break;
 263         }
 264 }
 265
 266 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 267                 u32 trailer, struct be_mcc_compl *cmp)
 268 {
 269         u8 event_type = 0;
 270         struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
 271
 272         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 273                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 274
 275         switch (event_type) {
 276         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 277                 if (evt->valid)
 278                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 279                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 280         break;
 281         default:
 282                 dev_warn(&adapter->pdev->dev, "Unknown debug event\n");
 283         break;
 284         }
 285 }
 286
 287 static inline bool is_link_state_evt(u32 trailer)
 288 {
 289         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 290                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 291                                 ASYNC_EVENT_CODE_LINK_STATE;
 292 }
 293
 294 static inline bool is_grp5_evt(u32 trailer)
 295 {
 296         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 297                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 298                                 ASYNC_EVENT_CODE_GRP_5);
 299 }
 300
 301 static inline bool is_dbg_evt(u32 trailer)
 302 {
 303         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 304                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 305                                 ASYNC_EVENT_CODE_QNQ);
 306 }
 307
 308 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 309 {
 310         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 311         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 312
 313         if (be_mcc_compl_is_new(compl)) {
 314                 queue_tail_inc(mcc_cq);
 315                 return compl;
 316         }
 317         return NULL;
 318 }
 319
 320 void be_async_mcc_enable(struct be_adapter *adapter)
 321 {
 322         spin_lock_bh(&adapter->mcc_cq_lock);
 323
 324         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 325         adapter->mcc_obj.rearm_cq = true;
 326
 327         spin_unlock_bh(&adapter->mcc_cq_lock);
 328 }
 329
 330 void be_async_mcc_disable(struct be_adapter *adapter)
 331 {
 332         spin_lock_bh(&adapter->mcc_cq_lock);
 333
 334         adapter->mcc_obj.rearm_cq = false;
 335         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 336
 337         spin_unlock_bh(&adapter->mcc_cq_lock);
 338 }
 339
 340 int be_process_mcc(struct be_adapter *adapter)
 341 {
 342         struct be_mcc_compl *compl;
 343         int num = 0, status = 0;
 344         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 345
 346         spin_lock(&adapter->mcc_cq_lock);
 347         while ((compl = be_mcc_compl_get(adapter))) {
 348                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 349                         /* Interpret flags as an async trailer */
 350                         if (is_link_state_evt(compl->flags))
 351                                 be_async_link_state_process(adapter,
 352                                 (struct be_async_event_link_state *) compl);
 353                         else if (is_grp5_evt(compl->flags))
 354                                 be_async_grp5_evt_process(adapter,
 355                                 compl->flags, compl);
 356                         else if (is_dbg_evt(compl->flags))
 357                                 be_async_dbg_evt_process(adapter,
 358                                 compl->flags, compl);
 359                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 360                                 status = be_mcc_compl_process(adapter, compl);
 361                                 atomic_dec(&mcc_obj->q.used);
 362                 }
 363                 be_mcc_compl_use(compl);
 364                 num++;
 365         }
 366
 367         if (num)
 368                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 369
 370         spin_unlock(&adapter->mcc_cq_lock);
 371         return status;
 372 }
 373
 374 /* Wait till no more pending mcc requests are present */
 375 static int be_mcc_wait_compl(struct be_adapter *adapter)
 376 {
 377 #define mcc_timeout             120000 /* 12s timeout */
 378         int i, status = 0;
 379         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 380
 381         for (i = 0; i < mcc_timeout; i++) {
 382                 if (be_error(adapter))
 383                         return -EIO;
 384
 385                 local_bh_disable();
 386                 status = be_process_mcc(adapter);
 387                 local_bh_enable();
 388
 389                 if (atomic_read(&mcc_obj->q.used) == 0)
 390                         break;
 391                 udelay(100);
 392         }
 393         if (i == mcc_timeout) {
 394                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 395                 adapter->fw_timeout = true;
 396                 return -EIO;
 397         }
 398         return status;
 399 }
 400
 401 /* Notify MCC requests and wait for completion */
 402 static int be_mcc_notify_wait(struct be_adapter *adapter)
 403 {
 404         int status;
 405         struct be_mcc_wrb *wrb;
 406         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 407         u16 index = mcc_obj->q.head;
 408         struct be_cmd_resp_hdr *resp;
 409
 410         index_dec(&index, mcc_obj->q.len);
 411         wrb = queue_index_node(&mcc_obj->q, index);
 412
 413         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 414
 415         be_mcc_notify(adapter);
 416
 417         status = be_mcc_wait_compl(adapter);
 418         if (status == -EIO)
 419                 goto out;
 420
 421         status = resp->status;
 422 out:
 423         return status;
 424 }
 425
 426 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 427 {
 428         int msecs = 0;
 429         u32 ready;
 430
 431         do {
 432                 if (be_error(adapter))
 433                         return -EIO;
 434
 435                 ready = ioread32(db);
 436                 if (ready == 0xffffffff)
 437                         return -1;
 438
 439                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 440                 if (ready)
 441                         break;
 442
 443                 if (msecs > 4000) {
 444                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 445                         adapter->fw_timeout = true;
 446                         be_detect_error(adapter);
 447                         return -1;
 448                 }
 449
 450                 msleep(1);
 451                 msecs++;
 452         } while (true);
 453
 454         return 0;
 455 }
 456
 457 /*
 458  * Insert the mailbox address into the doorbell in two steps
 459  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 460  */
 461 static int be_mbox_notify_wait(struct be_adapter *adapter)
 462 {
 463         int status;
 464         u32 val = 0;
 465         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 466         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 467         struct be_mcc_mailbox *mbox = mbox_mem->va;
 468         struct be_mcc_compl *compl = &mbox->compl;
 469
 470         /* wait for ready to be set */
 471         status = be_mbox_db_ready_wait(adapter, db);
 472         if (status != 0)
 473                 return status;
 474
 475         val |= MPU_MAILBOX_DB_HI_MASK;
 476         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 477         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 478         iowrite32(val, db);
 479
 480         /* wait for ready to be set */
 481         status = be_mbox_db_ready_wait(adapter, db);
 482         if (status != 0)
 483                 return status;
 484
 485         val = 0;
 486         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 487         val |= (u32)(mbox_mem->dma >> 4) << 2;
 488         iowrite32(val, db);
 489
 490         status = be_mbox_db_ready_wait(adapter, db);
 491         if (status != 0)
 492                 return status;
 493
 494         /* A cq entry has been made now */
 495         if (be_mcc_compl_is_new(compl)) {
 496                 status = be_mcc_compl_process(adapter, &mbox->compl);
 497                 be_mcc_compl_use(compl);
 498                 if (status)
 499                         return status;
 500         } else {
 501                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 502                 return -1;
 503         }
 504         return 0;
 505 }
 506
 507 static u16 be_POST_stage_get(struct be_adapter *adapter)
 508 {
 509         u32 sem;
 510
 511         if (BEx_chip(adapter))
 512                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 513         else
 514                 pci_read_config_dword(adapter->pdev,
 515                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 516
 517         return sem & POST_STAGE_MASK;
 518 }
 519
 520 int lancer_wait_ready(struct be_adapter *adapter)
 521 {
 522 #define SLIPORT_READY_TIMEOUT 30
 523         u32 sliport_status;
 524         int status = 0, i;
 525
 526         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 527                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 528                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 529                         break;
 530
 531                 msleep(1000);
 532         }
 533
 534         if (i == SLIPORT_READY_TIMEOUT)
 535                 status = -1;
 536
 537         return status;
 538 }
 539
 540 static bool lancer_provisioning_error(struct be_adapter *adapter)
 541 {
 542         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 543         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 544         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 545                 sliport_err1 = ioread32(adapter->db +
 546                                         SLIPORT_ERROR1_OFFSET);
 547                 sliport_err2 = ioread32(adapter->db +
 548                                         SLIPORT_ERROR2_OFFSET);
 549
 550                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 551                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 552                         return true;
 553         }
 554         return false;
 555 }
 556
 557 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 558 {
 559         int status;
 560         u32 sliport_status, err, reset_needed;
 561         bool resource_error;
 562
 563         resource_error = lancer_provisioning_error(adapter);
 564         if (resource_error)
 565                 return -1;
 566
 567         status = lancer_wait_ready(adapter);
 568         if (!status) {
 569                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 570                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 571                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 572                 if (err && reset_needed) {
 573                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 574                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 575
 576                         /* check adapter has corrected the error */
 577                         status = lancer_wait_ready(adapter);
 578                         sliport_status = ioread32(adapter->db +
 579                                                   SLIPORT_STATUS_OFFSET);
 580                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 581                                                 SLIPORT_STATUS_RN_MASK);
 582                         if (status || sliport_status)
 583                                 status = -1;
 584                 } else if (err || reset_needed) {
 585                         status = -1;
 586                 }
 587         }
 588         /* Stop error recovery if error is not recoverable.
 589          * No resource error is temporary errors and will go away
 590          * when PF provisions resources.
 591          */
 592         resource_error = lancer_provisioning_error(adapter);
 593         if (status == -1 && !resource_error)
 594                 adapter->eeh_error = true;
 595
 596         return status;
 597 }
 598
 599 int be_fw_wait_ready(struct be_adapter *adapter)
 600 {
 601         u16 stage;
 602         int status, timeout = 0;
 603         struct device *dev = &adapter->pdev->dev;
 604
 605         if (lancer_chip(adapter)) {
 606                 status = lancer_wait_ready(adapter);
 607                 return status;
 608         }
 609
 610         do {
 611                 stage = be_POST_stage_get(adapter);
 612                 if (stage == POST_STAGE_ARMFW_RDY)
 613                         return 0;
 614
 615                 dev_info(dev, "Waiting for POST, %ds elapsed\n",
 616                          timeout);
 617                 if (msleep_interruptible(2000)) {
 618                         dev_err(dev, "Waiting for POST aborted\n");
 619                         return -EINTR;
 620                 }
 621                 timeout += 2;
 622         } while (timeout < 60);
 623
 624         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 625         return -1;
 626 }
 627
 628
 629 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 630 {
 631         return &wrb->payload.sgl[0];
 632 }
 633
 634
 635 /* Don't touch the hdr after it's prepared */
 636 /* mem will be NULL for embedded commands */
 637 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 638                                 u8 subsystem, u8 opcode, int cmd_len,
 639                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 640 {
 641         struct be_sge *sge;
 642         unsigned long addr = (unsigned long)req_hdr;
 643         u64 req_addr = addr;
 644
 645         req_hdr->opcode = opcode;
 646         req_hdr->subsystem = subsystem;
 647         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 648         req_hdr->version = 0;
 649
 650         wrb->tag0 = req_addr & 0xFFFFFFFF;
 651         wrb->tag1 = upper_32_bits(req_addr);
 652
 653         wrb->payload_length = cmd_len;
 654         if (mem) {
 655                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 656                         MCC_WRB_SGE_CNT_SHIFT;
 657                 sge = nonembedded_sgl(wrb);
 658                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 659                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 660                 sge->len = cpu_to_le32(mem->size);
 661         } else
 662                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 663         be_dws_cpu_to_le(wrb, 8);
 664 }
 665
 666 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 667                         struct be_dma_mem *mem)
 668 {
 669         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 670         u64 dma = (u64)mem->dma;
 671
 672         for (i = 0; i < buf_pages; i++) {
 673                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 674                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 675                 dma += PAGE_SIZE_4K;
 676         }
 677 }
 678
 679 /* Converts interrupt delay in microseconds to multiplier value */
 680 static u32 eq_delay_to_mult(u32 usec_delay)
 681 {
 682 #define MAX_INTR_RATE                   651042
 683         const u32 round = 10;
 684         u32 multiplier;
 685
 686         if (usec_delay == 0)
 687                 multiplier = 0;
 688         else {
 689                 u32 interrupt_rate = 1000000 / usec_delay;
 690                 /* Max delay, corresponding to the lowest interrupt rate */
 691                 if (interrupt_rate == 0)
 692                         multiplier = 1023;
 693                 else {
 694                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 695                         multiplier /= interrupt_rate;
 696                         /* Round the multiplier to the closest value.*/
 697                         multiplier = (multiplier + round/2) / round;
 698                         multiplier = min(multiplier, (u32)1023);
 699                 }
 700         }
 701         return multiplier;
 702 }
 703
 704 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 705 {
 706         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 707         struct be_mcc_wrb *wrb
 708                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 709         memset(wrb, 0, sizeof(*wrb));
 710         return wrb;
 711 }
 712
 713 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 714 {
 715         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 716         struct be_mcc_wrb *wrb;
 717
 718         if (!mccq->created)
 719                 return NULL;
 720
 721         if (atomic_read(&mccq->used) >= mccq->len)
 722                 return NULL;
 723
 724         wrb = queue_head_node(mccq);
 725         queue_head_inc(mccq);
 726         atomic_inc(&mccq->used);
 727         memset(wrb, 0, sizeof(*wrb));
 728         return wrb;
 729 }
 730
 731 /* Tell fw we're about to start firing cmds by writing a
 732  * special pattern across the wrb hdr; uses mbox
 733  */
 734 int be_cmd_fw_init(struct be_adapter *adapter)
 735 {
 736         u8 *wrb;
 737         int status;
 738
 739         if (lancer_chip(adapter))
 740                 return 0;
 741
 742         if (mutex_lock_interruptible(&adapter->mbox_lock))
 743                 return -1;
 744
 745         wrb = (u8 *)wrb_from_mbox(adapter);
 746         *wrb++ = 0xFF;
 747         *wrb++ = 0x12;
 748         *wrb++ = 0x34;
 749         *wrb++ = 0xFF;
 750         *wrb++ = 0xFF;
 751         *wrb++ = 0x56;
 752         *wrb++ = 0x78;
 753         *wrb = 0xFF;
 754
 755         status = be_mbox_notify_wait(adapter);
 756
 757         mutex_unlock(&adapter->mbox_lock);
 758         return status;
 759 }
 760
 761 /* Tell fw we're done with firing cmds by writing a
 762  * special pattern across the wrb hdr; uses mbox
 763  */
 764 int be_cmd_fw_clean(struct be_adapter *adapter)
 765 {
 766         u8 *wrb;
 767         int status;
 768
 769         if (lancer_chip(adapter))
 770                 return 0;
 771
 772         if (mutex_lock_interruptible(&adapter->mbox_lock))
 773                 return -1;
 774
 775         wrb = (u8 *)wrb_from_mbox(adapter);
 776         *wrb++ = 0xFF;
 777         *wrb++ = 0xAA;
 778         *wrb++ = 0xBB;
 779         *wrb++ = 0xFF;
 780         *wrb++ = 0xFF;
 781         *wrb++ = 0xCC;
 782         *wrb++ = 0xDD;
 783         *wrb = 0xFF;
 784
 785         status = be_mbox_notify_wait(adapter);
 786
 787         mutex_unlock(&adapter->mbox_lock);
 788         return status;
 789 }
 790
 791 int be_cmd_eq_create(struct be_adapter *adapter,
 792                 struct be_queue_info *eq, int eq_delay)
 793 {
 794         struct be_mcc_wrb *wrb;
 795         struct be_cmd_req_eq_create *req;
 796         struct be_dma_mem *q_mem = &eq->dma_mem;
 797         int status;
 798
 799         if (mutex_lock_interruptible(&adapter->mbox_lock))
 800                 return -1;
 801
 802         wrb = wrb_from_mbox(adapter);
 803         req = embedded_payload(wrb);
 804
 805         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 806                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 807
 808         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 809
 810         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 811         /* 4byte eqe*/
 812         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 813         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 814                         __ilog2_u32(eq->len/256));
 815         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 816                         eq_delay_to_mult(eq_delay));
 817         be_dws_cpu_to_le(req->context, sizeof(req->context));
 818
 819         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 820
 821         status = be_mbox_notify_wait(adapter);
 822         if (!status) {
 823                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 824                 eq->id = le16_to_cpu(resp->eq_id);
 825                 eq->created = true;
 826         }
 827
 828         mutex_unlock(&adapter->mbox_lock);
 829         return status;
 830 }
 831
 832 /* Use MCC */
 833 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 834                           bool permanent, u32 if_handle, u32 pmac_id)
 835 {
 836         struct be_mcc_wrb *wrb;
 837         struct be_cmd_req_mac_query *req;
 838         int status;
 839
 840         spin_lock_bh(&adapter->mcc_lock);
 841
 842         wrb = wrb_from_mccq(adapter);
 843         if (!wrb) {
 844                 status = -EBUSY;
 845                 goto err;
 846         }
 847         req = embedded_payload(wrb);
 848
 849         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 850                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 851         req->type = MAC_ADDRESS_TYPE_NETWORK;
 852         if (permanent) {
 853                 req->permanent = 1;
 854         } else {
 855                 req->if_id = cpu_to_le16((u16) if_handle);
 856                 req->pmac_id = cpu_to_le32(pmac_id);
 857                 req->permanent = 0;
 858         }
 859
 860         status = be_mcc_notify_wait(adapter);
 861         if (!status) {
 862                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 863                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 864         }
 865
 866 err:
 867         spin_unlock_bh(&adapter->mcc_lock);
 868         return status;
 869 }
 870
 871 /* Uses synchronous MCCQ */
 872 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 873                 u32 if_id, u32 *pmac_id, u32 domain)
 874 {
 875         struct be_mcc_wrb *wrb;
 876         struct be_cmd_req_pmac_add *req;
 877         int status;
 878
 879         spin_lock_bh(&adapter->mcc_lock);
 880
 881         wrb = wrb_from_mccq(adapter);
 882         if (!wrb) {
 883                 status = -EBUSY;
 884                 goto err;
 885         }
 886         req = embedded_payload(wrb);
 887
 888         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 889                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 890
 891         req->hdr.domain = domain;
 892         req->if_id = cpu_to_le32(if_id);
 893         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 894
 895         status = be_mcc_notify_wait(adapter);
 896         if (!status) {
 897                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 898                 *pmac_id = le32_to_cpu(resp->pmac_id);
 899         }
 900
 901 err:
 902         spin_unlock_bh(&adapter->mcc_lock);
 903
 904          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 905                 status = -EPERM;
 906
 907         return status;
 908 }
 909
 910 /* Uses synchronous MCCQ */
 911 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 912 {
 913         struct be_mcc_wrb *wrb;
 914         struct be_cmd_req_pmac_del *req;
 915         int status;
 916
 917         if (pmac_id == -1)
 918                 return 0;
 919
 920         spin_lock_bh(&adapter->mcc_lock);
 921
 922         wrb = wrb_from_mccq(adapter);
 923         if (!wrb) {
 924                 status = -EBUSY;
 925                 goto err;
 926         }
 927         req = embedded_payload(wrb);
 928
 929         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 930                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 931
 932         req->hdr.domain = dom;
 933         req->if_id = cpu_to_le32(if_id);
 934         req->pmac_id = cpu_to_le32(pmac_id);
 935
 936         status = be_mcc_notify_wait(adapter);
 937
 938 err:
 939         spin_unlock_bh(&adapter->mcc_lock);
 940         return status;
 941 }
 942
 943 /* Uses Mbox */
 944 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
 945                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
 946 {
 947         struct be_mcc_wrb *wrb;
 948         struct be_cmd_req_cq_create *req;
 949         struct be_dma_mem *q_mem = &cq->dma_mem;
 950         void *ctxt;
 951         int status;
 952
 953         if (mutex_lock_interruptible(&adapter->mbox_lock))
 954                 return -1;
 955
 956         wrb = wrb_from_mbox(adapter);
 957         req = embedded_payload(wrb);
 958         ctxt = &req->context;
 959
 960         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 961                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 962
 963         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 964         if (lancer_chip(adapter)) {
 965                 req->hdr.version = 2;
 966                 req->page_size = 1; /* 1 for 4K */
 967                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 968                                                                 no_delay);
 969                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 970                                                 __ilog2_u32(cq->len/256));
 971                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 972                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 973                                                                 ctxt, 1);
 974                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 975                                                                 ctxt, eq->id);
 976         } else {
 977                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 978                                                                 coalesce_wm);
 979                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 980                                                                 ctxt, no_delay);
 981                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 982                                                 __ilog2_u32(cq->len/256));
 983                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 984                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 985                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 986         }
 987
 988         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 989
 990         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 991
 992         status = be_mbox_notify_wait(adapter);
 993         if (!status) {
 994                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 995                 cq->id = le16_to_cpu(resp->cq_id);
 996                 cq->created = true;
 997         }
 998
 999         mutex_unlock(&adapter->mbox_lock);
1000
1001         return status;
1002 }
1003
1004 static u32 be_encoded_q_len(int q_len)
1005 {
1006         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1007         if (len_encoded == 16)
1008                 len_encoded = 0;
1009         return len_encoded;
1010 }
1011
1012 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1013                         struct be_queue_info *mccq,
1014                         struct be_queue_info *cq)
1015 {
1016         struct be_mcc_wrb *wrb;
1017         struct be_cmd_req_mcc_ext_create *req;
1018         struct be_dma_mem *q_mem = &mccq->dma_mem;
1019         void *ctxt;
1020         int status;
1021
1022         if (mutex_lock_interruptible(&adapter->mbox_lock))
1023                 return -1;
1024
1025         wrb = wrb_from_mbox(adapter);
1026         req = embedded_payload(wrb);
1027         ctxt = &req->context;
1028
1029         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1030                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1031
1032         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1033         if (lancer_chip(adapter)) {
1034                 req->hdr.version = 1;
1035                 req->cq_id = cpu_to_le16(cq->id);
1036
1037                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1038                                                 be_encoded_q_len(mccq->len));
1039                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1040                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1041                                                                 ctxt, cq->id);
1042                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1043                                                                  ctxt, 1);
1044
1045         } else {
1046                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1047                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1048                                                 be_encoded_q_len(mccq->len));
1049                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1050         }
1051
1052         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1053         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1054         req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1055         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1056
1057         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1058
1059         status = be_mbox_notify_wait(adapter);
1060         if (!status) {
1061                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1062                 mccq->id = le16_to_cpu(resp->id);
1063                 mccq->created = true;
1064         }
1065         mutex_unlock(&adapter->mbox_lock);
1066
1067         return status;
1068 }
1069
1070 int be_cmd_mccq_org_create(struct be_adapter *adapter,
1071                         struct be_queue_info *mccq,
1072                         struct be_queue_info *cq)
1073 {
1074         struct be_mcc_wrb *wrb;
1075         struct be_cmd_req_mcc_create *req;
1076         struct be_dma_mem *q_mem = &mccq->dma_mem;
1077         void *ctxt;
1078         int status;
1079
1080         if (mutex_lock_interruptible(&adapter->mbox_lock))
1081                 return -1;
1082
1083         wrb = wrb_from_mbox(adapter);
1084         req = embedded_payload(wrb);
1085         ctxt = &req->context;
1086
1087         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1088                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1089
1090         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1091
1092         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1093         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1094                         be_encoded_q_len(mccq->len));
1095         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1096
1097         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1098
1099         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1100
1101         status = be_mbox_notify_wait(adapter);
1102         if (!status) {
1103                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1104                 mccq->id = le16_to_cpu(resp->id);
1105                 mccq->created = true;
1106         }
1107
1108         mutex_unlock(&adapter->mbox_lock);
1109         return status;
1110 }
1111
1112 int be_cmd_mccq_create(struct be_adapter *adapter,
1113                         struct be_queue_info *mccq,
1114                         struct be_queue_info *cq)
1115 {
1116         int status;
1117
1118         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1119         if (status && !lancer_chip(adapter)) {
1120                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1121                         "or newer to avoid conflicting priorities between NIC "
1122                         "and FCoE traffic");
1123                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1124         }
1125         return status;
1126 }
1127
1128 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1129 {
1130         struct be_mcc_wrb *wrb;
1131         struct be_cmd_req_eth_tx_create *req;
1132         struct be_queue_info *txq = &txo->q;
1133         struct be_queue_info *cq = &txo->cq;
1134         struct be_dma_mem *q_mem = &txq->dma_mem;
1135         int status, ver = 0;
1136
1137         spin_lock_bh(&adapter->mcc_lock);
1138
1139         wrb = wrb_from_mccq(adapter);
1140         if (!wrb) {
1141                 status = -EBUSY;
1142                 goto err;
1143         }
1144
1145         req = embedded_payload(wrb);
1146
1147         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1148                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1149
1150         if (lancer_chip(adapter)) {
1151                 req->hdr.version = 1;
1152                 req->if_id = cpu_to_le16(adapter->if_handle);
1153         } else if (BEx_chip(adapter)) {
1154                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1155                         req->hdr.version = 2;
1156         } else { /* For SH */
1157                 req->hdr.version = 2;
1158         }
1159
1160         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1161         req->ulp_num = BE_ULP1_NUM;
1162         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1163         req->cq_id = cpu_to_le16(cq->id);
1164         req->queue_size = be_encoded_q_len(txq->len);
1165         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1166
1167         ver = req->hdr.version;
1168
1169         status = be_mcc_notify_wait(adapter);
1170         if (!status) {
1171                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1172                 txq->id = le16_to_cpu(resp->cid);
1173                 if (ver == 2)
1174                         txo->db_offset = le32_to_cpu(resp->db_offset);
1175                 else
1176                         txo->db_offset = DB_TXULP1_OFFSET;
1177                 txq->created = true;
1178         }
1179
1180 err:
1181         spin_unlock_bh(&adapter->mcc_lock);
1182
1183         return status;
1184 }
1185
1186 /* Uses MCC */
1187 int be_cmd_rxq_create(struct be_adapter *adapter,
1188                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1189                 u32 if_id, u32 rss, u8 *rss_id)
1190 {
1191         struct be_mcc_wrb *wrb;
1192         struct be_cmd_req_eth_rx_create *req;
1193         struct be_dma_mem *q_mem = &rxq->dma_mem;
1194         int status;
1195
1196         spin_lock_bh(&adapter->mcc_lock);
1197
1198         wrb = wrb_from_mccq(adapter);
1199         if (!wrb) {
1200                 status = -EBUSY;
1201                 goto err;
1202         }
1203         req = embedded_payload(wrb);
1204
1205         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1206                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1207
1208         req->cq_id = cpu_to_le16(cq_id);
1209         req->frag_size = fls(frag_size) - 1;
1210         req->num_pages = 2;
1211         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1212         req->interface_id = cpu_to_le32(if_id);
1213         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1214         req->rss_queue = cpu_to_le32(rss);
1215
1216         status = be_mcc_notify_wait(adapter);
1217         if (!status) {
1218                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1219                 rxq->id = le16_to_cpu(resp->id);
1220                 rxq->created = true;
1221                 *rss_id = resp->rss_id;
1222         }
1223
1224 err:
1225         spin_unlock_bh(&adapter->mcc_lock);
1226         return status;
1227 }
1228
1229 /* Generic destroyer function for all types of queues
1230  * Uses Mbox
1231  */
1232 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1233                 int queue_type)
1234 {
1235         struct be_mcc_wrb *wrb;
1236         struct be_cmd_req_q_destroy *req;
1237         u8 subsys = 0, opcode = 0;
1238         int status;
1239
1240         if (mutex_lock_interruptible(&adapter->mbox_lock))
1241                 return -1;
1242
1243         wrb = wrb_from_mbox(adapter);
1244         req = embedded_payload(wrb);
1245
1246         switch (queue_type) {
1247         case QTYPE_EQ:
1248                 subsys = CMD_SUBSYSTEM_COMMON;
1249                 opcode = OPCODE_COMMON_EQ_DESTROY;
1250                 break;
1251         case QTYPE_CQ:
1252                 subsys = CMD_SUBSYSTEM_COMMON;
1253                 opcode = OPCODE_COMMON_CQ_DESTROY;
1254                 break;
1255         case QTYPE_TXQ:
1256                 subsys = CMD_SUBSYSTEM_ETH;
1257                 opcode = OPCODE_ETH_TX_DESTROY;
1258                 break;
1259         case QTYPE_RXQ:
1260                 subsys = CMD_SUBSYSTEM_ETH;
1261                 opcode = OPCODE_ETH_RX_DESTROY;
1262                 break;
1263         case QTYPE_MCCQ:
1264                 subsys = CMD_SUBSYSTEM_COMMON;
1265                 opcode = OPCODE_COMMON_MCC_DESTROY;
1266                 break;
1267         default:
1268                 BUG();
1269         }
1270
1271         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1272                                 NULL);
1273         req->id = cpu_to_le16(q->id);
1274
1275         status = be_mbox_notify_wait(adapter);
1276         q->created = false;
1277
1278         mutex_unlock(&adapter->mbox_lock);
1279         return status;
1280 }
1281
1282 /* Uses MCC */
1283 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1284 {
1285         struct be_mcc_wrb *wrb;
1286         struct be_cmd_req_q_destroy *req;
1287         int status;
1288
1289         spin_lock_bh(&adapter->mcc_lock);
1290
1291         wrb = wrb_from_mccq(adapter);
1292         if (!wrb) {
1293                 status = -EBUSY;
1294                 goto err;
1295         }
1296         req = embedded_payload(wrb);
1297
1298         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1299                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1300         req->id = cpu_to_le16(q->id);
1301
1302         status = be_mcc_notify_wait(adapter);
1303         q->created = false;
1304
1305 err:
1306         spin_unlock_bh(&adapter->mcc_lock);
1307         return status;
1308 }
1309
1310 /* Create an rx filtering policy configuration on an i/f
1311  * Uses MCCQ
1312  */
1313 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1314                      u32 *if_handle, u32 domain)
1315 {
1316         struct be_mcc_wrb *wrb;
1317         struct be_cmd_req_if_create *req;
1318         int status;
1319
1320         spin_lock_bh(&adapter->mcc_lock);
1321
1322         wrb = wrb_from_mccq(adapter);
1323         if (!wrb) {
1324                 status = -EBUSY;
1325                 goto err;
1326         }
1327         req = embedded_payload(wrb);
1328
1329         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1330                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1331         req->hdr.domain = domain;
1332         req->capability_flags = cpu_to_le32(cap_flags);
1333         req->enable_flags = cpu_to_le32(en_flags);
1334
1335         req->pmac_invalid = true;
1336
1337         status = be_mcc_notify_wait(adapter);
1338         if (!status) {
1339                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1340                 *if_handle = le32_to_cpu(resp->interface_id);
1341         }
1342
1343 err:
1344         spin_unlock_bh(&adapter->mcc_lock);
1345         return status;
1346 }
1347
1348 /* Uses MCCQ */
1349 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1350 {
1351         struct be_mcc_wrb *wrb;
1352         struct be_cmd_req_if_destroy *req;
1353         int status;
1354
1355         if (interface_id == -1)
1356                 return 0;
1357
1358         spin_lock_bh(&adapter->mcc_lock);
1359
1360         wrb = wrb_from_mccq(adapter);
1361         if (!wrb) {
1362                 status = -EBUSY;
1363                 goto err;
1364         }
1365         req = embedded_payload(wrb);
1366
1367         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1368                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1369         req->hdr.domain = domain;
1370         req->interface_id = cpu_to_le32(interface_id);
1371
1372         status = be_mcc_notify_wait(adapter);
1373 err:
1374         spin_unlock_bh(&adapter->mcc_lock);
1375         return status;
1376 }
1377
1378 /* Get stats is a non embedded command: the request is not embedded inside
1379  * WRB but is a separate dma memory block
1380  * Uses asynchronous MCC
1381  */
1382 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1383 {
1384         struct be_mcc_wrb *wrb;
1385         struct be_cmd_req_hdr *hdr;
1386         int status = 0;
1387
1388         spin_lock_bh(&adapter->mcc_lock);
1389
1390         wrb = wrb_from_mccq(adapter);
1391         if (!wrb) {
1392                 status = -EBUSY;
1393                 goto err;
1394         }
1395         hdr = nonemb_cmd->va;
1396
1397         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1398                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1399
1400         /* version 1 of the cmd is not supported only by BE2 */
1401         if (!BE2_chip(adapter))
1402                 hdr->version = 1;
1403
1404         be_mcc_notify(adapter);
1405         adapter->stats_cmd_sent = true;
1406
1407 err:
1408         spin_unlock_bh(&adapter->mcc_lock);
1409         return status;
1410 }
1411
1412 /* Lancer Stats */
1413 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1414                                 struct be_dma_mem *nonemb_cmd)
1415 {
1416
1417         struct be_mcc_wrb *wrb;
1418         struct lancer_cmd_req_pport_stats *req;
1419         int status = 0;
1420
1421         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1422                             CMD_SUBSYSTEM_ETH))
1423                 return -EPERM;
1424
1425         spin_lock_bh(&adapter->mcc_lock);
1426
1427         wrb = wrb_from_mccq(adapter);
1428         if (!wrb) {
1429                 status = -EBUSY;
1430                 goto err;
1431         }
1432         req = nonemb_cmd->va;
1433
1434         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1435                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1436                         nonemb_cmd);
1437
1438         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1439         req->cmd_params.params.reset_stats = 0;
1440
1441         be_mcc_notify(adapter);
1442         adapter->stats_cmd_sent = true;
1443
1444 err:
1445         spin_unlock_bh(&adapter->mcc_lock);
1446         return status;
1447 }
1448
1449 static int be_mac_to_link_speed(int mac_speed)
1450 {
1451         switch (mac_speed) {
1452         case PHY_LINK_SPEED_ZERO:
1453                 return 0;
1454         case PHY_LINK_SPEED_10MBPS:
1455                 return 10;
1456         case PHY_LINK_SPEED_100MBPS:
1457                 return 100;
1458         case PHY_LINK_SPEED_1GBPS:
1459                 return 1000;
1460         case PHY_LINK_SPEED_10GBPS:
1461                 return 10000;
1462         }
1463         return 0;
1464 }
1465
1466 /* Uses synchronous mcc
1467  * Returns link_speed in Mbps
1468  */
1469 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1470                              u8 *link_status, u32 dom)
1471 {
1472         struct be_mcc_wrb *wrb;
1473         struct be_cmd_req_link_status *req;
1474         int status;
1475
1476         spin_lock_bh(&adapter->mcc_lock);
1477
1478         if (link_status)
1479                 *link_status = LINK_DOWN;
1480
1481         wrb = wrb_from_mccq(adapter);
1482         if (!wrb) {
1483                 status = -EBUSY;
1484                 goto err;
1485         }
1486         req = embedded_payload(wrb);
1487
1488         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1489                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1490
1491         /* version 1 of the cmd is not supported only by BE2 */
1492         if (!BE2_chip(adapter))
1493                 req->hdr.version = 1;
1494
1495         req->hdr.domain = dom;
1496
1497         status = be_mcc_notify_wait(adapter);
1498         if (!status) {
1499                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1500                 if (link_speed) {
1501                         *link_speed = resp->link_speed ?
1502                                       le16_to_cpu(resp->link_speed) * 10 :
1503                                       be_mac_to_link_speed(resp->mac_speed);
1504
1505                         if (!resp->logical_link_status)
1506                                 *link_speed = 0;
1507                 }
1508                 if (link_status)
1509                         *link_status = resp->logical_link_status;
1510         }
1511
1512 err:
1513         spin_unlock_bh(&adapter->mcc_lock);
1514         return status;
1515 }
1516
1517 /* Uses synchronous mcc */
1518 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1519 {
1520         struct be_mcc_wrb *wrb;
1521         struct be_cmd_req_get_cntl_addnl_attribs *req;
1522         int status;
1523
1524         spin_lock_bh(&adapter->mcc_lock);
1525
1526         wrb = wrb_from_mccq(adapter);
1527         if (!wrb) {
1528                 status = -EBUSY;
1529                 goto err;
1530         }
1531         req = embedded_payload(wrb);
1532
1533         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1534                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1535                 wrb, NULL);
1536
1537         be_mcc_notify(adapter);
1538
1539 err:
1540         spin_unlock_bh(&adapter->mcc_lock);
1541         return status;
1542 }
1543
1544 /* Uses synchronous mcc */
1545 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1546 {
1547         struct be_mcc_wrb *wrb;
1548         struct be_cmd_req_get_fat *req;
1549         int status;
1550
1551         spin_lock_bh(&adapter->mcc_lock);
1552
1553         wrb = wrb_from_mccq(adapter);
1554         if (!wrb) {
1555                 status = -EBUSY;
1556                 goto err;
1557         }
1558         req = embedded_payload(wrb);
1559
1560         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1561                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1562         req->fat_operation = cpu_to_le32(QUERY_FAT);
1563         status = be_mcc_notify_wait(adapter);
1564         if (!status) {
1565                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1566                 if (log_size && resp->log_size)
1567                         *log_size = le32_to_cpu(resp->log_size) -
1568                                         sizeof(u32);
1569         }
1570 err:
1571         spin_unlock_bh(&adapter->mcc_lock);
1572         return status;
1573 }
1574
1575 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1576 {
1577         struct be_dma_mem get_fat_cmd;
1578         struct be_mcc_wrb *wrb;
1579         struct be_cmd_req_get_fat *req;
1580         u32 offset = 0, total_size, buf_size,
1581                                 log_offset = sizeof(u32), payload_len;
1582         int status;
1583
1584         if (buf_len == 0)
1585                 return;
1586
1587         total_size = buf_len;
1588
1589         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1590         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1591                         get_fat_cmd.size,
1592                         &get_fat_cmd.dma);
1593         if (!get_fat_cmd.va) {
1594                 status = -ENOMEM;
1595                 dev_err(&adapter->pdev->dev,
1596                 "Memory allocation failure while retrieving FAT data\n");
1597                 return;
1598         }
1599
1600         spin_lock_bh(&adapter->mcc_lock);
1601
1602         while (total_size) {
1603                 buf_size = min(total_size, (u32)60*1024);
1604                 total_size -= buf_size;
1605
1606                 wrb = wrb_from_mccq(adapter);
1607                 if (!wrb) {
1608                         status = -EBUSY;
1609                         goto err;
1610                 }
1611                 req = get_fat_cmd.va;
1612
1613                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1614                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1615                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1616                                 &get_fat_cmd);
1617
1618                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1619                 req->read_log_offset = cpu_to_le32(log_offset);
1620                 req->read_log_length = cpu_to_le32(buf_size);
1621                 req->data_buffer_size = cpu_to_le32(buf_size);
1622
1623                 status = be_mcc_notify_wait(adapter);
1624                 if (!status) {
1625                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1626                         memcpy(buf + offset,
1627                                 resp->data_buffer,
1628                                 le32_to_cpu(resp->read_log_length));
1629                 } else {
1630                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1631                         goto err;
1632                 }
1633                 offset += buf_size;
1634                 log_offset += buf_size;
1635         }
1636 err:
1637         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1638                         get_fat_cmd.va,
1639                         get_fat_cmd.dma);
1640         spin_unlock_bh(&adapter->mcc_lock);
1641 }
1642
1643 /* Uses synchronous mcc */
1644 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1645                         char *fw_on_flash)
1646 {
1647         struct be_mcc_wrb *wrb;
1648         struct be_cmd_req_get_fw_version *req;
1649         int status;
1650
1651         spin_lock_bh(&adapter->mcc_lock);
1652
1653         wrb = wrb_from_mccq(adapter);
1654         if (!wrb) {
1655                 status = -EBUSY;
1656                 goto err;
1657         }
1658
1659         req = embedded_payload(wrb);
1660
1661         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1662                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1663         status = be_mcc_notify_wait(adapter);
1664         if (!status) {
1665                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1666                 strcpy(fw_ver, resp->firmware_version_string);
1667                 if (fw_on_flash)
1668                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1669         }
1670 err:
1671         spin_unlock_bh(&adapter->mcc_lock);
1672         return status;
1673 }
1674
1675 /* set the EQ delay interval of an EQ to specified value
1676  * Uses async mcc
1677  */
1678 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1679 {
1680         struct be_mcc_wrb *wrb;
1681         struct be_cmd_req_modify_eq_delay *req;
1682         int status = 0;
1683
1684         spin_lock_bh(&adapter->mcc_lock);
1685
1686         wrb = wrb_from_mccq(adapter);
1687         if (!wrb) {
1688                 status = -EBUSY;
1689                 goto err;
1690         }
1691         req = embedded_payload(wrb);
1692
1693         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1694                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1695
1696         req->num_eq = cpu_to_le32(1);
1697         req->delay[0].eq_id = cpu_to_le32(eq_id);
1698         req->delay[0].phase = 0;
1699         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1700
1701         be_mcc_notify(adapter);
1702
1703 err:
1704         spin_unlock_bh(&adapter->mcc_lock);
1705         return status;
1706 }
1707
1708 /* Uses sycnhronous mcc */
1709 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1710                         u32 num, bool untagged, bool promiscuous)
1711 {
1712         struct be_mcc_wrb *wrb;
1713         struct be_cmd_req_vlan_config *req;
1714         int status;
1715
1716         spin_lock_bh(&adapter->mcc_lock);
1717
1718         wrb = wrb_from_mccq(adapter);
1719         if (!wrb) {
1720                 status = -EBUSY;
1721                 goto err;
1722         }
1723         req = embedded_payload(wrb);
1724
1725         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1726                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1727
1728         req->interface_id = if_id;
1729         req->promiscuous = promiscuous;
1730         req->untagged = untagged;
1731         req->num_vlan = num;
1732         if (!promiscuous) {
1733                 memcpy(req->normal_vlan, vtag_array,
1734                         req->num_vlan * sizeof(vtag_array[0]));
1735         }
1736
1737         status = be_mcc_notify_wait(adapter);
1738
1739 err:
1740         spin_unlock_bh(&adapter->mcc_lock);
1741         return status;
1742 }
1743
1744 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1745 {
1746         struct be_mcc_wrb *wrb;
1747         struct be_dma_mem *mem = &adapter->rx_filter;
1748         struct be_cmd_req_rx_filter *req = mem->va;
1749         int status;
1750
1751         spin_lock_bh(&adapter->mcc_lock);
1752
1753         wrb = wrb_from_mccq(adapter);
1754         if (!wrb) {
1755                 status = -EBUSY;
1756                 goto err;
1757         }
1758         memset(req, 0, sizeof(*req));
1759         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1760                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1761                                 wrb, mem);
1762
1763         req->if_id = cpu_to_le32(adapter->if_handle);
1764         if (flags & IFF_PROMISC) {
1765                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1766                                         BE_IF_FLAGS_VLAN_PROMISCUOUS);
1767                 if (value == ON)
1768                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1769                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1770         } else if (flags & IFF_ALLMULTI) {
1771                 req->if_flags_mask = req->if_flags =
1772                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1773         } else {
1774                 struct netdev_hw_addr *ha;
1775                 int i = 0;
1776
1777                 req->if_flags_mask = req->if_flags =
1778                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1779
1780                 /* Reset mcast promisc mode if already set by setting mask
1781                  * and not setting flags field
1782                  */
1783                 req->if_flags_mask |=
1784                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1785                                     adapter->if_cap_flags);
1786
1787                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1788                 netdev_for_each_mc_addr(ha, adapter->netdev)
1789                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1790         }
1791
1792         status = be_mcc_notify_wait(adapter);
1793 err:
1794         spin_unlock_bh(&adapter->mcc_lock);
1795         return status;
1796 }
1797
1798 /* Uses synchrounous mcc */
1799 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1800 {
1801         struct be_mcc_wrb *wrb;
1802         struct be_cmd_req_set_flow_control *req;
1803         int status;
1804
1805         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1806                             CMD_SUBSYSTEM_COMMON))
1807                 return -EPERM;
1808
1809         spin_lock_bh(&adapter->mcc_lock);
1810
1811         wrb = wrb_from_mccq(adapter);
1812         if (!wrb) {
1813                 status = -EBUSY;
1814                 goto err;
1815         }
1816         req = embedded_payload(wrb);
1817
1818         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1819                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1820
1821         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1822         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1823
1824         status = be_mcc_notify_wait(adapter);
1825
1826 err:
1827         spin_unlock_bh(&adapter->mcc_lock);
1828         return status;
1829 }
1830
1831 /* Uses sycn mcc */
1832 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1833 {
1834         struct be_mcc_wrb *wrb;
1835         struct be_cmd_req_get_flow_control *req;
1836         int status;
1837
1838         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1839                             CMD_SUBSYSTEM_COMMON))
1840                 return -EPERM;
1841
1842         spin_lock_bh(&adapter->mcc_lock);
1843
1844         wrb = wrb_from_mccq(adapter);
1845         if (!wrb) {
1846                 status = -EBUSY;
1847                 goto err;
1848         }
1849         req = embedded_payload(wrb);
1850
1851         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1852                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1853
1854         status = be_mcc_notify_wait(adapter);
1855         if (!status) {
1856                 struct be_cmd_resp_get_flow_control *resp =
1857                                                 embedded_payload(wrb);
1858                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1859                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1860         }
1861
1862 err:
1863         spin_unlock_bh(&adapter->mcc_lock);
1864         return status;
1865 }
1866
1867 /* Uses mbox */
1868 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1869                         u32 *mode, u32 *caps, u16 *asic_rev)
1870 {
1871         struct be_mcc_wrb *wrb;
1872         struct be_cmd_req_query_fw_cfg *req;
1873         int status;
1874
1875         if (mutex_lock_interruptible(&adapter->mbox_lock))
1876                 return -1;
1877
1878         wrb = wrb_from_mbox(adapter);
1879         req = embedded_payload(wrb);
1880
1881         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1882                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1883
1884         status = be_mbox_notify_wait(adapter);
1885         if (!status) {
1886                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1887                 *port_num = le32_to_cpu(resp->phys_port);
1888                 *mode = le32_to_cpu(resp->function_mode);
1889                 *caps = le32_to_cpu(resp->function_caps);
1890                 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1891         }
1892
1893         mutex_unlock(&adapter->mbox_lock);
1894         return status;
1895 }
1896
1897 /* Uses mbox */
1898 int be_cmd_reset_function(struct be_adapter *adapter)
1899 {
1900         struct be_mcc_wrb *wrb;
1901         struct be_cmd_req_hdr *req;
1902         int status;
1903
1904         if (lancer_chip(adapter)) {
1905                 status = lancer_wait_ready(adapter);
1906                 if (!status) {
1907                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1908                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1909                         status = lancer_test_and_set_rdy_state(adapter);
1910                 }
1911                 if (status) {
1912                         dev_err(&adapter->pdev->dev,
1913                                 "Adapter in non recoverable error\n");
1914                 }
1915                 return status;
1916         }
1917
1918         if (mutex_lock_interruptible(&adapter->mbox_lock))
1919                 return -1;
1920
1921         wrb = wrb_from_mbox(adapter);
1922         req = embedded_payload(wrb);
1923
1924         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1925                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1926
1927         status = be_mbox_notify_wait(adapter);
1928
1929         mutex_unlock(&adapter->mbox_lock);
1930         return status;
1931 }
1932
1933 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1934                         u32 rss_hash_opts, u16 table_size)
1935 {
1936         struct be_mcc_wrb *wrb;
1937         struct be_cmd_req_rss_config *req;
1938         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1939                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1940                         0x3ea83c02, 0x4a110304};
1941         int status;
1942
1943         if (mutex_lock_interruptible(&adapter->mbox_lock))
1944                 return -1;
1945
1946         wrb = wrb_from_mbox(adapter);
1947         req = embedded_payload(wrb);
1948
1949         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1950                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1951
1952         req->if_id = cpu_to_le32(adapter->if_handle);
1953         req->enable_rss = cpu_to_le16(rss_hash_opts);
1954         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1955
1956         if (lancer_chip(adapter) || skyhawk_chip(adapter))
1957                 req->hdr.version = 1;
1958
1959         memcpy(req->cpu_table, rsstable, table_size);
1960         memcpy(req->hash, myhash, sizeof(myhash));
1961         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1962
1963         status = be_mbox_notify_wait(adapter);
1964
1965         mutex_unlock(&adapter->mbox_lock);
1966         return status;
1967 }
1968
1969 /* Uses sync mcc */
1970 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1971                         u8 bcn, u8 sts, u8 state)
1972 {
1973         struct be_mcc_wrb *wrb;
1974         struct be_cmd_req_enable_disable_beacon *req;
1975         int status;
1976
1977         spin_lock_bh(&adapter->mcc_lock);
1978
1979         wrb = wrb_from_mccq(adapter);
1980         if (!wrb) {
1981                 status = -EBUSY;
1982                 goto err;
1983         }
1984         req = embedded_payload(wrb);
1985
1986         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1987                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1988
1989         req->port_num = port_num;
1990         req->beacon_state = state;
1991         req->beacon_duration = bcn;
1992         req->status_duration = sts;
1993
1994         status = be_mcc_notify_wait(adapter);
1995
1996 err:
1997         spin_unlock_bh(&adapter->mcc_lock);
1998         return status;
1999 }
2000
2001 /* Uses sync mcc */
2002 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2003 {
2004         struct be_mcc_wrb *wrb;
2005         struct be_cmd_req_get_beacon_state *req;
2006         int status;
2007
2008         spin_lock_bh(&adapter->mcc_lock);
2009
2010         wrb = wrb_from_mccq(adapter);
2011         if (!wrb) {
2012                 status = -EBUSY;
2013                 goto err;
2014         }
2015         req = embedded_payload(wrb);
2016
2017         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2018                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
2019
2020         req->port_num = port_num;
2021
2022         status = be_mcc_notify_wait(adapter);
2023         if (!status) {
2024                 struct be_cmd_resp_get_beacon_state *resp =
2025                                                 embedded_payload(wrb);
2026                 *state = resp->beacon_state;
2027         }
2028
2029 err:
2030         spin_unlock_bh(&adapter->mcc_lock);
2031         return status;
2032 }
2033
2034 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2035                             u32 data_size, u32 data_offset,
2036                             const char *obj_name, u32 *data_written,
2037                             u8 *change_status, u8 *addn_status)
2038 {
2039         struct be_mcc_wrb *wrb;
2040         struct lancer_cmd_req_write_object *req;
2041         struct lancer_cmd_resp_write_object *resp;
2042         void *ctxt = NULL;
2043         int status;
2044
2045         spin_lock_bh(&adapter->mcc_lock);
2046         adapter->flash_status = 0;
2047
2048         wrb = wrb_from_mccq(adapter);
2049         if (!wrb) {
2050                 status = -EBUSY;
2051                 goto err_unlock;
2052         }
2053
2054         req = embedded_payload(wrb);
2055
2056         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2057                                 OPCODE_COMMON_WRITE_OBJECT,
2058                                 sizeof(struct lancer_cmd_req_write_object), wrb,
2059                                 NULL);
2060
2061         ctxt = &req->context;
2062         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2063                         write_length, ctxt, data_size);
2064
2065         if (data_size == 0)
2066                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2067                                 eof, ctxt, 1);
2068         else
2069                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2070                                 eof, ctxt, 0);
2071
2072         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2073         req->write_offset = cpu_to_le32(data_offset);
2074         strcpy(req->object_name, obj_name);
2075         req->descriptor_count = cpu_to_le32(1);
2076         req->buf_len = cpu_to_le32(data_size);
2077         req->addr_low = cpu_to_le32((cmd->dma +
2078                                 sizeof(struct lancer_cmd_req_write_object))
2079                                 & 0xFFFFFFFF);
2080         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2081                                 sizeof(struct lancer_cmd_req_write_object)));
2082
2083         be_mcc_notify(adapter);
2084         spin_unlock_bh(&adapter->mcc_lock);
2085
2086         if (!wait_for_completion_timeout(&adapter->flash_compl,
2087                                          msecs_to_jiffies(30000)))
2088                 status = -1;
2089         else
2090                 status = adapter->flash_status;
2091
2092         resp = embedded_payload(wrb);
2093         if (!status) {
2094                 *data_written = le32_to_cpu(resp->actual_write_len);
2095                 *change_status = resp->change_status;
2096         } else {
2097                 *addn_status = resp->additional_status;
2098         }
2099
2100         return status;
2101
2102 err_unlock:
2103         spin_unlock_bh(&adapter->mcc_lock);
2104         return status;
2105 }
2106
2107 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2108                 u32 data_size, u32 data_offset, const char *obj_name,
2109                 u32 *data_read, u32 *eof, u8 *addn_status)
2110 {
2111         struct be_mcc_wrb *wrb;
2112         struct lancer_cmd_req_read_object *req;
2113         struct lancer_cmd_resp_read_object *resp;
2114         int status;
2115
2116         spin_lock_bh(&adapter->mcc_lock);
2117
2118         wrb = wrb_from_mccq(adapter);
2119         if (!wrb) {
2120                 status = -EBUSY;
2121                 goto err_unlock;
2122         }
2123
2124         req = embedded_payload(wrb);
2125
2126         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2127                         OPCODE_COMMON_READ_OBJECT,
2128                         sizeof(struct lancer_cmd_req_read_object), wrb,
2129                         NULL);
2130
2131         req->desired_read_len = cpu_to_le32(data_size);
2132         req->read_offset = cpu_to_le32(data_offset);
2133         strcpy(req->object_name, obj_name);
2134         req->descriptor_count = cpu_to_le32(1);
2135         req->buf_len = cpu_to_le32(data_size);
2136         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2137         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2138
2139         status = be_mcc_notify_wait(adapter);
2140
2141         resp = embedded_payload(wrb);
2142         if (!status) {
2143                 *data_read = le32_to_cpu(resp->actual_read_len);
2144                 *eof = le32_to_cpu(resp->eof);
2145         } else {
2146                 *addn_status = resp->additional_status;
2147         }
2148
2149 err_unlock:
2150         spin_unlock_bh(&adapter->mcc_lock);
2151         return status;
2152 }
2153
2154 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2155                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2156 {
2157         struct be_mcc_wrb *wrb;
2158         struct be_cmd_write_flashrom *req;
2159         int status;
2160
2161         spin_lock_bh(&adapter->mcc_lock);
2162         adapter->flash_status = 0;
2163
2164         wrb = wrb_from_mccq(adapter);
2165         if (!wrb) {
2166                 status = -EBUSY;
2167                 goto err_unlock;
2168         }
2169         req = cmd->va;
2170
2171         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2172                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2173
2174         req->params.op_type = cpu_to_le32(flash_type);
2175         req->params.op_code = cpu_to_le32(flash_opcode);
2176         req->params.data_buf_size = cpu_to_le32(buf_size);
2177
2178         be_mcc_notify(adapter);
2179         spin_unlock_bh(&adapter->mcc_lock);
2180
2181         if (!wait_for_completion_timeout(&adapter->flash_compl,
2182                         msecs_to_jiffies(40000)))
2183                 status = -1;
2184         else
2185                 status = adapter->flash_status;
2186
2187         return status;
2188
2189 err_unlock:
2190         spin_unlock_bh(&adapter->mcc_lock);
2191         return status;
2192 }
2193
2194 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2195                          int offset)
2196 {
2197         struct be_mcc_wrb *wrb;
2198         struct be_cmd_read_flash_crc *req;
2199         int status;
2200
2201         spin_lock_bh(&adapter->mcc_lock);
2202
2203         wrb = wrb_from_mccq(adapter);
2204         if (!wrb) {
2205                 status = -EBUSY;
2206                 goto err;
2207         }
2208         req = embedded_payload(wrb);
2209
2210         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2211                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2212                                wrb, NULL);
2213
2214         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2215         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2216         req->params.offset = cpu_to_le32(offset);
2217         req->params.data_buf_size = cpu_to_le32(0x4);
2218
2219         status = be_mcc_notify_wait(adapter);
2220         if (!status)
2221                 memcpy(flashed_crc, req->crc, 4);
2222
2223 err:
2224         spin_unlock_bh(&adapter->mcc_lock);
2225         return status;
2226 }
2227
2228 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2229                                 struct be_dma_mem *nonemb_cmd)
2230 {
2231         struct be_mcc_wrb *wrb;
2232         struct be_cmd_req_acpi_wol_magic_config *req;
2233         int status;
2234
2235         spin_lock_bh(&adapter->mcc_lock);
2236
2237         wrb = wrb_from_mccq(adapter);
2238         if (!wrb) {
2239                 status = -EBUSY;
2240                 goto err;
2241         }
2242         req = nonemb_cmd->va;
2243
2244         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2245                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2246                 nonemb_cmd);
2247         memcpy(req->magic_mac, mac, ETH_ALEN);
2248
2249         status = be_mcc_notify_wait(adapter);
2250
2251 err:
2252         spin_unlock_bh(&adapter->mcc_lock);
2253         return status;
2254 }
2255
2256 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2257                         u8 loopback_type, u8 enable)
2258 {
2259         struct be_mcc_wrb *wrb;
2260         struct be_cmd_req_set_lmode *req;
2261         int status;
2262
2263         spin_lock_bh(&adapter->mcc_lock);
2264
2265         wrb = wrb_from_mccq(adapter);
2266         if (!wrb) {
2267                 status = -EBUSY;
2268                 goto err;
2269         }
2270
2271         req = embedded_payload(wrb);
2272
2273         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2274                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2275                         NULL);
2276
2277         req->src_port = port_num;
2278         req->dest_port = port_num;
2279         req->loopback_type = loopback_type;
2280         req->loopback_state = enable;
2281
2282         status = be_mcc_notify_wait(adapter);
2283 err:
2284         spin_unlock_bh(&adapter->mcc_lock);
2285         return status;
2286 }
2287
2288 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2289                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2290 {
2291         struct be_mcc_wrb *wrb;
2292         struct be_cmd_req_loopback_test *req;
2293         int status;
2294
2295         spin_lock_bh(&adapter->mcc_lock);
2296
2297         wrb = wrb_from_mccq(adapter);
2298         if (!wrb) {
2299                 status = -EBUSY;
2300                 goto err;
2301         }
2302
2303         req = embedded_payload(wrb);
2304
2305         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2306                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2307         req->hdr.timeout = cpu_to_le32(4);
2308
2309         req->pattern = cpu_to_le64(pattern);
2310         req->src_port = cpu_to_le32(port_num);
2311         req->dest_port = cpu_to_le32(port_num);
2312         req->pkt_size = cpu_to_le32(pkt_size);
2313         req->num_pkts = cpu_to_le32(num_pkts);
2314         req->loopback_type = cpu_to_le32(loopback_type);
2315
2316         status = be_mcc_notify_wait(adapter);
2317         if (!status) {
2318                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2319                 status = le32_to_cpu(resp->status);
2320         }
2321
2322 err:
2323         spin_unlock_bh(&adapter->mcc_lock);
2324         return status;
2325 }
2326
2327 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2328                                 u32 byte_cnt, struct be_dma_mem *cmd)
2329 {
2330         struct be_mcc_wrb *wrb;
2331         struct be_cmd_req_ddrdma_test *req;
2332         int status;
2333         int i, j = 0;
2334
2335         spin_lock_bh(&adapter->mcc_lock);
2336
2337         wrb = wrb_from_mccq(adapter);
2338         if (!wrb) {
2339                 status = -EBUSY;
2340                 goto err;
2341         }
2342         req = cmd->va;
2343         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2344                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2345
2346         req->pattern = cpu_to_le64(pattern);
2347         req->byte_count = cpu_to_le32(byte_cnt);
2348         for (i = 0; i < byte_cnt; i++) {
2349                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2350                 j++;
2351                 if (j > 7)
2352                         j = 0;
2353         }
2354
2355         status = be_mcc_notify_wait(adapter);
2356
2357         if (!status) {
2358                 struct be_cmd_resp_ddrdma_test *resp;
2359                 resp = cmd->va;
2360                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2361                                 resp->snd_err) {
2362                         status = -1;
2363                 }
2364         }
2365
2366 err:
2367         spin_unlock_bh(&adapter->mcc_lock);
2368         return status;
2369 }
2370
2371 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2372                                 struct be_dma_mem *nonemb_cmd)
2373 {
2374         struct be_mcc_wrb *wrb;
2375         struct be_cmd_req_seeprom_read *req;
2376         int status;
2377
2378         spin_lock_bh(&adapter->mcc_lock);
2379
2380         wrb = wrb_from_mccq(adapter);
2381         if (!wrb) {
2382                 status = -EBUSY;
2383                 goto err;
2384         }
2385         req = nonemb_cmd->va;
2386
2387         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2388                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2389                         nonemb_cmd);
2390
2391         status = be_mcc_notify_wait(adapter);
2392
2393 err:
2394         spin_unlock_bh(&adapter->mcc_lock);
2395         return status;
2396 }
2397
2398 int be_cmd_get_phy_info(struct be_adapter *adapter)
2399 {
2400         struct be_mcc_wrb *wrb;
2401         struct be_cmd_req_get_phy_info *req;
2402         struct be_dma_mem cmd;
2403         int status;
2404
2405         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2406                             CMD_SUBSYSTEM_COMMON))
2407                 return -EPERM;
2408
2409         spin_lock_bh(&adapter->mcc_lock);
2410
2411         wrb = wrb_from_mccq(adapter);
2412         if (!wrb) {
2413                 status = -EBUSY;
2414                 goto err;
2415         }
2416         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2417         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2418                                         &cmd.dma);
2419         if (!cmd.va) {
2420                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2421                 status = -ENOMEM;
2422                 goto err;
2423         }
2424
2425         req = cmd.va;
2426
2427         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2428                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2429                         wrb, &cmd);
2430
2431         status = be_mcc_notify_wait(adapter);
2432         if (!status) {
2433                 struct be_phy_info *resp_phy_info =
2434                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2435                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2436                 adapter->phy.interface_type =
2437                         le16_to_cpu(resp_phy_info->interface_type);
2438                 adapter->phy.auto_speeds_supported =
2439                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2440                 adapter->phy.fixed_speeds_supported =
2441                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2442                 adapter->phy.misc_params =
2443                         le32_to_cpu(resp_phy_info->misc_params);
2444         }
2445         pci_free_consistent(adapter->pdev, cmd.size,
2446                                 cmd.va, cmd.dma);
2447 err:
2448         spin_unlock_bh(&adapter->mcc_lock);
2449         return status;
2450 }
2451
2452 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2453 {
2454         struct be_mcc_wrb *wrb;
2455         struct be_cmd_req_set_qos *req;
2456         int status;
2457
2458         spin_lock_bh(&adapter->mcc_lock);
2459
2460         wrb = wrb_from_mccq(adapter);
2461         if (!wrb) {
2462                 status = -EBUSY;
2463                 goto err;
2464         }
2465
2466         req = embedded_payload(wrb);
2467
2468         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2469                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2470
2471         req->hdr.domain = domain;
2472         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2473         req->max_bps_nic = cpu_to_le32(bps);
2474
2475         status = be_mcc_notify_wait(adapter);
2476
2477 err:
2478         spin_unlock_bh(&adapter->mcc_lock);
2479         return status;
2480 }
2481
2482 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2483 {
2484         struct be_mcc_wrb *wrb;
2485         struct be_cmd_req_cntl_attribs *req;
2486         struct be_cmd_resp_cntl_attribs *resp;
2487         int status;
2488         int payload_len = max(sizeof(*req), sizeof(*resp));
2489         struct mgmt_controller_attrib *attribs;
2490         struct be_dma_mem attribs_cmd;
2491
2492         if (mutex_lock_interruptible(&adapter->mbox_lock))
2493                 return -1;
2494
2495         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2496         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2497         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2498                                                 &attribs_cmd.dma);
2499         if (!attribs_cmd.va) {
2500                 dev_err(&adapter->pdev->dev,
2501                                 "Memory allocation failure\n");
2502                 status = -ENOMEM;
2503                 goto err;
2504         }
2505
2506         wrb = wrb_from_mbox(adapter);
2507         if (!wrb) {
2508                 status = -EBUSY;
2509                 goto err;
2510         }
2511         req = attribs_cmd.va;
2512
2513         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2514                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2515                         &attribs_cmd);
2516
2517         status = be_mbox_notify_wait(adapter);
2518         if (!status) {
2519                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2520                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2521         }
2522
2523 err:
2524         mutex_unlock(&adapter->mbox_lock);
2525         if (attribs_cmd.va)
2526                 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2527                                     attribs_cmd.va, attribs_cmd.dma);
2528         return status;
2529 }
2530
2531 /* Uses mbox */
2532 int be_cmd_req_native_mode(struct be_adapter *adapter)
2533 {
2534         struct be_mcc_wrb *wrb;
2535         struct be_cmd_req_set_func_cap *req;
2536         int status;
2537
2538         if (mutex_lock_interruptible(&adapter->mbox_lock))
2539                 return -1;
2540
2541         wrb = wrb_from_mbox(adapter);
2542         if (!wrb) {
2543                 status = -EBUSY;
2544                 goto err;
2545         }
2546
2547         req = embedded_payload(wrb);
2548
2549         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2550                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2551
2552         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2553                                 CAPABILITY_BE3_NATIVE_ERX_API);
2554         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2555
2556         status = be_mbox_notify_wait(adapter);
2557         if (!status) {
2558                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2559                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2560                                         CAPABILITY_BE3_NATIVE_ERX_API;
2561                 if (!adapter->be3_native)
2562                         dev_warn(&adapter->pdev->dev,
2563                                  "adapter not in advanced mode\n");
2564         }
2565 err:
2566         mutex_unlock(&adapter->mbox_lock);
2567         return status;
2568 }
2569
2570 /* Get privilege(s) for a function */
2571 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2572                              u32 domain)
2573 {
2574         struct be_mcc_wrb *wrb;
2575         struct be_cmd_req_get_fn_privileges *req;
2576         int status;
2577
2578         spin_lock_bh(&adapter->mcc_lock);
2579
2580         wrb = wrb_from_mccq(adapter);
2581         if (!wrb) {
2582                 status = -EBUSY;
2583                 goto err;
2584         }
2585
2586         req = embedded_payload(wrb);
2587
2588         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2589                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2590                                wrb, NULL);
2591
2592         req->hdr.domain = domain;
2593
2594         status = be_mcc_notify_wait(adapter);
2595         if (!status) {
2596                 struct be_cmd_resp_get_fn_privileges *resp =
2597                                                 embedded_payload(wrb);
2598                 *privilege = le32_to_cpu(resp->privilege_mask);
2599         }
2600
2601 err:
2602         spin_unlock_bh(&adapter->mcc_lock);
2603         return status;
2604 }
2605
2606 /* Uses synchronous MCCQ */
2607 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2608                              bool *pmac_id_active, u32 *pmac_id, u8 domain)
2609 {
2610         struct be_mcc_wrb *wrb;
2611         struct be_cmd_req_get_mac_list *req;
2612         int status;
2613         int mac_count;
2614         struct be_dma_mem get_mac_list_cmd;
2615         int i;
2616
2617         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2618         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2619         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2620                         get_mac_list_cmd.size,
2621                         &get_mac_list_cmd.dma);
2622
2623         if (!get_mac_list_cmd.va) {
2624                 dev_err(&adapter->pdev->dev,
2625                                 "Memory allocation failure during GET_MAC_LIST\n");
2626                 return -ENOMEM;
2627         }
2628
2629         spin_lock_bh(&adapter->mcc_lock);
2630
2631         wrb = wrb_from_mccq(adapter);
2632         if (!wrb) {
2633                 status = -EBUSY;
2634                 goto out;
2635         }
2636
2637         req = get_mac_list_cmd.va;
2638
2639         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2640                                 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2641                                 wrb, &get_mac_list_cmd);
2642
2643         req->hdr.domain = domain;
2644         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2645         req->perm_override = 1;
2646
2647         status = be_mcc_notify_wait(adapter);
2648         if (!status) {
2649                 struct be_cmd_resp_get_mac_list *resp =
2650                                                 get_mac_list_cmd.va;
2651                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2652                 /* Mac list returned could contain one or more active mac_ids
2653                  * or one or more true or pseudo permanant mac addresses.
2654                  * If an active mac_id is present, return first active mac_id
2655                  * found.
2656                  */
2657                 for (i = 0; i < mac_count; i++) {
2658                         struct get_list_macaddr *mac_entry;
2659                         u16 mac_addr_size;
2660                         u32 mac_id;
2661
2662                         mac_entry = &resp->macaddr_list[i];
2663                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2664                         /* mac_id is a 32 bit value and mac_addr size
2665                          * is 6 bytes
2666                          */
2667                         if (mac_addr_size == sizeof(u32)) {
2668                                 *pmac_id_active = true;
2669                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2670                                 *pmac_id = le32_to_cpu(mac_id);
2671                                 goto out;
2672                         }
2673                 }
2674                 /* If no active mac_id found, return first mac addr */
2675                 *pmac_id_active = false;
2676                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2677                                                                 ETH_ALEN);
2678         }
2679
2680 out:
2681         spin_unlock_bh(&adapter->mcc_lock);
2682         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2683                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2684         return status;
2685 }
2686
2687 /* Uses synchronous MCCQ */
2688 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2689                         u8 mac_count, u32 domain)
2690 {
2691         struct be_mcc_wrb *wrb;
2692         struct be_cmd_req_set_mac_list *req;
2693         int status;
2694         struct be_dma_mem cmd;
2695
2696         memset(&cmd, 0, sizeof(struct be_dma_mem));
2697         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2698         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2699                         &cmd.dma, GFP_KERNEL);
2700         if (!cmd.va)
2701                 return -ENOMEM;
2702
2703         spin_lock_bh(&adapter->mcc_lock);
2704
2705         wrb = wrb_from_mccq(adapter);
2706         if (!wrb) {
2707                 status = -EBUSY;
2708                 goto err;
2709         }
2710
2711         req = cmd.va;
2712         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2713                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2714                                 wrb, &cmd);
2715
2716         req->hdr.domain = domain;
2717         req->mac_count = mac_count;
2718         if (mac_count)
2719                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2720
2721         status = be_mcc_notify_wait(adapter);
2722
2723 err:
2724         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2725                                 cmd.va, cmd.dma);
2726         spin_unlock_bh(&adapter->mcc_lock);
2727         return status;
2728 }
2729
2730 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2731                         u32 domain, u16 intf_id)
2732 {
2733         struct be_mcc_wrb *wrb;
2734         struct be_cmd_req_set_hsw_config *req;
2735         void *ctxt;
2736         int status;
2737
2738         spin_lock_bh(&adapter->mcc_lock);
2739
2740         wrb = wrb_from_mccq(adapter);
2741         if (!wrb) {
2742                 status = -EBUSY;
2743                 goto err;
2744         }
2745
2746         req = embedded_payload(wrb);
2747         ctxt = &req->context;
2748
2749         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2750                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2751
2752         req->hdr.domain = domain;
2753         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2754         if (pvid) {
2755                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2756                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2757         }
2758
2759         be_dws_cpu_to_le(req->context, sizeof(req->context));
2760         status = be_mcc_notify_wait(adapter);
2761
2762 err:
2763         spin_unlock_bh(&adapter->mcc_lock);
2764         return status;
2765 }
2766
2767 /* Get Hyper switch config */
2768 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2769                         u32 domain, u16 intf_id)
2770 {
2771         struct be_mcc_wrb *wrb;
2772         struct be_cmd_req_get_hsw_config *req;
2773         void *ctxt;
2774         int status;
2775         u16 vid;
2776
2777         spin_lock_bh(&adapter->mcc_lock);
2778
2779         wrb = wrb_from_mccq(adapter);
2780         if (!wrb) {
2781                 status = -EBUSY;
2782                 goto err;
2783         }
2784
2785         req = embedded_payload(wrb);
2786         ctxt = &req->context;
2787
2788         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2789                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2790
2791         req->hdr.domain = domain;
2792         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2793                                                                 intf_id);
2794         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2795         be_dws_cpu_to_le(req->context, sizeof(req->context));
2796
2797         status = be_mcc_notify_wait(adapter);
2798         if (!status) {
2799                 struct be_cmd_resp_get_hsw_config *resp =
2800                                                 embedded_payload(wrb);
2801                 be_dws_le_to_cpu(&resp->context,
2802                                                 sizeof(resp->context));
2803                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2804                                                         pvid, &resp->context);
2805                 *pvid = le16_to_cpu(vid);
2806         }
2807
2808 err:
2809         spin_unlock_bh(&adapter->mcc_lock);
2810         return status;
2811 }
2812
2813 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2814 {
2815         struct be_mcc_wrb *wrb;
2816         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2817         int status;
2818         int payload_len = sizeof(*req);
2819         struct be_dma_mem cmd;
2820
2821         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2822                             CMD_SUBSYSTEM_ETH))
2823                 return -EPERM;
2824
2825         if (mutex_lock_interruptible(&adapter->mbox_lock))
2826                 return -1;
2827
2828         memset(&cmd, 0, sizeof(struct be_dma_mem));
2829         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2830         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2831                                                &cmd.dma);
2832         if (!cmd.va) {
2833                 dev_err(&adapter->pdev->dev,
2834                                 "Memory allocation failure\n");
2835                 status = -ENOMEM;
2836                 goto err;
2837         }
2838
2839         wrb = wrb_from_mbox(adapter);
2840         if (!wrb) {
2841                 status = -EBUSY;
2842                 goto err;
2843         }
2844
2845         req = cmd.va;
2846
2847         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2848                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2849                                payload_len, wrb, &cmd);
2850
2851         req->hdr.version = 1;
2852         req->query_options = BE_GET_WOL_CAP;
2853
2854         status = be_mbox_notify_wait(adapter);
2855         if (!status) {
2856                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2857                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2858
2859                 /* the command could succeed misleadingly on old f/w
2860                  * which is not aware of the V1 version. fake an error. */
2861                 if (resp->hdr.response_length < payload_len) {
2862                         status = -1;
2863                         goto err;
2864                 }
2865                 adapter->wol_cap = resp->wol_settings;
2866         }
2867 err:
2868         mutex_unlock(&adapter->mbox_lock);
2869         if (cmd.va)
2870                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2871         return status;
2872
2873 }
2874 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2875                                    struct be_dma_mem *cmd)
2876 {
2877         struct be_mcc_wrb *wrb;
2878         struct be_cmd_req_get_ext_fat_caps *req;
2879         int status;
2880
2881         if (mutex_lock_interruptible(&adapter->mbox_lock))
2882                 return -1;
2883
2884         wrb = wrb_from_mbox(adapter);
2885         if (!wrb) {
2886                 status = -EBUSY;
2887                 goto err;
2888         }
2889
2890         req = cmd->va;
2891         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2892                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2893                                cmd->size, wrb, cmd);
2894         req->parameter_type = cpu_to_le32(1);
2895
2896         status = be_mbox_notify_wait(adapter);
2897 err:
2898         mutex_unlock(&adapter->mbox_lock);
2899         return status;
2900 }
2901
2902 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2903                                    struct be_dma_mem *cmd,
2904                                    struct be_fat_conf_params *configs)
2905 {
2906         struct be_mcc_wrb *wrb;
2907         struct be_cmd_req_set_ext_fat_caps *req;
2908         int status;
2909
2910         spin_lock_bh(&adapter->mcc_lock);
2911
2912         wrb = wrb_from_mccq(adapter);
2913         if (!wrb) {
2914                 status = -EBUSY;
2915                 goto err;
2916         }
2917
2918         req = cmd->va;
2919         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2920         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2921                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2922                                cmd->size, wrb, cmd);
2923
2924         status = be_mcc_notify_wait(adapter);
2925 err:
2926         spin_unlock_bh(&adapter->mcc_lock);
2927         return status;
2928 }
2929
2930 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2931 {
2932         struct be_mcc_wrb *wrb;
2933         struct be_cmd_req_get_port_name *req;
2934         int status;
2935
2936         if (!lancer_chip(adapter)) {
2937                 *port_name = adapter->hba_port_num + '0';
2938                 return 0;
2939         }
2940
2941         spin_lock_bh(&adapter->mcc_lock);
2942
2943         wrb = wrb_from_mccq(adapter);
2944         if (!wrb) {
2945                 status = -EBUSY;
2946                 goto err;
2947         }
2948
2949         req = embedded_payload(wrb);
2950
2951         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2952                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2953                                NULL);
2954         req->hdr.version = 1;
2955
2956         status = be_mcc_notify_wait(adapter);
2957         if (!status) {
2958                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2959                 *port_name = resp->port_name[adapter->hba_port_num];
2960         } else {
2961                 *port_name = adapter->hba_port_num + '0';
2962         }
2963 err:
2964         spin_unlock_bh(&adapter->mcc_lock);
2965         return status;
2966 }
2967
2968 static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
2969                                                     u32 max_buf_size)
2970 {
2971         struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf;
2972         int i;
2973
2974         for (i = 0; i < desc_count; i++) {
2975                 desc->desc_len = desc->desc_len ? : RESOURCE_DESC_SIZE;
2976                 if (((void *)desc + desc->desc_len) >
2977                     (void *)(buf + max_buf_size)) {
2978                         desc = NULL;
2979                         break;
2980                 }
2981
2982                 if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
2983                     desc->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
2984                         break;
2985
2986                 desc = (void *)desc + desc->desc_len;
2987         }
2988
2989         if (!desc || i == MAX_RESOURCE_DESC)
2990                 return NULL;
2991
2992         return desc;
2993 }
2994
2995 /* Uses Mbox */
2996 int be_cmd_get_func_config(struct be_adapter *adapter)
2997 {
2998         struct be_mcc_wrb *wrb;
2999         struct be_cmd_req_get_func_config *req;
3000         int status;
3001         struct be_dma_mem cmd;
3002
3003         if (mutex_lock_interruptible(&adapter->mbox_lock))
3004                 return -1;
3005
3006         memset(&cmd, 0, sizeof(struct be_dma_mem));
3007         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3008         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3009                                       &cmd.dma);
3010         if (!cmd.va) {
3011                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3012                 status = -ENOMEM;
3013                 goto err;
3014         }
3015
3016         wrb = wrb_from_mbox(adapter);
3017         if (!wrb) {
3018                 status = -EBUSY;
3019                 goto err;
3020         }
3021
3022         req = cmd.va;
3023
3024         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3025                                OPCODE_COMMON_GET_FUNC_CONFIG,
3026                                cmd.size, wrb, &cmd);
3027
3028         if (skyhawk_chip(adapter))
3029                 req->hdr.version = 1;
3030
3031         status = be_mbox_notify_wait(adapter);
3032         if (!status) {
3033                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3034                 u32 desc_count = le32_to_cpu(resp->desc_count);
3035                 struct be_nic_resource_desc *desc;
3036
3037                 desc = be_get_nic_desc(resp->func_param, desc_count,
3038                                        sizeof(resp->func_param));
3039                 if (!desc) {
3040                         status = -EINVAL;
3041                         goto err;
3042                 }
3043
3044                 adapter->pf_number = desc->pf_num;
3045                 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count);
3046                 adapter->max_vlans = le16_to_cpu(desc->vlan_count);
3047                 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3048                 adapter->max_tx_queues = le16_to_cpu(desc->txq_count);
3049                 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count);
3050                 adapter->max_rx_queues = le16_to_cpu(desc->rq_count);
3051
3052                 adapter->max_event_queues = le16_to_cpu(desc->eq_count);
3053                 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags);
3054         }
3055 err:
3056         mutex_unlock(&adapter->mbox_lock);
3057         if (cmd.va)
3058                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3059         return status;
3060 }
3061
3062 /* Uses mbox */
3063 int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3064                                    u8 domain, struct be_dma_mem *cmd)
3065 {
3066         struct be_mcc_wrb *wrb;
3067         struct be_cmd_req_get_profile_config *req;
3068         int status;
3069
3070         if (mutex_lock_interruptible(&adapter->mbox_lock))
3071                 return -1;
3072         wrb = wrb_from_mbox(adapter);
3073
3074         req = cmd->va;
3075         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3076                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3077                                cmd->size, wrb, cmd);
3078
3079         req->type = ACTIVE_PROFILE_TYPE;
3080         req->hdr.domain = domain;
3081         if (!lancer_chip(adapter))
3082                 req->hdr.version = 1;
3083
3084         status = be_mbox_notify_wait(adapter);
3085
3086         mutex_unlock(&adapter->mbox_lock);
3087         return status;
3088 }
3089
3090 /* Uses sync mcc */
3091 int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3092                                    u8 domain, struct be_dma_mem *cmd)
3093 {
3094         struct be_mcc_wrb *wrb;
3095         struct be_cmd_req_get_profile_config *req;
3096         int status;
3097
3098         spin_lock_bh(&adapter->mcc_lock);
3099
3100         wrb = wrb_from_mccq(adapter);
3101         if (!wrb) {
3102                 status = -EBUSY;
3103                 goto err;
3104         }
3105
3106         req = cmd->va;
3107         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3108                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3109                                cmd->size, wrb, cmd);
3110
3111         req->type = ACTIVE_PROFILE_TYPE;
3112         req->hdr.domain = domain;
3113         if (!lancer_chip(adapter))
3114                 req->hdr.version = 1;
3115
3116         status = be_mcc_notify_wait(adapter);
3117
3118 err:
3119         spin_unlock_bh(&adapter->mcc_lock);
3120         return status;
3121 }
3122
3123 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3124 int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
3125                               u16 *txq_count, u8 domain)
3126 {
3127         struct be_queue_info *mccq = &adapter->mcc_obj.q;
3128         struct be_dma_mem cmd;
3129         int status;
3130
3131         memset(&cmd, 0, sizeof(struct be_dma_mem));
3132         if (!lancer_chip(adapter))
3133                 cmd.size = sizeof(struct be_cmd_resp_get_profile_config_v1);
3134         else
3135                 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3136         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3137                                       &cmd.dma);
3138         if (!cmd.va) {
3139                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3140                 return -ENOMEM;
3141         }
3142
3143         if (!mccq->created)
3144                 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3145         else
3146                 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3147         if (!status) {
3148                 struct be_cmd_resp_get_profile_config *resp = cmd.va;
3149                 u32 desc_count = le32_to_cpu(resp->desc_count);
3150                 struct be_nic_resource_desc *desc;
3151
3152                 desc = be_get_nic_desc(resp->func_param, desc_count,
3153                                        sizeof(resp->func_param));
3154
3155                 if (!desc) {
3156                         status = -EINVAL;
3157                         goto err;
3158                 }
3159                 if (cap_flags)
3160                         *cap_flags = le32_to_cpu(desc->cap_flags);
3161                 if (txq_count)
3162                         *txq_count = le32_to_cpu(desc->txq_count);
3163         }
3164 err:
3165         if (cmd.va)
3166                 pci_free_consistent(adapter->pdev, cmd.size,
3167                                     cmd.va, cmd.dma);
3168         return status;
3169 }
3170
3171 /* Uses sync mcc */
3172 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3173                               u8 domain)
3174 {
3175         struct be_mcc_wrb *wrb;
3176         struct be_cmd_req_set_profile_config *req;
3177         int status;
3178
3179         spin_lock_bh(&adapter->mcc_lock);
3180
3181         wrb = wrb_from_mccq(adapter);
3182         if (!wrb) {
3183                 status = -EBUSY;
3184                 goto err;
3185         }
3186
3187         req = embedded_payload(wrb);
3188
3189         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3190                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3191                                wrb, NULL);
3192
3193         req->hdr.domain = domain;
3194         req->desc_count = cpu_to_le32(1);
3195
3196         req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3197         req->nic_desc.desc_len = RESOURCE_DESC_SIZE;
3198         req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3199         req->nic_desc.pf_num = adapter->pf_number;
3200         req->nic_desc.vf_num = domain;
3201
3202         /* Mark fields invalid */
3203         req->nic_desc.unicast_mac_count = 0xFFFF;
3204         req->nic_desc.mcc_count = 0xFFFF;
3205         req->nic_desc.vlan_count = 0xFFFF;
3206         req->nic_desc.mcast_mac_count = 0xFFFF;
3207         req->nic_desc.txq_count = 0xFFFF;
3208         req->nic_desc.rq_count = 0xFFFF;
3209         req->nic_desc.rssq_count = 0xFFFF;
3210         req->nic_desc.lro_count = 0xFFFF;
3211         req->nic_desc.cq_count = 0xFFFF;
3212         req->nic_desc.toe_conn_count = 0xFFFF;
3213         req->nic_desc.eq_count = 0xFFFF;
3214         req->nic_desc.link_param = 0xFF;
3215         req->nic_desc.bw_min = 0xFFFFFFFF;
3216         req->nic_desc.acpi_params = 0xFF;
3217         req->nic_desc.wol_param = 0x0F;
3218
3219         /* Change BW */
3220         req->nic_desc.bw_min = cpu_to_le32(bps);
3221         req->nic_desc.bw_max = cpu_to_le32(bps);
3222         status = be_mcc_notify_wait(adapter);
3223 err:
3224         spin_unlock_bh(&adapter->mcc_lock);
3225         return status;
3226 }
3227
3228 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3229                      int vf_num)
3230 {
3231         struct be_mcc_wrb *wrb;
3232         struct be_cmd_req_get_iface_list *req;
3233         struct be_cmd_resp_get_iface_list *resp;
3234         int status;
3235
3236         spin_lock_bh(&adapter->mcc_lock);
3237
3238         wrb = wrb_from_mccq(adapter);
3239         if (!wrb) {
3240                 status = -EBUSY;
3241                 goto err;
3242         }
3243         req = embedded_payload(wrb);
3244
3245         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3246                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3247                                wrb, NULL);
3248         req->hdr.domain = vf_num + 1;
3249
3250         status = be_mcc_notify_wait(adapter);
3251         if (!status) {
3252                 resp = (struct be_cmd_resp_get_iface_list *)req;
3253                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3254         }
3255
3256 err:
3257         spin_unlock_bh(&adapter->mcc_lock);
3258         return status;
3259 }
3260
3261 /* Uses sync mcc */
3262 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3263 {
3264         struct be_mcc_wrb *wrb;
3265         struct be_cmd_enable_disable_vf *req;
3266         int status;
3267
3268         if (!lancer_chip(adapter))
3269                 return 0;
3270
3271         spin_lock_bh(&adapter->mcc_lock);
3272
3273         wrb = wrb_from_mccq(adapter);
3274         if (!wrb) {
3275                 status = -EBUSY;
3276                 goto err;
3277         }
3278
3279         req = embedded_payload(wrb);
3280
3281         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3282                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3283                                wrb, NULL);
3284
3285         req->hdr.domain = domain;
3286         req->enable = 1;
3287         status = be_mcc_notify_wait(adapter);
3288 err:
3289         spin_unlock_bh(&adapter->mcc_lock);
3290         return status;
3291 }
3292
3293 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3294 {
3295         struct be_mcc_wrb *wrb;
3296         struct be_cmd_req_intr_set *req;
3297         int status;
3298
3299         if (mutex_lock_interruptible(&adapter->mbox_lock))
3300                 return -1;
3301
3302         wrb = wrb_from_mbox(adapter);
3303
3304         req = embedded_payload(wrb);
3305
3306         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3307                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3308                                wrb, NULL);
3309
3310         req->intr_enabled = intr_enable;
3311
3312         status = be_mbox_notify_wait(adapter);
3313
3314         mutex_unlock(&adapter->mbox_lock);
3315         return status;
3316 }
3317
3318 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3319                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3320 {
3321         struct be_adapter *adapter = netdev_priv(netdev_handle);
3322         struct be_mcc_wrb *wrb;
3323         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3324         struct be_cmd_req_hdr *req;
3325         struct be_cmd_resp_hdr *resp;
3326         int status;
3327
3328         spin_lock_bh(&adapter->mcc_lock);
3329
3330         wrb = wrb_from_mccq(adapter);
3331         if (!wrb) {
3332                 status = -EBUSY;
3333                 goto err;
3334         }
3335         req = embedded_payload(wrb);
3336         resp = embedded_payload(wrb);
3337
3338         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3339                                hdr->opcode, wrb_payload_size, wrb, NULL);
3340         memcpy(req, wrb_payload, wrb_payload_size);
3341         be_dws_cpu_to_le(req, wrb_payload_size);
3342
3343         status = be_mcc_notify_wait(adapter);
3344         if (cmd_status)
3345                 *cmd_status = (status & 0xffff);
3346         if (ext_status)
3347                 *ext_status = 0;
3348         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3349         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3350 err:
3351         spin_unlock_bh(&adapter->mcc_lock);
3352         return status;
3353 }
3354 EXPORT_SYMBOL(be_roce_mcc_cmd);