2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/init.h>
36 #include <linux/delay.h>
41 static int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
42 const u8 *fw_data, unsigned int size, int force);
44 * t4_wait_op_done_val - wait until an operation is completed
45 * @adapter: the adapter performing the operation
46 * @reg: the register to check for completion
47 * @mask: a single-bit field within @reg that indicates completion
48 * @polarity: the value of the field when the operation is completed
49 * @attempts: number of check iterations
50 * @delay: delay in usecs between iterations
51 * @valp: where to store the value of the register at completion time
53 * Wait until an operation is completed by checking a bit in a register
54 * up to @attempts times. If @valp is not NULL the value of the register
55 * at the time it indicated completion is stored there. Returns 0 if the
56 * operation completes and -EAGAIN otherwise.
58 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
59 int polarity, int attempts, int delay, u32 *valp)
62 u32 val = t4_read_reg(adapter, reg);
64 if (!!(val & mask) == polarity) {
76 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
77 int polarity, int attempts, int delay)
79 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
84 * t4_set_reg_field - set a register field to a value
85 * @adapter: the adapter to program
86 * @addr: the register address
87 * @mask: specifies the portion of the register to modify
88 * @val: the new value for the register field
90 * Sets a register field specified by the supplied mask to the
93 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
96 u32 v = t4_read_reg(adapter, addr) & ~mask;
98 t4_write_reg(adapter, addr, v | val);
99 (void) t4_read_reg(adapter, addr); /* flush */
103 * t4_read_indirect - read indirectly addressed registers
105 * @addr_reg: register holding the indirect address
106 * @data_reg: register holding the value of the indirect register
107 * @vals: where the read register values are stored
108 * @nregs: how many indirect registers to read
109 * @start_idx: index of first indirect register to read
111 * Reads registers that are accessed indirectly through an address/data
114 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
115 unsigned int data_reg, u32 *vals,
116 unsigned int nregs, unsigned int start_idx)
119 t4_write_reg(adap, addr_reg, start_idx);
120 *vals++ = t4_read_reg(adap, data_reg);
126 * t4_write_indirect - write indirectly addressed registers
128 * @addr_reg: register holding the indirect addresses
129 * @data_reg: register holding the value for the indirect registers
130 * @vals: values to write
131 * @nregs: how many indirect registers to write
132 * @start_idx: address of first indirect register to write
134 * Writes a sequential block of registers that are accessed indirectly
135 * through an address/data register pair.
137 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
138 unsigned int data_reg, const u32 *vals,
139 unsigned int nregs, unsigned int start_idx)
142 t4_write_reg(adap, addr_reg, start_idx++);
143 t4_write_reg(adap, data_reg, *vals++);
148 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
150 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
153 for ( ; nflit; nflit--, mbox_addr += 8)
154 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
158 * Handle a FW assertion reported in a mailbox.
160 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
162 struct fw_debug_cmd asrt;
164 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
165 dev_alert(adap->pdev_dev,
166 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
167 asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line),
168 ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y));
171 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
173 dev_err(adap->pdev_dev,
174 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
175 (unsigned long long)t4_read_reg64(adap, data_reg),
176 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
177 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
178 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
179 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
180 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
181 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
182 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
186 * t4_wr_mbox_meat - send a command to FW through the given mailbox
188 * @mbox: index of the mailbox to use
189 * @cmd: the command to write
190 * @size: command length in bytes
191 * @rpl: where to optionally store the reply
192 * @sleep_ok: if true we may sleep while awaiting command completion
194 * Sends the given command to FW through the selected mailbox and waits
195 * for the FW to execute the command. If @rpl is not %NULL it is used to
196 * store the FW's reply to the command. The command and its optional
197 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
198 * to respond. @sleep_ok determines whether we may sleep while awaiting
199 * the response. If sleeping is allowed we use progressive backoff
202 * The return value is 0 on success or a negative errno on failure. A
203 * failure can happen either because we are not able to execute the
204 * command or FW executes it but signals an error. In the latter case
205 * the return value is the error code indicated by FW (negated).
207 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
208 void *rpl, bool sleep_ok)
210 static const int delay[] = {
211 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
216 int i, ms, delay_idx;
217 const __be64 *p = cmd;
218 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA);
219 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL);
221 if ((size & 15) || size > MBOX_LEN)
225 * If the device is off-line, as in EEH, commands will time out.
226 * Fail them early so we don't waste time waiting.
228 if (adap->pdev->error_state != pci_channel_io_normal)
231 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
232 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
233 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
235 if (v != MBOX_OWNER_DRV)
236 return v ? -EBUSY : -ETIMEDOUT;
238 for (i = 0; i < size; i += 8)
239 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
241 t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
242 t4_read_reg(adap, ctl_reg); /* flush write */
247 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
249 ms = delay[delay_idx]; /* last element may repeat */
250 if (delay_idx < ARRAY_SIZE(delay) - 1)
256 v = t4_read_reg(adap, ctl_reg);
257 if (MBOWNER_GET(v) == MBOX_OWNER_DRV) {
258 if (!(v & MBMSGVALID)) {
259 t4_write_reg(adap, ctl_reg, 0);
263 res = t4_read_reg64(adap, data_reg);
264 if (FW_CMD_OP_GET(res >> 32) == FW_DEBUG_CMD) {
265 fw_asrt(adap, data_reg);
266 res = FW_CMD_RETVAL(EIO);
268 get_mbox_rpl(adap, rpl, size / 8, data_reg);
270 if (FW_CMD_RETVAL_GET((int)res))
271 dump_mbox(adap, mbox, data_reg);
272 t4_write_reg(adap, ctl_reg, 0);
273 return -FW_CMD_RETVAL_GET((int)res);
277 dump_mbox(adap, mbox, data_reg);
278 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
279 *(const u8 *)cmd, mbox);
284 * t4_mc_read - read from MC through backdoor accesses
286 * @addr: address of first byte requested
287 * @idx: which MC to access
288 * @data: 64 bytes of data containing the requested address
289 * @ecc: where to store the corresponding 64-bit ECC word
291 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
292 * that covers the requested address @addr. If @parity is not %NULL it
293 * is assigned the 64-bit ECC word for the read data.
295 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
298 u32 mc_bist_cmd, mc_bist_cmd_addr, mc_bist_cmd_len;
299 u32 mc_bist_status_rdata, mc_bist_data_pattern;
301 if (is_t4(adap->params.chip)) {
302 mc_bist_cmd = MC_BIST_CMD;
303 mc_bist_cmd_addr = MC_BIST_CMD_ADDR;
304 mc_bist_cmd_len = MC_BIST_CMD_LEN;
305 mc_bist_status_rdata = MC_BIST_STATUS_RDATA;
306 mc_bist_data_pattern = MC_BIST_DATA_PATTERN;
308 mc_bist_cmd = MC_REG(MC_P_BIST_CMD, idx);
309 mc_bist_cmd_addr = MC_REG(MC_P_BIST_CMD_ADDR, idx);
310 mc_bist_cmd_len = MC_REG(MC_P_BIST_CMD_LEN, idx);
311 mc_bist_status_rdata = MC_REG(MC_P_BIST_STATUS_RDATA, idx);
312 mc_bist_data_pattern = MC_REG(MC_P_BIST_DATA_PATTERN, idx);
315 if (t4_read_reg(adap, mc_bist_cmd) & START_BIST)
317 t4_write_reg(adap, mc_bist_cmd_addr, addr & ~0x3fU);
318 t4_write_reg(adap, mc_bist_cmd_len, 64);
319 t4_write_reg(adap, mc_bist_data_pattern, 0xc);
320 t4_write_reg(adap, mc_bist_cmd, BIST_OPCODE(1) | START_BIST |
322 i = t4_wait_op_done(adap, mc_bist_cmd, START_BIST, 0, 10, 1);
326 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata, i)
328 for (i = 15; i >= 0; i--)
329 *data++ = htonl(t4_read_reg(adap, MC_DATA(i)));
331 *ecc = t4_read_reg64(adap, MC_DATA(16));
337 * t4_edc_read - read from EDC through backdoor accesses
339 * @idx: which EDC to access
340 * @addr: address of first byte requested
341 * @data: 64 bytes of data containing the requested address
342 * @ecc: where to store the corresponding 64-bit ECC word
344 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
345 * that covers the requested address @addr. If @parity is not %NULL it
346 * is assigned the 64-bit ECC word for the read data.
348 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
351 u32 edc_bist_cmd, edc_bist_cmd_addr, edc_bist_cmd_len;
352 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata;
354 if (is_t4(adap->params.chip)) {
355 edc_bist_cmd = EDC_REG(EDC_BIST_CMD, idx);
356 edc_bist_cmd_addr = EDC_REG(EDC_BIST_CMD_ADDR, idx);
357 edc_bist_cmd_len = EDC_REG(EDC_BIST_CMD_LEN, idx);
358 edc_bist_cmd_data_pattern = EDC_REG(EDC_BIST_DATA_PATTERN,
360 edc_bist_status_rdata = EDC_REG(EDC_BIST_STATUS_RDATA,
363 edc_bist_cmd = EDC_REG_T5(EDC_H_BIST_CMD, idx);
364 edc_bist_cmd_addr = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx);
365 edc_bist_cmd_len = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx);
366 edc_bist_cmd_data_pattern =
367 EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx);
368 edc_bist_status_rdata =
369 EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx);
372 if (t4_read_reg(adap, edc_bist_cmd) & START_BIST)
374 t4_write_reg(adap, edc_bist_cmd_addr, addr & ~0x3fU);
375 t4_write_reg(adap, edc_bist_cmd_len, 64);
376 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
377 t4_write_reg(adap, edc_bist_cmd,
378 BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST);
379 i = t4_wait_op_done(adap, edc_bist_cmd, START_BIST, 0, 10, 1);
383 #define EDC_DATA(i) (EDC_BIST_STATUS_REG(edc_bist_status_rdata, i))
385 for (i = 15; i >= 0; i--)
386 *data++ = htonl(t4_read_reg(adap, EDC_DATA(i)));
388 *ecc = t4_read_reg64(adap, EDC_DATA(16));
394 * t4_mem_win_rw - read/write memory through PCIE memory window
396 * @addr: address of first byte requested
397 * @data: MEMWIN0_APERTURE bytes of data containing the requested address
398 * @dir: direction of transfer 1 => read, 0 => write
400 * Read/write MEMWIN0_APERTURE bytes of data from MC starting at a
401 * MEMWIN0_APERTURE-byte-aligned address that covers the requested
404 static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir)
407 u32 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
410 * Setup offset into PCIE memory window. Address must be a
411 * MEMWIN0_APERTURE-byte-aligned address. (Read back MA register to
412 * ensure that changes propagate before we attempt to use the new
415 t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
416 (addr & ~(MEMWIN0_APERTURE - 1)) | win_pf);
417 t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
419 /* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */
420 for (i = 0; i < MEMWIN0_APERTURE; i = i+0x4) {
422 *data++ = (__force __be32) t4_read_reg(adap,
425 t4_write_reg(adap, (MEMWIN0_BASE + i),
426 (__force u32) *data++);
433 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
435 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
436 * @addr: address within indicated memory type
437 * @len: amount of memory to transfer
438 * @buf: host memory buffer
439 * @dir: direction of transfer 1 => read, 0 => write
441 * Reads/writes an [almost] arbitrary memory region in the firmware: the
442 * firmware memory address, length and host buffer must be aligned on
443 * 32-bit boudaries. The memory is transferred as a raw byte sequence
444 * from/to the firmware's memory. If this memory contains data
445 * structures which contain multi-byte integers, it's the callers
446 * responsibility to perform appropriate byte order conversions.
448 static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len,
449 __be32 *buf, int dir)
451 u32 pos, start, end, offset, memoffset;
452 u32 edc_size, mc_size;
457 * Argument sanity checks ...
459 if ((addr & 0x3) || (len & 0x3))
462 data = vmalloc(MEMWIN0_APERTURE);
466 /* Offset into the region of memory which is being accessed
470 * MEM_MC0 = 2 -- For T5
471 * MEM_MC1 = 3 -- For T5
473 edc_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM0_BAR));
474 if (mtype != MEM_MC1)
475 memoffset = (mtype * (edc_size * 1024 * 1024));
477 mc_size = EXT_MEM_SIZE_GET(t4_read_reg(adap,
479 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
482 /* Determine the PCIE_MEM_ACCESS_OFFSET */
483 addr = addr + memoffset;
486 * The underlaying EDC/MC read routines read MEMWIN0_APERTURE bytes
487 * at a time so we need to round down the start and round up the end.
488 * We'll start copying out of the first line at (addr - start) a word
491 start = addr & ~(MEMWIN0_APERTURE-1);
492 end = (addr + len + MEMWIN0_APERTURE-1) & ~(MEMWIN0_APERTURE-1);
493 offset = (addr - start)/sizeof(__be32);
495 for (pos = start; pos < end; pos += MEMWIN0_APERTURE, offset = 0) {
498 * If we're writing, copy the data from the caller's memory
503 * If we're doing a partial write, then we need to do
504 * a read-modify-write ...
506 if (offset || len < MEMWIN0_APERTURE) {
507 ret = t4_mem_win_rw(adap, pos, data, 1);
511 while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
513 data[offset++] = *buf++;
514 len -= sizeof(__be32);
519 * Transfer a block of memory and bail if there's an error.
521 ret = t4_mem_win_rw(adap, pos, data, dir);
526 * If we're reading, copy the data into the caller's memory
530 while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
532 *buf++ = data[offset++];
533 len -= sizeof(__be32);
541 int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
544 return t4_memory_rw(adap, mtype, addr, len, buf, 0);
547 #define EEPROM_STAT_ADDR 0x7bfc
548 #define VPD_BASE 0x400
549 #define VPD_BASE_OLD 0
553 * t4_seeprom_wp - enable/disable EEPROM write protection
554 * @adapter: the adapter
555 * @enable: whether to enable or disable write protection
557 * Enables or disables write protection on the serial EEPROM.
559 int t4_seeprom_wp(struct adapter *adapter, bool enable)
561 unsigned int v = enable ? 0xc : 0;
562 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
563 return ret < 0 ? ret : 0;
567 * get_vpd_params - read VPD parameters from VPD EEPROM
568 * @adapter: adapter to read
569 * @p: where to store the parameters
571 * Reads card parameters stored in VPD EEPROM.
573 int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
575 u32 cclk_param, cclk_val;
579 unsigned int vpdr_len, kw_offset, id_len;
581 vpd = vmalloc(VPD_LEN);
585 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
588 addr = *vpd == 0x82 ? VPD_BASE : VPD_BASE_OLD;
590 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
594 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
595 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
600 id_len = pci_vpd_lrdt_size(vpd);
604 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
606 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
611 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
612 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
613 if (vpdr_len + kw_offset > VPD_LEN) {
614 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
619 #define FIND_VPD_KW(var, name) do { \
620 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
622 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
626 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
629 FIND_VPD_KW(i, "RV");
630 for (csum = 0; i >= 0; i--)
634 dev_err(adapter->pdev_dev,
635 "corrupted VPD EEPROM, actual csum %u\n", csum);
640 FIND_VPD_KW(ec, "EC");
641 FIND_VPD_KW(sn, "SN");
644 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
646 memcpy(p->ec, vpd + ec, EC_LEN);
648 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
649 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
653 * Ask firmware for the Core Clock since it knows how to translate the
654 * Reference Clock ('V2') VPD field into a Core Clock value ...
656 cclk_param = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
657 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
658 ret = t4_query_params(adapter, adapter->mbox, 0, 0,
659 1, &cclk_param, &cclk_val);
670 /* serial flash and firmware constants */
672 SF_ATTEMPTS = 10, /* max retries for SF operations */
674 /* flash command opcodes */
675 SF_PROG_PAGE = 2, /* program page */
676 SF_WR_DISABLE = 4, /* disable writes */
677 SF_RD_STATUS = 5, /* read status register */
678 SF_WR_ENABLE = 6, /* enable writes */
679 SF_RD_DATA_FAST = 0xb, /* read flash */
680 SF_RD_ID = 0x9f, /* read ID */
681 SF_ERASE_SECTOR = 0xd8, /* erase sector */
683 FW_MAX_SIZE = 512 * 1024,
687 * sf1_read - read data from the serial flash
688 * @adapter: the adapter
689 * @byte_cnt: number of bytes to read
690 * @cont: whether another operation will be chained
691 * @lock: whether to lock SF for PL access only
692 * @valp: where to store the read data
694 * Reads up to 4 bytes of data from the serial flash. The location of
695 * the read needs to be specified prior to calling this by issuing the
696 * appropriate commands to the serial flash.
698 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
703 if (!byte_cnt || byte_cnt > 4)
705 if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
707 cont = cont ? SF_CONT : 0;
708 lock = lock ? SF_LOCK : 0;
709 t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1));
710 ret = t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
712 *valp = t4_read_reg(adapter, SF_DATA);
717 * sf1_write - write data to the serial flash
718 * @adapter: the adapter
719 * @byte_cnt: number of bytes to write
720 * @cont: whether another operation will be chained
721 * @lock: whether to lock SF for PL access only
722 * @val: value to write
724 * Writes up to 4 bytes of data to the serial flash. The location of
725 * the write needs to be specified prior to calling this by issuing the
726 * appropriate commands to the serial flash.
728 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
731 if (!byte_cnt || byte_cnt > 4)
733 if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
735 cont = cont ? SF_CONT : 0;
736 lock = lock ? SF_LOCK : 0;
737 t4_write_reg(adapter, SF_DATA, val);
738 t4_write_reg(adapter, SF_OP, lock |
739 cont | BYTECNT(byte_cnt - 1) | OP_WR);
740 return t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
744 * flash_wait_op - wait for a flash operation to complete
745 * @adapter: the adapter
746 * @attempts: max number of polls of the status register
747 * @delay: delay between polls in ms
749 * Wait for a flash operation to complete by polling the status register.
751 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
757 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
758 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
770 * t4_read_flash - read words from serial flash
771 * @adapter: the adapter
772 * @addr: the start address for the read
773 * @nwords: how many 32-bit words to read
774 * @data: where to store the read data
775 * @byte_oriented: whether to store data as bytes or as words
777 * Read the specified number of 32-bit words from the serial flash.
778 * If @byte_oriented is set the read data is stored as a byte array
779 * (i.e., big-endian), otherwise as 32-bit words in the platform's
782 static int t4_read_flash(struct adapter *adapter, unsigned int addr,
783 unsigned int nwords, u32 *data, int byte_oriented)
787 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
790 addr = swab32(addr) | SF_RD_DATA_FAST;
792 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
793 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
796 for ( ; nwords; nwords--, data++) {
797 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
799 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
803 *data = (__force __u32) (htonl(*data));
809 * t4_write_flash - write up to a page of data to the serial flash
810 * @adapter: the adapter
811 * @addr: the start address to write
812 * @n: length of data to write in bytes
813 * @data: the data to write
815 * Writes up to a page of data (256 bytes) to the serial flash starting
816 * at the given address. All the data must be written to the same page.
818 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
819 unsigned int n, const u8 *data)
823 unsigned int i, c, left, val, offset = addr & 0xff;
825 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
828 val = swab32(addr) | SF_PROG_PAGE;
830 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
831 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
834 for (left = n; left; left -= c) {
836 for (val = 0, i = 0; i < c; ++i)
837 val = (val << 8) + *data++;
839 ret = sf1_write(adapter, c, c != left, 1, val);
843 ret = flash_wait_op(adapter, 8, 1);
847 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
849 /* Read the page to verify the write succeeded */
850 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
854 if (memcmp(data - n, (u8 *)buf + offset, n)) {
855 dev_err(adapter->pdev_dev,
856 "failed to correctly write the flash page at %#x\n",
863 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
868 * t4_get_fw_version - read the firmware version
869 * @adapter: the adapter
870 * @vers: where to place the version
872 * Reads the FW version from flash.
874 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
876 return t4_read_flash(adapter, FLASH_FW_START +
877 offsetof(struct fw_hdr, fw_ver), 1,
882 * t4_get_tp_version - read the TP microcode version
883 * @adapter: the adapter
884 * @vers: where to place the version
886 * Reads the TP microcode version from flash.
888 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
890 return t4_read_flash(adapter, FLASH_FW_START +
891 offsetof(struct fw_hdr, tp_microcode_ver),
895 /* Is the given firmware API compatible with the one the driver was compiled
898 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
901 /* short circuit if it's the exact same firmware version */
902 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
905 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
906 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
907 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
914 /* The firmware in the filesystem is usable, but should it be installed?
915 * This routine explains itself in detail if it indicates the filesystem
916 * firmware should be installed.
918 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
923 if (!card_fw_usable) {
924 reason = "incompatible or unusable";
929 reason = "older than the version supported with this driver";
936 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
937 "installing firmware %u.%u.%u.%u on card.\n",
938 FW_HDR_FW_VER_MAJOR_GET(c), FW_HDR_FW_VER_MINOR_GET(c),
939 FW_HDR_FW_VER_MICRO_GET(c), FW_HDR_FW_VER_BUILD_GET(c), reason,
940 FW_HDR_FW_VER_MAJOR_GET(k), FW_HDR_FW_VER_MINOR_GET(k),
941 FW_HDR_FW_VER_MICRO_GET(k), FW_HDR_FW_VER_BUILD_GET(k));
946 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
947 const u8 *fw_data, unsigned int fw_size,
948 struct fw_hdr *card_fw, enum dev_state state,
951 int ret, card_fw_usable, fs_fw_usable;
952 const struct fw_hdr *fs_fw;
953 const struct fw_hdr *drv_fw;
955 drv_fw = &fw_info->fw_hdr;
957 /* Read the header of the firmware on the card */
958 ret = -t4_read_flash(adap, FLASH_FW_START,
959 sizeof(*card_fw) / sizeof(uint32_t),
960 (uint32_t *)card_fw, 1);
962 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
964 dev_err(adap->pdev_dev,
965 "Unable to read card's firmware header: %d\n", ret);
969 if (fw_data != NULL) {
970 fs_fw = (const void *)fw_data;
971 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
977 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
978 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
979 /* Common case: the firmware on the card is an exact match and
980 * the filesystem one is an exact match too, or the filesystem
981 * one is absent/incompatible.
983 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
984 should_install_fs_fw(adap, card_fw_usable,
985 be32_to_cpu(fs_fw->fw_ver),
986 be32_to_cpu(card_fw->fw_ver))) {
987 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
990 dev_err(adap->pdev_dev,
991 "failed to install firmware: %d\n", ret);
995 /* Installed successfully, update the cached header too. */
996 memcpy(card_fw, fs_fw, sizeof(*card_fw));
998 *reset = 0; /* already reset as part of load_fw */
1001 if (!card_fw_usable) {
1004 d = be32_to_cpu(drv_fw->fw_ver);
1005 c = be32_to_cpu(card_fw->fw_ver);
1006 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
1008 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
1010 "driver compiled with %d.%d.%d.%d, "
1011 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
1013 FW_HDR_FW_VER_MAJOR_GET(d), FW_HDR_FW_VER_MINOR_GET(d),
1014 FW_HDR_FW_VER_MICRO_GET(d), FW_HDR_FW_VER_BUILD_GET(d),
1015 FW_HDR_FW_VER_MAJOR_GET(c), FW_HDR_FW_VER_MINOR_GET(c),
1016 FW_HDR_FW_VER_MICRO_GET(c), FW_HDR_FW_VER_BUILD_GET(c),
1017 FW_HDR_FW_VER_MAJOR_GET(k), FW_HDR_FW_VER_MINOR_GET(k),
1018 FW_HDR_FW_VER_MICRO_GET(k), FW_HDR_FW_VER_BUILD_GET(k));
1023 /* We're using whatever's on the card and it's known to be good. */
1024 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
1025 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
1032 * t4_flash_erase_sectors - erase a range of flash sectors
1033 * @adapter: the adapter
1034 * @start: the first sector to erase
1035 * @end: the last sector to erase
1037 * Erases the sectors in the given inclusive range.
1039 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
1043 while (start <= end) {
1044 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
1045 (ret = sf1_write(adapter, 4, 0, 1,
1046 SF_ERASE_SECTOR | (start << 8))) != 0 ||
1047 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
1048 dev_err(adapter->pdev_dev,
1049 "erase of flash sector %d failed, error %d\n",
1055 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
1060 * t4_flash_cfg_addr - return the address of the flash configuration file
1061 * @adapter: the adapter
1063 * Return the address within the flash where the Firmware Configuration
1066 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
1068 if (adapter->params.sf_size == 0x100000)
1069 return FLASH_FPGA_CFG_START;
1071 return FLASH_CFG_START;
1075 * t4_load_fw - download firmware
1076 * @adap: the adapter
1077 * @fw_data: the firmware image to write
1080 * Write the supplied firmware image to the card's serial flash.
1082 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
1087 u8 first_page[SF_PAGE_SIZE];
1088 const __be32 *p = (const __be32 *)fw_data;
1089 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
1090 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
1091 unsigned int fw_img_start = adap->params.sf_fw_start;
1092 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
1095 dev_err(adap->pdev_dev, "FW image has no data\n");
1099 dev_err(adap->pdev_dev,
1100 "FW image size not multiple of 512 bytes\n");
1103 if (ntohs(hdr->len512) * 512 != size) {
1104 dev_err(adap->pdev_dev,
1105 "FW image size differs from size in FW header\n");
1108 if (size > FW_MAX_SIZE) {
1109 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
1114 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
1115 csum += ntohl(p[i]);
1117 if (csum != 0xffffffff) {
1118 dev_err(adap->pdev_dev,
1119 "corrupted firmware image, checksum %#x\n", csum);
1123 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
1124 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
1129 * We write the correct version at the end so the driver can see a bad
1130 * version if the FW write fails. Start by writing a copy of the
1131 * first page with a bad version.
1133 memcpy(first_page, fw_data, SF_PAGE_SIZE);
1134 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
1135 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
1139 addr = fw_img_start;
1140 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
1141 addr += SF_PAGE_SIZE;
1142 fw_data += SF_PAGE_SIZE;
1143 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
1148 ret = t4_write_flash(adap,
1149 fw_img_start + offsetof(struct fw_hdr, fw_ver),
1150 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
1153 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
1158 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1159 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG)
1162 * t4_link_start - apply link configuration to MAC/PHY
1163 * @phy: the PHY to setup
1164 * @mac: the MAC to setup
1165 * @lc: the requested link configuration
1167 * Set up a port's MAC and PHY according to a desired link configuration.
1168 * - If the PHY can auto-negotiate first decide what to advertise, then
1169 * enable/disable auto-negotiation as desired, and reset.
1170 * - If the PHY does not auto-negotiate just reset it.
1171 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1172 * otherwise do it later based on the outcome of auto-negotiation.
1174 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1175 struct link_config *lc)
1177 struct fw_port_cmd c;
1178 unsigned int fc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO);
1181 if (lc->requested_fc & PAUSE_RX)
1182 fc |= FW_PORT_CAP_FC_RX;
1183 if (lc->requested_fc & PAUSE_TX)
1184 fc |= FW_PORT_CAP_FC_TX;
1186 memset(&c, 0, sizeof(c));
1187 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
1188 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
1189 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1192 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1193 c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc);
1194 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1195 } else if (lc->autoneg == AUTONEG_DISABLE) {
1196 c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi);
1197 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1199 c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi);
1201 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1205 * t4_restart_aneg - restart autonegotiation
1206 * @adap: the adapter
1207 * @mbox: mbox to use for the FW command
1208 * @port: the port id
1210 * Restarts autonegotiation for the selected port.
1212 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
1214 struct fw_port_cmd c;
1216 memset(&c, 0, sizeof(c));
1217 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
1218 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
1219 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1221 c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG);
1222 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1225 typedef void (*int_handler_t)(struct adapter *adap);
1228 unsigned int mask; /* bits to check in interrupt status */
1229 const char *msg; /* message to print or NULL */
1230 short stat_idx; /* stat counter to increment or -1 */
1231 unsigned short fatal; /* whether the condition reported is fatal */
1232 int_handler_t int_handler; /* platform-specific int handler */
1236 * t4_handle_intr_status - table driven interrupt handler
1237 * @adapter: the adapter that generated the interrupt
1238 * @reg: the interrupt status register to process
1239 * @acts: table of interrupt actions
1241 * A table driven interrupt handler that applies a set of masks to an
1242 * interrupt status word and performs the corresponding actions if the
1243 * interrupts described by the mask have occurred. The actions include
1244 * optionally emitting a warning or alert message. The table is terminated
1245 * by an entry specifying mask 0. Returns the number of fatal interrupt
1248 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
1249 const struct intr_info *acts)
1252 unsigned int mask = 0;
1253 unsigned int status = t4_read_reg(adapter, reg);
1255 for ( ; acts->mask; ++acts) {
1256 if (!(status & acts->mask))
1260 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1261 status & acts->mask);
1262 } else if (acts->msg && printk_ratelimit())
1263 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1264 status & acts->mask);
1265 if (acts->int_handler)
1266 acts->int_handler(adapter);
1270 if (status) /* clear processed interrupts */
1271 t4_write_reg(adapter, reg, status);
1276 * Interrupt handler for the PCIE module.
1278 static void pcie_intr_handler(struct adapter *adapter)
1280 static const struct intr_info sysbus_intr_info[] = {
1281 { RNPP, "RXNP array parity error", -1, 1 },
1282 { RPCP, "RXPC array parity error", -1, 1 },
1283 { RCIP, "RXCIF array parity error", -1, 1 },
1284 { RCCP, "Rx completions control array parity error", -1, 1 },
1285 { RFTP, "RXFT array parity error", -1, 1 },
1288 static const struct intr_info pcie_port_intr_info[] = {
1289 { TPCP, "TXPC array parity error", -1, 1 },
1290 { TNPP, "TXNP array parity error", -1, 1 },
1291 { TFTP, "TXFT array parity error", -1, 1 },
1292 { TCAP, "TXCA array parity error", -1, 1 },
1293 { TCIP, "TXCIF array parity error", -1, 1 },
1294 { RCAP, "RXCA array parity error", -1, 1 },
1295 { OTDD, "outbound request TLP discarded", -1, 1 },
1296 { RDPE, "Rx data parity error", -1, 1 },
1297 { TDUE, "Tx uncorrectable data error", -1, 1 },
1300 static const struct intr_info pcie_intr_info[] = {
1301 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
1302 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
1303 { MSIDATAPERR, "MSI data parity error", -1, 1 },
1304 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
1305 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
1306 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
1307 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
1308 { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
1309 { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
1310 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
1311 { CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
1312 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
1313 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
1314 { DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
1315 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
1316 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
1317 { HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
1318 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
1319 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
1320 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
1321 { FIDPERR, "PCI FID parity error", -1, 1 },
1322 { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
1323 { MATAGPERR, "PCI MA tag parity error", -1, 1 },
1324 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
1325 { RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
1326 { RXWRPERR, "PCI Rx write parity error", -1, 1 },
1327 { RPLPERR, "PCI replay buffer parity error", -1, 1 },
1328 { PCIESINT, "PCI core secondary fault", -1, 1 },
1329 { PCIEPINT, "PCI core primary fault", -1, 1 },
1330 { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 },
1334 static struct intr_info t5_pcie_intr_info[] = {
1335 { MSTGRPPERR, "Master Response Read Queue parity error",
1337 { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
1338 { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
1339 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
1340 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
1341 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
1342 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
1343 { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
1345 { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
1347 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
1348 { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
1349 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
1350 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
1351 { DREQWRPERR, "PCI DMA channel write request parity error",
1353 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
1354 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
1355 { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
1356 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
1357 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
1358 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
1359 { FIDPERR, "PCI FID parity error", -1, 1 },
1360 { VFIDPERR, "PCI INTx clear parity error", -1, 1 },
1361 { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
1362 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
1363 { IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
1365 { IPRXDATAGRPPERR, "PCI IP Rx data group parity error", -1, 1 },
1366 { RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
1367 { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
1368 { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
1369 { READRSPERR, "Outbound read error", -1, 0 },
1375 fat = t4_handle_intr_status(adapter,
1376 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
1378 t4_handle_intr_status(adapter,
1379 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
1380 pcie_port_intr_info) +
1381 t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
1382 is_t4(adapter->params.chip) ?
1383 pcie_intr_info : t5_pcie_intr_info);
1386 t4_fatal_err(adapter);
1390 * TP interrupt handler.
1392 static void tp_intr_handler(struct adapter *adapter)
1394 static const struct intr_info tp_intr_info[] = {
1395 { 0x3fffffff, "TP parity error", -1, 1 },
1396 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
1400 if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info))
1401 t4_fatal_err(adapter);
1405 * SGE interrupt handler.
1407 static void sge_intr_handler(struct adapter *adapter)
1411 static const struct intr_info sge_intr_info[] = {
1412 { ERR_CPL_EXCEED_IQE_SIZE,
1413 "SGE received CPL exceeding IQE size", -1, 1 },
1414 { ERR_INVALID_CIDX_INC,
1415 "SGE GTS CIDX increment too large", -1, 0 },
1416 { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
1417 { DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
1418 { DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
1419 { ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
1420 { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,
1421 "SGE IQID > 1023 received CPL for FL", -1, 0 },
1422 { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
1424 { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
1426 { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
1428 { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
1430 { ERR_ING_CTXT_PRIO,
1431 "SGE too many priority ingress contexts", -1, 0 },
1432 { ERR_EGR_CTXT_PRIO,
1433 "SGE too many priority egress contexts", -1, 0 },
1434 { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
1435 { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
1439 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) |
1440 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32);
1442 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
1443 (unsigned long long)v);
1444 t4_write_reg(adapter, SGE_INT_CAUSE1, v);
1445 t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32);
1448 if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) ||
1450 t4_fatal_err(adapter);
1454 * CIM interrupt handler.
1456 static void cim_intr_handler(struct adapter *adapter)
1458 static const struct intr_info cim_intr_info[] = {
1459 { PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
1460 { OBQPARERR, "CIM OBQ parity error", -1, 1 },
1461 { IBQPARERR, "CIM IBQ parity error", -1, 1 },
1462 { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
1463 { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
1464 { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
1465 { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
1468 static const struct intr_info cim_upintr_info[] = {
1469 { RSVDSPACEINT, "CIM reserved space access", -1, 1 },
1470 { ILLTRANSINT, "CIM illegal transaction", -1, 1 },
1471 { ILLWRINT, "CIM illegal write", -1, 1 },
1472 { ILLRDINT, "CIM illegal read", -1, 1 },
1473 { ILLRDBEINT, "CIM illegal read BE", -1, 1 },
1474 { ILLWRBEINT, "CIM illegal write BE", -1, 1 },
1475 { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
1476 { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
1477 { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
1478 { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
1479 { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
1480 { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
1481 { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
1482 { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
1483 { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
1484 { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
1485 { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
1486 { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
1487 { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
1488 { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
1489 { SGLRDPLINT , "CIM single read from PL space", -1, 1 },
1490 { SGLWRPLINT , "CIM single write to PL space", -1, 1 },
1491 { BLKRDPLINT , "CIM block read from PL space", -1, 1 },
1492 { BLKWRPLINT , "CIM block write to PL space", -1, 1 },
1493 { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
1494 { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
1495 { TIMEOUTINT , "CIM PIF timeout", -1, 1 },
1496 { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
1502 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
1504 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE,
1507 t4_fatal_err(adapter);
1511 * ULP RX interrupt handler.
1513 static void ulprx_intr_handler(struct adapter *adapter)
1515 static const struct intr_info ulprx_intr_info[] = {
1516 { 0x1800000, "ULPRX context error", -1, 1 },
1517 { 0x7fffff, "ULPRX parity error", -1, 1 },
1521 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info))
1522 t4_fatal_err(adapter);
1526 * ULP TX interrupt handler.
1528 static void ulptx_intr_handler(struct adapter *adapter)
1530 static const struct intr_info ulptx_intr_info[] = {
1531 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
1533 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
1535 { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
1537 { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
1539 { 0xfffffff, "ULPTX parity error", -1, 1 },
1543 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info))
1544 t4_fatal_err(adapter);
1548 * PM TX interrupt handler.
1550 static void pmtx_intr_handler(struct adapter *adapter)
1552 static const struct intr_info pmtx_intr_info[] = {
1553 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
1554 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
1555 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
1556 { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
1557 { PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 },
1558 { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
1559 { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 },
1560 { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
1561 { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
1565 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info))
1566 t4_fatal_err(adapter);
1570 * PM RX interrupt handler.
1572 static void pmrx_intr_handler(struct adapter *adapter)
1574 static const struct intr_info pmrx_intr_info[] = {
1575 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
1576 { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 },
1577 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
1578 { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 },
1579 { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
1580 { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
1584 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info))
1585 t4_fatal_err(adapter);
1589 * CPL switch interrupt handler.
1591 static void cplsw_intr_handler(struct adapter *adapter)
1593 static const struct intr_info cplsw_intr_info[] = {
1594 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
1595 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
1596 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
1597 { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
1598 { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
1599 { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
1603 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info))
1604 t4_fatal_err(adapter);
1608 * LE interrupt handler.
1610 static void le_intr_handler(struct adapter *adap)
1612 static const struct intr_info le_intr_info[] = {
1613 { LIPMISS, "LE LIP miss", -1, 0 },
1614 { LIP0, "LE 0 LIP error", -1, 0 },
1615 { PARITYERR, "LE parity error", -1, 1 },
1616 { UNKNOWNCMD, "LE unknown command", -1, 1 },
1617 { REQQPARERR, "LE request queue parity error", -1, 1 },
1621 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info))
1626 * MPS interrupt handler.
1628 static void mps_intr_handler(struct adapter *adapter)
1630 static const struct intr_info mps_rx_intr_info[] = {
1631 { 0xffffff, "MPS Rx parity error", -1, 1 },
1634 static const struct intr_info mps_tx_intr_info[] = {
1635 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
1636 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
1637 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
1638 { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 },
1639 { BUBBLE, "MPS Tx underflow", -1, 1 },
1640 { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
1641 { FRMERR, "MPS Tx framing error", -1, 1 },
1644 static const struct intr_info mps_trc_intr_info[] = {
1645 { FILTMEM, "MPS TRC filter parity error", -1, 1 },
1646 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
1647 { MISCPERR, "MPS TRC misc parity error", -1, 1 },
1650 static const struct intr_info mps_stat_sram_intr_info[] = {
1651 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
1654 static const struct intr_info mps_stat_tx_intr_info[] = {
1655 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
1658 static const struct intr_info mps_stat_rx_intr_info[] = {
1659 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
1662 static const struct intr_info mps_cls_intr_info[] = {
1663 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
1664 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
1665 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
1671 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE,
1673 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE,
1675 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE,
1676 mps_trc_intr_info) +
1677 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM,
1678 mps_stat_sram_intr_info) +
1679 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
1680 mps_stat_tx_intr_info) +
1681 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
1682 mps_stat_rx_intr_info) +
1683 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE,
1686 t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT |
1687 RXINT | TXINT | STATINT);
1688 t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */
1690 t4_fatal_err(adapter);
1693 #define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE)
1696 * EDC/MC interrupt handler.
1698 static void mem_intr_handler(struct adapter *adapter, int idx)
1700 static const char name[3][5] = { "EDC0", "EDC1", "MC" };
1702 unsigned int addr, cnt_addr, v;
1704 if (idx <= MEM_EDC1) {
1705 addr = EDC_REG(EDC_INT_CAUSE, idx);
1706 cnt_addr = EDC_REG(EDC_ECC_STATUS, idx);
1708 addr = MC_INT_CAUSE;
1709 cnt_addr = MC_ECC_STATUS;
1712 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
1713 if (v & PERR_INT_CAUSE)
1714 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
1716 if (v & ECC_CE_INT_CAUSE) {
1717 u32 cnt = ECC_CECNT_GET(t4_read_reg(adapter, cnt_addr));
1719 t4_write_reg(adapter, cnt_addr, ECC_CECNT_MASK);
1720 if (printk_ratelimit())
1721 dev_warn(adapter->pdev_dev,
1722 "%u %s correctable ECC data error%s\n",
1723 cnt, name[idx], cnt > 1 ? "s" : "");
1725 if (v & ECC_UE_INT_CAUSE)
1726 dev_alert(adapter->pdev_dev,
1727 "%s uncorrectable ECC data error\n", name[idx]);
1729 t4_write_reg(adapter, addr, v);
1730 if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE))
1731 t4_fatal_err(adapter);
1735 * MA interrupt handler.
1737 static void ma_intr_handler(struct adapter *adap)
1739 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE);
1741 if (status & MEM_PERR_INT_CAUSE)
1742 dev_alert(adap->pdev_dev,
1743 "MA parity error, parity status %#x\n",
1744 t4_read_reg(adap, MA_PARITY_ERROR_STATUS));
1745 if (status & MEM_WRAP_INT_CAUSE) {
1746 v = t4_read_reg(adap, MA_INT_WRAP_STATUS);
1747 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
1748 "client %u to address %#x\n",
1749 MEM_WRAP_CLIENT_NUM_GET(v),
1750 MEM_WRAP_ADDRESS_GET(v) << 4);
1752 t4_write_reg(adap, MA_INT_CAUSE, status);
1757 * SMB interrupt handler.
1759 static void smb_intr_handler(struct adapter *adap)
1761 static const struct intr_info smb_intr_info[] = {
1762 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
1763 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
1764 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
1768 if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info))
1773 * NC-SI interrupt handler.
1775 static void ncsi_intr_handler(struct adapter *adap)
1777 static const struct intr_info ncsi_intr_info[] = {
1778 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
1779 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
1780 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
1781 { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
1785 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info))
1790 * XGMAC interrupt handler.
1792 static void xgmac_intr_handler(struct adapter *adap, int port)
1794 u32 v, int_cause_reg;
1796 if (is_t4(adap->params.chip))
1797 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE);
1799 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE);
1801 v = t4_read_reg(adap, int_cause_reg);
1803 v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR;
1807 if (v & TXFIFO_PRTY_ERR)
1808 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
1810 if (v & RXFIFO_PRTY_ERR)
1811 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
1813 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v);
1818 * PL interrupt handler.
1820 static void pl_intr_handler(struct adapter *adap)
1822 static const struct intr_info pl_intr_info[] = {
1823 { FATALPERR, "T4 fatal parity error", -1, 1 },
1824 { PERRVFID, "PL VFID_MAP parity error", -1, 1 },
1828 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info))
1832 #define PF_INTR_MASK (PFSW)
1833 #define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
1834 EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \
1835 CPL_SWITCH | SGE | ULP_TX)
1838 * t4_slow_intr_handler - control path interrupt handler
1839 * @adapter: the adapter
1841 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
1842 * The designation 'slow' is because it involves register reads, while
1843 * data interrupts typically don't involve any MMIOs.
1845 int t4_slow_intr_handler(struct adapter *adapter)
1847 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE);
1849 if (!(cause & GLBL_INTR_MASK))
1852 cim_intr_handler(adapter);
1854 mps_intr_handler(adapter);
1856 ncsi_intr_handler(adapter);
1858 pl_intr_handler(adapter);
1860 smb_intr_handler(adapter);
1862 xgmac_intr_handler(adapter, 0);
1864 xgmac_intr_handler(adapter, 1);
1865 if (cause & XGMAC_KR0)
1866 xgmac_intr_handler(adapter, 2);
1867 if (cause & XGMAC_KR1)
1868 xgmac_intr_handler(adapter, 3);
1870 pcie_intr_handler(adapter);
1872 mem_intr_handler(adapter, MEM_MC);
1874 mem_intr_handler(adapter, MEM_EDC0);
1876 mem_intr_handler(adapter, MEM_EDC1);
1878 le_intr_handler(adapter);
1880 tp_intr_handler(adapter);
1882 ma_intr_handler(adapter);
1884 pmtx_intr_handler(adapter);
1886 pmrx_intr_handler(adapter);
1888 ulprx_intr_handler(adapter);
1889 if (cause & CPL_SWITCH)
1890 cplsw_intr_handler(adapter);
1892 sge_intr_handler(adapter);
1894 ulptx_intr_handler(adapter);
1896 /* Clear the interrupts just processed for which we are the master. */
1897 t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK);
1898 (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */
1903 * t4_intr_enable - enable interrupts
1904 * @adapter: the adapter whose interrupts should be enabled
1906 * Enable PF-specific interrupts for the calling function and the top-level
1907 * interrupt concentrator for global interrupts. Interrupts are already
1908 * enabled at each module, here we just enable the roots of the interrupt
1911 * Note: this function should be called only when the driver manages
1912 * non PF-specific interrupts from the various HW modules. Only one PCI
1913 * function at a time should be doing this.
1915 void t4_intr_enable(struct adapter *adapter)
1917 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
1919 t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE |
1920 ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 |
1921 ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 |
1922 ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 |
1923 ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |
1924 ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |
1925 ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR |
1926 DBFIFO_HP_INT | DBFIFO_LP_INT |
1928 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK);
1929 t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf);
1933 * t4_intr_disable - disable interrupts
1934 * @adapter: the adapter whose interrupts should be disabled
1936 * Disable interrupts. We only disable the top-level interrupt
1937 * concentrators. The caller must be a PCI function managing global
1940 void t4_intr_disable(struct adapter *adapter)
1942 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
1944 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0);
1945 t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0);
1949 * hash_mac_addr - return the hash value of a MAC address
1950 * @addr: the 48-bit Ethernet MAC address
1952 * Hashes a MAC address according to the hash function used by HW inexact
1953 * (hash) address matching.
1955 static int hash_mac_addr(const u8 *addr)
1957 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1958 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1966 * t4_config_rss_range - configure a portion of the RSS mapping table
1967 * @adapter: the adapter
1968 * @mbox: mbox to use for the FW command
1969 * @viid: virtual interface whose RSS subtable is to be written
1970 * @start: start entry in the table to write
1971 * @n: how many table entries to write
1972 * @rspq: values for the response queue lookup table
1973 * @nrspq: number of values in @rspq
1975 * Programs the selected part of the VI's RSS mapping table with the
1976 * provided values. If @nrspq < @n the supplied values are used repeatedly
1977 * until the full table range is populated.
1979 * The caller must ensure the values in @rspq are in the range allowed for
1982 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1983 int start, int n, const u16 *rspq, unsigned int nrspq)
1986 const u16 *rsp = rspq;
1987 const u16 *rsp_end = rspq + nrspq;
1988 struct fw_rss_ind_tbl_cmd cmd;
1990 memset(&cmd, 0, sizeof(cmd));
1991 cmd.op_to_viid = htonl(FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
1992 FW_CMD_REQUEST | FW_CMD_WRITE |
1993 FW_RSS_IND_TBL_CMD_VIID(viid));
1994 cmd.retval_len16 = htonl(FW_LEN16(cmd));
1996 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
1998 int nq = min(n, 32);
1999 __be32 *qp = &cmd.iq0_to_iq2;
2001 cmd.niqid = htons(nq);
2002 cmd.startidx = htons(start);
2010 v = FW_RSS_IND_TBL_CMD_IQ0(*rsp);
2011 if (++rsp >= rsp_end)
2013 v |= FW_RSS_IND_TBL_CMD_IQ1(*rsp);
2014 if (++rsp >= rsp_end)
2016 v |= FW_RSS_IND_TBL_CMD_IQ2(*rsp);
2017 if (++rsp >= rsp_end)
2024 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2032 * t4_config_glbl_rss - configure the global RSS mode
2033 * @adapter: the adapter
2034 * @mbox: mbox to use for the FW command
2035 * @mode: global RSS mode
2036 * @flags: mode-specific flags
2038 * Sets the global RSS mode.
2040 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
2043 struct fw_rss_glb_config_cmd c;
2045 memset(&c, 0, sizeof(c));
2046 c.op_to_write = htonl(FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
2047 FW_CMD_REQUEST | FW_CMD_WRITE);
2048 c.retval_len16 = htonl(FW_LEN16(c));
2049 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
2050 c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
2051 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
2052 c.u.basicvirtual.mode_pkd =
2053 htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
2054 c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags);
2057 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2061 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
2062 * @adap: the adapter
2063 * @v4: holds the TCP/IP counter values
2064 * @v6: holds the TCP/IPv6 counter values
2066 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
2067 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
2069 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
2070 struct tp_tcp_stats *v6)
2072 u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1];
2074 #define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST)
2075 #define STAT(x) val[STAT_IDX(x)]
2076 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
2079 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
2080 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST);
2081 v4->tcpOutRsts = STAT(OUT_RST);
2082 v4->tcpInSegs = STAT64(IN_SEG);
2083 v4->tcpOutSegs = STAT64(OUT_SEG);
2084 v4->tcpRetransSegs = STAT64(RXT_SEG);
2087 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
2088 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST);
2089 v6->tcpOutRsts = STAT(OUT_RST);
2090 v6->tcpInSegs = STAT64(IN_SEG);
2091 v6->tcpOutSegs = STAT64(OUT_SEG);
2092 v6->tcpRetransSegs = STAT64(RXT_SEG);
2100 * t4_read_mtu_tbl - returns the values in the HW path MTU table
2101 * @adap: the adapter
2102 * @mtus: where to store the MTU values
2103 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
2105 * Reads the HW path MTU table.
2107 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
2112 for (i = 0; i < NMTUS; ++i) {
2113 t4_write_reg(adap, TP_MTU_TABLE,
2114 MTUINDEX(0xff) | MTUVALUE(i));
2115 v = t4_read_reg(adap, TP_MTU_TABLE);
2116 mtus[i] = MTUVALUE_GET(v);
2118 mtu_log[i] = MTUWIDTH_GET(v);
2123 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
2124 * @adap: the adapter
2125 * @addr: the indirect TP register address
2126 * @mask: specifies the field within the register to modify
2127 * @val: new value for the field
2129 * Sets a field of an indirect TP register to the given value.
2131 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
2132 unsigned int mask, unsigned int val)
2134 t4_write_reg(adap, TP_PIO_ADDR, addr);
2135 val |= t4_read_reg(adap, TP_PIO_DATA) & ~mask;
2136 t4_write_reg(adap, TP_PIO_DATA, val);
2140 * init_cong_ctrl - initialize congestion control parameters
2141 * @a: the alpha values for congestion control
2142 * @b: the beta values for congestion control
2144 * Initialize the congestion control parameters.
2146 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2148 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
2173 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
2176 b[13] = b[14] = b[15] = b[16] = 3;
2177 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
2178 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
2183 /* The minimum additive increment value for the congestion control table */
2184 #define CC_MIN_INCR 2U
2187 * t4_load_mtus - write the MTU and congestion control HW tables
2188 * @adap: the adapter
2189 * @mtus: the values for the MTU table
2190 * @alpha: the values for the congestion control alpha parameter
2191 * @beta: the values for the congestion control beta parameter
2193 * Write the HW MTU table with the supplied MTUs and the high-speed
2194 * congestion control table with the supplied alpha, beta, and MTUs.
2195 * We write the two tables together because the additive increments
2196 * depend on the MTUs.
2198 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
2199 const unsigned short *alpha, const unsigned short *beta)
2201 static const unsigned int avg_pkts[NCCTRL_WIN] = {
2202 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
2203 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
2204 28672, 40960, 57344, 81920, 114688, 163840, 229376
2209 for (i = 0; i < NMTUS; ++i) {
2210 unsigned int mtu = mtus[i];
2211 unsigned int log2 = fls(mtu);
2213 if (!(mtu & ((1 << log2) >> 2))) /* round */
2215 t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) |
2216 MTUWIDTH(log2) | MTUVALUE(mtu));
2218 for (w = 0; w < NCCTRL_WIN; ++w) {
2221 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
2224 t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) |
2225 (w << 16) | (beta[w] << 13) | inc);
2231 * get_mps_bg_map - return the buffer groups associated with a port
2232 * @adap: the adapter
2233 * @idx: the port index
2235 * Returns a bitmap indicating which MPS buffer groups are associated
2236 * with the given port. Bit i is set if buffer group i is used by the
2239 static unsigned int get_mps_bg_map(struct adapter *adap, int idx)
2241 u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL));
2244 return idx == 0 ? 0xf : 0;
2246 return idx < 2 ? (3 << (2 * idx)) : 0;
2251 * t4_get_port_stats - collect port statistics
2252 * @adap: the adapter
2253 * @idx: the port index
2254 * @p: the stats structure to fill
2256 * Collect statistics related to the given port from HW.
2258 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2260 u32 bgmap = get_mps_bg_map(adap, idx);
2262 #define GET_STAT(name) \
2263 t4_read_reg64(adap, \
2264 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
2265 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
2266 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
2268 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2269 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2270 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2271 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2272 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2273 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2274 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2275 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2276 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2277 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2278 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2279 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2280 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2281 p->tx_drop = GET_STAT(TX_PORT_DROP);
2282 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2283 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2284 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2285 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2286 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2287 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2288 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2289 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2290 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2292 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2293 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2294 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2295 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2296 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2297 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2298 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2299 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2300 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2301 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2302 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2303 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2304 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2305 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2306 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2307 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2308 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2309 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2310 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2311 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2312 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2313 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2314 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2315 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2316 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2317 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2318 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2320 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2321 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2322 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2323 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2324 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2325 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2326 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2327 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2334 * t4_wol_magic_enable - enable/disable magic packet WoL
2335 * @adap: the adapter
2336 * @port: the physical port index
2337 * @addr: MAC address expected in magic packets, %NULL to disable
2339 * Enables/disables magic packet wake-on-LAN for the selected port.
2341 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
2344 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
2346 if (is_t4(adap->params.chip)) {
2347 mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO);
2348 mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI);
2349 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
2351 mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO);
2352 mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI);
2353 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
2357 t4_write_reg(adap, mag_id_reg_l,
2358 (addr[2] << 24) | (addr[3] << 16) |
2359 (addr[4] << 8) | addr[5]);
2360 t4_write_reg(adap, mag_id_reg_h,
2361 (addr[0] << 8) | addr[1]);
2363 t4_set_reg_field(adap, port_cfg_reg, MAGICEN,
2364 addr ? MAGICEN : 0);
2368 * t4_wol_pat_enable - enable/disable pattern-based WoL
2369 * @adap: the adapter
2370 * @port: the physical port index
2371 * @map: bitmap of which HW pattern filters to set
2372 * @mask0: byte mask for bytes 0-63 of a packet
2373 * @mask1: byte mask for bytes 64-127 of a packet
2374 * @crc: Ethernet CRC for selected bytes
2375 * @enable: enable/disable switch
2377 * Sets the pattern filters indicated in @map to mask out the bytes
2378 * specified in @mask0/@mask1 in received packets and compare the CRC of
2379 * the resulting packet against @crc. If @enable is %true pattern-based
2380 * WoL is enabled, otherwise disabled.
2382 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2383 u64 mask0, u64 mask1, unsigned int crc, bool enable)
2388 if (is_t4(adap->params.chip))
2389 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
2391 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
2394 t4_set_reg_field(adap, port_cfg_reg, PATEN, 0);
2400 #define EPIO_REG(name) \
2401 (is_t4(adap->params.chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \
2402 T5_PORT_REG(port, MAC_PORT_EPIO_##name))
2404 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
2405 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
2406 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
2408 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
2412 /* write byte masks */
2413 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
2414 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR);
2415 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2416 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
2420 t4_write_reg(adap, EPIO_REG(DATA0), crc);
2421 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR);
2422 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2423 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
2428 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN);
2432 /* t4_mk_filtdelwr - create a delete filter WR
2433 * @ftid: the filter ID
2434 * @wr: the filter work request to populate
2435 * @qid: ingress queue to receive the delete notification
2437 * Creates a filter work request to delete the supplied filter. If @qid is
2438 * negative the delete notification is suppressed.
2440 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
2442 memset(wr, 0, sizeof(*wr));
2443 wr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
2444 wr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*wr) / 16));
2445 wr->tid_to_iq = htonl(V_FW_FILTER_WR_TID(ftid) |
2446 V_FW_FILTER_WR_NOREPLY(qid < 0));
2447 wr->del_filter_to_l2tix = htonl(F_FW_FILTER_WR_DEL_FILTER);
2449 wr->rx_chan_rx_rpl_iq = htons(V_FW_FILTER_WR_RX_RPL_IQ(qid));
2452 #define INIT_CMD(var, cmd, rd_wr) do { \
2453 (var).op_to_write = htonl(FW_CMD_OP(FW_##cmd##_CMD) | \
2454 FW_CMD_REQUEST | FW_CMD_##rd_wr); \
2455 (var).retval_len16 = htonl(FW_LEN16(var)); \
2458 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
2461 struct fw_ldst_cmd c;
2463 memset(&c, 0, sizeof(c));
2464 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2466 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE));
2467 c.cycles_to_len16 = htonl(FW_LEN16(c));
2468 c.u.addrval.addr = htonl(addr);
2469 c.u.addrval.val = htonl(val);
2471 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2475 * t4_mem_win_read_len - read memory through PCIE memory window
2476 * @adap: the adapter
2477 * @addr: address of first byte requested aligned on 32b.
2478 * @data: len bytes to hold the data read
2479 * @len: amount of data to read from window. Must be <=
2480 * MEMWIN0_APERATURE after adjusting for 16B for T4 and
2481 * 128B for T5 alignment requirements of the the memory window.
2483 * Read len bytes of data from MC starting at @addr.
2485 int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len)
2488 u32 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
2490 /* Align on a 2KB boundary.
2492 off = addr & MEMWIN0_APERTURE;
2493 if ((addr & 3) || (len + off) > MEMWIN0_APERTURE)
2496 t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
2497 (addr & ~MEMWIN0_APERTURE) | win_pf);
2498 t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
2500 for (i = 0; i < len; i += 4)
2501 *data++ = (__force __be32) t4_read_reg(adap,
2502 (MEMWIN0_BASE + off + i));
2508 * t4_mdio_rd - read a PHY register through MDIO
2509 * @adap: the adapter
2510 * @mbox: mailbox to use for the FW command
2511 * @phy_addr: the PHY address
2512 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2513 * @reg: the register to read
2514 * @valp: where to store the value
2516 * Issues a FW command through the given mailbox to read a PHY register.
2518 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2519 unsigned int mmd, unsigned int reg, u16 *valp)
2522 struct fw_ldst_cmd c;
2524 memset(&c, 0, sizeof(c));
2525 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2526 FW_CMD_READ | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2527 c.cycles_to_len16 = htonl(FW_LEN16(c));
2528 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2529 FW_LDST_CMD_MMD(mmd));
2530 c.u.mdio.raddr = htons(reg);
2532 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2534 *valp = ntohs(c.u.mdio.rval);
2539 * t4_mdio_wr - write a PHY register through MDIO
2540 * @adap: the adapter
2541 * @mbox: mailbox to use for the FW command
2542 * @phy_addr: the PHY address
2543 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2544 * @reg: the register to write
2545 * @valp: value to write
2547 * Issues a FW command through the given mailbox to write a PHY register.
2549 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2550 unsigned int mmd, unsigned int reg, u16 val)
2552 struct fw_ldst_cmd c;
2554 memset(&c, 0, sizeof(c));
2555 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2556 FW_CMD_WRITE | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2557 c.cycles_to_len16 = htonl(FW_LEN16(c));
2558 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2559 FW_LDST_CMD_MMD(mmd));
2560 c.u.mdio.raddr = htons(reg);
2561 c.u.mdio.rval = htons(val);
2563 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2567 * t4_fw_hello - establish communication with FW
2568 * @adap: the adapter
2569 * @mbox: mailbox to use for the FW command
2570 * @evt_mbox: mailbox to receive async FW events
2571 * @master: specifies the caller's willingness to be the device master
2572 * @state: returns the current device state (if non-NULL)
2574 * Issues a command to establish communication with FW. Returns either
2575 * an error (negative integer) or the mailbox of the Master PF.
2577 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2578 enum dev_master master, enum dev_state *state)
2581 struct fw_hello_cmd c;
2583 unsigned int master_mbox;
2584 int retries = FW_CMD_HELLO_RETRIES;
2587 memset(&c, 0, sizeof(c));
2588 INIT_CMD(c, HELLO, WRITE);
2589 c.err_to_clearinit = htonl(
2590 FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2591 FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2592 FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2593 FW_HELLO_CMD_MBMASTER_MASK) |
2594 FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2595 FW_HELLO_CMD_STAGE(fw_hello_cmd_stage_os) |
2596 FW_HELLO_CMD_CLEARINIT);
2599 * Issue the HELLO command to the firmware. If it's not successful
2600 * but indicates that we got a "busy" or "timeout" condition, retry
2601 * the HELLO until we exhaust our retry limit.
2603 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2605 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2610 v = ntohl(c.err_to_clearinit);
2611 master_mbox = FW_HELLO_CMD_MBMASTER_GET(v);
2613 if (v & FW_HELLO_CMD_ERR)
2614 *state = DEV_STATE_ERR;
2615 else if (v & FW_HELLO_CMD_INIT)
2616 *state = DEV_STATE_INIT;
2618 *state = DEV_STATE_UNINIT;
2622 * If we're not the Master PF then we need to wait around for the
2623 * Master PF Driver to finish setting up the adapter.
2625 * Note that we also do this wait if we're a non-Master-capable PF and
2626 * there is no current Master PF; a Master PF may show up momentarily
2627 * and we wouldn't want to fail pointlessly. (This can happen when an
2628 * OS loads lots of different drivers rapidly at the same time). In
2629 * this case, the Master PF returned by the firmware will be
2630 * FW_PCIE_FW_MASTER_MASK so the test below will work ...
2632 if ((v & (FW_HELLO_CMD_ERR|FW_HELLO_CMD_INIT)) == 0 &&
2633 master_mbox != mbox) {
2634 int waiting = FW_CMD_HELLO_TIMEOUT;
2637 * Wait for the firmware to either indicate an error or
2638 * initialized state. If we see either of these we bail out
2639 * and report the issue to the caller. If we exhaust the
2640 * "hello timeout" and we haven't exhausted our retries, try
2641 * again. Otherwise bail with a timeout error.
2650 * If neither Error nor Initialialized are indicated
2651 * by the firmware keep waiting till we exaust our
2652 * timeout ... and then retry if we haven't exhausted
2655 pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
2656 if (!(pcie_fw & (FW_PCIE_FW_ERR|FW_PCIE_FW_INIT))) {
2667 * We either have an Error or Initialized condition
2668 * report errors preferentially.
2671 if (pcie_fw & FW_PCIE_FW_ERR)
2672 *state = DEV_STATE_ERR;
2673 else if (pcie_fw & FW_PCIE_FW_INIT)
2674 *state = DEV_STATE_INIT;
2678 * If we arrived before a Master PF was selected and
2679 * there's not a valid Master PF, grab its identity
2682 if (master_mbox == FW_PCIE_FW_MASTER_MASK &&
2683 (pcie_fw & FW_PCIE_FW_MASTER_VLD))
2684 master_mbox = FW_PCIE_FW_MASTER_GET(pcie_fw);
2693 * t4_fw_bye - end communication with FW
2694 * @adap: the adapter
2695 * @mbox: mailbox to use for the FW command
2697 * Issues a command to terminate communication with FW.
2699 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2701 struct fw_bye_cmd c;
2703 memset(&c, 0, sizeof(c));
2704 INIT_CMD(c, BYE, WRITE);
2705 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2709 * t4_init_cmd - ask FW to initialize the device
2710 * @adap: the adapter
2711 * @mbox: mailbox to use for the FW command
2713 * Issues a command to FW to partially initialize the device. This
2714 * performs initialization that generally doesn't depend on user input.
2716 int t4_early_init(struct adapter *adap, unsigned int mbox)
2718 struct fw_initialize_cmd c;
2720 memset(&c, 0, sizeof(c));
2721 INIT_CMD(c, INITIALIZE, WRITE);
2722 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2726 * t4_fw_reset - issue a reset to FW
2727 * @adap: the adapter
2728 * @mbox: mailbox to use for the FW command
2729 * @reset: specifies the type of reset to perform
2731 * Issues a reset command of the specified type to FW.
2733 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2735 struct fw_reset_cmd c;
2737 memset(&c, 0, sizeof(c));
2738 INIT_CMD(c, RESET, WRITE);
2739 c.val = htonl(reset);
2740 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2744 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2745 * @adap: the adapter
2746 * @mbox: mailbox to use for the FW RESET command (if desired)
2747 * @force: force uP into RESET even if FW RESET command fails
2749 * Issues a RESET command to firmware (if desired) with a HALT indication
2750 * and then puts the microprocessor into RESET state. The RESET command
2751 * will only be issued if a legitimate mailbox is provided (mbox <=
2752 * FW_PCIE_FW_MASTER_MASK).
2754 * This is generally used in order for the host to safely manipulate the
2755 * adapter without fear of conflicting with whatever the firmware might
2756 * be doing. The only way out of this state is to RESTART the firmware
2759 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2764 * If a legitimate mailbox is provided, issue a RESET command
2765 * with a HALT indication.
2767 if (mbox <= FW_PCIE_FW_MASTER_MASK) {
2768 struct fw_reset_cmd c;
2770 memset(&c, 0, sizeof(c));
2771 INIT_CMD(c, RESET, WRITE);
2772 c.val = htonl(PIORST | PIORSTMODE);
2773 c.halt_pkd = htonl(FW_RESET_CMD_HALT(1U));
2774 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2778 * Normally we won't complete the operation if the firmware RESET
2779 * command fails but if our caller insists we'll go ahead and put the
2780 * uP into RESET. This can be useful if the firmware is hung or even
2781 * missing ... We'll have to take the risk of putting the uP into
2782 * RESET without the cooperation of firmware in that case.
2784 * We also force the firmware's HALT flag to be on in case we bypassed
2785 * the firmware RESET command above or we're dealing with old firmware
2786 * which doesn't have the HALT capability. This will serve as a flag
2787 * for the incoming firmware to know that it's coming out of a HALT
2788 * rather than a RESET ... if it's new enough to understand that ...
2790 if (ret == 0 || force) {
2791 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);
2792 t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT,
2797 * And we always return the result of the firmware RESET command
2798 * even when we force the uP into RESET ...
2804 * t4_fw_restart - restart the firmware by taking the uP out of RESET
2805 * @adap: the adapter
2806 * @reset: if we want to do a RESET to restart things
2808 * Restart firmware previously halted by t4_fw_halt(). On successful
2809 * return the previous PF Master remains as the new PF Master and there
2810 * is no need to issue a new HELLO command, etc.
2812 * We do this in two ways:
2814 * 1. If we're dealing with newer firmware we'll simply want to take
2815 * the chip's microprocessor out of RESET. This will cause the
2816 * firmware to start up from its start vector. And then we'll loop
2817 * until the firmware indicates it's started again (PCIE_FW.HALT
2818 * reset to 0) or we timeout.
2820 * 2. If we're dealing with older firmware then we'll need to RESET
2821 * the chip since older firmware won't recognize the PCIE_FW.HALT
2822 * flag and automatically RESET itself on startup.
2824 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
2828 * Since we're directing the RESET instead of the firmware
2829 * doing it automatically, we need to clear the PCIE_FW.HALT
2832 t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT, 0);
2835 * If we've been given a valid mailbox, first try to get the
2836 * firmware to do the RESET. If that works, great and we can
2837 * return success. Otherwise, if we haven't been given a
2838 * valid mailbox or the RESET command failed, fall back to
2839 * hitting the chip with a hammer.
2841 if (mbox <= FW_PCIE_FW_MASTER_MASK) {
2842 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
2844 if (t4_fw_reset(adap, mbox,
2845 PIORST | PIORSTMODE) == 0)
2849 t4_write_reg(adap, PL_RST, PIORST | PIORSTMODE);
2854 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
2855 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
2856 if (!(t4_read_reg(adap, PCIE_FW) & FW_PCIE_FW_HALT))
2867 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
2868 * @adap: the adapter
2869 * @mbox: mailbox to use for the FW RESET command (if desired)
2870 * @fw_data: the firmware image to write
2872 * @force: force upgrade even if firmware doesn't cooperate
2874 * Perform all of the steps necessary for upgrading an adapter's
2875 * firmware image. Normally this requires the cooperation of the
2876 * existing firmware in order to halt all existing activities
2877 * but if an invalid mailbox token is passed in we skip that step
2878 * (though we'll still put the adapter microprocessor into RESET in
2881 * On successful return the new firmware will have been loaded and
2882 * the adapter will have been fully RESET losing all previous setup
2883 * state. On unsuccessful return the adapter may be completely hosed ...
2884 * positive errno indicates that the adapter is ~probably~ intact, a
2885 * negative errno indicates that things are looking bad ...
2887 static int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
2888 const u8 *fw_data, unsigned int size, int force)
2890 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
2893 ret = t4_fw_halt(adap, mbox, force);
2894 if (ret < 0 && !force)
2897 ret = t4_load_fw(adap, fw_data, size);
2902 * Older versions of the firmware don't understand the new
2903 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
2904 * restart. So for newly loaded older firmware we'll have to do the
2905 * RESET for it so it starts up on a clean slate. We can tell if
2906 * the newly loaded firmware will handle this right by checking
2907 * its header flags to see if it advertises the capability.
2909 reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
2910 return t4_fw_restart(adap, mbox, reset);
2914 * t4_fixup_host_params - fix up host-dependent parameters
2915 * @adap: the adapter
2916 * @page_size: the host's Base Page Size
2917 * @cache_line_size: the host's Cache Line Size
2919 * Various registers in T4 contain values which are dependent on the
2920 * host's Base Page and Cache Line Sizes. This function will fix all of
2921 * those registers with the appropriate values as passed in ...
2923 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
2924 unsigned int cache_line_size)
2926 unsigned int page_shift = fls(page_size) - 1;
2927 unsigned int sge_hps = page_shift - 10;
2928 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
2929 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
2930 unsigned int fl_align_log = fls(fl_align) - 1;
2932 t4_write_reg(adap, SGE_HOST_PAGE_SIZE,
2933 HOSTPAGESIZEPF0(sge_hps) |
2934 HOSTPAGESIZEPF1(sge_hps) |
2935 HOSTPAGESIZEPF2(sge_hps) |
2936 HOSTPAGESIZEPF3(sge_hps) |
2937 HOSTPAGESIZEPF4(sge_hps) |
2938 HOSTPAGESIZEPF5(sge_hps) |
2939 HOSTPAGESIZEPF6(sge_hps) |
2940 HOSTPAGESIZEPF7(sge_hps));
2942 t4_set_reg_field(adap, SGE_CONTROL,
2943 INGPADBOUNDARY_MASK |
2944 EGRSTATUSPAGESIZE_MASK,
2945 INGPADBOUNDARY(fl_align_log - 5) |
2946 EGRSTATUSPAGESIZE(stat_len != 64));
2949 * Adjust various SGE Free List Host Buffer Sizes.
2951 * This is something of a crock since we're using fixed indices into
2952 * the array which are also known by the sge.c code and the T4
2953 * Firmware Configuration File. We need to come up with a much better
2954 * approach to managing this array. For now, the first four entries
2959 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
2960 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
2962 * For the single-MTU buffers in unpacked mode we need to include
2963 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
2964 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
2965 * Padding boundry. All of these are accommodated in the Factory
2966 * Default Firmware Configuration File but we need to adjust it for
2967 * this host's cache line size.
2969 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0, page_size);
2970 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2,
2971 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2) + fl_align-1)
2973 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3,
2974 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3) + fl_align-1)
2977 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(page_shift - 12));
2983 * t4_fw_initialize - ask FW to initialize the device
2984 * @adap: the adapter
2985 * @mbox: mailbox to use for the FW command
2987 * Issues a command to FW to partially initialize the device. This
2988 * performs initialization that generally doesn't depend on user input.
2990 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
2992 struct fw_initialize_cmd c;
2994 memset(&c, 0, sizeof(c));
2995 INIT_CMD(c, INITIALIZE, WRITE);
2996 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3000 * t4_query_params - query FW or device parameters
3001 * @adap: the adapter
3002 * @mbox: mailbox to use for the FW command
3005 * @nparams: the number of parameters
3006 * @params: the parameter names
3007 * @val: the parameter values
3009 * Reads the value of FW or device parameters. Up to 7 parameters can be
3012 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3013 unsigned int vf, unsigned int nparams, const u32 *params,
3017 struct fw_params_cmd c;
3018 __be32 *p = &c.param[0].mnem;
3023 memset(&c, 0, sizeof(c));
3024 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
3025 FW_CMD_READ | FW_PARAMS_CMD_PFN(pf) |
3026 FW_PARAMS_CMD_VFN(vf));
3027 c.retval_len16 = htonl(FW_LEN16(c));
3028 for (i = 0; i < nparams; i++, p += 2)
3029 *p = htonl(*params++);
3031 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3033 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3039 * t4_set_params - sets FW or device parameters
3040 * @adap: the adapter
3041 * @mbox: mailbox to use for the FW command
3044 * @nparams: the number of parameters
3045 * @params: the parameter names
3046 * @val: the parameter values
3048 * Sets the value of FW or device parameters. Up to 7 parameters can be
3049 * specified at once.
3051 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3052 unsigned int vf, unsigned int nparams, const u32 *params,
3055 struct fw_params_cmd c;
3056 __be32 *p = &c.param[0].mnem;
3061 memset(&c, 0, sizeof(c));
3062 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
3063 FW_CMD_WRITE | FW_PARAMS_CMD_PFN(pf) |
3064 FW_PARAMS_CMD_VFN(vf));
3065 c.retval_len16 = htonl(FW_LEN16(c));
3067 *p++ = htonl(*params++);
3068 *p++ = htonl(*val++);
3071 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3075 * t4_cfg_pfvf - configure PF/VF resource limits
3076 * @adap: the adapter
3077 * @mbox: mailbox to use for the FW command
3078 * @pf: the PF being configured
3079 * @vf: the VF being configured
3080 * @txq: the max number of egress queues
3081 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
3082 * @rxqi: the max number of interrupt-capable ingress queues
3083 * @rxq: the max number of interruptless ingress queues
3084 * @tc: the PCI traffic class
3085 * @vi: the max number of virtual interfaces
3086 * @cmask: the channel access rights mask for the PF/VF
3087 * @pmask: the port access rights mask for the PF/VF
3088 * @nexact: the maximum number of exact MPS filters
3089 * @rcaps: read capabilities
3090 * @wxcaps: write/execute capabilities
3092 * Configures resource limits and capabilities for a physical or virtual
3095 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
3096 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
3097 unsigned int rxqi, unsigned int rxq, unsigned int tc,
3098 unsigned int vi, unsigned int cmask, unsigned int pmask,
3099 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
3101 struct fw_pfvf_cmd c;
3103 memset(&c, 0, sizeof(c));
3104 c.op_to_vfn = htonl(FW_CMD_OP(FW_PFVF_CMD) | FW_CMD_REQUEST |
3105 FW_CMD_WRITE | FW_PFVF_CMD_PFN(pf) |
3106 FW_PFVF_CMD_VFN(vf));
3107 c.retval_len16 = htonl(FW_LEN16(c));
3108 c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) |
3109 FW_PFVF_CMD_NIQ(rxq));
3110 c.type_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) |
3111 FW_PFVF_CMD_PMASK(pmask) |
3112 FW_PFVF_CMD_NEQ(txq));
3113 c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) |
3114 FW_PFVF_CMD_NEXACTF(nexact));
3115 c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS(rcaps) |
3116 FW_PFVF_CMD_WX_CAPS(wxcaps) |
3117 FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
3118 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3122 * t4_alloc_vi - allocate a virtual interface
3123 * @adap: the adapter
3124 * @mbox: mailbox to use for the FW command
3125 * @port: physical port associated with the VI
3126 * @pf: the PF owning the VI
3127 * @vf: the VF owning the VI
3128 * @nmac: number of MAC addresses needed (1 to 5)
3129 * @mac: the MAC addresses of the VI
3130 * @rss_size: size of RSS table slice associated with this VI
3132 * Allocates a virtual interface for the given physical port. If @mac is
3133 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3134 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3135 * stored consecutively so the space needed is @nmac * 6 bytes.
3136 * Returns a negative error number or the non-negative VI id.
3138 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3139 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3140 unsigned int *rss_size)
3145 memset(&c, 0, sizeof(c));
3146 c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST |
3147 FW_CMD_WRITE | FW_CMD_EXEC |
3148 FW_VI_CMD_PFN(pf) | FW_VI_CMD_VFN(vf));
3149 c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC | FW_LEN16(c));
3150 c.portid_pkd = FW_VI_CMD_PORTID(port);
3153 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3158 memcpy(mac, c.mac, sizeof(c.mac));
3161 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3163 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3165 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3167 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3171 *rss_size = FW_VI_CMD_RSSSIZE_GET(ntohs(c.rsssize_pkd));
3172 return FW_VI_CMD_VIID_GET(ntohs(c.type_viid));
3176 * t4_set_rxmode - set Rx properties of a virtual interface
3177 * @adap: the adapter
3178 * @mbox: mailbox to use for the FW command
3180 * @mtu: the new MTU or -1
3181 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3182 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3183 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3184 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
3185 * @sleep_ok: if true we may sleep while awaiting command completion
3187 * Sets Rx properties of a virtual interface.
3189 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3190 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3193 struct fw_vi_rxmode_cmd c;
3195 /* convert to FW values */
3197 mtu = FW_RXMODE_MTU_NO_CHG;
3199 promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK;
3201 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK;
3203 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK;
3205 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_MASK;
3207 memset(&c, 0, sizeof(c));
3208 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST |
3209 FW_CMD_WRITE | FW_VI_RXMODE_CMD_VIID(viid));
3210 c.retval_len16 = htonl(FW_LEN16(c));
3211 c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU(mtu) |
3212 FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3213 FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3214 FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3215 FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3216 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3220 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
3221 * @adap: the adapter
3222 * @mbox: mailbox to use for the FW command
3224 * @free: if true any existing filters for this VI id are first removed
3225 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
3226 * @addr: the MAC address(es)
3227 * @idx: where to store the index of each allocated filter
3228 * @hash: pointer to hash address filter bitmap
3229 * @sleep_ok: call is allowed to sleep
3231 * Allocates an exact-match filter for each of the supplied addresses and
3232 * sets it to the corresponding address. If @idx is not %NULL it should
3233 * have at least @naddr entries, each of which will be set to the index of
3234 * the filter allocated for the corresponding MAC address. If a filter
3235 * could not be allocated for an address its index is set to 0xffff.
3236 * If @hash is not %NULL addresses that fail to allocate an exact filter
3237 * are hashed and update the hash filter bitmap pointed at by @hash.
3239 * Returns a negative error number or the number of filters allocated.
3241 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
3242 unsigned int viid, bool free, unsigned int naddr,
3243 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
3246 struct fw_vi_mac_cmd c;
3247 struct fw_vi_mac_exact *p;
3248 unsigned int max_naddr = is_t4(adap->params.chip) ?
3249 NUM_MPS_CLS_SRAM_L_INSTANCES :
3250 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3255 memset(&c, 0, sizeof(c));
3256 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3257 FW_CMD_WRITE | (free ? FW_CMD_EXEC : 0) |
3258 FW_VI_MAC_CMD_VIID(viid));
3259 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS(free) |
3260 FW_CMD_LEN16((naddr + 2) / 2));
3262 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
3263 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
3264 FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
3265 memcpy(p->macaddr, addr[i], sizeof(p->macaddr));
3268 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
3272 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
3273 u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
3276 idx[i] = index >= max_naddr ? 0xffff : index;
3277 if (index < max_naddr)
3280 *hash |= (1ULL << hash_mac_addr(addr[i]));
3286 * t4_change_mac - modifies the exact-match filter for a MAC address
3287 * @adap: the adapter
3288 * @mbox: mailbox to use for the FW command
3290 * @idx: index of existing filter for old value of MAC address, or -1
3291 * @addr: the new MAC address value
3292 * @persist: whether a new MAC allocation should be persistent
3293 * @add_smt: if true also add the address to the HW SMT
3295 * Modifies an exact-match filter and sets it to the new MAC address.
3296 * Note that in general it is not possible to modify the value of a given
3297 * filter so the generic way to modify an address filter is to free the one
3298 * being used by the old address value and allocate a new filter for the
3299 * new address value. @idx can be -1 if the address is a new addition.
3301 * Returns a negative error number or the index of the filter with the new
3304 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3305 int idx, const u8 *addr, bool persist, bool add_smt)
3308 struct fw_vi_mac_cmd c;
3309 struct fw_vi_mac_exact *p = c.u.exact;
3310 unsigned int max_mac_addr = is_t4(adap->params.chip) ?
3311 NUM_MPS_CLS_SRAM_L_INSTANCES :
3312 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3314 if (idx < 0) /* new allocation */
3315 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3316 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3318 memset(&c, 0, sizeof(c));
3319 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3320 FW_CMD_WRITE | FW_VI_MAC_CMD_VIID(viid));
3321 c.freemacs_to_len16 = htonl(FW_CMD_LEN16(1));
3322 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
3323 FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3324 FW_VI_MAC_CMD_IDX(idx));
3325 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3327 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3329 ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
3330 if (ret >= max_mac_addr)
3337 * t4_set_addr_hash - program the MAC inexact-match hash filter
3338 * @adap: the adapter
3339 * @mbox: mailbox to use for the FW command
3341 * @ucast: whether the hash filter should also match unicast addresses
3342 * @vec: the value to be written to the hash filter
3343 * @sleep_ok: call is allowed to sleep
3345 * Sets the 64-bit inexact-match hash filter for a virtual interface.
3347 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
3348 bool ucast, u64 vec, bool sleep_ok)
3350 struct fw_vi_mac_cmd c;
3352 memset(&c, 0, sizeof(c));
3353 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3354 FW_CMD_WRITE | FW_VI_ENABLE_CMD_VIID(viid));
3355 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN |
3356 FW_VI_MAC_CMD_HASHUNIEN(ucast) |
3358 c.u.hash.hashvec = cpu_to_be64(vec);
3359 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3363 * t4_enable_vi - enable/disable a virtual interface
3364 * @adap: the adapter
3365 * @mbox: mailbox to use for the FW command
3367 * @rx_en: 1=enable Rx, 0=disable Rx
3368 * @tx_en: 1=enable Tx, 0=disable Tx
3370 * Enables/disables a virtual interface.
3372 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3373 bool rx_en, bool tx_en)
3375 struct fw_vi_enable_cmd c;
3377 memset(&c, 0, sizeof(c));
3378 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
3379 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
3380 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN(rx_en) |
3381 FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c));
3382 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3386 * t4_identify_port - identify a VI's port by blinking its LED
3387 * @adap: the adapter
3388 * @mbox: mailbox to use for the FW command
3390 * @nblinks: how many times to blink LED at 2.5 Hz
3392 * Identifies a VI's port by blinking its LED.
3394 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
3395 unsigned int nblinks)
3397 struct fw_vi_enable_cmd c;
3399 memset(&c, 0, sizeof(c));
3400 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
3401 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
3402 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
3403 c.blinkdur = htons(nblinks);
3404 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3408 * t4_iq_free - free an ingress queue and its FLs
3409 * @adap: the adapter
3410 * @mbox: mailbox to use for the FW command
3411 * @pf: the PF owning the queues
3412 * @vf: the VF owning the queues
3413 * @iqtype: the ingress queue type
3414 * @iqid: ingress queue id
3415 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3416 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3418 * Frees an ingress queue and its associated FLs, if any.
3420 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3421 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3422 unsigned int fl0id, unsigned int fl1id)
3426 memset(&c, 0, sizeof(c));
3427 c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST |
3428 FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) |
3430 c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE | FW_LEN16(c));
3431 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iqtype));
3432 c.iqid = htons(iqid);
3433 c.fl0id = htons(fl0id);
3434 c.fl1id = htons(fl1id);
3435 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3439 * t4_eth_eq_free - free an Ethernet egress queue
3440 * @adap: the adapter
3441 * @mbox: mailbox to use for the FW command
3442 * @pf: the PF owning the queue
3443 * @vf: the VF owning the queue
3444 * @eqid: egress queue id
3446 * Frees an Ethernet egress queue.
3448 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3449 unsigned int vf, unsigned int eqid)
3451 struct fw_eq_eth_cmd c;
3453 memset(&c, 0, sizeof(c));
3454 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST |
3455 FW_CMD_EXEC | FW_EQ_ETH_CMD_PFN(pf) |
3456 FW_EQ_ETH_CMD_VFN(vf));
3457 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3458 c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID(eqid));
3459 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3463 * t4_ctrl_eq_free - free a control egress queue
3464 * @adap: the adapter
3465 * @mbox: mailbox to use for the FW command
3466 * @pf: the PF owning the queue
3467 * @vf: the VF owning the queue
3468 * @eqid: egress queue id
3470 * Frees a control egress queue.
3472 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3473 unsigned int vf, unsigned int eqid)
3475 struct fw_eq_ctrl_cmd c;
3477 memset(&c, 0, sizeof(c));
3478 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST |
3479 FW_CMD_EXEC | FW_EQ_CTRL_CMD_PFN(pf) |
3480 FW_EQ_CTRL_CMD_VFN(vf));
3481 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
3482 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID(eqid));
3483 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3487 * t4_ofld_eq_free - free an offload egress queue
3488 * @adap: the adapter
3489 * @mbox: mailbox to use for the FW command
3490 * @pf: the PF owning the queue
3491 * @vf: the VF owning the queue
3492 * @eqid: egress queue id
3494 * Frees a control egress queue.
3496 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3497 unsigned int vf, unsigned int eqid)
3499 struct fw_eq_ofld_cmd c;
3501 memset(&c, 0, sizeof(c));
3502 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST |
3503 FW_CMD_EXEC | FW_EQ_OFLD_CMD_PFN(pf) |
3504 FW_EQ_OFLD_CMD_VFN(vf));
3505 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
3506 c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eqid));
3507 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3511 * t4_handle_fw_rpl - process a FW reply message
3512 * @adap: the adapter
3513 * @rpl: start of the FW message
3515 * Processes a FW message, such as link state change messages.
3517 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3519 u8 opcode = *(const u8 *)rpl;
3521 if (opcode == FW_PORT_CMD) { /* link/module state change message */
3522 int speed = 0, fc = 0;
3523 const struct fw_port_cmd *p = (void *)rpl;
3524 int chan = FW_PORT_CMD_PORTID_GET(ntohl(p->op_to_portid));
3525 int port = adap->chan_map[chan];
3526 struct port_info *pi = adap2pinfo(adap, port);
3527 struct link_config *lc = &pi->link_cfg;
3528 u32 stat = ntohl(p->u.info.lstatus_to_modtype);
3529 int link_ok = (stat & FW_PORT_CMD_LSTATUS) != 0;
3530 u32 mod = FW_PORT_CMD_MODTYPE_GET(stat);
3532 if (stat & FW_PORT_CMD_RXPAUSE)
3534 if (stat & FW_PORT_CMD_TXPAUSE)
3536 if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3538 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3540 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3541 speed = SPEED_10000;
3543 if (link_ok != lc->link_ok || speed != lc->speed ||
3544 fc != lc->fc) { /* something changed */
3545 lc->link_ok = link_ok;
3548 t4_os_link_changed(adap, port, link_ok);
3550 if (mod != pi->mod_type) {
3552 t4_os_portmod_changed(adap, port);
3558 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
3562 if (pci_is_pcie(adapter->pdev)) {
3563 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
3564 p->speed = val & PCI_EXP_LNKSTA_CLS;
3565 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
3570 * init_link_config - initialize a link's SW state
3571 * @lc: structure holding the link state
3572 * @caps: link capabilities
3574 * Initializes the SW state maintained for each link, including the link's
3575 * capabilities and default speed/flow-control/autonegotiation settings.
3577 static void init_link_config(struct link_config *lc, unsigned int caps)
3579 lc->supported = caps;
3580 lc->requested_speed = 0;
3582 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
3583 if (lc->supported & FW_PORT_CAP_ANEG) {
3584 lc->advertising = lc->supported & ADVERT_MASK;
3585 lc->autoneg = AUTONEG_ENABLE;
3586 lc->requested_fc |= PAUSE_AUTONEG;
3588 lc->advertising = 0;
3589 lc->autoneg = AUTONEG_DISABLE;
3593 int t4_wait_dev_ready(struct adapter *adap)
3595 if (t4_read_reg(adap, PL_WHOAMI) != 0xffffffff)
3598 return t4_read_reg(adap, PL_WHOAMI) != 0xffffffff ? 0 : -EIO;
3601 static int get_flash_params(struct adapter *adap)
3606 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
3608 ret = sf1_read(adap, 3, 0, 1, &info);
3609 t4_write_reg(adap, SF_OP, 0); /* unlock SF */
3613 if ((info & 0xff) != 0x20) /* not a Numonix flash */
3615 info >>= 16; /* log2 of size */
3616 if (info >= 0x14 && info < 0x18)
3617 adap->params.sf_nsec = 1 << (info - 16);
3618 else if (info == 0x18)
3619 adap->params.sf_nsec = 64;
3622 adap->params.sf_size = 1 << info;
3623 adap->params.sf_fw_start =
3624 t4_read_reg(adap, CIM_BOOT_CFG) & BOOTADDR_MASK;
3629 * t4_prep_adapter - prepare SW and HW for operation
3630 * @adapter: the adapter
3631 * @reset: if true perform a HW reset
3633 * Initialize adapter SW state for the various HW modules, set initial
3634 * values for some adapter tunables, take PHYs out of reset, and
3635 * initialize the MDIO interface.
3637 int t4_prep_adapter(struct adapter *adapter)
3643 ret = t4_wait_dev_ready(adapter);
3647 get_pci_mode(adapter, &adapter->params.pci);
3648 pl_rev = G_REV(t4_read_reg(adapter, PL_REV));
3650 ret = get_flash_params(adapter);
3652 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
3656 /* Retrieve adapter's device ID
3658 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
3659 ver = device_id >> 12;
3660 adapter->params.chip = 0;
3663 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
3666 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3669 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3674 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3677 * Default port for debugging in case we can't reach FW.
3679 adapter->params.nports = 1;
3680 adapter->params.portvec = 1;
3681 adapter->params.vpd.cclk = 50000;
3685 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
3689 struct fw_port_cmd c;
3690 struct fw_rss_vi_config_cmd rvc;
3692 memset(&c, 0, sizeof(c));
3693 memset(&rvc, 0, sizeof(rvc));
3695 for_each_port(adap, i) {
3696 unsigned int rss_size;
3697 struct port_info *p = adap2pinfo(adap, i);
3699 while ((adap->params.portvec & (1 << j)) == 0)
3702 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) |
3703 FW_CMD_REQUEST | FW_CMD_READ |
3704 FW_PORT_CMD_PORTID(j));
3705 c.action_to_len16 = htonl(
3706 FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
3708 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3712 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
3719 p->rss_size = rss_size;
3720 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
3722 ret = ntohl(c.u.info.lstatus_to_modtype);
3723 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP) ?
3724 FW_PORT_CMD_MDIOADDR_GET(ret) : -1;
3725 p->port_type = FW_PORT_CMD_PTYPE_GET(ret);
3726 p->mod_type = FW_PORT_MOD_TYPE_NA;
3728 rvc.op_to_viid = htonl(FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
3729 FW_CMD_REQUEST | FW_CMD_READ |
3730 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
3731 rvc.retval_len16 = htonl(FW_LEN16(rvc));
3732 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
3735 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
3737 init_link_config(&p->link_cfg, ntohs(c.u.info.pcap));