2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/init.h>
36 #include <linux/delay.h>
42 * t4_wait_op_done_val - wait until an operation is completed
43 * @adapter: the adapter performing the operation
44 * @reg: the register to check for completion
45 * @mask: a single-bit field within @reg that indicates completion
46 * @polarity: the value of the field when the operation is completed
47 * @attempts: number of check iterations
48 * @delay: delay in usecs between iterations
49 * @valp: where to store the value of the register at completion time
51 * Wait until an operation is completed by checking a bit in a register
52 * up to @attempts times. If @valp is not NULL the value of the register
53 * at the time it indicated completion is stored there. Returns 0 if the
54 * operation completes and -EAGAIN otherwise.
56 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
57 int polarity, int attempts, int delay, u32 *valp)
60 u32 val = t4_read_reg(adapter, reg);
62 if (!!(val & mask) == polarity) {
74 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
75 int polarity, int attempts, int delay)
77 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
82 * t4_set_reg_field - set a register field to a value
83 * @adapter: the adapter to program
84 * @addr: the register address
85 * @mask: specifies the portion of the register to modify
86 * @val: the new value for the register field
88 * Sets a register field specified by the supplied mask to the
91 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
94 u32 v = t4_read_reg(adapter, addr) & ~mask;
96 t4_write_reg(adapter, addr, v | val);
97 (void) t4_read_reg(adapter, addr); /* flush */
101 * t4_read_indirect - read indirectly addressed registers
103 * @addr_reg: register holding the indirect address
104 * @data_reg: register holding the value of the indirect register
105 * @vals: where the read register values are stored
106 * @nregs: how many indirect registers to read
107 * @start_idx: index of first indirect register to read
109 * Reads registers that are accessed indirectly through an address/data
112 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
113 unsigned int data_reg, u32 *vals,
114 unsigned int nregs, unsigned int start_idx)
117 t4_write_reg(adap, addr_reg, start_idx);
118 *vals++ = t4_read_reg(adap, data_reg);
124 * t4_write_indirect - write indirectly addressed registers
126 * @addr_reg: register holding the indirect addresses
127 * @data_reg: register holding the value for the indirect registers
128 * @vals: values to write
129 * @nregs: how many indirect registers to write
130 * @start_idx: address of first indirect register to write
132 * Writes a sequential block of registers that are accessed indirectly
133 * through an address/data register pair.
135 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
136 unsigned int data_reg, const u32 *vals,
137 unsigned int nregs, unsigned int start_idx)
140 t4_write_reg(adap, addr_reg, start_idx++);
141 t4_write_reg(adap, data_reg, *vals++);
146 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
148 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
151 for ( ; nflit; nflit--, mbox_addr += 8)
152 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
156 * Handle a FW assertion reported in a mailbox.
158 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
160 struct fw_debug_cmd asrt;
162 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
163 dev_alert(adap->pdev_dev,
164 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
165 asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line),
166 ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y));
169 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
171 dev_err(adap->pdev_dev,
172 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
173 (unsigned long long)t4_read_reg64(adap, data_reg),
174 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
175 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
176 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
177 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
178 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
179 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
180 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
184 * t4_wr_mbox_meat - send a command to FW through the given mailbox
186 * @mbox: index of the mailbox to use
187 * @cmd: the command to write
188 * @size: command length in bytes
189 * @rpl: where to optionally store the reply
190 * @sleep_ok: if true we may sleep while awaiting command completion
192 * Sends the given command to FW through the selected mailbox and waits
193 * for the FW to execute the command. If @rpl is not %NULL it is used to
194 * store the FW's reply to the command. The command and its optional
195 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
196 * to respond. @sleep_ok determines whether we may sleep while awaiting
197 * the response. If sleeping is allowed we use progressive backoff
200 * The return value is 0 on success or a negative errno on failure. A
201 * failure can happen either because we are not able to execute the
202 * command or FW executes it but signals an error. In the latter case
203 * the return value is the error code indicated by FW (negated).
205 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
206 void *rpl, bool sleep_ok)
208 static const int delay[] = {
209 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
214 int i, ms, delay_idx;
215 const __be64 *p = cmd;
216 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA);
217 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL);
219 if ((size & 15) || size > MBOX_LEN)
223 * If the device is off-line, as in EEH, commands will time out.
224 * Fail them early so we don't waste time waiting.
226 if (adap->pdev->error_state != pci_channel_io_normal)
229 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
230 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
231 v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
233 if (v != MBOX_OWNER_DRV)
234 return v ? -EBUSY : -ETIMEDOUT;
236 for (i = 0; i < size; i += 8)
237 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
239 t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
240 t4_read_reg(adap, ctl_reg); /* flush write */
245 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
247 ms = delay[delay_idx]; /* last element may repeat */
248 if (delay_idx < ARRAY_SIZE(delay) - 1)
254 v = t4_read_reg(adap, ctl_reg);
255 if (MBOWNER_GET(v) == MBOX_OWNER_DRV) {
256 if (!(v & MBMSGVALID)) {
257 t4_write_reg(adap, ctl_reg, 0);
261 res = t4_read_reg64(adap, data_reg);
262 if (FW_CMD_OP_GET(res >> 32) == FW_DEBUG_CMD) {
263 fw_asrt(adap, data_reg);
264 res = FW_CMD_RETVAL(EIO);
266 get_mbox_rpl(adap, rpl, size / 8, data_reg);
268 if (FW_CMD_RETVAL_GET((int)res))
269 dump_mbox(adap, mbox, data_reg);
270 t4_write_reg(adap, ctl_reg, 0);
271 return -FW_CMD_RETVAL_GET((int)res);
275 dump_mbox(adap, mbox, data_reg);
276 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
277 *(const u8 *)cmd, mbox);
282 * t4_mc_read - read from MC through backdoor accesses
284 * @addr: address of first byte requested
285 * @idx: which MC to access
286 * @data: 64 bytes of data containing the requested address
287 * @ecc: where to store the corresponding 64-bit ECC word
289 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
290 * that covers the requested address @addr. If @parity is not %NULL it
291 * is assigned the 64-bit ECC word for the read data.
293 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
296 u32 mc_bist_cmd, mc_bist_cmd_addr, mc_bist_cmd_len;
297 u32 mc_bist_status_rdata, mc_bist_data_pattern;
299 if (is_t4(adap->params.chip)) {
300 mc_bist_cmd = MC_BIST_CMD;
301 mc_bist_cmd_addr = MC_BIST_CMD_ADDR;
302 mc_bist_cmd_len = MC_BIST_CMD_LEN;
303 mc_bist_status_rdata = MC_BIST_STATUS_RDATA;
304 mc_bist_data_pattern = MC_BIST_DATA_PATTERN;
306 mc_bist_cmd = MC_REG(MC_P_BIST_CMD, idx);
307 mc_bist_cmd_addr = MC_REG(MC_P_BIST_CMD_ADDR, idx);
308 mc_bist_cmd_len = MC_REG(MC_P_BIST_CMD_LEN, idx);
309 mc_bist_status_rdata = MC_REG(MC_P_BIST_STATUS_RDATA, idx);
310 mc_bist_data_pattern = MC_REG(MC_P_BIST_DATA_PATTERN, idx);
313 if (t4_read_reg(adap, mc_bist_cmd) & START_BIST)
315 t4_write_reg(adap, mc_bist_cmd_addr, addr & ~0x3fU);
316 t4_write_reg(adap, mc_bist_cmd_len, 64);
317 t4_write_reg(adap, mc_bist_data_pattern, 0xc);
318 t4_write_reg(adap, mc_bist_cmd, BIST_OPCODE(1) | START_BIST |
320 i = t4_wait_op_done(adap, mc_bist_cmd, START_BIST, 0, 10, 1);
324 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata, i)
326 for (i = 15; i >= 0; i--)
327 *data++ = htonl(t4_read_reg(adap, MC_DATA(i)));
329 *ecc = t4_read_reg64(adap, MC_DATA(16));
335 * t4_edc_read - read from EDC through backdoor accesses
337 * @idx: which EDC to access
338 * @addr: address of first byte requested
339 * @data: 64 bytes of data containing the requested address
340 * @ecc: where to store the corresponding 64-bit ECC word
342 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
343 * that covers the requested address @addr. If @parity is not %NULL it
344 * is assigned the 64-bit ECC word for the read data.
346 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
349 u32 edc_bist_cmd, edc_bist_cmd_addr, edc_bist_cmd_len;
350 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata;
352 if (is_t4(adap->params.chip)) {
353 edc_bist_cmd = EDC_REG(EDC_BIST_CMD, idx);
354 edc_bist_cmd_addr = EDC_REG(EDC_BIST_CMD_ADDR, idx);
355 edc_bist_cmd_len = EDC_REG(EDC_BIST_CMD_LEN, idx);
356 edc_bist_cmd_data_pattern = EDC_REG(EDC_BIST_DATA_PATTERN,
358 edc_bist_status_rdata = EDC_REG(EDC_BIST_STATUS_RDATA,
361 edc_bist_cmd = EDC_REG_T5(EDC_H_BIST_CMD, idx);
362 edc_bist_cmd_addr = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx);
363 edc_bist_cmd_len = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx);
364 edc_bist_cmd_data_pattern =
365 EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx);
366 edc_bist_status_rdata =
367 EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx);
370 if (t4_read_reg(adap, edc_bist_cmd) & START_BIST)
372 t4_write_reg(adap, edc_bist_cmd_addr, addr & ~0x3fU);
373 t4_write_reg(adap, edc_bist_cmd_len, 64);
374 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
375 t4_write_reg(adap, edc_bist_cmd,
376 BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST);
377 i = t4_wait_op_done(adap, edc_bist_cmd, START_BIST, 0, 10, 1);
381 #define EDC_DATA(i) (EDC_BIST_STATUS_REG(edc_bist_status_rdata, i))
383 for (i = 15; i >= 0; i--)
384 *data++ = htonl(t4_read_reg(adap, EDC_DATA(i)));
386 *ecc = t4_read_reg64(adap, EDC_DATA(16));
392 * t4_mem_win_rw - read/write memory through PCIE memory window
394 * @addr: address of first byte requested
395 * @data: MEMWIN0_APERTURE bytes of data containing the requested address
396 * @dir: direction of transfer 1 => read, 0 => write
398 * Read/write MEMWIN0_APERTURE bytes of data from MC starting at a
399 * MEMWIN0_APERTURE-byte-aligned address that covers the requested
402 static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir)
405 u32 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
408 * Setup offset into PCIE memory window. Address must be a
409 * MEMWIN0_APERTURE-byte-aligned address. (Read back MA register to
410 * ensure that changes propagate before we attempt to use the new
413 t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
414 (addr & ~(MEMWIN0_APERTURE - 1)) | win_pf);
415 t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
417 /* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */
418 for (i = 0; i < MEMWIN0_APERTURE; i = i+0x4) {
420 *data++ = (__force __be32) t4_read_reg(adap,
423 t4_write_reg(adap, (MEMWIN0_BASE + i),
424 (__force u32) *data++);
431 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
433 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
434 * @addr: address within indicated memory type
435 * @len: amount of memory to transfer
436 * @buf: host memory buffer
437 * @dir: direction of transfer 1 => read, 0 => write
439 * Reads/writes an [almost] arbitrary memory region in the firmware: the
440 * firmware memory address, length and host buffer must be aligned on
441 * 32-bit boudaries. The memory is transferred as a raw byte sequence
442 * from/to the firmware's memory. If this memory contains data
443 * structures which contain multi-byte integers, it's the callers
444 * responsibility to perform appropriate byte order conversions.
446 static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len,
447 __be32 *buf, int dir)
449 u32 pos, start, end, offset, memoffset;
450 u32 edc_size, mc_size;
455 * Argument sanity checks ...
457 if ((addr & 0x3) || (len & 0x3))
460 data = vmalloc(MEMWIN0_APERTURE);
464 /* Offset into the region of memory which is being accessed
468 * MEM_MC0 = 2 -- For T5
469 * MEM_MC1 = 3 -- For T5
471 edc_size = EDRAM_SIZE_GET(t4_read_reg(adap, MA_EDRAM0_BAR));
472 if (mtype != MEM_MC1)
473 memoffset = (mtype * (edc_size * 1024 * 1024));
475 mc_size = EXT_MEM_SIZE_GET(t4_read_reg(adap,
477 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
480 /* Determine the PCIE_MEM_ACCESS_OFFSET */
481 addr = addr + memoffset;
484 * The underlaying EDC/MC read routines read MEMWIN0_APERTURE bytes
485 * at a time so we need to round down the start and round up the end.
486 * We'll start copying out of the first line at (addr - start) a word
489 start = addr & ~(MEMWIN0_APERTURE-1);
490 end = (addr + len + MEMWIN0_APERTURE-1) & ~(MEMWIN0_APERTURE-1);
491 offset = (addr - start)/sizeof(__be32);
493 for (pos = start; pos < end; pos += MEMWIN0_APERTURE, offset = 0) {
496 * If we're writing, copy the data from the caller's memory
501 * If we're doing a partial write, then we need to do
502 * a read-modify-write ...
504 if (offset || len < MEMWIN0_APERTURE) {
505 ret = t4_mem_win_rw(adap, pos, data, 1);
509 while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
511 data[offset++] = *buf++;
512 len -= sizeof(__be32);
517 * Transfer a block of memory and bail if there's an error.
519 ret = t4_mem_win_rw(adap, pos, data, dir);
524 * If we're reading, copy the data into the caller's memory
528 while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
530 *buf++ = data[offset++];
531 len -= sizeof(__be32);
539 int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
542 return t4_memory_rw(adap, mtype, addr, len, buf, 0);
545 #define EEPROM_STAT_ADDR 0x7bfc
546 #define VPD_BASE 0x400
547 #define VPD_BASE_OLD 0
551 * t4_seeprom_wp - enable/disable EEPROM write protection
552 * @adapter: the adapter
553 * @enable: whether to enable or disable write protection
555 * Enables or disables write protection on the serial EEPROM.
557 int t4_seeprom_wp(struct adapter *adapter, bool enable)
559 unsigned int v = enable ? 0xc : 0;
560 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
561 return ret < 0 ? ret : 0;
565 * get_vpd_params - read VPD parameters from VPD EEPROM
566 * @adapter: adapter to read
567 * @p: where to store the parameters
569 * Reads card parameters stored in VPD EEPROM.
571 int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
573 u32 cclk_param, cclk_val;
577 unsigned int vpdr_len, kw_offset, id_len;
579 vpd = vmalloc(VPD_LEN);
583 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
586 addr = *vpd == 0x82 ? VPD_BASE : VPD_BASE_OLD;
588 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
592 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
593 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
598 id_len = pci_vpd_lrdt_size(vpd);
602 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
604 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
609 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
610 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
611 if (vpdr_len + kw_offset > VPD_LEN) {
612 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
617 #define FIND_VPD_KW(var, name) do { \
618 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
620 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
624 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
627 FIND_VPD_KW(i, "RV");
628 for (csum = 0; i >= 0; i--)
632 dev_err(adapter->pdev_dev,
633 "corrupted VPD EEPROM, actual csum %u\n", csum);
638 FIND_VPD_KW(ec, "EC");
639 FIND_VPD_KW(sn, "SN");
642 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
644 memcpy(p->ec, vpd + ec, EC_LEN);
646 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
647 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
651 * Ask firmware for the Core Clock since it knows how to translate the
652 * Reference Clock ('V2') VPD field into a Core Clock value ...
654 cclk_param = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
655 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
656 ret = t4_query_params(adapter, adapter->mbox, 0, 0,
657 1, &cclk_param, &cclk_val);
668 /* serial flash and firmware constants */
670 SF_ATTEMPTS = 10, /* max retries for SF operations */
672 /* flash command opcodes */
673 SF_PROG_PAGE = 2, /* program page */
674 SF_WR_DISABLE = 4, /* disable writes */
675 SF_RD_STATUS = 5, /* read status register */
676 SF_WR_ENABLE = 6, /* enable writes */
677 SF_RD_DATA_FAST = 0xb, /* read flash */
678 SF_RD_ID = 0x9f, /* read ID */
679 SF_ERASE_SECTOR = 0xd8, /* erase sector */
681 FW_MAX_SIZE = 512 * 1024,
685 * sf1_read - read data from the serial flash
686 * @adapter: the adapter
687 * @byte_cnt: number of bytes to read
688 * @cont: whether another operation will be chained
689 * @lock: whether to lock SF for PL access only
690 * @valp: where to store the read data
692 * Reads up to 4 bytes of data from the serial flash. The location of
693 * the read needs to be specified prior to calling this by issuing the
694 * appropriate commands to the serial flash.
696 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
701 if (!byte_cnt || byte_cnt > 4)
703 if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
705 cont = cont ? SF_CONT : 0;
706 lock = lock ? SF_LOCK : 0;
707 t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1));
708 ret = t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
710 *valp = t4_read_reg(adapter, SF_DATA);
715 * sf1_write - write data to the serial flash
716 * @adapter: the adapter
717 * @byte_cnt: number of bytes to write
718 * @cont: whether another operation will be chained
719 * @lock: whether to lock SF for PL access only
720 * @val: value to write
722 * Writes up to 4 bytes of data to the serial flash. The location of
723 * the write needs to be specified prior to calling this by issuing the
724 * appropriate commands to the serial flash.
726 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
729 if (!byte_cnt || byte_cnt > 4)
731 if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
733 cont = cont ? SF_CONT : 0;
734 lock = lock ? SF_LOCK : 0;
735 t4_write_reg(adapter, SF_DATA, val);
736 t4_write_reg(adapter, SF_OP, lock |
737 cont | BYTECNT(byte_cnt - 1) | OP_WR);
738 return t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
742 * flash_wait_op - wait for a flash operation to complete
743 * @adapter: the adapter
744 * @attempts: max number of polls of the status register
745 * @delay: delay between polls in ms
747 * Wait for a flash operation to complete by polling the status register.
749 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
755 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
756 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
768 * t4_read_flash - read words from serial flash
769 * @adapter: the adapter
770 * @addr: the start address for the read
771 * @nwords: how many 32-bit words to read
772 * @data: where to store the read data
773 * @byte_oriented: whether to store data as bytes or as words
775 * Read the specified number of 32-bit words from the serial flash.
776 * If @byte_oriented is set the read data is stored as a byte array
777 * (i.e., big-endian), otherwise as 32-bit words in the platform's
780 static int t4_read_flash(struct adapter *adapter, unsigned int addr,
781 unsigned int nwords, u32 *data, int byte_oriented)
785 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
788 addr = swab32(addr) | SF_RD_DATA_FAST;
790 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
791 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
794 for ( ; nwords; nwords--, data++) {
795 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
797 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
801 *data = (__force __u32) (htonl(*data));
807 * t4_write_flash - write up to a page of data to the serial flash
808 * @adapter: the adapter
809 * @addr: the start address to write
810 * @n: length of data to write in bytes
811 * @data: the data to write
813 * Writes up to a page of data (256 bytes) to the serial flash starting
814 * at the given address. All the data must be written to the same page.
816 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
817 unsigned int n, const u8 *data)
821 unsigned int i, c, left, val, offset = addr & 0xff;
823 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
826 val = swab32(addr) | SF_PROG_PAGE;
828 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
829 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
832 for (left = n; left; left -= c) {
834 for (val = 0, i = 0; i < c; ++i)
835 val = (val << 8) + *data++;
837 ret = sf1_write(adapter, c, c != left, 1, val);
841 ret = flash_wait_op(adapter, 8, 1);
845 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
847 /* Read the page to verify the write succeeded */
848 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
852 if (memcmp(data - n, (u8 *)buf + offset, n)) {
853 dev_err(adapter->pdev_dev,
854 "failed to correctly write the flash page at %#x\n",
861 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
866 * t4_get_fw_version - read the firmware version
867 * @adapter: the adapter
868 * @vers: where to place the version
870 * Reads the FW version from flash.
872 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
874 return t4_read_flash(adapter, FLASH_FW_START +
875 offsetof(struct fw_hdr, fw_ver), 1,
880 * t4_get_tp_version - read the TP microcode version
881 * @adapter: the adapter
882 * @vers: where to place the version
884 * Reads the TP microcode version from flash.
886 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
888 return t4_read_flash(adapter, FLASH_FW_START +
889 offsetof(struct fw_hdr, tp_microcode_ver),
893 /* Is the given firmware API compatible with the one the driver was compiled
896 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
899 /* short circuit if it's the exact same firmware version */
900 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
903 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
904 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
905 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
912 /* The firmware in the filesystem is usable, but should it be installed?
913 * This routine explains itself in detail if it indicates the filesystem
914 * firmware should be installed.
916 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
921 if (!card_fw_usable) {
922 reason = "incompatible or unusable";
927 reason = "older than the version supported with this driver";
934 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
935 "installing firmware %u.%u.%u.%u on card.\n",
936 FW_HDR_FW_VER_MAJOR_GET(c), FW_HDR_FW_VER_MINOR_GET(c),
937 FW_HDR_FW_VER_MICRO_GET(c), FW_HDR_FW_VER_BUILD_GET(c), reason,
938 FW_HDR_FW_VER_MAJOR_GET(k), FW_HDR_FW_VER_MINOR_GET(k),
939 FW_HDR_FW_VER_MICRO_GET(k), FW_HDR_FW_VER_BUILD_GET(k));
944 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
945 const u8 *fw_data, unsigned int fw_size,
946 struct fw_hdr *card_fw, enum dev_state state,
949 int ret, card_fw_usable, fs_fw_usable;
950 const struct fw_hdr *fs_fw;
951 const struct fw_hdr *drv_fw;
953 drv_fw = &fw_info->fw_hdr;
955 /* Read the header of the firmware on the card */
956 ret = -t4_read_flash(adap, FLASH_FW_START,
957 sizeof(*card_fw) / sizeof(uint32_t),
958 (uint32_t *)card_fw, 1);
960 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
962 dev_err(adap->pdev_dev,
963 "Unable to read card's firmware header: %d\n", ret);
967 if (fw_data != NULL) {
968 fs_fw = (const void *)fw_data;
969 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
975 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
976 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
977 /* Common case: the firmware on the card is an exact match and
978 * the filesystem one is an exact match too, or the filesystem
979 * one is absent/incompatible.
981 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
982 should_install_fs_fw(adap, card_fw_usable,
983 be32_to_cpu(fs_fw->fw_ver),
984 be32_to_cpu(card_fw->fw_ver))) {
985 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
988 dev_err(adap->pdev_dev,
989 "failed to install firmware: %d\n", ret);
993 /* Installed successfully, update the cached header too. */
994 memcpy(card_fw, fs_fw, sizeof(*card_fw));
996 *reset = 0; /* already reset as part of load_fw */
999 if (!card_fw_usable) {
1002 d = be32_to_cpu(drv_fw->fw_ver);
1003 c = be32_to_cpu(card_fw->fw_ver);
1004 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
1006 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
1008 "driver compiled with %d.%d.%d.%d, "
1009 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
1011 FW_HDR_FW_VER_MAJOR_GET(d), FW_HDR_FW_VER_MINOR_GET(d),
1012 FW_HDR_FW_VER_MICRO_GET(d), FW_HDR_FW_VER_BUILD_GET(d),
1013 FW_HDR_FW_VER_MAJOR_GET(c), FW_HDR_FW_VER_MINOR_GET(c),
1014 FW_HDR_FW_VER_MICRO_GET(c), FW_HDR_FW_VER_BUILD_GET(c),
1015 FW_HDR_FW_VER_MAJOR_GET(k), FW_HDR_FW_VER_MINOR_GET(k),
1016 FW_HDR_FW_VER_MICRO_GET(k), FW_HDR_FW_VER_BUILD_GET(k));
1021 /* We're using whatever's on the card and it's known to be good. */
1022 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
1023 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
1030 * t4_flash_erase_sectors - erase a range of flash sectors
1031 * @adapter: the adapter
1032 * @start: the first sector to erase
1033 * @end: the last sector to erase
1035 * Erases the sectors in the given inclusive range.
1037 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
1041 while (start <= end) {
1042 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
1043 (ret = sf1_write(adapter, 4, 0, 1,
1044 SF_ERASE_SECTOR | (start << 8))) != 0 ||
1045 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
1046 dev_err(adapter->pdev_dev,
1047 "erase of flash sector %d failed, error %d\n",
1053 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
1058 * t4_flash_cfg_addr - return the address of the flash configuration file
1059 * @adapter: the adapter
1061 * Return the address within the flash where the Firmware Configuration
1064 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
1066 if (adapter->params.sf_size == 0x100000)
1067 return FLASH_FPGA_CFG_START;
1069 return FLASH_CFG_START;
1073 * t4_load_cfg - download config file
1074 * @adap: the adapter
1075 * @cfg_data: the cfg text file to write
1076 * @size: text file size
1078 * Write the supplied config text file to the card's serial flash.
1080 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
1084 unsigned int flash_cfg_start_sec;
1085 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
1087 addr = t4_flash_cfg_addr(adap);
1088 flash_cfg_start_sec = addr / SF_SEC_SIZE;
1090 if (size > FLASH_CFG_MAX_SIZE) {
1091 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
1092 FLASH_CFG_MAX_SIZE);
1096 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
1098 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
1099 flash_cfg_start_sec + i - 1);
1101 * If size == 0 then we're simply erasing the FLASH sectors associated
1102 * with the on-adapter Firmware Configuration File.
1104 if (ret || size == 0)
1107 /* this will write to the flash up to SF_PAGE_SIZE at a time */
1108 for (i = 0; i < size; i += SF_PAGE_SIZE) {
1109 if ((size - i) < SF_PAGE_SIZE)
1113 ret = t4_write_flash(adap, addr, n, cfg_data);
1117 addr += SF_PAGE_SIZE;
1118 cfg_data += SF_PAGE_SIZE;
1123 dev_err(adap->pdev_dev, "config file %s failed %d\n",
1124 (size == 0 ? "clear" : "download"), ret);
1129 * t4_load_fw - download firmware
1130 * @adap: the adapter
1131 * @fw_data: the firmware image to write
1134 * Write the supplied firmware image to the card's serial flash.
1136 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
1141 u8 first_page[SF_PAGE_SIZE];
1142 const __be32 *p = (const __be32 *)fw_data;
1143 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
1144 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
1145 unsigned int fw_img_start = adap->params.sf_fw_start;
1146 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
1149 dev_err(adap->pdev_dev, "FW image has no data\n");
1153 dev_err(adap->pdev_dev,
1154 "FW image size not multiple of 512 bytes\n");
1157 if (ntohs(hdr->len512) * 512 != size) {
1158 dev_err(adap->pdev_dev,
1159 "FW image size differs from size in FW header\n");
1162 if (size > FW_MAX_SIZE) {
1163 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
1168 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
1169 csum += ntohl(p[i]);
1171 if (csum != 0xffffffff) {
1172 dev_err(adap->pdev_dev,
1173 "corrupted firmware image, checksum %#x\n", csum);
1177 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
1178 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
1183 * We write the correct version at the end so the driver can see a bad
1184 * version if the FW write fails. Start by writing a copy of the
1185 * first page with a bad version.
1187 memcpy(first_page, fw_data, SF_PAGE_SIZE);
1188 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
1189 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
1193 addr = fw_img_start;
1194 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
1195 addr += SF_PAGE_SIZE;
1196 fw_data += SF_PAGE_SIZE;
1197 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
1202 ret = t4_write_flash(adap,
1203 fw_img_start + offsetof(struct fw_hdr, fw_ver),
1204 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
1207 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
1212 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1213 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG)
1216 * t4_link_start - apply link configuration to MAC/PHY
1217 * @phy: the PHY to setup
1218 * @mac: the MAC to setup
1219 * @lc: the requested link configuration
1221 * Set up a port's MAC and PHY according to a desired link configuration.
1222 * - If the PHY can auto-negotiate first decide what to advertise, then
1223 * enable/disable auto-negotiation as desired, and reset.
1224 * - If the PHY does not auto-negotiate just reset it.
1225 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1226 * otherwise do it later based on the outcome of auto-negotiation.
1228 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
1229 struct link_config *lc)
1231 struct fw_port_cmd c;
1232 unsigned int fc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO);
1235 if (lc->requested_fc & PAUSE_RX)
1236 fc |= FW_PORT_CAP_FC_RX;
1237 if (lc->requested_fc & PAUSE_TX)
1238 fc |= FW_PORT_CAP_FC_TX;
1240 memset(&c, 0, sizeof(c));
1241 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
1242 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
1243 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1246 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
1247 c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc);
1248 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1249 } else if (lc->autoneg == AUTONEG_DISABLE) {
1250 c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi);
1251 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1253 c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi);
1255 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1259 * t4_restart_aneg - restart autonegotiation
1260 * @adap: the adapter
1261 * @mbox: mbox to use for the FW command
1262 * @port: the port id
1264 * Restarts autonegotiation for the selected port.
1266 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
1268 struct fw_port_cmd c;
1270 memset(&c, 0, sizeof(c));
1271 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
1272 FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
1273 c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
1275 c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG);
1276 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
1279 typedef void (*int_handler_t)(struct adapter *adap);
1282 unsigned int mask; /* bits to check in interrupt status */
1283 const char *msg; /* message to print or NULL */
1284 short stat_idx; /* stat counter to increment or -1 */
1285 unsigned short fatal; /* whether the condition reported is fatal */
1286 int_handler_t int_handler; /* platform-specific int handler */
1290 * t4_handle_intr_status - table driven interrupt handler
1291 * @adapter: the adapter that generated the interrupt
1292 * @reg: the interrupt status register to process
1293 * @acts: table of interrupt actions
1295 * A table driven interrupt handler that applies a set of masks to an
1296 * interrupt status word and performs the corresponding actions if the
1297 * interrupts described by the mask have occurred. The actions include
1298 * optionally emitting a warning or alert message. The table is terminated
1299 * by an entry specifying mask 0. Returns the number of fatal interrupt
1302 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
1303 const struct intr_info *acts)
1306 unsigned int mask = 0;
1307 unsigned int status = t4_read_reg(adapter, reg);
1309 for ( ; acts->mask; ++acts) {
1310 if (!(status & acts->mask))
1314 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1315 status & acts->mask);
1316 } else if (acts->msg && printk_ratelimit())
1317 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
1318 status & acts->mask);
1319 if (acts->int_handler)
1320 acts->int_handler(adapter);
1324 if (status) /* clear processed interrupts */
1325 t4_write_reg(adapter, reg, status);
1330 * Interrupt handler for the PCIE module.
1332 static void pcie_intr_handler(struct adapter *adapter)
1334 static const struct intr_info sysbus_intr_info[] = {
1335 { RNPP, "RXNP array parity error", -1, 1 },
1336 { RPCP, "RXPC array parity error", -1, 1 },
1337 { RCIP, "RXCIF array parity error", -1, 1 },
1338 { RCCP, "Rx completions control array parity error", -1, 1 },
1339 { RFTP, "RXFT array parity error", -1, 1 },
1342 static const struct intr_info pcie_port_intr_info[] = {
1343 { TPCP, "TXPC array parity error", -1, 1 },
1344 { TNPP, "TXNP array parity error", -1, 1 },
1345 { TFTP, "TXFT array parity error", -1, 1 },
1346 { TCAP, "TXCA array parity error", -1, 1 },
1347 { TCIP, "TXCIF array parity error", -1, 1 },
1348 { RCAP, "RXCA array parity error", -1, 1 },
1349 { OTDD, "outbound request TLP discarded", -1, 1 },
1350 { RDPE, "Rx data parity error", -1, 1 },
1351 { TDUE, "Tx uncorrectable data error", -1, 1 },
1354 static const struct intr_info pcie_intr_info[] = {
1355 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
1356 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
1357 { MSIDATAPERR, "MSI data parity error", -1, 1 },
1358 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
1359 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
1360 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
1361 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
1362 { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
1363 { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
1364 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
1365 { CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
1366 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
1367 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
1368 { DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
1369 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
1370 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
1371 { HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
1372 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
1373 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
1374 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
1375 { FIDPERR, "PCI FID parity error", -1, 1 },
1376 { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
1377 { MATAGPERR, "PCI MA tag parity error", -1, 1 },
1378 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
1379 { RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
1380 { RXWRPERR, "PCI Rx write parity error", -1, 1 },
1381 { RPLPERR, "PCI replay buffer parity error", -1, 1 },
1382 { PCIESINT, "PCI core secondary fault", -1, 1 },
1383 { PCIEPINT, "PCI core primary fault", -1, 1 },
1384 { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 },
1388 static struct intr_info t5_pcie_intr_info[] = {
1389 { MSTGRPPERR, "Master Response Read Queue parity error",
1391 { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
1392 { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
1393 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
1394 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
1395 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
1396 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
1397 { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
1399 { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
1401 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
1402 { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
1403 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
1404 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
1405 { DREQWRPERR, "PCI DMA channel write request parity error",
1407 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
1408 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
1409 { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
1410 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
1411 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
1412 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
1413 { FIDPERR, "PCI FID parity error", -1, 1 },
1414 { VFIDPERR, "PCI INTx clear parity error", -1, 1 },
1415 { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
1416 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
1417 { IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
1419 { IPRXDATAGRPPERR, "PCI IP Rx data group parity error", -1, 1 },
1420 { RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
1421 { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
1422 { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
1423 { READRSPERR, "Outbound read error", -1, 0 },
1429 fat = t4_handle_intr_status(adapter,
1430 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
1432 t4_handle_intr_status(adapter,
1433 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
1434 pcie_port_intr_info) +
1435 t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
1436 is_t4(adapter->params.chip) ?
1437 pcie_intr_info : t5_pcie_intr_info);
1440 t4_fatal_err(adapter);
1444 * TP interrupt handler.
1446 static void tp_intr_handler(struct adapter *adapter)
1448 static const struct intr_info tp_intr_info[] = {
1449 { 0x3fffffff, "TP parity error", -1, 1 },
1450 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
1454 if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info))
1455 t4_fatal_err(adapter);
1459 * SGE interrupt handler.
1461 static void sge_intr_handler(struct adapter *adapter)
1465 static const struct intr_info sge_intr_info[] = {
1466 { ERR_CPL_EXCEED_IQE_SIZE,
1467 "SGE received CPL exceeding IQE size", -1, 1 },
1468 { ERR_INVALID_CIDX_INC,
1469 "SGE GTS CIDX increment too large", -1, 0 },
1470 { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
1471 { DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
1472 { DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
1473 { ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
1474 { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,
1475 "SGE IQID > 1023 received CPL for FL", -1, 0 },
1476 { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
1478 { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
1480 { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
1482 { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
1484 { ERR_ING_CTXT_PRIO,
1485 "SGE too many priority ingress contexts", -1, 0 },
1486 { ERR_EGR_CTXT_PRIO,
1487 "SGE too many priority egress contexts", -1, 0 },
1488 { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
1489 { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
1493 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) |
1494 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32);
1496 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
1497 (unsigned long long)v);
1498 t4_write_reg(adapter, SGE_INT_CAUSE1, v);
1499 t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32);
1502 if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) ||
1504 t4_fatal_err(adapter);
1508 * CIM interrupt handler.
1510 static void cim_intr_handler(struct adapter *adapter)
1512 static const struct intr_info cim_intr_info[] = {
1513 { PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
1514 { OBQPARERR, "CIM OBQ parity error", -1, 1 },
1515 { IBQPARERR, "CIM IBQ parity error", -1, 1 },
1516 { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
1517 { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
1518 { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
1519 { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
1522 static const struct intr_info cim_upintr_info[] = {
1523 { RSVDSPACEINT, "CIM reserved space access", -1, 1 },
1524 { ILLTRANSINT, "CIM illegal transaction", -1, 1 },
1525 { ILLWRINT, "CIM illegal write", -1, 1 },
1526 { ILLRDINT, "CIM illegal read", -1, 1 },
1527 { ILLRDBEINT, "CIM illegal read BE", -1, 1 },
1528 { ILLWRBEINT, "CIM illegal write BE", -1, 1 },
1529 { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
1530 { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
1531 { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
1532 { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
1533 { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
1534 { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
1535 { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
1536 { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
1537 { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
1538 { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
1539 { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
1540 { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
1541 { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
1542 { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
1543 { SGLRDPLINT , "CIM single read from PL space", -1, 1 },
1544 { SGLWRPLINT , "CIM single write to PL space", -1, 1 },
1545 { BLKRDPLINT , "CIM block read from PL space", -1, 1 },
1546 { BLKWRPLINT , "CIM block write to PL space", -1, 1 },
1547 { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
1548 { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
1549 { TIMEOUTINT , "CIM PIF timeout", -1, 1 },
1550 { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
1556 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
1558 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE,
1561 t4_fatal_err(adapter);
1565 * ULP RX interrupt handler.
1567 static void ulprx_intr_handler(struct adapter *adapter)
1569 static const struct intr_info ulprx_intr_info[] = {
1570 { 0x1800000, "ULPRX context error", -1, 1 },
1571 { 0x7fffff, "ULPRX parity error", -1, 1 },
1575 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info))
1576 t4_fatal_err(adapter);
1580 * ULP TX interrupt handler.
1582 static void ulptx_intr_handler(struct adapter *adapter)
1584 static const struct intr_info ulptx_intr_info[] = {
1585 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
1587 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
1589 { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
1591 { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
1593 { 0xfffffff, "ULPTX parity error", -1, 1 },
1597 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info))
1598 t4_fatal_err(adapter);
1602 * PM TX interrupt handler.
1604 static void pmtx_intr_handler(struct adapter *adapter)
1606 static const struct intr_info pmtx_intr_info[] = {
1607 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
1608 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
1609 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
1610 { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
1611 { PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 },
1612 { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
1613 { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 },
1614 { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
1615 { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
1619 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info))
1620 t4_fatal_err(adapter);
1624 * PM RX interrupt handler.
1626 static void pmrx_intr_handler(struct adapter *adapter)
1628 static const struct intr_info pmrx_intr_info[] = {
1629 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
1630 { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 },
1631 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
1632 { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 },
1633 { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
1634 { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
1638 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info))
1639 t4_fatal_err(adapter);
1643 * CPL switch interrupt handler.
1645 static void cplsw_intr_handler(struct adapter *adapter)
1647 static const struct intr_info cplsw_intr_info[] = {
1648 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
1649 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
1650 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
1651 { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
1652 { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
1653 { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
1657 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info))
1658 t4_fatal_err(adapter);
1662 * LE interrupt handler.
1664 static void le_intr_handler(struct adapter *adap)
1666 static const struct intr_info le_intr_info[] = {
1667 { LIPMISS, "LE LIP miss", -1, 0 },
1668 { LIP0, "LE 0 LIP error", -1, 0 },
1669 { PARITYERR, "LE parity error", -1, 1 },
1670 { UNKNOWNCMD, "LE unknown command", -1, 1 },
1671 { REQQPARERR, "LE request queue parity error", -1, 1 },
1675 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info))
1680 * MPS interrupt handler.
1682 static void mps_intr_handler(struct adapter *adapter)
1684 static const struct intr_info mps_rx_intr_info[] = {
1685 { 0xffffff, "MPS Rx parity error", -1, 1 },
1688 static const struct intr_info mps_tx_intr_info[] = {
1689 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
1690 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
1691 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
1692 { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 },
1693 { BUBBLE, "MPS Tx underflow", -1, 1 },
1694 { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
1695 { FRMERR, "MPS Tx framing error", -1, 1 },
1698 static const struct intr_info mps_trc_intr_info[] = {
1699 { FILTMEM, "MPS TRC filter parity error", -1, 1 },
1700 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
1701 { MISCPERR, "MPS TRC misc parity error", -1, 1 },
1704 static const struct intr_info mps_stat_sram_intr_info[] = {
1705 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
1708 static const struct intr_info mps_stat_tx_intr_info[] = {
1709 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
1712 static const struct intr_info mps_stat_rx_intr_info[] = {
1713 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
1716 static const struct intr_info mps_cls_intr_info[] = {
1717 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
1718 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
1719 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
1725 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE,
1727 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE,
1729 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE,
1730 mps_trc_intr_info) +
1731 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM,
1732 mps_stat_sram_intr_info) +
1733 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
1734 mps_stat_tx_intr_info) +
1735 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
1736 mps_stat_rx_intr_info) +
1737 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE,
1740 t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT |
1741 RXINT | TXINT | STATINT);
1742 t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */
1744 t4_fatal_err(adapter);
1747 #define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE)
1750 * EDC/MC interrupt handler.
1752 static void mem_intr_handler(struct adapter *adapter, int idx)
1754 static const char name[3][5] = { "EDC0", "EDC1", "MC" };
1756 unsigned int addr, cnt_addr, v;
1758 if (idx <= MEM_EDC1) {
1759 addr = EDC_REG(EDC_INT_CAUSE, idx);
1760 cnt_addr = EDC_REG(EDC_ECC_STATUS, idx);
1762 addr = MC_INT_CAUSE;
1763 cnt_addr = MC_ECC_STATUS;
1766 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
1767 if (v & PERR_INT_CAUSE)
1768 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
1770 if (v & ECC_CE_INT_CAUSE) {
1771 u32 cnt = ECC_CECNT_GET(t4_read_reg(adapter, cnt_addr));
1773 t4_write_reg(adapter, cnt_addr, ECC_CECNT_MASK);
1774 if (printk_ratelimit())
1775 dev_warn(adapter->pdev_dev,
1776 "%u %s correctable ECC data error%s\n",
1777 cnt, name[idx], cnt > 1 ? "s" : "");
1779 if (v & ECC_UE_INT_CAUSE)
1780 dev_alert(adapter->pdev_dev,
1781 "%s uncorrectable ECC data error\n", name[idx]);
1783 t4_write_reg(adapter, addr, v);
1784 if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE))
1785 t4_fatal_err(adapter);
1789 * MA interrupt handler.
1791 static void ma_intr_handler(struct adapter *adap)
1793 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE);
1795 if (status & MEM_PERR_INT_CAUSE)
1796 dev_alert(adap->pdev_dev,
1797 "MA parity error, parity status %#x\n",
1798 t4_read_reg(adap, MA_PARITY_ERROR_STATUS));
1799 if (status & MEM_WRAP_INT_CAUSE) {
1800 v = t4_read_reg(adap, MA_INT_WRAP_STATUS);
1801 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
1802 "client %u to address %#x\n",
1803 MEM_WRAP_CLIENT_NUM_GET(v),
1804 MEM_WRAP_ADDRESS_GET(v) << 4);
1806 t4_write_reg(adap, MA_INT_CAUSE, status);
1811 * SMB interrupt handler.
1813 static void smb_intr_handler(struct adapter *adap)
1815 static const struct intr_info smb_intr_info[] = {
1816 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
1817 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
1818 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
1822 if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info))
1827 * NC-SI interrupt handler.
1829 static void ncsi_intr_handler(struct adapter *adap)
1831 static const struct intr_info ncsi_intr_info[] = {
1832 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
1833 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
1834 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
1835 { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
1839 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info))
1844 * XGMAC interrupt handler.
1846 static void xgmac_intr_handler(struct adapter *adap, int port)
1848 u32 v, int_cause_reg;
1850 if (is_t4(adap->params.chip))
1851 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE);
1853 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE);
1855 v = t4_read_reg(adap, int_cause_reg);
1857 v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR;
1861 if (v & TXFIFO_PRTY_ERR)
1862 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
1864 if (v & RXFIFO_PRTY_ERR)
1865 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
1867 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v);
1872 * PL interrupt handler.
1874 static void pl_intr_handler(struct adapter *adap)
1876 static const struct intr_info pl_intr_info[] = {
1877 { FATALPERR, "T4 fatal parity error", -1, 1 },
1878 { PERRVFID, "PL VFID_MAP parity error", -1, 1 },
1882 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info))
1886 #define PF_INTR_MASK (PFSW)
1887 #define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
1888 EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \
1889 CPL_SWITCH | SGE | ULP_TX)
1892 * t4_slow_intr_handler - control path interrupt handler
1893 * @adapter: the adapter
1895 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
1896 * The designation 'slow' is because it involves register reads, while
1897 * data interrupts typically don't involve any MMIOs.
1899 int t4_slow_intr_handler(struct adapter *adapter)
1901 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE);
1903 if (!(cause & GLBL_INTR_MASK))
1906 cim_intr_handler(adapter);
1908 mps_intr_handler(adapter);
1910 ncsi_intr_handler(adapter);
1912 pl_intr_handler(adapter);
1914 smb_intr_handler(adapter);
1916 xgmac_intr_handler(adapter, 0);
1918 xgmac_intr_handler(adapter, 1);
1919 if (cause & XGMAC_KR0)
1920 xgmac_intr_handler(adapter, 2);
1921 if (cause & XGMAC_KR1)
1922 xgmac_intr_handler(adapter, 3);
1924 pcie_intr_handler(adapter);
1926 mem_intr_handler(adapter, MEM_MC);
1928 mem_intr_handler(adapter, MEM_EDC0);
1930 mem_intr_handler(adapter, MEM_EDC1);
1932 le_intr_handler(adapter);
1934 tp_intr_handler(adapter);
1936 ma_intr_handler(adapter);
1938 pmtx_intr_handler(adapter);
1940 pmrx_intr_handler(adapter);
1942 ulprx_intr_handler(adapter);
1943 if (cause & CPL_SWITCH)
1944 cplsw_intr_handler(adapter);
1946 sge_intr_handler(adapter);
1948 ulptx_intr_handler(adapter);
1950 /* Clear the interrupts just processed for which we are the master. */
1951 t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK);
1952 (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */
1957 * t4_intr_enable - enable interrupts
1958 * @adapter: the adapter whose interrupts should be enabled
1960 * Enable PF-specific interrupts for the calling function and the top-level
1961 * interrupt concentrator for global interrupts. Interrupts are already
1962 * enabled at each module, here we just enable the roots of the interrupt
1965 * Note: this function should be called only when the driver manages
1966 * non PF-specific interrupts from the various HW modules. Only one PCI
1967 * function at a time should be doing this.
1969 void t4_intr_enable(struct adapter *adapter)
1971 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
1973 t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE |
1974 ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 |
1975 ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 |
1976 ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 |
1977 ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |
1978 ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |
1979 ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR |
1980 DBFIFO_HP_INT | DBFIFO_LP_INT |
1982 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK);
1983 t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf);
1987 * t4_intr_disable - disable interrupts
1988 * @adapter: the adapter whose interrupts should be disabled
1990 * Disable interrupts. We only disable the top-level interrupt
1991 * concentrators. The caller must be a PCI function managing global
1994 void t4_intr_disable(struct adapter *adapter)
1996 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
1998 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0);
1999 t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0);
2003 * hash_mac_addr - return the hash value of a MAC address
2004 * @addr: the 48-bit Ethernet MAC address
2006 * Hashes a MAC address according to the hash function used by HW inexact
2007 * (hash) address matching.
2009 static int hash_mac_addr(const u8 *addr)
2011 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
2012 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
2020 * t4_config_rss_range - configure a portion of the RSS mapping table
2021 * @adapter: the adapter
2022 * @mbox: mbox to use for the FW command
2023 * @viid: virtual interface whose RSS subtable is to be written
2024 * @start: start entry in the table to write
2025 * @n: how many table entries to write
2026 * @rspq: values for the response queue lookup table
2027 * @nrspq: number of values in @rspq
2029 * Programs the selected part of the VI's RSS mapping table with the
2030 * provided values. If @nrspq < @n the supplied values are used repeatedly
2031 * until the full table range is populated.
2033 * The caller must ensure the values in @rspq are in the range allowed for
2036 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2037 int start, int n, const u16 *rspq, unsigned int nrspq)
2040 const u16 *rsp = rspq;
2041 const u16 *rsp_end = rspq + nrspq;
2042 struct fw_rss_ind_tbl_cmd cmd;
2044 memset(&cmd, 0, sizeof(cmd));
2045 cmd.op_to_viid = htonl(FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2046 FW_CMD_REQUEST | FW_CMD_WRITE |
2047 FW_RSS_IND_TBL_CMD_VIID(viid));
2048 cmd.retval_len16 = htonl(FW_LEN16(cmd));
2050 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
2052 int nq = min(n, 32);
2053 __be32 *qp = &cmd.iq0_to_iq2;
2055 cmd.niqid = htons(nq);
2056 cmd.startidx = htons(start);
2064 v = FW_RSS_IND_TBL_CMD_IQ0(*rsp);
2065 if (++rsp >= rsp_end)
2067 v |= FW_RSS_IND_TBL_CMD_IQ1(*rsp);
2068 if (++rsp >= rsp_end)
2070 v |= FW_RSS_IND_TBL_CMD_IQ2(*rsp);
2071 if (++rsp >= rsp_end)
2078 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2086 * t4_config_glbl_rss - configure the global RSS mode
2087 * @adapter: the adapter
2088 * @mbox: mbox to use for the FW command
2089 * @mode: global RSS mode
2090 * @flags: mode-specific flags
2092 * Sets the global RSS mode.
2094 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
2097 struct fw_rss_glb_config_cmd c;
2099 memset(&c, 0, sizeof(c));
2100 c.op_to_write = htonl(FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
2101 FW_CMD_REQUEST | FW_CMD_WRITE);
2102 c.retval_len16 = htonl(FW_LEN16(c));
2103 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
2104 c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
2105 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
2106 c.u.basicvirtual.mode_pkd =
2107 htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
2108 c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags);
2111 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2115 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
2116 * @adap: the adapter
2117 * @v4: holds the TCP/IP counter values
2118 * @v6: holds the TCP/IPv6 counter values
2120 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
2121 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
2123 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
2124 struct tp_tcp_stats *v6)
2126 u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1];
2128 #define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST)
2129 #define STAT(x) val[STAT_IDX(x)]
2130 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
2133 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
2134 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST);
2135 v4->tcpOutRsts = STAT(OUT_RST);
2136 v4->tcpInSegs = STAT64(IN_SEG);
2137 v4->tcpOutSegs = STAT64(OUT_SEG);
2138 v4->tcpRetransSegs = STAT64(RXT_SEG);
2141 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
2142 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST);
2143 v6->tcpOutRsts = STAT(OUT_RST);
2144 v6->tcpInSegs = STAT64(IN_SEG);
2145 v6->tcpOutSegs = STAT64(OUT_SEG);
2146 v6->tcpRetransSegs = STAT64(RXT_SEG);
2154 * t4_read_mtu_tbl - returns the values in the HW path MTU table
2155 * @adap: the adapter
2156 * @mtus: where to store the MTU values
2157 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
2159 * Reads the HW path MTU table.
2161 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
2166 for (i = 0; i < NMTUS; ++i) {
2167 t4_write_reg(adap, TP_MTU_TABLE,
2168 MTUINDEX(0xff) | MTUVALUE(i));
2169 v = t4_read_reg(adap, TP_MTU_TABLE);
2170 mtus[i] = MTUVALUE_GET(v);
2172 mtu_log[i] = MTUWIDTH_GET(v);
2177 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
2178 * @adap: the adapter
2179 * @addr: the indirect TP register address
2180 * @mask: specifies the field within the register to modify
2181 * @val: new value for the field
2183 * Sets a field of an indirect TP register to the given value.
2185 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
2186 unsigned int mask, unsigned int val)
2188 t4_write_reg(adap, TP_PIO_ADDR, addr);
2189 val |= t4_read_reg(adap, TP_PIO_DATA) & ~mask;
2190 t4_write_reg(adap, TP_PIO_DATA, val);
2194 * init_cong_ctrl - initialize congestion control parameters
2195 * @a: the alpha values for congestion control
2196 * @b: the beta values for congestion control
2198 * Initialize the congestion control parameters.
2200 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2202 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
2227 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
2230 b[13] = b[14] = b[15] = b[16] = 3;
2231 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
2232 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
2237 /* The minimum additive increment value for the congestion control table */
2238 #define CC_MIN_INCR 2U
2241 * t4_load_mtus - write the MTU and congestion control HW tables
2242 * @adap: the adapter
2243 * @mtus: the values for the MTU table
2244 * @alpha: the values for the congestion control alpha parameter
2245 * @beta: the values for the congestion control beta parameter
2247 * Write the HW MTU table with the supplied MTUs and the high-speed
2248 * congestion control table with the supplied alpha, beta, and MTUs.
2249 * We write the two tables together because the additive increments
2250 * depend on the MTUs.
2252 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
2253 const unsigned short *alpha, const unsigned short *beta)
2255 static const unsigned int avg_pkts[NCCTRL_WIN] = {
2256 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
2257 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
2258 28672, 40960, 57344, 81920, 114688, 163840, 229376
2263 for (i = 0; i < NMTUS; ++i) {
2264 unsigned int mtu = mtus[i];
2265 unsigned int log2 = fls(mtu);
2267 if (!(mtu & ((1 << log2) >> 2))) /* round */
2269 t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) |
2270 MTUWIDTH(log2) | MTUVALUE(mtu));
2272 for (w = 0; w < NCCTRL_WIN; ++w) {
2275 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
2278 t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) |
2279 (w << 16) | (beta[w] << 13) | inc);
2285 * get_mps_bg_map - return the buffer groups associated with a port
2286 * @adap: the adapter
2287 * @idx: the port index
2289 * Returns a bitmap indicating which MPS buffer groups are associated
2290 * with the given port. Bit i is set if buffer group i is used by the
2293 static unsigned int get_mps_bg_map(struct adapter *adap, int idx)
2295 u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL));
2298 return idx == 0 ? 0xf : 0;
2300 return idx < 2 ? (3 << (2 * idx)) : 0;
2305 * t4_get_port_stats - collect port statistics
2306 * @adap: the adapter
2307 * @idx: the port index
2308 * @p: the stats structure to fill
2310 * Collect statistics related to the given port from HW.
2312 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2314 u32 bgmap = get_mps_bg_map(adap, idx);
2316 #define GET_STAT(name) \
2317 t4_read_reg64(adap, \
2318 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
2319 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
2320 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
2322 p->tx_octets = GET_STAT(TX_PORT_BYTES);
2323 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
2324 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
2325 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
2326 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
2327 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
2328 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
2329 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
2330 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
2331 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
2332 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
2333 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2334 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
2335 p->tx_drop = GET_STAT(TX_PORT_DROP);
2336 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
2337 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
2338 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
2339 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
2340 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
2341 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
2342 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
2343 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
2344 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
2346 p->rx_octets = GET_STAT(RX_PORT_BYTES);
2347 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
2348 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
2349 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
2350 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
2351 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
2352 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2353 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
2354 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
2355 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
2356 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
2357 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
2358 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
2359 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
2360 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
2361 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
2362 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
2363 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
2364 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
2365 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
2366 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
2367 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
2368 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
2369 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
2370 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
2371 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
2372 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
2374 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
2375 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
2376 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
2377 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
2378 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
2379 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
2380 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
2381 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
2388 * t4_wol_magic_enable - enable/disable magic packet WoL
2389 * @adap: the adapter
2390 * @port: the physical port index
2391 * @addr: MAC address expected in magic packets, %NULL to disable
2393 * Enables/disables magic packet wake-on-LAN for the selected port.
2395 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
2398 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
2400 if (is_t4(adap->params.chip)) {
2401 mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO);
2402 mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI);
2403 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
2405 mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO);
2406 mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI);
2407 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
2411 t4_write_reg(adap, mag_id_reg_l,
2412 (addr[2] << 24) | (addr[3] << 16) |
2413 (addr[4] << 8) | addr[5]);
2414 t4_write_reg(adap, mag_id_reg_h,
2415 (addr[0] << 8) | addr[1]);
2417 t4_set_reg_field(adap, port_cfg_reg, MAGICEN,
2418 addr ? MAGICEN : 0);
2422 * t4_wol_pat_enable - enable/disable pattern-based WoL
2423 * @adap: the adapter
2424 * @port: the physical port index
2425 * @map: bitmap of which HW pattern filters to set
2426 * @mask0: byte mask for bytes 0-63 of a packet
2427 * @mask1: byte mask for bytes 64-127 of a packet
2428 * @crc: Ethernet CRC for selected bytes
2429 * @enable: enable/disable switch
2431 * Sets the pattern filters indicated in @map to mask out the bytes
2432 * specified in @mask0/@mask1 in received packets and compare the CRC of
2433 * the resulting packet against @crc. If @enable is %true pattern-based
2434 * WoL is enabled, otherwise disabled.
2436 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2437 u64 mask0, u64 mask1, unsigned int crc, bool enable)
2442 if (is_t4(adap->params.chip))
2443 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
2445 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
2448 t4_set_reg_field(adap, port_cfg_reg, PATEN, 0);
2454 #define EPIO_REG(name) \
2455 (is_t4(adap->params.chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \
2456 T5_PORT_REG(port, MAC_PORT_EPIO_##name))
2458 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
2459 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
2460 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
2462 for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
2466 /* write byte masks */
2467 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
2468 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR);
2469 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2470 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
2474 t4_write_reg(adap, EPIO_REG(DATA0), crc);
2475 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR);
2476 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2477 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
2482 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN);
2486 /* t4_mk_filtdelwr - create a delete filter WR
2487 * @ftid: the filter ID
2488 * @wr: the filter work request to populate
2489 * @qid: ingress queue to receive the delete notification
2491 * Creates a filter work request to delete the supplied filter. If @qid is
2492 * negative the delete notification is suppressed.
2494 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
2496 memset(wr, 0, sizeof(*wr));
2497 wr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
2498 wr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*wr) / 16));
2499 wr->tid_to_iq = htonl(V_FW_FILTER_WR_TID(ftid) |
2500 V_FW_FILTER_WR_NOREPLY(qid < 0));
2501 wr->del_filter_to_l2tix = htonl(F_FW_FILTER_WR_DEL_FILTER);
2503 wr->rx_chan_rx_rpl_iq = htons(V_FW_FILTER_WR_RX_RPL_IQ(qid));
2506 #define INIT_CMD(var, cmd, rd_wr) do { \
2507 (var).op_to_write = htonl(FW_CMD_OP(FW_##cmd##_CMD) | \
2508 FW_CMD_REQUEST | FW_CMD_##rd_wr); \
2509 (var).retval_len16 = htonl(FW_LEN16(var)); \
2512 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
2515 struct fw_ldst_cmd c;
2517 memset(&c, 0, sizeof(c));
2518 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2520 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE));
2521 c.cycles_to_len16 = htonl(FW_LEN16(c));
2522 c.u.addrval.addr = htonl(addr);
2523 c.u.addrval.val = htonl(val);
2525 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2529 * t4_mem_win_read_len - read memory through PCIE memory window
2530 * @adap: the adapter
2531 * @addr: address of first byte requested aligned on 32b.
2532 * @data: len bytes to hold the data read
2533 * @len: amount of data to read from window. Must be <=
2534 * MEMWIN0_APERATURE after adjusting for 16B for T4 and
2535 * 128B for T5 alignment requirements of the the memory window.
2537 * Read len bytes of data from MC starting at @addr.
2539 int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len)
2542 u32 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
2544 /* Align on a 2KB boundary.
2546 off = addr & MEMWIN0_APERTURE;
2547 if ((addr & 3) || (len + off) > MEMWIN0_APERTURE)
2550 t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
2551 (addr & ~MEMWIN0_APERTURE) | win_pf);
2552 t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
2554 for (i = 0; i < len; i += 4)
2555 *data++ = (__force __be32) t4_read_reg(adap,
2556 (MEMWIN0_BASE + off + i));
2562 * t4_mdio_rd - read a PHY register through MDIO
2563 * @adap: the adapter
2564 * @mbox: mailbox to use for the FW command
2565 * @phy_addr: the PHY address
2566 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2567 * @reg: the register to read
2568 * @valp: where to store the value
2570 * Issues a FW command through the given mailbox to read a PHY register.
2572 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2573 unsigned int mmd, unsigned int reg, u16 *valp)
2576 struct fw_ldst_cmd c;
2578 memset(&c, 0, sizeof(c));
2579 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2580 FW_CMD_READ | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2581 c.cycles_to_len16 = htonl(FW_LEN16(c));
2582 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2583 FW_LDST_CMD_MMD(mmd));
2584 c.u.mdio.raddr = htons(reg);
2586 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2588 *valp = ntohs(c.u.mdio.rval);
2593 * t4_mdio_wr - write a PHY register through MDIO
2594 * @adap: the adapter
2595 * @mbox: mailbox to use for the FW command
2596 * @phy_addr: the PHY address
2597 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2598 * @reg: the register to write
2599 * @valp: value to write
2601 * Issues a FW command through the given mailbox to write a PHY register.
2603 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
2604 unsigned int mmd, unsigned int reg, u16 val)
2606 struct fw_ldst_cmd c;
2608 memset(&c, 0, sizeof(c));
2609 c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
2610 FW_CMD_WRITE | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
2611 c.cycles_to_len16 = htonl(FW_LEN16(c));
2612 c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
2613 FW_LDST_CMD_MMD(mmd));
2614 c.u.mdio.raddr = htons(reg);
2615 c.u.mdio.rval = htons(val);
2617 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2621 * t4_fw_hello - establish communication with FW
2622 * @adap: the adapter
2623 * @mbox: mailbox to use for the FW command
2624 * @evt_mbox: mailbox to receive async FW events
2625 * @master: specifies the caller's willingness to be the device master
2626 * @state: returns the current device state (if non-NULL)
2628 * Issues a command to establish communication with FW. Returns either
2629 * an error (negative integer) or the mailbox of the Master PF.
2631 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
2632 enum dev_master master, enum dev_state *state)
2635 struct fw_hello_cmd c;
2637 unsigned int master_mbox;
2638 int retries = FW_CMD_HELLO_RETRIES;
2641 memset(&c, 0, sizeof(c));
2642 INIT_CMD(c, HELLO, WRITE);
2643 c.err_to_clearinit = htonl(
2644 FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
2645 FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
2646 FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
2647 FW_HELLO_CMD_MBMASTER_MASK) |
2648 FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
2649 FW_HELLO_CMD_STAGE(fw_hello_cmd_stage_os) |
2650 FW_HELLO_CMD_CLEARINIT);
2653 * Issue the HELLO command to the firmware. If it's not successful
2654 * but indicates that we got a "busy" or "timeout" condition, retry
2655 * the HELLO until we exhaust our retry limit.
2657 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
2659 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
2664 v = ntohl(c.err_to_clearinit);
2665 master_mbox = FW_HELLO_CMD_MBMASTER_GET(v);
2667 if (v & FW_HELLO_CMD_ERR)
2668 *state = DEV_STATE_ERR;
2669 else if (v & FW_HELLO_CMD_INIT)
2670 *state = DEV_STATE_INIT;
2672 *state = DEV_STATE_UNINIT;
2676 * If we're not the Master PF then we need to wait around for the
2677 * Master PF Driver to finish setting up the adapter.
2679 * Note that we also do this wait if we're a non-Master-capable PF and
2680 * there is no current Master PF; a Master PF may show up momentarily
2681 * and we wouldn't want to fail pointlessly. (This can happen when an
2682 * OS loads lots of different drivers rapidly at the same time). In
2683 * this case, the Master PF returned by the firmware will be
2684 * FW_PCIE_FW_MASTER_MASK so the test below will work ...
2686 if ((v & (FW_HELLO_CMD_ERR|FW_HELLO_CMD_INIT)) == 0 &&
2687 master_mbox != mbox) {
2688 int waiting = FW_CMD_HELLO_TIMEOUT;
2691 * Wait for the firmware to either indicate an error or
2692 * initialized state. If we see either of these we bail out
2693 * and report the issue to the caller. If we exhaust the
2694 * "hello timeout" and we haven't exhausted our retries, try
2695 * again. Otherwise bail with a timeout error.
2704 * If neither Error nor Initialialized are indicated
2705 * by the firmware keep waiting till we exaust our
2706 * timeout ... and then retry if we haven't exhausted
2709 pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
2710 if (!(pcie_fw & (FW_PCIE_FW_ERR|FW_PCIE_FW_INIT))) {
2721 * We either have an Error or Initialized condition
2722 * report errors preferentially.
2725 if (pcie_fw & FW_PCIE_FW_ERR)
2726 *state = DEV_STATE_ERR;
2727 else if (pcie_fw & FW_PCIE_FW_INIT)
2728 *state = DEV_STATE_INIT;
2732 * If we arrived before a Master PF was selected and
2733 * there's not a valid Master PF, grab its identity
2736 if (master_mbox == FW_PCIE_FW_MASTER_MASK &&
2737 (pcie_fw & FW_PCIE_FW_MASTER_VLD))
2738 master_mbox = FW_PCIE_FW_MASTER_GET(pcie_fw);
2747 * t4_fw_bye - end communication with FW
2748 * @adap: the adapter
2749 * @mbox: mailbox to use for the FW command
2751 * Issues a command to terminate communication with FW.
2753 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
2755 struct fw_bye_cmd c;
2757 memset(&c, 0, sizeof(c));
2758 INIT_CMD(c, BYE, WRITE);
2759 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2763 * t4_init_cmd - ask FW to initialize the device
2764 * @adap: the adapter
2765 * @mbox: mailbox to use for the FW command
2767 * Issues a command to FW to partially initialize the device. This
2768 * performs initialization that generally doesn't depend on user input.
2770 int t4_early_init(struct adapter *adap, unsigned int mbox)
2772 struct fw_initialize_cmd c;
2774 memset(&c, 0, sizeof(c));
2775 INIT_CMD(c, INITIALIZE, WRITE);
2776 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2780 * t4_fw_reset - issue a reset to FW
2781 * @adap: the adapter
2782 * @mbox: mailbox to use for the FW command
2783 * @reset: specifies the type of reset to perform
2785 * Issues a reset command of the specified type to FW.
2787 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
2789 struct fw_reset_cmd c;
2791 memset(&c, 0, sizeof(c));
2792 INIT_CMD(c, RESET, WRITE);
2793 c.val = htonl(reset);
2794 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2798 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2799 * @adap: the adapter
2800 * @mbox: mailbox to use for the FW RESET command (if desired)
2801 * @force: force uP into RESET even if FW RESET command fails
2803 * Issues a RESET command to firmware (if desired) with a HALT indication
2804 * and then puts the microprocessor into RESET state. The RESET command
2805 * will only be issued if a legitimate mailbox is provided (mbox <=
2806 * FW_PCIE_FW_MASTER_MASK).
2808 * This is generally used in order for the host to safely manipulate the
2809 * adapter without fear of conflicting with whatever the firmware might
2810 * be doing. The only way out of this state is to RESTART the firmware
2813 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2818 * If a legitimate mailbox is provided, issue a RESET command
2819 * with a HALT indication.
2821 if (mbox <= FW_PCIE_FW_MASTER_MASK) {
2822 struct fw_reset_cmd c;
2824 memset(&c, 0, sizeof(c));
2825 INIT_CMD(c, RESET, WRITE);
2826 c.val = htonl(PIORST | PIORSTMODE);
2827 c.halt_pkd = htonl(FW_RESET_CMD_HALT(1U));
2828 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2832 * Normally we won't complete the operation if the firmware RESET
2833 * command fails but if our caller insists we'll go ahead and put the
2834 * uP into RESET. This can be useful if the firmware is hung or even
2835 * missing ... We'll have to take the risk of putting the uP into
2836 * RESET without the cooperation of firmware in that case.
2838 * We also force the firmware's HALT flag to be on in case we bypassed
2839 * the firmware RESET command above or we're dealing with old firmware
2840 * which doesn't have the HALT capability. This will serve as a flag
2841 * for the incoming firmware to know that it's coming out of a HALT
2842 * rather than a RESET ... if it's new enough to understand that ...
2844 if (ret == 0 || force) {
2845 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);
2846 t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT,
2851 * And we always return the result of the firmware RESET command
2852 * even when we force the uP into RESET ...
2858 * t4_fw_restart - restart the firmware by taking the uP out of RESET
2859 * @adap: the adapter
2860 * @reset: if we want to do a RESET to restart things
2862 * Restart firmware previously halted by t4_fw_halt(). On successful
2863 * return the previous PF Master remains as the new PF Master and there
2864 * is no need to issue a new HELLO command, etc.
2866 * We do this in two ways:
2868 * 1. If we're dealing with newer firmware we'll simply want to take
2869 * the chip's microprocessor out of RESET. This will cause the
2870 * firmware to start up from its start vector. And then we'll loop
2871 * until the firmware indicates it's started again (PCIE_FW.HALT
2872 * reset to 0) or we timeout.
2874 * 2. If we're dealing with older firmware then we'll need to RESET
2875 * the chip since older firmware won't recognize the PCIE_FW.HALT
2876 * flag and automatically RESET itself on startup.
2878 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
2882 * Since we're directing the RESET instead of the firmware
2883 * doing it automatically, we need to clear the PCIE_FW.HALT
2886 t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT, 0);
2889 * If we've been given a valid mailbox, first try to get the
2890 * firmware to do the RESET. If that works, great and we can
2891 * return success. Otherwise, if we haven't been given a
2892 * valid mailbox or the RESET command failed, fall back to
2893 * hitting the chip with a hammer.
2895 if (mbox <= FW_PCIE_FW_MASTER_MASK) {
2896 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
2898 if (t4_fw_reset(adap, mbox,
2899 PIORST | PIORSTMODE) == 0)
2903 t4_write_reg(adap, PL_RST, PIORST | PIORSTMODE);
2908 t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
2909 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
2910 if (!(t4_read_reg(adap, PCIE_FW) & FW_PCIE_FW_HALT))
2921 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
2922 * @adap: the adapter
2923 * @mbox: mailbox to use for the FW RESET command (if desired)
2924 * @fw_data: the firmware image to write
2926 * @force: force upgrade even if firmware doesn't cooperate
2928 * Perform all of the steps necessary for upgrading an adapter's
2929 * firmware image. Normally this requires the cooperation of the
2930 * existing firmware in order to halt all existing activities
2931 * but if an invalid mailbox token is passed in we skip that step
2932 * (though we'll still put the adapter microprocessor into RESET in
2935 * On successful return the new firmware will have been loaded and
2936 * the adapter will have been fully RESET losing all previous setup
2937 * state. On unsuccessful return the adapter may be completely hosed ...
2938 * positive errno indicates that the adapter is ~probably~ intact, a
2939 * negative errno indicates that things are looking bad ...
2941 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
2942 const u8 *fw_data, unsigned int size, int force)
2944 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
2947 ret = t4_fw_halt(adap, mbox, force);
2948 if (ret < 0 && !force)
2951 ret = t4_load_fw(adap, fw_data, size);
2956 * Older versions of the firmware don't understand the new
2957 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
2958 * restart. So for newly loaded older firmware we'll have to do the
2959 * RESET for it so it starts up on a clean slate. We can tell if
2960 * the newly loaded firmware will handle this right by checking
2961 * its header flags to see if it advertises the capability.
2963 reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
2964 return t4_fw_restart(adap, mbox, reset);
2969 * t4_fw_config_file - setup an adapter via a Configuration File
2970 * @adap: the adapter
2971 * @mbox: mailbox to use for the FW command
2972 * @mtype: the memory type where the Configuration File is located
2973 * @maddr: the memory address where the Configuration File is located
2974 * @finiver: return value for CF [fini] version
2975 * @finicsum: return value for CF [fini] checksum
2976 * @cfcsum: return value for CF computed checksum
2978 * Issue a command to get the firmware to process the Configuration
2979 * File located at the specified mtype/maddress. If the Configuration
2980 * File is processed successfully and return value pointers are
2981 * provided, the Configuration File "[fini] section version and
2982 * checksum values will be returned along with the computed checksum.
2983 * It's up to the caller to decide how it wants to respond to the
2984 * checksums not matching but it recommended that a prominant warning
2985 * be emitted in order to help people rapidly identify changed or
2986 * corrupted Configuration Files.
2988 * Also note that it's possible to modify things like "niccaps",
2989 * "toecaps",etc. between processing the Configuration File and telling
2990 * the firmware to use the new configuration. Callers which want to
2991 * do this will need to "hand-roll" their own CAPS_CONFIGS commands for
2992 * Configuration Files if they want to do this.
2994 int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
2995 unsigned int mtype, unsigned int maddr,
2996 u32 *finiver, u32 *finicsum, u32 *cfcsum)
2998 struct fw_caps_config_cmd caps_cmd;
3002 * Tell the firmware to process the indicated Configuration File.
3003 * If there are no errors and the caller has provided return value
3004 * pointers for the [fini] section version, checksum and computed
3005 * checksum, pass those back to the caller.
3007 memset(&caps_cmd, 0, sizeof(caps_cmd));
3008 caps_cmd.op_to_write =
3009 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3012 caps_cmd.cfvalid_to_len16 =
3013 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
3014 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3015 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
3016 FW_LEN16(caps_cmd));
3017 ret = t4_wr_mbox(adap, mbox, &caps_cmd, sizeof(caps_cmd), &caps_cmd);
3022 *finiver = ntohl(caps_cmd.finiver);
3024 *finicsum = ntohl(caps_cmd.finicsum);
3026 *cfcsum = ntohl(caps_cmd.cfcsum);
3029 * And now tell the firmware to use the configuration we just loaded.
3031 caps_cmd.op_to_write =
3032 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3035 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3036 return t4_wr_mbox(adap, mbox, &caps_cmd, sizeof(caps_cmd), NULL);
3040 * t4_fixup_host_params - fix up host-dependent parameters
3041 * @adap: the adapter
3042 * @page_size: the host's Base Page Size
3043 * @cache_line_size: the host's Cache Line Size
3045 * Various registers in T4 contain values which are dependent on the
3046 * host's Base Page and Cache Line Sizes. This function will fix all of
3047 * those registers with the appropriate values as passed in ...
3049 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3050 unsigned int cache_line_size)
3052 unsigned int page_shift = fls(page_size) - 1;
3053 unsigned int sge_hps = page_shift - 10;
3054 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3055 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3056 unsigned int fl_align_log = fls(fl_align) - 1;
3058 t4_write_reg(adap, SGE_HOST_PAGE_SIZE,
3059 HOSTPAGESIZEPF0(sge_hps) |
3060 HOSTPAGESIZEPF1(sge_hps) |
3061 HOSTPAGESIZEPF2(sge_hps) |
3062 HOSTPAGESIZEPF3(sge_hps) |
3063 HOSTPAGESIZEPF4(sge_hps) |
3064 HOSTPAGESIZEPF5(sge_hps) |
3065 HOSTPAGESIZEPF6(sge_hps) |
3066 HOSTPAGESIZEPF7(sge_hps));
3068 t4_set_reg_field(adap, SGE_CONTROL,
3069 INGPADBOUNDARY_MASK |
3070 EGRSTATUSPAGESIZE_MASK,
3071 INGPADBOUNDARY(fl_align_log - 5) |
3072 EGRSTATUSPAGESIZE(stat_len != 64));
3075 * Adjust various SGE Free List Host Buffer Sizes.
3077 * This is something of a crock since we're using fixed indices into
3078 * the array which are also known by the sge.c code and the T4
3079 * Firmware Configuration File. We need to come up with a much better
3080 * approach to managing this array. For now, the first four entries
3085 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3086 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3088 * For the single-MTU buffers in unpacked mode we need to include
3089 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3090 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3091 * Padding boundry. All of these are accommodated in the Factory
3092 * Default Firmware Configuration File but we need to adjust it for
3093 * this host's cache line size.
3095 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0, page_size);
3096 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2,
3097 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2) + fl_align-1)
3099 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3,
3100 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3) + fl_align-1)
3103 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(page_shift - 12));
3109 * t4_fw_initialize - ask FW to initialize the device
3110 * @adap: the adapter
3111 * @mbox: mailbox to use for the FW command
3113 * Issues a command to FW to partially initialize the device. This
3114 * performs initialization that generally doesn't depend on user input.
3116 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3118 struct fw_initialize_cmd c;
3120 memset(&c, 0, sizeof(c));
3121 INIT_CMD(c, INITIALIZE, WRITE);
3122 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3126 * t4_query_params - query FW or device parameters
3127 * @adap: the adapter
3128 * @mbox: mailbox to use for the FW command
3131 * @nparams: the number of parameters
3132 * @params: the parameter names
3133 * @val: the parameter values
3135 * Reads the value of FW or device parameters. Up to 7 parameters can be
3138 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3139 unsigned int vf, unsigned int nparams, const u32 *params,
3143 struct fw_params_cmd c;
3144 __be32 *p = &c.param[0].mnem;
3149 memset(&c, 0, sizeof(c));
3150 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
3151 FW_CMD_READ | FW_PARAMS_CMD_PFN(pf) |
3152 FW_PARAMS_CMD_VFN(vf));
3153 c.retval_len16 = htonl(FW_LEN16(c));
3154 for (i = 0; i < nparams; i++, p += 2)
3155 *p = htonl(*params++);
3157 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3159 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3165 * t4_set_params - sets FW or device parameters
3166 * @adap: the adapter
3167 * @mbox: mailbox to use for the FW command
3170 * @nparams: the number of parameters
3171 * @params: the parameter names
3172 * @val: the parameter values
3174 * Sets the value of FW or device parameters. Up to 7 parameters can be
3175 * specified at once.
3177 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3178 unsigned int vf, unsigned int nparams, const u32 *params,
3181 struct fw_params_cmd c;
3182 __be32 *p = &c.param[0].mnem;
3187 memset(&c, 0, sizeof(c));
3188 c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
3189 FW_CMD_WRITE | FW_PARAMS_CMD_PFN(pf) |
3190 FW_PARAMS_CMD_VFN(vf));
3191 c.retval_len16 = htonl(FW_LEN16(c));
3193 *p++ = htonl(*params++);
3194 *p++ = htonl(*val++);
3197 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3201 * t4_cfg_pfvf - configure PF/VF resource limits
3202 * @adap: the adapter
3203 * @mbox: mailbox to use for the FW command
3204 * @pf: the PF being configured
3205 * @vf: the VF being configured
3206 * @txq: the max number of egress queues
3207 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
3208 * @rxqi: the max number of interrupt-capable ingress queues
3209 * @rxq: the max number of interruptless ingress queues
3210 * @tc: the PCI traffic class
3211 * @vi: the max number of virtual interfaces
3212 * @cmask: the channel access rights mask for the PF/VF
3213 * @pmask: the port access rights mask for the PF/VF
3214 * @nexact: the maximum number of exact MPS filters
3215 * @rcaps: read capabilities
3216 * @wxcaps: write/execute capabilities
3218 * Configures resource limits and capabilities for a physical or virtual
3221 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
3222 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
3223 unsigned int rxqi, unsigned int rxq, unsigned int tc,
3224 unsigned int vi, unsigned int cmask, unsigned int pmask,
3225 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
3227 struct fw_pfvf_cmd c;
3229 memset(&c, 0, sizeof(c));
3230 c.op_to_vfn = htonl(FW_CMD_OP(FW_PFVF_CMD) | FW_CMD_REQUEST |
3231 FW_CMD_WRITE | FW_PFVF_CMD_PFN(pf) |
3232 FW_PFVF_CMD_VFN(vf));
3233 c.retval_len16 = htonl(FW_LEN16(c));
3234 c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) |
3235 FW_PFVF_CMD_NIQ(rxq));
3236 c.type_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) |
3237 FW_PFVF_CMD_PMASK(pmask) |
3238 FW_PFVF_CMD_NEQ(txq));
3239 c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) |
3240 FW_PFVF_CMD_NEXACTF(nexact));
3241 c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS(rcaps) |
3242 FW_PFVF_CMD_WX_CAPS(wxcaps) |
3243 FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
3244 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3248 * t4_alloc_vi - allocate a virtual interface
3249 * @adap: the adapter
3250 * @mbox: mailbox to use for the FW command
3251 * @port: physical port associated with the VI
3252 * @pf: the PF owning the VI
3253 * @vf: the VF owning the VI
3254 * @nmac: number of MAC addresses needed (1 to 5)
3255 * @mac: the MAC addresses of the VI
3256 * @rss_size: size of RSS table slice associated with this VI
3258 * Allocates a virtual interface for the given physical port. If @mac is
3259 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3260 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3261 * stored consecutively so the space needed is @nmac * 6 bytes.
3262 * Returns a negative error number or the non-negative VI id.
3264 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3265 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3266 unsigned int *rss_size)
3271 memset(&c, 0, sizeof(c));
3272 c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST |
3273 FW_CMD_WRITE | FW_CMD_EXEC |
3274 FW_VI_CMD_PFN(pf) | FW_VI_CMD_VFN(vf));
3275 c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC | FW_LEN16(c));
3276 c.portid_pkd = FW_VI_CMD_PORTID(port);
3279 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3284 memcpy(mac, c.mac, sizeof(c.mac));
3287 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3289 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3291 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3293 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
3297 *rss_size = FW_VI_CMD_RSSSIZE_GET(ntohs(c.rsssize_pkd));
3298 return FW_VI_CMD_VIID_GET(ntohs(c.type_viid));
3302 * t4_set_rxmode - set Rx properties of a virtual interface
3303 * @adap: the adapter
3304 * @mbox: mailbox to use for the FW command
3306 * @mtu: the new MTU or -1
3307 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3308 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3309 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3310 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
3311 * @sleep_ok: if true we may sleep while awaiting command completion
3313 * Sets Rx properties of a virtual interface.
3315 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3316 int mtu, int promisc, int all_multi, int bcast, int vlanex,
3319 struct fw_vi_rxmode_cmd c;
3321 /* convert to FW values */
3323 mtu = FW_RXMODE_MTU_NO_CHG;
3325 promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK;
3327 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK;
3329 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK;
3331 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_MASK;
3333 memset(&c, 0, sizeof(c));
3334 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST |
3335 FW_CMD_WRITE | FW_VI_RXMODE_CMD_VIID(viid));
3336 c.retval_len16 = htonl(FW_LEN16(c));
3337 c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU(mtu) |
3338 FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3339 FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3340 FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3341 FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3342 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3346 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
3347 * @adap: the adapter
3348 * @mbox: mailbox to use for the FW command
3350 * @free: if true any existing filters for this VI id are first removed
3351 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
3352 * @addr: the MAC address(es)
3353 * @idx: where to store the index of each allocated filter
3354 * @hash: pointer to hash address filter bitmap
3355 * @sleep_ok: call is allowed to sleep
3357 * Allocates an exact-match filter for each of the supplied addresses and
3358 * sets it to the corresponding address. If @idx is not %NULL it should
3359 * have at least @naddr entries, each of which will be set to the index of
3360 * the filter allocated for the corresponding MAC address. If a filter
3361 * could not be allocated for an address its index is set to 0xffff.
3362 * If @hash is not %NULL addresses that fail to allocate an exact filter
3363 * are hashed and update the hash filter bitmap pointed at by @hash.
3365 * Returns a negative error number or the number of filters allocated.
3367 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
3368 unsigned int viid, bool free, unsigned int naddr,
3369 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
3372 struct fw_vi_mac_cmd c;
3373 struct fw_vi_mac_exact *p;
3374 unsigned int max_naddr = is_t4(adap->params.chip) ?
3375 NUM_MPS_CLS_SRAM_L_INSTANCES :
3376 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3381 memset(&c, 0, sizeof(c));
3382 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3383 FW_CMD_WRITE | (free ? FW_CMD_EXEC : 0) |
3384 FW_VI_MAC_CMD_VIID(viid));
3385 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS(free) |
3386 FW_CMD_LEN16((naddr + 2) / 2));
3388 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
3389 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
3390 FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
3391 memcpy(p->macaddr, addr[i], sizeof(p->macaddr));
3394 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
3398 for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
3399 u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
3402 idx[i] = index >= max_naddr ? 0xffff : index;
3403 if (index < max_naddr)
3406 *hash |= (1ULL << hash_mac_addr(addr[i]));
3412 * t4_change_mac - modifies the exact-match filter for a MAC address
3413 * @adap: the adapter
3414 * @mbox: mailbox to use for the FW command
3416 * @idx: index of existing filter for old value of MAC address, or -1
3417 * @addr: the new MAC address value
3418 * @persist: whether a new MAC allocation should be persistent
3419 * @add_smt: if true also add the address to the HW SMT
3421 * Modifies an exact-match filter and sets it to the new MAC address.
3422 * Note that in general it is not possible to modify the value of a given
3423 * filter so the generic way to modify an address filter is to free the one
3424 * being used by the old address value and allocate a new filter for the
3425 * new address value. @idx can be -1 if the address is a new addition.
3427 * Returns a negative error number or the index of the filter with the new
3430 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3431 int idx, const u8 *addr, bool persist, bool add_smt)
3434 struct fw_vi_mac_cmd c;
3435 struct fw_vi_mac_exact *p = c.u.exact;
3436 unsigned int max_mac_addr = is_t4(adap->params.chip) ?
3437 NUM_MPS_CLS_SRAM_L_INSTANCES :
3438 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
3440 if (idx < 0) /* new allocation */
3441 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3442 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3444 memset(&c, 0, sizeof(c));
3445 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3446 FW_CMD_WRITE | FW_VI_MAC_CMD_VIID(viid));
3447 c.freemacs_to_len16 = htonl(FW_CMD_LEN16(1));
3448 p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
3449 FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3450 FW_VI_MAC_CMD_IDX(idx));
3451 memcpy(p->macaddr, addr, sizeof(p->macaddr));
3453 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3455 ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
3456 if (ret >= max_mac_addr)
3463 * t4_set_addr_hash - program the MAC inexact-match hash filter
3464 * @adap: the adapter
3465 * @mbox: mailbox to use for the FW command
3467 * @ucast: whether the hash filter should also match unicast addresses
3468 * @vec: the value to be written to the hash filter
3469 * @sleep_ok: call is allowed to sleep
3471 * Sets the 64-bit inexact-match hash filter for a virtual interface.
3473 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
3474 bool ucast, u64 vec, bool sleep_ok)
3476 struct fw_vi_mac_cmd c;
3478 memset(&c, 0, sizeof(c));
3479 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
3480 FW_CMD_WRITE | FW_VI_ENABLE_CMD_VIID(viid));
3481 c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN |
3482 FW_VI_MAC_CMD_HASHUNIEN(ucast) |
3484 c.u.hash.hashvec = cpu_to_be64(vec);
3485 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3489 * t4_enable_vi - enable/disable a virtual interface
3490 * @adap: the adapter
3491 * @mbox: mailbox to use for the FW command
3493 * @rx_en: 1=enable Rx, 0=disable Rx
3494 * @tx_en: 1=enable Tx, 0=disable Tx
3496 * Enables/disables a virtual interface.
3498 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3499 bool rx_en, bool tx_en)
3501 struct fw_vi_enable_cmd c;
3503 memset(&c, 0, sizeof(c));
3504 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
3505 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
3506 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN(rx_en) |
3507 FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c));
3508 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3512 * t4_identify_port - identify a VI's port by blinking its LED
3513 * @adap: the adapter
3514 * @mbox: mailbox to use for the FW command
3516 * @nblinks: how many times to blink LED at 2.5 Hz
3518 * Identifies a VI's port by blinking its LED.
3520 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
3521 unsigned int nblinks)
3523 struct fw_vi_enable_cmd c;
3525 memset(&c, 0, sizeof(c));
3526 c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
3527 FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
3528 c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
3529 c.blinkdur = htons(nblinks);
3530 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3534 * t4_iq_free - free an ingress queue and its FLs
3535 * @adap: the adapter
3536 * @mbox: mailbox to use for the FW command
3537 * @pf: the PF owning the queues
3538 * @vf: the VF owning the queues
3539 * @iqtype: the ingress queue type
3540 * @iqid: ingress queue id
3541 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3542 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3544 * Frees an ingress queue and its associated FLs, if any.
3546 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3547 unsigned int vf, unsigned int iqtype, unsigned int iqid,
3548 unsigned int fl0id, unsigned int fl1id)
3552 memset(&c, 0, sizeof(c));
3553 c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST |
3554 FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) |
3556 c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE | FW_LEN16(c));
3557 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iqtype));
3558 c.iqid = htons(iqid);
3559 c.fl0id = htons(fl0id);
3560 c.fl1id = htons(fl1id);
3561 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3565 * t4_eth_eq_free - free an Ethernet egress queue
3566 * @adap: the adapter
3567 * @mbox: mailbox to use for the FW command
3568 * @pf: the PF owning the queue
3569 * @vf: the VF owning the queue
3570 * @eqid: egress queue id
3572 * Frees an Ethernet egress queue.
3574 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3575 unsigned int vf, unsigned int eqid)
3577 struct fw_eq_eth_cmd c;
3579 memset(&c, 0, sizeof(c));
3580 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST |
3581 FW_CMD_EXEC | FW_EQ_ETH_CMD_PFN(pf) |
3582 FW_EQ_ETH_CMD_VFN(vf));
3583 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
3584 c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID(eqid));
3585 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3589 * t4_ctrl_eq_free - free a control egress queue
3590 * @adap: the adapter
3591 * @mbox: mailbox to use for the FW command
3592 * @pf: the PF owning the queue
3593 * @vf: the VF owning the queue
3594 * @eqid: egress queue id
3596 * Frees a control egress queue.
3598 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3599 unsigned int vf, unsigned int eqid)
3601 struct fw_eq_ctrl_cmd c;
3603 memset(&c, 0, sizeof(c));
3604 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST |
3605 FW_CMD_EXEC | FW_EQ_CTRL_CMD_PFN(pf) |
3606 FW_EQ_CTRL_CMD_VFN(vf));
3607 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
3608 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID(eqid));
3609 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3613 * t4_ofld_eq_free - free an offload egress queue
3614 * @adap: the adapter
3615 * @mbox: mailbox to use for the FW command
3616 * @pf: the PF owning the queue
3617 * @vf: the VF owning the queue
3618 * @eqid: egress queue id
3620 * Frees a control egress queue.
3622 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
3623 unsigned int vf, unsigned int eqid)
3625 struct fw_eq_ofld_cmd c;
3627 memset(&c, 0, sizeof(c));
3628 c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST |
3629 FW_CMD_EXEC | FW_EQ_OFLD_CMD_PFN(pf) |
3630 FW_EQ_OFLD_CMD_VFN(vf));
3631 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
3632 c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eqid));
3633 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3637 * t4_handle_fw_rpl - process a FW reply message
3638 * @adap: the adapter
3639 * @rpl: start of the FW message
3641 * Processes a FW message, such as link state change messages.
3643 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
3645 u8 opcode = *(const u8 *)rpl;
3647 if (opcode == FW_PORT_CMD) { /* link/module state change message */
3648 int speed = 0, fc = 0;
3649 const struct fw_port_cmd *p = (void *)rpl;
3650 int chan = FW_PORT_CMD_PORTID_GET(ntohl(p->op_to_portid));
3651 int port = adap->chan_map[chan];
3652 struct port_info *pi = adap2pinfo(adap, port);
3653 struct link_config *lc = &pi->link_cfg;
3654 u32 stat = ntohl(p->u.info.lstatus_to_modtype);
3655 int link_ok = (stat & FW_PORT_CMD_LSTATUS) != 0;
3656 u32 mod = FW_PORT_CMD_MODTYPE_GET(stat);
3658 if (stat & FW_PORT_CMD_RXPAUSE)
3660 if (stat & FW_PORT_CMD_TXPAUSE)
3662 if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
3664 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
3666 else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
3667 speed = SPEED_10000;
3669 if (link_ok != lc->link_ok || speed != lc->speed ||
3670 fc != lc->fc) { /* something changed */
3671 lc->link_ok = link_ok;
3674 t4_os_link_changed(adap, port, link_ok);
3676 if (mod != pi->mod_type) {
3678 t4_os_portmod_changed(adap, port);
3684 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
3688 if (pci_is_pcie(adapter->pdev)) {
3689 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
3690 p->speed = val & PCI_EXP_LNKSTA_CLS;
3691 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
3696 * init_link_config - initialize a link's SW state
3697 * @lc: structure holding the link state
3698 * @caps: link capabilities
3700 * Initializes the SW state maintained for each link, including the link's
3701 * capabilities and default speed/flow-control/autonegotiation settings.
3703 static void init_link_config(struct link_config *lc, unsigned int caps)
3705 lc->supported = caps;
3706 lc->requested_speed = 0;
3708 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
3709 if (lc->supported & FW_PORT_CAP_ANEG) {
3710 lc->advertising = lc->supported & ADVERT_MASK;
3711 lc->autoneg = AUTONEG_ENABLE;
3712 lc->requested_fc |= PAUSE_AUTONEG;
3714 lc->advertising = 0;
3715 lc->autoneg = AUTONEG_DISABLE;
3719 int t4_wait_dev_ready(struct adapter *adap)
3721 if (t4_read_reg(adap, PL_WHOAMI) != 0xffffffff)
3724 return t4_read_reg(adap, PL_WHOAMI) != 0xffffffff ? 0 : -EIO;
3727 static int get_flash_params(struct adapter *adap)
3732 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
3734 ret = sf1_read(adap, 3, 0, 1, &info);
3735 t4_write_reg(adap, SF_OP, 0); /* unlock SF */
3739 if ((info & 0xff) != 0x20) /* not a Numonix flash */
3741 info >>= 16; /* log2 of size */
3742 if (info >= 0x14 && info < 0x18)
3743 adap->params.sf_nsec = 1 << (info - 16);
3744 else if (info == 0x18)
3745 adap->params.sf_nsec = 64;
3748 adap->params.sf_size = 1 << info;
3749 adap->params.sf_fw_start =
3750 t4_read_reg(adap, CIM_BOOT_CFG) & BOOTADDR_MASK;
3755 * t4_prep_adapter - prepare SW and HW for operation
3756 * @adapter: the adapter
3757 * @reset: if true perform a HW reset
3759 * Initialize adapter SW state for the various HW modules, set initial
3760 * values for some adapter tunables, take PHYs out of reset, and
3761 * initialize the MDIO interface.
3763 int t4_prep_adapter(struct adapter *adapter)
3769 ret = t4_wait_dev_ready(adapter);
3773 get_pci_mode(adapter, &adapter->params.pci);
3774 pl_rev = G_REV(t4_read_reg(adapter, PL_REV));
3776 ret = get_flash_params(adapter);
3778 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
3782 /* Retrieve adapter's device ID
3784 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
3785 ver = device_id >> 12;
3786 adapter->params.chip = 0;
3789 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
3792 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
3795 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3800 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3803 * Default port for debugging in case we can't reach FW.
3805 adapter->params.nports = 1;
3806 adapter->params.portvec = 1;
3807 adapter->params.vpd.cclk = 50000;
3811 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
3815 struct fw_port_cmd c;
3816 struct fw_rss_vi_config_cmd rvc;
3818 memset(&c, 0, sizeof(c));
3819 memset(&rvc, 0, sizeof(rvc));
3821 for_each_port(adap, i) {
3822 unsigned int rss_size;
3823 struct port_info *p = adap2pinfo(adap, i);
3825 while ((adap->params.portvec & (1 << j)) == 0)
3828 c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) |
3829 FW_CMD_REQUEST | FW_CMD_READ |
3830 FW_PORT_CMD_PORTID(j));
3831 c.action_to_len16 = htonl(
3832 FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
3834 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3838 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
3845 p->rss_size = rss_size;
3846 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
3848 ret = ntohl(c.u.info.lstatus_to_modtype);
3849 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP) ?
3850 FW_PORT_CMD_MDIOADDR_GET(ret) : -1;
3851 p->port_type = FW_PORT_CMD_PTYPE_GET(ret);
3852 p->mod_type = FW_PORT_MOD_TYPE_NA;
3854 rvc.op_to_viid = htonl(FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
3855 FW_CMD_REQUEST | FW_CMD_READ |
3856 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
3857 rvc.retval_len16 = htonl(FW_LEN16(rvc));
3858 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
3861 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
3863 init_link_config(&p->link_cfg, ntohs(c.u.info.pcap));