2 * Atmel MACB Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 /* MACB register offsets */
14 #define MACB_NCR 0x0000
15 #define MACB_NCFGR 0x0004
16 #define MACB_NSR 0x0008
17 #define MACB_TAR 0x000c /* AT91RM9200 only */
18 #define MACB_TCR 0x0010 /* AT91RM9200 only */
19 #define MACB_TSR 0x0014
20 #define MACB_RBQP 0x0018
21 #define MACB_TBQP 0x001c
22 #define MACB_RSR 0x0020
23 #define MACB_ISR 0x0024
24 #define MACB_IER 0x0028
25 #define MACB_IDR 0x002c
26 #define MACB_IMR 0x0030
27 #define MACB_MAN 0x0034
28 #define MACB_PTR 0x0038
29 #define MACB_PFR 0x003c
30 #define MACB_FTO 0x0040
31 #define MACB_SCF 0x0044
32 #define MACB_MCF 0x0048
33 #define MACB_FRO 0x004c
34 #define MACB_FCSE 0x0050
35 #define MACB_ALE 0x0054
36 #define MACB_DTF 0x0058
37 #define MACB_LCOL 0x005c
38 #define MACB_EXCOL 0x0060
39 #define MACB_TUND 0x0064
40 #define MACB_CSE 0x0068
41 #define MACB_RRE 0x006c
42 #define MACB_ROVR 0x0070
43 #define MACB_RSE 0x0074
44 #define MACB_ELE 0x0078
45 #define MACB_RJA 0x007c
46 #define MACB_USF 0x0080
47 #define MACB_STE 0x0084
48 #define MACB_RLE 0x0088
49 #define MACB_TPF 0x008c
50 #define MACB_HRB 0x0090
51 #define MACB_HRT 0x0094
52 #define MACB_SA1B 0x0098
53 #define MACB_SA1T 0x009c
54 #define MACB_SA2B 0x00a0
55 #define MACB_SA2T 0x00a4
56 #define MACB_SA3B 0x00a8
57 #define MACB_SA3T 0x00ac
58 #define MACB_SA4B 0x00b0
59 #define MACB_SA4T 0x00b4
60 #define MACB_TID 0x00b8
61 #define MACB_TPQ 0x00bc
62 #define MACB_USRIO 0x00c0
63 #define MACB_WOL 0x00c4
64 #define MACB_MID 0x00fc
66 /* GEM register offsets. */
67 #define GEM_NCFGR 0x0004
68 #define GEM_USRIO 0x000c
69 #define GEM_DMACFG 0x0010
70 #define GEM_HRB 0x0080
71 #define GEM_HRT 0x0084
72 #define GEM_SA1B 0x0088
73 #define GEM_SA1T 0x008C
74 #define GEM_OTX 0x0100
75 #define GEM_DCFG1 0x0280
76 #define GEM_DCFG2 0x0284
77 #define GEM_DCFG3 0x0288
78 #define GEM_DCFG4 0x028c
79 #define GEM_DCFG5 0x0290
80 #define GEM_DCFG6 0x0294
81 #define GEM_DCFG7 0x0298
83 /* Bitfields in NCR */
84 #define MACB_LB_OFFSET 0
85 #define MACB_LB_SIZE 1
86 #define MACB_LLB_OFFSET 1
87 #define MACB_LLB_SIZE 1
88 #define MACB_RE_OFFSET 2
89 #define MACB_RE_SIZE 1
90 #define MACB_TE_OFFSET 3
91 #define MACB_TE_SIZE 1
92 #define MACB_MPE_OFFSET 4
93 #define MACB_MPE_SIZE 1
94 #define MACB_CLRSTAT_OFFSET 5
95 #define MACB_CLRSTAT_SIZE 1
96 #define MACB_INCSTAT_OFFSET 6
97 #define MACB_INCSTAT_SIZE 1
98 #define MACB_WESTAT_OFFSET 7
99 #define MACB_WESTAT_SIZE 1
100 #define MACB_BP_OFFSET 8
101 #define MACB_BP_SIZE 1
102 #define MACB_TSTART_OFFSET 9
103 #define MACB_TSTART_SIZE 1
104 #define MACB_THALT_OFFSET 10
105 #define MACB_THALT_SIZE 1
106 #define MACB_NCR_TPF_OFFSET 11
107 #define MACB_NCR_TPF_SIZE 1
108 #define MACB_TZQ_OFFSET 12
109 #define MACB_TZQ_SIZE 1
111 /* Bitfields in NCFGR */
112 #define MACB_SPD_OFFSET 0
113 #define MACB_SPD_SIZE 1
114 #define MACB_FD_OFFSET 1
115 #define MACB_FD_SIZE 1
116 #define MACB_BIT_RATE_OFFSET 2
117 #define MACB_BIT_RATE_SIZE 1
118 #define MACB_JFRAME_OFFSET 3
119 #define MACB_JFRAME_SIZE 1
120 #define MACB_CAF_OFFSET 4
121 #define MACB_CAF_SIZE 1
122 #define MACB_NBC_OFFSET 5
123 #define MACB_NBC_SIZE 1
124 #define MACB_NCFGR_MTI_OFFSET 6
125 #define MACB_NCFGR_MTI_SIZE 1
126 #define MACB_UNI_OFFSET 7
127 #define MACB_UNI_SIZE 1
128 #define MACB_BIG_OFFSET 8
129 #define MACB_BIG_SIZE 1
130 #define MACB_EAE_OFFSET 9
131 #define MACB_EAE_SIZE 1
132 #define MACB_CLK_OFFSET 10
133 #define MACB_CLK_SIZE 2
134 #define MACB_RTY_OFFSET 12
135 #define MACB_RTY_SIZE 1
136 #define MACB_PAE_OFFSET 13
137 #define MACB_PAE_SIZE 1
138 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
139 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
140 #define MACB_RBOF_OFFSET 14
141 #define MACB_RBOF_SIZE 2
142 #define MACB_RLCE_OFFSET 16
143 #define MACB_RLCE_SIZE 1
144 #define MACB_DRFCS_OFFSET 17
145 #define MACB_DRFCS_SIZE 1
146 #define MACB_EFRHD_OFFSET 18
147 #define MACB_EFRHD_SIZE 1
148 #define MACB_IRXFCS_OFFSET 19
149 #define MACB_IRXFCS_SIZE 1
151 /* GEM specific NCFGR bitfields. */
152 #define GEM_CLK_OFFSET 18
153 #define GEM_CLK_SIZE 3
154 #define GEM_DBW_OFFSET 21
155 #define GEM_DBW_SIZE 2
157 /* Constants for data bus width. */
162 /* Bitfields in DMACFG. */
163 #define GEM_RXBS_OFFSET 16
164 #define GEM_RXBS_SIZE 8
166 /* Bitfields in NSR */
167 #define MACB_NSR_LINK_OFFSET 0
168 #define MACB_NSR_LINK_SIZE 1
169 #define MACB_MDIO_OFFSET 1
170 #define MACB_MDIO_SIZE 1
171 #define MACB_IDLE_OFFSET 2
172 #define MACB_IDLE_SIZE 1
174 /* Bitfields in TSR */
175 #define MACB_UBR_OFFSET 0
176 #define MACB_UBR_SIZE 1
177 #define MACB_COL_OFFSET 1
178 #define MACB_COL_SIZE 1
179 #define MACB_TSR_RLE_OFFSET 2
180 #define MACB_TSR_RLE_SIZE 1
181 #define MACB_TGO_OFFSET 3
182 #define MACB_TGO_SIZE 1
183 #define MACB_BEX_OFFSET 4
184 #define MACB_BEX_SIZE 1
185 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
186 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
187 #define MACB_COMP_OFFSET 5
188 #define MACB_COMP_SIZE 1
189 #define MACB_UND_OFFSET 6
190 #define MACB_UND_SIZE 1
192 /* Bitfields in RSR */
193 #define MACB_BNA_OFFSET 0
194 #define MACB_BNA_SIZE 1
195 #define MACB_REC_OFFSET 1
196 #define MACB_REC_SIZE 1
197 #define MACB_OVR_OFFSET 2
198 #define MACB_OVR_SIZE 1
200 /* Bitfields in ISR/IER/IDR/IMR */
201 #define MACB_MFD_OFFSET 0
202 #define MACB_MFD_SIZE 1
203 #define MACB_RCOMP_OFFSET 1
204 #define MACB_RCOMP_SIZE 1
205 #define MACB_RXUBR_OFFSET 2
206 #define MACB_RXUBR_SIZE 1
207 #define MACB_TXUBR_OFFSET 3
208 #define MACB_TXUBR_SIZE 1
209 #define MACB_ISR_TUND_OFFSET 4
210 #define MACB_ISR_TUND_SIZE 1
211 #define MACB_ISR_RLE_OFFSET 5
212 #define MACB_ISR_RLE_SIZE 1
213 #define MACB_TXERR_OFFSET 6
214 #define MACB_TXERR_SIZE 1
215 #define MACB_TCOMP_OFFSET 7
216 #define MACB_TCOMP_SIZE 1
217 #define MACB_ISR_LINK_OFFSET 9
218 #define MACB_ISR_LINK_SIZE 1
219 #define MACB_ISR_ROVR_OFFSET 10
220 #define MACB_ISR_ROVR_SIZE 1
221 #define MACB_HRESP_OFFSET 11
222 #define MACB_HRESP_SIZE 1
223 #define MACB_PFR_OFFSET 12
224 #define MACB_PFR_SIZE 1
225 #define MACB_PTZ_OFFSET 13
226 #define MACB_PTZ_SIZE 1
228 /* Bitfields in MAN */
229 #define MACB_DATA_OFFSET 0
230 #define MACB_DATA_SIZE 16
231 #define MACB_CODE_OFFSET 16
232 #define MACB_CODE_SIZE 2
233 #define MACB_REGA_OFFSET 18
234 #define MACB_REGA_SIZE 5
235 #define MACB_PHYA_OFFSET 23
236 #define MACB_PHYA_SIZE 5
237 #define MACB_RW_OFFSET 28
238 #define MACB_RW_SIZE 2
239 #define MACB_SOF_OFFSET 30
240 #define MACB_SOF_SIZE 2
242 /* Bitfields in USRIO (AVR32) */
243 #define MACB_MII_OFFSET 0
244 #define MACB_MII_SIZE 1
245 #define MACB_EAM_OFFSET 1
246 #define MACB_EAM_SIZE 1
247 #define MACB_TX_PAUSE_OFFSET 2
248 #define MACB_TX_PAUSE_SIZE 1
249 #define MACB_TX_PAUSE_ZERO_OFFSET 3
250 #define MACB_TX_PAUSE_ZERO_SIZE 1
252 /* Bitfields in USRIO (AT91) */
253 #define MACB_RMII_OFFSET 0
254 #define MACB_RMII_SIZE 1
255 #define MACB_CLKEN_OFFSET 1
256 #define MACB_CLKEN_SIZE 1
258 /* Bitfields in WOL */
259 #define MACB_IP_OFFSET 0
260 #define MACB_IP_SIZE 16
261 #define MACB_MAG_OFFSET 16
262 #define MACB_MAG_SIZE 1
263 #define MACB_ARP_OFFSET 17
264 #define MACB_ARP_SIZE 1
265 #define MACB_SA1_OFFSET 18
266 #define MACB_SA1_SIZE 1
267 #define MACB_WOL_MTI_OFFSET 19
268 #define MACB_WOL_MTI_SIZE 1
270 /* Bitfields in MID */
271 #define MACB_IDNUM_OFFSET 16
272 #define MACB_IDNUM_SIZE 16
273 #define MACB_REV_OFFSET 0
274 #define MACB_REV_SIZE 16
276 /* Bitfields in DCFG1. */
277 #define GEM_DBWDEF_OFFSET 25
278 #define GEM_DBWDEF_SIZE 3
280 /* Constants for CLK */
281 #define MACB_CLK_DIV8 0
282 #define MACB_CLK_DIV16 1
283 #define MACB_CLK_DIV32 2
284 #define MACB_CLK_DIV64 3
286 /* GEM specific constants for CLK. */
287 #define GEM_CLK_DIV8 0
288 #define GEM_CLK_DIV16 1
289 #define GEM_CLK_DIV32 2
290 #define GEM_CLK_DIV48 3
291 #define GEM_CLK_DIV64 4
292 #define GEM_CLK_DIV96 5
294 /* Constants for MAN register */
295 #define MACB_MAN_SOF 1
296 #define MACB_MAN_WRITE 1
297 #define MACB_MAN_READ 2
298 #define MACB_MAN_CODE 2
300 /* Bit manipulation macros */
301 #define MACB_BIT(name) \
302 (1 << MACB_##name##_OFFSET)
303 #define MACB_BF(name,value) \
304 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
305 << MACB_##name##_OFFSET)
306 #define MACB_BFEXT(name,value)\
307 (((value) >> MACB_##name##_OFFSET) \
308 & ((1 << MACB_##name##_SIZE) - 1))
309 #define MACB_BFINS(name,value,old) \
310 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
311 << MACB_##name##_OFFSET)) \
312 | MACB_BF(name,value))
314 #define GEM_BIT(name) \
315 (1 << GEM_##name##_OFFSET)
316 #define GEM_BF(name, value) \
317 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
318 << GEM_##name##_OFFSET)
319 #define GEM_BFEXT(name, value)\
320 (((value) >> GEM_##name##_OFFSET) \
321 & ((1 << GEM_##name##_SIZE) - 1))
322 #define GEM_BFINS(name, value, old) \
323 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
324 << GEM_##name##_OFFSET)) \
325 | GEM_BF(name, value))
327 /* Register access macros */
328 #define macb_readl(port,reg) \
329 __raw_readl((port)->regs + MACB_##reg)
330 #define macb_writel(port,reg,value) \
331 __raw_writel((value), (port)->regs + MACB_##reg)
332 #define gem_readl(port, reg) \
333 __raw_readl((port)->regs + GEM_##reg)
334 #define gem_writel(port, reg, value) \
335 __raw_writel((value), (port)->regs + GEM_##reg)
338 * Conditional GEM/MACB macros. These perform the operation to the correct
339 * register dependent on whether the device is a GEM or a MACB. For registers
340 * and bitfields that are common across both devices, use macb_{read,write}l
341 * to avoid the cost of the conditional.
343 #define macb_or_gem_writel(__bp, __reg, __value) \
345 if (macb_is_gem((__bp))) \
346 gem_writel((__bp), __reg, __value); \
348 macb_writel((__bp), __reg, __value); \
351 #define macb_or_gem_readl(__bp, __reg) \
354 if (macb_is_gem((__bp))) \
355 __v = gem_readl((__bp), __reg); \
357 __v = macb_readl((__bp), __reg); \
366 /* DMA descriptor bitfields */
367 #define MACB_RX_USED_OFFSET 0
368 #define MACB_RX_USED_SIZE 1
369 #define MACB_RX_WRAP_OFFSET 1
370 #define MACB_RX_WRAP_SIZE 1
371 #define MACB_RX_WADDR_OFFSET 2
372 #define MACB_RX_WADDR_SIZE 30
374 #define MACB_RX_FRMLEN_OFFSET 0
375 #define MACB_RX_FRMLEN_SIZE 12
376 #define MACB_RX_OFFSET_OFFSET 12
377 #define MACB_RX_OFFSET_SIZE 2
378 #define MACB_RX_SOF_OFFSET 14
379 #define MACB_RX_SOF_SIZE 1
380 #define MACB_RX_EOF_OFFSET 15
381 #define MACB_RX_EOF_SIZE 1
382 #define MACB_RX_CFI_OFFSET 16
383 #define MACB_RX_CFI_SIZE 1
384 #define MACB_RX_VLAN_PRI_OFFSET 17
385 #define MACB_RX_VLAN_PRI_SIZE 3
386 #define MACB_RX_PRI_TAG_OFFSET 20
387 #define MACB_RX_PRI_TAG_SIZE 1
388 #define MACB_RX_VLAN_TAG_OFFSET 21
389 #define MACB_RX_VLAN_TAG_SIZE 1
390 #define MACB_RX_TYPEID_MATCH_OFFSET 22
391 #define MACB_RX_TYPEID_MATCH_SIZE 1
392 #define MACB_RX_SA4_MATCH_OFFSET 23
393 #define MACB_RX_SA4_MATCH_SIZE 1
394 #define MACB_RX_SA3_MATCH_OFFSET 24
395 #define MACB_RX_SA3_MATCH_SIZE 1
396 #define MACB_RX_SA2_MATCH_OFFSET 25
397 #define MACB_RX_SA2_MATCH_SIZE 1
398 #define MACB_RX_SA1_MATCH_OFFSET 26
399 #define MACB_RX_SA1_MATCH_SIZE 1
400 #define MACB_RX_EXT_MATCH_OFFSET 28
401 #define MACB_RX_EXT_MATCH_SIZE 1
402 #define MACB_RX_UHASH_MATCH_OFFSET 29
403 #define MACB_RX_UHASH_MATCH_SIZE 1
404 #define MACB_RX_MHASH_MATCH_OFFSET 30
405 #define MACB_RX_MHASH_MATCH_SIZE 1
406 #define MACB_RX_BROADCAST_OFFSET 31
407 #define MACB_RX_BROADCAST_SIZE 1
409 #define MACB_TX_FRMLEN_OFFSET 0
410 #define MACB_TX_FRMLEN_SIZE 11
411 #define MACB_TX_LAST_OFFSET 15
412 #define MACB_TX_LAST_SIZE 1
413 #define MACB_TX_NOCRC_OFFSET 16
414 #define MACB_TX_NOCRC_SIZE 1
415 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
416 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
417 #define MACB_TX_UNDERRUN_OFFSET 28
418 #define MACB_TX_UNDERRUN_SIZE 1
419 #define MACB_TX_ERROR_OFFSET 29
420 #define MACB_TX_ERROR_SIZE 1
421 #define MACB_TX_WRAP_OFFSET 30
422 #define MACB_TX_WRAP_SIZE 1
423 #define MACB_TX_USED_OFFSET 31
424 #define MACB_TX_USED_SIZE 1
432 * Hardware-collected statistics. Used when updating the network
433 * device stats by a periodic timer.
439 u32 tx_multiple_cols;
445 u32 tx_excessive_cols;
447 u32 tx_carrier_errors;
448 u32 rx_resource_errors;
450 u32 rx_symbol_errors;
451 u32 rx_oversize_pkts;
453 u32 rx_undersize_pkts;
455 u32 rx_length_mismatch;
463 u32 tx_broadcast_frames;
464 u32 tx_multicast_frames;
466 u32 tx_64_byte_frames;
467 u32 tx_65_127_byte_frames;
468 u32 tx_128_255_byte_frames;
469 u32 tx_256_511_byte_frames;
470 u32 tx_512_1023_byte_frames;
471 u32 tx_1024_1518_byte_frames;
472 u32 tx_greater_than_1518_byte_frames;
474 u32 tx_single_collision_frames;
475 u32 tx_multiple_collision_frames;
476 u32 tx_excessive_collisions;
477 u32 tx_late_collisions;
478 u32 tx_deferred_frames;
479 u32 tx_carrier_sense_errors;
483 u32 rx_broadcast_frames;
484 u32 rx_multicast_frames;
486 u32 rx_64_byte_frames;
487 u32 rx_65_127_byte_frames;
488 u32 rx_128_255_byte_frames;
489 u32 rx_256_511_byte_frames;
490 u32 rx_512_1023_byte_frames;
491 u32 rx_1024_1518_byte_frames;
492 u32 rx_greater_than_1518_byte_frames;
493 u32 rx_undersized_frames;
494 u32 rx_oversize_frames;
496 u32 rx_frame_check_sequence_errors;
497 u32 rx_length_field_frame_errors;
498 u32 rx_symbol_errors;
499 u32 rx_alignment_errors;
500 u32 rx_resource_errors;
502 u32 rx_ip_header_checksum_errors;
503 u32 rx_tcp_checksum_errors;
504 u32 rx_udp_checksum_errors;
512 #define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */
513 #define MAX_RX_DESCR 9 /* max number of receive buffers */
515 struct recv_desc_bufs {
516 struct rbf_t descriptors[MAX_RX_DESCR]; /* must be on sizeof (rbf_t) boundary */
517 char recv_buf[MAX_RX_DESCR][MAX_RBUFF_SZ]; /* must be on long boundary */
523 unsigned int rx_tail;
524 struct dma_desc *rx_ring;
527 unsigned int tx_head, tx_tail;
528 struct dma_desc *tx_ring;
529 struct ring_info *tx_skb;
532 struct platform_device *pdev;
535 struct net_device *dev;
536 struct napi_struct napi;
537 struct net_device_stats stats;
539 struct macb_stats macb;
540 struct gem_stats gem;
543 dma_addr_t rx_ring_dma;
544 dma_addr_t tx_ring_dma;
545 dma_addr_t rx_buffers_dma;
547 unsigned int rx_pending, tx_pending;
549 struct mii_bus *mii_bus;
550 struct phy_device *phy_dev;
555 phy_interface_t phy_interface;
558 struct mii_if_info mii; /* ethtool support */
559 struct macb_platform_data board_data; /* board-specific
560 * configuration (shared with
561 * macb for common data */
562 struct clk *ether_clk; /* clock */
565 unsigned long phy_type; /* type of PHY (PHY_ID) */
566 short phy_media; /* media interface type */
567 unsigned short phy_address; /* 5-bit MDI address of PHY (0..31) */
568 struct timer_list check_timer; /* Poll link status */
571 struct sk_buff *skb; /* holds skb until xmit interrupt completes */
572 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
573 int skb_length; /* saved skb length for pci_unmap_single */
576 int rxBuffIndex; /* index into receive descriptor list */
577 struct recv_desc_bufs *dlist; /* descriptor list address */
578 struct recv_desc_bufs *dlist_phys; /* descriptor list physical address */
581 static inline bool macb_is_gem(struct macb *bp)
583 return MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2;