2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/platform_data/macb.h>
24 #include <linux/platform_device.h>
25 #include <linux/phy.h>
27 #include <linux/of_device.h>
28 #include <linux/of_net.h>
32 #define RX_BUFFER_SIZE 128
33 #define RX_RING_SIZE 512
34 #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
36 /* Make the IP header word-aligned (the ethernet header is 14 bytes) */
39 #define TX_RING_SIZE 128
40 #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
41 #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
43 #define TX_RING_GAP(bp) \
44 (TX_RING_SIZE - (bp)->tx_pending)
45 #define TX_BUFFS_AVAIL(bp) \
46 (((bp)->tx_tail <= (bp)->tx_head) ? \
47 (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
48 (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
49 #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
51 #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
53 /* minimum number of free TX descriptors before waking up TX process */
54 #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
56 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
59 static void __macb_set_hwaddr(struct macb *bp)
64 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
65 macb_or_gem_writel(bp, SA1B, bottom);
66 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
67 macb_or_gem_writel(bp, SA1T, top);
70 static void __init macb_get_hwaddr(struct macb *bp)
76 bottom = macb_or_gem_readl(bp, SA1B);
77 top = macb_or_gem_readl(bp, SA1T);
79 addr[0] = bottom & 0xff;
80 addr[1] = (bottom >> 8) & 0xff;
81 addr[2] = (bottom >> 16) & 0xff;
82 addr[3] = (bottom >> 24) & 0xff;
84 addr[5] = (top >> 8) & 0xff;
86 if (is_valid_ether_addr(addr)) {
87 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
89 netdev_info(bp->dev, "invalid hw address, using random\n");
90 eth_hw_addr_random(bp->dev);
94 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
96 struct macb *bp = bus->priv;
99 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
100 | MACB_BF(RW, MACB_MAN_READ)
101 | MACB_BF(PHYA, mii_id)
102 | MACB_BF(REGA, regnum)
103 | MACB_BF(CODE, MACB_MAN_CODE)));
105 /* wait for end of transfer */
106 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
109 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
114 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
117 struct macb *bp = bus->priv;
119 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
120 | MACB_BF(RW, MACB_MAN_WRITE)
121 | MACB_BF(PHYA, mii_id)
122 | MACB_BF(REGA, regnum)
123 | MACB_BF(CODE, MACB_MAN_CODE)
124 | MACB_BF(DATA, value)));
126 /* wait for end of transfer */
127 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
133 static int macb_mdio_reset(struct mii_bus *bus)
138 static void macb_handle_link_change(struct net_device *dev)
140 struct macb *bp = netdev_priv(dev);
141 struct phy_device *phydev = bp->phy_dev;
144 int status_change = 0;
146 spin_lock_irqsave(&bp->lock, flags);
149 if ((bp->speed != phydev->speed) ||
150 (bp->duplex != phydev->duplex)) {
153 reg = macb_readl(bp, NCFGR);
154 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
156 reg &= ~GEM_BIT(GBE);
160 if (phydev->speed == SPEED_100)
161 reg |= MACB_BIT(SPD);
162 if (phydev->speed == SPEED_1000)
165 macb_or_gem_writel(bp, NCFGR, reg);
167 bp->speed = phydev->speed;
168 bp->duplex = phydev->duplex;
173 if (phydev->link != bp->link) {
178 bp->link = phydev->link;
183 spin_unlock_irqrestore(&bp->lock, flags);
187 netif_carrier_on(dev);
188 netdev_info(dev, "link up (%d/%s)\n",
190 phydev->duplex == DUPLEX_FULL ?
193 netif_carrier_off(dev);
194 netdev_info(dev, "link down\n");
199 /* based on au1000_eth. c*/
200 static int macb_mii_probe(struct net_device *dev)
202 struct macb *bp = netdev_priv(dev);
203 struct phy_device *phydev;
206 phydev = phy_find_first(bp->mii_bus);
208 netdev_err(dev, "no PHY found\n");
212 /* TODO : add pin_irq */
214 /* attach the mac to the phy */
215 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
218 netdev_err(dev, "Could not attach to PHY\n");
222 /* mask with MAC supported features */
224 phydev->supported &= PHY_GBIT_FEATURES;
226 phydev->supported &= PHY_BASIC_FEATURES;
228 phydev->advertising = phydev->supported;
233 bp->phy_dev = phydev;
238 int macb_mii_init(struct macb *bp)
240 struct macb_platform_data *pdata;
243 /* Enable management port */
244 macb_writel(bp, NCR, MACB_BIT(MPE));
246 bp->mii_bus = mdiobus_alloc();
247 if (bp->mii_bus == NULL) {
252 bp->mii_bus->name = "MACB_mii_bus";
253 bp->mii_bus->read = &macb_mdio_read;
254 bp->mii_bus->write = &macb_mdio_write;
255 bp->mii_bus->reset = &macb_mdio_reset;
256 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
257 bp->pdev->name, bp->pdev->id);
258 bp->mii_bus->priv = bp;
259 bp->mii_bus->parent = &bp->dev->dev;
260 pdata = bp->pdev->dev.platform_data;
263 bp->mii_bus->phy_mask = pdata->phy_mask;
265 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
266 if (!bp->mii_bus->irq) {
268 goto err_out_free_mdiobus;
271 for (i = 0; i < PHY_MAX_ADDR; i++)
272 bp->mii_bus->irq[i] = PHY_POLL;
274 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
276 if (mdiobus_register(bp->mii_bus))
277 goto err_out_free_mdio_irq;
279 if (macb_mii_probe(bp->dev) != 0) {
280 goto err_out_unregister_bus;
285 err_out_unregister_bus:
286 mdiobus_unregister(bp->mii_bus);
287 err_out_free_mdio_irq:
288 kfree(bp->mii_bus->irq);
289 err_out_free_mdiobus:
290 mdiobus_free(bp->mii_bus);
294 EXPORT_SYMBOL_GPL(macb_mii_init);
296 static void macb_update_stats(struct macb *bp)
298 u32 __iomem *reg = bp->regs + MACB_PFR;
299 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
300 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
302 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
304 for(; p < end; p++, reg++)
305 *p += __raw_readl(reg);
308 static void macb_tx(struct macb *bp)
314 status = macb_readl(bp, TSR);
315 macb_writel(bp, TSR, status);
317 netdev_vdbg(bp->dev, "macb_tx status = 0x%03lx\n", (unsigned long)status);
319 if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
321 netdev_err(bp->dev, "TX %s, resetting buffers\n",
322 status & MACB_BIT(UND) ?
323 "underrun" : "retry limit exceeded");
325 /* Transfer ongoing, disable transmitter, to avoid confusion */
326 if (status & MACB_BIT(TGO))
327 macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
331 /*Mark all the buffer as used to avoid sending a lost buffer*/
332 for (i = 0; i < TX_RING_SIZE; i++)
333 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
336 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
338 /* free transmit buffer in upper layer*/
339 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
340 struct ring_info *rp = &bp->tx_skb[tail];
341 struct sk_buff *skb = rp->skb;
347 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
350 dev_kfree_skb_irq(skb);
353 bp->tx_head = bp->tx_tail = 0;
355 /* Enable the transmitter again */
356 if (status & MACB_BIT(TGO))
357 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
360 if (!(status & MACB_BIT(COMP)))
362 * This may happen when a buffer becomes complete
363 * between reading the ISR and scanning the
364 * descriptors. Nothing to worry about.
369 for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
370 struct ring_info *rp = &bp->tx_skb[tail];
371 struct sk_buff *skb = rp->skb;
376 /* Make hw descriptor updates visible to CPU */
379 bufstat = bp->tx_ring[tail].ctrl;
381 if (!(bufstat & MACB_BIT(TX_USED)))
384 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
386 dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
388 bp->stats.tx_packets++;
389 bp->stats.tx_bytes += skb->len;
391 dev_kfree_skb_irq(skb);
395 if (netif_queue_stopped(bp->dev) &&
396 TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
397 netif_wake_queue(bp->dev);
400 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
401 unsigned int last_frag)
405 unsigned int offset = 0;
408 len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
410 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
411 first_frag, last_frag, len);
413 skb = netdev_alloc_skb(bp->dev, len + RX_OFFSET);
415 bp->stats.rx_dropped++;
416 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
417 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
418 if (frag == last_frag)
422 /* Make descriptor updates visible to hardware */
428 skb_reserve(skb, RX_OFFSET);
429 skb_checksum_none_assert(skb);
432 for (frag = first_frag; ; frag = NEXT_RX(frag)) {
433 unsigned int frag_len = RX_BUFFER_SIZE;
435 if (offset + frag_len > len) {
436 BUG_ON(frag != last_frag);
437 frag_len = len - offset;
439 skb_copy_to_linear_data_offset(skb, offset,
441 (RX_BUFFER_SIZE * frag)),
443 offset += RX_BUFFER_SIZE;
444 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
446 if (frag == last_frag)
450 /* Make descriptor updates visible to hardware */
453 skb->protocol = eth_type_trans(skb, bp->dev);
455 bp->stats.rx_packets++;
456 bp->stats.rx_bytes += len;
457 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
458 skb->len, skb->csum);
459 netif_receive_skb(skb);
464 /* Mark DMA descriptors from begin up to and not including end as unused */
465 static void discard_partial_frame(struct macb *bp, unsigned int begin,
470 for (frag = begin; frag != end; frag = NEXT_RX(frag))
471 bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
473 /* Make descriptor updates visible to hardware */
477 * When this happens, the hardware stats registers for
478 * whatever caused this is updated, so we don't have to record
483 static int macb_rx(struct macb *bp, int budget)
486 unsigned int tail = bp->rx_tail;
489 for (; budget > 0; tail = NEXT_RX(tail)) {
492 /* Make hw descriptor updates visible to CPU */
495 addr = bp->rx_ring[tail].addr;
496 ctrl = bp->rx_ring[tail].ctrl;
498 if (!(addr & MACB_BIT(RX_USED)))
501 if (ctrl & MACB_BIT(RX_SOF)) {
502 if (first_frag != -1)
503 discard_partial_frame(bp, first_frag, tail);
507 if (ctrl & MACB_BIT(RX_EOF)) {
509 BUG_ON(first_frag == -1);
511 dropped = macb_rx_frame(bp, first_frag, tail);
520 if (first_frag != -1)
521 bp->rx_tail = first_frag;
528 static int macb_poll(struct napi_struct *napi, int budget)
530 struct macb *bp = container_of(napi, struct macb, napi);
534 status = macb_readl(bp, RSR);
535 macb_writel(bp, RSR, status);
539 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
540 (unsigned long)status, budget);
542 work_done = macb_rx(bp, budget);
543 if (work_done < budget) {
547 * We've done what we can to clean the buffers. Make sure we
548 * get notified when new packets arrive.
550 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
553 /* TODO: Handle errors */
558 static irqreturn_t macb_interrupt(int irq, void *dev_id)
560 struct net_device *dev = dev_id;
561 struct macb *bp = netdev_priv(dev);
564 status = macb_readl(bp, ISR);
566 if (unlikely(!status))
569 spin_lock(&bp->lock);
572 /* close possible race with dev_close */
573 if (unlikely(!netif_running(dev))) {
574 macb_writel(bp, IDR, -1);
578 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
580 if (status & MACB_RX_INT_FLAGS) {
582 * There's no point taking any more interrupts
583 * until we have processed the buffers. The
584 * scheduling call may fail if the poll routine
585 * is already scheduled, so disable interrupts
588 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
590 if (napi_schedule_prep(&bp->napi)) {
591 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
592 __napi_schedule(&bp->napi);
596 if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
601 * Link change detection isn't possible with RMII, so we'll
602 * add that if/when we get our hands on a full-blown MII PHY.
605 if (status & MACB_BIT(ISR_ROVR)) {
606 /* We missed at least one packet */
608 bp->hw_stats.gem.rx_overruns++;
610 bp->hw_stats.macb.rx_overruns++;
613 if (status & MACB_BIT(HRESP)) {
615 * TODO: Reset the hardware, and maybe move the
616 * netdev_err to a lower-priority context as well
619 netdev_err(dev, "DMA bus error: HRESP not OK\n");
622 status = macb_readl(bp, ISR);
625 spin_unlock(&bp->lock);
630 #ifdef CONFIG_NET_POLL_CONTROLLER
632 * Polling receive - used by netconsole and other diagnostic tools
633 * to allow network i/o with interrupts disabled.
635 static void macb_poll_controller(struct net_device *dev)
639 local_irq_save(flags);
640 macb_interrupt(dev->irq, dev);
641 local_irq_restore(flags);
645 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
647 struct macb *bp = netdev_priv(dev);
649 unsigned int len, entry;
653 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
655 "start_xmit: len %u head %p data %p tail %p end %p\n",
656 skb->len, skb->head, skb->data,
657 skb_tail_pointer(skb), skb_end_pointer(skb));
658 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
659 skb->data, 16, true);
663 spin_lock_irqsave(&bp->lock, flags);
665 /* This is a hard error, log it. */
666 if (TX_BUFFS_AVAIL(bp) < 1) {
667 netif_stop_queue(dev);
668 spin_unlock_irqrestore(&bp->lock, flags);
669 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
670 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
671 bp->tx_head, bp->tx_tail);
672 return NETDEV_TX_BUSY;
676 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
677 mapping = dma_map_single(&bp->pdev->dev, skb->data,
679 bp->tx_skb[entry].skb = skb;
680 bp->tx_skb[entry].mapping = mapping;
681 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
682 skb->data, (unsigned long)mapping);
684 ctrl = MACB_BF(TX_FRMLEN, len);
685 ctrl |= MACB_BIT(TX_LAST);
686 if (entry == (TX_RING_SIZE - 1))
687 ctrl |= MACB_BIT(TX_WRAP);
689 bp->tx_ring[entry].addr = mapping;
690 bp->tx_ring[entry].ctrl = ctrl;
692 /* Make newly initialized descriptor visible to hardware */
695 entry = NEXT_TX(entry);
698 skb_tx_timestamp(skb);
700 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
702 if (TX_BUFFS_AVAIL(bp) < 1)
703 netif_stop_queue(dev);
705 spin_unlock_irqrestore(&bp->lock, flags);
710 static void macb_free_consistent(struct macb *bp)
717 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
718 bp->rx_ring, bp->rx_ring_dma);
722 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
723 bp->tx_ring, bp->tx_ring_dma);
726 if (bp->rx_buffers) {
727 dma_free_coherent(&bp->pdev->dev,
728 RX_RING_SIZE * RX_BUFFER_SIZE,
729 bp->rx_buffers, bp->rx_buffers_dma);
730 bp->rx_buffers = NULL;
734 static int macb_alloc_consistent(struct macb *bp)
738 size = TX_RING_SIZE * sizeof(struct ring_info);
739 bp->tx_skb = kmalloc(size, GFP_KERNEL);
743 size = RX_RING_BYTES;
744 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
745 &bp->rx_ring_dma, GFP_KERNEL);
749 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
750 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
752 size = TX_RING_BYTES;
753 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
754 &bp->tx_ring_dma, GFP_KERNEL);
758 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
759 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
761 size = RX_RING_SIZE * RX_BUFFER_SIZE;
762 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
763 &bp->rx_buffers_dma, GFP_KERNEL);
767 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
768 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
773 macb_free_consistent(bp);
777 static void macb_init_rings(struct macb *bp)
782 addr = bp->rx_buffers_dma;
783 for (i = 0; i < RX_RING_SIZE; i++) {
784 bp->rx_ring[i].addr = addr;
785 bp->rx_ring[i].ctrl = 0;
786 addr += RX_BUFFER_SIZE;
788 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
790 for (i = 0; i < TX_RING_SIZE; i++) {
791 bp->tx_ring[i].addr = 0;
792 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
794 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
796 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
799 static void macb_reset_hw(struct macb *bp)
802 * Disable RX and TX (XXX: Should we halt the transmission
805 macb_writel(bp, NCR, 0);
807 /* Clear the stats registers (XXX: Update stats first?) */
808 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
810 /* Clear all status flags */
811 macb_writel(bp, TSR, -1);
812 macb_writel(bp, RSR, -1);
814 /* Disable all interrupts */
815 macb_writel(bp, IDR, -1);
819 static u32 gem_mdc_clk_div(struct macb *bp)
822 unsigned long pclk_hz = clk_get_rate(bp->pclk);
824 if (pclk_hz <= 20000000)
825 config = GEM_BF(CLK, GEM_CLK_DIV8);
826 else if (pclk_hz <= 40000000)
827 config = GEM_BF(CLK, GEM_CLK_DIV16);
828 else if (pclk_hz <= 80000000)
829 config = GEM_BF(CLK, GEM_CLK_DIV32);
830 else if (pclk_hz <= 120000000)
831 config = GEM_BF(CLK, GEM_CLK_DIV48);
832 else if (pclk_hz <= 160000000)
833 config = GEM_BF(CLK, GEM_CLK_DIV64);
835 config = GEM_BF(CLK, GEM_CLK_DIV96);
840 static u32 macb_mdc_clk_div(struct macb *bp)
843 unsigned long pclk_hz;
846 return gem_mdc_clk_div(bp);
848 pclk_hz = clk_get_rate(bp->pclk);
849 if (pclk_hz <= 20000000)
850 config = MACB_BF(CLK, MACB_CLK_DIV8);
851 else if (pclk_hz <= 40000000)
852 config = MACB_BF(CLK, MACB_CLK_DIV16);
853 else if (pclk_hz <= 80000000)
854 config = MACB_BF(CLK, MACB_CLK_DIV32);
856 config = MACB_BF(CLK, MACB_CLK_DIV64);
862 * Get the DMA bus width field of the network configuration register that we
863 * should program. We find the width from decoding the design configuration
864 * register to find the maximum supported data bus width.
866 static u32 macb_dbw(struct macb *bp)
868 if (!macb_is_gem(bp))
871 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
873 return GEM_BF(DBW, GEM_DBW128);
875 return GEM_BF(DBW, GEM_DBW64);
878 return GEM_BF(DBW, GEM_DBW32);
883 * Configure the receive DMA engine to use the correct receive buffer size.
884 * This is a configurable parameter for GEM.
886 static void macb_configure_dma(struct macb *bp)
890 if (macb_is_gem(bp)) {
891 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
892 dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64);
893 gem_writel(bp, DMACFG, dmacfg);
897 static void macb_init_hw(struct macb *bp)
902 __macb_set_hwaddr(bp);
904 config = macb_mdc_clk_div(bp);
905 config |= MACB_BIT(PAE); /* PAuse Enable */
906 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
907 config |= MACB_BIT(BIG); /* Receive oversized frames */
908 if (bp->dev->flags & IFF_PROMISC)
909 config |= MACB_BIT(CAF); /* Copy All Frames */
910 if (!(bp->dev->flags & IFF_BROADCAST))
911 config |= MACB_BIT(NBC); /* No BroadCast */
912 config |= macb_dbw(bp);
913 macb_writel(bp, NCFGR, config);
915 macb_configure_dma(bp);
917 /* Initialize TX and RX buffers */
918 macb_writel(bp, RBQP, bp->rx_ring_dma);
919 macb_writel(bp, TBQP, bp->tx_ring_dma);
921 /* Enable TX and RX */
922 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
924 /* Enable interrupts */
925 macb_writel(bp, IER, (MACB_BIT(RCOMP)
937 * The hash address register is 64 bits long and takes up two
938 * locations in the memory map. The least significant bits are stored
939 * in EMAC_HSL and the most significant bits in EMAC_HSH.
941 * The unicast hash enable and the multicast hash enable bits in the
942 * network configuration register enable the reception of hash matched
943 * frames. The destination address is reduced to a 6 bit index into
944 * the 64 bit hash register using the following hash function. The
945 * hash function is an exclusive or of every sixth bit of the
946 * destination address.
948 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
949 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
950 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
951 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
952 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
953 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
955 * da[0] represents the least significant bit of the first byte
956 * received, that is, the multicast/unicast indicator, and da[47]
957 * represents the most significant bit of the last byte received. If
958 * the hash index, hi[n], points to a bit that is set in the hash
959 * register then the frame will be matched according to whether the
960 * frame is multicast or unicast. A multicast match will be signalled
961 * if the multicast hash enable bit is set, da[0] is 1 and the hash
962 * index points to a bit set in the hash register. A unicast match
963 * will be signalled if the unicast hash enable bit is set, da[0] is 0
964 * and the hash index points to a bit set in the hash register. To
965 * receive all multicast frames, the hash register should be set with
966 * all ones and the multicast hash enable bit should be set in the
967 * network configuration register.
970 static inline int hash_bit_value(int bitnr, __u8 *addr)
972 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
978 * Return the hash index value for the specified address.
980 static int hash_get_index(__u8 *addr)
985 for (j = 0; j < 6; j++) {
986 for (i = 0, bitval = 0; i < 8; i++)
987 bitval ^= hash_bit_value(i*6 + j, addr);
989 hash_index |= (bitval << j);
996 * Add multicast addresses to the internal multicast-hash table.
998 static void macb_sethashtable(struct net_device *dev)
1000 struct netdev_hw_addr *ha;
1001 unsigned long mc_filter[2];
1003 struct macb *bp = netdev_priv(dev);
1005 mc_filter[0] = mc_filter[1] = 0;
1007 netdev_for_each_mc_addr(ha, dev) {
1008 bitnr = hash_get_index(ha->addr);
1009 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1012 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1013 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1017 * Enable/Disable promiscuous and multicast modes.
1019 void macb_set_rx_mode(struct net_device *dev)
1022 struct macb *bp = netdev_priv(dev);
1024 cfg = macb_readl(bp, NCFGR);
1026 if (dev->flags & IFF_PROMISC)
1027 /* Enable promiscuous mode */
1028 cfg |= MACB_BIT(CAF);
1029 else if (dev->flags & (~IFF_PROMISC))
1030 /* Disable promiscuous mode */
1031 cfg &= ~MACB_BIT(CAF);
1033 if (dev->flags & IFF_ALLMULTI) {
1034 /* Enable all multicast mode */
1035 macb_or_gem_writel(bp, HRB, -1);
1036 macb_or_gem_writel(bp, HRT, -1);
1037 cfg |= MACB_BIT(NCFGR_MTI);
1038 } else if (!netdev_mc_empty(dev)) {
1039 /* Enable specific multicasts */
1040 macb_sethashtable(dev);
1041 cfg |= MACB_BIT(NCFGR_MTI);
1042 } else if (dev->flags & (~IFF_ALLMULTI)) {
1043 /* Disable all multicast mode */
1044 macb_or_gem_writel(bp, HRB, 0);
1045 macb_or_gem_writel(bp, HRT, 0);
1046 cfg &= ~MACB_BIT(NCFGR_MTI);
1049 macb_writel(bp, NCFGR, cfg);
1051 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1053 static int macb_open(struct net_device *dev)
1055 struct macb *bp = netdev_priv(dev);
1058 netdev_dbg(bp->dev, "open\n");
1060 /* carrier starts down */
1061 netif_carrier_off(dev);
1063 /* if the phy is not yet register, retry later*/
1067 if (!is_valid_ether_addr(dev->dev_addr))
1068 return -EADDRNOTAVAIL;
1070 err = macb_alloc_consistent(bp);
1072 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1077 napi_enable(&bp->napi);
1079 macb_init_rings(bp);
1082 /* schedule a link state check */
1083 phy_start(bp->phy_dev);
1085 netif_start_queue(dev);
1090 static int macb_close(struct net_device *dev)
1092 struct macb *bp = netdev_priv(dev);
1093 unsigned long flags;
1095 netif_stop_queue(dev);
1096 napi_disable(&bp->napi);
1099 phy_stop(bp->phy_dev);
1101 spin_lock_irqsave(&bp->lock, flags);
1103 netif_carrier_off(dev);
1104 spin_unlock_irqrestore(&bp->lock, flags);
1106 macb_free_consistent(bp);
1111 static void gem_update_stats(struct macb *bp)
1113 u32 __iomem *reg = bp->regs + GEM_OTX;
1114 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1115 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1117 for (; p < end; p++, reg++)
1118 *p += __raw_readl(reg);
1121 static struct net_device_stats *gem_get_stats(struct macb *bp)
1123 struct gem_stats *hwstat = &bp->hw_stats.gem;
1124 struct net_device_stats *nstat = &bp->stats;
1126 gem_update_stats(bp);
1128 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1129 hwstat->rx_alignment_errors +
1130 hwstat->rx_resource_errors +
1131 hwstat->rx_overruns +
1132 hwstat->rx_oversize_frames +
1133 hwstat->rx_jabbers +
1134 hwstat->rx_undersized_frames +
1135 hwstat->rx_length_field_frame_errors);
1136 nstat->tx_errors = (hwstat->tx_late_collisions +
1137 hwstat->tx_excessive_collisions +
1138 hwstat->tx_underrun +
1139 hwstat->tx_carrier_sense_errors);
1140 nstat->multicast = hwstat->rx_multicast_frames;
1141 nstat->collisions = (hwstat->tx_single_collision_frames +
1142 hwstat->tx_multiple_collision_frames +
1143 hwstat->tx_excessive_collisions);
1144 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1145 hwstat->rx_jabbers +
1146 hwstat->rx_undersized_frames +
1147 hwstat->rx_length_field_frame_errors);
1148 nstat->rx_over_errors = hwstat->rx_resource_errors;
1149 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1150 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1151 nstat->rx_fifo_errors = hwstat->rx_overruns;
1152 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1153 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1154 nstat->tx_fifo_errors = hwstat->tx_underrun;
1159 static struct net_device_stats *macb_get_stats(struct net_device *dev)
1161 struct macb *bp = netdev_priv(dev);
1162 struct net_device_stats *nstat = &bp->stats;
1163 struct macb_stats *hwstat = &bp->hw_stats.macb;
1165 if (macb_is_gem(bp))
1166 return gem_get_stats(bp);
1168 /* read stats from hardware */
1169 macb_update_stats(bp);
1171 /* Convert HW stats into netdevice stats */
1172 nstat->rx_errors = (hwstat->rx_fcs_errors +
1173 hwstat->rx_align_errors +
1174 hwstat->rx_resource_errors +
1175 hwstat->rx_overruns +
1176 hwstat->rx_oversize_pkts +
1177 hwstat->rx_jabbers +
1178 hwstat->rx_undersize_pkts +
1179 hwstat->sqe_test_errors +
1180 hwstat->rx_length_mismatch);
1181 nstat->tx_errors = (hwstat->tx_late_cols +
1182 hwstat->tx_excessive_cols +
1183 hwstat->tx_underruns +
1184 hwstat->tx_carrier_errors);
1185 nstat->collisions = (hwstat->tx_single_cols +
1186 hwstat->tx_multiple_cols +
1187 hwstat->tx_excessive_cols);
1188 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1189 hwstat->rx_jabbers +
1190 hwstat->rx_undersize_pkts +
1191 hwstat->rx_length_mismatch);
1192 nstat->rx_over_errors = hwstat->rx_resource_errors +
1193 hwstat->rx_overruns;
1194 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1195 nstat->rx_frame_errors = hwstat->rx_align_errors;
1196 nstat->rx_fifo_errors = hwstat->rx_overruns;
1197 /* XXX: What does "missed" mean? */
1198 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1199 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1200 nstat->tx_fifo_errors = hwstat->tx_underruns;
1201 /* Don't know about heartbeat or window errors... */
1206 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1208 struct macb *bp = netdev_priv(dev);
1209 struct phy_device *phydev = bp->phy_dev;
1214 return phy_ethtool_gset(phydev, cmd);
1217 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1219 struct macb *bp = netdev_priv(dev);
1220 struct phy_device *phydev = bp->phy_dev;
1225 return phy_ethtool_sset(phydev, cmd);
1228 const struct ethtool_ops macb_ethtool_ops = {
1229 .get_settings = macb_get_settings,
1230 .set_settings = macb_set_settings,
1231 .get_link = ethtool_op_get_link,
1232 .get_ts_info = ethtool_op_get_ts_info,
1234 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1236 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1238 struct macb *bp = netdev_priv(dev);
1239 struct phy_device *phydev = bp->phy_dev;
1241 if (!netif_running(dev))
1247 return phy_mii_ioctl(phydev, rq, cmd);
1249 EXPORT_SYMBOL_GPL(macb_ioctl);
1251 static const struct net_device_ops macb_netdev_ops = {
1252 .ndo_open = macb_open,
1253 .ndo_stop = macb_close,
1254 .ndo_start_xmit = macb_start_xmit,
1255 .ndo_set_rx_mode = macb_set_rx_mode,
1256 .ndo_get_stats = macb_get_stats,
1257 .ndo_do_ioctl = macb_ioctl,
1258 .ndo_validate_addr = eth_validate_addr,
1259 .ndo_change_mtu = eth_change_mtu,
1260 .ndo_set_mac_address = eth_mac_addr,
1261 #ifdef CONFIG_NET_POLL_CONTROLLER
1262 .ndo_poll_controller = macb_poll_controller,
1266 #if defined(CONFIG_OF)
1267 static const struct of_device_id macb_dt_ids[] = {
1268 { .compatible = "cdns,at32ap7000-macb" },
1269 { .compatible = "cdns,at91sam9260-macb" },
1270 { .compatible = "cdns,macb" },
1271 { .compatible = "cdns,pc302-gem" },
1272 { .compatible = "cdns,gem" },
1276 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1278 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1280 struct device_node *np = pdev->dev.of_node;
1283 return of_get_phy_mode(np);
1288 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1290 struct device_node *np = bp->pdev->dev.of_node;
1292 const char *mac = of_get_mac_address(np);
1294 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1302 static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev)
1306 static int __devinit macb_get_hwaddr_dt(struct macb *bp)
1312 static int __init macb_probe(struct platform_device *pdev)
1314 struct macb_platform_data *pdata;
1315 struct resource *regs;
1316 struct net_device *dev;
1318 struct phy_device *phydev;
1322 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1324 dev_err(&pdev->dev, "no mmio resource defined\n");
1329 dev = alloc_etherdev(sizeof(*bp));
1333 SET_NETDEV_DEV(dev, &pdev->dev);
1335 /* TODO: Actually, we have some interesting features... */
1338 bp = netdev_priv(dev);
1342 spin_lock_init(&bp->lock);
1344 bp->pclk = clk_get(&pdev->dev, "pclk");
1345 if (IS_ERR(bp->pclk)) {
1346 dev_err(&pdev->dev, "failed to get macb_clk\n");
1347 goto err_out_free_dev;
1349 clk_enable(bp->pclk);
1351 bp->hclk = clk_get(&pdev->dev, "hclk");
1352 if (IS_ERR(bp->hclk)) {
1353 dev_err(&pdev->dev, "failed to get hclk\n");
1354 goto err_out_put_pclk;
1356 clk_enable(bp->hclk);
1358 bp->regs = ioremap(regs->start, resource_size(regs));
1360 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1362 goto err_out_disable_clocks;
1365 dev->irq = platform_get_irq(pdev, 0);
1366 err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
1368 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1370 goto err_out_iounmap;
1373 dev->netdev_ops = &macb_netdev_ops;
1374 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1375 dev->ethtool_ops = &macb_ethtool_ops;
1377 dev->base_addr = regs->start;
1379 /* Set MII management clock divider */
1380 config = macb_mdc_clk_div(bp);
1381 config |= macb_dbw(bp);
1382 macb_writel(bp, NCFGR, config);
1384 err = macb_get_hwaddr_dt(bp);
1386 macb_get_hwaddr(bp);
1388 err = macb_get_phy_mode_dt(pdev);
1390 pdata = pdev->dev.platform_data;
1391 if (pdata && pdata->is_rmii)
1392 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1394 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1396 bp->phy_interface = err;
1399 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1400 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1401 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1402 #if defined(CONFIG_ARCH_AT91)
1403 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1406 macb_or_gem_writel(bp, USRIO, 0);
1409 #if defined(CONFIG_ARCH_AT91)
1410 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1412 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1415 bp->tx_pending = DEF_TX_RING_PENDING;
1417 err = register_netdev(dev);
1419 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1420 goto err_out_free_irq;
1423 if (macb_mii_init(bp) != 0) {
1424 goto err_out_unregister_netdev;
1427 platform_set_drvdata(pdev, dev);
1429 netif_carrier_off(dev);
1431 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1432 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1433 dev->irq, dev->dev_addr);
1435 phydev = bp->phy_dev;
1436 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1437 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1441 err_out_unregister_netdev:
1442 unregister_netdev(dev);
1444 free_irq(dev->irq, dev);
1447 err_out_disable_clocks:
1448 clk_disable(bp->hclk);
1450 clk_disable(bp->pclk);
1456 platform_set_drvdata(pdev, NULL);
1460 static int __exit macb_remove(struct platform_device *pdev)
1462 struct net_device *dev;
1465 dev = platform_get_drvdata(pdev);
1468 bp = netdev_priv(dev);
1470 phy_disconnect(bp->phy_dev);
1471 mdiobus_unregister(bp->mii_bus);
1472 kfree(bp->mii_bus->irq);
1473 mdiobus_free(bp->mii_bus);
1474 unregister_netdev(dev);
1475 free_irq(dev->irq, dev);
1477 clk_disable(bp->hclk);
1479 clk_disable(bp->pclk);
1482 platform_set_drvdata(pdev, NULL);
1489 static int macb_suspend(struct platform_device *pdev, pm_message_t state)
1491 struct net_device *netdev = platform_get_drvdata(pdev);
1492 struct macb *bp = netdev_priv(netdev);
1494 netif_carrier_off(netdev);
1495 netif_device_detach(netdev);
1497 clk_disable(bp->hclk);
1498 clk_disable(bp->pclk);
1503 static int macb_resume(struct platform_device *pdev)
1505 struct net_device *netdev = platform_get_drvdata(pdev);
1506 struct macb *bp = netdev_priv(netdev);
1508 clk_enable(bp->pclk);
1509 clk_enable(bp->hclk);
1511 netif_device_attach(netdev);
1516 #define macb_suspend NULL
1517 #define macb_resume NULL
1520 static struct platform_driver macb_driver = {
1521 .remove = __exit_p(macb_remove),
1522 .suspend = macb_suspend,
1523 .resume = macb_resume,
1526 .owner = THIS_MODULE,
1527 .of_match_table = of_match_ptr(macb_dt_ids),
1531 static int __init macb_init(void)
1533 return platform_driver_probe(&macb_driver, macb_probe);
1536 static void __exit macb_exit(void)
1538 platform_driver_unregister(&macb_driver);
1541 module_init(macb_init);
1542 module_exit(macb_exit);
1544 MODULE_LICENSE("GPL");
1545 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
1546 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1547 MODULE_ALIAS("platform:macb");