2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2012 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #if IS_ENABLED(CONFIG_HWMON)
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
52 #include <net/checksum.h>
56 #include <asm/byteorder.h>
57 #include <linux/uaccess.h>
60 #include <asm/idprom.h>
69 /* Functions & macros to verify TG3_FLAGS types */
71 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
73 return test_bit(flag, bits);
76 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
81 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
83 clear_bit(flag, bits);
86 #define tg3_flag(tp, flag) \
87 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
88 #define tg3_flag_set(tp, flag) \
89 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_clear(tp, flag) \
91 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
93 #define DRV_MODULE_NAME "tg3"
95 #define TG3_MIN_NUM 124
96 #define DRV_MODULE_VERSION \
97 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
98 #define DRV_MODULE_RELDATE "March 21, 2012"
100 #define RESET_KIND_SHUTDOWN 0
101 #define RESET_KIND_INIT 1
102 #define RESET_KIND_SUSPEND 2
104 #define TG3_DEF_RX_MODE 0
105 #define TG3_DEF_TX_MODE 0
106 #define TG3_DEF_MSG_ENABLE \
116 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
118 /* length of time before we decide the hardware is borked,
119 * and dev->tx_timeout() should be called to fix the problem
122 #define TG3_TX_TIMEOUT (5 * HZ)
124 /* hardware minimum and maximum for a single frame's data payload */
125 #define TG3_MIN_MTU 60
126 #define TG3_MAX_MTU(tp) \
127 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
129 /* These numbers seem to be hard coded in the NIC firmware somehow.
130 * You can't change the ring sizes, but you can change where you place
131 * them in the NIC onboard memory.
133 #define TG3_RX_STD_RING_SIZE(tp) \
134 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
135 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
136 #define TG3_DEF_RX_RING_PENDING 200
137 #define TG3_RX_JMB_RING_SIZE(tp) \
138 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
139 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
140 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
142 /* Do not place this n-ring entries value into the tp struct itself,
143 * we really want to expose these constants to GCC so that modulo et
144 * al. operations are done with shifts and masks instead of with
145 * hw multiply/modulo instructions. Another solution would be to
146 * replace things like '% foo' with '& (foo - 1)'.
149 #define TG3_TX_RING_SIZE 512
150 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
152 #define TG3_RX_STD_RING_BYTES(tp) \
153 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
154 #define TG3_RX_JMB_RING_BYTES(tp) \
155 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
156 #define TG3_RX_RCB_RING_BYTES(tp) \
157 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
158 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
160 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
162 #define TG3_DMA_BYTE_ENAB 64
164 #define TG3_RX_STD_DMA_SZ 1536
165 #define TG3_RX_JMB_DMA_SZ 9046
167 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
169 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
170 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
172 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
173 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
175 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
176 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
178 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
179 * that are at least dword aligned when used in PCIX mode. The driver
180 * works around this bug by double copying the packet. This workaround
181 * is built into the normal double copy length check for efficiency.
183 * However, the double copy is only necessary on those architectures
184 * where unaligned memory accesses are inefficient. For those architectures
185 * where unaligned memory accesses incur little penalty, we can reintegrate
186 * the 5701 in the normal rx path. Doing so saves a device structure
187 * dereference by hardcoding the double copy threshold in place.
189 #define TG3_RX_COPY_THRESHOLD 256
190 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
191 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
193 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196 #if (NET_IP_ALIGN != 0)
197 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
199 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
202 /* minimum number of free TX descriptors required to wake up TX process */
203 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
204 #define TG3_TX_BD_DMA_MAX_2K 2048
205 #define TG3_TX_BD_DMA_MAX_4K 4096
207 #define TG3_RAW_IP_ALIGN 2
209 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
210 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
212 #define FIRMWARE_TG3 "tigon/tg3.bin"
213 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
214 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
216 static char version[] __devinitdata =
217 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
219 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
220 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
221 MODULE_LICENSE("GPL");
222 MODULE_VERSION(DRV_MODULE_VERSION);
223 MODULE_FIRMWARE(FIRMWARE_TG3);
224 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
225 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
227 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
228 module_param(tg3_debug, int, 0);
229 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
231 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
306 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
307 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
308 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
309 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
310 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
311 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
312 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
313 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
317 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
319 static const struct {
320 const char string[ETH_GSTRING_LEN];
321 } ethtool_stats_keys[] = {
324 { "rx_ucast_packets" },
325 { "rx_mcast_packets" },
326 { "rx_bcast_packets" },
328 { "rx_align_errors" },
329 { "rx_xon_pause_rcvd" },
330 { "rx_xoff_pause_rcvd" },
331 { "rx_mac_ctrl_rcvd" },
332 { "rx_xoff_entered" },
333 { "rx_frame_too_long_errors" },
335 { "rx_undersize_packets" },
336 { "rx_in_length_errors" },
337 { "rx_out_length_errors" },
338 { "rx_64_or_less_octet_packets" },
339 { "rx_65_to_127_octet_packets" },
340 { "rx_128_to_255_octet_packets" },
341 { "rx_256_to_511_octet_packets" },
342 { "rx_512_to_1023_octet_packets" },
343 { "rx_1024_to_1522_octet_packets" },
344 { "rx_1523_to_2047_octet_packets" },
345 { "rx_2048_to_4095_octet_packets" },
346 { "rx_4096_to_8191_octet_packets" },
347 { "rx_8192_to_9022_octet_packets" },
354 { "tx_flow_control" },
356 { "tx_single_collisions" },
357 { "tx_mult_collisions" },
359 { "tx_excessive_collisions" },
360 { "tx_late_collisions" },
361 { "tx_collide_2times" },
362 { "tx_collide_3times" },
363 { "tx_collide_4times" },
364 { "tx_collide_5times" },
365 { "tx_collide_6times" },
366 { "tx_collide_7times" },
367 { "tx_collide_8times" },
368 { "tx_collide_9times" },
369 { "tx_collide_10times" },
370 { "tx_collide_11times" },
371 { "tx_collide_12times" },
372 { "tx_collide_13times" },
373 { "tx_collide_14times" },
374 { "tx_collide_15times" },
375 { "tx_ucast_packets" },
376 { "tx_mcast_packets" },
377 { "tx_bcast_packets" },
378 { "tx_carrier_sense_errors" },
382 { "dma_writeq_full" },
383 { "dma_write_prioq_full" },
387 { "rx_threshold_hit" },
389 { "dma_readq_full" },
390 { "dma_read_prioq_full" },
391 { "tx_comp_queue_full" },
393 { "ring_set_send_prod_index" },
394 { "ring_status_update" },
396 { "nic_avoided_irqs" },
397 { "nic_tx_threshold_hit" },
399 { "mbuf_lwm_thresh_hit" },
402 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
405 static const struct {
406 const char string[ETH_GSTRING_LEN];
407 } ethtool_test_keys[] = {
408 { "nvram test (online) " },
409 { "link test (online) " },
410 { "register test (offline)" },
411 { "memory test (offline)" },
412 { "mac loopback test (offline)" },
413 { "phy loopback test (offline)" },
414 { "ext loopback test (offline)" },
415 { "interrupt test (offline)" },
418 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
421 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
423 writel(val, tp->regs + off);
426 static u32 tg3_read32(struct tg3 *tp, u32 off)
428 return readl(tp->regs + off);
431 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
433 writel(val, tp->aperegs + off);
436 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
438 return readl(tp->aperegs + off);
441 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
445 spin_lock_irqsave(&tp->indirect_lock, flags);
446 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
447 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
448 spin_unlock_irqrestore(&tp->indirect_lock, flags);
451 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
453 writel(val, tp->regs + off);
454 readl(tp->regs + off);
457 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
462 spin_lock_irqsave(&tp->indirect_lock, flags);
463 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
464 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
465 spin_unlock_irqrestore(&tp->indirect_lock, flags);
469 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
473 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
474 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
475 TG3_64BIT_REG_LOW, val);
478 if (off == TG3_RX_STD_PROD_IDX_REG) {
479 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
480 TG3_64BIT_REG_LOW, val);
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
486 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
487 spin_unlock_irqrestore(&tp->indirect_lock, flags);
489 /* In indirect mode when disabling interrupts, we also need
490 * to clear the interrupt bit in the GRC local ctrl register.
492 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
494 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
495 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
499 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
506 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
511 /* usec_wait specifies the wait time in usec when writing to certain registers
512 * where it is unsafe to read back the register without some delay.
513 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
514 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
516 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
518 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
519 /* Non-posted methods */
520 tp->write32(tp, off, val);
523 tg3_write32(tp, off, val);
528 /* Wait again after the read for the posted method to guarantee that
529 * the wait time is met.
535 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
537 tp->write32_mbox(tp, off, val);
538 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
539 tp->read32_mbox(tp, off);
542 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
544 void __iomem *mbox = tp->regs + off;
546 if (tg3_flag(tp, TXD_MBOX_HWBUG))
548 if (tg3_flag(tp, MBOX_WRITE_REORDER))
552 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
554 return readl(tp->regs + off + GRCMBOX_BASE);
557 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
559 writel(val, tp->regs + off + GRCMBOX_BASE);
562 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
563 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
564 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
565 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
566 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
568 #define tw32(reg, val) tp->write32(tp, reg, val)
569 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
570 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
571 #define tr32(reg) tp->read32(tp, reg)
573 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
577 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
578 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
581 spin_lock_irqsave(&tp->indirect_lock, flags);
582 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
583 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
584 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
586 /* Always leave this as zero. */
587 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
589 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
590 tw32_f(TG3PCI_MEM_WIN_DATA, val);
592 /* Always leave this as zero. */
593 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
595 spin_unlock_irqrestore(&tp->indirect_lock, flags);
598 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
603 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
608 spin_lock_irqsave(&tp->indirect_lock, flags);
609 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
610 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
611 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
613 /* Always leave this as zero. */
614 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
616 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
617 *val = tr32(TG3PCI_MEM_WIN_DATA);
619 /* Always leave this as zero. */
620 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
622 spin_unlock_irqrestore(&tp->indirect_lock, flags);
625 static void tg3_ape_lock_init(struct tg3 *tp)
630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
631 regbase = TG3_APE_LOCK_GRANT;
633 regbase = TG3_APE_PER_LOCK_GRANT;
635 /* Make sure the driver hasn't any stale locks. */
636 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
638 case TG3_APE_LOCK_PHY0:
639 case TG3_APE_LOCK_PHY1:
640 case TG3_APE_LOCK_PHY2:
641 case TG3_APE_LOCK_PHY3:
642 bit = APE_LOCK_GRANT_DRIVER;
646 bit = APE_LOCK_GRANT_DRIVER;
648 bit = 1 << tp->pci_fn;
650 tg3_ape_write32(tp, regbase + 4 * i, bit);
655 static int tg3_ape_lock(struct tg3 *tp, int locknum)
659 u32 status, req, gnt, bit;
661 if (!tg3_flag(tp, ENABLE_APE))
665 case TG3_APE_LOCK_GPIO:
666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
668 case TG3_APE_LOCK_GRC:
669 case TG3_APE_LOCK_MEM:
671 bit = APE_LOCK_REQ_DRIVER;
673 bit = 1 << tp->pci_fn;
675 case TG3_APE_LOCK_PHY0:
676 case TG3_APE_LOCK_PHY1:
677 case TG3_APE_LOCK_PHY2:
678 case TG3_APE_LOCK_PHY3:
679 bit = APE_LOCK_REQ_DRIVER;
685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
686 req = TG3_APE_LOCK_REQ;
687 gnt = TG3_APE_LOCK_GRANT;
689 req = TG3_APE_PER_LOCK_REQ;
690 gnt = TG3_APE_PER_LOCK_GRANT;
695 tg3_ape_write32(tp, req + off, bit);
697 /* Wait for up to 1 millisecond to acquire lock. */
698 for (i = 0; i < 100; i++) {
699 status = tg3_ape_read32(tp, gnt + off);
706 /* Revoke the lock request. */
707 tg3_ape_write32(tp, gnt + off, bit);
714 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
718 if (!tg3_flag(tp, ENABLE_APE))
722 case TG3_APE_LOCK_GPIO:
723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
725 case TG3_APE_LOCK_GRC:
726 case TG3_APE_LOCK_MEM:
728 bit = APE_LOCK_GRANT_DRIVER;
730 bit = 1 << tp->pci_fn;
732 case TG3_APE_LOCK_PHY0:
733 case TG3_APE_LOCK_PHY1:
734 case TG3_APE_LOCK_PHY2:
735 case TG3_APE_LOCK_PHY3:
736 bit = APE_LOCK_GRANT_DRIVER;
742 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
743 gnt = TG3_APE_LOCK_GRANT;
745 gnt = TG3_APE_PER_LOCK_GRANT;
747 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
750 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
755 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
758 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
759 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
762 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
765 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
768 return timeout_us ? 0 : -EBUSY;
771 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
775 for (i = 0; i < timeout_us / 10; i++) {
776 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
778 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
784 return i == timeout_us / 10;
787 int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, u32 len)
790 u32 i, bufoff, msgoff, maxlen, apedata;
792 if (!tg3_flag(tp, APE_HAS_NCSI))
795 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
796 if (apedata != APE_SEG_SIG_MAGIC)
799 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
800 if (!(apedata & APE_FW_STATUS_READY))
803 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
805 msgoff = bufoff + 2 * sizeof(u32);
806 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
811 /* Cap xfer sizes to scratchpad limits. */
812 length = (len > maxlen) ? maxlen : len;
815 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
816 if (!(apedata & APE_FW_STATUS_READY))
819 /* Wait for up to 1 msec for APE to service previous event. */
820 err = tg3_ape_event_lock(tp, 1000);
824 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
825 APE_EVENT_STATUS_SCRTCHPD_READ |
826 APE_EVENT_STATUS_EVENT_PENDING;
827 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
829 tg3_ape_write32(tp, bufoff, base_off);
830 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
832 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
833 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
837 if (tg3_ape_wait_for_event(tp, 30000))
840 for (i = 0; length; i += 4, length -= 4) {
841 u32 val = tg3_ape_read32(tp, msgoff + i);
842 memcpy(data, &val, sizeof(u32));
850 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
855 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
856 if (apedata != APE_SEG_SIG_MAGIC)
859 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
860 if (!(apedata & APE_FW_STATUS_READY))
863 /* Wait for up to 1 millisecond for APE to service previous event. */
864 err = tg3_ape_event_lock(tp, 1000);
868 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
869 event | APE_EVENT_STATUS_EVENT_PENDING);
871 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
872 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
877 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
882 if (!tg3_flag(tp, ENABLE_APE))
886 case RESET_KIND_INIT:
887 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
888 APE_HOST_SEG_SIG_MAGIC);
889 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
890 APE_HOST_SEG_LEN_MAGIC);
891 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
892 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
893 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
894 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
895 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
896 APE_HOST_BEHAV_NO_PHYLOCK);
897 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
898 TG3_APE_HOST_DRVR_STATE_START);
900 event = APE_EVENT_STATUS_STATE_START;
902 case RESET_KIND_SHUTDOWN:
903 /* With the interface we are currently using,
904 * APE does not track driver state. Wiping
905 * out the HOST SEGMENT SIGNATURE forces
906 * the APE to assume OS absent status.
908 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
910 if (device_may_wakeup(&tp->pdev->dev) &&
911 tg3_flag(tp, WOL_ENABLE)) {
912 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
913 TG3_APE_HOST_WOL_SPEED_AUTO);
914 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
916 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
918 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
920 event = APE_EVENT_STATUS_STATE_UNLOAD;
922 case RESET_KIND_SUSPEND:
923 event = APE_EVENT_STATUS_STATE_SUSPEND;
929 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
931 tg3_ape_send_event(tp, event);
934 static void tg3_disable_ints(struct tg3 *tp)
938 tw32(TG3PCI_MISC_HOST_CTRL,
939 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
940 for (i = 0; i < tp->irq_max; i++)
941 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
944 static void tg3_enable_ints(struct tg3 *tp)
951 tw32(TG3PCI_MISC_HOST_CTRL,
952 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
954 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
955 for (i = 0; i < tp->irq_cnt; i++) {
956 struct tg3_napi *tnapi = &tp->napi[i];
958 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
959 if (tg3_flag(tp, 1SHOT_MSI))
960 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
962 tp->coal_now |= tnapi->coal_now;
965 /* Force an initial interrupt */
966 if (!tg3_flag(tp, TAGGED_STATUS) &&
967 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
968 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
970 tw32(HOSTCC_MODE, tp->coal_now);
972 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
975 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
977 struct tg3 *tp = tnapi->tp;
978 struct tg3_hw_status *sblk = tnapi->hw_status;
979 unsigned int work_exists = 0;
981 /* check for phy events */
982 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
983 if (sblk->status & SD_STATUS_LINK_CHG)
987 /* check for TX work to do */
988 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
991 /* check for RX work to do */
992 if (tnapi->rx_rcb_prod_idx &&
993 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1000 * similar to tg3_enable_ints, but it accurately determines whether there
1001 * is new work pending and can return without flushing the PIO write
1002 * which reenables interrupts
1004 static void tg3_int_reenable(struct tg3_napi *tnapi)
1006 struct tg3 *tp = tnapi->tp;
1008 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1011 /* When doing tagged status, this work check is unnecessary.
1012 * The last_tag we write above tells the chip which piece of
1013 * work we've completed.
1015 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1016 tw32(HOSTCC_MODE, tp->coalesce_mode |
1017 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1020 static void tg3_switch_clocks(struct tg3 *tp)
1023 u32 orig_clock_ctrl;
1025 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1028 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1030 orig_clock_ctrl = clock_ctrl;
1031 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1032 CLOCK_CTRL_CLKRUN_OENABLE |
1034 tp->pci_clock_ctrl = clock_ctrl;
1036 if (tg3_flag(tp, 5705_PLUS)) {
1037 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1038 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1039 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1041 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1042 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1044 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1046 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1047 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1050 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1053 #define PHY_BUSY_LOOPS 5000
1055 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1061 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1063 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1067 tg3_ape_lock(tp, tp->phy_ape_lock);
1071 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1072 MI_COM_PHY_ADDR_MASK);
1073 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1074 MI_COM_REG_ADDR_MASK);
1075 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1077 tw32_f(MAC_MI_COM, frame_val);
1079 loops = PHY_BUSY_LOOPS;
1080 while (loops != 0) {
1082 frame_val = tr32(MAC_MI_COM);
1084 if ((frame_val & MI_COM_BUSY) == 0) {
1086 frame_val = tr32(MAC_MI_COM);
1094 *val = frame_val & MI_COM_DATA_MASK;
1098 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1099 tw32_f(MAC_MI_MODE, tp->mi_mode);
1103 tg3_ape_unlock(tp, tp->phy_ape_lock);
1108 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1114 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1115 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1118 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1120 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1124 tg3_ape_lock(tp, tp->phy_ape_lock);
1126 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (val & MI_COM_DATA_MASK);
1131 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1133 tw32_f(MAC_MI_COM, frame_val);
1135 loops = PHY_BUSY_LOOPS;
1136 while (loops != 0) {
1138 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1141 frame_val = tr32(MAC_MI_COM);
1151 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1152 tw32_f(MAC_MI_MODE, tp->mi_mode);
1156 tg3_ape_unlock(tp, tp->phy_ape_lock);
1161 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1165 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1169 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1173 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1174 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1178 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1184 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1188 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1192 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1196 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1197 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1201 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1207 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1211 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1213 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1218 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1222 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1224 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1229 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1233 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1234 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1235 MII_TG3_AUXCTL_SHDWSEL_MISC);
1237 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1242 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1244 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1245 set |= MII_TG3_AUXCTL_MISC_WREN;
1247 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1250 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1251 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1252 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1253 MII_TG3_AUXCTL_ACTL_TX_6DB)
1255 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1256 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1257 MII_TG3_AUXCTL_ACTL_TX_6DB);
1259 static int tg3_bmcr_reset(struct tg3 *tp)
1264 /* OK, reset it, and poll the BMCR_RESET bit until it
1265 * clears or we time out.
1267 phy_control = BMCR_RESET;
1268 err = tg3_writephy(tp, MII_BMCR, phy_control);
1274 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1278 if ((phy_control & BMCR_RESET) == 0) {
1290 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1292 struct tg3 *tp = bp->priv;
1295 spin_lock_bh(&tp->lock);
1297 if (tg3_readphy(tp, reg, &val))
1300 spin_unlock_bh(&tp->lock);
1305 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1307 struct tg3 *tp = bp->priv;
1310 spin_lock_bh(&tp->lock);
1312 if (tg3_writephy(tp, reg, val))
1315 spin_unlock_bh(&tp->lock);
1320 static int tg3_mdio_reset(struct mii_bus *bp)
1325 static void tg3_mdio_config_5785(struct tg3 *tp)
1328 struct phy_device *phydev;
1330 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1331 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1332 case PHY_ID_BCM50610:
1333 case PHY_ID_BCM50610M:
1334 val = MAC_PHYCFG2_50610_LED_MODES;
1336 case PHY_ID_BCMAC131:
1337 val = MAC_PHYCFG2_AC131_LED_MODES;
1339 case PHY_ID_RTL8211C:
1340 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1342 case PHY_ID_RTL8201E:
1343 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1349 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1350 tw32(MAC_PHYCFG2, val);
1352 val = tr32(MAC_PHYCFG1);
1353 val &= ~(MAC_PHYCFG1_RGMII_INT |
1354 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1355 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1356 tw32(MAC_PHYCFG1, val);
1361 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1362 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1363 MAC_PHYCFG2_FMODE_MASK_MASK |
1364 MAC_PHYCFG2_GMODE_MASK_MASK |
1365 MAC_PHYCFG2_ACT_MASK_MASK |
1366 MAC_PHYCFG2_QUAL_MASK_MASK |
1367 MAC_PHYCFG2_INBAND_ENABLE;
1369 tw32(MAC_PHYCFG2, val);
1371 val = tr32(MAC_PHYCFG1);
1372 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1373 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1374 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1375 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1376 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1377 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1378 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1380 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1381 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1382 tw32(MAC_PHYCFG1, val);
1384 val = tr32(MAC_EXT_RGMII_MODE);
1385 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1386 MAC_RGMII_MODE_RX_QUALITY |
1387 MAC_RGMII_MODE_RX_ACTIVITY |
1388 MAC_RGMII_MODE_RX_ENG_DET |
1389 MAC_RGMII_MODE_TX_ENABLE |
1390 MAC_RGMII_MODE_TX_LOWPWR |
1391 MAC_RGMII_MODE_TX_RESET);
1392 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1393 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1394 val |= MAC_RGMII_MODE_RX_INT_B |
1395 MAC_RGMII_MODE_RX_QUALITY |
1396 MAC_RGMII_MODE_RX_ACTIVITY |
1397 MAC_RGMII_MODE_RX_ENG_DET;
1398 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1399 val |= MAC_RGMII_MODE_TX_ENABLE |
1400 MAC_RGMII_MODE_TX_LOWPWR |
1401 MAC_RGMII_MODE_TX_RESET;
1403 tw32(MAC_EXT_RGMII_MODE, val);
1406 static void tg3_mdio_start(struct tg3 *tp)
1408 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1409 tw32_f(MAC_MI_MODE, tp->mi_mode);
1412 if (tg3_flag(tp, MDIOBUS_INITED) &&
1413 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1414 tg3_mdio_config_5785(tp);
1417 static int tg3_mdio_init(struct tg3 *tp)
1421 struct phy_device *phydev;
1423 if (tg3_flag(tp, 5717_PLUS)) {
1426 tp->phy_addr = tp->pci_fn + 1;
1428 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1429 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1431 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1432 TG3_CPMU_PHY_STRAP_IS_SERDES;
1436 tp->phy_addr = TG3_PHY_MII_ADDR;
1440 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1443 tp->mdio_bus = mdiobus_alloc();
1444 if (tp->mdio_bus == NULL)
1447 tp->mdio_bus->name = "tg3 mdio bus";
1448 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1449 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1450 tp->mdio_bus->priv = tp;
1451 tp->mdio_bus->parent = &tp->pdev->dev;
1452 tp->mdio_bus->read = &tg3_mdio_read;
1453 tp->mdio_bus->write = &tg3_mdio_write;
1454 tp->mdio_bus->reset = &tg3_mdio_reset;
1455 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1456 tp->mdio_bus->irq = &tp->mdio_irq[0];
1458 for (i = 0; i < PHY_MAX_ADDR; i++)
1459 tp->mdio_bus->irq[i] = PHY_POLL;
1461 /* The bus registration will look for all the PHYs on the mdio bus.
1462 * Unfortunately, it does not ensure the PHY is powered up before
1463 * accessing the PHY ID registers. A chip reset is the
1464 * quickest way to bring the device back to an operational state..
1466 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1469 i = mdiobus_register(tp->mdio_bus);
1471 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1472 mdiobus_free(tp->mdio_bus);
1476 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1478 if (!phydev || !phydev->drv) {
1479 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1480 mdiobus_unregister(tp->mdio_bus);
1481 mdiobus_free(tp->mdio_bus);
1485 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1486 case PHY_ID_BCM57780:
1487 phydev->interface = PHY_INTERFACE_MODE_GMII;
1488 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1490 case PHY_ID_BCM50610:
1491 case PHY_ID_BCM50610M:
1492 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1493 PHY_BRCM_RX_REFCLK_UNUSED |
1494 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1495 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1496 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1497 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1498 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1499 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1500 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1501 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1503 case PHY_ID_RTL8211C:
1504 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1506 case PHY_ID_RTL8201E:
1507 case PHY_ID_BCMAC131:
1508 phydev->interface = PHY_INTERFACE_MODE_MII;
1509 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1510 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1514 tg3_flag_set(tp, MDIOBUS_INITED);
1516 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1517 tg3_mdio_config_5785(tp);
1522 static void tg3_mdio_fini(struct tg3 *tp)
1524 if (tg3_flag(tp, MDIOBUS_INITED)) {
1525 tg3_flag_clear(tp, MDIOBUS_INITED);
1526 mdiobus_unregister(tp->mdio_bus);
1527 mdiobus_free(tp->mdio_bus);
1531 /* tp->lock is held. */
1532 static inline void tg3_generate_fw_event(struct tg3 *tp)
1536 val = tr32(GRC_RX_CPU_EVENT);
1537 val |= GRC_RX_CPU_DRIVER_EVENT;
1538 tw32_f(GRC_RX_CPU_EVENT, val);
1540 tp->last_event_jiffies = jiffies;
1543 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1545 /* tp->lock is held. */
1546 static void tg3_wait_for_event_ack(struct tg3 *tp)
1549 unsigned int delay_cnt;
1552 /* If enough time has passed, no wait is necessary. */
1553 time_remain = (long)(tp->last_event_jiffies + 1 +
1554 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1556 if (time_remain < 0)
1559 /* Check if we can shorten the wait time. */
1560 delay_cnt = jiffies_to_usecs(time_remain);
1561 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1562 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1563 delay_cnt = (delay_cnt >> 3) + 1;
1565 for (i = 0; i < delay_cnt; i++) {
1566 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1572 /* tp->lock is held. */
1573 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1578 if (!tg3_readphy(tp, MII_BMCR, ®))
1580 if (!tg3_readphy(tp, MII_BMSR, ®))
1581 val |= (reg & 0xffff);
1585 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1587 if (!tg3_readphy(tp, MII_LPA, ®))
1588 val |= (reg & 0xffff);
1592 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1593 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1595 if (!tg3_readphy(tp, MII_STAT1000, ®))
1596 val |= (reg & 0xffff);
1600 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1607 /* tp->lock is held. */
1608 static void tg3_ump_link_report(struct tg3 *tp)
1612 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1615 tg3_phy_gather_ump_data(tp, data);
1617 tg3_wait_for_event_ack(tp);
1619 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1620 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1621 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1622 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1623 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1624 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1626 tg3_generate_fw_event(tp);
1629 /* tp->lock is held. */
1630 static void tg3_stop_fw(struct tg3 *tp)
1632 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1633 /* Wait for RX cpu to ACK the previous event. */
1634 tg3_wait_for_event_ack(tp);
1636 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1638 tg3_generate_fw_event(tp);
1640 /* Wait for RX cpu to ACK this event. */
1641 tg3_wait_for_event_ack(tp);
1645 /* tp->lock is held. */
1646 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1648 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1649 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1651 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1653 case RESET_KIND_INIT:
1654 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1658 case RESET_KIND_SHUTDOWN:
1659 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1663 case RESET_KIND_SUSPEND:
1664 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1673 if (kind == RESET_KIND_INIT ||
1674 kind == RESET_KIND_SUSPEND)
1675 tg3_ape_driver_state_change(tp, kind);
1678 /* tp->lock is held. */
1679 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1681 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1683 case RESET_KIND_INIT:
1684 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1685 DRV_STATE_START_DONE);
1688 case RESET_KIND_SHUTDOWN:
1689 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1690 DRV_STATE_UNLOAD_DONE);
1698 if (kind == RESET_KIND_SHUTDOWN)
1699 tg3_ape_driver_state_change(tp, kind);
1702 /* tp->lock is held. */
1703 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1705 if (tg3_flag(tp, ENABLE_ASF)) {
1707 case RESET_KIND_INIT:
1708 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1712 case RESET_KIND_SHUTDOWN:
1713 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1717 case RESET_KIND_SUSPEND:
1718 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1728 static int tg3_poll_fw(struct tg3 *tp)
1733 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1734 /* Wait up to 20ms for init done. */
1735 for (i = 0; i < 200; i++) {
1736 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1743 /* Wait for firmware initialization to complete. */
1744 for (i = 0; i < 100000; i++) {
1745 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1746 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1751 /* Chip might not be fitted with firmware. Some Sun onboard
1752 * parts are configured like that. So don't signal the timeout
1753 * of the above loop as an error, but do report the lack of
1754 * running firmware once.
1756 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1757 tg3_flag_set(tp, NO_FWARE_REPORTED);
1759 netdev_info(tp->dev, "No firmware running\n");
1762 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1763 /* The 57765 A0 needs a little more
1764 * time to do some important work.
1772 static void tg3_link_report(struct tg3 *tp)
1774 if (!netif_carrier_ok(tp->dev)) {
1775 netif_info(tp, link, tp->dev, "Link is down\n");
1776 tg3_ump_link_report(tp);
1777 } else if (netif_msg_link(tp)) {
1778 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1779 (tp->link_config.active_speed == SPEED_1000 ?
1781 (tp->link_config.active_speed == SPEED_100 ?
1783 (tp->link_config.active_duplex == DUPLEX_FULL ?
1786 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1787 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1789 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1792 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1793 netdev_info(tp->dev, "EEE is %s\n",
1794 tp->setlpicnt ? "enabled" : "disabled");
1796 tg3_ump_link_report(tp);
1800 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1804 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1805 miireg = ADVERTISE_1000XPAUSE;
1806 else if (flow_ctrl & FLOW_CTRL_TX)
1807 miireg = ADVERTISE_1000XPSE_ASYM;
1808 else if (flow_ctrl & FLOW_CTRL_RX)
1809 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1816 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1820 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1821 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1822 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1823 if (lcladv & ADVERTISE_1000XPAUSE)
1825 if (rmtadv & ADVERTISE_1000XPAUSE)
1832 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1836 u32 old_rx_mode = tp->rx_mode;
1837 u32 old_tx_mode = tp->tx_mode;
1839 if (tg3_flag(tp, USE_PHYLIB))
1840 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1842 autoneg = tp->link_config.autoneg;
1844 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1845 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1846 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1848 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1850 flowctrl = tp->link_config.flowctrl;
1852 tp->link_config.active_flowctrl = flowctrl;
1854 if (flowctrl & FLOW_CTRL_RX)
1855 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1857 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1859 if (old_rx_mode != tp->rx_mode)
1860 tw32_f(MAC_RX_MODE, tp->rx_mode);
1862 if (flowctrl & FLOW_CTRL_TX)
1863 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1865 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1867 if (old_tx_mode != tp->tx_mode)
1868 tw32_f(MAC_TX_MODE, tp->tx_mode);
1871 static void tg3_adjust_link(struct net_device *dev)
1873 u8 oldflowctrl, linkmesg = 0;
1874 u32 mac_mode, lcl_adv, rmt_adv;
1875 struct tg3 *tp = netdev_priv(dev);
1876 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1878 spin_lock_bh(&tp->lock);
1880 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1881 MAC_MODE_HALF_DUPLEX);
1883 oldflowctrl = tp->link_config.active_flowctrl;
1889 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1890 mac_mode |= MAC_MODE_PORT_MODE_MII;
1891 else if (phydev->speed == SPEED_1000 ||
1892 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1893 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1895 mac_mode |= MAC_MODE_PORT_MODE_MII;
1897 if (phydev->duplex == DUPLEX_HALF)
1898 mac_mode |= MAC_MODE_HALF_DUPLEX;
1900 lcl_adv = mii_advertise_flowctrl(
1901 tp->link_config.flowctrl);
1904 rmt_adv = LPA_PAUSE_CAP;
1905 if (phydev->asym_pause)
1906 rmt_adv |= LPA_PAUSE_ASYM;
1909 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1911 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1913 if (mac_mode != tp->mac_mode) {
1914 tp->mac_mode = mac_mode;
1915 tw32_f(MAC_MODE, tp->mac_mode);
1919 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1920 if (phydev->speed == SPEED_10)
1922 MAC_MI_STAT_10MBPS_MODE |
1923 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1925 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1928 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1929 tw32(MAC_TX_LENGTHS,
1930 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1931 (6 << TX_LENGTHS_IPG_SHIFT) |
1932 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1934 tw32(MAC_TX_LENGTHS,
1935 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1936 (6 << TX_LENGTHS_IPG_SHIFT) |
1937 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1939 if (phydev->link != tp->old_link ||
1940 phydev->speed != tp->link_config.active_speed ||
1941 phydev->duplex != tp->link_config.active_duplex ||
1942 oldflowctrl != tp->link_config.active_flowctrl)
1945 tp->old_link = phydev->link;
1946 tp->link_config.active_speed = phydev->speed;
1947 tp->link_config.active_duplex = phydev->duplex;
1949 spin_unlock_bh(&tp->lock);
1952 tg3_link_report(tp);
1955 static int tg3_phy_init(struct tg3 *tp)
1957 struct phy_device *phydev;
1959 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1962 /* Bring the PHY back to a known state. */
1965 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1967 /* Attach the MAC to the PHY. */
1968 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1969 phydev->dev_flags, phydev->interface);
1970 if (IS_ERR(phydev)) {
1971 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1972 return PTR_ERR(phydev);
1975 /* Mask with MAC supported features. */
1976 switch (phydev->interface) {
1977 case PHY_INTERFACE_MODE_GMII:
1978 case PHY_INTERFACE_MODE_RGMII:
1979 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1980 phydev->supported &= (PHY_GBIT_FEATURES |
1982 SUPPORTED_Asym_Pause);
1986 case PHY_INTERFACE_MODE_MII:
1987 phydev->supported &= (PHY_BASIC_FEATURES |
1989 SUPPORTED_Asym_Pause);
1992 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1996 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1998 phydev->advertising = phydev->supported;
2003 static void tg3_phy_start(struct tg3 *tp)
2005 struct phy_device *phydev;
2007 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2010 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2012 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2013 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2014 phydev->speed = tp->link_config.speed;
2015 phydev->duplex = tp->link_config.duplex;
2016 phydev->autoneg = tp->link_config.autoneg;
2017 phydev->advertising = tp->link_config.advertising;
2022 phy_start_aneg(phydev);
2025 static void tg3_phy_stop(struct tg3 *tp)
2027 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2030 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2033 static void tg3_phy_fini(struct tg3 *tp)
2035 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2036 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2037 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2041 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2046 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2049 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2050 /* Cannot do read-modify-write on 5401 */
2051 err = tg3_phy_auxctl_write(tp,
2052 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2053 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2058 err = tg3_phy_auxctl_read(tp,
2059 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2063 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2064 err = tg3_phy_auxctl_write(tp,
2065 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2071 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2075 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2078 tg3_writephy(tp, MII_TG3_FET_TEST,
2079 phytest | MII_TG3_FET_SHADOW_EN);
2080 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2082 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2084 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2085 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2087 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2091 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2095 if (!tg3_flag(tp, 5705_PLUS) ||
2096 (tg3_flag(tp, 5717_PLUS) &&
2097 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2100 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2101 tg3_phy_fet_toggle_apd(tp, enable);
2105 reg = MII_TG3_MISC_SHDW_WREN |
2106 MII_TG3_MISC_SHDW_SCR5_SEL |
2107 MII_TG3_MISC_SHDW_SCR5_LPED |
2108 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2109 MII_TG3_MISC_SHDW_SCR5_SDTL |
2110 MII_TG3_MISC_SHDW_SCR5_C125OE;
2111 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2112 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2114 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2117 reg = MII_TG3_MISC_SHDW_WREN |
2118 MII_TG3_MISC_SHDW_APD_SEL |
2119 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2121 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2123 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2126 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2130 if (!tg3_flag(tp, 5705_PLUS) ||
2131 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2134 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2137 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2138 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2140 tg3_writephy(tp, MII_TG3_FET_TEST,
2141 ephy | MII_TG3_FET_SHADOW_EN);
2142 if (!tg3_readphy(tp, reg, &phy)) {
2144 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2146 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2147 tg3_writephy(tp, reg, phy);
2149 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2154 ret = tg3_phy_auxctl_read(tp,
2155 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2158 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2160 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2161 tg3_phy_auxctl_write(tp,
2162 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2167 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2172 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2175 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2177 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2178 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2181 static void tg3_phy_apply_otp(struct tg3 *tp)
2190 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2193 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2194 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2195 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2197 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2198 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2199 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2201 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2202 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2203 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2205 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2206 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2208 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2209 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2211 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2212 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2213 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2215 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2218 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2222 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2227 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2228 current_link_up == 1 &&
2229 tp->link_config.active_duplex == DUPLEX_FULL &&
2230 (tp->link_config.active_speed == SPEED_100 ||
2231 tp->link_config.active_speed == SPEED_1000)) {
2234 if (tp->link_config.active_speed == SPEED_1000)
2235 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2237 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2239 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2241 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2242 TG3_CL45_D7_EEERES_STAT, &val);
2244 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2245 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2249 if (!tp->setlpicnt) {
2250 if (current_link_up == 1 &&
2251 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2252 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2253 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2256 val = tr32(TG3_CPMU_EEE_MODE);
2257 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2261 static void tg3_phy_eee_enable(struct tg3 *tp)
2265 if (tp->link_config.active_speed == SPEED_1000 &&
2266 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2267 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2268 tg3_flag(tp, 57765_CLASS)) &&
2269 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2270 val = MII_TG3_DSP_TAP26_ALNOKO |
2271 MII_TG3_DSP_TAP26_RMRXSTO;
2272 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2273 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2276 val = tr32(TG3_CPMU_EEE_MODE);
2277 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2280 static int tg3_wait_macro_done(struct tg3 *tp)
2287 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2288 if ((tmp32 & 0x1000) == 0)
2298 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2300 static const u32 test_pat[4][6] = {
2301 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2302 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2303 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2304 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2308 for (chan = 0; chan < 4; chan++) {
2311 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2312 (chan * 0x2000) | 0x0200);
2313 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2315 for (i = 0; i < 6; i++)
2316 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2319 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2320 if (tg3_wait_macro_done(tp)) {
2325 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2326 (chan * 0x2000) | 0x0200);
2327 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2328 if (tg3_wait_macro_done(tp)) {
2333 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2334 if (tg3_wait_macro_done(tp)) {
2339 for (i = 0; i < 6; i += 2) {
2342 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2343 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2344 tg3_wait_macro_done(tp)) {
2350 if (low != test_pat[chan][i] ||
2351 high != test_pat[chan][i+1]) {
2352 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2353 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2354 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2364 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2368 for (chan = 0; chan < 4; chan++) {
2371 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2372 (chan * 0x2000) | 0x0200);
2373 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2374 for (i = 0; i < 6; i++)
2375 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2376 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2377 if (tg3_wait_macro_done(tp))
2384 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2386 u32 reg32, phy9_orig;
2387 int retries, do_phy_reset, err;
2393 err = tg3_bmcr_reset(tp);
2399 /* Disable transmitter and interrupt. */
2400 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2404 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2406 /* Set full-duplex, 1000 mbps. */
2407 tg3_writephy(tp, MII_BMCR,
2408 BMCR_FULLDPLX | BMCR_SPEED1000);
2410 /* Set to master mode. */
2411 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2414 tg3_writephy(tp, MII_CTRL1000,
2415 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2417 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2421 /* Block the PHY control access. */
2422 tg3_phydsp_write(tp, 0x8005, 0x0800);
2424 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2427 } while (--retries);
2429 err = tg3_phy_reset_chanpat(tp);
2433 tg3_phydsp_write(tp, 0x8005, 0x0000);
2435 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2436 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2438 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2440 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2442 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2444 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2451 /* This will reset the tigon3 PHY if there is no valid
2452 * link unless the FORCE argument is non-zero.
2454 static int tg3_phy_reset(struct tg3 *tp)
2459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2460 val = tr32(GRC_MISC_CFG);
2461 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2464 err = tg3_readphy(tp, MII_BMSR, &val);
2465 err |= tg3_readphy(tp, MII_BMSR, &val);
2469 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2470 netif_carrier_off(tp->dev);
2471 tg3_link_report(tp);
2474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2476 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2477 err = tg3_phy_reset_5703_4_5(tp);
2484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2485 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2486 cpmuctrl = tr32(TG3_CPMU_CTRL);
2487 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2489 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2492 err = tg3_bmcr_reset(tp);
2496 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2497 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2498 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2500 tw32(TG3_CPMU_CTRL, cpmuctrl);
2503 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2504 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2505 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2506 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2507 CPMU_LSPD_1000MB_MACCLK_12_5) {
2508 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2510 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2514 if (tg3_flag(tp, 5717_PLUS) &&
2515 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2518 tg3_phy_apply_otp(tp);
2520 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2521 tg3_phy_toggle_apd(tp, true);
2523 tg3_phy_toggle_apd(tp, false);
2526 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2527 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2528 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2529 tg3_phydsp_write(tp, 0x000a, 0x0323);
2530 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2533 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2534 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2535 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2538 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2539 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2540 tg3_phydsp_write(tp, 0x000a, 0x310b);
2541 tg3_phydsp_write(tp, 0x201f, 0x9506);
2542 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2543 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2545 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2546 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2547 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2548 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2549 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2550 tg3_writephy(tp, MII_TG3_TEST1,
2551 MII_TG3_TEST1_TRIM_EN | 0x4);
2553 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2555 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2559 /* Set Extended packet length bit (bit 14) on all chips that */
2560 /* support jumbo frames */
2561 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2562 /* Cannot do read-modify-write on 5401 */
2563 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2564 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2565 /* Set bit 14 with read-modify-write to preserve other bits */
2566 err = tg3_phy_auxctl_read(tp,
2567 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2569 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2570 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2573 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2574 * jumbo frames transmission.
2576 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2577 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2578 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2579 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2583 /* adjust output voltage */
2584 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2587 tg3_phy_toggle_automdix(tp, 1);
2588 tg3_phy_set_wirespeed(tp);
2592 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2593 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2594 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2595 TG3_GPIO_MSG_NEED_VAUX)
2596 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2597 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2598 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2599 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2600 (TG3_GPIO_MSG_DRVR_PRES << 12))
2602 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2603 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2604 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2605 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2606 (TG3_GPIO_MSG_NEED_VAUX << 12))
2608 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2613 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2614 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2616 status = tr32(TG3_CPMU_DRV_STATUS);
2618 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2619 status &= ~(TG3_GPIO_MSG_MASK << shift);
2620 status |= (newstat << shift);
2622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2623 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2624 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2626 tw32(TG3_CPMU_DRV_STATUS, status);
2628 return status >> TG3_APE_GPIO_MSG_SHIFT;
2631 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2633 if (!tg3_flag(tp, IS_NIC))
2636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2639 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2642 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2644 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2645 TG3_GRC_LCLCTL_PWRSW_DELAY);
2647 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2649 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2650 TG3_GRC_LCLCTL_PWRSW_DELAY);
2656 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2660 if (!tg3_flag(tp, IS_NIC) ||
2661 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2665 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2667 tw32_wait_f(GRC_LOCAL_CTRL,
2668 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2669 TG3_GRC_LCLCTL_PWRSW_DELAY);
2671 tw32_wait_f(GRC_LOCAL_CTRL,
2673 TG3_GRC_LCLCTL_PWRSW_DELAY);
2675 tw32_wait_f(GRC_LOCAL_CTRL,
2676 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2677 TG3_GRC_LCLCTL_PWRSW_DELAY);
2680 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2682 if (!tg3_flag(tp, IS_NIC))
2685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2686 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2687 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2688 (GRC_LCLCTRL_GPIO_OE0 |
2689 GRC_LCLCTRL_GPIO_OE1 |
2690 GRC_LCLCTRL_GPIO_OE2 |
2691 GRC_LCLCTRL_GPIO_OUTPUT0 |
2692 GRC_LCLCTRL_GPIO_OUTPUT1),
2693 TG3_GRC_LCLCTL_PWRSW_DELAY);
2694 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2695 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2696 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2697 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2698 GRC_LCLCTRL_GPIO_OE1 |
2699 GRC_LCLCTRL_GPIO_OE2 |
2700 GRC_LCLCTRL_GPIO_OUTPUT0 |
2701 GRC_LCLCTRL_GPIO_OUTPUT1 |
2703 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2704 TG3_GRC_LCLCTL_PWRSW_DELAY);
2706 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2707 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2708 TG3_GRC_LCLCTL_PWRSW_DELAY);
2710 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2711 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2712 TG3_GRC_LCLCTL_PWRSW_DELAY);
2715 u32 grc_local_ctrl = 0;
2717 /* Workaround to prevent overdrawing Amps. */
2718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2719 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2720 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2722 TG3_GRC_LCLCTL_PWRSW_DELAY);
2725 /* On 5753 and variants, GPIO2 cannot be used. */
2726 no_gpio2 = tp->nic_sram_data_cfg &
2727 NIC_SRAM_DATA_CFG_NO_GPIO2;
2729 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2730 GRC_LCLCTRL_GPIO_OE1 |
2731 GRC_LCLCTRL_GPIO_OE2 |
2732 GRC_LCLCTRL_GPIO_OUTPUT1 |
2733 GRC_LCLCTRL_GPIO_OUTPUT2;
2735 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2736 GRC_LCLCTRL_GPIO_OUTPUT2);
2738 tw32_wait_f(GRC_LOCAL_CTRL,
2739 tp->grc_local_ctrl | grc_local_ctrl,
2740 TG3_GRC_LCLCTL_PWRSW_DELAY);
2742 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2744 tw32_wait_f(GRC_LOCAL_CTRL,
2745 tp->grc_local_ctrl | grc_local_ctrl,
2746 TG3_GRC_LCLCTL_PWRSW_DELAY);
2749 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2750 tw32_wait_f(GRC_LOCAL_CTRL,
2751 tp->grc_local_ctrl | grc_local_ctrl,
2752 TG3_GRC_LCLCTL_PWRSW_DELAY);
2757 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2761 /* Serialize power state transitions */
2762 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2765 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2766 msg = TG3_GPIO_MSG_NEED_VAUX;
2768 msg = tg3_set_function_status(tp, msg);
2770 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2773 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2774 tg3_pwrsrc_switch_to_vaux(tp);
2776 tg3_pwrsrc_die_with_vmain(tp);
2779 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2782 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2784 bool need_vaux = false;
2786 /* The GPIOs do something completely different on 57765. */
2787 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2791 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2792 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2793 tg3_frob_aux_power_5717(tp, include_wol ?
2794 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2798 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2799 struct net_device *dev_peer;
2801 dev_peer = pci_get_drvdata(tp->pdev_peer);
2803 /* remove_one() may have been run on the peer. */
2805 struct tg3 *tp_peer = netdev_priv(dev_peer);
2807 if (tg3_flag(tp_peer, INIT_COMPLETE))
2810 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2811 tg3_flag(tp_peer, ENABLE_ASF))
2816 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2817 tg3_flag(tp, ENABLE_ASF))
2821 tg3_pwrsrc_switch_to_vaux(tp);
2823 tg3_pwrsrc_die_with_vmain(tp);
2826 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2828 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2830 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2831 if (speed != SPEED_10)
2833 } else if (speed == SPEED_10)
2839 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2843 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2844 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2845 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2846 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2849 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2850 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2851 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2858 val = tr32(GRC_MISC_CFG);
2859 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2862 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2864 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2867 tg3_writephy(tp, MII_ADVERTISE, 0);
2868 tg3_writephy(tp, MII_BMCR,
2869 BMCR_ANENABLE | BMCR_ANRESTART);
2871 tg3_writephy(tp, MII_TG3_FET_TEST,
2872 phytest | MII_TG3_FET_SHADOW_EN);
2873 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2874 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2876 MII_TG3_FET_SHDW_AUXMODE4,
2879 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2882 } else if (do_low_power) {
2883 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2884 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2886 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2887 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2888 MII_TG3_AUXCTL_PCTL_VREG_11V;
2889 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2892 /* The PHY should not be powered down on some chips because
2895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2896 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2897 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2898 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
2899 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
2903 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2904 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2905 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2906 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2907 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2908 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2911 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2914 /* tp->lock is held. */
2915 static int tg3_nvram_lock(struct tg3 *tp)
2917 if (tg3_flag(tp, NVRAM)) {
2920 if (tp->nvram_lock_cnt == 0) {
2921 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2922 for (i = 0; i < 8000; i++) {
2923 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2928 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2932 tp->nvram_lock_cnt++;
2937 /* tp->lock is held. */
2938 static void tg3_nvram_unlock(struct tg3 *tp)
2940 if (tg3_flag(tp, NVRAM)) {
2941 if (tp->nvram_lock_cnt > 0)
2942 tp->nvram_lock_cnt--;
2943 if (tp->nvram_lock_cnt == 0)
2944 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2948 /* tp->lock is held. */
2949 static void tg3_enable_nvram_access(struct tg3 *tp)
2951 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2952 u32 nvaccess = tr32(NVRAM_ACCESS);
2954 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2958 /* tp->lock is held. */
2959 static void tg3_disable_nvram_access(struct tg3 *tp)
2961 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2962 u32 nvaccess = tr32(NVRAM_ACCESS);
2964 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2968 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2969 u32 offset, u32 *val)
2974 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2977 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2978 EEPROM_ADDR_DEVID_MASK |
2980 tw32(GRC_EEPROM_ADDR,
2982 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2983 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2984 EEPROM_ADDR_ADDR_MASK) |
2985 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2987 for (i = 0; i < 1000; i++) {
2988 tmp = tr32(GRC_EEPROM_ADDR);
2990 if (tmp & EEPROM_ADDR_COMPLETE)
2994 if (!(tmp & EEPROM_ADDR_COMPLETE))
2997 tmp = tr32(GRC_EEPROM_DATA);
3000 * The data will always be opposite the native endian
3001 * format. Perform a blind byteswap to compensate.
3008 #define NVRAM_CMD_TIMEOUT 10000
3010 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3014 tw32(NVRAM_CMD, nvram_cmd);
3015 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3017 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3023 if (i == NVRAM_CMD_TIMEOUT)
3029 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3031 if (tg3_flag(tp, NVRAM) &&
3032 tg3_flag(tp, NVRAM_BUFFERED) &&
3033 tg3_flag(tp, FLASH) &&
3034 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3035 (tp->nvram_jedecnum == JEDEC_ATMEL))
3037 addr = ((addr / tp->nvram_pagesize) <<
3038 ATMEL_AT45DB0X1B_PAGE_POS) +
3039 (addr % tp->nvram_pagesize);
3044 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3046 if (tg3_flag(tp, NVRAM) &&
3047 tg3_flag(tp, NVRAM_BUFFERED) &&
3048 tg3_flag(tp, FLASH) &&
3049 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3050 (tp->nvram_jedecnum == JEDEC_ATMEL))
3052 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3053 tp->nvram_pagesize) +
3054 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3059 /* NOTE: Data read in from NVRAM is byteswapped according to
3060 * the byteswapping settings for all other register accesses.
3061 * tg3 devices are BE devices, so on a BE machine, the data
3062 * returned will be exactly as it is seen in NVRAM. On a LE
3063 * machine, the 32-bit value will be byteswapped.
3065 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3069 if (!tg3_flag(tp, NVRAM))
3070 return tg3_nvram_read_using_eeprom(tp, offset, val);
3072 offset = tg3_nvram_phys_addr(tp, offset);
3074 if (offset > NVRAM_ADDR_MSK)
3077 ret = tg3_nvram_lock(tp);
3081 tg3_enable_nvram_access(tp);
3083 tw32(NVRAM_ADDR, offset);
3084 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3085 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3088 *val = tr32(NVRAM_RDDATA);
3090 tg3_disable_nvram_access(tp);
3092 tg3_nvram_unlock(tp);
3097 /* Ensures NVRAM data is in bytestream format. */
3098 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3101 int res = tg3_nvram_read(tp, offset, &v);
3103 *val = cpu_to_be32(v);
3107 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3108 u32 offset, u32 len, u8 *buf)
3113 for (i = 0; i < len; i += 4) {
3119 memcpy(&data, buf + i, 4);
3122 * The SEEPROM interface expects the data to always be opposite
3123 * the native endian format. We accomplish this by reversing
3124 * all the operations that would have been performed on the
3125 * data from a call to tg3_nvram_read_be32().
3127 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3129 val = tr32(GRC_EEPROM_ADDR);
3130 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3132 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3134 tw32(GRC_EEPROM_ADDR, val |
3135 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3136 (addr & EEPROM_ADDR_ADDR_MASK) |
3140 for (j = 0; j < 1000; j++) {
3141 val = tr32(GRC_EEPROM_ADDR);
3143 if (val & EEPROM_ADDR_COMPLETE)
3147 if (!(val & EEPROM_ADDR_COMPLETE)) {
3156 /* offset and length are dword aligned */
3157 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3161 u32 pagesize = tp->nvram_pagesize;
3162 u32 pagemask = pagesize - 1;
3166 tmp = kmalloc(pagesize, GFP_KERNEL);
3172 u32 phy_addr, page_off, size;
3174 phy_addr = offset & ~pagemask;
3176 for (j = 0; j < pagesize; j += 4) {
3177 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3178 (__be32 *) (tmp + j));
3185 page_off = offset & pagemask;
3192 memcpy(tmp + page_off, buf, size);
3194 offset = offset + (pagesize - page_off);
3196 tg3_enable_nvram_access(tp);
3199 * Before we can erase the flash page, we need
3200 * to issue a special "write enable" command.
3202 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3204 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3207 /* Erase the target page */
3208 tw32(NVRAM_ADDR, phy_addr);
3210 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3211 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3213 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3216 /* Issue another write enable to start the write. */
3217 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3219 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3222 for (j = 0; j < pagesize; j += 4) {
3225 data = *((__be32 *) (tmp + j));
3227 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3229 tw32(NVRAM_ADDR, phy_addr + j);
3231 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3235 nvram_cmd |= NVRAM_CMD_FIRST;
3236 else if (j == (pagesize - 4))
3237 nvram_cmd |= NVRAM_CMD_LAST;
3239 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3247 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3248 tg3_nvram_exec_cmd(tp, nvram_cmd);
3255 /* offset and length are dword aligned */
3256 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3261 for (i = 0; i < len; i += 4, offset += 4) {
3262 u32 page_off, phy_addr, nvram_cmd;
3265 memcpy(&data, buf + i, 4);
3266 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3268 page_off = offset % tp->nvram_pagesize;
3270 phy_addr = tg3_nvram_phys_addr(tp, offset);
3272 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3274 if (page_off == 0 || i == 0)
3275 nvram_cmd |= NVRAM_CMD_FIRST;
3276 if (page_off == (tp->nvram_pagesize - 4))
3277 nvram_cmd |= NVRAM_CMD_LAST;
3280 nvram_cmd |= NVRAM_CMD_LAST;
3282 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3283 !tg3_flag(tp, FLASH) ||
3284 !tg3_flag(tp, 57765_PLUS))
3285 tw32(NVRAM_ADDR, phy_addr);
3287 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
3288 !tg3_flag(tp, 5755_PLUS) &&
3289 (tp->nvram_jedecnum == JEDEC_ST) &&
3290 (nvram_cmd & NVRAM_CMD_FIRST)) {
3293 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3294 ret = tg3_nvram_exec_cmd(tp, cmd);
3298 if (!tg3_flag(tp, FLASH)) {
3299 /* We always do complete word writes to eeprom. */
3300 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3303 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3310 /* offset and length are dword aligned */
3311 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3315 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3316 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3317 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3321 if (!tg3_flag(tp, NVRAM)) {
3322 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3326 ret = tg3_nvram_lock(tp);
3330 tg3_enable_nvram_access(tp);
3331 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3332 tw32(NVRAM_WRITE1, 0x406);
3334 grc_mode = tr32(GRC_MODE);
3335 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3337 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3338 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3341 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3345 grc_mode = tr32(GRC_MODE);
3346 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3348 tg3_disable_nvram_access(tp);
3349 tg3_nvram_unlock(tp);
3352 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3353 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3360 #define RX_CPU_SCRATCH_BASE 0x30000
3361 #define RX_CPU_SCRATCH_SIZE 0x04000
3362 #define TX_CPU_SCRATCH_BASE 0x34000
3363 #define TX_CPU_SCRATCH_SIZE 0x04000
3365 /* tp->lock is held. */
3366 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3370 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3373 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3375 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3378 if (offset == RX_CPU_BASE) {
3379 for (i = 0; i < 10000; i++) {
3380 tw32(offset + CPU_STATE, 0xffffffff);
3381 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3382 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3386 tw32(offset + CPU_STATE, 0xffffffff);
3387 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3390 for (i = 0; i < 10000; i++) {
3391 tw32(offset + CPU_STATE, 0xffffffff);
3392 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3393 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3399 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3400 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3404 /* Clear firmware's nvram arbitration. */
3405 if (tg3_flag(tp, NVRAM))
3406 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3411 unsigned int fw_base;
3412 unsigned int fw_len;
3413 const __be32 *fw_data;
3416 /* tp->lock is held. */
3417 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3418 u32 cpu_scratch_base, int cpu_scratch_size,
3419 struct fw_info *info)
3421 int err, lock_err, i;
3422 void (*write_op)(struct tg3 *, u32, u32);
3424 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3426 "%s: Trying to load TX cpu firmware which is 5705\n",
3431 if (tg3_flag(tp, 5705_PLUS))
3432 write_op = tg3_write_mem;
3434 write_op = tg3_write_indirect_reg32;
3436 /* It is possible that bootcode is still loading at this point.
3437 * Get the nvram lock first before halting the cpu.
3439 lock_err = tg3_nvram_lock(tp);
3440 err = tg3_halt_cpu(tp, cpu_base);
3442 tg3_nvram_unlock(tp);
3446 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3447 write_op(tp, cpu_scratch_base + i, 0);
3448 tw32(cpu_base + CPU_STATE, 0xffffffff);
3449 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3450 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3451 write_op(tp, (cpu_scratch_base +
3452 (info->fw_base & 0xffff) +
3454 be32_to_cpu(info->fw_data[i]));
3462 /* tp->lock is held. */
3463 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3465 struct fw_info info;
3466 const __be32 *fw_data;
3469 fw_data = (void *)tp->fw->data;
3471 /* Firmware blob starts with version numbers, followed by
3472 start address and length. We are setting complete length.
3473 length = end_address_of_bss - start_address_of_text.
3474 Remainder is the blob to be loaded contiguously
3475 from start address. */
3477 info.fw_base = be32_to_cpu(fw_data[1]);
3478 info.fw_len = tp->fw->size - 12;
3479 info.fw_data = &fw_data[3];
3481 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3482 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3487 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3488 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3493 /* Now startup only the RX cpu. */
3494 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3495 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3497 for (i = 0; i < 5; i++) {
3498 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3500 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3501 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3502 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3506 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3507 "should be %08x\n", __func__,
3508 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3511 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3512 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3517 /* tp->lock is held. */
3518 static int tg3_load_tso_firmware(struct tg3 *tp)
3520 struct fw_info info;
3521 const __be32 *fw_data;
3522 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3525 if (tg3_flag(tp, HW_TSO_1) ||
3526 tg3_flag(tp, HW_TSO_2) ||
3527 tg3_flag(tp, HW_TSO_3))
3530 fw_data = (void *)tp->fw->data;
3532 /* Firmware blob starts with version numbers, followed by
3533 start address and length. We are setting complete length.
3534 length = end_address_of_bss - start_address_of_text.
3535 Remainder is the blob to be loaded contiguously
3536 from start address. */
3538 info.fw_base = be32_to_cpu(fw_data[1]);
3539 cpu_scratch_size = tp->fw_len;
3540 info.fw_len = tp->fw->size - 12;
3541 info.fw_data = &fw_data[3];
3543 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3544 cpu_base = RX_CPU_BASE;
3545 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3547 cpu_base = TX_CPU_BASE;
3548 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3549 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3552 err = tg3_load_firmware_cpu(tp, cpu_base,
3553 cpu_scratch_base, cpu_scratch_size,
3558 /* Now startup the cpu. */
3559 tw32(cpu_base + CPU_STATE, 0xffffffff);
3560 tw32_f(cpu_base + CPU_PC, info.fw_base);
3562 for (i = 0; i < 5; i++) {
3563 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3565 tw32(cpu_base + CPU_STATE, 0xffffffff);
3566 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3567 tw32_f(cpu_base + CPU_PC, info.fw_base);
3572 "%s fails to set CPU PC, is %08x should be %08x\n",
3573 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3576 tw32(cpu_base + CPU_STATE, 0xffffffff);
3577 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3582 /* tp->lock is held. */
3583 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3585 u32 addr_high, addr_low;
3588 addr_high = ((tp->dev->dev_addr[0] << 8) |
3589 tp->dev->dev_addr[1]);
3590 addr_low = ((tp->dev->dev_addr[2] << 24) |
3591 (tp->dev->dev_addr[3] << 16) |
3592 (tp->dev->dev_addr[4] << 8) |
3593 (tp->dev->dev_addr[5] << 0));
3594 for (i = 0; i < 4; i++) {
3595 if (i == 1 && skip_mac_1)
3597 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3598 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3601 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3602 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3603 for (i = 0; i < 12; i++) {
3604 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3605 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3609 addr_high = (tp->dev->dev_addr[0] +
3610 tp->dev->dev_addr[1] +
3611 tp->dev->dev_addr[2] +
3612 tp->dev->dev_addr[3] +
3613 tp->dev->dev_addr[4] +
3614 tp->dev->dev_addr[5]) &
3615 TX_BACKOFF_SEED_MASK;
3616 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3619 static void tg3_enable_register_access(struct tg3 *tp)
3622 * Make sure register accesses (indirect or otherwise) will function
3625 pci_write_config_dword(tp->pdev,
3626 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3629 static int tg3_power_up(struct tg3 *tp)
3633 tg3_enable_register_access(tp);
3635 err = pci_set_power_state(tp->pdev, PCI_D0);
3637 /* Switch out of Vaux if it is a NIC */
3638 tg3_pwrsrc_switch_to_vmain(tp);
3640 netdev_err(tp->dev, "Transition to D0 failed\n");
3646 static int tg3_setup_phy(struct tg3 *, int);
3648 static int tg3_power_down_prepare(struct tg3 *tp)
3651 bool device_should_wake, do_low_power;
3653 tg3_enable_register_access(tp);
3655 /* Restore the CLKREQ setting. */
3656 if (tg3_flag(tp, CLKREQ_BUG)) {
3659 pci_read_config_word(tp->pdev,
3660 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3662 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3663 pci_write_config_word(tp->pdev,
3664 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3668 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3669 tw32(TG3PCI_MISC_HOST_CTRL,
3670 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3672 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3673 tg3_flag(tp, WOL_ENABLE);
3675 if (tg3_flag(tp, USE_PHYLIB)) {
3676 do_low_power = false;
3677 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3678 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3679 struct phy_device *phydev;
3680 u32 phyid, advertising;
3682 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3684 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3686 tp->link_config.speed = phydev->speed;
3687 tp->link_config.duplex = phydev->duplex;
3688 tp->link_config.autoneg = phydev->autoneg;
3689 tp->link_config.advertising = phydev->advertising;
3691 advertising = ADVERTISED_TP |
3693 ADVERTISED_Autoneg |
3694 ADVERTISED_10baseT_Half;
3696 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3697 if (tg3_flag(tp, WOL_SPEED_100MB))
3699 ADVERTISED_100baseT_Half |
3700 ADVERTISED_100baseT_Full |
3701 ADVERTISED_10baseT_Full;
3703 advertising |= ADVERTISED_10baseT_Full;
3706 phydev->advertising = advertising;
3708 phy_start_aneg(phydev);
3710 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3711 if (phyid != PHY_ID_BCMAC131) {
3712 phyid &= PHY_BCM_OUI_MASK;
3713 if (phyid == PHY_BCM_OUI_1 ||
3714 phyid == PHY_BCM_OUI_2 ||
3715 phyid == PHY_BCM_OUI_3)
3716 do_low_power = true;
3720 do_low_power = true;
3722 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
3723 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3725 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
3726 tg3_setup_phy(tp, 0);
3729 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3732 val = tr32(GRC_VCPU_EXT_CTRL);
3733 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3734 } else if (!tg3_flag(tp, ENABLE_ASF)) {
3738 for (i = 0; i < 200; i++) {
3739 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3740 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3745 if (tg3_flag(tp, WOL_CAP))
3746 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3747 WOL_DRV_STATE_SHUTDOWN |
3751 if (device_should_wake) {
3754 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3756 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3757 tg3_phy_auxctl_write(tp,
3758 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3759 MII_TG3_AUXCTL_PCTL_WOL_EN |
3760 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3761 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3765 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3766 mac_mode = MAC_MODE_PORT_MODE_GMII;
3768 mac_mode = MAC_MODE_PORT_MODE_MII;
3770 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3771 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3773 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3774 SPEED_100 : SPEED_10;
3775 if (tg3_5700_link_polarity(tp, speed))
3776 mac_mode |= MAC_MODE_LINK_POLARITY;
3778 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3781 mac_mode = MAC_MODE_PORT_MODE_TBI;
3784 if (!tg3_flag(tp, 5750_PLUS))
3785 tw32(MAC_LED_CTRL, tp->led_ctrl);
3787 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3788 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3789 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3790 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3792 if (tg3_flag(tp, ENABLE_APE))
3793 mac_mode |= MAC_MODE_APE_TX_EN |
3794 MAC_MODE_APE_RX_EN |
3795 MAC_MODE_TDE_ENABLE;
3797 tw32_f(MAC_MODE, mac_mode);
3800 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3804 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3805 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3806 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3809 base_val = tp->pci_clock_ctrl;
3810 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3811 CLOCK_CTRL_TXCLK_DISABLE);
3813 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3814 CLOCK_CTRL_PWRDOWN_PLL133, 40);
3815 } else if (tg3_flag(tp, 5780_CLASS) ||
3816 tg3_flag(tp, CPMU_PRESENT) ||
3817 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3819 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3820 u32 newbits1, newbits2;
3822 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3823 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3824 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3825 CLOCK_CTRL_TXCLK_DISABLE |
3827 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3828 } else if (tg3_flag(tp, 5705_PLUS)) {
3829 newbits1 = CLOCK_CTRL_625_CORE;
3830 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3832 newbits1 = CLOCK_CTRL_ALTCLK;
3833 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3836 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3839 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3842 if (!tg3_flag(tp, 5705_PLUS)) {
3845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3847 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3848 CLOCK_CTRL_TXCLK_DISABLE |
3849 CLOCK_CTRL_44MHZ_CORE);
3851 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3854 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3855 tp->pci_clock_ctrl | newbits3, 40);
3859 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3860 tg3_power_down_phy(tp, do_low_power);
3862 tg3_frob_aux_power(tp, true);
3864 /* Workaround for unstable PLL clock */
3865 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3866 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3867 u32 val = tr32(0x7d00);
3869 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3871 if (!tg3_flag(tp, ENABLE_ASF)) {
3874 err = tg3_nvram_lock(tp);
3875 tg3_halt_cpu(tp, RX_CPU_BASE);
3877 tg3_nvram_unlock(tp);
3881 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3886 static void tg3_power_down(struct tg3 *tp)
3888 tg3_power_down_prepare(tp);
3890 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3891 pci_set_power_state(tp->pdev, PCI_D3hot);
3894 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3896 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3897 case MII_TG3_AUX_STAT_10HALF:
3899 *duplex = DUPLEX_HALF;
3902 case MII_TG3_AUX_STAT_10FULL:
3904 *duplex = DUPLEX_FULL;
3907 case MII_TG3_AUX_STAT_100HALF:
3909 *duplex = DUPLEX_HALF;
3912 case MII_TG3_AUX_STAT_100FULL:
3914 *duplex = DUPLEX_FULL;
3917 case MII_TG3_AUX_STAT_1000HALF:
3918 *speed = SPEED_1000;
3919 *duplex = DUPLEX_HALF;
3922 case MII_TG3_AUX_STAT_1000FULL:
3923 *speed = SPEED_1000;
3924 *duplex = DUPLEX_FULL;
3928 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3929 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3931 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3935 *speed = SPEED_UNKNOWN;
3936 *duplex = DUPLEX_UNKNOWN;
3941 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3946 new_adv = ADVERTISE_CSMA;
3947 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
3948 new_adv |= mii_advertise_flowctrl(flowctrl);
3950 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3954 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3955 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
3957 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3958 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3959 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3961 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3966 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3969 tw32(TG3_CPMU_EEE_MODE,
3970 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3972 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3977 /* Advertise 100-BaseTX EEE ability */
3978 if (advertise & ADVERTISED_100baseT_Full)
3979 val |= MDIO_AN_EEE_ADV_100TX;
3980 /* Advertise 1000-BaseT EEE ability */
3981 if (advertise & ADVERTISED_1000baseT_Full)
3982 val |= MDIO_AN_EEE_ADV_1000T;
3983 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3987 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3989 case ASIC_REV_57765:
3990 case ASIC_REV_57766:
3992 /* If we advertised any eee advertisements above... */
3994 val = MII_TG3_DSP_TAP26_ALNOKO |
3995 MII_TG3_DSP_TAP26_RMRXSTO |
3996 MII_TG3_DSP_TAP26_OPCSINPT;
3997 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4000 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4001 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4002 MII_TG3_DSP_CH34TP2_HIBW01);
4005 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
4014 static void tg3_phy_copper_begin(struct tg3 *tp)
4016 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4017 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4020 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
4021 adv = ADVERTISED_10baseT_Half |
4022 ADVERTISED_10baseT_Full;
4023 if (tg3_flag(tp, WOL_SPEED_100MB))
4024 adv |= ADVERTISED_100baseT_Half |
4025 ADVERTISED_100baseT_Full;
4027 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4029 adv = tp->link_config.advertising;
4030 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4031 adv &= ~(ADVERTISED_1000baseT_Half |
4032 ADVERTISED_1000baseT_Full);
4034 fc = tp->link_config.flowctrl;
4037 tg3_phy_autoneg_cfg(tp, adv, fc);
4039 tg3_writephy(tp, MII_BMCR,
4040 BMCR_ANENABLE | BMCR_ANRESTART);
4043 u32 bmcr, orig_bmcr;
4045 tp->link_config.active_speed = tp->link_config.speed;
4046 tp->link_config.active_duplex = tp->link_config.duplex;
4049 switch (tp->link_config.speed) {
4055 bmcr |= BMCR_SPEED100;
4059 bmcr |= BMCR_SPEED1000;
4063 if (tp->link_config.duplex == DUPLEX_FULL)
4064 bmcr |= BMCR_FULLDPLX;
4066 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4067 (bmcr != orig_bmcr)) {
4068 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4069 for (i = 0; i < 1500; i++) {
4073 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4074 tg3_readphy(tp, MII_BMSR, &tmp))
4076 if (!(tmp & BMSR_LSTATUS)) {
4081 tg3_writephy(tp, MII_BMCR, bmcr);
4087 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4091 /* Turn off tap power management. */
4092 /* Set Extended packet length bit */
4093 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4095 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4096 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4097 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4098 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4099 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4106 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4108 u32 advmsk, tgtadv, advertising;
4110 advertising = tp->link_config.advertising;
4111 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4113 advmsk = ADVERTISE_ALL;
4114 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4115 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4116 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4119 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4122 if ((*lcladv & advmsk) != tgtadv)
4125 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4128 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4130 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4134 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4135 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
4136 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4137 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4138 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4140 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4143 if (tg3_ctrl != tgtadv)
4150 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4154 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4157 if (tg3_readphy(tp, MII_STAT1000, &val))
4160 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4163 if (tg3_readphy(tp, MII_LPA, rmtadv))
4166 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4167 tp->link_config.rmt_adv = lpeth;
4172 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4174 int current_link_up;
4176 u32 lcl_adv, rmt_adv;
4184 (MAC_STATUS_SYNC_CHANGED |
4185 MAC_STATUS_CFG_CHANGED |
4186 MAC_STATUS_MI_COMPLETION |
4187 MAC_STATUS_LNKSTATE_CHANGED));
4190 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4192 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4196 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4198 /* Some third-party PHYs need to be reset on link going
4201 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4202 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
4203 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
4204 netif_carrier_ok(tp->dev)) {
4205 tg3_readphy(tp, MII_BMSR, &bmsr);
4206 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4207 !(bmsr & BMSR_LSTATUS))
4213 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4214 tg3_readphy(tp, MII_BMSR, &bmsr);
4215 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4216 !tg3_flag(tp, INIT_COMPLETE))
4219 if (!(bmsr & BMSR_LSTATUS)) {
4220 err = tg3_init_5401phy_dsp(tp);
4224 tg3_readphy(tp, MII_BMSR, &bmsr);
4225 for (i = 0; i < 1000; i++) {
4227 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4228 (bmsr & BMSR_LSTATUS)) {
4234 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4235 TG3_PHY_REV_BCM5401_B0 &&
4236 !(bmsr & BMSR_LSTATUS) &&
4237 tp->link_config.active_speed == SPEED_1000) {
4238 err = tg3_phy_reset(tp);
4240 err = tg3_init_5401phy_dsp(tp);
4245 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4246 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
4247 /* 5701 {A0,B0} CRC bug workaround */
4248 tg3_writephy(tp, 0x15, 0x0a75);
4249 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4250 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4251 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4254 /* Clear pending interrupts... */
4255 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4256 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4258 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4259 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4260 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4261 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
4264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
4265 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4266 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4267 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4269 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4272 current_link_up = 0;
4273 current_speed = SPEED_UNKNOWN;
4274 current_duplex = DUPLEX_UNKNOWN;
4275 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4276 tp->link_config.rmt_adv = 0;
4278 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4279 err = tg3_phy_auxctl_read(tp,
4280 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4282 if (!err && !(val & (1 << 10))) {
4283 tg3_phy_auxctl_write(tp,
4284 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4291 for (i = 0; i < 100; i++) {
4292 tg3_readphy(tp, MII_BMSR, &bmsr);
4293 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4294 (bmsr & BMSR_LSTATUS))
4299 if (bmsr & BMSR_LSTATUS) {
4302 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4303 for (i = 0; i < 2000; i++) {
4305 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4310 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4315 for (i = 0; i < 200; i++) {
4316 tg3_readphy(tp, MII_BMCR, &bmcr);
4317 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4319 if (bmcr && bmcr != 0x7fff)
4327 tp->link_config.active_speed = current_speed;
4328 tp->link_config.active_duplex = current_duplex;
4330 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4331 if ((bmcr & BMCR_ANENABLE) &&
4332 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4333 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4334 current_link_up = 1;
4336 if (!(bmcr & BMCR_ANENABLE) &&
4337 tp->link_config.speed == current_speed &&
4338 tp->link_config.duplex == current_duplex &&
4339 tp->link_config.flowctrl ==
4340 tp->link_config.active_flowctrl) {
4341 current_link_up = 1;
4345 if (current_link_up == 1 &&
4346 tp->link_config.active_duplex == DUPLEX_FULL) {
4349 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4350 reg = MII_TG3_FET_GEN_STAT;
4351 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4353 reg = MII_TG3_EXT_STAT;
4354 bit = MII_TG3_EXT_STAT_MDIX;
4357 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4358 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4360 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4365 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4366 tg3_phy_copper_begin(tp);
4368 tg3_readphy(tp, MII_BMSR, &bmsr);
4369 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4370 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4371 current_link_up = 1;
4374 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4375 if (current_link_up == 1) {
4376 if (tp->link_config.active_speed == SPEED_100 ||
4377 tp->link_config.active_speed == SPEED_10)
4378 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4380 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4381 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4382 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4384 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4386 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4387 if (tp->link_config.active_duplex == DUPLEX_HALF)
4388 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4390 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4391 if (current_link_up == 1 &&
4392 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4393 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4395 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4398 /* ??? Without this setting Netgear GA302T PHY does not
4399 * ??? send/receive packets...
4401 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4402 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4403 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4404 tw32_f(MAC_MI_MODE, tp->mi_mode);
4408 tw32_f(MAC_MODE, tp->mac_mode);
4411 tg3_phy_eee_adjust(tp, current_link_up);
4413 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4414 /* Polled via timer. */
4415 tw32_f(MAC_EVENT, 0);
4417 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4421 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4422 current_link_up == 1 &&
4423 tp->link_config.active_speed == SPEED_1000 &&
4424 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4427 (MAC_STATUS_SYNC_CHANGED |
4428 MAC_STATUS_CFG_CHANGED));
4431 NIC_SRAM_FIRMWARE_MBOX,
4432 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4435 /* Prevent send BD corruption. */
4436 if (tg3_flag(tp, CLKREQ_BUG)) {
4437 u16 oldlnkctl, newlnkctl;
4439 pci_read_config_word(tp->pdev,
4440 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4442 if (tp->link_config.active_speed == SPEED_100 ||
4443 tp->link_config.active_speed == SPEED_10)
4444 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4446 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4447 if (newlnkctl != oldlnkctl)
4448 pci_write_config_word(tp->pdev,
4449 pci_pcie_cap(tp->pdev) +
4450 PCI_EXP_LNKCTL, newlnkctl);
4453 if (current_link_up != netif_carrier_ok(tp->dev)) {
4454 if (current_link_up)
4455 netif_carrier_on(tp->dev);
4457 netif_carrier_off(tp->dev);
4458 tg3_link_report(tp);
4464 struct tg3_fiber_aneginfo {
4466 #define ANEG_STATE_UNKNOWN 0
4467 #define ANEG_STATE_AN_ENABLE 1
4468 #define ANEG_STATE_RESTART_INIT 2
4469 #define ANEG_STATE_RESTART 3
4470 #define ANEG_STATE_DISABLE_LINK_OK 4
4471 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4472 #define ANEG_STATE_ABILITY_DETECT 6
4473 #define ANEG_STATE_ACK_DETECT_INIT 7
4474 #define ANEG_STATE_ACK_DETECT 8
4475 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4476 #define ANEG_STATE_COMPLETE_ACK 10
4477 #define ANEG_STATE_IDLE_DETECT_INIT 11
4478 #define ANEG_STATE_IDLE_DETECT 12
4479 #define ANEG_STATE_LINK_OK 13
4480 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4481 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4484 #define MR_AN_ENABLE 0x00000001
4485 #define MR_RESTART_AN 0x00000002
4486 #define MR_AN_COMPLETE 0x00000004
4487 #define MR_PAGE_RX 0x00000008
4488 #define MR_NP_LOADED 0x00000010
4489 #define MR_TOGGLE_TX 0x00000020
4490 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4491 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4492 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4493 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4494 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4495 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4496 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4497 #define MR_TOGGLE_RX 0x00002000
4498 #define MR_NP_RX 0x00004000
4500 #define MR_LINK_OK 0x80000000
4502 unsigned long link_time, cur_time;
4504 u32 ability_match_cfg;
4505 int ability_match_count;
4507 char ability_match, idle_match, ack_match;
4509 u32 txconfig, rxconfig;
4510 #define ANEG_CFG_NP 0x00000080
4511 #define ANEG_CFG_ACK 0x00000040
4512 #define ANEG_CFG_RF2 0x00000020
4513 #define ANEG_CFG_RF1 0x00000010
4514 #define ANEG_CFG_PS2 0x00000001
4515 #define ANEG_CFG_PS1 0x00008000
4516 #define ANEG_CFG_HD 0x00004000
4517 #define ANEG_CFG_FD 0x00002000
4518 #define ANEG_CFG_INVAL 0x00001f06
4523 #define ANEG_TIMER_ENAB 2
4524 #define ANEG_FAILED -1
4526 #define ANEG_STATE_SETTLE_TIME 10000
4528 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4529 struct tg3_fiber_aneginfo *ap)
4532 unsigned long delta;
4536 if (ap->state == ANEG_STATE_UNKNOWN) {
4540 ap->ability_match_cfg = 0;
4541 ap->ability_match_count = 0;
4542 ap->ability_match = 0;
4548 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4549 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4551 if (rx_cfg_reg != ap->ability_match_cfg) {
4552 ap->ability_match_cfg = rx_cfg_reg;
4553 ap->ability_match = 0;
4554 ap->ability_match_count = 0;
4556 if (++ap->ability_match_count > 1) {
4557 ap->ability_match = 1;
4558 ap->ability_match_cfg = rx_cfg_reg;
4561 if (rx_cfg_reg & ANEG_CFG_ACK)
4569 ap->ability_match_cfg = 0;
4570 ap->ability_match_count = 0;
4571 ap->ability_match = 0;
4577 ap->rxconfig = rx_cfg_reg;
4580 switch (ap->state) {
4581 case ANEG_STATE_UNKNOWN:
4582 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4583 ap->state = ANEG_STATE_AN_ENABLE;
4586 case ANEG_STATE_AN_ENABLE:
4587 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4588 if (ap->flags & MR_AN_ENABLE) {
4591 ap->ability_match_cfg = 0;
4592 ap->ability_match_count = 0;
4593 ap->ability_match = 0;
4597 ap->state = ANEG_STATE_RESTART_INIT;
4599 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4603 case ANEG_STATE_RESTART_INIT:
4604 ap->link_time = ap->cur_time;
4605 ap->flags &= ~(MR_NP_LOADED);
4607 tw32(MAC_TX_AUTO_NEG, 0);
4608 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4609 tw32_f(MAC_MODE, tp->mac_mode);
4612 ret = ANEG_TIMER_ENAB;
4613 ap->state = ANEG_STATE_RESTART;
4616 case ANEG_STATE_RESTART:
4617 delta = ap->cur_time - ap->link_time;
4618 if (delta > ANEG_STATE_SETTLE_TIME)
4619 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4621 ret = ANEG_TIMER_ENAB;
4624 case ANEG_STATE_DISABLE_LINK_OK:
4628 case ANEG_STATE_ABILITY_DETECT_INIT:
4629 ap->flags &= ~(MR_TOGGLE_TX);
4630 ap->txconfig = ANEG_CFG_FD;
4631 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4632 if (flowctrl & ADVERTISE_1000XPAUSE)
4633 ap->txconfig |= ANEG_CFG_PS1;
4634 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4635 ap->txconfig |= ANEG_CFG_PS2;
4636 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4637 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4638 tw32_f(MAC_MODE, tp->mac_mode);
4641 ap->state = ANEG_STATE_ABILITY_DETECT;
4644 case ANEG_STATE_ABILITY_DETECT:
4645 if (ap->ability_match != 0 && ap->rxconfig != 0)
4646 ap->state = ANEG_STATE_ACK_DETECT_INIT;
4649 case ANEG_STATE_ACK_DETECT_INIT:
4650 ap->txconfig |= ANEG_CFG_ACK;
4651 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4652 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4653 tw32_f(MAC_MODE, tp->mac_mode);
4656 ap->state = ANEG_STATE_ACK_DETECT;
4659 case ANEG_STATE_ACK_DETECT:
4660 if (ap->ack_match != 0) {
4661 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4662 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4663 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4665 ap->state = ANEG_STATE_AN_ENABLE;
4667 } else if (ap->ability_match != 0 &&
4668 ap->rxconfig == 0) {
4669 ap->state = ANEG_STATE_AN_ENABLE;
4673 case ANEG_STATE_COMPLETE_ACK_INIT:
4674 if (ap->rxconfig & ANEG_CFG_INVAL) {
4678 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4679 MR_LP_ADV_HALF_DUPLEX |
4680 MR_LP_ADV_SYM_PAUSE |
4681 MR_LP_ADV_ASYM_PAUSE |
4682 MR_LP_ADV_REMOTE_FAULT1 |
4683 MR_LP_ADV_REMOTE_FAULT2 |
4684 MR_LP_ADV_NEXT_PAGE |
4687 if (ap->rxconfig & ANEG_CFG_FD)
4688 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4689 if (ap->rxconfig & ANEG_CFG_HD)
4690 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4691 if (ap->rxconfig & ANEG_CFG_PS1)
4692 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4693 if (ap->rxconfig & ANEG_CFG_PS2)
4694 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4695 if (ap->rxconfig & ANEG_CFG_RF1)
4696 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4697 if (ap->rxconfig & ANEG_CFG_RF2)
4698 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4699 if (ap->rxconfig & ANEG_CFG_NP)
4700 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4702 ap->link_time = ap->cur_time;
4704 ap->flags ^= (MR_TOGGLE_TX);
4705 if (ap->rxconfig & 0x0008)
4706 ap->flags |= MR_TOGGLE_RX;
4707 if (ap->rxconfig & ANEG_CFG_NP)
4708 ap->flags |= MR_NP_RX;
4709 ap->flags |= MR_PAGE_RX;
4711 ap->state = ANEG_STATE_COMPLETE_ACK;
4712 ret = ANEG_TIMER_ENAB;
4715 case ANEG_STATE_COMPLETE_ACK:
4716 if (ap->ability_match != 0 &&
4717 ap->rxconfig == 0) {
4718 ap->state = ANEG_STATE_AN_ENABLE;
4721 delta = ap->cur_time - ap->link_time;
4722 if (delta > ANEG_STATE_SETTLE_TIME) {
4723 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4724 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4726 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4727 !(ap->flags & MR_NP_RX)) {
4728 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4736 case ANEG_STATE_IDLE_DETECT_INIT:
4737 ap->link_time = ap->cur_time;
4738 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4739 tw32_f(MAC_MODE, tp->mac_mode);
4742 ap->state = ANEG_STATE_IDLE_DETECT;
4743 ret = ANEG_TIMER_ENAB;
4746 case ANEG_STATE_IDLE_DETECT:
4747 if (ap->ability_match != 0 &&
4748 ap->rxconfig == 0) {
4749 ap->state = ANEG_STATE_AN_ENABLE;
4752 delta = ap->cur_time - ap->link_time;
4753 if (delta > ANEG_STATE_SETTLE_TIME) {
4754 /* XXX another gem from the Broadcom driver :( */
4755 ap->state = ANEG_STATE_LINK_OK;
4759 case ANEG_STATE_LINK_OK:
4760 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4764 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4765 /* ??? unimplemented */
4768 case ANEG_STATE_NEXT_PAGE_WAIT:
4769 /* ??? unimplemented */
4780 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4783 struct tg3_fiber_aneginfo aninfo;
4784 int status = ANEG_FAILED;
4788 tw32_f(MAC_TX_AUTO_NEG, 0);
4790 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4791 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4794 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4797 memset(&aninfo, 0, sizeof(aninfo));
4798 aninfo.flags |= MR_AN_ENABLE;
4799 aninfo.state = ANEG_STATE_UNKNOWN;
4800 aninfo.cur_time = 0;
4802 while (++tick < 195000) {
4803 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4804 if (status == ANEG_DONE || status == ANEG_FAILED)
4810 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4811 tw32_f(MAC_MODE, tp->mac_mode);
4814 *txflags = aninfo.txconfig;
4815 *rxflags = aninfo.flags;
4817 if (status == ANEG_DONE &&
4818 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4819 MR_LP_ADV_FULL_DUPLEX)))
4825 static void tg3_init_bcm8002(struct tg3 *tp)
4827 u32 mac_status = tr32(MAC_STATUS);
4830 /* Reset when initting first time or we have a link. */
4831 if (tg3_flag(tp, INIT_COMPLETE) &&
4832 !(mac_status & MAC_STATUS_PCS_SYNCED))
4835 /* Set PLL lock range. */
4836 tg3_writephy(tp, 0x16, 0x8007);
4839 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4841 /* Wait for reset to complete. */
4842 /* XXX schedule_timeout() ... */
4843 for (i = 0; i < 500; i++)
4846 /* Config mode; select PMA/Ch 1 regs. */
4847 tg3_writephy(tp, 0x10, 0x8411);
4849 /* Enable auto-lock and comdet, select txclk for tx. */
4850 tg3_writephy(tp, 0x11, 0x0a10);
4852 tg3_writephy(tp, 0x18, 0x00a0);
4853 tg3_writephy(tp, 0x16, 0x41ff);
4855 /* Assert and deassert POR. */
4856 tg3_writephy(tp, 0x13, 0x0400);
4858 tg3_writephy(tp, 0x13, 0x0000);
4860 tg3_writephy(tp, 0x11, 0x0a50);
4862 tg3_writephy(tp, 0x11, 0x0a10);
4864 /* Wait for signal to stabilize */
4865 /* XXX schedule_timeout() ... */
4866 for (i = 0; i < 15000; i++)
4869 /* Deselect the channel register so we can read the PHYID
4872 tg3_writephy(tp, 0x10, 0x8011);
4875 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4878 u32 sg_dig_ctrl, sg_dig_status;
4879 u32 serdes_cfg, expected_sg_dig_ctrl;
4880 int workaround, port_a;
4881 int current_link_up;
4884 expected_sg_dig_ctrl = 0;
4887 current_link_up = 0;
4889 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4890 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4892 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4895 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4896 /* preserve bits 20-23 for voltage regulator */
4897 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4900 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4902 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4903 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4905 u32 val = serdes_cfg;
4911 tw32_f(MAC_SERDES_CFG, val);
4914 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4916 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4917 tg3_setup_flow_control(tp, 0, 0);
4918 current_link_up = 1;
4923 /* Want auto-negotiation. */
4924 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4926 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4927 if (flowctrl & ADVERTISE_1000XPAUSE)
4928 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4929 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4930 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4932 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4933 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4934 tp->serdes_counter &&
4935 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4936 MAC_STATUS_RCVD_CFG)) ==
4937 MAC_STATUS_PCS_SYNCED)) {
4938 tp->serdes_counter--;
4939 current_link_up = 1;
4944 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4945 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4947 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4949 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4950 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4951 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4952 MAC_STATUS_SIGNAL_DET)) {
4953 sg_dig_status = tr32(SG_DIG_STATUS);
4954 mac_status = tr32(MAC_STATUS);
4956 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4957 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4958 u32 local_adv = 0, remote_adv = 0;
4960 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4961 local_adv |= ADVERTISE_1000XPAUSE;
4962 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4963 local_adv |= ADVERTISE_1000XPSE_ASYM;
4965 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4966 remote_adv |= LPA_1000XPAUSE;
4967 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4968 remote_adv |= LPA_1000XPAUSE_ASYM;
4970 tp->link_config.rmt_adv =
4971 mii_adv_to_ethtool_adv_x(remote_adv);
4973 tg3_setup_flow_control(tp, local_adv, remote_adv);
4974 current_link_up = 1;
4975 tp->serdes_counter = 0;
4976 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4977 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4978 if (tp->serdes_counter)
4979 tp->serdes_counter--;
4982 u32 val = serdes_cfg;
4989 tw32_f(MAC_SERDES_CFG, val);
4992 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4995 /* Link parallel detection - link is up */
4996 /* only if we have PCS_SYNC and not */
4997 /* receiving config code words */
4998 mac_status = tr32(MAC_STATUS);
4999 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5000 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5001 tg3_setup_flow_control(tp, 0, 0);
5002 current_link_up = 1;
5004 TG3_PHYFLG_PARALLEL_DETECT;
5005 tp->serdes_counter =
5006 SERDES_PARALLEL_DET_TIMEOUT;
5008 goto restart_autoneg;
5012 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5013 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5017 return current_link_up;
5020 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5022 int current_link_up = 0;
5024 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5027 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5028 u32 txflags, rxflags;
5031 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5032 u32 local_adv = 0, remote_adv = 0;
5034 if (txflags & ANEG_CFG_PS1)
5035 local_adv |= ADVERTISE_1000XPAUSE;
5036 if (txflags & ANEG_CFG_PS2)
5037 local_adv |= ADVERTISE_1000XPSE_ASYM;
5039 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5040 remote_adv |= LPA_1000XPAUSE;
5041 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5042 remote_adv |= LPA_1000XPAUSE_ASYM;
5044 tp->link_config.rmt_adv =
5045 mii_adv_to_ethtool_adv_x(remote_adv);
5047 tg3_setup_flow_control(tp, local_adv, remote_adv);
5049 current_link_up = 1;
5051 for (i = 0; i < 30; i++) {
5054 (MAC_STATUS_SYNC_CHANGED |
5055 MAC_STATUS_CFG_CHANGED));
5057 if ((tr32(MAC_STATUS) &
5058 (MAC_STATUS_SYNC_CHANGED |
5059 MAC_STATUS_CFG_CHANGED)) == 0)
5063 mac_status = tr32(MAC_STATUS);
5064 if (current_link_up == 0 &&
5065 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5066 !(mac_status & MAC_STATUS_RCVD_CFG))
5067 current_link_up = 1;
5069 tg3_setup_flow_control(tp, 0, 0);
5071 /* Forcing 1000FD link up. */
5072 current_link_up = 1;
5074 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5077 tw32_f(MAC_MODE, tp->mac_mode);
5082 return current_link_up;
5085 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
5088 u16 orig_active_speed;
5089 u8 orig_active_duplex;
5091 int current_link_up;
5094 orig_pause_cfg = tp->link_config.active_flowctrl;
5095 orig_active_speed = tp->link_config.active_speed;
5096 orig_active_duplex = tp->link_config.active_duplex;
5098 if (!tg3_flag(tp, HW_AUTONEG) &&
5099 netif_carrier_ok(tp->dev) &&
5100 tg3_flag(tp, INIT_COMPLETE)) {
5101 mac_status = tr32(MAC_STATUS);
5102 mac_status &= (MAC_STATUS_PCS_SYNCED |
5103 MAC_STATUS_SIGNAL_DET |
5104 MAC_STATUS_CFG_CHANGED |
5105 MAC_STATUS_RCVD_CFG);
5106 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5107 MAC_STATUS_SIGNAL_DET)) {
5108 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5109 MAC_STATUS_CFG_CHANGED));
5114 tw32_f(MAC_TX_AUTO_NEG, 0);
5116 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5117 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5118 tw32_f(MAC_MODE, tp->mac_mode);
5121 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5122 tg3_init_bcm8002(tp);
5124 /* Enable link change event even when serdes polling. */
5125 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5128 current_link_up = 0;
5129 tp->link_config.rmt_adv = 0;
5130 mac_status = tr32(MAC_STATUS);
5132 if (tg3_flag(tp, HW_AUTONEG))
5133 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5135 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5137 tp->napi[0].hw_status->status =
5138 (SD_STATUS_UPDATED |
5139 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5141 for (i = 0; i < 100; i++) {
5142 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5143 MAC_STATUS_CFG_CHANGED));
5145 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5146 MAC_STATUS_CFG_CHANGED |
5147 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5151 mac_status = tr32(MAC_STATUS);
5152 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5153 current_link_up = 0;
5154 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5155 tp->serdes_counter == 0) {
5156 tw32_f(MAC_MODE, (tp->mac_mode |
5157 MAC_MODE_SEND_CONFIGS));
5159 tw32_f(MAC_MODE, tp->mac_mode);
5163 if (current_link_up == 1) {
5164 tp->link_config.active_speed = SPEED_1000;
5165 tp->link_config.active_duplex = DUPLEX_FULL;
5166 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5167 LED_CTRL_LNKLED_OVERRIDE |
5168 LED_CTRL_1000MBPS_ON));
5170 tp->link_config.active_speed = SPEED_UNKNOWN;
5171 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5172 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5173 LED_CTRL_LNKLED_OVERRIDE |
5174 LED_CTRL_TRAFFIC_OVERRIDE));
5177 if (current_link_up != netif_carrier_ok(tp->dev)) {
5178 if (current_link_up)
5179 netif_carrier_on(tp->dev);
5181 netif_carrier_off(tp->dev);
5182 tg3_link_report(tp);
5184 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5185 if (orig_pause_cfg != now_pause_cfg ||
5186 orig_active_speed != tp->link_config.active_speed ||
5187 orig_active_duplex != tp->link_config.active_duplex)
5188 tg3_link_report(tp);
5194 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
5196 int current_link_up, err = 0;
5200 u32 local_adv, remote_adv;
5202 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5203 tw32_f(MAC_MODE, tp->mac_mode);
5209 (MAC_STATUS_SYNC_CHANGED |
5210 MAC_STATUS_CFG_CHANGED |
5211 MAC_STATUS_MI_COMPLETION |
5212 MAC_STATUS_LNKSTATE_CHANGED));
5218 current_link_up = 0;
5219 current_speed = SPEED_UNKNOWN;
5220 current_duplex = DUPLEX_UNKNOWN;
5221 tp->link_config.rmt_adv = 0;
5223 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5224 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
5226 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5227 bmsr |= BMSR_LSTATUS;
5229 bmsr &= ~BMSR_LSTATUS;
5232 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5234 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5235 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5236 /* do nothing, just check for link up at the end */
5237 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5240 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5241 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5242 ADVERTISE_1000XPAUSE |
5243 ADVERTISE_1000XPSE_ASYM |
5246 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5247 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5249 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5250 tg3_writephy(tp, MII_ADVERTISE, newadv);
5251 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5252 tg3_writephy(tp, MII_BMCR, bmcr);
5254 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5255 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5256 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5263 bmcr &= ~BMCR_SPEED1000;
5264 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5266 if (tp->link_config.duplex == DUPLEX_FULL)
5267 new_bmcr |= BMCR_FULLDPLX;
5269 if (new_bmcr != bmcr) {
5270 /* BMCR_SPEED1000 is a reserved bit that needs
5271 * to be set on write.
5273 new_bmcr |= BMCR_SPEED1000;
5275 /* Force a linkdown */
5276 if (netif_carrier_ok(tp->dev)) {
5279 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5280 adv &= ~(ADVERTISE_1000XFULL |
5281 ADVERTISE_1000XHALF |
5283 tg3_writephy(tp, MII_ADVERTISE, adv);
5284 tg3_writephy(tp, MII_BMCR, bmcr |
5288 netif_carrier_off(tp->dev);
5290 tg3_writephy(tp, MII_BMCR, new_bmcr);
5292 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5293 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5294 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
5296 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5297 bmsr |= BMSR_LSTATUS;
5299 bmsr &= ~BMSR_LSTATUS;
5301 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5305 if (bmsr & BMSR_LSTATUS) {
5306 current_speed = SPEED_1000;
5307 current_link_up = 1;
5308 if (bmcr & BMCR_FULLDPLX)
5309 current_duplex = DUPLEX_FULL;
5311 current_duplex = DUPLEX_HALF;
5316 if (bmcr & BMCR_ANENABLE) {
5319 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5320 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5321 common = local_adv & remote_adv;
5322 if (common & (ADVERTISE_1000XHALF |
5323 ADVERTISE_1000XFULL)) {
5324 if (common & ADVERTISE_1000XFULL)
5325 current_duplex = DUPLEX_FULL;
5327 current_duplex = DUPLEX_HALF;
5329 tp->link_config.rmt_adv =
5330 mii_adv_to_ethtool_adv_x(remote_adv);
5331 } else if (!tg3_flag(tp, 5780_CLASS)) {
5332 /* Link is up via parallel detect */
5334 current_link_up = 0;
5339 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5340 tg3_setup_flow_control(tp, local_adv, remote_adv);
5342 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5343 if (tp->link_config.active_duplex == DUPLEX_HALF)
5344 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5346 tw32_f(MAC_MODE, tp->mac_mode);
5349 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5351 tp->link_config.active_speed = current_speed;
5352 tp->link_config.active_duplex = current_duplex;
5354 if (current_link_up != netif_carrier_ok(tp->dev)) {
5355 if (current_link_up)
5356 netif_carrier_on(tp->dev);
5358 netif_carrier_off(tp->dev);
5359 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5361 tg3_link_report(tp);
5366 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5368 if (tp->serdes_counter) {
5369 /* Give autoneg time to complete. */
5370 tp->serdes_counter--;
5374 if (!netif_carrier_ok(tp->dev) &&
5375 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5378 tg3_readphy(tp, MII_BMCR, &bmcr);
5379 if (bmcr & BMCR_ANENABLE) {
5382 /* Select shadow register 0x1f */
5383 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5384 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5386 /* Select expansion interrupt status register */
5387 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5388 MII_TG3_DSP_EXP1_INT_STAT);
5389 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5390 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5392 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5393 /* We have signal detect and not receiving
5394 * config code words, link is up by parallel
5398 bmcr &= ~BMCR_ANENABLE;
5399 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5400 tg3_writephy(tp, MII_BMCR, bmcr);
5401 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5404 } else if (netif_carrier_ok(tp->dev) &&
5405 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5406 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5409 /* Select expansion interrupt status register */
5410 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5411 MII_TG3_DSP_EXP1_INT_STAT);
5412 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5416 /* Config code words received, turn on autoneg. */
5417 tg3_readphy(tp, MII_BMCR, &bmcr);
5418 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5420 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5426 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5431 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5432 err = tg3_setup_fiber_phy(tp, force_reset);
5433 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5434 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5436 err = tg3_setup_copper_phy(tp, force_reset);
5438 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5441 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5442 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5444 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5449 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5450 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5451 tw32(GRC_MISC_CFG, val);
5454 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5455 (6 << TX_LENGTHS_IPG_SHIFT);
5456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5457 val |= tr32(MAC_TX_LENGTHS) &
5458 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5459 TX_LENGTHS_CNT_DWN_VAL_MSK);
5461 if (tp->link_config.active_speed == SPEED_1000 &&
5462 tp->link_config.active_duplex == DUPLEX_HALF)
5463 tw32(MAC_TX_LENGTHS, val |
5464 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5466 tw32(MAC_TX_LENGTHS, val |
5467 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5469 if (!tg3_flag(tp, 5705_PLUS)) {
5470 if (netif_carrier_ok(tp->dev)) {
5471 tw32(HOSTCC_STAT_COAL_TICKS,
5472 tp->coal.stats_block_coalesce_usecs);
5474 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5478 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5479 val = tr32(PCIE_PWR_MGMT_THRESH);
5480 if (!netif_carrier_ok(tp->dev))
5481 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5484 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5485 tw32(PCIE_PWR_MGMT_THRESH, val);
5491 static inline int tg3_irq_sync(struct tg3 *tp)
5493 return tp->irq_sync;
5496 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5500 dst = (u32 *)((u8 *)dst + off);
5501 for (i = 0; i < len; i += sizeof(u32))
5502 *dst++ = tr32(off + i);
5505 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5507 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5508 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5509 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5510 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5511 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5512 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5513 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5514 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5515 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5516 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5517 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5518 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5519 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5520 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5521 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5522 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5523 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5524 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5525 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5527 if (tg3_flag(tp, SUPPORT_MSIX))
5528 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5530 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5531 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5532 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5533 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5534 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5535 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5536 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5537 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5539 if (!tg3_flag(tp, 5705_PLUS)) {
5540 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5541 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5542 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5545 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5546 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5547 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5548 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5549 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5551 if (tg3_flag(tp, NVRAM))
5552 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5555 static void tg3_dump_state(struct tg3 *tp)
5560 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5562 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5566 if (tg3_flag(tp, PCI_EXPRESS)) {
5567 /* Read up to but not including private PCI registers */
5568 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5569 regs[i / sizeof(u32)] = tr32(i);
5571 tg3_dump_legacy_regs(tp, regs);
5573 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5574 if (!regs[i + 0] && !regs[i + 1] &&
5575 !regs[i + 2] && !regs[i + 3])
5578 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5580 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5585 for (i = 0; i < tp->irq_cnt; i++) {
5586 struct tg3_napi *tnapi = &tp->napi[i];
5588 /* SW status block */
5590 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5592 tnapi->hw_status->status,
5593 tnapi->hw_status->status_tag,
5594 tnapi->hw_status->rx_jumbo_consumer,
5595 tnapi->hw_status->rx_consumer,
5596 tnapi->hw_status->rx_mini_consumer,
5597 tnapi->hw_status->idx[0].rx_producer,
5598 tnapi->hw_status->idx[0].tx_consumer);
5601 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5603 tnapi->last_tag, tnapi->last_irq_tag,
5604 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5606 tnapi->prodring.rx_std_prod_idx,
5607 tnapi->prodring.rx_std_cons_idx,
5608 tnapi->prodring.rx_jmb_prod_idx,
5609 tnapi->prodring.rx_jmb_cons_idx);
5613 /* This is called whenever we suspect that the system chipset is re-
5614 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5615 * is bogus tx completions. We try to recover by setting the
5616 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5619 static void tg3_tx_recover(struct tg3 *tp)
5621 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5622 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5624 netdev_warn(tp->dev,
5625 "The system may be re-ordering memory-mapped I/O "
5626 "cycles to the network device, attempting to recover. "
5627 "Please report the problem to the driver maintainer "
5628 "and include system chipset information.\n");
5630 spin_lock(&tp->lock);
5631 tg3_flag_set(tp, TX_RECOVERY_PENDING);
5632 spin_unlock(&tp->lock);
5635 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5637 /* Tell compiler to fetch tx indices from memory. */
5639 return tnapi->tx_pending -
5640 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5643 /* Tigon3 never reports partial packet sends. So we do not
5644 * need special logic to handle SKBs that have not had all
5645 * of their frags sent yet, like SunGEM does.
5647 static void tg3_tx(struct tg3_napi *tnapi)
5649 struct tg3 *tp = tnapi->tp;
5650 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5651 u32 sw_idx = tnapi->tx_cons;
5652 struct netdev_queue *txq;
5653 int index = tnapi - tp->napi;
5654 unsigned int pkts_compl = 0, bytes_compl = 0;
5656 if (tg3_flag(tp, ENABLE_TSS))
5659 txq = netdev_get_tx_queue(tp->dev, index);
5661 while (sw_idx != hw_idx) {
5662 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5663 struct sk_buff *skb = ri->skb;
5666 if (unlikely(skb == NULL)) {
5671 pci_unmap_single(tp->pdev,
5672 dma_unmap_addr(ri, mapping),
5678 while (ri->fragmented) {
5679 ri->fragmented = false;
5680 sw_idx = NEXT_TX(sw_idx);
5681 ri = &tnapi->tx_buffers[sw_idx];
5684 sw_idx = NEXT_TX(sw_idx);
5686 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5687 ri = &tnapi->tx_buffers[sw_idx];
5688 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5691 pci_unmap_page(tp->pdev,
5692 dma_unmap_addr(ri, mapping),
5693 skb_frag_size(&skb_shinfo(skb)->frags[i]),
5696 while (ri->fragmented) {
5697 ri->fragmented = false;
5698 sw_idx = NEXT_TX(sw_idx);
5699 ri = &tnapi->tx_buffers[sw_idx];
5702 sw_idx = NEXT_TX(sw_idx);
5706 bytes_compl += skb->len;
5710 if (unlikely(tx_bug)) {
5716 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
5718 tnapi->tx_cons = sw_idx;
5720 /* Need to make the tx_cons update visible to tg3_start_xmit()
5721 * before checking for netif_queue_stopped(). Without the
5722 * memory barrier, there is a small possibility that tg3_start_xmit()
5723 * will miss it and cause the queue to be stopped forever.
5727 if (unlikely(netif_tx_queue_stopped(txq) &&
5728 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5729 __netif_tx_lock(txq, smp_processor_id());
5730 if (netif_tx_queue_stopped(txq) &&
5731 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5732 netif_tx_wake_queue(txq);
5733 __netif_tx_unlock(txq);
5737 static void tg3_frag_free(bool is_frag, void *data)
5740 put_page(virt_to_head_page(data));
5745 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5747 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
5748 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5753 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5754 map_sz, PCI_DMA_FROMDEVICE);
5755 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
5760 /* Returns size of skb allocated or < 0 on error.
5762 * We only need to fill in the address because the other members
5763 * of the RX descriptor are invariant, see tg3_init_rings.
5765 * Note the purposeful assymetry of cpu vs. chip accesses. For
5766 * posting buffers we only dirty the first cache line of the RX
5767 * descriptor (containing the address). Whereas for the RX status
5768 * buffers the cpu only reads the last cacheline of the RX descriptor
5769 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5771 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5772 u32 opaque_key, u32 dest_idx_unmasked,
5773 unsigned int *frag_size)
5775 struct tg3_rx_buffer_desc *desc;
5776 struct ring_info *map;
5779 int skb_size, data_size, dest_idx;
5781 switch (opaque_key) {
5782 case RXD_OPAQUE_RING_STD:
5783 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5784 desc = &tpr->rx_std[dest_idx];
5785 map = &tpr->rx_std_buffers[dest_idx];
5786 data_size = tp->rx_pkt_map_sz;
5789 case RXD_OPAQUE_RING_JUMBO:
5790 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5791 desc = &tpr->rx_jmb[dest_idx].std;
5792 map = &tpr->rx_jmb_buffers[dest_idx];
5793 data_size = TG3_RX_JMB_MAP_SZ;
5800 /* Do not overwrite any of the map or rp information
5801 * until we are sure we can commit to a new buffer.
5803 * Callers depend upon this behavior and assume that
5804 * we leave everything unchanged if we fail.
5806 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
5807 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5808 if (skb_size <= PAGE_SIZE) {
5809 data = netdev_alloc_frag(skb_size);
5810 *frag_size = skb_size;
5812 data = kmalloc(skb_size, GFP_ATOMIC);
5818 mapping = pci_map_single(tp->pdev,
5819 data + TG3_RX_OFFSET(tp),
5821 PCI_DMA_FROMDEVICE);
5822 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
5823 tg3_frag_free(skb_size <= PAGE_SIZE, data);
5828 dma_unmap_addr_set(map, mapping, mapping);
5830 desc->addr_hi = ((u64)mapping >> 32);
5831 desc->addr_lo = ((u64)mapping & 0xffffffff);
5836 /* We only need to move over in the address because the other
5837 * members of the RX descriptor are invariant. See notes above
5838 * tg3_alloc_rx_data for full details.
5840 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5841 struct tg3_rx_prodring_set *dpr,
5842 u32 opaque_key, int src_idx,
5843 u32 dest_idx_unmasked)
5845 struct tg3 *tp = tnapi->tp;
5846 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5847 struct ring_info *src_map, *dest_map;
5848 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5851 switch (opaque_key) {
5852 case RXD_OPAQUE_RING_STD:
5853 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5854 dest_desc = &dpr->rx_std[dest_idx];
5855 dest_map = &dpr->rx_std_buffers[dest_idx];
5856 src_desc = &spr->rx_std[src_idx];
5857 src_map = &spr->rx_std_buffers[src_idx];
5860 case RXD_OPAQUE_RING_JUMBO:
5861 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5862 dest_desc = &dpr->rx_jmb[dest_idx].std;
5863 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5864 src_desc = &spr->rx_jmb[src_idx].std;
5865 src_map = &spr->rx_jmb_buffers[src_idx];
5872 dest_map->data = src_map->data;
5873 dma_unmap_addr_set(dest_map, mapping,
5874 dma_unmap_addr(src_map, mapping));
5875 dest_desc->addr_hi = src_desc->addr_hi;
5876 dest_desc->addr_lo = src_desc->addr_lo;
5878 /* Ensure that the update to the skb happens after the physical
5879 * addresses have been transferred to the new BD location.
5883 src_map->data = NULL;
5886 /* The RX ring scheme is composed of multiple rings which post fresh
5887 * buffers to the chip, and one special ring the chip uses to report
5888 * status back to the host.
5890 * The special ring reports the status of received packets to the
5891 * host. The chip does not write into the original descriptor the
5892 * RX buffer was obtained from. The chip simply takes the original
5893 * descriptor as provided by the host, updates the status and length
5894 * field, then writes this into the next status ring entry.
5896 * Each ring the host uses to post buffers to the chip is described
5897 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5898 * it is first placed into the on-chip ram. When the packet's length
5899 * is known, it walks down the TG3_BDINFO entries to select the ring.
5900 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5901 * which is within the range of the new packet's length is chosen.
5903 * The "separate ring for rx status" scheme may sound queer, but it makes
5904 * sense from a cache coherency perspective. If only the host writes
5905 * to the buffer post rings, and only the chip writes to the rx status
5906 * rings, then cache lines never move beyond shared-modified state.
5907 * If both the host and chip were to write into the same ring, cache line
5908 * eviction could occur since both entities want it in an exclusive state.
5910 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5912 struct tg3 *tp = tnapi->tp;
5913 u32 work_mask, rx_std_posted = 0;
5914 u32 std_prod_idx, jmb_prod_idx;
5915 u32 sw_idx = tnapi->rx_rcb_ptr;
5918 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5920 hw_idx = *(tnapi->rx_rcb_prod_idx);
5922 * We need to order the read of hw_idx and the read of
5923 * the opaque cookie.
5928 std_prod_idx = tpr->rx_std_prod_idx;
5929 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5930 while (sw_idx != hw_idx && budget > 0) {
5931 struct ring_info *ri;
5932 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5934 struct sk_buff *skb;
5935 dma_addr_t dma_addr;
5936 u32 opaque_key, desc_idx, *post_ptr;
5939 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5940 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5941 if (opaque_key == RXD_OPAQUE_RING_STD) {
5942 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5943 dma_addr = dma_unmap_addr(ri, mapping);
5945 post_ptr = &std_prod_idx;
5947 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5948 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5949 dma_addr = dma_unmap_addr(ri, mapping);
5951 post_ptr = &jmb_prod_idx;
5953 goto next_pkt_nopost;
5955 work_mask |= opaque_key;
5957 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5958 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5960 tg3_recycle_rx(tnapi, tpr, opaque_key,
5961 desc_idx, *post_ptr);
5963 /* Other statistics kept track of by card. */
5968 prefetch(data + TG3_RX_OFFSET(tp));
5969 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5972 if (len > TG3_RX_COPY_THRESH(tp)) {
5974 unsigned int frag_size;
5976 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
5977 *post_ptr, &frag_size);
5981 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5982 PCI_DMA_FROMDEVICE);
5984 skb = build_skb(data, frag_size);
5986 tg3_frag_free(frag_size != 0, data);
5987 goto drop_it_no_recycle;
5989 skb_reserve(skb, TG3_RX_OFFSET(tp));
5990 /* Ensure that the update to the data happens
5991 * after the usage of the old DMA mapping.
5998 tg3_recycle_rx(tnapi, tpr, opaque_key,
5999 desc_idx, *post_ptr);
6001 skb = netdev_alloc_skb(tp->dev,
6002 len + TG3_RAW_IP_ALIGN);
6004 goto drop_it_no_recycle;
6006 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6007 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6009 data + TG3_RX_OFFSET(tp),
6011 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6015 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6016 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6017 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6018 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6019 skb->ip_summed = CHECKSUM_UNNECESSARY;
6021 skb_checksum_none_assert(skb);
6023 skb->protocol = eth_type_trans(skb, tp->dev);
6025 if (len > (tp->dev->mtu + ETH_HLEN) &&
6026 skb->protocol != htons(ETH_P_8021Q)) {
6028 goto drop_it_no_recycle;
6031 if (desc->type_flags & RXD_FLAG_VLAN &&
6032 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6033 __vlan_hwaccel_put_tag(skb,
6034 desc->err_vlan & RXD_VLAN_MASK);
6036 napi_gro_receive(&tnapi->napi, skb);
6044 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6045 tpr->rx_std_prod_idx = std_prod_idx &
6046 tp->rx_std_ring_mask;
6047 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6048 tpr->rx_std_prod_idx);
6049 work_mask &= ~RXD_OPAQUE_RING_STD;
6054 sw_idx &= tp->rx_ret_ring_mask;
6056 /* Refresh hw_idx to see if there is new work */
6057 if (sw_idx == hw_idx) {
6058 hw_idx = *(tnapi->rx_rcb_prod_idx);
6063 /* ACK the status ring. */
6064 tnapi->rx_rcb_ptr = sw_idx;
6065 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6067 /* Refill RX ring(s). */
6068 if (!tg3_flag(tp, ENABLE_RSS)) {
6069 /* Sync BD data before updating mailbox */
6072 if (work_mask & RXD_OPAQUE_RING_STD) {
6073 tpr->rx_std_prod_idx = std_prod_idx &
6074 tp->rx_std_ring_mask;
6075 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6076 tpr->rx_std_prod_idx);
6078 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6079 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6080 tp->rx_jmb_ring_mask;
6081 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6082 tpr->rx_jmb_prod_idx);
6085 } else if (work_mask) {
6086 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6087 * updated before the producer indices can be updated.
6091 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6092 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6094 if (tnapi != &tp->napi[1]) {
6095 tp->rx_refill = true;
6096 napi_schedule(&tp->napi[1].napi);
6103 static void tg3_poll_link(struct tg3 *tp)
6105 /* handle link change and other phy events */
6106 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
6107 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6109 if (sblk->status & SD_STATUS_LINK_CHG) {
6110 sblk->status = SD_STATUS_UPDATED |
6111 (sblk->status & ~SD_STATUS_LINK_CHG);
6112 spin_lock(&tp->lock);
6113 if (tg3_flag(tp, USE_PHYLIB)) {
6115 (MAC_STATUS_SYNC_CHANGED |
6116 MAC_STATUS_CFG_CHANGED |
6117 MAC_STATUS_MI_COMPLETION |
6118 MAC_STATUS_LNKSTATE_CHANGED));
6121 tg3_setup_phy(tp, 0);
6122 spin_unlock(&tp->lock);
6127 static int tg3_rx_prodring_xfer(struct tg3 *tp,
6128 struct tg3_rx_prodring_set *dpr,
6129 struct tg3_rx_prodring_set *spr)
6131 u32 si, di, cpycnt, src_prod_idx;
6135 src_prod_idx = spr->rx_std_prod_idx;
6137 /* Make sure updates to the rx_std_buffers[] entries and the
6138 * standard producer index are seen in the correct order.
6142 if (spr->rx_std_cons_idx == src_prod_idx)
6145 if (spr->rx_std_cons_idx < src_prod_idx)
6146 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
6148 cpycnt = tp->rx_std_ring_mask + 1 -
6149 spr->rx_std_cons_idx;
6151 cpycnt = min(cpycnt,
6152 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
6154 si = spr->rx_std_cons_idx;
6155 di = dpr->rx_std_prod_idx;
6157 for (i = di; i < di + cpycnt; i++) {
6158 if (dpr->rx_std_buffers[i].data) {
6168 /* Ensure that updates to the rx_std_buffers ring and the
6169 * shadowed hardware producer ring from tg3_recycle_skb() are
6170 * ordered correctly WRT the skb check above.
6174 memcpy(&dpr->rx_std_buffers[di],
6175 &spr->rx_std_buffers[si],
6176 cpycnt * sizeof(struct ring_info));
6178 for (i = 0; i < cpycnt; i++, di++, si++) {
6179 struct tg3_rx_buffer_desc *sbd, *dbd;
6180 sbd = &spr->rx_std[si];
6181 dbd = &dpr->rx_std[di];
6182 dbd->addr_hi = sbd->addr_hi;
6183 dbd->addr_lo = sbd->addr_lo;
6186 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
6187 tp->rx_std_ring_mask;
6188 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
6189 tp->rx_std_ring_mask;
6193 src_prod_idx = spr->rx_jmb_prod_idx;
6195 /* Make sure updates to the rx_jmb_buffers[] entries and
6196 * the jumbo producer index are seen in the correct order.
6200 if (spr->rx_jmb_cons_idx == src_prod_idx)
6203 if (spr->rx_jmb_cons_idx < src_prod_idx)
6204 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
6206 cpycnt = tp->rx_jmb_ring_mask + 1 -
6207 spr->rx_jmb_cons_idx;
6209 cpycnt = min(cpycnt,
6210 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
6212 si = spr->rx_jmb_cons_idx;
6213 di = dpr->rx_jmb_prod_idx;
6215 for (i = di; i < di + cpycnt; i++) {
6216 if (dpr->rx_jmb_buffers[i].data) {
6226 /* Ensure that updates to the rx_jmb_buffers ring and the
6227 * shadowed hardware producer ring from tg3_recycle_skb() are
6228 * ordered correctly WRT the skb check above.
6232 memcpy(&dpr->rx_jmb_buffers[di],
6233 &spr->rx_jmb_buffers[si],
6234 cpycnt * sizeof(struct ring_info));
6236 for (i = 0; i < cpycnt; i++, di++, si++) {
6237 struct tg3_rx_buffer_desc *sbd, *dbd;
6238 sbd = &spr->rx_jmb[si].std;
6239 dbd = &dpr->rx_jmb[di].std;
6240 dbd->addr_hi = sbd->addr_hi;
6241 dbd->addr_lo = sbd->addr_lo;
6244 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
6245 tp->rx_jmb_ring_mask;
6246 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
6247 tp->rx_jmb_ring_mask;
6253 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
6255 struct tg3 *tp = tnapi->tp;
6257 /* run TX completion thread */
6258 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
6260 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6264 if (!tnapi->rx_rcb_prod_idx)
6267 /* run RX thread, within the bounds set by NAPI.
6268 * All RX "locking" is done by ensuring outside
6269 * code synchronizes with tg3->napi.poll()
6271 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
6272 work_done += tg3_rx(tnapi, budget - work_done);
6274 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
6275 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
6277 u32 std_prod_idx = dpr->rx_std_prod_idx;
6278 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
6280 tp->rx_refill = false;
6281 for (i = 1; i <= tp->rxq_cnt; i++)
6282 err |= tg3_rx_prodring_xfer(tp, dpr,
6283 &tp->napi[i].prodring);
6287 if (std_prod_idx != dpr->rx_std_prod_idx)
6288 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6289 dpr->rx_std_prod_idx);
6291 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
6292 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6293 dpr->rx_jmb_prod_idx);
6298 tw32_f(HOSTCC_MODE, tp->coal_now);
6304 static inline void tg3_reset_task_schedule(struct tg3 *tp)
6306 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
6307 schedule_work(&tp->reset_task);
6310 static inline void tg3_reset_task_cancel(struct tg3 *tp)
6312 cancel_work_sync(&tp->reset_task);
6313 tg3_flag_clear(tp, RESET_TASK_PENDING);
6314 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
6317 static int tg3_poll_msix(struct napi_struct *napi, int budget)
6319 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6320 struct tg3 *tp = tnapi->tp;
6322 struct tg3_hw_status *sblk = tnapi->hw_status;
6325 work_done = tg3_poll_work(tnapi, work_done, budget);
6327 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6330 if (unlikely(work_done >= budget))
6333 /* tp->last_tag is used in tg3_int_reenable() below
6334 * to tell the hw how much work has been processed,
6335 * so we must read it before checking for more work.
6337 tnapi->last_tag = sblk->status_tag;
6338 tnapi->last_irq_tag = tnapi->last_tag;
6341 /* check for RX/TX work to do */
6342 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
6343 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
6345 /* This test here is not race free, but will reduce
6346 * the number of interrupts by looping again.
6348 if (tnapi == &tp->napi[1] && tp->rx_refill)
6351 napi_complete(napi);
6352 /* Reenable interrupts. */
6353 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
6355 /* This test here is synchronized by napi_schedule()
6356 * and napi_complete() to close the race condition.
6358 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
6359 tw32(HOSTCC_MODE, tp->coalesce_mode |
6360 HOSTCC_MODE_ENABLE |
6371 /* work_done is guaranteed to be less than budget. */
6372 napi_complete(napi);
6373 tg3_reset_task_schedule(tp);
6377 static void tg3_process_error(struct tg3 *tp)
6380 bool real_error = false;
6382 if (tg3_flag(tp, ERROR_PROCESSED))
6385 /* Check Flow Attention register */
6386 val = tr32(HOSTCC_FLOW_ATTN);
6387 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
6388 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
6392 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
6393 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
6397 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
6398 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6407 tg3_flag_set(tp, ERROR_PROCESSED);
6408 tg3_reset_task_schedule(tp);
6411 static int tg3_poll(struct napi_struct *napi, int budget)
6413 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6414 struct tg3 *tp = tnapi->tp;
6416 struct tg3_hw_status *sblk = tnapi->hw_status;
6419 if (sblk->status & SD_STATUS_ERROR)
6420 tg3_process_error(tp);
6424 work_done = tg3_poll_work(tnapi, work_done, budget);
6426 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6429 if (unlikely(work_done >= budget))
6432 if (tg3_flag(tp, TAGGED_STATUS)) {
6433 /* tp->last_tag is used in tg3_int_reenable() below
6434 * to tell the hw how much work has been processed,
6435 * so we must read it before checking for more work.
6437 tnapi->last_tag = sblk->status_tag;
6438 tnapi->last_irq_tag = tnapi->last_tag;
6441 sblk->status &= ~SD_STATUS_UPDATED;
6443 if (likely(!tg3_has_work(tnapi))) {
6444 napi_complete(napi);
6445 tg3_int_reenable(tnapi);
6453 /* work_done is guaranteed to be less than budget. */
6454 napi_complete(napi);
6455 tg3_reset_task_schedule(tp);
6459 static void tg3_napi_disable(struct tg3 *tp)
6463 for (i = tp->irq_cnt - 1; i >= 0; i--)
6464 napi_disable(&tp->napi[i].napi);
6467 static void tg3_napi_enable(struct tg3 *tp)
6471 for (i = 0; i < tp->irq_cnt; i++)
6472 napi_enable(&tp->napi[i].napi);
6475 static void tg3_napi_init(struct tg3 *tp)
6479 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6480 for (i = 1; i < tp->irq_cnt; i++)
6481 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6484 static void tg3_napi_fini(struct tg3 *tp)
6488 for (i = 0; i < tp->irq_cnt; i++)
6489 netif_napi_del(&tp->napi[i].napi);
6492 static inline void tg3_netif_stop(struct tg3 *tp)
6494 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6495 tg3_napi_disable(tp);
6496 netif_tx_disable(tp->dev);
6499 static inline void tg3_netif_start(struct tg3 *tp)
6501 /* NOTE: unconditional netif_tx_wake_all_queues is only
6502 * appropriate so long as all callers are assured to
6503 * have free tx slots (such as after tg3_init_hw)
6505 netif_tx_wake_all_queues(tp->dev);
6507 tg3_napi_enable(tp);
6508 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6509 tg3_enable_ints(tp);
6512 static void tg3_irq_quiesce(struct tg3 *tp)
6516 BUG_ON(tp->irq_sync);
6521 for (i = 0; i < tp->irq_cnt; i++)
6522 synchronize_irq(tp->napi[i].irq_vec);
6525 /* Fully shutdown all tg3 driver activity elsewhere in the system.
6526 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6527 * with as well. Most of the time, this is not necessary except when
6528 * shutting down the device.
6530 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6532 spin_lock_bh(&tp->lock);
6534 tg3_irq_quiesce(tp);
6537 static inline void tg3_full_unlock(struct tg3 *tp)
6539 spin_unlock_bh(&tp->lock);
6542 /* One-shot MSI handler - Chip automatically disables interrupt
6543 * after sending MSI so driver doesn't have to do it.
6545 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
6547 struct tg3_napi *tnapi = dev_id;
6548 struct tg3 *tp = tnapi->tp;
6550 prefetch(tnapi->hw_status);
6552 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6554 if (likely(!tg3_irq_sync(tp)))
6555 napi_schedule(&tnapi->napi);
6560 /* MSI ISR - No need to check for interrupt sharing and no need to
6561 * flush status block and interrupt mailbox. PCI ordering rules
6562 * guarantee that MSI will arrive after the status block.
6564 static irqreturn_t tg3_msi(int irq, void *dev_id)
6566 struct tg3_napi *tnapi = dev_id;
6567 struct tg3 *tp = tnapi->tp;
6569 prefetch(tnapi->hw_status);
6571 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6573 * Writing any value to intr-mbox-0 clears PCI INTA# and
6574 * chip-internal interrupt pending events.
6575 * Writing non-zero to intr-mbox-0 additional tells the
6576 * NIC to stop sending us irqs, engaging "in-intr-handler"
6579 tw32_mailbox(tnapi->int_mbox, 0x00000001);
6580 if (likely(!tg3_irq_sync(tp)))
6581 napi_schedule(&tnapi->napi);
6583 return IRQ_RETVAL(1);
6586 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
6588 struct tg3_napi *tnapi = dev_id;
6589 struct tg3 *tp = tnapi->tp;
6590 struct tg3_hw_status *sblk = tnapi->hw_status;
6591 unsigned int handled = 1;
6593 /* In INTx mode, it is possible for the interrupt to arrive at
6594 * the CPU before the status block posted prior to the interrupt.
6595 * Reading the PCI State register will confirm whether the
6596 * interrupt is ours and will flush the status block.
6598 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
6599 if (tg3_flag(tp, CHIP_RESETTING) ||
6600 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6607 * Writing any value to intr-mbox-0 clears PCI INTA# and
6608 * chip-internal interrupt pending events.
6609 * Writing non-zero to intr-mbox-0 additional tells the
6610 * NIC to stop sending us irqs, engaging "in-intr-handler"
6613 * Flush the mailbox to de-assert the IRQ immediately to prevent
6614 * spurious interrupts. The flush impacts performance but
6615 * excessive spurious interrupts can be worse in some cases.
6617 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6618 if (tg3_irq_sync(tp))
6620 sblk->status &= ~SD_STATUS_UPDATED;
6621 if (likely(tg3_has_work(tnapi))) {
6622 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6623 napi_schedule(&tnapi->napi);
6625 /* No work, shared interrupt perhaps? re-enable
6626 * interrupts, and flush that PCI write
6628 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6632 return IRQ_RETVAL(handled);
6635 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
6637 struct tg3_napi *tnapi = dev_id;
6638 struct tg3 *tp = tnapi->tp;
6639 struct tg3_hw_status *sblk = tnapi->hw_status;
6640 unsigned int handled = 1;
6642 /* In INTx mode, it is possible for the interrupt to arrive at
6643 * the CPU before the status block posted prior to the interrupt.
6644 * Reading the PCI State register will confirm whether the
6645 * interrupt is ours and will flush the status block.
6647 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
6648 if (tg3_flag(tp, CHIP_RESETTING) ||
6649 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6656 * writing any value to intr-mbox-0 clears PCI INTA# and
6657 * chip-internal interrupt pending events.
6658 * writing non-zero to intr-mbox-0 additional tells the
6659 * NIC to stop sending us irqs, engaging "in-intr-handler"
6662 * Flush the mailbox to de-assert the IRQ immediately to prevent
6663 * spurious interrupts. The flush impacts performance but
6664 * excessive spurious interrupts can be worse in some cases.
6666 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6669 * In a shared interrupt configuration, sometimes other devices'
6670 * interrupts will scream. We record the current status tag here
6671 * so that the above check can report that the screaming interrupts
6672 * are unhandled. Eventually they will be silenced.
6674 tnapi->last_irq_tag = sblk->status_tag;
6676 if (tg3_irq_sync(tp))
6679 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6681 napi_schedule(&tnapi->napi);
6684 return IRQ_RETVAL(handled);
6687 /* ISR for interrupt test */
6688 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
6690 struct tg3_napi *tnapi = dev_id;
6691 struct tg3 *tp = tnapi->tp;
6692 struct tg3_hw_status *sblk = tnapi->hw_status;
6694 if ((sblk->status & SD_STATUS_UPDATED) ||
6695 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6696 tg3_disable_ints(tp);
6697 return IRQ_RETVAL(1);
6699 return IRQ_RETVAL(0);
6702 #ifdef CONFIG_NET_POLL_CONTROLLER
6703 static void tg3_poll_controller(struct net_device *dev)
6706 struct tg3 *tp = netdev_priv(dev);
6708 for (i = 0; i < tp->irq_cnt; i++)
6709 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6713 static void tg3_tx_timeout(struct net_device *dev)
6715 struct tg3 *tp = netdev_priv(dev);
6717 if (netif_msg_tx_err(tp)) {
6718 netdev_err(dev, "transmit timed out, resetting\n");
6722 tg3_reset_task_schedule(tp);
6725 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6726 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6728 u32 base = (u32) mapping & 0xffffffff;
6730 return (base > 0xffffdcc0) && (base + len + 8 < base);
6733 /* Test for DMA addresses > 40-bit */
6734 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6737 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6738 if (tg3_flag(tp, 40BIT_DMA_BUG))
6739 return ((u64) mapping + len) > DMA_BIT_MASK(40);
6746 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
6747 dma_addr_t mapping, u32 len, u32 flags,
6750 txbd->addr_hi = ((u64) mapping >> 32);
6751 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6752 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6753 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
6756 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
6757 dma_addr_t map, u32 len, u32 flags,
6760 struct tg3 *tp = tnapi->tp;
6763 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6766 if (tg3_4g_overflow_test(map, len))
6769 if (tg3_40bit_overflow_test(tp, map, len))
6772 if (tp->dma_limit) {
6773 u32 prvidx = *entry;
6774 u32 tmp_flag = flags & ~TXD_FLAG_END;
6775 while (len > tp->dma_limit && *budget) {
6776 u32 frag_len = tp->dma_limit;
6777 len -= tp->dma_limit;
6779 /* Avoid the 8byte DMA problem */
6781 len += tp->dma_limit / 2;
6782 frag_len = tp->dma_limit / 2;
6785 tnapi->tx_buffers[*entry].fragmented = true;
6787 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6788 frag_len, tmp_flag, mss, vlan);
6791 *entry = NEXT_TX(*entry);
6798 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6799 len, flags, mss, vlan);
6801 *entry = NEXT_TX(*entry);
6804 tnapi->tx_buffers[prvidx].fragmented = false;
6808 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6809 len, flags, mss, vlan);
6810 *entry = NEXT_TX(*entry);
6816 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
6819 struct sk_buff *skb;
6820 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
6825 pci_unmap_single(tnapi->tp->pdev,
6826 dma_unmap_addr(txb, mapping),
6830 while (txb->fragmented) {
6831 txb->fragmented = false;
6832 entry = NEXT_TX(entry);
6833 txb = &tnapi->tx_buffers[entry];
6836 for (i = 0; i <= last; i++) {
6837 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6839 entry = NEXT_TX(entry);
6840 txb = &tnapi->tx_buffers[entry];
6842 pci_unmap_page(tnapi->tp->pdev,
6843 dma_unmap_addr(txb, mapping),
6844 skb_frag_size(frag), PCI_DMA_TODEVICE);
6846 while (txb->fragmented) {
6847 txb->fragmented = false;
6848 entry = NEXT_TX(entry);
6849 txb = &tnapi->tx_buffers[entry];
6854 /* Workaround 4GB and 40-bit hardware DMA bugs. */
6855 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
6856 struct sk_buff **pskb,
6857 u32 *entry, u32 *budget,
6858 u32 base_flags, u32 mss, u32 vlan)
6860 struct tg3 *tp = tnapi->tp;
6861 struct sk_buff *new_skb, *skb = *pskb;
6862 dma_addr_t new_addr = 0;
6865 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6866 new_skb = skb_copy(skb, GFP_ATOMIC);
6868 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6870 new_skb = skb_copy_expand(skb,
6871 skb_headroom(skb) + more_headroom,
6872 skb_tailroom(skb), GFP_ATOMIC);
6878 /* New SKB is guaranteed to be linear. */
6879 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6881 /* Make sure the mapping succeeded */
6882 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
6883 dev_kfree_skb(new_skb);
6886 u32 save_entry = *entry;
6888 base_flags |= TXD_FLAG_END;
6890 tnapi->tx_buffers[*entry].skb = new_skb;
6891 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
6894 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
6895 new_skb->len, base_flags,
6897 tg3_tx_skb_unmap(tnapi, save_entry, -1);
6898 dev_kfree_skb(new_skb);
6909 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
6911 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6912 * TSO header is greater than 80 bytes.
6914 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6916 struct sk_buff *segs, *nskb;
6917 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6919 /* Estimate the number of fragments in the worst case */
6920 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6921 netif_stop_queue(tp->dev);
6923 /* netif_tx_stop_queue() must be done before checking
6924 * checking tx index in tg3_tx_avail() below, because in
6925 * tg3_tx(), we update tx index before checking for
6926 * netif_tx_queue_stopped().
6929 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6930 return NETDEV_TX_BUSY;
6932 netif_wake_queue(tp->dev);
6935 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6937 goto tg3_tso_bug_end;
6943 tg3_start_xmit(nskb, tp->dev);
6949 return NETDEV_TX_OK;
6952 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6953 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6955 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6957 struct tg3 *tp = netdev_priv(dev);
6958 u32 len, entry, base_flags, mss, vlan = 0;
6960 int i = -1, would_hit_hwbug;
6962 struct tg3_napi *tnapi;
6963 struct netdev_queue *txq;
6966 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6967 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6968 if (tg3_flag(tp, ENABLE_TSS))
6971 budget = tg3_tx_avail(tnapi);
6973 /* We are running in BH disabled context with netif_tx_lock
6974 * and TX reclaim runs via tp->napi.poll inside of a software
6975 * interrupt. Furthermore, IRQ processing runs lockless so we have
6976 * no IRQ context deadlocks to worry about either. Rejoice!
6978 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
6979 if (!netif_tx_queue_stopped(txq)) {
6980 netif_tx_stop_queue(txq);
6982 /* This is a hard error, log it. */
6984 "BUG! Tx Ring full when queue awake!\n");
6986 return NETDEV_TX_BUSY;
6989 entry = tnapi->tx_prod;
6991 if (skb->ip_summed == CHECKSUM_PARTIAL)
6992 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6994 mss = skb_shinfo(skb)->gso_size;
6997 u32 tcp_opt_len, hdr_len;
6999 if (skb_header_cloned(skb) &&
7000 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7004 tcp_opt_len = tcp_optlen(skb);
7006 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7008 if (!skb_is_gso_v6(skb)) {
7010 iph->tot_len = htons(mss + hdr_len);
7013 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7014 tg3_flag(tp, TSO_BUG))
7015 return tg3_tso_bug(tp, skb);
7017 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7018 TXD_FLAG_CPU_POST_DMA);
7020 if (tg3_flag(tp, HW_TSO_1) ||
7021 tg3_flag(tp, HW_TSO_2) ||
7022 tg3_flag(tp, HW_TSO_3)) {
7023 tcp_hdr(skb)->check = 0;
7024 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7026 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7031 if (tg3_flag(tp, HW_TSO_3)) {
7032 mss |= (hdr_len & 0xc) << 12;
7034 base_flags |= 0x00000010;
7035 base_flags |= (hdr_len & 0x3e0) << 5;
7036 } else if (tg3_flag(tp, HW_TSO_2))
7037 mss |= hdr_len << 9;
7038 else if (tg3_flag(tp, HW_TSO_1) ||
7039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7040 if (tcp_opt_len || iph->ihl > 5) {
7043 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7044 mss |= (tsflags << 11);
7047 if (tcp_opt_len || iph->ihl > 5) {
7050 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7051 base_flags |= tsflags << 12;
7056 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7057 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7058 base_flags |= TXD_FLAG_JMB_PKT;
7060 if (vlan_tx_tag_present(skb)) {
7061 base_flags |= TXD_FLAG_VLAN;
7062 vlan = vlan_tx_tag_get(skb);
7065 len = skb_headlen(skb);
7067 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
7068 if (pci_dma_mapping_error(tp->pdev, mapping))
7072 tnapi->tx_buffers[entry].skb = skb;
7073 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
7075 would_hit_hwbug = 0;
7077 if (tg3_flag(tp, 5701_DMA_BUG))
7078 would_hit_hwbug = 1;
7080 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
7081 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
7083 would_hit_hwbug = 1;
7084 } else if (skb_shinfo(skb)->nr_frags > 0) {
7087 if (!tg3_flag(tp, HW_TSO_1) &&
7088 !tg3_flag(tp, HW_TSO_2) &&
7089 !tg3_flag(tp, HW_TSO_3))
7092 /* Now loop through additional data
7093 * fragments, and queue them.
7095 last = skb_shinfo(skb)->nr_frags - 1;
7096 for (i = 0; i <= last; i++) {
7097 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7099 len = skb_frag_size(frag);
7100 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
7101 len, DMA_TO_DEVICE);
7103 tnapi->tx_buffers[entry].skb = NULL;
7104 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
7106 if (dma_mapping_error(&tp->pdev->dev, mapping))
7110 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
7112 ((i == last) ? TXD_FLAG_END : 0),
7114 would_hit_hwbug = 1;
7120 if (would_hit_hwbug) {
7121 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
7123 /* If the workaround fails due to memory/mapping
7124 * failure, silently drop this packet.
7126 entry = tnapi->tx_prod;
7127 budget = tg3_tx_avail(tnapi);
7128 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
7129 base_flags, mss, vlan))
7133 skb_tx_timestamp(skb);
7134 netdev_tx_sent_queue(txq, skb->len);
7136 /* Sync BD data before updating mailbox */
7139 /* Packets are ready, update Tx producer idx local and on card. */
7140 tw32_tx_mbox(tnapi->prodmbox, entry);
7142 tnapi->tx_prod = entry;
7143 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
7144 netif_tx_stop_queue(txq);
7146 /* netif_tx_stop_queue() must be done before checking
7147 * checking tx index in tg3_tx_avail() below, because in
7148 * tg3_tx(), we update tx index before checking for
7149 * netif_tx_queue_stopped().
7152 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
7153 netif_tx_wake_queue(txq);
7157 return NETDEV_TX_OK;
7160 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
7161 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
7166 return NETDEV_TX_OK;
7169 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
7172 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
7173 MAC_MODE_PORT_MODE_MASK);
7175 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
7177 if (!tg3_flag(tp, 5705_PLUS))
7178 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7180 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
7181 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
7183 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7185 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
7187 if (tg3_flag(tp, 5705_PLUS) ||
7188 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
7189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
7190 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
7193 tw32(MAC_MODE, tp->mac_mode);
7197 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
7199 u32 val, bmcr, mac_mode, ptest = 0;
7201 tg3_phy_toggle_apd(tp, false);
7202 tg3_phy_toggle_automdix(tp, 0);
7204 if (extlpbk && tg3_phy_set_extloopbk(tp))
7207 bmcr = BMCR_FULLDPLX;
7212 bmcr |= BMCR_SPEED100;
7216 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7218 bmcr |= BMCR_SPEED100;
7221 bmcr |= BMCR_SPEED1000;
7226 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
7227 tg3_readphy(tp, MII_CTRL1000, &val);
7228 val |= CTL1000_AS_MASTER |
7229 CTL1000_ENABLE_MASTER;
7230 tg3_writephy(tp, MII_CTRL1000, val);
7232 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
7233 MII_TG3_FET_PTEST_TRIM_2;
7234 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
7237 bmcr |= BMCR_LOOPBACK;
7239 tg3_writephy(tp, MII_BMCR, bmcr);
7241 /* The write needs to be flushed for the FETs */
7242 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7243 tg3_readphy(tp, MII_BMCR, &bmcr);
7247 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
7248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
7249 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
7250 MII_TG3_FET_PTEST_FRC_TX_LINK |
7251 MII_TG3_FET_PTEST_FRC_TX_LOCK);
7253 /* The write needs to be flushed for the AC131 */
7254 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
7257 /* Reset to prevent losing 1st rx packet intermittently */
7258 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
7259 tg3_flag(tp, 5780_CLASS)) {
7260 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7262 tw32_f(MAC_RX_MODE, tp->rx_mode);
7265 mac_mode = tp->mac_mode &
7266 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
7267 if (speed == SPEED_1000)
7268 mac_mode |= MAC_MODE_PORT_MODE_GMII;
7270 mac_mode |= MAC_MODE_PORT_MODE_MII;
7272 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
7273 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
7275 if (masked_phy_id == TG3_PHY_ID_BCM5401)
7276 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7277 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
7278 mac_mode |= MAC_MODE_LINK_POLARITY;
7280 tg3_writephy(tp, MII_TG3_EXT_CTRL,
7281 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
7284 tw32(MAC_MODE, mac_mode);
7290 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
7292 struct tg3 *tp = netdev_priv(dev);
7294 if (features & NETIF_F_LOOPBACK) {
7295 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
7298 spin_lock_bh(&tp->lock);
7299 tg3_mac_loopback(tp, true);
7300 netif_carrier_on(tp->dev);
7301 spin_unlock_bh(&tp->lock);
7302 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
7304 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
7307 spin_lock_bh(&tp->lock);
7308 tg3_mac_loopback(tp, false);
7309 /* Force link status check */
7310 tg3_setup_phy(tp, 1);
7311 spin_unlock_bh(&tp->lock);
7312 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
7316 static netdev_features_t tg3_fix_features(struct net_device *dev,
7317 netdev_features_t features)
7319 struct tg3 *tp = netdev_priv(dev);
7321 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
7322 features &= ~NETIF_F_ALL_TSO;
7327 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
7329 netdev_features_t changed = dev->features ^ features;
7331 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7332 tg3_set_loopback(dev, features);
7337 static void tg3_rx_prodring_free(struct tg3 *tp,
7338 struct tg3_rx_prodring_set *tpr)
7342 if (tpr != &tp->napi[0].prodring) {
7343 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
7344 i = (i + 1) & tp->rx_std_ring_mask)
7345 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7348 if (tg3_flag(tp, JUMBO_CAPABLE)) {
7349 for (i = tpr->rx_jmb_cons_idx;
7350 i != tpr->rx_jmb_prod_idx;
7351 i = (i + 1) & tp->rx_jmb_ring_mask) {
7352 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7360 for (i = 0; i <= tp->rx_std_ring_mask; i++)
7361 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7364 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7365 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
7366 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7371 /* Initialize rx rings for packet processing.
7373 * The chip has been shut down and the driver detached from
7374 * the networking, so no interrupts or new tx packets will
7375 * end up in the driver. tp->{tx,}lock are held and thus
7378 static int tg3_rx_prodring_alloc(struct tg3 *tp,
7379 struct tg3_rx_prodring_set *tpr)
7381 u32 i, rx_pkt_dma_sz;
7383 tpr->rx_std_cons_idx = 0;
7384 tpr->rx_std_prod_idx = 0;
7385 tpr->rx_jmb_cons_idx = 0;
7386 tpr->rx_jmb_prod_idx = 0;
7388 if (tpr != &tp->napi[0].prodring) {
7389 memset(&tpr->rx_std_buffers[0], 0,
7390 TG3_RX_STD_BUFF_RING_SIZE(tp));
7391 if (tpr->rx_jmb_buffers)
7392 memset(&tpr->rx_jmb_buffers[0], 0,
7393 TG3_RX_JMB_BUFF_RING_SIZE(tp));
7397 /* Zero out all descriptors. */
7398 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
7400 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
7401 if (tg3_flag(tp, 5780_CLASS) &&
7402 tp->dev->mtu > ETH_DATA_LEN)
7403 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7404 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7406 /* Initialize invariants of the rings, we only set this
7407 * stuff once. This works because the card does not
7408 * write into the rx buffer posting rings.
7410 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
7411 struct tg3_rx_buffer_desc *rxd;
7413 rxd = &tpr->rx_std[i];
7414 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
7415 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7416 rxd->opaque = (RXD_OPAQUE_RING_STD |
7417 (i << RXD_OPAQUE_INDEX_SHIFT));
7420 /* Now allocate fresh SKBs for each rx ring. */
7421 for (i = 0; i < tp->rx_pending; i++) {
7422 unsigned int frag_size;
7424 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
7426 netdev_warn(tp->dev,
7427 "Using a smaller RX standard ring. Only "
7428 "%d out of %d buffers were allocated "
7429 "successfully\n", i, tp->rx_pending);
7437 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7440 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
7442 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
7445 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
7446 struct tg3_rx_buffer_desc *rxd;
7448 rxd = &tpr->rx_jmb[i].std;
7449 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7450 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7452 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7453 (i << RXD_OPAQUE_INDEX_SHIFT));
7456 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7457 unsigned int frag_size;
7459 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
7461 netdev_warn(tp->dev,
7462 "Using a smaller RX jumbo ring. Only %d "
7463 "out of %d buffers were allocated "
7464 "successfully\n", i, tp->rx_jumbo_pending);
7467 tp->rx_jumbo_pending = i;
7476 tg3_rx_prodring_free(tp, tpr);
7480 static void tg3_rx_prodring_fini(struct tg3 *tp,
7481 struct tg3_rx_prodring_set *tpr)
7483 kfree(tpr->rx_std_buffers);
7484 tpr->rx_std_buffers = NULL;
7485 kfree(tpr->rx_jmb_buffers);
7486 tpr->rx_jmb_buffers = NULL;
7488 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7489 tpr->rx_std, tpr->rx_std_mapping);
7493 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7494 tpr->rx_jmb, tpr->rx_jmb_mapping);
7499 static int tg3_rx_prodring_init(struct tg3 *tp,
7500 struct tg3_rx_prodring_set *tpr)
7502 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7504 if (!tpr->rx_std_buffers)
7507 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7508 TG3_RX_STD_RING_BYTES(tp),
7509 &tpr->rx_std_mapping,
7514 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7515 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
7517 if (!tpr->rx_jmb_buffers)
7520 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7521 TG3_RX_JMB_RING_BYTES(tp),
7522 &tpr->rx_jmb_mapping,
7531 tg3_rx_prodring_fini(tp, tpr);
7535 /* Free up pending packets in all rx/tx rings.
7537 * The chip has been shut down and the driver detached from
7538 * the networking, so no interrupts or new tx packets will
7539 * end up in the driver. tp->{tx,}lock is not held and we are not
7540 * in an interrupt context and thus may sleep.
7542 static void tg3_free_rings(struct tg3 *tp)
7546 for (j = 0; j < tp->irq_cnt; j++) {
7547 struct tg3_napi *tnapi = &tp->napi[j];
7549 tg3_rx_prodring_free(tp, &tnapi->prodring);
7551 if (!tnapi->tx_buffers)
7554 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7555 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
7560 tg3_tx_skb_unmap(tnapi, i,
7561 skb_shinfo(skb)->nr_frags - 1);
7563 dev_kfree_skb_any(skb);
7565 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
7569 /* Initialize tx/rx rings for packet processing.
7571 * The chip has been shut down and the driver detached from
7572 * the networking, so no interrupts or new tx packets will
7573 * end up in the driver. tp->{tx,}lock are held and thus
7576 static int tg3_init_rings(struct tg3 *tp)
7580 /* Free up all the SKBs. */
7583 for (i = 0; i < tp->irq_cnt; i++) {
7584 struct tg3_napi *tnapi = &tp->napi[i];
7586 tnapi->last_tag = 0;
7587 tnapi->last_irq_tag = 0;
7588 tnapi->hw_status->status = 0;
7589 tnapi->hw_status->status_tag = 0;
7590 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7595 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
7597 tnapi->rx_rcb_ptr = 0;
7599 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7601 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
7610 static void tg3_mem_tx_release(struct tg3 *tp)
7614 for (i = 0; i < tp->irq_max; i++) {
7615 struct tg3_napi *tnapi = &tp->napi[i];
7617 if (tnapi->tx_ring) {
7618 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7619 tnapi->tx_ring, tnapi->tx_desc_mapping);
7620 tnapi->tx_ring = NULL;
7623 kfree(tnapi->tx_buffers);
7624 tnapi->tx_buffers = NULL;
7628 static int tg3_mem_tx_acquire(struct tg3 *tp)
7631 struct tg3_napi *tnapi = &tp->napi[0];
7633 /* If multivector TSS is enabled, vector 0 does not handle
7634 * tx interrupts. Don't allocate any resources for it.
7636 if (tg3_flag(tp, ENABLE_TSS))
7639 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
7640 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
7641 TG3_TX_RING_SIZE, GFP_KERNEL);
7642 if (!tnapi->tx_buffers)
7645 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7647 &tnapi->tx_desc_mapping,
7649 if (!tnapi->tx_ring)
7656 tg3_mem_tx_release(tp);
7660 static void tg3_mem_rx_release(struct tg3 *tp)
7664 for (i = 0; i < tp->irq_max; i++) {
7665 struct tg3_napi *tnapi = &tp->napi[i];
7667 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7672 dma_free_coherent(&tp->pdev->dev,
7673 TG3_RX_RCB_RING_BYTES(tp),
7675 tnapi->rx_rcb_mapping);
7676 tnapi->rx_rcb = NULL;
7680 static int tg3_mem_rx_acquire(struct tg3 *tp)
7682 unsigned int i, limit;
7684 limit = tp->rxq_cnt;
7686 /* If RSS is enabled, we need a (dummy) producer ring
7687 * set on vector zero. This is the true hw prodring.
7689 if (tg3_flag(tp, ENABLE_RSS))
7692 for (i = 0; i < limit; i++) {
7693 struct tg3_napi *tnapi = &tp->napi[i];
7695 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7698 /* If multivector RSS is enabled, vector 0
7699 * does not handle rx or tx interrupts.
7700 * Don't allocate any resources for it.
7702 if (!i && tg3_flag(tp, ENABLE_RSS))
7705 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7706 TG3_RX_RCB_RING_BYTES(tp),
7707 &tnapi->rx_rcb_mapping,
7712 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7718 tg3_mem_rx_release(tp);
7723 * Must not be invoked with interrupt sources disabled and
7724 * the hardware shutdown down.
7726 static void tg3_free_consistent(struct tg3 *tp)
7730 for (i = 0; i < tp->irq_cnt; i++) {
7731 struct tg3_napi *tnapi = &tp->napi[i];
7733 if (tnapi->hw_status) {
7734 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7736 tnapi->status_mapping);
7737 tnapi->hw_status = NULL;
7741 tg3_mem_rx_release(tp);
7742 tg3_mem_tx_release(tp);
7745 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7746 tp->hw_stats, tp->stats_mapping);
7747 tp->hw_stats = NULL;
7752 * Must not be invoked with interrupt sources disabled and
7753 * the hardware shutdown down. Can sleep.
7755 static int tg3_alloc_consistent(struct tg3 *tp)
7759 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7760 sizeof(struct tg3_hw_stats),
7766 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7768 for (i = 0; i < tp->irq_cnt; i++) {
7769 struct tg3_napi *tnapi = &tp->napi[i];
7770 struct tg3_hw_status *sblk;
7772 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7774 &tnapi->status_mapping,
7776 if (!tnapi->hw_status)
7779 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7780 sblk = tnapi->hw_status;
7782 if (tg3_flag(tp, ENABLE_RSS)) {
7786 * When RSS is enabled, the status block format changes
7787 * slightly. The "rx_jumbo_consumer", "reserved",
7788 * and "rx_mini_consumer" members get mapped to the
7789 * other three rx return ring producer indexes.
7793 prodptr = &sblk->idx[0].rx_producer;
7796 prodptr = &sblk->rx_jumbo_consumer;
7799 prodptr = &sblk->reserved;
7802 prodptr = &sblk->rx_mini_consumer;
7805 tnapi->rx_rcb_prod_idx = prodptr;
7807 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7811 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
7817 tg3_free_consistent(tp);
7821 #define MAX_WAIT_CNT 1000
7823 /* To stop a block, clear the enable bit and poll till it
7824 * clears. tp->lock is held.
7826 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
7831 if (tg3_flag(tp, 5705_PLUS)) {
7838 /* We can't enable/disable these bits of the
7839 * 5705/5750, just say success.
7852 for (i = 0; i < MAX_WAIT_CNT; i++) {
7855 if ((val & enable_bit) == 0)
7859 if (i == MAX_WAIT_CNT && !silent) {
7860 dev_err(&tp->pdev->dev,
7861 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7869 /* tp->lock is held. */
7870 static int tg3_abort_hw(struct tg3 *tp, int silent)
7874 tg3_disable_ints(tp);
7876 tp->rx_mode &= ~RX_MODE_ENABLE;
7877 tw32_f(MAC_RX_MODE, tp->rx_mode);
7880 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7881 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7882 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7883 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7884 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7885 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
7887 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7888 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7889 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7890 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7891 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7892 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7893 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
7895 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7896 tw32_f(MAC_MODE, tp->mac_mode);
7899 tp->tx_mode &= ~TX_MODE_ENABLE;
7900 tw32_f(MAC_TX_MODE, tp->tx_mode);
7902 for (i = 0; i < MAX_WAIT_CNT; i++) {
7904 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7907 if (i >= MAX_WAIT_CNT) {
7908 dev_err(&tp->pdev->dev,
7909 "%s timed out, TX_MODE_ENABLE will not clear "
7910 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
7914 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
7915 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7916 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
7918 tw32(FTQ_RESET, 0xffffffff);
7919 tw32(FTQ_RESET, 0x00000000);
7921 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7922 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7924 for (i = 0; i < tp->irq_cnt; i++) {
7925 struct tg3_napi *tnapi = &tp->napi[i];
7926 if (tnapi->hw_status)
7927 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7933 /* Save PCI command register before chip reset */
7934 static void tg3_save_pci_state(struct tg3 *tp)
7936 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7939 /* Restore PCI state after chip reset */
7940 static void tg3_restore_pci_state(struct tg3 *tp)
7944 /* Re-enable indirect register accesses. */
7945 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7946 tp->misc_host_ctrl);
7948 /* Set MAX PCI retry to zero. */
7949 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7950 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7951 tg3_flag(tp, PCIX_MODE))
7952 val |= PCISTATE_RETRY_SAME_DMA;
7953 /* Allow reads and writes to the APE register and memory space. */
7954 if (tg3_flag(tp, ENABLE_APE))
7955 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7956 PCISTATE_ALLOW_APE_SHMEM_WR |
7957 PCISTATE_ALLOW_APE_PSPACE_WR;
7958 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7960 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7962 if (!tg3_flag(tp, PCI_EXPRESS)) {
7963 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7964 tp->pci_cacheline_sz);
7965 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7969 /* Make sure PCI-X relaxed ordering bit is clear. */
7970 if (tg3_flag(tp, PCIX_MODE)) {
7973 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7975 pcix_cmd &= ~PCI_X_CMD_ERO;
7976 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7980 if (tg3_flag(tp, 5780_CLASS)) {
7982 /* Chip reset on 5780 will reset MSI enable bit,
7983 * so need to restore it.
7985 if (tg3_flag(tp, USING_MSI)) {
7988 pci_read_config_word(tp->pdev,
7989 tp->msi_cap + PCI_MSI_FLAGS,
7991 pci_write_config_word(tp->pdev,
7992 tp->msi_cap + PCI_MSI_FLAGS,
7993 ctrl | PCI_MSI_FLAGS_ENABLE);
7994 val = tr32(MSGINT_MODE);
7995 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8000 /* tp->lock is held. */
8001 static int tg3_chip_reset(struct tg3 *tp)
8004 void (*write_op)(struct tg3 *, u32, u32);
8009 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8011 /* No matching tg3_nvram_unlock() after this because
8012 * chip reset below will undo the nvram lock.
8014 tp->nvram_lock_cnt = 0;
8016 /* GRC_MISC_CFG core clock reset will clear the memory
8017 * enable bit in PCI register 4 and the MSI enable bit
8018 * on some chips, so we save relevant registers here.
8020 tg3_save_pci_state(tp);
8022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8023 tg3_flag(tp, 5755_PLUS))
8024 tw32(GRC_FASTBOOT_PC, 0);
8027 * We must avoid the readl() that normally takes place.
8028 * It locks machines, causes machine checks, and other
8029 * fun things. So, temporarily disable the 5701
8030 * hardware workaround, while we do the reset.
8032 write_op = tp->write32;
8033 if (write_op == tg3_write_flush_reg32)
8034 tp->write32 = tg3_write32;
8036 /* Prevent the irq handler from reading or writing PCI registers
8037 * during chip reset when the memory enable bit in the PCI command
8038 * register may be cleared. The chip does not generate interrupt
8039 * at this time, but the irq handler may still be called due to irq
8040 * sharing or irqpoll.
8042 tg3_flag_set(tp, CHIP_RESETTING);
8043 for (i = 0; i < tp->irq_cnt; i++) {
8044 struct tg3_napi *tnapi = &tp->napi[i];
8045 if (tnapi->hw_status) {
8046 tnapi->hw_status->status = 0;
8047 tnapi->hw_status->status_tag = 0;
8049 tnapi->last_tag = 0;
8050 tnapi->last_irq_tag = 0;
8054 for (i = 0; i < tp->irq_cnt; i++)
8055 synchronize_irq(tp->napi[i].irq_vec);
8057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8058 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8059 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8063 val = GRC_MISC_CFG_CORECLK_RESET;
8065 if (tg3_flag(tp, PCI_EXPRESS)) {
8066 /* Force PCIe 1.0a mode */
8067 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
8068 !tg3_flag(tp, 57765_PLUS) &&
8069 tr32(TG3_PCIE_PHY_TSTCTL) ==
8070 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8071 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
8073 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
8074 tw32(GRC_MISC_CFG, (1 << 29));
8079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8080 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
8081 tw32(GRC_VCPU_EXT_CTRL,
8082 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
8085 /* Manage gphy power for all CPMU absent PCIe devices. */
8086 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
8087 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
8089 tw32(GRC_MISC_CFG, val);
8091 /* restore 5701 hardware bug workaround write method */
8092 tp->write32 = write_op;
8094 /* Unfortunately, we have to delay before the PCI read back.
8095 * Some 575X chips even will not respond to a PCI cfg access
8096 * when the reset command is given to the chip.
8098 * How do these hardware designers expect things to work
8099 * properly if the PCI write is posted for a long period
8100 * of time? It is always necessary to have some method by
8101 * which a register read back can occur to push the write
8102 * out which does the reset.
8104 * For most tg3 variants the trick below was working.
8109 /* Flush PCI posted writes. The normal MMIO registers
8110 * are inaccessible at this time so this is the only
8111 * way to make this reliably (actually, this is no longer
8112 * the case, see above). I tried to use indirect
8113 * register read/write but this upset some 5701 variants.
8115 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
8119 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
8122 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
8126 /* Wait for link training to complete. */
8127 for (i = 0; i < 5000; i++)
8130 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
8131 pci_write_config_dword(tp->pdev, 0xc4,
8132 cfg_val | (1 << 15));
8135 /* Clear the "no snoop" and "relaxed ordering" bits. */
8136 pci_read_config_word(tp->pdev,
8137 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
8139 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
8140 PCI_EXP_DEVCTL_NOSNOOP_EN);
8142 * Older PCIe devices only support the 128 byte
8143 * MPS setting. Enforce the restriction.
8145 if (!tg3_flag(tp, CPMU_PRESENT))
8146 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
8147 pci_write_config_word(tp->pdev,
8148 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
8151 /* Clear error status */
8152 pci_write_config_word(tp->pdev,
8153 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
8154 PCI_EXP_DEVSTA_CED |
8155 PCI_EXP_DEVSTA_NFED |
8156 PCI_EXP_DEVSTA_FED |
8157 PCI_EXP_DEVSTA_URD);
8160 tg3_restore_pci_state(tp);
8162 tg3_flag_clear(tp, CHIP_RESETTING);
8163 tg3_flag_clear(tp, ERROR_PROCESSED);
8166 if (tg3_flag(tp, 5780_CLASS))
8167 val = tr32(MEMARB_MODE);
8168 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
8170 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
8172 tw32(0x5000, 0x400);
8175 tw32(GRC_MODE, tp->grc_mode);
8177 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
8180 tw32(0xc4, val | (1 << 15));
8183 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
8184 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8185 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
8186 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
8187 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
8188 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8191 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8192 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
8194 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8195 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
8200 tw32_f(MAC_MODE, val);
8203 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
8205 err = tg3_poll_fw(tp);
8211 if (tg3_flag(tp, PCI_EXPRESS) &&
8212 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8213 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
8214 !tg3_flag(tp, 57765_PLUS)) {
8217 tw32(0x7c00, val | (1 << 25));
8220 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8221 val = tr32(TG3_CPMU_CLCK_ORIDE);
8222 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8225 /* Reprobe ASF enable state. */
8226 tg3_flag_clear(tp, ENABLE_ASF);
8227 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
8228 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8229 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8232 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8233 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8234 tg3_flag_set(tp, ENABLE_ASF);
8235 tp->last_event_jiffies = jiffies;
8236 if (tg3_flag(tp, 5750_PLUS))
8237 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
8244 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
8245 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
8247 /* tp->lock is held. */
8248 static int tg3_halt(struct tg3 *tp, int kind, int silent)
8254 tg3_write_sig_pre_reset(tp, kind);
8256 tg3_abort_hw(tp, silent);
8257 err = tg3_chip_reset(tp);
8259 __tg3_set_mac_addr(tp, 0);
8261 tg3_write_sig_legacy(tp, kind);
8262 tg3_write_sig_post_reset(tp, kind);
8265 /* Save the stats across chip resets... */
8266 tg3_get_nstats(tp, &tp->net_stats_prev);
8267 tg3_get_estats(tp, &tp->estats_prev);
8269 /* And make sure the next sample is new data */
8270 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
8279 static int tg3_set_mac_addr(struct net_device *dev, void *p)
8281 struct tg3 *tp = netdev_priv(dev);
8282 struct sockaddr *addr = p;
8283 int err = 0, skip_mac_1 = 0;
8285 if (!is_valid_ether_addr(addr->sa_data))
8286 return -EADDRNOTAVAIL;
8288 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8290 if (!netif_running(dev))
8293 if (tg3_flag(tp, ENABLE_ASF)) {
8294 u32 addr0_high, addr0_low, addr1_high, addr1_low;
8296 addr0_high = tr32(MAC_ADDR_0_HIGH);
8297 addr0_low = tr32(MAC_ADDR_0_LOW);
8298 addr1_high = tr32(MAC_ADDR_1_HIGH);
8299 addr1_low = tr32(MAC_ADDR_1_LOW);
8301 /* Skip MAC addr 1 if ASF is using it. */
8302 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
8303 !(addr1_high == 0 && addr1_low == 0))
8306 spin_lock_bh(&tp->lock);
8307 __tg3_set_mac_addr(tp, skip_mac_1);
8308 spin_unlock_bh(&tp->lock);
8313 /* tp->lock is held. */
8314 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
8315 dma_addr_t mapping, u32 maxlen_flags,
8319 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
8320 ((u64) mapping >> 32));
8322 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
8323 ((u64) mapping & 0xffffffff));
8325 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
8328 if (!tg3_flag(tp, 5705_PLUS))
8330 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
8334 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8338 if (!tg3_flag(tp, ENABLE_TSS)) {
8339 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
8340 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
8341 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
8343 tw32(HOSTCC_TXCOL_TICKS, 0);
8344 tw32(HOSTCC_TXMAX_FRAMES, 0);
8345 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
8348 if (!tg3_flag(tp, ENABLE_RSS)) {
8349 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8350 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8351 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8353 tw32(HOSTCC_RXCOL_TICKS, 0);
8354 tw32(HOSTCC_RXMAX_FRAMES, 0);
8355 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
8358 if (!tg3_flag(tp, 5705_PLUS)) {
8359 u32 val = ec->stats_block_coalesce_usecs;
8361 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8362 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8364 if (!netif_carrier_ok(tp->dev))
8367 tw32(HOSTCC_STAT_COAL_TICKS, val);
8370 for (i = 0; i < tp->irq_cnt - 1; i++) {
8373 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8374 tw32(reg, ec->rx_coalesce_usecs);
8375 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8376 tw32(reg, ec->rx_max_coalesced_frames);
8377 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8378 tw32(reg, ec->rx_max_coalesced_frames_irq);
8380 if (tg3_flag(tp, ENABLE_TSS)) {
8381 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8382 tw32(reg, ec->tx_coalesce_usecs);
8383 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8384 tw32(reg, ec->tx_max_coalesced_frames);
8385 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8386 tw32(reg, ec->tx_max_coalesced_frames_irq);
8390 for (; i < tp->irq_max - 1; i++) {
8391 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8392 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8393 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8395 if (tg3_flag(tp, ENABLE_TSS)) {
8396 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8397 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8398 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8403 /* tp->lock is held. */
8404 static void tg3_rings_reset(struct tg3 *tp)
8407 u32 stblk, txrcb, rxrcb, limit;
8408 struct tg3_napi *tnapi = &tp->napi[0];
8410 /* Disable all transmit rings but the first. */
8411 if (!tg3_flag(tp, 5705_PLUS))
8412 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
8413 else if (tg3_flag(tp, 5717_PLUS))
8414 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
8415 else if (tg3_flag(tp, 57765_CLASS))
8416 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
8418 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8420 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8421 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8422 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8423 BDINFO_FLAGS_DISABLED);
8426 /* Disable all receive return rings but the first. */
8427 if (tg3_flag(tp, 5717_PLUS))
8428 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
8429 else if (!tg3_flag(tp, 5705_PLUS))
8430 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
8431 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8432 tg3_flag(tp, 57765_CLASS))
8433 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8435 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8437 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8438 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8439 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8440 BDINFO_FLAGS_DISABLED);
8442 /* Disable interrupts */
8443 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
8444 tp->napi[0].chk_msi_cnt = 0;
8445 tp->napi[0].last_rx_cons = 0;
8446 tp->napi[0].last_tx_cons = 0;
8448 /* Zero mailbox registers. */
8449 if (tg3_flag(tp, SUPPORT_MSIX)) {
8450 for (i = 1; i < tp->irq_max; i++) {
8451 tp->napi[i].tx_prod = 0;
8452 tp->napi[i].tx_cons = 0;
8453 if (tg3_flag(tp, ENABLE_TSS))
8454 tw32_mailbox(tp->napi[i].prodmbox, 0);
8455 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8456 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
8457 tp->napi[i].chk_msi_cnt = 0;
8458 tp->napi[i].last_rx_cons = 0;
8459 tp->napi[i].last_tx_cons = 0;
8461 if (!tg3_flag(tp, ENABLE_TSS))
8462 tw32_mailbox(tp->napi[0].prodmbox, 0);
8464 tp->napi[0].tx_prod = 0;
8465 tp->napi[0].tx_cons = 0;
8466 tw32_mailbox(tp->napi[0].prodmbox, 0);
8467 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8470 /* Make sure the NIC-based send BD rings are disabled. */
8471 if (!tg3_flag(tp, 5705_PLUS)) {
8472 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8473 for (i = 0; i < 16; i++)
8474 tw32_tx_mbox(mbox + i * 8, 0);
8477 txrcb = NIC_SRAM_SEND_RCB;
8478 rxrcb = NIC_SRAM_RCV_RET_RCB;
8480 /* Clear status block in ram. */
8481 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8483 /* Set status block DMA address */
8484 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8485 ((u64) tnapi->status_mapping >> 32));
8486 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8487 ((u64) tnapi->status_mapping & 0xffffffff));
8489 if (tnapi->tx_ring) {
8490 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8491 (TG3_TX_RING_SIZE <<
8492 BDINFO_FLAGS_MAXLEN_SHIFT),
8493 NIC_SRAM_TX_BUFFER_DESC);
8494 txrcb += TG3_BDINFO_SIZE;
8497 if (tnapi->rx_rcb) {
8498 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8499 (tp->rx_ret_ring_mask + 1) <<
8500 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
8501 rxrcb += TG3_BDINFO_SIZE;
8504 stblk = HOSTCC_STATBLCK_RING1;
8506 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8507 u64 mapping = (u64)tnapi->status_mapping;
8508 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8509 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8511 /* Clear status block in ram. */
8512 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8514 if (tnapi->tx_ring) {
8515 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8516 (TG3_TX_RING_SIZE <<
8517 BDINFO_FLAGS_MAXLEN_SHIFT),
8518 NIC_SRAM_TX_BUFFER_DESC);
8519 txrcb += TG3_BDINFO_SIZE;
8522 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8523 ((tp->rx_ret_ring_mask + 1) <<
8524 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8527 rxrcb += TG3_BDINFO_SIZE;
8531 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8533 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8535 if (!tg3_flag(tp, 5750_PLUS) ||
8536 tg3_flag(tp, 5780_CLASS) ||
8537 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8538 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8539 tg3_flag(tp, 57765_PLUS))
8540 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8541 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8542 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8543 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8545 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8547 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8548 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8550 val = min(nic_rep_thresh, host_rep_thresh);
8551 tw32(RCVBDI_STD_THRESH, val);
8553 if (tg3_flag(tp, 57765_PLUS))
8554 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8556 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8559 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8561 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8563 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8564 tw32(RCVBDI_JUMBO_THRESH, val);
8566 if (tg3_flag(tp, 57765_PLUS))
8567 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8570 static inline u32 calc_crc(unsigned char *buf, int len)
8578 for (j = 0; j < len; j++) {
8581 for (k = 0; k < 8; k++) {
8594 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8596 /* accept or reject all multicast frames */
8597 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8598 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8599 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8600 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8603 static void __tg3_set_rx_mode(struct net_device *dev)
8605 struct tg3 *tp = netdev_priv(dev);
8608 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8609 RX_MODE_KEEP_VLAN_TAG);
8611 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
8612 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8615 if (!tg3_flag(tp, ENABLE_ASF))
8616 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8619 if (dev->flags & IFF_PROMISC) {
8620 /* Promiscuous mode. */
8621 rx_mode |= RX_MODE_PROMISC;
8622 } else if (dev->flags & IFF_ALLMULTI) {
8623 /* Accept all multicast. */
8624 tg3_set_multi(tp, 1);
8625 } else if (netdev_mc_empty(dev)) {
8626 /* Reject all multicast. */
8627 tg3_set_multi(tp, 0);
8629 /* Accept one or more multicast(s). */
8630 struct netdev_hw_addr *ha;
8631 u32 mc_filter[4] = { 0, };
8636 netdev_for_each_mc_addr(ha, dev) {
8637 crc = calc_crc(ha->addr, ETH_ALEN);
8639 regidx = (bit & 0x60) >> 5;
8641 mc_filter[regidx] |= (1 << bit);
8644 tw32(MAC_HASH_REG_0, mc_filter[0]);
8645 tw32(MAC_HASH_REG_1, mc_filter[1]);
8646 tw32(MAC_HASH_REG_2, mc_filter[2]);
8647 tw32(MAC_HASH_REG_3, mc_filter[3]);
8650 if (rx_mode != tp->rx_mode) {
8651 tp->rx_mode = rx_mode;
8652 tw32_f(MAC_RX_MODE, rx_mode);
8657 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
8661 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
8662 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
8665 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
8669 if (!tg3_flag(tp, SUPPORT_MSIX))
8672 if (tp->irq_cnt <= 2) {
8673 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
8677 /* Validate table against current IRQ count */
8678 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8679 if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1)
8683 if (i != TG3_RSS_INDIR_TBL_SIZE)
8684 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
8687 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
8690 u32 reg = MAC_RSS_INDIR_TBL_0;
8692 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8693 u32 val = tp->rss_ind_tbl[i];
8695 for (; i % 8; i++) {
8697 val |= tp->rss_ind_tbl[i];
8704 /* tp->lock is held. */
8705 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8707 u32 val, rdmac_mode;
8709 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8711 tg3_disable_ints(tp);
8715 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8717 if (tg3_flag(tp, INIT_COMPLETE))
8718 tg3_abort_hw(tp, 1);
8720 /* Enable MAC control of LPI */
8721 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8722 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8723 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8724 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8726 tw32_f(TG3_CPMU_EEE_CTRL,
8727 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8729 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8730 TG3_CPMU_EEEMD_LPI_IN_TX |
8731 TG3_CPMU_EEEMD_LPI_IN_RX |
8732 TG3_CPMU_EEEMD_EEE_ENABLE;
8734 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8735 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8737 if (tg3_flag(tp, ENABLE_APE))
8738 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8740 tw32_f(TG3_CPMU_EEE_MODE, val);
8742 tw32_f(TG3_CPMU_EEE_DBTMR1,
8743 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8744 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8746 tw32_f(TG3_CPMU_EEE_DBTMR2,
8747 TG3_CPMU_DBTMR2_APE_TX_2047US |
8748 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8754 err = tg3_chip_reset(tp);
8758 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8760 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8761 val = tr32(TG3_CPMU_CTRL);
8762 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8763 tw32(TG3_CPMU_CTRL, val);
8765 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8766 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8767 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8768 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8770 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8771 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8772 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8773 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8775 val = tr32(TG3_CPMU_HST_ACC);
8776 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8777 val |= CPMU_HST_ACC_MACCLK_6_25;
8778 tw32(TG3_CPMU_HST_ACC, val);
8781 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8782 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8783 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8784 PCIE_PWR_MGMT_L1_THRESH_4MS;
8785 tw32(PCIE_PWR_MGMT_THRESH, val);
8787 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8788 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8790 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8792 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8793 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8796 if (tg3_flag(tp, L1PLLPD_EN)) {
8797 u32 grc_mode = tr32(GRC_MODE);
8799 /* Access the lower 1K of PL PCIE block registers. */
8800 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8801 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8803 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8804 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8805 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8807 tw32(GRC_MODE, grc_mode);
8810 if (tg3_flag(tp, 57765_CLASS)) {
8811 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8812 u32 grc_mode = tr32(GRC_MODE);
8814 /* Access the lower 1K of PL PCIE block registers. */
8815 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8816 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8818 val = tr32(TG3_PCIE_TLDLPL_PORT +
8819 TG3_PCIE_PL_LO_PHYCTL5);
8820 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8821 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8823 tw32(GRC_MODE, grc_mode);
8826 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8827 u32 grc_mode = tr32(GRC_MODE);
8829 /* Access the lower 1K of DL PCIE block registers. */
8830 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8831 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8833 val = tr32(TG3_PCIE_TLDLPL_PORT +
8834 TG3_PCIE_DL_LO_FTSMAX);
8835 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8836 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8837 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8839 tw32(GRC_MODE, grc_mode);
8842 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8843 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8844 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8845 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8848 /* This works around an issue with Athlon chipsets on
8849 * B3 tigon3 silicon. This bit has no effect on any
8850 * other revision. But do not set this on PCI Express
8851 * chips and don't even touch the clocks if the CPMU is present.
8853 if (!tg3_flag(tp, CPMU_PRESENT)) {
8854 if (!tg3_flag(tp, PCI_EXPRESS))
8855 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8856 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8859 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8860 tg3_flag(tp, PCIX_MODE)) {
8861 val = tr32(TG3PCI_PCISTATE);
8862 val |= PCISTATE_RETRY_SAME_DMA;
8863 tw32(TG3PCI_PCISTATE, val);
8866 if (tg3_flag(tp, ENABLE_APE)) {
8867 /* Allow reads and writes to the
8868 * APE register and memory space.
8870 val = tr32(TG3PCI_PCISTATE);
8871 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8872 PCISTATE_ALLOW_APE_SHMEM_WR |
8873 PCISTATE_ALLOW_APE_PSPACE_WR;
8874 tw32(TG3PCI_PCISTATE, val);
8877 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8878 /* Enable some hw fixes. */
8879 val = tr32(TG3PCI_MSI_DATA);
8880 val |= (1 << 26) | (1 << 28) | (1 << 29);
8881 tw32(TG3PCI_MSI_DATA, val);
8884 /* Descriptor ring init may make accesses to the
8885 * NIC SRAM area to setup the TX descriptors, so we
8886 * can only do this after the hardware has been
8887 * successfully reset.
8889 err = tg3_init_rings(tp);
8893 if (tg3_flag(tp, 57765_PLUS)) {
8894 val = tr32(TG3PCI_DMA_RW_CTRL) &
8895 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8896 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8897 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8898 if (!tg3_flag(tp, 57765_CLASS) &&
8899 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8900 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8901 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8902 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8903 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8904 /* This value is determined during the probe time DMA
8905 * engine test, tg3_test_dma.
8907 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8910 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8911 GRC_MODE_4X_NIC_SEND_RINGS |
8912 GRC_MODE_NO_TX_PHDR_CSUM |
8913 GRC_MODE_NO_RX_PHDR_CSUM);
8914 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8916 /* Pseudo-header checksum is done by hardware logic and not
8917 * the offload processers, so make the chip do the pseudo-
8918 * header checksums on receive. For transmit it is more
8919 * convenient to do the pseudo-header checksum in software
8920 * as Linux does that on transmit for us in all cases.
8922 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8926 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8928 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8929 val = tr32(GRC_MISC_CFG);
8931 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8932 tw32(GRC_MISC_CFG, val);
8934 /* Initialize MBUF/DESC pool. */
8935 if (tg3_flag(tp, 5750_PLUS)) {
8937 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8938 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8940 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8942 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8943 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8944 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8945 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8948 fw_len = tp->fw_len;
8949 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8950 tw32(BUFMGR_MB_POOL_ADDR,
8951 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8952 tw32(BUFMGR_MB_POOL_SIZE,
8953 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8956 if (tp->dev->mtu <= ETH_DATA_LEN) {
8957 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8958 tp->bufmgr_config.mbuf_read_dma_low_water);
8959 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8960 tp->bufmgr_config.mbuf_mac_rx_low_water);
8961 tw32(BUFMGR_MB_HIGH_WATER,
8962 tp->bufmgr_config.mbuf_high_water);
8964 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8965 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8966 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8967 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8968 tw32(BUFMGR_MB_HIGH_WATER,
8969 tp->bufmgr_config.mbuf_high_water_jumbo);
8971 tw32(BUFMGR_DMA_LOW_WATER,
8972 tp->bufmgr_config.dma_low_water);
8973 tw32(BUFMGR_DMA_HIGH_WATER,
8974 tp->bufmgr_config.dma_high_water);
8976 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8978 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8980 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8981 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8982 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8983 tw32(BUFMGR_MODE, val);
8984 for (i = 0; i < 2000; i++) {
8985 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8990 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8994 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8995 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8997 tg3_setup_rxbd_thresholds(tp);
8999 /* Initialize TG3_BDINFO's at:
9000 * RCVDBDI_STD_BD: standard eth size rx ring
9001 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9002 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9005 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9006 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9007 * ring attribute flags
9008 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9010 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9011 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9013 * The size of each ring is fixed in the firmware, but the location is
9016 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
9017 ((u64) tpr->rx_std_mapping >> 32));
9018 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
9019 ((u64) tpr->rx_std_mapping & 0xffffffff));
9020 if (!tg3_flag(tp, 5717_PLUS))
9021 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
9022 NIC_SRAM_RX_BUFFER_DESC);
9024 /* Disable the mini ring */
9025 if (!tg3_flag(tp, 5705_PLUS))
9026 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
9027 BDINFO_FLAGS_DISABLED);
9029 /* Program the jumbo buffer descriptor ring control
9030 * blocks on those devices that have them.
9032 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
9033 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
9035 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
9036 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
9037 ((u64) tpr->rx_jmb_mapping >> 32));
9038 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
9039 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
9040 val = TG3_RX_JMB_RING_SIZE(tp) <<
9041 BDINFO_FLAGS_MAXLEN_SHIFT;
9042 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
9043 val | BDINFO_FLAGS_USE_EXT_RECV);
9044 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
9045 tg3_flag(tp, 57765_CLASS))
9046 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
9047 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
9049 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
9050 BDINFO_FLAGS_DISABLED);
9053 if (tg3_flag(tp, 57765_PLUS)) {
9054 val = TG3_RX_STD_RING_SIZE(tp);
9055 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
9056 val |= (TG3_RX_STD_DMA_SZ << 2);
9058 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
9060 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
9062 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
9064 tpr->rx_std_prod_idx = tp->rx_pending;
9065 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
9067 tpr->rx_jmb_prod_idx =
9068 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
9069 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
9071 tg3_rings_reset(tp);
9073 /* Initialize MAC address and backoff seed. */
9074 __tg3_set_mac_addr(tp, 0);
9076 /* MTU + ethernet header + FCS + optional VLAN tag */
9077 tw32(MAC_RX_MTU_SIZE,
9078 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
9080 /* The slot time is changed by tg3_setup_phy if we
9081 * run at gigabit with half duplex.
9083 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
9084 (6 << TX_LENGTHS_IPG_SHIFT) |
9085 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
9087 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
9088 val |= tr32(MAC_TX_LENGTHS) &
9089 (TX_LENGTHS_JMB_FRM_LEN_MSK |
9090 TX_LENGTHS_CNT_DWN_VAL_MSK);
9092 tw32(MAC_TX_LENGTHS, val);
9094 /* Receive rules. */
9095 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
9096 tw32(RCVLPC_CONFIG, 0x0181);
9098 /* Calculate RDMAC_MODE setting early, we need it to determine
9099 * the RCVLPC_STATE_ENABLE mask.
9101 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
9102 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
9103 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
9104 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
9105 RDMAC_MODE_LNGREAD_ENAB);
9107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9108 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
9110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9113 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
9114 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
9115 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
9117 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9118 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
9119 if (tg3_flag(tp, TSO_CAPABLE) &&
9120 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
9121 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
9122 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
9123 !tg3_flag(tp, IS_5788)) {
9124 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
9128 if (tg3_flag(tp, PCI_EXPRESS))
9129 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
9131 if (tg3_flag(tp, HW_TSO_1) ||
9132 tg3_flag(tp, HW_TSO_2) ||
9133 tg3_flag(tp, HW_TSO_3))
9134 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
9136 if (tg3_flag(tp, 57765_PLUS) ||
9137 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9138 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9139 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
9141 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
9142 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
9144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9145 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9146 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9147 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9148 tg3_flag(tp, 57765_PLUS)) {
9149 val = tr32(TG3_RDMA_RSRVCTRL_REG);
9150 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) {
9151 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
9152 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
9153 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
9154 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
9155 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
9156 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
9158 tw32(TG3_RDMA_RSRVCTRL_REG,
9159 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
9162 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9163 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9164 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9165 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
9166 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
9167 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
9170 /* Receive/send statistics. */
9171 if (tg3_flag(tp, 5750_PLUS)) {
9172 val = tr32(RCVLPC_STATS_ENABLE);
9173 val &= ~RCVLPC_STATSENAB_DACK_FIX;
9174 tw32(RCVLPC_STATS_ENABLE, val);
9175 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
9176 tg3_flag(tp, TSO_CAPABLE)) {
9177 val = tr32(RCVLPC_STATS_ENABLE);
9178 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
9179 tw32(RCVLPC_STATS_ENABLE, val);
9181 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
9183 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
9184 tw32(SNDDATAI_STATSENAB, 0xffffff);
9185 tw32(SNDDATAI_STATSCTRL,
9186 (SNDDATAI_SCTRL_ENABLE |
9187 SNDDATAI_SCTRL_FASTUPD));
9189 /* Setup host coalescing engine. */
9190 tw32(HOSTCC_MODE, 0);
9191 for (i = 0; i < 2000; i++) {
9192 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
9197 __tg3_set_coalesce(tp, &tp->coal);
9199 if (!tg3_flag(tp, 5705_PLUS)) {
9200 /* Status/statistics block address. See tg3_timer,
9201 * the tg3_periodic_fetch_stats call there, and
9202 * tg3_get_stats to see how this works for 5705/5750 chips.
9204 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9205 ((u64) tp->stats_mapping >> 32));
9206 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9207 ((u64) tp->stats_mapping & 0xffffffff));
9208 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
9210 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
9212 /* Clear statistics and status block memory areas */
9213 for (i = NIC_SRAM_STATS_BLK;
9214 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
9216 tg3_write_mem(tp, i, 0);
9221 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
9223 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
9224 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
9225 if (!tg3_flag(tp, 5705_PLUS))
9226 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
9228 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9229 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
9230 /* reset to prevent losing 1st rx packet intermittently */
9231 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9235 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9236 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
9237 MAC_MODE_FHDE_ENABLE;
9238 if (tg3_flag(tp, ENABLE_APE))
9239 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
9240 if (!tg3_flag(tp, 5705_PLUS) &&
9241 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9242 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
9243 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
9244 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
9247 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9248 * If TG3_FLAG_IS_NIC is zero, we should read the
9249 * register to preserve the GPIO settings for LOMs. The GPIOs,
9250 * whether used as inputs or outputs, are set by boot code after
9253 if (!tg3_flag(tp, IS_NIC)) {
9256 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
9257 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
9258 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
9260 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9261 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
9262 GRC_LCLCTRL_GPIO_OUTPUT3;
9264 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9265 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
9267 tp->grc_local_ctrl &= ~gpio_mask;
9268 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
9270 /* GPIO1 must be driven high for eeprom write protect */
9271 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9272 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9273 GRC_LCLCTRL_GPIO_OUTPUT1);
9275 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9278 if (tg3_flag(tp, USING_MSIX)) {
9279 val = tr32(MSGINT_MODE);
9280 val |= MSGINT_MODE_ENABLE;
9281 if (tp->irq_cnt > 1)
9282 val |= MSGINT_MODE_MULTIVEC_EN;
9283 if (!tg3_flag(tp, 1SHOT_MSI))
9284 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
9285 tw32(MSGINT_MODE, val);
9288 if (!tg3_flag(tp, 5705_PLUS)) {
9289 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
9293 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
9294 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
9295 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
9296 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
9297 WDMAC_MODE_LNGREAD_ENAB);
9299 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9300 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
9301 if (tg3_flag(tp, TSO_CAPABLE) &&
9302 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
9303 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
9305 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
9306 !tg3_flag(tp, IS_5788)) {
9307 val |= WDMAC_MODE_RX_ACCEL;
9311 /* Enable host coalescing bug fix */
9312 if (tg3_flag(tp, 5755_PLUS))
9313 val |= WDMAC_MODE_STATUS_TAG_FIX;
9315 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9316 val |= WDMAC_MODE_BURST_ALL_DATA;
9318 tw32_f(WDMAC_MODE, val);
9321 if (tg3_flag(tp, PCIX_MODE)) {
9324 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9327 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
9328 pcix_cmd |= PCI_X_CMD_READ_2K;
9329 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9330 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
9331 pcix_cmd |= PCI_X_CMD_READ_2K;
9333 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9337 tw32_f(RDMAC_MODE, rdmac_mode);
9340 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
9341 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
9342 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
9345 if (i < TG3_NUM_RDMA_CHANNELS) {
9346 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9347 val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;
9348 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9349 tg3_flag_set(tp, 5719_RDMA_BUG);
9353 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
9354 if (!tg3_flag(tp, 5705_PLUS))
9355 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9359 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
9361 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
9363 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
9364 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
9365 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
9366 if (tg3_flag(tp, LRG_PROD_RING_CAP))
9367 val |= RCVDBDI_MODE_LRG_RING_SZ;
9368 tw32(RCVDBDI_MODE, val);
9369 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
9370 if (tg3_flag(tp, HW_TSO_1) ||
9371 tg3_flag(tp, HW_TSO_2) ||
9372 tg3_flag(tp, HW_TSO_3))
9373 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
9374 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
9375 if (tg3_flag(tp, ENABLE_TSS))
9376 val |= SNDBDI_MODE_MULTI_TXQ_EN;
9377 tw32(SNDBDI_MODE, val);
9378 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
9380 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9381 err = tg3_load_5701_a0_firmware_fix(tp);
9386 if (tg3_flag(tp, TSO_CAPABLE)) {
9387 err = tg3_load_tso_firmware(tp);
9392 tp->tx_mode = TX_MODE_ENABLE;
9394 if (tg3_flag(tp, 5755_PLUS) ||
9395 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9396 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
9398 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9399 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
9400 tp->tx_mode &= ~val;
9401 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
9404 tw32_f(MAC_TX_MODE, tp->tx_mode);
9407 if (tg3_flag(tp, ENABLE_RSS)) {
9408 tg3_rss_write_indir_tbl(tp);
9410 /* Setup the "secret" hash key. */
9411 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
9412 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
9413 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
9414 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
9415 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
9416 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
9417 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
9418 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
9419 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
9420 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
9423 tp->rx_mode = RX_MODE_ENABLE;
9424 if (tg3_flag(tp, 5755_PLUS))
9425 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
9427 if (tg3_flag(tp, ENABLE_RSS))
9428 tp->rx_mode |= RX_MODE_RSS_ENABLE |
9429 RX_MODE_RSS_ITBL_HASH_BITS_7 |
9430 RX_MODE_RSS_IPV6_HASH_EN |
9431 RX_MODE_RSS_TCP_IPV6_HASH_EN |
9432 RX_MODE_RSS_IPV4_HASH_EN |
9433 RX_MODE_RSS_TCP_IPV4_HASH_EN;
9435 tw32_f(MAC_RX_MODE, tp->rx_mode);
9438 tw32(MAC_LED_CTRL, tp->led_ctrl);
9440 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
9441 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9442 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9445 tw32_f(MAC_RX_MODE, tp->rx_mode);
9448 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9449 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
9450 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
9451 /* Set drive transmission level to 1.2V */
9452 /* only if the signal pre-emphasis bit is not set */
9453 val = tr32(MAC_SERDES_CFG);
9456 tw32(MAC_SERDES_CFG, val);
9458 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9459 tw32(MAC_SERDES_CFG, 0x616000);
9462 /* Prevent chip from dropping frames when flow control
9465 if (tg3_flag(tp, 57765_CLASS))
9469 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
9471 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9472 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
9473 /* Use hardware link auto-negotiation */
9474 tg3_flag_set(tp, HW_AUTONEG);
9477 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9478 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9481 tmp = tr32(SERDES_RX_CTRL);
9482 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9483 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9484 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9485 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9488 if (!tg3_flag(tp, USE_PHYLIB)) {
9489 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9490 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
9492 err = tg3_setup_phy(tp, 0);
9496 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9497 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
9500 /* Clear CRC stats. */
9501 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9502 tg3_writephy(tp, MII_TG3_TEST1,
9503 tmp | MII_TG3_TEST1_CRC_EN);
9504 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
9509 __tg3_set_rx_mode(tp->dev);
9511 /* Initialize receive rules. */
9512 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9513 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9514 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9515 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9517 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
9521 if (tg3_flag(tp, ENABLE_ASF))
9525 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9527 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9529 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9531 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9533 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9535 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9537 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9539 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9541 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9543 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9545 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9547 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9549 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9551 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9559 if (tg3_flag(tp, ENABLE_APE))
9560 /* Write our heartbeat update interval to APE. */
9561 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9562 APE_HOST_HEARTBEAT_INT_DISABLE);
9564 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9569 /* Called at device open time to get the chip ready for
9570 * packet processing. Invoked with tp->lock held.
9572 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9574 tg3_switch_clocks(tp);
9576 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9578 return tg3_reset_hw(tp, reset_phy);
9581 #if IS_ENABLED(CONFIG_HWMON)
9582 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
9586 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
9587 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
9589 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
9592 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
9593 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
9594 memset(ocir, 0, TG3_OCIR_LEN);
9598 /* sysfs attributes for hwmon */
9599 static ssize_t tg3_show_temp(struct device *dev,
9600 struct device_attribute *devattr, char *buf)
9602 struct pci_dev *pdev = to_pci_dev(dev);
9603 struct net_device *netdev = pci_get_drvdata(pdev);
9604 struct tg3 *tp = netdev_priv(netdev);
9605 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
9608 spin_lock_bh(&tp->lock);
9609 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
9610 sizeof(temperature));
9611 spin_unlock_bh(&tp->lock);
9612 return sprintf(buf, "%u\n", temperature);
9616 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
9617 TG3_TEMP_SENSOR_OFFSET);
9618 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
9619 TG3_TEMP_CAUTION_OFFSET);
9620 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
9621 TG3_TEMP_MAX_OFFSET);
9623 static struct attribute *tg3_attributes[] = {
9624 &sensor_dev_attr_temp1_input.dev_attr.attr,
9625 &sensor_dev_attr_temp1_crit.dev_attr.attr,
9626 &sensor_dev_attr_temp1_max.dev_attr.attr,
9630 static const struct attribute_group tg3_group = {
9631 .attrs = tg3_attributes,
9636 static void tg3_hwmon_close(struct tg3 *tp)
9638 #if IS_ENABLED(CONFIG_HWMON)
9639 if (tp->hwmon_dev) {
9640 hwmon_device_unregister(tp->hwmon_dev);
9641 tp->hwmon_dev = NULL;
9642 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
9647 static void tg3_hwmon_open(struct tg3 *tp)
9649 #if IS_ENABLED(CONFIG_HWMON)
9652 struct pci_dev *pdev = tp->pdev;
9653 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
9655 tg3_sd_scan_scratchpad(tp, ocirs);
9657 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
9658 if (!ocirs[i].src_data_length)
9661 size += ocirs[i].src_hdr_length;
9662 size += ocirs[i].src_data_length;
9668 /* Register hwmon sysfs hooks */
9669 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
9671 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
9675 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
9676 if (IS_ERR(tp->hwmon_dev)) {
9677 tp->hwmon_dev = NULL;
9678 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
9679 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
9685 #define TG3_STAT_ADD32(PSTAT, REG) \
9686 do { u32 __val = tr32(REG); \
9687 (PSTAT)->low += __val; \
9688 if ((PSTAT)->low < __val) \
9689 (PSTAT)->high += 1; \
9692 static void tg3_periodic_fetch_stats(struct tg3 *tp)
9694 struct tg3_hw_stats *sp = tp->hw_stats;
9696 if (!netif_carrier_ok(tp->dev))
9699 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9700 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9701 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9702 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9703 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9704 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9705 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9706 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9707 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9708 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9709 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9710 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9711 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9712 if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&
9713 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
9714 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
9717 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9718 val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;
9719 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
9720 tg3_flag_clear(tp, 5719_RDMA_BUG);
9723 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9724 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9725 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9726 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9727 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9728 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9729 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9730 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9731 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9732 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9733 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9734 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9735 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9736 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
9738 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
9739 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9740 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9741 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
9742 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9744 u32 val = tr32(HOSTCC_FLOW_ATTN);
9745 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9747 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9748 sp->rx_discards.low += val;
9749 if (sp->rx_discards.low < val)
9750 sp->rx_discards.high += 1;
9752 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9754 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
9757 static void tg3_chk_missed_msi(struct tg3 *tp)
9761 for (i = 0; i < tp->irq_cnt; i++) {
9762 struct tg3_napi *tnapi = &tp->napi[i];
9764 if (tg3_has_work(tnapi)) {
9765 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9766 tnapi->last_tx_cons == tnapi->tx_cons) {
9767 if (tnapi->chk_msi_cnt < 1) {
9768 tnapi->chk_msi_cnt++;
9774 tnapi->chk_msi_cnt = 0;
9775 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9776 tnapi->last_tx_cons = tnapi->tx_cons;
9780 static void tg3_timer(unsigned long __opaque)
9782 struct tg3 *tp = (struct tg3 *) __opaque;
9784 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
9787 spin_lock(&tp->lock);
9789 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9790 tg3_flag(tp, 57765_CLASS))
9791 tg3_chk_missed_msi(tp);
9793 if (!tg3_flag(tp, TAGGED_STATUS)) {
9794 /* All of this garbage is because when using non-tagged
9795 * IRQ status the mailbox/status_block protocol the chip
9796 * uses with the cpu is race prone.
9798 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9799 tw32(GRC_LOCAL_CTRL,
9800 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9802 tw32(HOSTCC_MODE, tp->coalesce_mode |
9803 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9806 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9807 spin_unlock(&tp->lock);
9808 tg3_reset_task_schedule(tp);
9813 /* This part only runs once per second. */
9814 if (!--tp->timer_counter) {
9815 if (tg3_flag(tp, 5705_PLUS))
9816 tg3_periodic_fetch_stats(tp);
9818 if (tp->setlpicnt && !--tp->setlpicnt)
9819 tg3_phy_eee_enable(tp);
9821 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9825 mac_stat = tr32(MAC_STATUS);
9828 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9829 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9831 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9835 tg3_setup_phy(tp, 0);
9836 } else if (tg3_flag(tp, POLL_SERDES)) {
9837 u32 mac_stat = tr32(MAC_STATUS);
9840 if (netif_carrier_ok(tp->dev) &&
9841 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9844 if (!netif_carrier_ok(tp->dev) &&
9845 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9846 MAC_STATUS_SIGNAL_DET))) {
9850 if (!tp->serdes_counter) {
9853 ~MAC_MODE_PORT_MODE_MASK));
9855 tw32_f(MAC_MODE, tp->mac_mode);
9858 tg3_setup_phy(tp, 0);
9860 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9861 tg3_flag(tp, 5780_CLASS)) {
9862 tg3_serdes_parallel_detect(tp);
9865 tp->timer_counter = tp->timer_multiplier;
9868 /* Heartbeat is only sent once every 2 seconds.
9870 * The heartbeat is to tell the ASF firmware that the host
9871 * driver is still alive. In the event that the OS crashes,
9872 * ASF needs to reset the hardware to free up the FIFO space
9873 * that may be filled with rx packets destined for the host.
9874 * If the FIFO is full, ASF will no longer function properly.
9876 * Unintended resets have been reported on real time kernels
9877 * where the timer doesn't run on time. Netpoll will also have
9880 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9881 * to check the ring condition when the heartbeat is expiring
9882 * before doing the reset. This will prevent most unintended
9885 if (!--tp->asf_counter) {
9886 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9887 tg3_wait_for_event_ack(tp);
9889 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9890 FWCMD_NICDRV_ALIVE3);
9891 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9892 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9893 TG3_FW_UPDATE_TIMEOUT_SEC);
9895 tg3_generate_fw_event(tp);
9897 tp->asf_counter = tp->asf_multiplier;
9900 spin_unlock(&tp->lock);
9903 tp->timer.expires = jiffies + tp->timer_offset;
9904 add_timer(&tp->timer);
9907 static void __devinit tg3_timer_init(struct tg3 *tp)
9909 if (tg3_flag(tp, TAGGED_STATUS) &&
9910 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9911 !tg3_flag(tp, 57765_CLASS))
9912 tp->timer_offset = HZ;
9914 tp->timer_offset = HZ / 10;
9916 BUG_ON(tp->timer_offset > HZ);
9918 tp->timer_multiplier = (HZ / tp->timer_offset);
9919 tp->asf_multiplier = (HZ / tp->timer_offset) *
9920 TG3_FW_UPDATE_FREQ_SEC;
9922 init_timer(&tp->timer);
9923 tp->timer.data = (unsigned long) tp;
9924 tp->timer.function = tg3_timer;
9927 static void tg3_timer_start(struct tg3 *tp)
9929 tp->asf_counter = tp->asf_multiplier;
9930 tp->timer_counter = tp->timer_multiplier;
9932 tp->timer.expires = jiffies + tp->timer_offset;
9933 add_timer(&tp->timer);
9936 static void tg3_timer_stop(struct tg3 *tp)
9938 del_timer_sync(&tp->timer);
9941 /* Restart hardware after configuration changes, self-test, etc.
9942 * Invoked with tp->lock held.
9944 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
9945 __releases(tp->lock)
9946 __acquires(tp->lock)
9950 err = tg3_init_hw(tp, reset_phy);
9953 "Failed to re-initialize device, aborting\n");
9954 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9955 tg3_full_unlock(tp);
9958 tg3_napi_enable(tp);
9960 tg3_full_lock(tp, 0);
9965 static void tg3_reset_task(struct work_struct *work)
9967 struct tg3 *tp = container_of(work, struct tg3, reset_task);
9970 tg3_full_lock(tp, 0);
9972 if (!netif_running(tp->dev)) {
9973 tg3_flag_clear(tp, RESET_TASK_PENDING);
9974 tg3_full_unlock(tp);
9978 tg3_full_unlock(tp);
9984 tg3_full_lock(tp, 1);
9986 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
9987 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9988 tp->write32_rx_mbox = tg3_write_flush_reg32;
9989 tg3_flag_set(tp, MBOX_WRITE_REORDER);
9990 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
9993 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
9994 err = tg3_init_hw(tp, 1);
9998 tg3_netif_start(tp);
10001 tg3_full_unlock(tp);
10006 tg3_flag_clear(tp, RESET_TASK_PENDING);
10009 static int tg3_request_irq(struct tg3 *tp, int irq_num)
10012 unsigned long flags;
10014 struct tg3_napi *tnapi = &tp->napi[irq_num];
10016 if (tp->irq_cnt == 1)
10017 name = tp->dev->name;
10019 name = &tnapi->irq_lbl[0];
10020 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
10021 name[IFNAMSIZ-1] = 0;
10024 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
10026 if (tg3_flag(tp, 1SHOT_MSI))
10027 fn = tg3_msi_1shot;
10030 fn = tg3_interrupt;
10031 if (tg3_flag(tp, TAGGED_STATUS))
10032 fn = tg3_interrupt_tagged;
10033 flags = IRQF_SHARED;
10036 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
10039 static int tg3_test_interrupt(struct tg3 *tp)
10041 struct tg3_napi *tnapi = &tp->napi[0];
10042 struct net_device *dev = tp->dev;
10043 int err, i, intr_ok = 0;
10046 if (!netif_running(dev))
10049 tg3_disable_ints(tp);
10051 free_irq(tnapi->irq_vec, tnapi);
10054 * Turn off MSI one shot mode. Otherwise this test has no
10055 * observable way to know whether the interrupt was delivered.
10057 if (tg3_flag(tp, 57765_PLUS)) {
10058 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
10059 tw32(MSGINT_MODE, val);
10062 err = request_irq(tnapi->irq_vec, tg3_test_isr,
10063 IRQF_SHARED, dev->name, tnapi);
10067 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
10068 tg3_enable_ints(tp);
10070 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10073 for (i = 0; i < 5; i++) {
10074 u32 int_mbox, misc_host_ctrl;
10076 int_mbox = tr32_mailbox(tnapi->int_mbox);
10077 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
10079 if ((int_mbox != 0) ||
10080 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
10085 if (tg3_flag(tp, 57765_PLUS) &&
10086 tnapi->hw_status->status_tag != tnapi->last_tag)
10087 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
10092 tg3_disable_ints(tp);
10094 free_irq(tnapi->irq_vec, tnapi);
10096 err = tg3_request_irq(tp, 0);
10102 /* Reenable MSI one shot mode. */
10103 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
10104 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
10105 tw32(MSGINT_MODE, val);
10113 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
10114 * successfully restored
10116 static int tg3_test_msi(struct tg3 *tp)
10121 if (!tg3_flag(tp, USING_MSI))
10124 /* Turn off SERR reporting in case MSI terminates with Master
10127 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10128 pci_write_config_word(tp->pdev, PCI_COMMAND,
10129 pci_cmd & ~PCI_COMMAND_SERR);
10131 err = tg3_test_interrupt(tp);
10133 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10138 /* other failures */
10142 /* MSI test failed, go back to INTx mode */
10143 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
10144 "to INTx mode. Please report this failure to the PCI "
10145 "maintainer and include system chipset information\n");
10147 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
10149 pci_disable_msi(tp->pdev);
10151 tg3_flag_clear(tp, USING_MSI);
10152 tp->napi[0].irq_vec = tp->pdev->irq;
10154 err = tg3_request_irq(tp, 0);
10158 /* Need to reset the chip because the MSI cycle may have terminated
10159 * with Master Abort.
10161 tg3_full_lock(tp, 1);
10163 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10164 err = tg3_init_hw(tp, 1);
10166 tg3_full_unlock(tp);
10169 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
10174 static int tg3_request_firmware(struct tg3 *tp)
10176 const __be32 *fw_data;
10178 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
10179 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
10184 fw_data = (void *)tp->fw->data;
10186 /* Firmware blob starts with version numbers, followed by
10187 * start address and _full_ length including BSS sections
10188 * (which must be longer than the actual data, of course
10191 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
10192 if (tp->fw_len < (tp->fw->size - 12)) {
10193 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
10194 tp->fw_len, tp->fw_needed);
10195 release_firmware(tp->fw);
10200 /* We no longer need firmware; we have it. */
10201 tp->fw_needed = NULL;
10205 static u32 tg3_irq_count(struct tg3 *tp)
10207 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
10210 /* We want as many rx rings enabled as there are cpus.
10211 * In multiqueue MSI-X mode, the first MSI-X vector
10212 * only deals with link interrupts, etc, so we add
10213 * one to the number of vectors we are requesting.
10215 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
10221 static bool tg3_enable_msix(struct tg3 *tp)
10224 struct msix_entry msix_ent[tp->irq_max];
10226 tp->rxq_cnt = netif_get_num_default_rss_queues();
10227 if (tp->rxq_cnt > tp->rxq_max)
10228 tp->rxq_cnt = tp->rxq_max;
10229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
10230 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
10231 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
10233 tp->irq_cnt = tg3_irq_count(tp);
10235 for (i = 0; i < tp->irq_max; i++) {
10236 msix_ent[i].entry = i;
10237 msix_ent[i].vector = 0;
10240 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
10243 } else if (rc != 0) {
10244 if (pci_enable_msix(tp->pdev, msix_ent, rc))
10246 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
10249 tp->rxq_cnt = max(rc - 1, 1);
10251 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
10254 for (i = 0; i < tp->irq_max; i++)
10255 tp->napi[i].irq_vec = msix_ent[i].vector;
10257 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
10258 pci_disable_msix(tp->pdev);
10262 if (tp->irq_cnt == 1)
10265 tg3_flag_set(tp, ENABLE_RSS);
10267 if (tp->txq_cnt > 1)
10268 tg3_flag_set(tp, ENABLE_TSS);
10270 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
10275 static void tg3_ints_init(struct tg3 *tp)
10277 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
10278 !tg3_flag(tp, TAGGED_STATUS)) {
10279 /* All MSI supporting chips should support tagged
10280 * status. Assert that this is the case.
10282 netdev_warn(tp->dev,
10283 "MSI without TAGGED_STATUS? Not using MSI\n");
10287 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
10288 tg3_flag_set(tp, USING_MSIX);
10289 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
10290 tg3_flag_set(tp, USING_MSI);
10292 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
10293 u32 msi_mode = tr32(MSGINT_MODE);
10294 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
10295 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
10296 if (!tg3_flag(tp, 1SHOT_MSI))
10297 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
10298 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
10301 if (!tg3_flag(tp, USING_MSIX)) {
10303 tp->napi[0].irq_vec = tp->pdev->irq;
10306 if (tp->irq_cnt == 1) {
10309 netif_set_real_num_tx_queues(tp->dev, 1);
10310 netif_set_real_num_rx_queues(tp->dev, 1);
10314 static void tg3_ints_fini(struct tg3 *tp)
10316 if (tg3_flag(tp, USING_MSIX))
10317 pci_disable_msix(tp->pdev);
10318 else if (tg3_flag(tp, USING_MSI))
10319 pci_disable_msi(tp->pdev);
10320 tg3_flag_clear(tp, USING_MSI);
10321 tg3_flag_clear(tp, USING_MSIX);
10322 tg3_flag_clear(tp, ENABLE_RSS);
10323 tg3_flag_clear(tp, ENABLE_TSS);
10326 static int tg3_open(struct net_device *dev)
10328 struct tg3 *tp = netdev_priv(dev);
10331 if (tp->fw_needed) {
10332 err = tg3_request_firmware(tp);
10333 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
10337 netdev_warn(tp->dev, "TSO capability disabled\n");
10338 tg3_flag_clear(tp, TSO_CAPABLE);
10339 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
10340 netdev_notice(tp->dev, "TSO capability restored\n");
10341 tg3_flag_set(tp, TSO_CAPABLE);
10345 netif_carrier_off(tp->dev);
10347 err = tg3_power_up(tp);
10351 tg3_full_lock(tp, 0);
10353 tg3_disable_ints(tp);
10354 tg3_flag_clear(tp, INIT_COMPLETE);
10356 tg3_full_unlock(tp);
10359 * Setup interrupts first so we know how
10360 * many NAPI resources to allocate
10364 tg3_rss_check_indir_tbl(tp);
10366 /* The placement of this call is tied
10367 * to the setup and use of Host TX descriptors.
10369 err = tg3_alloc_consistent(tp);
10375 tg3_napi_enable(tp);
10377 for (i = 0; i < tp->irq_cnt; i++) {
10378 struct tg3_napi *tnapi = &tp->napi[i];
10379 err = tg3_request_irq(tp, i);
10381 for (i--; i >= 0; i--) {
10382 tnapi = &tp->napi[i];
10383 free_irq(tnapi->irq_vec, tnapi);
10389 tg3_full_lock(tp, 0);
10391 err = tg3_init_hw(tp, 1);
10393 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10394 tg3_free_rings(tp);
10397 tg3_full_unlock(tp);
10402 if (tg3_flag(tp, USING_MSI)) {
10403 err = tg3_test_msi(tp);
10406 tg3_full_lock(tp, 0);
10407 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10408 tg3_free_rings(tp);
10409 tg3_full_unlock(tp);
10414 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
10415 u32 val = tr32(PCIE_TRANSACTION_CFG);
10417 tw32(PCIE_TRANSACTION_CFG,
10418 val | PCIE_TRANS_CFG_1SHOT_MSI);
10424 tg3_hwmon_open(tp);
10426 tg3_full_lock(tp, 0);
10428 tg3_timer_start(tp);
10429 tg3_flag_set(tp, INIT_COMPLETE);
10430 tg3_enable_ints(tp);
10432 tg3_full_unlock(tp);
10434 netif_tx_start_all_queues(dev);
10437 * Reset loopback feature if it was turned on while the device was down
10438 * make sure that it's installed properly now.
10440 if (dev->features & NETIF_F_LOOPBACK)
10441 tg3_set_loopback(dev, dev->features);
10446 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10447 struct tg3_napi *tnapi = &tp->napi[i];
10448 free_irq(tnapi->irq_vec, tnapi);
10452 tg3_napi_disable(tp);
10454 tg3_free_consistent(tp);
10458 tg3_frob_aux_power(tp, false);
10459 pci_set_power_state(tp->pdev, PCI_D3hot);
10463 static int tg3_close(struct net_device *dev)
10466 struct tg3 *tp = netdev_priv(dev);
10468 tg3_napi_disable(tp);
10469 tg3_reset_task_cancel(tp);
10471 netif_tx_stop_all_queues(dev);
10473 tg3_timer_stop(tp);
10475 tg3_hwmon_close(tp);
10479 tg3_full_lock(tp, 1);
10481 tg3_disable_ints(tp);
10483 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10484 tg3_free_rings(tp);
10485 tg3_flag_clear(tp, INIT_COMPLETE);
10487 tg3_full_unlock(tp);
10489 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10490 struct tg3_napi *tnapi = &tp->napi[i];
10491 free_irq(tnapi->irq_vec, tnapi);
10496 /* Clear stats across close / open calls */
10497 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
10498 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
10502 tg3_free_consistent(tp);
10504 tg3_power_down(tp);
10506 netif_carrier_off(tp->dev);
10511 static inline u64 get_stat64(tg3_stat64_t *val)
10513 return ((u64)val->high << 32) | ((u64)val->low);
10516 static u64 tg3_calc_crc_errors(struct tg3 *tp)
10518 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10520 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10521 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10522 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
10525 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
10526 tg3_writephy(tp, MII_TG3_TEST1,
10527 val | MII_TG3_TEST1_CRC_EN);
10528 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
10532 tp->phy_crc_errors += val;
10534 return tp->phy_crc_errors;
10537 return get_stat64(&hw_stats->rx_fcs_errors);
10540 #define ESTAT_ADD(member) \
10541 estats->member = old_estats->member + \
10542 get_stat64(&hw_stats->member)
10544 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
10546 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
10547 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10549 ESTAT_ADD(rx_octets);
10550 ESTAT_ADD(rx_fragments);
10551 ESTAT_ADD(rx_ucast_packets);
10552 ESTAT_ADD(rx_mcast_packets);
10553 ESTAT_ADD(rx_bcast_packets);
10554 ESTAT_ADD(rx_fcs_errors);
10555 ESTAT_ADD(rx_align_errors);
10556 ESTAT_ADD(rx_xon_pause_rcvd);
10557 ESTAT_ADD(rx_xoff_pause_rcvd);
10558 ESTAT_ADD(rx_mac_ctrl_rcvd);
10559 ESTAT_ADD(rx_xoff_entered);
10560 ESTAT_ADD(rx_frame_too_long_errors);
10561 ESTAT_ADD(rx_jabbers);
10562 ESTAT_ADD(rx_undersize_packets);
10563 ESTAT_ADD(rx_in_length_errors);
10564 ESTAT_ADD(rx_out_length_errors);
10565 ESTAT_ADD(rx_64_or_less_octet_packets);
10566 ESTAT_ADD(rx_65_to_127_octet_packets);
10567 ESTAT_ADD(rx_128_to_255_octet_packets);
10568 ESTAT_ADD(rx_256_to_511_octet_packets);
10569 ESTAT_ADD(rx_512_to_1023_octet_packets);
10570 ESTAT_ADD(rx_1024_to_1522_octet_packets);
10571 ESTAT_ADD(rx_1523_to_2047_octet_packets);
10572 ESTAT_ADD(rx_2048_to_4095_octet_packets);
10573 ESTAT_ADD(rx_4096_to_8191_octet_packets);
10574 ESTAT_ADD(rx_8192_to_9022_octet_packets);
10576 ESTAT_ADD(tx_octets);
10577 ESTAT_ADD(tx_collisions);
10578 ESTAT_ADD(tx_xon_sent);
10579 ESTAT_ADD(tx_xoff_sent);
10580 ESTAT_ADD(tx_flow_control);
10581 ESTAT_ADD(tx_mac_errors);
10582 ESTAT_ADD(tx_single_collisions);
10583 ESTAT_ADD(tx_mult_collisions);
10584 ESTAT_ADD(tx_deferred);
10585 ESTAT_ADD(tx_excessive_collisions);
10586 ESTAT_ADD(tx_late_collisions);
10587 ESTAT_ADD(tx_collide_2times);
10588 ESTAT_ADD(tx_collide_3times);
10589 ESTAT_ADD(tx_collide_4times);
10590 ESTAT_ADD(tx_collide_5times);
10591 ESTAT_ADD(tx_collide_6times);
10592 ESTAT_ADD(tx_collide_7times);
10593 ESTAT_ADD(tx_collide_8times);
10594 ESTAT_ADD(tx_collide_9times);
10595 ESTAT_ADD(tx_collide_10times);
10596 ESTAT_ADD(tx_collide_11times);
10597 ESTAT_ADD(tx_collide_12times);
10598 ESTAT_ADD(tx_collide_13times);
10599 ESTAT_ADD(tx_collide_14times);
10600 ESTAT_ADD(tx_collide_15times);
10601 ESTAT_ADD(tx_ucast_packets);
10602 ESTAT_ADD(tx_mcast_packets);
10603 ESTAT_ADD(tx_bcast_packets);
10604 ESTAT_ADD(tx_carrier_sense_errors);
10605 ESTAT_ADD(tx_discards);
10606 ESTAT_ADD(tx_errors);
10608 ESTAT_ADD(dma_writeq_full);
10609 ESTAT_ADD(dma_write_prioq_full);
10610 ESTAT_ADD(rxbds_empty);
10611 ESTAT_ADD(rx_discards);
10612 ESTAT_ADD(rx_errors);
10613 ESTAT_ADD(rx_threshold_hit);
10615 ESTAT_ADD(dma_readq_full);
10616 ESTAT_ADD(dma_read_prioq_full);
10617 ESTAT_ADD(tx_comp_queue_full);
10619 ESTAT_ADD(ring_set_send_prod_index);
10620 ESTAT_ADD(ring_status_update);
10621 ESTAT_ADD(nic_irqs);
10622 ESTAT_ADD(nic_avoided_irqs);
10623 ESTAT_ADD(nic_tx_threshold_hit);
10625 ESTAT_ADD(mbuf_lwm_thresh_hit);
10628 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
10630 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
10631 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10633 stats->rx_packets = old_stats->rx_packets +
10634 get_stat64(&hw_stats->rx_ucast_packets) +
10635 get_stat64(&hw_stats->rx_mcast_packets) +
10636 get_stat64(&hw_stats->rx_bcast_packets);
10638 stats->tx_packets = old_stats->tx_packets +
10639 get_stat64(&hw_stats->tx_ucast_packets) +
10640 get_stat64(&hw_stats->tx_mcast_packets) +
10641 get_stat64(&hw_stats->tx_bcast_packets);
10643 stats->rx_bytes = old_stats->rx_bytes +
10644 get_stat64(&hw_stats->rx_octets);
10645 stats->tx_bytes = old_stats->tx_bytes +
10646 get_stat64(&hw_stats->tx_octets);
10648 stats->rx_errors = old_stats->rx_errors +
10649 get_stat64(&hw_stats->rx_errors);
10650 stats->tx_errors = old_stats->tx_errors +
10651 get_stat64(&hw_stats->tx_errors) +
10652 get_stat64(&hw_stats->tx_mac_errors) +
10653 get_stat64(&hw_stats->tx_carrier_sense_errors) +
10654 get_stat64(&hw_stats->tx_discards);
10656 stats->multicast = old_stats->multicast +
10657 get_stat64(&hw_stats->rx_mcast_packets);
10658 stats->collisions = old_stats->collisions +
10659 get_stat64(&hw_stats->tx_collisions);
10661 stats->rx_length_errors = old_stats->rx_length_errors +
10662 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10663 get_stat64(&hw_stats->rx_undersize_packets);
10665 stats->rx_over_errors = old_stats->rx_over_errors +
10666 get_stat64(&hw_stats->rxbds_empty);
10667 stats->rx_frame_errors = old_stats->rx_frame_errors +
10668 get_stat64(&hw_stats->rx_align_errors);
10669 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10670 get_stat64(&hw_stats->tx_discards);
10671 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10672 get_stat64(&hw_stats->tx_carrier_sense_errors);
10674 stats->rx_crc_errors = old_stats->rx_crc_errors +
10675 tg3_calc_crc_errors(tp);
10677 stats->rx_missed_errors = old_stats->rx_missed_errors +
10678 get_stat64(&hw_stats->rx_discards);
10680 stats->rx_dropped = tp->rx_dropped;
10681 stats->tx_dropped = tp->tx_dropped;
10684 static int tg3_get_regs_len(struct net_device *dev)
10686 return TG3_REG_BLK_SIZE;
10689 static void tg3_get_regs(struct net_device *dev,
10690 struct ethtool_regs *regs, void *_p)
10692 struct tg3 *tp = netdev_priv(dev);
10696 memset(_p, 0, TG3_REG_BLK_SIZE);
10698 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10701 tg3_full_lock(tp, 0);
10703 tg3_dump_legacy_regs(tp, (u32 *)_p);
10705 tg3_full_unlock(tp);
10708 static int tg3_get_eeprom_len(struct net_device *dev)
10710 struct tg3 *tp = netdev_priv(dev);
10712 return tp->nvram_size;
10715 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10717 struct tg3 *tp = netdev_priv(dev);
10720 u32 i, offset, len, b_offset, b_count;
10723 if (tg3_flag(tp, NO_NVRAM))
10726 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10729 offset = eeprom->offset;
10733 eeprom->magic = TG3_EEPROM_MAGIC;
10736 /* adjustments to start on required 4 byte boundary */
10737 b_offset = offset & 3;
10738 b_count = 4 - b_offset;
10739 if (b_count > len) {
10740 /* i.e. offset=1 len=2 */
10743 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
10746 memcpy(data, ((char *)&val) + b_offset, b_count);
10749 eeprom->len += b_count;
10752 /* read bytes up to the last 4 byte boundary */
10753 pd = &data[eeprom->len];
10754 for (i = 0; i < (len - (len & 3)); i += 4) {
10755 ret = tg3_nvram_read_be32(tp, offset + i, &val);
10760 memcpy(pd + i, &val, 4);
10765 /* read last bytes not ending on 4 byte boundary */
10766 pd = &data[eeprom->len];
10768 b_offset = offset + len - b_count;
10769 ret = tg3_nvram_read_be32(tp, b_offset, &val);
10772 memcpy(pd, &val, b_count);
10773 eeprom->len += b_count;
10778 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10780 struct tg3 *tp = netdev_priv(dev);
10782 u32 offset, len, b_offset, odd_len;
10786 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10789 if (tg3_flag(tp, NO_NVRAM) ||
10790 eeprom->magic != TG3_EEPROM_MAGIC)
10793 offset = eeprom->offset;
10796 if ((b_offset = (offset & 3))) {
10797 /* adjustments to start on required 4 byte boundary */
10798 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10809 /* adjustments to end on required 4 byte boundary */
10811 len = (len + 3) & ~3;
10812 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10818 if (b_offset || odd_len) {
10819 buf = kmalloc(len, GFP_KERNEL);
10823 memcpy(buf, &start, 4);
10825 memcpy(buf+len-4, &end, 4);
10826 memcpy(buf + b_offset, data, eeprom->len);
10829 ret = tg3_nvram_write_block(tp, offset, len, buf);
10837 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10839 struct tg3 *tp = netdev_priv(dev);
10841 if (tg3_flag(tp, USE_PHYLIB)) {
10842 struct phy_device *phydev;
10843 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10845 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10846 return phy_ethtool_gset(phydev, cmd);
10849 cmd->supported = (SUPPORTED_Autoneg);
10851 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10852 cmd->supported |= (SUPPORTED_1000baseT_Half |
10853 SUPPORTED_1000baseT_Full);
10855 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10856 cmd->supported |= (SUPPORTED_100baseT_Half |
10857 SUPPORTED_100baseT_Full |
10858 SUPPORTED_10baseT_Half |
10859 SUPPORTED_10baseT_Full |
10861 cmd->port = PORT_TP;
10863 cmd->supported |= SUPPORTED_FIBRE;
10864 cmd->port = PORT_FIBRE;
10867 cmd->advertising = tp->link_config.advertising;
10868 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10869 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10870 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10871 cmd->advertising |= ADVERTISED_Pause;
10873 cmd->advertising |= ADVERTISED_Pause |
10874 ADVERTISED_Asym_Pause;
10876 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10877 cmd->advertising |= ADVERTISED_Asym_Pause;
10880 if (netif_running(dev) && netif_carrier_ok(dev)) {
10881 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10882 cmd->duplex = tp->link_config.active_duplex;
10883 cmd->lp_advertising = tp->link_config.rmt_adv;
10884 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10885 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
10886 cmd->eth_tp_mdix = ETH_TP_MDI_X;
10888 cmd->eth_tp_mdix = ETH_TP_MDI;
10891 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
10892 cmd->duplex = DUPLEX_UNKNOWN;
10893 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
10895 cmd->phy_address = tp->phy_addr;
10896 cmd->transceiver = XCVR_INTERNAL;
10897 cmd->autoneg = tp->link_config.autoneg;
10903 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10905 struct tg3 *tp = netdev_priv(dev);
10906 u32 speed = ethtool_cmd_speed(cmd);
10908 if (tg3_flag(tp, USE_PHYLIB)) {
10909 struct phy_device *phydev;
10910 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10912 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10913 return phy_ethtool_sset(phydev, cmd);
10916 if (cmd->autoneg != AUTONEG_ENABLE &&
10917 cmd->autoneg != AUTONEG_DISABLE)
10920 if (cmd->autoneg == AUTONEG_DISABLE &&
10921 cmd->duplex != DUPLEX_FULL &&
10922 cmd->duplex != DUPLEX_HALF)
10925 if (cmd->autoneg == AUTONEG_ENABLE) {
10926 u32 mask = ADVERTISED_Autoneg |
10928 ADVERTISED_Asym_Pause;
10930 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10931 mask |= ADVERTISED_1000baseT_Half |
10932 ADVERTISED_1000baseT_Full;
10934 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10935 mask |= ADVERTISED_100baseT_Half |
10936 ADVERTISED_100baseT_Full |
10937 ADVERTISED_10baseT_Half |
10938 ADVERTISED_10baseT_Full |
10941 mask |= ADVERTISED_FIBRE;
10943 if (cmd->advertising & ~mask)
10946 mask &= (ADVERTISED_1000baseT_Half |
10947 ADVERTISED_1000baseT_Full |
10948 ADVERTISED_100baseT_Half |
10949 ADVERTISED_100baseT_Full |
10950 ADVERTISED_10baseT_Half |
10951 ADVERTISED_10baseT_Full);
10953 cmd->advertising &= mask;
10955 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10956 if (speed != SPEED_1000)
10959 if (cmd->duplex != DUPLEX_FULL)
10962 if (speed != SPEED_100 &&
10968 tg3_full_lock(tp, 0);
10970 tp->link_config.autoneg = cmd->autoneg;
10971 if (cmd->autoneg == AUTONEG_ENABLE) {
10972 tp->link_config.advertising = (cmd->advertising |
10973 ADVERTISED_Autoneg);
10974 tp->link_config.speed = SPEED_UNKNOWN;
10975 tp->link_config.duplex = DUPLEX_UNKNOWN;
10977 tp->link_config.advertising = 0;
10978 tp->link_config.speed = speed;
10979 tp->link_config.duplex = cmd->duplex;
10982 if (netif_running(dev))
10983 tg3_setup_phy(tp, 1);
10985 tg3_full_unlock(tp);
10990 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10992 struct tg3 *tp = netdev_priv(dev);
10994 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
10995 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
10996 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
10997 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
11000 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
11002 struct tg3 *tp = netdev_priv(dev);
11004 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
11005 wol->supported = WAKE_MAGIC;
11007 wol->supported = 0;
11009 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
11010 wol->wolopts = WAKE_MAGIC;
11011 memset(&wol->sopass, 0, sizeof(wol->sopass));
11014 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
11016 struct tg3 *tp = netdev_priv(dev);
11017 struct device *dp = &tp->pdev->dev;
11019 if (wol->wolopts & ~WAKE_MAGIC)
11021 if ((wol->wolopts & WAKE_MAGIC) &&
11022 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
11025 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
11027 spin_lock_bh(&tp->lock);
11028 if (device_may_wakeup(dp))
11029 tg3_flag_set(tp, WOL_ENABLE);
11031 tg3_flag_clear(tp, WOL_ENABLE);
11032 spin_unlock_bh(&tp->lock);
11037 static u32 tg3_get_msglevel(struct net_device *dev)
11039 struct tg3 *tp = netdev_priv(dev);
11040 return tp->msg_enable;
11043 static void tg3_set_msglevel(struct net_device *dev, u32 value)
11045 struct tg3 *tp = netdev_priv(dev);
11046 tp->msg_enable = value;
11049 static int tg3_nway_reset(struct net_device *dev)
11051 struct tg3 *tp = netdev_priv(dev);
11054 if (!netif_running(dev))
11057 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11060 if (tg3_flag(tp, USE_PHYLIB)) {
11061 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11063 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
11067 spin_lock_bh(&tp->lock);
11069 tg3_readphy(tp, MII_BMCR, &bmcr);
11070 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
11071 ((bmcr & BMCR_ANENABLE) ||
11072 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
11073 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
11077 spin_unlock_bh(&tp->lock);
11083 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
11085 struct tg3 *tp = netdev_priv(dev);
11087 ering->rx_max_pending = tp->rx_std_ring_mask;
11088 if (tg3_flag(tp, JUMBO_RING_ENABLE))
11089 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
11091 ering->rx_jumbo_max_pending = 0;
11093 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
11095 ering->rx_pending = tp->rx_pending;
11096 if (tg3_flag(tp, JUMBO_RING_ENABLE))
11097 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
11099 ering->rx_jumbo_pending = 0;
11101 ering->tx_pending = tp->napi[0].tx_pending;
11104 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
11106 struct tg3 *tp = netdev_priv(dev);
11107 int i, irq_sync = 0, err = 0;
11109 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
11110 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
11111 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
11112 (ering->tx_pending <= MAX_SKB_FRAGS) ||
11113 (tg3_flag(tp, TSO_BUG) &&
11114 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
11117 if (netif_running(dev)) {
11119 tg3_netif_stop(tp);
11123 tg3_full_lock(tp, irq_sync);
11125 tp->rx_pending = ering->rx_pending;
11127 if (tg3_flag(tp, MAX_RXPEND_64) &&
11128 tp->rx_pending > 63)
11129 tp->rx_pending = 63;
11130 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
11132 for (i = 0; i < tp->irq_max; i++)
11133 tp->napi[i].tx_pending = ering->tx_pending;
11135 if (netif_running(dev)) {
11136 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11137 err = tg3_restart_hw(tp, 1);
11139 tg3_netif_start(tp);
11142 tg3_full_unlock(tp);
11144 if (irq_sync && !err)
11150 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
11152 struct tg3 *tp = netdev_priv(dev);
11154 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
11156 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
11157 epause->rx_pause = 1;
11159 epause->rx_pause = 0;
11161 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
11162 epause->tx_pause = 1;
11164 epause->tx_pause = 0;
11167 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
11169 struct tg3 *tp = netdev_priv(dev);
11172 if (tg3_flag(tp, USE_PHYLIB)) {
11174 struct phy_device *phydev;
11176 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11178 if (!(phydev->supported & SUPPORTED_Pause) ||
11179 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
11180 (epause->rx_pause != epause->tx_pause)))
11183 tp->link_config.flowctrl = 0;
11184 if (epause->rx_pause) {
11185 tp->link_config.flowctrl |= FLOW_CTRL_RX;
11187 if (epause->tx_pause) {
11188 tp->link_config.flowctrl |= FLOW_CTRL_TX;
11189 newadv = ADVERTISED_Pause;
11191 newadv = ADVERTISED_Pause |
11192 ADVERTISED_Asym_Pause;
11193 } else if (epause->tx_pause) {
11194 tp->link_config.flowctrl |= FLOW_CTRL_TX;
11195 newadv = ADVERTISED_Asym_Pause;
11199 if (epause->autoneg)
11200 tg3_flag_set(tp, PAUSE_AUTONEG);
11202 tg3_flag_clear(tp, PAUSE_AUTONEG);
11204 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
11205 u32 oldadv = phydev->advertising &
11206 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
11207 if (oldadv != newadv) {
11208 phydev->advertising &=
11209 ~(ADVERTISED_Pause |
11210 ADVERTISED_Asym_Pause);
11211 phydev->advertising |= newadv;
11212 if (phydev->autoneg) {
11214 * Always renegotiate the link to
11215 * inform our link partner of our
11216 * flow control settings, even if the
11217 * flow control is forced. Let
11218 * tg3_adjust_link() do the final
11219 * flow control setup.
11221 return phy_start_aneg(phydev);
11225 if (!epause->autoneg)
11226 tg3_setup_flow_control(tp, 0, 0);
11228 tp->link_config.advertising &=
11229 ~(ADVERTISED_Pause |
11230 ADVERTISED_Asym_Pause);
11231 tp->link_config.advertising |= newadv;
11236 if (netif_running(dev)) {
11237 tg3_netif_stop(tp);
11241 tg3_full_lock(tp, irq_sync);
11243 if (epause->autoneg)
11244 tg3_flag_set(tp, PAUSE_AUTONEG);
11246 tg3_flag_clear(tp, PAUSE_AUTONEG);
11247 if (epause->rx_pause)
11248 tp->link_config.flowctrl |= FLOW_CTRL_RX;
11250 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
11251 if (epause->tx_pause)
11252 tp->link_config.flowctrl |= FLOW_CTRL_TX;
11254 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
11256 if (netif_running(dev)) {
11257 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11258 err = tg3_restart_hw(tp, 1);
11260 tg3_netif_start(tp);
11263 tg3_full_unlock(tp);
11269 static int tg3_get_sset_count(struct net_device *dev, int sset)
11273 return TG3_NUM_TEST;
11275 return TG3_NUM_STATS;
11277 return -EOPNOTSUPP;
11281 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
11282 u32 *rules __always_unused)
11284 struct tg3 *tp = netdev_priv(dev);
11286 if (!tg3_flag(tp, SUPPORT_MSIX))
11287 return -EOPNOTSUPP;
11289 switch (info->cmd) {
11290 case ETHTOOL_GRXRINGS:
11291 if (netif_running(tp->dev))
11292 info->data = tp->rxq_cnt;
11294 info->data = num_online_cpus();
11295 if (info->data > TG3_RSS_MAX_NUM_QS)
11296 info->data = TG3_RSS_MAX_NUM_QS;
11299 /* The first interrupt vector only
11300 * handles link interrupts.
11306 return -EOPNOTSUPP;
11310 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
11313 struct tg3 *tp = netdev_priv(dev);
11315 if (tg3_flag(tp, SUPPORT_MSIX))
11316 size = TG3_RSS_INDIR_TBL_SIZE;
11321 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
11323 struct tg3 *tp = netdev_priv(dev);
11326 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
11327 indir[i] = tp->rss_ind_tbl[i];
11332 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
11334 struct tg3 *tp = netdev_priv(dev);
11337 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
11338 tp->rss_ind_tbl[i] = indir[i];
11340 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
11343 /* It is legal to write the indirection
11344 * table while the device is running.
11346 tg3_full_lock(tp, 0);
11347 tg3_rss_write_indir_tbl(tp);
11348 tg3_full_unlock(tp);
11353 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
11355 switch (stringset) {
11357 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
11360 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
11363 WARN_ON(1); /* we need a WARN() */
11368 static int tg3_set_phys_id(struct net_device *dev,
11369 enum ethtool_phys_id_state state)
11371 struct tg3 *tp = netdev_priv(dev);
11373 if (!netif_running(tp->dev))
11377 case ETHTOOL_ID_ACTIVE:
11378 return 1; /* cycle on/off once per second */
11380 case ETHTOOL_ID_ON:
11381 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11382 LED_CTRL_1000MBPS_ON |
11383 LED_CTRL_100MBPS_ON |
11384 LED_CTRL_10MBPS_ON |
11385 LED_CTRL_TRAFFIC_OVERRIDE |
11386 LED_CTRL_TRAFFIC_BLINK |
11387 LED_CTRL_TRAFFIC_LED);
11390 case ETHTOOL_ID_OFF:
11391 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11392 LED_CTRL_TRAFFIC_OVERRIDE);
11395 case ETHTOOL_ID_INACTIVE:
11396 tw32(MAC_LED_CTRL, tp->led_ctrl);
11403 static void tg3_get_ethtool_stats(struct net_device *dev,
11404 struct ethtool_stats *estats, u64 *tmp_stats)
11406 struct tg3 *tp = netdev_priv(dev);
11409 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
11411 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
11414 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
11418 u32 offset = 0, len = 0;
11421 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
11424 if (magic == TG3_EEPROM_MAGIC) {
11425 for (offset = TG3_NVM_DIR_START;
11426 offset < TG3_NVM_DIR_END;
11427 offset += TG3_NVM_DIRENT_SIZE) {
11428 if (tg3_nvram_read(tp, offset, &val))
11431 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
11432 TG3_NVM_DIRTYPE_EXTVPD)
11436 if (offset != TG3_NVM_DIR_END) {
11437 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
11438 if (tg3_nvram_read(tp, offset + 4, &offset))
11441 offset = tg3_nvram_logical_addr(tp, offset);
11445 if (!offset || !len) {
11446 offset = TG3_NVM_VPD_OFF;
11447 len = TG3_NVM_VPD_LEN;
11450 buf = kmalloc(len, GFP_KERNEL);
11454 if (magic == TG3_EEPROM_MAGIC) {
11455 for (i = 0; i < len; i += 4) {
11456 /* The data is in little-endian format in NVRAM.
11457 * Use the big-endian read routines to preserve
11458 * the byte order as it exists in NVRAM.
11460 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
11466 unsigned int pos = 0;
11468 ptr = (u8 *)&buf[0];
11469 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
11470 cnt = pci_read_vpd(tp->pdev, pos,
11472 if (cnt == -ETIMEDOUT || cnt == -EINTR)
11490 #define NVRAM_TEST_SIZE 0x100
11491 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
11492 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
11493 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
11494 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
11495 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
11496 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
11497 #define NVRAM_SELFBOOT_HW_SIZE 0x20
11498 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
11500 static int tg3_test_nvram(struct tg3 *tp)
11502 u32 csum, magic, len;
11504 int i, j, k, err = 0, size;
11506 if (tg3_flag(tp, NO_NVRAM))
11509 if (tg3_nvram_read(tp, 0, &magic) != 0)
11512 if (magic == TG3_EEPROM_MAGIC)
11513 size = NVRAM_TEST_SIZE;
11514 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
11515 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
11516 TG3_EEPROM_SB_FORMAT_1) {
11517 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
11518 case TG3_EEPROM_SB_REVISION_0:
11519 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
11521 case TG3_EEPROM_SB_REVISION_2:
11522 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
11524 case TG3_EEPROM_SB_REVISION_3:
11525 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
11527 case TG3_EEPROM_SB_REVISION_4:
11528 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
11530 case TG3_EEPROM_SB_REVISION_5:
11531 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
11533 case TG3_EEPROM_SB_REVISION_6:
11534 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
11541 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11542 size = NVRAM_SELFBOOT_HW_SIZE;
11546 buf = kmalloc(size, GFP_KERNEL);
11551 for (i = 0, j = 0; i < size; i += 4, j++) {
11552 err = tg3_nvram_read_be32(tp, i, &buf[j]);
11559 /* Selfboot format */
11560 magic = be32_to_cpu(buf[0]);
11561 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
11562 TG3_EEPROM_MAGIC_FW) {
11563 u8 *buf8 = (u8 *) buf, csum8 = 0;
11565 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
11566 TG3_EEPROM_SB_REVISION_2) {
11567 /* For rev 2, the csum doesn't include the MBA. */
11568 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
11570 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
11573 for (i = 0; i < size; i++)
11586 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
11587 TG3_EEPROM_MAGIC_HW) {
11588 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
11589 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
11590 u8 *buf8 = (u8 *) buf;
11592 /* Separate the parity bits and the data bytes. */
11593 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
11594 if ((i == 0) || (i == 8)) {
11598 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
11599 parity[k++] = buf8[i] & msk;
11601 } else if (i == 16) {
11605 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
11606 parity[k++] = buf8[i] & msk;
11609 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
11610 parity[k++] = buf8[i] & msk;
11613 data[j++] = buf8[i];
11617 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
11618 u8 hw8 = hweight8(data[i]);
11620 if ((hw8 & 0x1) && parity[i])
11622 else if (!(hw8 & 0x1) && !parity[i])
11631 /* Bootstrap checksum at offset 0x10 */
11632 csum = calc_crc((unsigned char *) buf, 0x10);
11633 if (csum != le32_to_cpu(buf[0x10/4]))
11636 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
11637 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
11638 if (csum != le32_to_cpu(buf[0xfc/4]))
11643 buf = tg3_vpd_readblock(tp, &len);
11647 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
11649 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11653 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
11656 i += PCI_VPD_LRDT_TAG_SIZE;
11657 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11658 PCI_VPD_RO_KEYWORD_CHKSUM);
11662 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11664 for (i = 0; i <= j; i++)
11665 csum8 += ((u8 *)buf)[i];
11679 #define TG3_SERDES_TIMEOUT_SEC 2
11680 #define TG3_COPPER_TIMEOUT_SEC 6
11682 static int tg3_test_link(struct tg3 *tp)
11686 if (!netif_running(tp->dev))
11689 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
11690 max = TG3_SERDES_TIMEOUT_SEC;
11692 max = TG3_COPPER_TIMEOUT_SEC;
11694 for (i = 0; i < max; i++) {
11695 if (netif_carrier_ok(tp->dev))
11698 if (msleep_interruptible(1000))
11705 /* Only test the commonly used registers */
11706 static int tg3_test_registers(struct tg3 *tp)
11708 int i, is_5705, is_5750;
11709 u32 offset, read_mask, write_mask, val, save_val, read_val;
11713 #define TG3_FL_5705 0x1
11714 #define TG3_FL_NOT_5705 0x2
11715 #define TG3_FL_NOT_5788 0x4
11716 #define TG3_FL_NOT_5750 0x8
11720 /* MAC Control Registers */
11721 { MAC_MODE, TG3_FL_NOT_5705,
11722 0x00000000, 0x00ef6f8c },
11723 { MAC_MODE, TG3_FL_5705,
11724 0x00000000, 0x01ef6b8c },
11725 { MAC_STATUS, TG3_FL_NOT_5705,
11726 0x03800107, 0x00000000 },
11727 { MAC_STATUS, TG3_FL_5705,
11728 0x03800100, 0x00000000 },
11729 { MAC_ADDR_0_HIGH, 0x0000,
11730 0x00000000, 0x0000ffff },
11731 { MAC_ADDR_0_LOW, 0x0000,
11732 0x00000000, 0xffffffff },
11733 { MAC_RX_MTU_SIZE, 0x0000,
11734 0x00000000, 0x0000ffff },
11735 { MAC_TX_MODE, 0x0000,
11736 0x00000000, 0x00000070 },
11737 { MAC_TX_LENGTHS, 0x0000,
11738 0x00000000, 0x00003fff },
11739 { MAC_RX_MODE, TG3_FL_NOT_5705,
11740 0x00000000, 0x000007fc },
11741 { MAC_RX_MODE, TG3_FL_5705,
11742 0x00000000, 0x000007dc },
11743 { MAC_HASH_REG_0, 0x0000,
11744 0x00000000, 0xffffffff },
11745 { MAC_HASH_REG_1, 0x0000,
11746 0x00000000, 0xffffffff },
11747 { MAC_HASH_REG_2, 0x0000,
11748 0x00000000, 0xffffffff },
11749 { MAC_HASH_REG_3, 0x0000,
11750 0x00000000, 0xffffffff },
11752 /* Receive Data and Receive BD Initiator Control Registers. */
11753 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11754 0x00000000, 0xffffffff },
11755 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11756 0x00000000, 0xffffffff },
11757 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11758 0x00000000, 0x00000003 },
11759 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11760 0x00000000, 0xffffffff },
11761 { RCVDBDI_STD_BD+0, 0x0000,
11762 0x00000000, 0xffffffff },
11763 { RCVDBDI_STD_BD+4, 0x0000,
11764 0x00000000, 0xffffffff },
11765 { RCVDBDI_STD_BD+8, 0x0000,
11766 0x00000000, 0xffff0002 },
11767 { RCVDBDI_STD_BD+0xc, 0x0000,
11768 0x00000000, 0xffffffff },
11770 /* Receive BD Initiator Control Registers. */
11771 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11772 0x00000000, 0xffffffff },
11773 { RCVBDI_STD_THRESH, TG3_FL_5705,
11774 0x00000000, 0x000003ff },
11775 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11776 0x00000000, 0xffffffff },
11778 /* Host Coalescing Control Registers. */
11779 { HOSTCC_MODE, TG3_FL_NOT_5705,
11780 0x00000000, 0x00000004 },
11781 { HOSTCC_MODE, TG3_FL_5705,
11782 0x00000000, 0x000000f6 },
11783 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11784 0x00000000, 0xffffffff },
11785 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11786 0x00000000, 0x000003ff },
11787 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11788 0x00000000, 0xffffffff },
11789 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11790 0x00000000, 0x000003ff },
11791 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11792 0x00000000, 0xffffffff },
11793 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11794 0x00000000, 0x000000ff },
11795 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11796 0x00000000, 0xffffffff },
11797 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11798 0x00000000, 0x000000ff },
11799 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11800 0x00000000, 0xffffffff },
11801 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11802 0x00000000, 0xffffffff },
11803 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11804 0x00000000, 0xffffffff },
11805 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11806 0x00000000, 0x000000ff },
11807 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11808 0x00000000, 0xffffffff },
11809 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11810 0x00000000, 0x000000ff },
11811 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11812 0x00000000, 0xffffffff },
11813 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11814 0x00000000, 0xffffffff },
11815 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11816 0x00000000, 0xffffffff },
11817 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11818 0x00000000, 0xffffffff },
11819 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11820 0x00000000, 0xffffffff },
11821 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11822 0xffffffff, 0x00000000 },
11823 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11824 0xffffffff, 0x00000000 },
11826 /* Buffer Manager Control Registers. */
11827 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
11828 0x00000000, 0x007fff80 },
11829 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
11830 0x00000000, 0x007fffff },
11831 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11832 0x00000000, 0x0000003f },
11833 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11834 0x00000000, 0x000001ff },
11835 { BUFMGR_MB_HIGH_WATER, 0x0000,
11836 0x00000000, 0x000001ff },
11837 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11838 0xffffffff, 0x00000000 },
11839 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11840 0xffffffff, 0x00000000 },
11842 /* Mailbox Registers */
11843 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11844 0x00000000, 0x000001ff },
11845 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11846 0x00000000, 0x000001ff },
11847 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11848 0x00000000, 0x000007ff },
11849 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11850 0x00000000, 0x000001ff },
11852 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11855 is_5705 = is_5750 = 0;
11856 if (tg3_flag(tp, 5705_PLUS)) {
11858 if (tg3_flag(tp, 5750_PLUS))
11862 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11863 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11866 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11869 if (tg3_flag(tp, IS_5788) &&
11870 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11873 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11876 offset = (u32) reg_tbl[i].offset;
11877 read_mask = reg_tbl[i].read_mask;
11878 write_mask = reg_tbl[i].write_mask;
11880 /* Save the original register content */
11881 save_val = tr32(offset);
11883 /* Determine the read-only value. */
11884 read_val = save_val & read_mask;
11886 /* Write zero to the register, then make sure the read-only bits
11887 * are not changed and the read/write bits are all zeros.
11891 val = tr32(offset);
11893 /* Test the read-only and read/write bits. */
11894 if (((val & read_mask) != read_val) || (val & write_mask))
11897 /* Write ones to all the bits defined by RdMask and WrMask, then
11898 * make sure the read-only bits are not changed and the
11899 * read/write bits are all ones.
11901 tw32(offset, read_mask | write_mask);
11903 val = tr32(offset);
11905 /* Test the read-only bits. */
11906 if ((val & read_mask) != read_val)
11909 /* Test the read/write bits. */
11910 if ((val & write_mask) != write_mask)
11913 tw32(offset, save_val);
11919 if (netif_msg_hw(tp))
11920 netdev_err(tp->dev,
11921 "Register test failed at offset %x\n", offset);
11922 tw32(offset, save_val);
11926 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11928 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11932 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11933 for (j = 0; j < len; j += 4) {
11936 tg3_write_mem(tp, offset + j, test_pattern[i]);
11937 tg3_read_mem(tp, offset + j, &val);
11938 if (val != test_pattern[i])
11945 static int tg3_test_memory(struct tg3 *tp)
11947 static struct mem_entry {
11950 } mem_tbl_570x[] = {
11951 { 0x00000000, 0x00b50},
11952 { 0x00002000, 0x1c000},
11953 { 0xffffffff, 0x00000}
11954 }, mem_tbl_5705[] = {
11955 { 0x00000100, 0x0000c},
11956 { 0x00000200, 0x00008},
11957 { 0x00004000, 0x00800},
11958 { 0x00006000, 0x01000},
11959 { 0x00008000, 0x02000},
11960 { 0x00010000, 0x0e000},
11961 { 0xffffffff, 0x00000}
11962 }, mem_tbl_5755[] = {
11963 { 0x00000200, 0x00008},
11964 { 0x00004000, 0x00800},
11965 { 0x00006000, 0x00800},
11966 { 0x00008000, 0x02000},
11967 { 0x00010000, 0x0c000},
11968 { 0xffffffff, 0x00000}
11969 }, mem_tbl_5906[] = {
11970 { 0x00000200, 0x00008},
11971 { 0x00004000, 0x00400},
11972 { 0x00006000, 0x00400},
11973 { 0x00008000, 0x01000},
11974 { 0x00010000, 0x01000},
11975 { 0xffffffff, 0x00000}
11976 }, mem_tbl_5717[] = {
11977 { 0x00000200, 0x00008},
11978 { 0x00010000, 0x0a000},
11979 { 0x00020000, 0x13c00},
11980 { 0xffffffff, 0x00000}
11981 }, mem_tbl_57765[] = {
11982 { 0x00000200, 0x00008},
11983 { 0x00004000, 0x00800},
11984 { 0x00006000, 0x09800},
11985 { 0x00010000, 0x0a000},
11986 { 0xffffffff, 0x00000}
11988 struct mem_entry *mem_tbl;
11992 if (tg3_flag(tp, 5717_PLUS))
11993 mem_tbl = mem_tbl_5717;
11994 else if (tg3_flag(tp, 57765_CLASS))
11995 mem_tbl = mem_tbl_57765;
11996 else if (tg3_flag(tp, 5755_PLUS))
11997 mem_tbl = mem_tbl_5755;
11998 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11999 mem_tbl = mem_tbl_5906;
12000 else if (tg3_flag(tp, 5705_PLUS))
12001 mem_tbl = mem_tbl_5705;
12003 mem_tbl = mem_tbl_570x;
12005 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
12006 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
12014 #define TG3_TSO_MSS 500
12016 #define TG3_TSO_IP_HDR_LEN 20
12017 #define TG3_TSO_TCP_HDR_LEN 20
12018 #define TG3_TSO_TCP_OPT_LEN 12
12020 static const u8 tg3_tso_header[] = {
12022 0x45, 0x00, 0x00, 0x00,
12023 0x00, 0x00, 0x40, 0x00,
12024 0x40, 0x06, 0x00, 0x00,
12025 0x0a, 0x00, 0x00, 0x01,
12026 0x0a, 0x00, 0x00, 0x02,
12027 0x0d, 0x00, 0xe0, 0x00,
12028 0x00, 0x00, 0x01, 0x00,
12029 0x00, 0x00, 0x02, 0x00,
12030 0x80, 0x10, 0x10, 0x00,
12031 0x14, 0x09, 0x00, 0x00,
12032 0x01, 0x01, 0x08, 0x0a,
12033 0x11, 0x11, 0x11, 0x11,
12034 0x11, 0x11, 0x11, 0x11,
12037 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
12039 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
12040 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
12042 struct sk_buff *skb;
12043 u8 *tx_data, *rx_data;
12045 int num_pkts, tx_len, rx_len, i, err;
12046 struct tg3_rx_buffer_desc *desc;
12047 struct tg3_napi *tnapi, *rnapi;
12048 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
12050 tnapi = &tp->napi[0];
12051 rnapi = &tp->napi[0];
12052 if (tp->irq_cnt > 1) {
12053 if (tg3_flag(tp, ENABLE_RSS))
12054 rnapi = &tp->napi[1];
12055 if (tg3_flag(tp, ENABLE_TSS))
12056 tnapi = &tp->napi[1];
12058 coal_now = tnapi->coal_now | rnapi->coal_now;
12063 skb = netdev_alloc_skb(tp->dev, tx_len);
12067 tx_data = skb_put(skb, tx_len);
12068 memcpy(tx_data, tp->dev->dev_addr, 6);
12069 memset(tx_data + 6, 0x0, 8);
12071 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
12073 if (tso_loopback) {
12074 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
12076 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
12077 TG3_TSO_TCP_OPT_LEN;
12079 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
12080 sizeof(tg3_tso_header));
12083 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
12084 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
12086 /* Set the total length field in the IP header */
12087 iph->tot_len = htons((u16)(mss + hdr_len));
12089 base_flags = (TXD_FLAG_CPU_PRE_DMA |
12090 TXD_FLAG_CPU_POST_DMA);
12092 if (tg3_flag(tp, HW_TSO_1) ||
12093 tg3_flag(tp, HW_TSO_2) ||
12094 tg3_flag(tp, HW_TSO_3)) {
12096 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
12097 th = (struct tcphdr *)&tx_data[val];
12100 base_flags |= TXD_FLAG_TCPUDP_CSUM;
12102 if (tg3_flag(tp, HW_TSO_3)) {
12103 mss |= (hdr_len & 0xc) << 12;
12104 if (hdr_len & 0x10)
12105 base_flags |= 0x00000010;
12106 base_flags |= (hdr_len & 0x3e0) << 5;
12107 } else if (tg3_flag(tp, HW_TSO_2))
12108 mss |= hdr_len << 9;
12109 else if (tg3_flag(tp, HW_TSO_1) ||
12110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
12111 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
12113 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
12116 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
12119 data_off = ETH_HLEN;
12121 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
12122 tx_len > VLAN_ETH_FRAME_LEN)
12123 base_flags |= TXD_FLAG_JMB_PKT;
12126 for (i = data_off; i < tx_len; i++)
12127 tx_data[i] = (u8) (i & 0xff);
12129 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
12130 if (pci_dma_mapping_error(tp->pdev, map)) {
12131 dev_kfree_skb(skb);
12135 val = tnapi->tx_prod;
12136 tnapi->tx_buffers[val].skb = skb;
12137 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
12139 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
12144 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
12146 budget = tg3_tx_avail(tnapi);
12147 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
12148 base_flags | TXD_FLAG_END, mss, 0)) {
12149 tnapi->tx_buffers[val].skb = NULL;
12150 dev_kfree_skb(skb);
12156 /* Sync BD data before updating mailbox */
12159 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
12160 tr32_mailbox(tnapi->prodmbox);
12164 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
12165 for (i = 0; i < 35; i++) {
12166 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
12171 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
12172 rx_idx = rnapi->hw_status->idx[0].rx_producer;
12173 if ((tx_idx == tnapi->tx_prod) &&
12174 (rx_idx == (rx_start_idx + num_pkts)))
12178 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
12179 dev_kfree_skb(skb);
12181 if (tx_idx != tnapi->tx_prod)
12184 if (rx_idx != rx_start_idx + num_pkts)
12188 while (rx_idx != rx_start_idx) {
12189 desc = &rnapi->rx_rcb[rx_start_idx++];
12190 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
12191 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
12193 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
12194 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
12197 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
12200 if (!tso_loopback) {
12201 if (rx_len != tx_len)
12204 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
12205 if (opaque_key != RXD_OPAQUE_RING_STD)
12208 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
12211 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
12212 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
12213 >> RXD_TCPCSUM_SHIFT != 0xffff) {
12217 if (opaque_key == RXD_OPAQUE_RING_STD) {
12218 rx_data = tpr->rx_std_buffers[desc_idx].data;
12219 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
12221 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
12222 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
12223 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
12228 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
12229 PCI_DMA_FROMDEVICE);
12231 rx_data += TG3_RX_OFFSET(tp);
12232 for (i = data_off; i < rx_len; i++, val++) {
12233 if (*(rx_data + i) != (u8) (val & 0xff))
12240 /* tg3_free_rings will unmap and free the rx_data */
12245 #define TG3_STD_LOOPBACK_FAILED 1
12246 #define TG3_JMB_LOOPBACK_FAILED 2
12247 #define TG3_TSO_LOOPBACK_FAILED 4
12248 #define TG3_LOOPBACK_FAILED \
12249 (TG3_STD_LOOPBACK_FAILED | \
12250 TG3_JMB_LOOPBACK_FAILED | \
12251 TG3_TSO_LOOPBACK_FAILED)
12253 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
12257 u32 jmb_pkt_sz = 9000;
12260 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
12262 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
12263 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
12265 if (!netif_running(tp->dev)) {
12266 data[0] = TG3_LOOPBACK_FAILED;
12267 data[1] = TG3_LOOPBACK_FAILED;
12269 data[2] = TG3_LOOPBACK_FAILED;
12273 err = tg3_reset_hw(tp, 1);
12275 data[0] = TG3_LOOPBACK_FAILED;
12276 data[1] = TG3_LOOPBACK_FAILED;
12278 data[2] = TG3_LOOPBACK_FAILED;
12282 if (tg3_flag(tp, ENABLE_RSS)) {
12285 /* Reroute all rx packets to the 1st queue */
12286 for (i = MAC_RSS_INDIR_TBL_0;
12287 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
12291 /* HW errata - mac loopback fails in some cases on 5780.
12292 * Normal traffic and PHY loopback are not affected by
12293 * errata. Also, the MAC loopback test is deprecated for
12294 * all newer ASIC revisions.
12296 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
12297 !tg3_flag(tp, CPMU_PRESENT)) {
12298 tg3_mac_loopback(tp, true);
12300 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
12301 data[0] |= TG3_STD_LOOPBACK_FAILED;
12303 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
12304 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
12305 data[0] |= TG3_JMB_LOOPBACK_FAILED;
12307 tg3_mac_loopback(tp, false);
12310 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
12311 !tg3_flag(tp, USE_PHYLIB)) {
12314 tg3_phy_lpbk_set(tp, 0, false);
12316 /* Wait for link */
12317 for (i = 0; i < 100; i++) {
12318 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
12323 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
12324 data[1] |= TG3_STD_LOOPBACK_FAILED;
12325 if (tg3_flag(tp, TSO_CAPABLE) &&
12326 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
12327 data[1] |= TG3_TSO_LOOPBACK_FAILED;
12328 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
12329 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
12330 data[1] |= TG3_JMB_LOOPBACK_FAILED;
12333 tg3_phy_lpbk_set(tp, 0, true);
12335 /* All link indications report up, but the hardware
12336 * isn't really ready for about 20 msec. Double it
12341 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
12342 data[2] |= TG3_STD_LOOPBACK_FAILED;
12343 if (tg3_flag(tp, TSO_CAPABLE) &&
12344 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
12345 data[2] |= TG3_TSO_LOOPBACK_FAILED;
12346 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
12347 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
12348 data[2] |= TG3_JMB_LOOPBACK_FAILED;
12351 /* Re-enable gphy autopowerdown. */
12352 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
12353 tg3_phy_toggle_apd(tp, true);
12356 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
12359 tp->phy_flags |= eee_cap;
12364 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
12367 struct tg3 *tp = netdev_priv(dev);
12368 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
12370 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
12371 tg3_power_up(tp)) {
12372 etest->flags |= ETH_TEST_FL_FAILED;
12373 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
12377 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
12379 if (tg3_test_nvram(tp) != 0) {
12380 etest->flags |= ETH_TEST_FL_FAILED;
12383 if (!doextlpbk && tg3_test_link(tp)) {
12384 etest->flags |= ETH_TEST_FL_FAILED;
12387 if (etest->flags & ETH_TEST_FL_OFFLINE) {
12388 int err, err2 = 0, irq_sync = 0;
12390 if (netif_running(dev)) {
12392 tg3_netif_stop(tp);
12396 tg3_full_lock(tp, irq_sync);
12398 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
12399 err = tg3_nvram_lock(tp);
12400 tg3_halt_cpu(tp, RX_CPU_BASE);
12401 if (!tg3_flag(tp, 5705_PLUS))
12402 tg3_halt_cpu(tp, TX_CPU_BASE);
12404 tg3_nvram_unlock(tp);
12406 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
12409 if (tg3_test_registers(tp) != 0) {
12410 etest->flags |= ETH_TEST_FL_FAILED;
12414 if (tg3_test_memory(tp) != 0) {
12415 etest->flags |= ETH_TEST_FL_FAILED;
12420 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
12422 if (tg3_test_loopback(tp, &data[4], doextlpbk))
12423 etest->flags |= ETH_TEST_FL_FAILED;
12425 tg3_full_unlock(tp);
12427 if (tg3_test_interrupt(tp) != 0) {
12428 etest->flags |= ETH_TEST_FL_FAILED;
12432 tg3_full_lock(tp, 0);
12434 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12435 if (netif_running(dev)) {
12436 tg3_flag_set(tp, INIT_COMPLETE);
12437 err2 = tg3_restart_hw(tp, 1);
12439 tg3_netif_start(tp);
12442 tg3_full_unlock(tp);
12444 if (irq_sync && !err2)
12447 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
12448 tg3_power_down(tp);
12452 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12454 struct mii_ioctl_data *data = if_mii(ifr);
12455 struct tg3 *tp = netdev_priv(dev);
12458 if (tg3_flag(tp, USE_PHYLIB)) {
12459 struct phy_device *phydev;
12460 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12462 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
12463 return phy_mii_ioctl(phydev, ifr, cmd);
12468 data->phy_id = tp->phy_addr;
12471 case SIOCGMIIREG: {
12474 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12475 break; /* We have no PHY */
12477 if (!netif_running(dev))
12480 spin_lock_bh(&tp->lock);
12481 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
12482 spin_unlock_bh(&tp->lock);
12484 data->val_out = mii_regval;
12490 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12491 break; /* We have no PHY */
12493 if (!netif_running(dev))
12496 spin_lock_bh(&tp->lock);
12497 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
12498 spin_unlock_bh(&tp->lock);
12506 return -EOPNOTSUPP;
12509 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12511 struct tg3 *tp = netdev_priv(dev);
12513 memcpy(ec, &tp->coal, sizeof(*ec));
12517 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12519 struct tg3 *tp = netdev_priv(dev);
12520 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
12521 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
12523 if (!tg3_flag(tp, 5705_PLUS)) {
12524 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
12525 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
12526 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
12527 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
12530 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
12531 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
12532 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
12533 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
12534 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
12535 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
12536 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
12537 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
12538 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
12539 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
12542 /* No rx interrupts will be generated if both are zero */
12543 if ((ec->rx_coalesce_usecs == 0) &&
12544 (ec->rx_max_coalesced_frames == 0))
12547 /* No tx interrupts will be generated if both are zero */
12548 if ((ec->tx_coalesce_usecs == 0) &&
12549 (ec->tx_max_coalesced_frames == 0))
12552 /* Only copy relevant parameters, ignore all others. */
12553 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
12554 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
12555 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
12556 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
12557 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
12558 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
12559 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
12560 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
12561 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
12563 if (netif_running(dev)) {
12564 tg3_full_lock(tp, 0);
12565 __tg3_set_coalesce(tp, &tp->coal);
12566 tg3_full_unlock(tp);
12571 static const struct ethtool_ops tg3_ethtool_ops = {
12572 .get_settings = tg3_get_settings,
12573 .set_settings = tg3_set_settings,
12574 .get_drvinfo = tg3_get_drvinfo,
12575 .get_regs_len = tg3_get_regs_len,
12576 .get_regs = tg3_get_regs,
12577 .get_wol = tg3_get_wol,
12578 .set_wol = tg3_set_wol,
12579 .get_msglevel = tg3_get_msglevel,
12580 .set_msglevel = tg3_set_msglevel,
12581 .nway_reset = tg3_nway_reset,
12582 .get_link = ethtool_op_get_link,
12583 .get_eeprom_len = tg3_get_eeprom_len,
12584 .get_eeprom = tg3_get_eeprom,
12585 .set_eeprom = tg3_set_eeprom,
12586 .get_ringparam = tg3_get_ringparam,
12587 .set_ringparam = tg3_set_ringparam,
12588 .get_pauseparam = tg3_get_pauseparam,
12589 .set_pauseparam = tg3_set_pauseparam,
12590 .self_test = tg3_self_test,
12591 .get_strings = tg3_get_strings,
12592 .set_phys_id = tg3_set_phys_id,
12593 .get_ethtool_stats = tg3_get_ethtool_stats,
12594 .get_coalesce = tg3_get_coalesce,
12595 .set_coalesce = tg3_set_coalesce,
12596 .get_sset_count = tg3_get_sset_count,
12597 .get_rxnfc = tg3_get_rxnfc,
12598 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
12599 .get_rxfh_indir = tg3_get_rxfh_indir,
12600 .set_rxfh_indir = tg3_set_rxfh_indir,
12601 .get_ts_info = ethtool_op_get_ts_info,
12604 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
12605 struct rtnl_link_stats64 *stats)
12607 struct tg3 *tp = netdev_priv(dev);
12609 spin_lock_bh(&tp->lock);
12610 if (!tp->hw_stats) {
12611 spin_unlock_bh(&tp->lock);
12612 return &tp->net_stats_prev;
12615 tg3_get_nstats(tp, stats);
12616 spin_unlock_bh(&tp->lock);
12621 static void tg3_set_rx_mode(struct net_device *dev)
12623 struct tg3 *tp = netdev_priv(dev);
12625 if (!netif_running(dev))
12628 tg3_full_lock(tp, 0);
12629 __tg3_set_rx_mode(dev);
12630 tg3_full_unlock(tp);
12633 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
12636 dev->mtu = new_mtu;
12638 if (new_mtu > ETH_DATA_LEN) {
12639 if (tg3_flag(tp, 5780_CLASS)) {
12640 netdev_update_features(dev);
12641 tg3_flag_clear(tp, TSO_CAPABLE);
12643 tg3_flag_set(tp, JUMBO_RING_ENABLE);
12646 if (tg3_flag(tp, 5780_CLASS)) {
12647 tg3_flag_set(tp, TSO_CAPABLE);
12648 netdev_update_features(dev);
12650 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
12654 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
12656 struct tg3 *tp = netdev_priv(dev);
12657 int err, reset_phy = 0;
12659 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
12662 if (!netif_running(dev)) {
12663 /* We'll just catch it later when the
12666 tg3_set_mtu(dev, tp, new_mtu);
12672 tg3_netif_stop(tp);
12674 tg3_full_lock(tp, 1);
12676 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12678 tg3_set_mtu(dev, tp, new_mtu);
12680 /* Reset PHY, otherwise the read DMA engine will be in a mode that
12681 * breaks all requests to 256 bytes.
12683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
12686 err = tg3_restart_hw(tp, reset_phy);
12689 tg3_netif_start(tp);
12691 tg3_full_unlock(tp);
12699 static const struct net_device_ops tg3_netdev_ops = {
12700 .ndo_open = tg3_open,
12701 .ndo_stop = tg3_close,
12702 .ndo_start_xmit = tg3_start_xmit,
12703 .ndo_get_stats64 = tg3_get_stats64,
12704 .ndo_validate_addr = eth_validate_addr,
12705 .ndo_set_rx_mode = tg3_set_rx_mode,
12706 .ndo_set_mac_address = tg3_set_mac_addr,
12707 .ndo_do_ioctl = tg3_ioctl,
12708 .ndo_tx_timeout = tg3_tx_timeout,
12709 .ndo_change_mtu = tg3_change_mtu,
12710 .ndo_fix_features = tg3_fix_features,
12711 .ndo_set_features = tg3_set_features,
12712 #ifdef CONFIG_NET_POLL_CONTROLLER
12713 .ndo_poll_controller = tg3_poll_controller,
12717 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
12719 u32 cursize, val, magic;
12721 tp->nvram_size = EEPROM_CHIP_SIZE;
12723 if (tg3_nvram_read(tp, 0, &magic) != 0)
12726 if ((magic != TG3_EEPROM_MAGIC) &&
12727 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
12728 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
12732 * Size the chip by reading offsets at increasing powers of two.
12733 * When we encounter our validation signature, we know the addressing
12734 * has wrapped around, and thus have our chip size.
12738 while (cursize < tp->nvram_size) {
12739 if (tg3_nvram_read(tp, cursize, &val) != 0)
12748 tp->nvram_size = cursize;
12751 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
12755 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
12758 /* Selfboot format */
12759 if (val != TG3_EEPROM_MAGIC) {
12760 tg3_get_eeprom_size(tp);
12764 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
12766 /* This is confusing. We want to operate on the
12767 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12768 * call will read from NVRAM and byteswap the data
12769 * according to the byteswapping settings for all
12770 * other register accesses. This ensures the data we
12771 * want will always reside in the lower 16-bits.
12772 * However, the data in NVRAM is in LE format, which
12773 * means the data from the NVRAM read will always be
12774 * opposite the endianness of the CPU. The 16-bit
12775 * byteswap then brings the data to CPU endianness.
12777 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
12781 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12784 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12788 nvcfg1 = tr32(NVRAM_CFG1);
12789 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
12790 tg3_flag_set(tp, FLASH);
12792 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12793 tw32(NVRAM_CFG1, nvcfg1);
12796 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12797 tg3_flag(tp, 5780_CLASS)) {
12798 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
12799 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12800 tp->nvram_jedecnum = JEDEC_ATMEL;
12801 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12802 tg3_flag_set(tp, NVRAM_BUFFERED);
12804 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12805 tp->nvram_jedecnum = JEDEC_ATMEL;
12806 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12808 case FLASH_VENDOR_ATMEL_EEPROM:
12809 tp->nvram_jedecnum = JEDEC_ATMEL;
12810 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12811 tg3_flag_set(tp, NVRAM_BUFFERED);
12813 case FLASH_VENDOR_ST:
12814 tp->nvram_jedecnum = JEDEC_ST;
12815 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
12816 tg3_flag_set(tp, NVRAM_BUFFERED);
12818 case FLASH_VENDOR_SAIFUN:
12819 tp->nvram_jedecnum = JEDEC_SAIFUN;
12820 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12822 case FLASH_VENDOR_SST_SMALL:
12823 case FLASH_VENDOR_SST_LARGE:
12824 tp->nvram_jedecnum = JEDEC_SST;
12825 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12829 tp->nvram_jedecnum = JEDEC_ATMEL;
12830 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12831 tg3_flag_set(tp, NVRAM_BUFFERED);
12835 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12837 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12838 case FLASH_5752PAGE_SIZE_256:
12839 tp->nvram_pagesize = 256;
12841 case FLASH_5752PAGE_SIZE_512:
12842 tp->nvram_pagesize = 512;
12844 case FLASH_5752PAGE_SIZE_1K:
12845 tp->nvram_pagesize = 1024;
12847 case FLASH_5752PAGE_SIZE_2K:
12848 tp->nvram_pagesize = 2048;
12850 case FLASH_5752PAGE_SIZE_4K:
12851 tp->nvram_pagesize = 4096;
12853 case FLASH_5752PAGE_SIZE_264:
12854 tp->nvram_pagesize = 264;
12856 case FLASH_5752PAGE_SIZE_528:
12857 tp->nvram_pagesize = 528;
12862 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12866 nvcfg1 = tr32(NVRAM_CFG1);
12868 /* NVRAM protection for TPM */
12869 if (nvcfg1 & (1 << 27))
12870 tg3_flag_set(tp, PROTECTED_NVRAM);
12872 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12873 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12874 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12875 tp->nvram_jedecnum = JEDEC_ATMEL;
12876 tg3_flag_set(tp, NVRAM_BUFFERED);
12878 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12879 tp->nvram_jedecnum = JEDEC_ATMEL;
12880 tg3_flag_set(tp, NVRAM_BUFFERED);
12881 tg3_flag_set(tp, FLASH);
12883 case FLASH_5752VENDOR_ST_M45PE10:
12884 case FLASH_5752VENDOR_ST_M45PE20:
12885 case FLASH_5752VENDOR_ST_M45PE40:
12886 tp->nvram_jedecnum = JEDEC_ST;
12887 tg3_flag_set(tp, NVRAM_BUFFERED);
12888 tg3_flag_set(tp, FLASH);
12892 if (tg3_flag(tp, FLASH)) {
12893 tg3_nvram_get_pagesize(tp, nvcfg1);
12895 /* For eeprom, set pagesize to maximum eeprom size */
12896 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12898 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12899 tw32(NVRAM_CFG1, nvcfg1);
12903 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12905 u32 nvcfg1, protect = 0;
12907 nvcfg1 = tr32(NVRAM_CFG1);
12909 /* NVRAM protection for TPM */
12910 if (nvcfg1 & (1 << 27)) {
12911 tg3_flag_set(tp, PROTECTED_NVRAM);
12915 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12917 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12918 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12919 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12920 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12921 tp->nvram_jedecnum = JEDEC_ATMEL;
12922 tg3_flag_set(tp, NVRAM_BUFFERED);
12923 tg3_flag_set(tp, FLASH);
12924 tp->nvram_pagesize = 264;
12925 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12926 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12927 tp->nvram_size = (protect ? 0x3e200 :
12928 TG3_NVRAM_SIZE_512KB);
12929 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12930 tp->nvram_size = (protect ? 0x1f200 :
12931 TG3_NVRAM_SIZE_256KB);
12933 tp->nvram_size = (protect ? 0x1f200 :
12934 TG3_NVRAM_SIZE_128KB);
12936 case FLASH_5752VENDOR_ST_M45PE10:
12937 case FLASH_5752VENDOR_ST_M45PE20:
12938 case FLASH_5752VENDOR_ST_M45PE40:
12939 tp->nvram_jedecnum = JEDEC_ST;
12940 tg3_flag_set(tp, NVRAM_BUFFERED);
12941 tg3_flag_set(tp, FLASH);
12942 tp->nvram_pagesize = 256;
12943 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12944 tp->nvram_size = (protect ?
12945 TG3_NVRAM_SIZE_64KB :
12946 TG3_NVRAM_SIZE_128KB);
12947 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12948 tp->nvram_size = (protect ?
12949 TG3_NVRAM_SIZE_64KB :
12950 TG3_NVRAM_SIZE_256KB);
12952 tp->nvram_size = (protect ?
12953 TG3_NVRAM_SIZE_128KB :
12954 TG3_NVRAM_SIZE_512KB);
12959 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12963 nvcfg1 = tr32(NVRAM_CFG1);
12965 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12966 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12967 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12968 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12969 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12970 tp->nvram_jedecnum = JEDEC_ATMEL;
12971 tg3_flag_set(tp, NVRAM_BUFFERED);
12972 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12974 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12975 tw32(NVRAM_CFG1, nvcfg1);
12977 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12978 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12979 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12980 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12981 tp->nvram_jedecnum = JEDEC_ATMEL;
12982 tg3_flag_set(tp, NVRAM_BUFFERED);
12983 tg3_flag_set(tp, FLASH);
12984 tp->nvram_pagesize = 264;
12986 case FLASH_5752VENDOR_ST_M45PE10:
12987 case FLASH_5752VENDOR_ST_M45PE20:
12988 case FLASH_5752VENDOR_ST_M45PE40:
12989 tp->nvram_jedecnum = JEDEC_ST;
12990 tg3_flag_set(tp, NVRAM_BUFFERED);
12991 tg3_flag_set(tp, FLASH);
12992 tp->nvram_pagesize = 256;
12997 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12999 u32 nvcfg1, protect = 0;
13001 nvcfg1 = tr32(NVRAM_CFG1);
13003 /* NVRAM protection for TPM */
13004 if (nvcfg1 & (1 << 27)) {
13005 tg3_flag_set(tp, PROTECTED_NVRAM);
13009 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
13011 case FLASH_5761VENDOR_ATMEL_ADB021D:
13012 case FLASH_5761VENDOR_ATMEL_ADB041D:
13013 case FLASH_5761VENDOR_ATMEL_ADB081D:
13014 case FLASH_5761VENDOR_ATMEL_ADB161D:
13015 case FLASH_5761VENDOR_ATMEL_MDB021D:
13016 case FLASH_5761VENDOR_ATMEL_MDB041D:
13017 case FLASH_5761VENDOR_ATMEL_MDB081D:
13018 case FLASH_5761VENDOR_ATMEL_MDB161D:
13019 tp->nvram_jedecnum = JEDEC_ATMEL;
13020 tg3_flag_set(tp, NVRAM_BUFFERED);
13021 tg3_flag_set(tp, FLASH);
13022 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
13023 tp->nvram_pagesize = 256;
13025 case FLASH_5761VENDOR_ST_A_M45PE20:
13026 case FLASH_5761VENDOR_ST_A_M45PE40:
13027 case FLASH_5761VENDOR_ST_A_M45PE80:
13028 case FLASH_5761VENDOR_ST_A_M45PE16:
13029 case FLASH_5761VENDOR_ST_M_M45PE20:
13030 case FLASH_5761VENDOR_ST_M_M45PE40:
13031 case FLASH_5761VENDOR_ST_M_M45PE80:
13032 case FLASH_5761VENDOR_ST_M_M45PE16:
13033 tp->nvram_jedecnum = JEDEC_ST;
13034 tg3_flag_set(tp, NVRAM_BUFFERED);
13035 tg3_flag_set(tp, FLASH);
13036 tp->nvram_pagesize = 256;
13041 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
13044 case FLASH_5761VENDOR_ATMEL_ADB161D:
13045 case FLASH_5761VENDOR_ATMEL_MDB161D:
13046 case FLASH_5761VENDOR_ST_A_M45PE16:
13047 case FLASH_5761VENDOR_ST_M_M45PE16:
13048 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
13050 case FLASH_5761VENDOR_ATMEL_ADB081D:
13051 case FLASH_5761VENDOR_ATMEL_MDB081D:
13052 case FLASH_5761VENDOR_ST_A_M45PE80:
13053 case FLASH_5761VENDOR_ST_M_M45PE80:
13054 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13056 case FLASH_5761VENDOR_ATMEL_ADB041D:
13057 case FLASH_5761VENDOR_ATMEL_MDB041D:
13058 case FLASH_5761VENDOR_ST_A_M45PE40:
13059 case FLASH_5761VENDOR_ST_M_M45PE40:
13060 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13062 case FLASH_5761VENDOR_ATMEL_ADB021D:
13063 case FLASH_5761VENDOR_ATMEL_MDB021D:
13064 case FLASH_5761VENDOR_ST_A_M45PE20:
13065 case FLASH_5761VENDOR_ST_M_M45PE20:
13066 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13072 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
13074 tp->nvram_jedecnum = JEDEC_ATMEL;
13075 tg3_flag_set(tp, NVRAM_BUFFERED);
13076 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13079 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
13083 nvcfg1 = tr32(NVRAM_CFG1);
13085 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13086 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
13087 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
13088 tp->nvram_jedecnum = JEDEC_ATMEL;
13089 tg3_flag_set(tp, NVRAM_BUFFERED);
13090 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13092 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13093 tw32(NVRAM_CFG1, nvcfg1);
13095 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13096 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
13097 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
13098 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
13099 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
13100 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
13101 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
13102 tp->nvram_jedecnum = JEDEC_ATMEL;
13103 tg3_flag_set(tp, NVRAM_BUFFERED);
13104 tg3_flag_set(tp, FLASH);
13106 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13107 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13108 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
13109 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
13110 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13112 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
13113 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
13114 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13116 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
13117 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
13118 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13122 case FLASH_5752VENDOR_ST_M45PE10:
13123 case FLASH_5752VENDOR_ST_M45PE20:
13124 case FLASH_5752VENDOR_ST_M45PE40:
13125 tp->nvram_jedecnum = JEDEC_ST;
13126 tg3_flag_set(tp, NVRAM_BUFFERED);
13127 tg3_flag_set(tp, FLASH);
13129 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13130 case FLASH_5752VENDOR_ST_M45PE10:
13131 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13133 case FLASH_5752VENDOR_ST_M45PE20:
13134 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13136 case FLASH_5752VENDOR_ST_M45PE40:
13137 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13142 tg3_flag_set(tp, NO_NVRAM);
13146 tg3_nvram_get_pagesize(tp, nvcfg1);
13147 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
13148 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
13152 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
13156 nvcfg1 = tr32(NVRAM_CFG1);
13158 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13159 case FLASH_5717VENDOR_ATMEL_EEPROM:
13160 case FLASH_5717VENDOR_MICRO_EEPROM:
13161 tp->nvram_jedecnum = JEDEC_ATMEL;
13162 tg3_flag_set(tp, NVRAM_BUFFERED);
13163 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13165 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13166 tw32(NVRAM_CFG1, nvcfg1);
13168 case FLASH_5717VENDOR_ATMEL_MDB011D:
13169 case FLASH_5717VENDOR_ATMEL_ADB011B:
13170 case FLASH_5717VENDOR_ATMEL_ADB011D:
13171 case FLASH_5717VENDOR_ATMEL_MDB021D:
13172 case FLASH_5717VENDOR_ATMEL_ADB021B:
13173 case FLASH_5717VENDOR_ATMEL_ADB021D:
13174 case FLASH_5717VENDOR_ATMEL_45USPT:
13175 tp->nvram_jedecnum = JEDEC_ATMEL;
13176 tg3_flag_set(tp, NVRAM_BUFFERED);
13177 tg3_flag_set(tp, FLASH);
13179 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13180 case FLASH_5717VENDOR_ATMEL_MDB021D:
13181 /* Detect size with tg3_nvram_get_size() */
13183 case FLASH_5717VENDOR_ATMEL_ADB021B:
13184 case FLASH_5717VENDOR_ATMEL_ADB021D:
13185 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13188 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13192 case FLASH_5717VENDOR_ST_M_M25PE10:
13193 case FLASH_5717VENDOR_ST_A_M25PE10:
13194 case FLASH_5717VENDOR_ST_M_M45PE10:
13195 case FLASH_5717VENDOR_ST_A_M45PE10:
13196 case FLASH_5717VENDOR_ST_M_M25PE20:
13197 case FLASH_5717VENDOR_ST_A_M25PE20:
13198 case FLASH_5717VENDOR_ST_M_M45PE20:
13199 case FLASH_5717VENDOR_ST_A_M45PE20:
13200 case FLASH_5717VENDOR_ST_25USPT:
13201 case FLASH_5717VENDOR_ST_45USPT:
13202 tp->nvram_jedecnum = JEDEC_ST;
13203 tg3_flag_set(tp, NVRAM_BUFFERED);
13204 tg3_flag_set(tp, FLASH);
13206 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13207 case FLASH_5717VENDOR_ST_M_M25PE20:
13208 case FLASH_5717VENDOR_ST_M_M45PE20:
13209 /* Detect size with tg3_nvram_get_size() */
13211 case FLASH_5717VENDOR_ST_A_M25PE20:
13212 case FLASH_5717VENDOR_ST_A_M45PE20:
13213 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13216 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13221 tg3_flag_set(tp, NO_NVRAM);
13225 tg3_nvram_get_pagesize(tp, nvcfg1);
13226 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
13227 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
13230 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
13232 u32 nvcfg1, nvmpinstrp;
13234 nvcfg1 = tr32(NVRAM_CFG1);
13235 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
13237 switch (nvmpinstrp) {
13238 case FLASH_5720_EEPROM_HD:
13239 case FLASH_5720_EEPROM_LD:
13240 tp->nvram_jedecnum = JEDEC_ATMEL;
13241 tg3_flag_set(tp, NVRAM_BUFFERED);
13243 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13244 tw32(NVRAM_CFG1, nvcfg1);
13245 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
13246 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13248 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
13250 case FLASH_5720VENDOR_M_ATMEL_DB011D:
13251 case FLASH_5720VENDOR_A_ATMEL_DB011B:
13252 case FLASH_5720VENDOR_A_ATMEL_DB011D:
13253 case FLASH_5720VENDOR_M_ATMEL_DB021D:
13254 case FLASH_5720VENDOR_A_ATMEL_DB021B:
13255 case FLASH_5720VENDOR_A_ATMEL_DB021D:
13256 case FLASH_5720VENDOR_M_ATMEL_DB041D:
13257 case FLASH_5720VENDOR_A_ATMEL_DB041B:
13258 case FLASH_5720VENDOR_A_ATMEL_DB041D:
13259 case FLASH_5720VENDOR_M_ATMEL_DB081D:
13260 case FLASH_5720VENDOR_A_ATMEL_DB081D:
13261 case FLASH_5720VENDOR_ATMEL_45USPT:
13262 tp->nvram_jedecnum = JEDEC_ATMEL;
13263 tg3_flag_set(tp, NVRAM_BUFFERED);
13264 tg3_flag_set(tp, FLASH);
13266 switch (nvmpinstrp) {
13267 case FLASH_5720VENDOR_M_ATMEL_DB021D:
13268 case FLASH_5720VENDOR_A_ATMEL_DB021B:
13269 case FLASH_5720VENDOR_A_ATMEL_DB021D:
13270 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13272 case FLASH_5720VENDOR_M_ATMEL_DB041D:
13273 case FLASH_5720VENDOR_A_ATMEL_DB041B:
13274 case FLASH_5720VENDOR_A_ATMEL_DB041D:
13275 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13277 case FLASH_5720VENDOR_M_ATMEL_DB081D:
13278 case FLASH_5720VENDOR_A_ATMEL_DB081D:
13279 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13282 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13286 case FLASH_5720VENDOR_M_ST_M25PE10:
13287 case FLASH_5720VENDOR_M_ST_M45PE10:
13288 case FLASH_5720VENDOR_A_ST_M25PE10:
13289 case FLASH_5720VENDOR_A_ST_M45PE10:
13290 case FLASH_5720VENDOR_M_ST_M25PE20:
13291 case FLASH_5720VENDOR_M_ST_M45PE20:
13292 case FLASH_5720VENDOR_A_ST_M25PE20:
13293 case FLASH_5720VENDOR_A_ST_M45PE20:
13294 case FLASH_5720VENDOR_M_ST_M25PE40:
13295 case FLASH_5720VENDOR_M_ST_M45PE40:
13296 case FLASH_5720VENDOR_A_ST_M25PE40:
13297 case FLASH_5720VENDOR_A_ST_M45PE40:
13298 case FLASH_5720VENDOR_M_ST_M25PE80:
13299 case FLASH_5720VENDOR_M_ST_M45PE80:
13300 case FLASH_5720VENDOR_A_ST_M25PE80:
13301 case FLASH_5720VENDOR_A_ST_M45PE80:
13302 case FLASH_5720VENDOR_ST_25USPT:
13303 case FLASH_5720VENDOR_ST_45USPT:
13304 tp->nvram_jedecnum = JEDEC_ST;
13305 tg3_flag_set(tp, NVRAM_BUFFERED);
13306 tg3_flag_set(tp, FLASH);
13308 switch (nvmpinstrp) {
13309 case FLASH_5720VENDOR_M_ST_M25PE20:
13310 case FLASH_5720VENDOR_M_ST_M45PE20:
13311 case FLASH_5720VENDOR_A_ST_M25PE20:
13312 case FLASH_5720VENDOR_A_ST_M45PE20:
13313 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13315 case FLASH_5720VENDOR_M_ST_M25PE40:
13316 case FLASH_5720VENDOR_M_ST_M45PE40:
13317 case FLASH_5720VENDOR_A_ST_M25PE40:
13318 case FLASH_5720VENDOR_A_ST_M45PE40:
13319 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13321 case FLASH_5720VENDOR_M_ST_M25PE80:
13322 case FLASH_5720VENDOR_M_ST_M45PE80:
13323 case FLASH_5720VENDOR_A_ST_M25PE80:
13324 case FLASH_5720VENDOR_A_ST_M45PE80:
13325 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13328 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13333 tg3_flag_set(tp, NO_NVRAM);
13337 tg3_nvram_get_pagesize(tp, nvcfg1);
13338 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
13339 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
13342 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
13343 static void __devinit tg3_nvram_init(struct tg3 *tp)
13345 tw32_f(GRC_EEPROM_ADDR,
13346 (EEPROM_ADDR_FSM_RESET |
13347 (EEPROM_DEFAULT_CLOCK_PERIOD <<
13348 EEPROM_ADDR_CLKPERD_SHIFT)));
13352 /* Enable seeprom accesses. */
13353 tw32_f(GRC_LOCAL_CTRL,
13354 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
13357 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13358 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
13359 tg3_flag_set(tp, NVRAM);
13361 if (tg3_nvram_lock(tp)) {
13362 netdev_warn(tp->dev,
13363 "Cannot get nvram lock, %s failed\n",
13367 tg3_enable_nvram_access(tp);
13369 tp->nvram_size = 0;
13371 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13372 tg3_get_5752_nvram_info(tp);
13373 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13374 tg3_get_5755_nvram_info(tp);
13375 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13376 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13377 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13378 tg3_get_5787_nvram_info(tp);
13379 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
13380 tg3_get_5761_nvram_info(tp);
13381 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13382 tg3_get_5906_nvram_info(tp);
13383 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13384 tg3_flag(tp, 57765_CLASS))
13385 tg3_get_57780_nvram_info(tp);
13386 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13387 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13388 tg3_get_5717_nvram_info(tp);
13389 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13390 tg3_get_5720_nvram_info(tp);
13392 tg3_get_nvram_info(tp);
13394 if (tp->nvram_size == 0)
13395 tg3_get_nvram_size(tp);
13397 tg3_disable_nvram_access(tp);
13398 tg3_nvram_unlock(tp);
13401 tg3_flag_clear(tp, NVRAM);
13402 tg3_flag_clear(tp, NVRAM_BUFFERED);
13404 tg3_get_eeprom_size(tp);
13408 struct subsys_tbl_ent {
13409 u16 subsys_vendor, subsys_devid;
13413 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
13414 /* Broadcom boards. */
13415 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13416 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
13417 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13418 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
13419 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13420 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
13421 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13422 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
13423 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13424 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
13425 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13426 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
13427 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13428 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
13429 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13430 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
13431 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13432 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
13433 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13434 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
13435 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13436 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
13439 { TG3PCI_SUBVENDOR_ID_3COM,
13440 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
13441 { TG3PCI_SUBVENDOR_ID_3COM,
13442 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
13443 { TG3PCI_SUBVENDOR_ID_3COM,
13444 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
13445 { TG3PCI_SUBVENDOR_ID_3COM,
13446 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
13447 { TG3PCI_SUBVENDOR_ID_3COM,
13448 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
13451 { TG3PCI_SUBVENDOR_ID_DELL,
13452 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
13453 { TG3PCI_SUBVENDOR_ID_DELL,
13454 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
13455 { TG3PCI_SUBVENDOR_ID_DELL,
13456 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
13457 { TG3PCI_SUBVENDOR_ID_DELL,
13458 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
13460 /* Compaq boards. */
13461 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13462 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
13463 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13464 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
13465 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13466 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
13467 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13468 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
13469 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13470 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
13473 { TG3PCI_SUBVENDOR_ID_IBM,
13474 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
13477 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
13481 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
13482 if ((subsys_id_to_phy_id[i].subsys_vendor ==
13483 tp->pdev->subsystem_vendor) &&
13484 (subsys_id_to_phy_id[i].subsys_devid ==
13485 tp->pdev->subsystem_device))
13486 return &subsys_id_to_phy_id[i];
13491 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
13495 tp->phy_id = TG3_PHY_ID_INVALID;
13496 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13498 /* Assume an onboard device and WOL capable by default. */
13499 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13500 tg3_flag_set(tp, WOL_CAP);
13502 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13503 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
13504 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13505 tg3_flag_set(tp, IS_NIC);
13507 val = tr32(VCPU_CFGSHDW);
13508 if (val & VCPU_CFGSHDW_ASPM_DBNC)
13509 tg3_flag_set(tp, ASPM_WORKAROUND);
13510 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
13511 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
13512 tg3_flag_set(tp, WOL_ENABLE);
13513 device_set_wakeup_enable(&tp->pdev->dev, true);
13518 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
13519 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13520 u32 nic_cfg, led_cfg;
13521 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
13522 int eeprom_phy_serdes = 0;
13524 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13525 tp->nic_sram_data_cfg = nic_cfg;
13527 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13528 ver >>= NIC_SRAM_DATA_VER_SHIFT;
13529 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13530 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13531 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
13532 (ver > 0) && (ver < 0x100))
13533 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13536 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13538 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13539 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13540 eeprom_phy_serdes = 1;
13542 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13543 if (nic_phy_id != 0) {
13544 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13545 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13547 eeprom_phy_id = (id1 >> 16) << 10;
13548 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13549 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13553 tp->phy_id = eeprom_phy_id;
13554 if (eeprom_phy_serdes) {
13555 if (!tg3_flag(tp, 5705_PLUS))
13556 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13558 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
13561 if (tg3_flag(tp, 5750_PLUS))
13562 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13563 SHASTA_EXT_LED_MODE_MASK);
13565 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13569 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13570 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13573 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13574 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13577 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13578 tp->led_ctrl = LED_CTRL_MODE_MAC;
13580 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13581 * read on some older 5700/5701 bootcode.
13583 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13585 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13587 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13591 case SHASTA_EXT_LED_SHARED:
13592 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13593 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13594 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13595 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13596 LED_CTRL_MODE_PHY_2);
13599 case SHASTA_EXT_LED_MAC:
13600 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13603 case SHASTA_EXT_LED_COMBO:
13604 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13605 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13606 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13607 LED_CTRL_MODE_PHY_2);
13612 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13613 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13614 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13615 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13617 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13618 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13620 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
13621 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13622 if ((tp->pdev->subsystem_vendor ==
13623 PCI_VENDOR_ID_ARIMA) &&
13624 (tp->pdev->subsystem_device == 0x205a ||
13625 tp->pdev->subsystem_device == 0x2063))
13626 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13628 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13629 tg3_flag_set(tp, IS_NIC);
13632 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
13633 tg3_flag_set(tp, ENABLE_ASF);
13634 if (tg3_flag(tp, 5750_PLUS))
13635 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
13638 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
13639 tg3_flag(tp, 5750_PLUS))
13640 tg3_flag_set(tp, ENABLE_APE);
13642 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
13643 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
13644 tg3_flag_clear(tp, WOL_CAP);
13646 if (tg3_flag(tp, WOL_CAP) &&
13647 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
13648 tg3_flag_set(tp, WOL_ENABLE);
13649 device_set_wakeup_enable(&tp->pdev->dev, true);
13652 if (cfg2 & (1 << 17))
13653 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
13655 /* serdes signal pre-emphasis in register 0x590 set by */
13656 /* bootcode if bit 18 is set */
13657 if (cfg2 & (1 << 18))
13658 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
13660 if ((tg3_flag(tp, 57765_PLUS) ||
13661 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13662 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
13663 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
13664 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
13666 if (tg3_flag(tp, PCI_EXPRESS) &&
13667 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13668 !tg3_flag(tp, 57765_PLUS)) {
13671 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13672 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
13673 tg3_flag_set(tp, ASPM_WORKAROUND);
13676 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
13677 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
13678 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
13679 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
13680 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
13681 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
13684 if (tg3_flag(tp, WOL_CAP))
13685 device_set_wakeup_enable(&tp->pdev->dev,
13686 tg3_flag(tp, WOL_ENABLE));
13688 device_set_wakeup_capable(&tp->pdev->dev, false);
13691 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13696 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13697 tw32(OTP_CTRL, cmd);
13699 /* Wait for up to 1 ms for command to execute. */
13700 for (i = 0; i < 100; i++) {
13701 val = tr32(OTP_STATUS);
13702 if (val & OTP_STATUS_CMD_DONE)
13707 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13710 /* Read the gphy configuration from the OTP region of the chip. The gphy
13711 * configuration is a 32-bit value that straddles the alignment boundary.
13712 * We do two 32-bit reads and then shift and merge the results.
13714 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13716 u32 bhalf_otp, thalf_otp;
13718 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13720 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13723 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13725 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13728 thalf_otp = tr32(OTP_READ_DATA);
13730 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13732 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13735 bhalf_otp = tr32(OTP_READ_DATA);
13737 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13740 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13742 u32 adv = ADVERTISED_Autoneg;
13744 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13745 adv |= ADVERTISED_1000baseT_Half |
13746 ADVERTISED_1000baseT_Full;
13748 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13749 adv |= ADVERTISED_100baseT_Half |
13750 ADVERTISED_100baseT_Full |
13751 ADVERTISED_10baseT_Half |
13752 ADVERTISED_10baseT_Full |
13755 adv |= ADVERTISED_FIBRE;
13757 tp->link_config.advertising = adv;
13758 tp->link_config.speed = SPEED_UNKNOWN;
13759 tp->link_config.duplex = DUPLEX_UNKNOWN;
13760 tp->link_config.autoneg = AUTONEG_ENABLE;
13761 tp->link_config.active_speed = SPEED_UNKNOWN;
13762 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
13767 static int __devinit tg3_phy_probe(struct tg3 *tp)
13769 u32 hw_phy_id_1, hw_phy_id_2;
13770 u32 hw_phy_id, hw_phy_id_masked;
13773 /* flow control autonegotiation is default behavior */
13774 tg3_flag_set(tp, PAUSE_AUTONEG);
13775 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13777 if (tg3_flag(tp, ENABLE_APE)) {
13778 switch (tp->pci_fn) {
13780 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
13783 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
13786 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
13789 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
13794 if (tg3_flag(tp, USE_PHYLIB))
13795 return tg3_phy_init(tp);
13797 /* Reading the PHY ID register can conflict with ASF
13798 * firmware access to the PHY hardware.
13801 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13802 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13804 /* Now read the physical PHY_ID from the chip and verify
13805 * that it is sane. If it doesn't look good, we fall back
13806 * to either the hard-coded table based PHY_ID and failing
13807 * that the value found in the eeprom area.
13809 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13810 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13812 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13813 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13814 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13816 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13819 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13820 tp->phy_id = hw_phy_id;
13821 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13822 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13824 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13826 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13827 /* Do nothing, phy ID already set up in
13828 * tg3_get_eeprom_hw_cfg().
13831 struct subsys_tbl_ent *p;
13833 /* No eeprom signature? Try the hardcoded
13834 * subsys device table.
13836 p = tg3_lookup_by_subsys(tp);
13840 tp->phy_id = p->phy_id;
13842 tp->phy_id == TG3_PHY_ID_BCM8002)
13843 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13847 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13848 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13850 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13851 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13852 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13853 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13854 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13856 tg3_phy_init_link_config(tp);
13858 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13859 !tg3_flag(tp, ENABLE_APE) &&
13860 !tg3_flag(tp, ENABLE_ASF)) {
13863 tg3_readphy(tp, MII_BMSR, &bmsr);
13864 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13865 (bmsr & BMSR_LSTATUS))
13866 goto skip_phy_reset;
13868 err = tg3_phy_reset(tp);
13872 tg3_phy_set_wirespeed(tp);
13874 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
13875 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13876 tp->link_config.flowctrl);
13878 tg3_writephy(tp, MII_BMCR,
13879 BMCR_ANENABLE | BMCR_ANRESTART);
13884 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13885 err = tg3_init_5401phy_dsp(tp);
13889 err = tg3_init_5401phy_dsp(tp);
13895 static void __devinit tg3_read_vpd(struct tg3 *tp)
13898 unsigned int block_end, rosize, len;
13902 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
13906 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
13908 goto out_not_found;
13910 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13911 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13912 i += PCI_VPD_LRDT_TAG_SIZE;
13914 if (block_end > vpdlen)
13915 goto out_not_found;
13917 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13918 PCI_VPD_RO_KEYWORD_MFR_ID);
13920 len = pci_vpd_info_field_size(&vpd_data[j]);
13922 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13923 if (j + len > block_end || len != 4 ||
13924 memcmp(&vpd_data[j], "1028", 4))
13927 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13928 PCI_VPD_RO_KEYWORD_VENDOR0);
13932 len = pci_vpd_info_field_size(&vpd_data[j]);
13934 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13935 if (j + len > block_end)
13938 memcpy(tp->fw_ver, &vpd_data[j], len);
13939 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
13943 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13944 PCI_VPD_RO_KEYWORD_PARTNO);
13946 goto out_not_found;
13948 len = pci_vpd_info_field_size(&vpd_data[i]);
13950 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13951 if (len > TG3_BPN_SIZE ||
13952 (len + i) > vpdlen)
13953 goto out_not_found;
13955 memcpy(tp->board_part_number, &vpd_data[i], len);
13959 if (tp->board_part_number[0])
13963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13964 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13965 strcpy(tp->board_part_number, "BCM5717");
13966 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13967 strcpy(tp->board_part_number, "BCM5718");
13970 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13971 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13972 strcpy(tp->board_part_number, "BCM57780");
13973 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13974 strcpy(tp->board_part_number, "BCM57760");
13975 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13976 strcpy(tp->board_part_number, "BCM57790");
13977 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13978 strcpy(tp->board_part_number, "BCM57788");
13981 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13982 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13983 strcpy(tp->board_part_number, "BCM57761");
13984 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13985 strcpy(tp->board_part_number, "BCM57765");
13986 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13987 strcpy(tp->board_part_number, "BCM57781");
13988 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13989 strcpy(tp->board_part_number, "BCM57785");
13990 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13991 strcpy(tp->board_part_number, "BCM57791");
13992 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13993 strcpy(tp->board_part_number, "BCM57795");
13996 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
13997 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
13998 strcpy(tp->board_part_number, "BCM57762");
13999 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
14000 strcpy(tp->board_part_number, "BCM57766");
14001 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
14002 strcpy(tp->board_part_number, "BCM57782");
14003 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
14004 strcpy(tp->board_part_number, "BCM57786");
14007 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14008 strcpy(tp->board_part_number, "BCM95906");
14011 strcpy(tp->board_part_number, "none");
14015 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
14019 if (tg3_nvram_read(tp, offset, &val) ||
14020 (val & 0xfc000000) != 0x0c000000 ||
14021 tg3_nvram_read(tp, offset + 4, &val) ||
14028 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
14030 u32 val, offset, start, ver_offset;
14032 bool newver = false;
14034 if (tg3_nvram_read(tp, 0xc, &offset) ||
14035 tg3_nvram_read(tp, 0x4, &start))
14038 offset = tg3_nvram_logical_addr(tp, offset);
14040 if (tg3_nvram_read(tp, offset, &val))
14043 if ((val & 0xfc000000) == 0x0c000000) {
14044 if (tg3_nvram_read(tp, offset + 4, &val))
14051 dst_off = strlen(tp->fw_ver);
14054 if (TG3_VER_SIZE - dst_off < 16 ||
14055 tg3_nvram_read(tp, offset + 8, &ver_offset))
14058 offset = offset + ver_offset - start;
14059 for (i = 0; i < 16; i += 4) {
14061 if (tg3_nvram_read_be32(tp, offset + i, &v))
14064 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
14069 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
14072 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
14073 TG3_NVM_BCVER_MAJSFT;
14074 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
14075 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
14076 "v%d.%02d", major, minor);
14080 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
14082 u32 val, major, minor;
14084 /* Use native endian representation */
14085 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
14088 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
14089 TG3_NVM_HWSB_CFG1_MAJSFT;
14090 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
14091 TG3_NVM_HWSB_CFG1_MINSFT;
14093 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
14096 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
14098 u32 offset, major, minor, build;
14100 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
14102 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
14105 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
14106 case TG3_EEPROM_SB_REVISION_0:
14107 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
14109 case TG3_EEPROM_SB_REVISION_2:
14110 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
14112 case TG3_EEPROM_SB_REVISION_3:
14113 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
14115 case TG3_EEPROM_SB_REVISION_4:
14116 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
14118 case TG3_EEPROM_SB_REVISION_5:
14119 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
14121 case TG3_EEPROM_SB_REVISION_6:
14122 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
14128 if (tg3_nvram_read(tp, offset, &val))
14131 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
14132 TG3_EEPROM_SB_EDH_BLD_SHFT;
14133 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
14134 TG3_EEPROM_SB_EDH_MAJ_SHFT;
14135 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
14137 if (minor > 99 || build > 26)
14140 offset = strlen(tp->fw_ver);
14141 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
14142 " v%d.%02d", major, minor);
14145 offset = strlen(tp->fw_ver);
14146 if (offset < TG3_VER_SIZE - 1)
14147 tp->fw_ver[offset] = 'a' + build - 1;
14151 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
14153 u32 val, offset, start;
14156 for (offset = TG3_NVM_DIR_START;
14157 offset < TG3_NVM_DIR_END;
14158 offset += TG3_NVM_DIRENT_SIZE) {
14159 if (tg3_nvram_read(tp, offset, &val))
14162 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
14166 if (offset == TG3_NVM_DIR_END)
14169 if (!tg3_flag(tp, 5705_PLUS))
14170 start = 0x08000000;
14171 else if (tg3_nvram_read(tp, offset - 4, &start))
14174 if (tg3_nvram_read(tp, offset + 4, &offset) ||
14175 !tg3_fw_img_is_valid(tp, offset) ||
14176 tg3_nvram_read(tp, offset + 8, &val))
14179 offset += val - start;
14181 vlen = strlen(tp->fw_ver);
14183 tp->fw_ver[vlen++] = ',';
14184 tp->fw_ver[vlen++] = ' ';
14186 for (i = 0; i < 4; i++) {
14188 if (tg3_nvram_read_be32(tp, offset, &v))
14191 offset += sizeof(v);
14193 if (vlen > TG3_VER_SIZE - sizeof(v)) {
14194 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
14198 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
14203 static void __devinit tg3_probe_ncsi(struct tg3 *tp)
14207 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
14208 if (apedata != APE_SEG_SIG_MAGIC)
14211 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
14212 if (!(apedata & APE_FW_STATUS_READY))
14215 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
14216 tg3_flag_set(tp, APE_HAS_NCSI);
14219 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
14225 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
14227 if (tg3_flag(tp, APE_HAS_NCSI))
14232 vlen = strlen(tp->fw_ver);
14234 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
14236 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
14237 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
14238 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
14239 (apedata & APE_FW_VERSION_BLDMSK));
14242 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
14245 bool vpd_vers = false;
14247 if (tp->fw_ver[0] != 0)
14250 if (tg3_flag(tp, NO_NVRAM)) {
14251 strcat(tp->fw_ver, "sb");
14255 if (tg3_nvram_read(tp, 0, &val))
14258 if (val == TG3_EEPROM_MAGIC)
14259 tg3_read_bc_ver(tp);
14260 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
14261 tg3_read_sb_ver(tp, val);
14262 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
14263 tg3_read_hwsb_ver(tp);
14265 if (tg3_flag(tp, ENABLE_ASF)) {
14266 if (tg3_flag(tp, ENABLE_APE)) {
14267 tg3_probe_ncsi(tp);
14269 tg3_read_dash_ver(tp);
14270 } else if (!vpd_vers) {
14271 tg3_read_mgmtfw_ver(tp);
14275 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
14278 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
14280 if (tg3_flag(tp, LRG_PROD_RING_CAP))
14281 return TG3_RX_RET_MAX_SIZE_5717;
14282 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
14283 return TG3_RX_RET_MAX_SIZE_5700;
14285 return TG3_RX_RET_MAX_SIZE_5705;
14288 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
14289 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
14290 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
14291 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
14295 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14297 struct pci_dev *peer;
14298 unsigned int func, devnr = tp->pdev->devfn & ~7;
14300 for (func = 0; func < 8; func++) {
14301 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14302 if (peer && peer != tp->pdev)
14306 /* 5704 can be configured in single-port mode, set peer to
14307 * tp->pdev in that case.
14315 * We don't need to keep the refcount elevated; there's no way
14316 * to remove one half of this device without removing the other
14323 static void __devinit tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
14325 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
14326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
14329 /* All devices that use the alternate
14330 * ASIC REV location have a CPMU.
14332 tg3_flag_set(tp, CPMU_PRESENT);
14334 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
14335 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
14336 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
14337 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
14338 reg = TG3PCI_GEN2_PRODID_ASICREV;
14339 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
14340 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
14341 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
14342 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
14343 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14344 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14345 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
14346 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
14347 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
14348 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
14349 reg = TG3PCI_GEN15_PRODID_ASICREV;
14351 reg = TG3PCI_PRODID_ASICREV;
14353 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
14356 /* Wrong chip ID in 5752 A0. This code can be removed later
14357 * as A0 is not in production.
14359 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
14360 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
14362 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14365 tg3_flag_set(tp, 5717_PLUS);
14367 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
14368 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
14369 tg3_flag_set(tp, 57765_CLASS);
14371 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS))
14372 tg3_flag_set(tp, 57765_PLUS);
14374 /* Intentionally exclude ASIC_REV_5906 */
14375 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14376 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14377 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14378 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14379 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14380 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14381 tg3_flag(tp, 57765_PLUS))
14382 tg3_flag_set(tp, 5755_PLUS);
14384 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
14385 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14386 tg3_flag_set(tp, 5780_CLASS);
14388 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14389 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14390 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14391 tg3_flag(tp, 5755_PLUS) ||
14392 tg3_flag(tp, 5780_CLASS))
14393 tg3_flag_set(tp, 5750_PLUS);
14395 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14396 tg3_flag(tp, 5750_PLUS))
14397 tg3_flag_set(tp, 5705_PLUS);
14400 static int __devinit tg3_get_invariants(struct tg3 *tp)
14403 u32 pci_state_reg, grc_misc_cfg;
14408 /* Force memory write invalidate off. If we leave it on,
14409 * then on 5700_BX chips we have to enable a workaround.
14410 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
14411 * to match the cacheline size. The Broadcom driver have this
14412 * workaround but turns MWI off all the times so never uses
14413 * it. This seems to suggest that the workaround is insufficient.
14415 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14416 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
14417 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14419 /* Important! -- Make sure register accesses are byteswapped
14420 * correctly. Also, for those chips that require it, make
14421 * sure that indirect register accesses are enabled before
14422 * the first operation.
14424 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14426 tp->misc_host_ctrl |= (misc_ctrl_reg &
14427 MISC_HOST_CTRL_CHIPREV);
14428 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14429 tp->misc_host_ctrl);
14431 tg3_detect_asic_rev(tp, misc_ctrl_reg);
14433 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
14434 * we need to disable memory and use config. cycles
14435 * only to access all registers. The 5702/03 chips
14436 * can mistakenly decode the special cycles from the
14437 * ICH chipsets as memory write cycles, causing corruption
14438 * of register and memory space. Only certain ICH bridges
14439 * will drive special cycles with non-zero data during the
14440 * address phase which can fall within the 5703's address
14441 * range. This is not an ICH bug as the PCI spec allows
14442 * non-zero address during special cycles. However, only
14443 * these ICH bridges are known to drive non-zero addresses
14444 * during special cycles.
14446 * Since special cycles do not cross PCI bridges, we only
14447 * enable this workaround if the 5703 is on the secondary
14448 * bus of these ICH bridges.
14450 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
14451 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
14452 static struct tg3_dev_id {
14456 } ich_chipsets[] = {
14457 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
14459 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
14461 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
14463 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
14467 struct tg3_dev_id *pci_id = &ich_chipsets[0];
14468 struct pci_dev *bridge = NULL;
14470 while (pci_id->vendor != 0) {
14471 bridge = pci_get_device(pci_id->vendor, pci_id->device,
14477 if (pci_id->rev != PCI_ANY_ID) {
14478 if (bridge->revision > pci_id->rev)
14481 if (bridge->subordinate &&
14482 (bridge->subordinate->number ==
14483 tp->pdev->bus->number)) {
14484 tg3_flag_set(tp, ICH_WORKAROUND);
14485 pci_dev_put(bridge);
14491 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14492 static struct tg3_dev_id {
14495 } bridge_chipsets[] = {
14496 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
14497 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
14500 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
14501 struct pci_dev *bridge = NULL;
14503 while (pci_id->vendor != 0) {
14504 bridge = pci_get_device(pci_id->vendor,
14511 if (bridge->subordinate &&
14512 (bridge->subordinate->number <=
14513 tp->pdev->bus->number) &&
14514 (bridge->subordinate->busn_res.end >=
14515 tp->pdev->bus->number)) {
14516 tg3_flag_set(tp, 5701_DMA_BUG);
14517 pci_dev_put(bridge);
14523 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
14524 * DMA addresses > 40-bit. This bridge may have other additional
14525 * 57xx devices behind it in some 4-port NIC designs for example.
14526 * Any tg3 device found behind the bridge will also need the 40-bit
14529 if (tg3_flag(tp, 5780_CLASS)) {
14530 tg3_flag_set(tp, 40BIT_DMA_BUG);
14531 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
14533 struct pci_dev *bridge = NULL;
14536 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
14537 PCI_DEVICE_ID_SERVERWORKS_EPB,
14539 if (bridge && bridge->subordinate &&
14540 (bridge->subordinate->number <=
14541 tp->pdev->bus->number) &&
14542 (bridge->subordinate->busn_res.end >=
14543 tp->pdev->bus->number)) {
14544 tg3_flag_set(tp, 40BIT_DMA_BUG);
14545 pci_dev_put(bridge);
14551 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14552 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14553 tp->pdev_peer = tg3_find_peer(tp);
14555 /* Determine TSO capabilities */
14556 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
14557 ; /* Do nothing. HW bug. */
14558 else if (tg3_flag(tp, 57765_PLUS))
14559 tg3_flag_set(tp, HW_TSO_3);
14560 else if (tg3_flag(tp, 5755_PLUS) ||
14561 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14562 tg3_flag_set(tp, HW_TSO_2);
14563 else if (tg3_flag(tp, 5750_PLUS)) {
14564 tg3_flag_set(tp, HW_TSO_1);
14565 tg3_flag_set(tp, TSO_BUG);
14566 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
14567 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
14568 tg3_flag_clear(tp, TSO_BUG);
14569 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14570 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14571 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
14572 tg3_flag_set(tp, TSO_BUG);
14573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14574 tp->fw_needed = FIRMWARE_TG3TSO5;
14576 tp->fw_needed = FIRMWARE_TG3TSO;
14579 /* Selectively allow TSO based on operating conditions */
14580 if (tg3_flag(tp, HW_TSO_1) ||
14581 tg3_flag(tp, HW_TSO_2) ||
14582 tg3_flag(tp, HW_TSO_3) ||
14584 /* For firmware TSO, assume ASF is disabled.
14585 * We'll disable TSO later if we discover ASF
14586 * is enabled in tg3_get_eeprom_hw_cfg().
14588 tg3_flag_set(tp, TSO_CAPABLE);
14590 tg3_flag_clear(tp, TSO_CAPABLE);
14591 tg3_flag_clear(tp, TSO_BUG);
14592 tp->fw_needed = NULL;
14595 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14596 tp->fw_needed = FIRMWARE_TG3;
14600 if (tg3_flag(tp, 5750_PLUS)) {
14601 tg3_flag_set(tp, SUPPORT_MSI);
14602 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14603 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14604 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14605 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14606 tp->pdev_peer == tp->pdev))
14607 tg3_flag_clear(tp, SUPPORT_MSI);
14609 if (tg3_flag(tp, 5755_PLUS) ||
14610 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14611 tg3_flag_set(tp, 1SHOT_MSI);
14614 if (tg3_flag(tp, 57765_PLUS)) {
14615 tg3_flag_set(tp, SUPPORT_MSIX);
14616 tp->irq_max = TG3_IRQ_MAX_VECS;
14622 if (tp->irq_max > 1) {
14623 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
14624 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
14626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14627 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14628 tp->txq_max = tp->irq_max - 1;
14631 if (tg3_flag(tp, 5755_PLUS) ||
14632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14633 tg3_flag_set(tp, SHORT_DMA_BUG);
14635 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14636 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
14638 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14639 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14641 tg3_flag_set(tp, LRG_PROD_RING_CAP);
14643 if (tg3_flag(tp, 57765_PLUS) &&
14644 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
14645 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
14647 if (!tg3_flag(tp, 5705_PLUS) ||
14648 tg3_flag(tp, 5780_CLASS) ||
14649 tg3_flag(tp, USE_JUMBO_BDFLAG))
14650 tg3_flag_set(tp, JUMBO_CAPABLE);
14652 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14655 if (pci_is_pcie(tp->pdev)) {
14658 tg3_flag_set(tp, PCI_EXPRESS);
14660 pci_read_config_word(tp->pdev,
14661 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
14663 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
14664 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14666 tg3_flag_clear(tp, HW_TSO_2);
14667 tg3_flag_clear(tp, TSO_CAPABLE);
14669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14670 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14671 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14672 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
14673 tg3_flag_set(tp, CLKREQ_BUG);
14674 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
14675 tg3_flag_set(tp, L1PLLPD_EN);
14677 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
14678 /* BCM5785 devices are effectively PCIe devices, and should
14679 * follow PCIe codepaths, but do not have a PCIe capabilities
14682 tg3_flag_set(tp, PCI_EXPRESS);
14683 } else if (!tg3_flag(tp, 5705_PLUS) ||
14684 tg3_flag(tp, 5780_CLASS)) {
14685 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14686 if (!tp->pcix_cap) {
14687 dev_err(&tp->pdev->dev,
14688 "Cannot find PCI-X capability, aborting\n");
14692 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
14693 tg3_flag_set(tp, PCIX_MODE);
14696 /* If we have an AMD 762 or VIA K8T800 chipset, write
14697 * reordering to the mailbox registers done by the host
14698 * controller can cause major troubles. We read back from
14699 * every mailbox register write to force the writes to be
14700 * posted to the chip in order.
14702 if (pci_dev_present(tg3_write_reorder_chipsets) &&
14703 !tg3_flag(tp, PCI_EXPRESS))
14704 tg3_flag_set(tp, MBOX_WRITE_REORDER);
14706 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14707 &tp->pci_cacheline_sz);
14708 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14709 &tp->pci_lat_timer);
14710 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14711 tp->pci_lat_timer < 64) {
14712 tp->pci_lat_timer = 64;
14713 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14714 tp->pci_lat_timer);
14717 /* Important! -- It is critical that the PCI-X hw workaround
14718 * situation is decided before the first MMIO register access.
14720 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14721 /* 5700 BX chips need to have their TX producer index
14722 * mailboxes written twice to workaround a bug.
14724 tg3_flag_set(tp, TXD_MBOX_HWBUG);
14726 /* If we are in PCI-X mode, enable register write workaround.
14728 * The workaround is to use indirect register accesses
14729 * for all chip writes not to mailbox registers.
14731 if (tg3_flag(tp, PCIX_MODE)) {
14734 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14736 /* The chip can have it's power management PCI config
14737 * space registers clobbered due to this bug.
14738 * So explicitly force the chip into D0 here.
14740 pci_read_config_dword(tp->pdev,
14741 tp->pm_cap + PCI_PM_CTRL,
14743 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14744 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
14745 pci_write_config_dword(tp->pdev,
14746 tp->pm_cap + PCI_PM_CTRL,
14749 /* Also, force SERR#/PERR# in PCI command. */
14750 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14751 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14752 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14756 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
14757 tg3_flag_set(tp, PCI_HIGH_SPEED);
14758 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
14759 tg3_flag_set(tp, PCI_32BIT);
14761 /* Chip-specific fixup from Broadcom driver */
14762 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14763 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14764 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14765 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14768 /* Default fast path register access methods */
14769 tp->read32 = tg3_read32;
14770 tp->write32 = tg3_write32;
14771 tp->read32_mbox = tg3_read32;
14772 tp->write32_mbox = tg3_write32;
14773 tp->write32_tx_mbox = tg3_write32;
14774 tp->write32_rx_mbox = tg3_write32;
14776 /* Various workaround register access methods */
14777 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
14778 tp->write32 = tg3_write_indirect_reg32;
14779 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14780 (tg3_flag(tp, PCI_EXPRESS) &&
14781 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14783 * Back to back register writes can cause problems on these
14784 * chips, the workaround is to read back all reg writes
14785 * except those to mailbox regs.
14787 * See tg3_write_indirect_reg32().
14789 tp->write32 = tg3_write_flush_reg32;
14792 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14793 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14794 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14795 tp->write32_rx_mbox = tg3_write_flush_reg32;
14798 if (tg3_flag(tp, ICH_WORKAROUND)) {
14799 tp->read32 = tg3_read_indirect_reg32;
14800 tp->write32 = tg3_write_indirect_reg32;
14801 tp->read32_mbox = tg3_read_indirect_mbox;
14802 tp->write32_mbox = tg3_write_indirect_mbox;
14803 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14804 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14809 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14810 pci_cmd &= ~PCI_COMMAND_MEMORY;
14811 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14813 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14814 tp->read32_mbox = tg3_read32_mbox_5906;
14815 tp->write32_mbox = tg3_write32_mbox_5906;
14816 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14817 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14820 if (tp->write32 == tg3_write_indirect_reg32 ||
14821 (tg3_flag(tp, PCIX_MODE) &&
14822 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14823 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14824 tg3_flag_set(tp, SRAM_USE_CONFIG);
14826 /* The memory arbiter has to be enabled in order for SRAM accesses
14827 * to succeed. Normally on powerup the tg3 chip firmware will make
14828 * sure it is enabled, but other entities such as system netboot
14829 * code might disable it.
14831 val = tr32(MEMARB_MODE);
14832 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14834 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14835 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14836 tg3_flag(tp, 5780_CLASS)) {
14837 if (tg3_flag(tp, PCIX_MODE)) {
14838 pci_read_config_dword(tp->pdev,
14839 tp->pcix_cap + PCI_X_STATUS,
14841 tp->pci_fn = val & 0x7;
14843 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14844 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14845 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14846 NIC_SRAM_CPMUSTAT_SIG) {
14847 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14848 tp->pci_fn = tp->pci_fn ? 1 : 0;
14850 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14851 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14852 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14853 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14854 NIC_SRAM_CPMUSTAT_SIG) {
14855 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14856 TG3_CPMU_STATUS_FSHFT_5719;
14860 /* Get eeprom hw config before calling tg3_set_power_state().
14861 * In particular, the TG3_FLAG_IS_NIC flag must be
14862 * determined before calling tg3_set_power_state() so that
14863 * we know whether or not to switch out of Vaux power.
14864 * When the flag is set, it means that GPIO1 is used for eeprom
14865 * write protect and also implies that it is a LOM where GPIOs
14866 * are not used to switch power.
14868 tg3_get_eeprom_hw_cfg(tp);
14870 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
14871 tg3_flag_clear(tp, TSO_CAPABLE);
14872 tg3_flag_clear(tp, TSO_BUG);
14873 tp->fw_needed = NULL;
14876 if (tg3_flag(tp, ENABLE_APE)) {
14877 /* Allow reads and writes to the
14878 * APE register and memory space.
14880 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14881 PCISTATE_ALLOW_APE_SHMEM_WR |
14882 PCISTATE_ALLOW_APE_PSPACE_WR;
14883 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14886 tg3_ape_lock_init(tp);
14889 /* Set up tp->grc_local_ctrl before calling
14890 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14891 * will bring 5700's external PHY out of reset.
14892 * It is also used as eeprom write protect on LOMs.
14894 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14896 tg3_flag(tp, EEPROM_WRITE_PROT))
14897 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14898 GRC_LCLCTRL_GPIO_OUTPUT1);
14899 /* Unused GPIO3 must be driven as output on 5752 because there
14900 * are no pull-up resistors on unused GPIO pins.
14902 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14903 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14907 tg3_flag(tp, 57765_CLASS))
14908 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14910 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14911 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14912 /* Turn off the debug UART. */
14913 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14914 if (tg3_flag(tp, IS_NIC))
14915 /* Keep VMain power. */
14916 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14917 GRC_LCLCTRL_GPIO_OUTPUT0;
14920 /* Switch out of Vaux if it is a NIC */
14921 tg3_pwrsrc_switch_to_vmain(tp);
14923 /* Derive initial jumbo mode from MTU assigned in
14924 * ether_setup() via the alloc_etherdev() call
14926 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14927 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14929 /* Determine WakeOnLan speed to use. */
14930 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14931 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14932 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14933 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14934 tg3_flag_clear(tp, WOL_SPEED_100MB);
14936 tg3_flag_set(tp, WOL_SPEED_100MB);
14939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14940 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14942 /* A few boards don't want Ethernet@WireSpeed phy feature */
14943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14944 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14945 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14946 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14947 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14948 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14949 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14951 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14952 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14953 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14954 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14955 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14957 if (tg3_flag(tp, 5705_PLUS) &&
14958 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14959 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14960 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14961 !tg3_flag(tp, 57765_PLUS)) {
14962 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14963 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14964 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14966 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14967 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14968 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14969 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14970 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14972 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14976 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14977 tp->phy_otp = tg3_read_otp_phycfg(tp);
14978 if (tp->phy_otp == 0)
14979 tp->phy_otp = TG3_OTP_DEFAULT;
14982 if (tg3_flag(tp, CPMU_PRESENT))
14983 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14985 tp->mi_mode = MAC_MI_MODE_BASE;
14987 tp->coalesce_mode = 0;
14988 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14989 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14990 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14992 /* Set these bits to enable statistics workaround. */
14993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14994 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14995 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14996 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14997 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
15000 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15001 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15002 tg3_flag_set(tp, USE_PHYLIB);
15004 err = tg3_mdio_init(tp);
15008 /* Initialize data/descriptor byte/word swapping. */
15009 val = tr32(GRC_MODE);
15010 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
15011 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
15012 GRC_MODE_WORD_SWAP_B2HRX_DATA |
15013 GRC_MODE_B2HRX_ENABLE |
15014 GRC_MODE_HTX2B_ENABLE |
15015 GRC_MODE_HOST_STACKUP);
15017 val &= GRC_MODE_HOST_STACKUP;
15019 tw32(GRC_MODE, val | tp->grc_mode);
15021 tg3_switch_clocks(tp);
15023 /* Clear this out for sanity. */
15024 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
15026 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
15028 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
15029 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
15030 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
15032 if (chiprevid == CHIPREV_ID_5701_A0 ||
15033 chiprevid == CHIPREV_ID_5701_B0 ||
15034 chiprevid == CHIPREV_ID_5701_B2 ||
15035 chiprevid == CHIPREV_ID_5701_B5) {
15036 void __iomem *sram_base;
15038 /* Write some dummy words into the SRAM status block
15039 * area, see if it reads back correctly. If the return
15040 * value is bad, force enable the PCIX workaround.
15042 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
15044 writel(0x00000000, sram_base);
15045 writel(0x00000000, sram_base + 4);
15046 writel(0xffffffff, sram_base + 4);
15047 if (readl(sram_base) != 0x00000000)
15048 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
15053 tg3_nvram_init(tp);
15055 grc_misc_cfg = tr32(GRC_MISC_CFG);
15056 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
15058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
15059 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
15060 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
15061 tg3_flag_set(tp, IS_5788);
15063 if (!tg3_flag(tp, IS_5788) &&
15064 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
15065 tg3_flag_set(tp, TAGGED_STATUS);
15066 if (tg3_flag(tp, TAGGED_STATUS)) {
15067 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
15068 HOSTCC_MODE_CLRTICK_TXBD);
15070 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
15071 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15072 tp->misc_host_ctrl);
15075 /* Preserve the APE MAC_MODE bits */
15076 if (tg3_flag(tp, ENABLE_APE))
15077 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
15081 /* these are limited to 10/100 only */
15082 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
15083 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
15084 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
15085 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
15086 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
15087 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
15088 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
15089 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
15090 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
15091 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
15092 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
15093 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
15094 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15095 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15096 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15097 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
15099 err = tg3_phy_probe(tp);
15101 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
15102 /* ... but do not return immediately ... */
15107 tg3_read_fw_ver(tp);
15109 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
15110 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
15112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
15113 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
15115 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
15118 /* 5700 {AX,BX} chips have a broken status block link
15119 * change bit implementation, so we must use the
15120 * status register in those cases.
15122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
15123 tg3_flag_set(tp, USE_LINKCHG_REG);
15125 tg3_flag_clear(tp, USE_LINKCHG_REG);
15127 /* The led_ctrl is set during tg3_phy_probe, here we might
15128 * have to force the link status polling mechanism based
15129 * upon subsystem IDs.
15131 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
15132 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
15133 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
15134 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
15135 tg3_flag_set(tp, USE_LINKCHG_REG);
15138 /* For all SERDES we poll the MAC status register. */
15139 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
15140 tg3_flag_set(tp, POLL_SERDES);
15142 tg3_flag_clear(tp, POLL_SERDES);
15144 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
15145 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
15146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
15147 tg3_flag(tp, PCIX_MODE)) {
15148 tp->rx_offset = NET_SKB_PAD;
15149 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
15150 tp->rx_copy_thresh = ~(u16)0;
15154 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
15155 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
15156 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
15158 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
15160 /* Increment the rx prod index on the rx std ring by at most
15161 * 8 for these chips to workaround hw errata.
15163 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
15164 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
15165 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
15166 tp->rx_std_max_post = 8;
15168 if (tg3_flag(tp, ASPM_WORKAROUND))
15169 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
15170 PCIE_PWR_MGMT_L1_THRESH_MSK;
15175 #ifdef CONFIG_SPARC
15176 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
15178 struct net_device *dev = tp->dev;
15179 struct pci_dev *pdev = tp->pdev;
15180 struct device_node *dp = pci_device_to_OF_node(pdev);
15181 const unsigned char *addr;
15184 addr = of_get_property(dp, "local-mac-address", &len);
15185 if (addr && len == 6) {
15186 memcpy(dev->dev_addr, addr, 6);
15187 memcpy(dev->perm_addr, dev->dev_addr, 6);
15193 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
15195 struct net_device *dev = tp->dev;
15197 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
15198 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
15203 static int __devinit tg3_get_device_address(struct tg3 *tp)
15205 struct net_device *dev = tp->dev;
15206 u32 hi, lo, mac_offset;
15209 #ifdef CONFIG_SPARC
15210 if (!tg3_get_macaddr_sparc(tp))
15215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
15216 tg3_flag(tp, 5780_CLASS)) {
15217 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
15219 if (tg3_nvram_lock(tp))
15220 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
15222 tg3_nvram_unlock(tp);
15223 } else if (tg3_flag(tp, 5717_PLUS)) {
15224 if (tp->pci_fn & 1)
15226 if (tp->pci_fn > 1)
15227 mac_offset += 0x18c;
15228 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
15231 /* First try to get it from MAC address mailbox. */
15232 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
15233 if ((hi >> 16) == 0x484b) {
15234 dev->dev_addr[0] = (hi >> 8) & 0xff;
15235 dev->dev_addr[1] = (hi >> 0) & 0xff;
15237 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
15238 dev->dev_addr[2] = (lo >> 24) & 0xff;
15239 dev->dev_addr[3] = (lo >> 16) & 0xff;
15240 dev->dev_addr[4] = (lo >> 8) & 0xff;
15241 dev->dev_addr[5] = (lo >> 0) & 0xff;
15243 /* Some old bootcode may report a 0 MAC address in SRAM */
15244 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
15247 /* Next, try NVRAM. */
15248 if (!tg3_flag(tp, NO_NVRAM) &&
15249 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
15250 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
15251 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
15252 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
15254 /* Finally just fetch it out of the MAC control regs. */
15256 hi = tr32(MAC_ADDR_0_HIGH);
15257 lo = tr32(MAC_ADDR_0_LOW);
15259 dev->dev_addr[5] = lo & 0xff;
15260 dev->dev_addr[4] = (lo >> 8) & 0xff;
15261 dev->dev_addr[3] = (lo >> 16) & 0xff;
15262 dev->dev_addr[2] = (lo >> 24) & 0xff;
15263 dev->dev_addr[1] = hi & 0xff;
15264 dev->dev_addr[0] = (hi >> 8) & 0xff;
15268 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
15269 #ifdef CONFIG_SPARC
15270 if (!tg3_get_default_macaddr_sparc(tp))
15275 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
15279 #define BOUNDARY_SINGLE_CACHELINE 1
15280 #define BOUNDARY_MULTI_CACHELINE 2
15282 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
15284 int cacheline_size;
15288 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
15290 cacheline_size = 1024;
15292 cacheline_size = (int) byte * 4;
15294 /* On 5703 and later chips, the boundary bits have no
15297 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15298 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
15299 !tg3_flag(tp, PCI_EXPRESS))
15302 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
15303 goal = BOUNDARY_MULTI_CACHELINE;
15305 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
15306 goal = BOUNDARY_SINGLE_CACHELINE;
15312 if (tg3_flag(tp, 57765_PLUS)) {
15313 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
15320 /* PCI controllers on most RISC systems tend to disconnect
15321 * when a device tries to burst across a cache-line boundary.
15322 * Therefore, letting tg3 do so just wastes PCI bandwidth.
15324 * Unfortunately, for PCI-E there are only limited
15325 * write-side controls for this, and thus for reads
15326 * we will still get the disconnects. We'll also waste
15327 * these PCI cycles for both read and write for chips
15328 * other than 5700 and 5701 which do not implement the
15331 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
15332 switch (cacheline_size) {
15337 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15338 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
15339 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
15341 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
15342 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
15347 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
15348 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
15352 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
15353 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
15356 } else if (tg3_flag(tp, PCI_EXPRESS)) {
15357 switch (cacheline_size) {
15361 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15362 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
15363 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
15369 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
15370 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
15374 switch (cacheline_size) {
15376 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15377 val |= (DMA_RWCTRL_READ_BNDRY_16 |
15378 DMA_RWCTRL_WRITE_BNDRY_16);
15383 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15384 val |= (DMA_RWCTRL_READ_BNDRY_32 |
15385 DMA_RWCTRL_WRITE_BNDRY_32);
15390 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15391 val |= (DMA_RWCTRL_READ_BNDRY_64 |
15392 DMA_RWCTRL_WRITE_BNDRY_64);
15397 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15398 val |= (DMA_RWCTRL_READ_BNDRY_128 |
15399 DMA_RWCTRL_WRITE_BNDRY_128);
15404 val |= (DMA_RWCTRL_READ_BNDRY_256 |
15405 DMA_RWCTRL_WRITE_BNDRY_256);
15408 val |= (DMA_RWCTRL_READ_BNDRY_512 |
15409 DMA_RWCTRL_WRITE_BNDRY_512);
15413 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
15414 DMA_RWCTRL_WRITE_BNDRY_1024);
15423 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
15425 struct tg3_internal_buffer_desc test_desc;
15426 u32 sram_dma_descs;
15429 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
15431 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
15432 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
15433 tw32(RDMAC_STATUS, 0);
15434 tw32(WDMAC_STATUS, 0);
15436 tw32(BUFMGR_MODE, 0);
15437 tw32(FTQ_RESET, 0);
15439 test_desc.addr_hi = ((u64) buf_dma) >> 32;
15440 test_desc.addr_lo = buf_dma & 0xffffffff;
15441 test_desc.nic_mbuf = 0x00002100;
15442 test_desc.len = size;
15445 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
15446 * the *second* time the tg3 driver was getting loaded after an
15449 * Broadcom tells me:
15450 * ...the DMA engine is connected to the GRC block and a DMA
15451 * reset may affect the GRC block in some unpredictable way...
15452 * The behavior of resets to individual blocks has not been tested.
15454 * Broadcom noted the GRC reset will also reset all sub-components.
15457 test_desc.cqid_sqid = (13 << 8) | 2;
15459 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
15462 test_desc.cqid_sqid = (16 << 8) | 7;
15464 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
15467 test_desc.flags = 0x00000005;
15469 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
15472 val = *(((u32 *)&test_desc) + i);
15473 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
15474 sram_dma_descs + (i * sizeof(u32)));
15475 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
15477 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
15480 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
15482 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
15485 for (i = 0; i < 40; i++) {
15489 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
15491 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
15492 if ((val & 0xffff) == sram_dma_descs) {
15503 #define TEST_BUFFER_SIZE 0x2000
15505 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
15506 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
15510 static int __devinit tg3_test_dma(struct tg3 *tp)
15512 dma_addr_t buf_dma;
15513 u32 *buf, saved_dma_rwctrl;
15516 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
15517 &buf_dma, GFP_KERNEL);
15523 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
15524 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
15526 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
15528 if (tg3_flag(tp, 57765_PLUS))
15531 if (tg3_flag(tp, PCI_EXPRESS)) {
15532 /* DMA read watermark not used on PCIE */
15533 tp->dma_rwctrl |= 0x00180000;
15534 } else if (!tg3_flag(tp, PCIX_MODE)) {
15535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
15536 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
15537 tp->dma_rwctrl |= 0x003f0000;
15539 tp->dma_rwctrl |= 0x003f000f;
15541 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15542 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
15543 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
15544 u32 read_water = 0x7;
15546 /* If the 5704 is behind the EPB bridge, we can
15547 * do the less restrictive ONE_DMA workaround for
15548 * better performance.
15550 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
15551 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15552 tp->dma_rwctrl |= 0x8000;
15553 else if (ccval == 0x6 || ccval == 0x7)
15554 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
15556 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
15558 /* Set bit 23 to enable PCIX hw bug fix */
15560 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
15561 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
15563 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
15564 /* 5780 always in PCIX mode */
15565 tp->dma_rwctrl |= 0x00144000;
15566 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
15567 /* 5714 always in PCIX mode */
15568 tp->dma_rwctrl |= 0x00148000;
15570 tp->dma_rwctrl |= 0x001b000f;
15574 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15575 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15576 tp->dma_rwctrl &= 0xfffffff0;
15578 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15579 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
15580 /* Remove this if it causes problems for some boards. */
15581 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
15583 /* On 5700/5701 chips, we need to set this bit.
15584 * Otherwise the chip will issue cacheline transactions
15585 * to streamable DMA memory with not all the byte
15586 * enables turned on. This is an error on several
15587 * RISC PCI controllers, in particular sparc64.
15589 * On 5703/5704 chips, this bit has been reassigned
15590 * a different meaning. In particular, it is used
15591 * on those chips to enable a PCI-X workaround.
15593 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15596 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15599 /* Unneeded, already done by tg3_get_invariants. */
15600 tg3_switch_clocks(tp);
15603 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15604 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15607 /* It is best to perform DMA test with maximum write burst size
15608 * to expose the 5700/5701 write DMA bug.
15610 saved_dma_rwctrl = tp->dma_rwctrl;
15611 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15612 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15617 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15620 /* Send the buffer to the chip. */
15621 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15623 dev_err(&tp->pdev->dev,
15624 "%s: Buffer write failed. err = %d\n",
15630 /* validate data reached card RAM correctly. */
15631 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15633 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15634 if (le32_to_cpu(val) != p[i]) {
15635 dev_err(&tp->pdev->dev,
15636 "%s: Buffer corrupted on device! "
15637 "(%d != %d)\n", __func__, val, i);
15638 /* ret = -ENODEV here? */
15643 /* Now read it back. */
15644 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15646 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15647 "err = %d\n", __func__, ret);
15652 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15656 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15657 DMA_RWCTRL_WRITE_BNDRY_16) {
15658 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15659 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15660 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15663 dev_err(&tp->pdev->dev,
15664 "%s: Buffer corrupted on read back! "
15665 "(%d != %d)\n", __func__, p[i], i);
15671 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15677 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15678 DMA_RWCTRL_WRITE_BNDRY_16) {
15679 /* DMA test passed without adjusting DMA boundary,
15680 * now look for chipsets that are known to expose the
15681 * DMA bug without failing the test.
15683 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
15684 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15685 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15687 /* Safe to use the calculated DMA boundary. */
15688 tp->dma_rwctrl = saved_dma_rwctrl;
15691 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15695 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
15700 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15702 if (tg3_flag(tp, 57765_PLUS)) {
15703 tp->bufmgr_config.mbuf_read_dma_low_water =
15704 DEFAULT_MB_RDMA_LOW_WATER_5705;
15705 tp->bufmgr_config.mbuf_mac_rx_low_water =
15706 DEFAULT_MB_MACRX_LOW_WATER_57765;
15707 tp->bufmgr_config.mbuf_high_water =
15708 DEFAULT_MB_HIGH_WATER_57765;
15710 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15711 DEFAULT_MB_RDMA_LOW_WATER_5705;
15712 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15713 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15714 tp->bufmgr_config.mbuf_high_water_jumbo =
15715 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
15716 } else if (tg3_flag(tp, 5705_PLUS)) {
15717 tp->bufmgr_config.mbuf_read_dma_low_water =
15718 DEFAULT_MB_RDMA_LOW_WATER_5705;
15719 tp->bufmgr_config.mbuf_mac_rx_low_water =
15720 DEFAULT_MB_MACRX_LOW_WATER_5705;
15721 tp->bufmgr_config.mbuf_high_water =
15722 DEFAULT_MB_HIGH_WATER_5705;
15723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15724 tp->bufmgr_config.mbuf_mac_rx_low_water =
15725 DEFAULT_MB_MACRX_LOW_WATER_5906;
15726 tp->bufmgr_config.mbuf_high_water =
15727 DEFAULT_MB_HIGH_WATER_5906;
15730 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15731 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15732 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15733 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15734 tp->bufmgr_config.mbuf_high_water_jumbo =
15735 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15737 tp->bufmgr_config.mbuf_read_dma_low_water =
15738 DEFAULT_MB_RDMA_LOW_WATER;
15739 tp->bufmgr_config.mbuf_mac_rx_low_water =
15740 DEFAULT_MB_MACRX_LOW_WATER;
15741 tp->bufmgr_config.mbuf_high_water =
15742 DEFAULT_MB_HIGH_WATER;
15744 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15745 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15746 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15747 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15748 tp->bufmgr_config.mbuf_high_water_jumbo =
15749 DEFAULT_MB_HIGH_WATER_JUMBO;
15752 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15753 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15756 static char * __devinit tg3_phy_string(struct tg3 *tp)
15758 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15759 case TG3_PHY_ID_BCM5400: return "5400";
15760 case TG3_PHY_ID_BCM5401: return "5401";
15761 case TG3_PHY_ID_BCM5411: return "5411";
15762 case TG3_PHY_ID_BCM5701: return "5701";
15763 case TG3_PHY_ID_BCM5703: return "5703";
15764 case TG3_PHY_ID_BCM5704: return "5704";
15765 case TG3_PHY_ID_BCM5705: return "5705";
15766 case TG3_PHY_ID_BCM5750: return "5750";
15767 case TG3_PHY_ID_BCM5752: return "5752";
15768 case TG3_PHY_ID_BCM5714: return "5714";
15769 case TG3_PHY_ID_BCM5780: return "5780";
15770 case TG3_PHY_ID_BCM5755: return "5755";
15771 case TG3_PHY_ID_BCM5787: return "5787";
15772 case TG3_PHY_ID_BCM5784: return "5784";
15773 case TG3_PHY_ID_BCM5756: return "5722/5756";
15774 case TG3_PHY_ID_BCM5906: return "5906";
15775 case TG3_PHY_ID_BCM5761: return "5761";
15776 case TG3_PHY_ID_BCM5718C: return "5718C";
15777 case TG3_PHY_ID_BCM5718S: return "5718S";
15778 case TG3_PHY_ID_BCM57765: return "57765";
15779 case TG3_PHY_ID_BCM5719C: return "5719C";
15780 case TG3_PHY_ID_BCM5720C: return "5720C";
15781 case TG3_PHY_ID_BCM8002: return "8002/serdes";
15782 case 0: return "serdes";
15783 default: return "unknown";
15787 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15789 if (tg3_flag(tp, PCI_EXPRESS)) {
15790 strcpy(str, "PCI Express");
15792 } else if (tg3_flag(tp, PCIX_MODE)) {
15793 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15795 strcpy(str, "PCIX:");
15797 if ((clock_ctrl == 7) ||
15798 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15799 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15800 strcat(str, "133MHz");
15801 else if (clock_ctrl == 0)
15802 strcat(str, "33MHz");
15803 else if (clock_ctrl == 2)
15804 strcat(str, "50MHz");
15805 else if (clock_ctrl == 4)
15806 strcat(str, "66MHz");
15807 else if (clock_ctrl == 6)
15808 strcat(str, "100MHz");
15810 strcpy(str, "PCI:");
15811 if (tg3_flag(tp, PCI_HIGH_SPEED))
15812 strcat(str, "66MHz");
15814 strcat(str, "33MHz");
15816 if (tg3_flag(tp, PCI_32BIT))
15817 strcat(str, ":32-bit");
15819 strcat(str, ":64-bit");
15823 static void __devinit tg3_init_coal(struct tg3 *tp)
15825 struct ethtool_coalesce *ec = &tp->coal;
15827 memset(ec, 0, sizeof(*ec));
15828 ec->cmd = ETHTOOL_GCOALESCE;
15829 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15830 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15831 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15832 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15833 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15834 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15835 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15836 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15837 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15839 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15840 HOSTCC_MODE_CLRTICK_TXBD)) {
15841 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15842 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15843 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15844 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15847 if (tg3_flag(tp, 5705_PLUS)) {
15848 ec->rx_coalesce_usecs_irq = 0;
15849 ec->tx_coalesce_usecs_irq = 0;
15850 ec->stats_block_coalesce_usecs = 0;
15854 static int __devinit tg3_init_one(struct pci_dev *pdev,
15855 const struct pci_device_id *ent)
15857 struct net_device *dev;
15859 int i, err, pm_cap;
15860 u32 sndmbx, rcvmbx, intmbx;
15862 u64 dma_mask, persist_dma_mask;
15863 netdev_features_t features = 0;
15865 printk_once(KERN_INFO "%s\n", version);
15867 err = pci_enable_device(pdev);
15869 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15873 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15875 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15876 goto err_out_disable_pdev;
15879 pci_set_master(pdev);
15881 /* Find power-management capability. */
15882 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15884 dev_err(&pdev->dev,
15885 "Cannot find Power Management capability, aborting\n");
15887 goto err_out_free_res;
15890 err = pci_set_power_state(pdev, PCI_D0);
15892 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15893 goto err_out_free_res;
15896 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15899 goto err_out_power_down;
15902 SET_NETDEV_DEV(dev, &pdev->dev);
15904 tp = netdev_priv(dev);
15907 tp->pm_cap = pm_cap;
15908 tp->rx_mode = TG3_DEF_RX_MODE;
15909 tp->tx_mode = TG3_DEF_TX_MODE;
15912 tp->msg_enable = tg3_debug;
15914 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15916 /* The word/byte swap controls here control register access byte
15917 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15920 tp->misc_host_ctrl =
15921 MISC_HOST_CTRL_MASK_PCI_INT |
15922 MISC_HOST_CTRL_WORD_SWAP |
15923 MISC_HOST_CTRL_INDIR_ACCESS |
15924 MISC_HOST_CTRL_PCISTATE_RW;
15926 /* The NONFRM (non-frame) byte/word swap controls take effect
15927 * on descriptor entries, anything which isn't packet data.
15929 * The StrongARM chips on the board (one for tx, one for rx)
15930 * are running in big-endian mode.
15932 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15933 GRC_MODE_WSWAP_NONFRM_DATA);
15934 #ifdef __BIG_ENDIAN
15935 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15937 spin_lock_init(&tp->lock);
15938 spin_lock_init(&tp->indirect_lock);
15939 INIT_WORK(&tp->reset_task, tg3_reset_task);
15941 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15943 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15945 goto err_out_free_dev;
15948 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15949 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15950 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15951 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15952 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15953 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15954 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15955 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15956 tg3_flag_set(tp, ENABLE_APE);
15957 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15958 if (!tp->aperegs) {
15959 dev_err(&pdev->dev,
15960 "Cannot map APE registers, aborting\n");
15962 goto err_out_iounmap;
15966 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15967 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15969 dev->ethtool_ops = &tg3_ethtool_ops;
15970 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15971 dev->netdev_ops = &tg3_netdev_ops;
15972 dev->irq = pdev->irq;
15974 err = tg3_get_invariants(tp);
15976 dev_err(&pdev->dev,
15977 "Problem fetching invariants of chip, aborting\n");
15978 goto err_out_apeunmap;
15981 /* The EPB bridge inside 5714, 5715, and 5780 and any
15982 * device behind the EPB cannot support DMA addresses > 40-bit.
15983 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15984 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15985 * do DMA address check in tg3_start_xmit().
15987 if (tg3_flag(tp, IS_5788))
15988 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15989 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15990 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15991 #ifdef CONFIG_HIGHMEM
15992 dma_mask = DMA_BIT_MASK(64);
15995 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15997 /* Configure DMA attributes. */
15998 if (dma_mask > DMA_BIT_MASK(32)) {
15999 err = pci_set_dma_mask(pdev, dma_mask);
16001 features |= NETIF_F_HIGHDMA;
16002 err = pci_set_consistent_dma_mask(pdev,
16005 dev_err(&pdev->dev, "Unable to obtain 64 bit "
16006 "DMA for consistent allocations\n");
16007 goto err_out_apeunmap;
16011 if (err || dma_mask == DMA_BIT_MASK(32)) {
16012 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
16014 dev_err(&pdev->dev,
16015 "No usable DMA configuration, aborting\n");
16016 goto err_out_apeunmap;
16020 tg3_init_bufmgr_config(tp);
16022 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
16024 /* 5700 B0 chips do not support checksumming correctly due
16025 * to hardware bugs.
16027 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
16028 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
16030 if (tg3_flag(tp, 5755_PLUS))
16031 features |= NETIF_F_IPV6_CSUM;
16034 /* TSO is on by default on chips that support hardware TSO.
16035 * Firmware TSO on older chips gives lower performance, so it
16036 * is off by default, but can be enabled using ethtool.
16038 if ((tg3_flag(tp, HW_TSO_1) ||
16039 tg3_flag(tp, HW_TSO_2) ||
16040 tg3_flag(tp, HW_TSO_3)) &&
16041 (features & NETIF_F_IP_CSUM))
16042 features |= NETIF_F_TSO;
16043 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
16044 if (features & NETIF_F_IPV6_CSUM)
16045 features |= NETIF_F_TSO6;
16046 if (tg3_flag(tp, HW_TSO_3) ||
16047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
16048 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
16049 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
16050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
16051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
16052 features |= NETIF_F_TSO_ECN;
16055 dev->features |= features;
16056 dev->vlan_features |= features;
16059 * Add loopback capability only for a subset of devices that support
16060 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
16061 * loopback for the remaining devices.
16063 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
16064 !tg3_flag(tp, CPMU_PRESENT))
16065 /* Add the loopback capability */
16066 features |= NETIF_F_LOOPBACK;
16068 dev->hw_features |= features;
16070 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
16071 !tg3_flag(tp, TSO_CAPABLE) &&
16072 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
16073 tg3_flag_set(tp, MAX_RXPEND_64);
16074 tp->rx_pending = 63;
16077 err = tg3_get_device_address(tp);
16079 dev_err(&pdev->dev,
16080 "Could not obtain valid ethernet address, aborting\n");
16081 goto err_out_apeunmap;
16085 * Reset chip in case UNDI or EFI driver did not shutdown
16086 * DMA self test will enable WDMAC and we'll see (spurious)
16087 * pending DMA on the PCI bus at that point.
16089 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
16090 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
16091 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
16092 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
16095 err = tg3_test_dma(tp);
16097 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
16098 goto err_out_apeunmap;
16101 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
16102 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
16103 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
16104 for (i = 0; i < tp->irq_max; i++) {
16105 struct tg3_napi *tnapi = &tp->napi[i];
16108 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
16110 tnapi->int_mbox = intmbx;
16116 tnapi->consmbox = rcvmbx;
16117 tnapi->prodmbox = sndmbx;
16120 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
16122 tnapi->coal_now = HOSTCC_MODE_NOW;
16124 if (!tg3_flag(tp, SUPPORT_MSIX))
16128 * If we support MSIX, we'll be using RSS. If we're using
16129 * RSS, the first vector only handles link interrupts and the
16130 * remaining vectors handle rx and tx interrupts. Reuse the
16131 * mailbox values for the next iteration. The values we setup
16132 * above are still useful for the single vectored mode.
16147 pci_set_drvdata(pdev, dev);
16149 if (tg3_flag(tp, 5717_PLUS)) {
16150 /* Resume a low-power mode */
16151 tg3_frob_aux_power(tp, false);
16154 tg3_timer_init(tp);
16156 err = register_netdev(dev);
16158 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
16159 goto err_out_apeunmap;
16162 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
16163 tp->board_part_number,
16164 tp->pci_chip_rev_id,
16165 tg3_bus_string(tp, str),
16168 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
16169 struct phy_device *phydev;
16170 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
16172 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
16173 phydev->drv->name, dev_name(&phydev->dev));
16177 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
16178 ethtype = "10/100Base-TX";
16179 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
16180 ethtype = "1000Base-SX";
16182 ethtype = "10/100/1000Base-T";
16184 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
16185 "(WireSpeed[%d], EEE[%d])\n",
16186 tg3_phy_string(tp), ethtype,
16187 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
16188 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
16191 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
16192 (dev->features & NETIF_F_RXCSUM) != 0,
16193 tg3_flag(tp, USE_LINKCHG_REG) != 0,
16194 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
16195 tg3_flag(tp, ENABLE_ASF) != 0,
16196 tg3_flag(tp, TSO_CAPABLE) != 0);
16197 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
16199 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
16200 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
16202 pci_save_state(pdev);
16208 iounmap(tp->aperegs);
16209 tp->aperegs = NULL;
16221 err_out_power_down:
16222 pci_set_power_state(pdev, PCI_D3hot);
16225 pci_release_regions(pdev);
16227 err_out_disable_pdev:
16228 pci_disable_device(pdev);
16229 pci_set_drvdata(pdev, NULL);
16233 static void __devexit tg3_remove_one(struct pci_dev *pdev)
16235 struct net_device *dev = pci_get_drvdata(pdev);
16238 struct tg3 *tp = netdev_priv(dev);
16240 release_firmware(tp->fw);
16242 tg3_reset_task_cancel(tp);
16244 if (tg3_flag(tp, USE_PHYLIB)) {
16249 unregister_netdev(dev);
16251 iounmap(tp->aperegs);
16252 tp->aperegs = NULL;
16259 pci_release_regions(pdev);
16260 pci_disable_device(pdev);
16261 pci_set_drvdata(pdev, NULL);
16265 #ifdef CONFIG_PM_SLEEP
16266 static int tg3_suspend(struct device *device)
16268 struct pci_dev *pdev = to_pci_dev(device);
16269 struct net_device *dev = pci_get_drvdata(pdev);
16270 struct tg3 *tp = netdev_priv(dev);
16273 if (!netif_running(dev))
16276 tg3_reset_task_cancel(tp);
16278 tg3_netif_stop(tp);
16280 tg3_timer_stop(tp);
16282 tg3_full_lock(tp, 1);
16283 tg3_disable_ints(tp);
16284 tg3_full_unlock(tp);
16286 netif_device_detach(dev);
16288 tg3_full_lock(tp, 0);
16289 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
16290 tg3_flag_clear(tp, INIT_COMPLETE);
16291 tg3_full_unlock(tp);
16293 err = tg3_power_down_prepare(tp);
16297 tg3_full_lock(tp, 0);
16299 tg3_flag_set(tp, INIT_COMPLETE);
16300 err2 = tg3_restart_hw(tp, 1);
16304 tg3_timer_start(tp);
16306 netif_device_attach(dev);
16307 tg3_netif_start(tp);
16310 tg3_full_unlock(tp);
16319 static int tg3_resume(struct device *device)
16321 struct pci_dev *pdev = to_pci_dev(device);
16322 struct net_device *dev = pci_get_drvdata(pdev);
16323 struct tg3 *tp = netdev_priv(dev);
16326 if (!netif_running(dev))
16329 netif_device_attach(dev);
16331 tg3_full_lock(tp, 0);
16333 tg3_flag_set(tp, INIT_COMPLETE);
16334 err = tg3_restart_hw(tp, 1);
16338 tg3_timer_start(tp);
16340 tg3_netif_start(tp);
16343 tg3_full_unlock(tp);
16351 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
16352 #define TG3_PM_OPS (&tg3_pm_ops)
16356 #define TG3_PM_OPS NULL
16358 #endif /* CONFIG_PM_SLEEP */
16361 * tg3_io_error_detected - called when PCI error is detected
16362 * @pdev: Pointer to PCI device
16363 * @state: The current pci connection state
16365 * This function is called after a PCI bus error affecting
16366 * this device has been detected.
16368 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
16369 pci_channel_state_t state)
16371 struct net_device *netdev = pci_get_drvdata(pdev);
16372 struct tg3 *tp = netdev_priv(netdev);
16373 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
16375 netdev_info(netdev, "PCI I/O error detected\n");
16379 if (!netif_running(netdev))
16384 tg3_netif_stop(tp);
16386 tg3_timer_stop(tp);
16388 /* Want to make sure that the reset task doesn't run */
16389 tg3_reset_task_cancel(tp);
16391 netif_device_detach(netdev);
16393 /* Clean up software state, even if MMIO is blocked */
16394 tg3_full_lock(tp, 0);
16395 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
16396 tg3_full_unlock(tp);
16399 if (state == pci_channel_io_perm_failure)
16400 err = PCI_ERS_RESULT_DISCONNECT;
16402 pci_disable_device(pdev);
16410 * tg3_io_slot_reset - called after the pci bus has been reset.
16411 * @pdev: Pointer to PCI device
16413 * Restart the card from scratch, as if from a cold-boot.
16414 * At this point, the card has exprienced a hard reset,
16415 * followed by fixups by BIOS, and has its config space
16416 * set up identically to what it was at cold boot.
16418 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
16420 struct net_device *netdev = pci_get_drvdata(pdev);
16421 struct tg3 *tp = netdev_priv(netdev);
16422 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
16427 if (pci_enable_device(pdev)) {
16428 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
16432 pci_set_master(pdev);
16433 pci_restore_state(pdev);
16434 pci_save_state(pdev);
16436 if (!netif_running(netdev)) {
16437 rc = PCI_ERS_RESULT_RECOVERED;
16441 err = tg3_power_up(tp);
16445 rc = PCI_ERS_RESULT_RECOVERED;
16454 * tg3_io_resume - called when traffic can start flowing again.
16455 * @pdev: Pointer to PCI device
16457 * This callback is called when the error recovery driver tells
16458 * us that its OK to resume normal operation.
16460 static void tg3_io_resume(struct pci_dev *pdev)
16462 struct net_device *netdev = pci_get_drvdata(pdev);
16463 struct tg3 *tp = netdev_priv(netdev);
16468 if (!netif_running(netdev))
16471 tg3_full_lock(tp, 0);
16472 tg3_flag_set(tp, INIT_COMPLETE);
16473 err = tg3_restart_hw(tp, 1);
16474 tg3_full_unlock(tp);
16476 netdev_err(netdev, "Cannot restart hardware after reset.\n");
16480 netif_device_attach(netdev);
16482 tg3_timer_start(tp);
16484 tg3_netif_start(tp);
16492 static struct pci_error_handlers tg3_err_handler = {
16493 .error_detected = tg3_io_error_detected,
16494 .slot_reset = tg3_io_slot_reset,
16495 .resume = tg3_io_resume
16498 static struct pci_driver tg3_driver = {
16499 .name = DRV_MODULE_NAME,
16500 .id_table = tg3_pci_tbl,
16501 .probe = tg3_init_one,
16502 .remove = __devexit_p(tg3_remove_one),
16503 .err_handler = &tg3_err_handler,
16504 .driver.pm = TG3_PM_OPS,
16507 static int __init tg3_init(void)
16509 return pci_register_driver(&tg3_driver);
16512 static void __exit tg3_cleanup(void)
16514 pci_unregister_driver(&tg3_driver);
16517 module_init(tg3_init);
16518 module_exit(tg3_cleanup);