Pileus Git - ~andy/linux/blob - drivers/net/ethernet/broadcom/cnic_defs.h

   1
   2 /* cnic.c: Broadcom CNIC core network driver.
   3  *
   4  * Copyright (c) 2006-2009 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  *
  10  */
  11
  12 #ifndef CNIC_DEFS_H
  13 #define CNIC_DEFS_H
  14
  15 /* KWQ (kernel work queue) request op codes */
  16 #define L2_KWQE_OPCODE_VALUE_FLUSH                  (4)
  17 #define L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE       (8)
  18
  19 #define L4_KWQE_OPCODE_VALUE_CONNECT1               (50)
  20 #define L4_KWQE_OPCODE_VALUE_CONNECT2               (51)
  21 #define L4_KWQE_OPCODE_VALUE_CONNECT3               (52)
  22 #define L4_KWQE_OPCODE_VALUE_RESET                  (53)
  23 #define L4_KWQE_OPCODE_VALUE_CLOSE                  (54)
  24 #define L4_KWQE_OPCODE_VALUE_UPDATE_SECRET          (60)
  25 #define L4_KWQE_OPCODE_VALUE_INIT_ULP               (61)
  26
  27 #define L4_KWQE_OPCODE_VALUE_OFFLOAD_PG             (1)
  28 #define L4_KWQE_OPCODE_VALUE_UPDATE_PG              (9)
  29 #define L4_KWQE_OPCODE_VALUE_UPLOAD_PG              (14)
  30
  31 #define L5CM_RAMROD_CMD_ID_BASE                 (0x80)
  32 #define L5CM_RAMROD_CMD_ID_TCP_CONNECT          (L5CM_RAMROD_CMD_ID_BASE + 3)
  33 #define L5CM_RAMROD_CMD_ID_CLOSE                (L5CM_RAMROD_CMD_ID_BASE + 12)
  34 #define L5CM_RAMROD_CMD_ID_ABORT                (L5CM_RAMROD_CMD_ID_BASE + 13)
  35 #define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE      (L5CM_RAMROD_CMD_ID_BASE + 14)
  36 #define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD    (L5CM_RAMROD_CMD_ID_BASE + 15)
  37
  38 #define FCOE_KCQE_OPCODE_INIT_FUNC                      (0x10)
  39 #define FCOE_KCQE_OPCODE_DESTROY_FUNC                   (0x11)
  40 #define FCOE_KCQE_OPCODE_STAT_FUNC                      (0x12)
  41 #define FCOE_KCQE_OPCODE_OFFLOAD_CONN                   (0x15)
  42 #define FCOE_KCQE_OPCODE_ENABLE_CONN                    (0x16)
  43 #define FCOE_KCQE_OPCODE_DISABLE_CONN                   (0x17)
  44 #define FCOE_KCQE_OPCODE_DESTROY_CONN                   (0x18)
  45 #define FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION  (0x20)
  46 #define FCOE_KCQE_OPCODE_FCOE_ERROR                             (0x21)
  47
  48 #define FCOE_RAMROD_CMD_ID_INIT_FUNC            (FCOE_KCQE_OPCODE_INIT_FUNC)
  49 #define FCOE_RAMROD_CMD_ID_DESTROY_FUNC         (FCOE_KCQE_OPCODE_DESTROY_FUNC)
  50 #define FCOE_RAMROD_CMD_ID_STAT_FUNC            (FCOE_KCQE_OPCODE_STAT_FUNC)
  51 #define FCOE_RAMROD_CMD_ID_OFFLOAD_CONN         (FCOE_KCQE_OPCODE_OFFLOAD_CONN)
  52 #define FCOE_RAMROD_CMD_ID_ENABLE_CONN          (FCOE_KCQE_OPCODE_ENABLE_CONN)
  53 #define FCOE_RAMROD_CMD_ID_DISABLE_CONN         (FCOE_KCQE_OPCODE_DISABLE_CONN)
  54 #define FCOE_RAMROD_CMD_ID_DESTROY_CONN         (FCOE_KCQE_OPCODE_DESTROY_CONN)
  55 #define FCOE_RAMROD_CMD_ID_TERMINATE_CONN       (0x81)
  56
  57 #define FCOE_KWQE_OPCODE_INIT1                  (0)
  58 #define FCOE_KWQE_OPCODE_INIT2                  (1)
  59 #define FCOE_KWQE_OPCODE_INIT3                  (2)
  60 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN1  (3)
  61 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN2  (4)
  62 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN3  (5)
  63 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN4  (6)
  64 #define FCOE_KWQE_OPCODE_ENABLE_CONN    (7)
  65 #define FCOE_KWQE_OPCODE_DISABLE_CONN   (8)
  66 #define FCOE_KWQE_OPCODE_DESTROY_CONN   (9)
  67 #define FCOE_KWQE_OPCODE_DESTROY                (10)
  68 #define FCOE_KWQE_OPCODE_STAT                   (11)
  69
  70 #define FCOE_KCQE_COMPLETION_STATUS_ERROR       (0x1)
  71 #define FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE   (0x3)
  72
  73 /* KCQ (kernel completion queue) response op codes */
  74 #define L4_KCQE_OPCODE_VALUE_CLOSE_COMP             (53)
  75 #define L4_KCQE_OPCODE_VALUE_RESET_COMP             (54)
  76 #define L4_KCQE_OPCODE_VALUE_FW_TCP_UPDATE          (55)
  77 #define L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE       (56)
  78 #define L4_KCQE_OPCODE_VALUE_RESET_RECEIVED         (57)
  79 #define L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED         (58)
  80 #define L4_KCQE_OPCODE_VALUE_INIT_ULP               (61)
  81
  82 #define L4_KCQE_OPCODE_VALUE_OFFLOAD_PG             (1)
  83 #define L4_KCQE_OPCODE_VALUE_UPDATE_PG              (9)
  84 #define L4_KCQE_OPCODE_VALUE_UPLOAD_PG              (14)
  85
  86 /* KCQ (kernel completion queue) completion status */
  87 #define L4_KCQE_COMPLETION_STATUS_SUCCESS           (0)
  88 #define L4_KCQE_COMPLETION_STATUS_NIC_ERROR         (4)
  89 #define L4_KCQE_COMPLETION_STATUS_TIMEOUT           (0x93)
  90
  91 #define L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL    (0x83)
  92 #define L4_KCQE_COMPLETION_STATUS_OFFLOADED_PG      (0x89)
  93
  94 #define L4_KCQE_OPCODE_VALUE_OOO_EVENT_NOTIFICATION (0xa0)
  95 #define L4_KCQE_OPCODE_VALUE_OOO_FLUSH              (0xa1)
  96
  97 #define L4_LAYER_CODE (4)
  98 #define L2_LAYER_CODE (2)
  99
 100 /*
 101  * L4 KCQ CQE
 102  */
 103 struct l4_kcq {
 104         u32 cid;
 105         u32 pg_cid;
 106         u32 conn_id;
 107         u32 pg_host_opaque;
 108 #if defined(__BIG_ENDIAN)
 109         u16 status;
 110         u16 reserved1;
 111 #elif defined(__LITTLE_ENDIAN)
 112         u16 reserved1;
 113         u16 status;
 114 #endif
 115         u32 reserved2[2];
 116 #if defined(__BIG_ENDIAN)
 117         u8 flags;
 118 #define L4_KCQ_RESERVED3 (0x7<<0)
 119 #define L4_KCQ_RESERVED3_SHIFT 0
 120 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
 121 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3
 122 #define L4_KCQ_LAYER_CODE (0x7<<4)
 123 #define L4_KCQ_LAYER_CODE_SHIFT 4
 124 #define L4_KCQ_RESERVED4 (0x1<<7)
 125 #define L4_KCQ_RESERVED4_SHIFT 7
 126         u8 op_code;
 127         u16 qe_self_seq;
 128 #elif defined(__LITTLE_ENDIAN)
 129         u16 qe_self_seq;
 130         u8 op_code;
 131         u8 flags;
 132 #define L4_KCQ_RESERVED3 (0xF<<0)
 133 #define L4_KCQ_RESERVED3_SHIFT 0
 134 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
 135 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3
 136 #define L4_KCQ_LAYER_CODE (0x7<<4)
 137 #define L4_KCQ_LAYER_CODE_SHIFT 4
 138 #define L4_KCQ_RESERVED4 (0x1<<7)
 139 #define L4_KCQ_RESERVED4_SHIFT 7
 140 #endif
 141 };
 142
 143
 144 /*
 145  * L4 KCQ CQE PG upload
 146  */
 147 struct l4_kcq_upload_pg {
 148         u32 pg_cid;
 149 #if defined(__BIG_ENDIAN)
 150         u16 pg_status;
 151         u16 pg_ipid_count;
 152 #elif defined(__LITTLE_ENDIAN)
 153         u16 pg_ipid_count;
 154         u16 pg_status;
 155 #endif
 156         u32 reserved1[5];
 157 #if defined(__BIG_ENDIAN)
 158         u8 flags;
 159 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0)
 160 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0
 161 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4)
 162 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4
 163 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7)
 164 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7
 165         u8 op_code;
 166         u16 qe_self_seq;
 167 #elif defined(__LITTLE_ENDIAN)
 168         u16 qe_self_seq;
 169         u8 op_code;
 170         u8 flags;
 171 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0)
 172 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0
 173 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4)
 174 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4
 175 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7)
 176 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7
 177 #endif
 178 };
 179
 180
 181 /*
 182  * Gracefully close the connection request
 183  */
 184 struct l4_kwq_close_req {
 185 #if defined(__BIG_ENDIAN)
 186         u8 flags;
 187 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0)
 188 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0
 189 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4)
 190 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4
 191 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7)
 192 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7
 193         u8 op_code;
 194         u16 reserved0;
 195 #elif defined(__LITTLE_ENDIAN)
 196         u16 reserved0;
 197         u8 op_code;
 198         u8 flags;
 199 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0)
 200 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0
 201 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4)
 202 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4
 203 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7)
 204 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7
 205 #endif
 206         u32 cid;
 207         u32 reserved2[6];
 208 };
 209
 210
 211 /*
 212  * The first request to be passed in order to establish connection in option2
 213  */
 214 struct l4_kwq_connect_req1 {
 215 #if defined(__BIG_ENDIAN)
 216         u8 flags;
 217 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0)
 218 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0
 219 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4)
 220 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4
 221 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7)
 222 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7
 223         u8 op_code;
 224         u8 reserved0;
 225         u8 conn_flags;
 226 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0)
 227 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0
 228 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1)
 229 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1
 230 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2)
 231 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2
 232 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3)
 233 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3
 234 #elif defined(__LITTLE_ENDIAN)
 235         u8 conn_flags;
 236 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0)
 237 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0
 238 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1)
 239 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1
 240 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2)
 241 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2
 242 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3)
 243 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3
 244         u8 reserved0;
 245         u8 op_code;
 246         u8 flags;
 247 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0)
 248 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0
 249 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4)
 250 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4
 251 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7)
 252 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7
 253 #endif
 254         u32 cid;
 255         u32 pg_cid;
 256         u32 src_ip;
 257         u32 dst_ip;
 258 #if defined(__BIG_ENDIAN)
 259         u16 dst_port;
 260         u16 src_port;
 261 #elif defined(__LITTLE_ENDIAN)
 262         u16 src_port;
 263         u16 dst_port;
 264 #endif
 265 #if defined(__BIG_ENDIAN)
 266         u8 rsrv1[3];
 267         u8 tcp_flags;
 268 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0)
 269 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0
 270 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1)
 271 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1
 272 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2)
 273 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2
 274 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3)
 275 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3
 276 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4)
 277 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4
 278 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5)
 279 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5
 280 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6)
 281 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6
 282 #elif defined(__LITTLE_ENDIAN)
 283         u8 tcp_flags;
 284 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0)
 285 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0
 286 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1)
 287 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1
 288 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2)
 289 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2
 290 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3)
 291 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3
 292 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4)
 293 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4
 294 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5)
 295 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5
 296 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6)
 297 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6
 298         u8 rsrv1[3];
 299 #endif
 300         u32 rsrv2;
 301 };
 302
 303
 304 /*
 305  * The second ( optional )request to be passed in order to establish
 306  * connection in option2 - for IPv6 only
 307  */
 308 struct l4_kwq_connect_req2 {
 309 #if defined(__BIG_ENDIAN)
 310         u8 flags;
 311 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0)
 312 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0
 313 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4)
 314 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4
 315 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7)
 316 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7
 317         u8 op_code;
 318         u8 reserved0;
 319         u8 rsrv;
 320 #elif defined(__LITTLE_ENDIAN)
 321         u8 rsrv;
 322         u8 reserved0;
 323         u8 op_code;
 324         u8 flags;
 325 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0)
 326 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0
 327 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4)
 328 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4
 329 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7)
 330 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7
 331 #endif
 332         u32 reserved2;
 333         u32 src_ip_v6_2;
 334         u32 src_ip_v6_3;
 335         u32 src_ip_v6_4;
 336         u32 dst_ip_v6_2;
 337         u32 dst_ip_v6_3;
 338         u32 dst_ip_v6_4;
 339 };
 340
 341
 342 /*
 343  * The third ( and last )request to be passed in order to establish
 344  * connection in option2
 345  */
 346 struct l4_kwq_connect_req3 {
 347 #if defined(__BIG_ENDIAN)
 348         u8 flags;
 349 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0)
 350 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0
 351 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4)
 352 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4
 353 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7)
 354 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7
 355         u8 op_code;
 356         u16 reserved0;
 357 #elif defined(__LITTLE_ENDIAN)
 358         u16 reserved0;
 359         u8 op_code;
 360         u8 flags;
 361 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0)
 362 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0
 363 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4)
 364 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4
 365 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7)
 366 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7
 367 #endif
 368         u32 ka_timeout;
 369         u32 ka_interval ;
 370 #if defined(__BIG_ENDIAN)
 371         u8 snd_seq_scale;
 372         u8 ttl;
 373         u8 tos;
 374         u8 ka_max_probe_count;
 375 #elif defined(__LITTLE_ENDIAN)
 376         u8 ka_max_probe_count;
 377         u8 tos;
 378         u8 ttl;
 379         u8 snd_seq_scale;
 380 #endif
 381 #if defined(__BIG_ENDIAN)
 382         u16 pmtu;
 383         u16 mss;
 384 #elif defined(__LITTLE_ENDIAN)
 385         u16 mss;
 386         u16 pmtu;
 387 #endif
 388         u32 rcv_buf;
 389         u32 snd_buf;
 390         u32 seed;
 391 };
 392
 393
 394 /*
 395  * a KWQE request to offload a PG connection
 396  */
 397 struct l4_kwq_offload_pg {
 398 #if defined(__BIG_ENDIAN)
 399         u8 flags;
 400 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0)
 401 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0
 402 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4)
 403 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4
 404 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7)
 405 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7
 406         u8 op_code;
 407         u16 reserved0;
 408 #elif defined(__LITTLE_ENDIAN)
 409         u16 reserved0;
 410         u8 op_code;
 411         u8 flags;
 412 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0)
 413 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0
 414 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4)
 415 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4
 416 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7)
 417 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7
 418 #endif
 419 #if defined(__BIG_ENDIAN)
 420         u8 l2hdr_nbytes;
 421         u8 pg_flags;
 422 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0)
 423 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0
 424 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1)
 425 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1
 426 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2)
 427 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2
 428         u8 da0;
 429         u8 da1;
 430 #elif defined(__LITTLE_ENDIAN)
 431         u8 da1;
 432         u8 da0;
 433         u8 pg_flags;
 434 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0)
 435 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0
 436 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1)
 437 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1
 438 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2)
 439 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2
 440         u8 l2hdr_nbytes;
 441 #endif
 442 #if defined(__BIG_ENDIAN)
 443         u8 da2;
 444         u8 da3;
 445         u8 da4;
 446         u8 da5;
 447 #elif defined(__LITTLE_ENDIAN)
 448         u8 da5;
 449         u8 da4;
 450         u8 da3;
 451         u8 da2;
 452 #endif
 453 #if defined(__BIG_ENDIAN)
 454         u8 sa0;
 455         u8 sa1;
 456         u8 sa2;
 457         u8 sa3;
 458 #elif defined(__LITTLE_ENDIAN)
 459         u8 sa3;
 460         u8 sa2;
 461         u8 sa1;
 462         u8 sa0;
 463 #endif
 464 #if defined(__BIG_ENDIAN)
 465         u8 sa4;
 466         u8 sa5;
 467         u16 etype;
 468 #elif defined(__LITTLE_ENDIAN)
 469         u16 etype;
 470         u8 sa5;
 471         u8 sa4;
 472 #endif
 473 #if defined(__BIG_ENDIAN)
 474         u16 vlan_tag;
 475         u16 ipid_start;
 476 #elif defined(__LITTLE_ENDIAN)
 477         u16 ipid_start;
 478         u16 vlan_tag;
 479 #endif
 480 #if defined(__BIG_ENDIAN)
 481         u16 ipid_count;
 482         u16 reserved3;
 483 #elif defined(__LITTLE_ENDIAN)
 484         u16 reserved3;
 485         u16 ipid_count;
 486 #endif
 487         u32 host_opaque;
 488 };
 489
 490
 491 /*
 492  * Abortively close the connection request
 493  */
 494 struct l4_kwq_reset_req {
 495 #if defined(__BIG_ENDIAN)
 496         u8 flags;
 497 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0)
 498 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0
 499 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4)
 500 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4
 501 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7)
 502 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7
 503         u8 op_code;
 504         u16 reserved0;
 505 #elif defined(__LITTLE_ENDIAN)
 506         u16 reserved0;
 507         u8 op_code;
 508         u8 flags;
 509 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0)
 510 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0
 511 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4)
 512 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4
 513 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7)
 514 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7
 515 #endif
 516         u32 cid;
 517         u32 reserved2[6];
 518 };
 519
 520
 521 /*
 522  * a KWQE request to update a PG connection
 523  */
 524 struct l4_kwq_update_pg {
 525 #if defined(__BIG_ENDIAN)
 526         u8 flags;
 527 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0)
 528 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0
 529 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4)
 530 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4
 531 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7)
 532 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7
 533         u8 opcode;
 534         u16 oper16;
 535 #elif defined(__LITTLE_ENDIAN)
 536         u16 oper16;
 537         u8 opcode;
 538         u8 flags;
 539 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0)
 540 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0
 541 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4)
 542 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4
 543 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7)
 544 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7
 545 #endif
 546         u32 pg_cid;
 547         u32 pg_host_opaque;
 548 #if defined(__BIG_ENDIAN)
 549         u8 pg_valids;
 550 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0)
 551 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0
 552 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1)
 553 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1
 554 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2)
 555 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2
 556         u8 pg_unused_a;
 557         u16 pg_ipid_count;
 558 #elif defined(__LITTLE_ENDIAN)
 559         u16 pg_ipid_count;
 560         u8 pg_unused_a;
 561         u8 pg_valids;
 562 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0)
 563 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0
 564 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1)
 565 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1
 566 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2)
 567 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2
 568 #endif
 569 #if defined(__BIG_ENDIAN)
 570         u16 reserverd3;
 571         u8 da0;
 572         u8 da1;
 573 #elif defined(__LITTLE_ENDIAN)
 574         u8 da1;
 575         u8 da0;
 576         u16 reserverd3;
 577 #endif
 578 #if defined(__BIG_ENDIAN)
 579         u8 da2;
 580         u8 da3;
 581         u8 da4;
 582         u8 da5;
 583 #elif defined(__LITTLE_ENDIAN)
 584         u8 da5;
 585         u8 da4;
 586         u8 da3;
 587         u8 da2;
 588 #endif
 589         u32 reserved4;
 590         u32 reserved5;
 591 };
 592
 593
 594 /*
 595  * a KWQE request to upload a PG or L4 context
 596  */
 597 struct l4_kwq_upload {
 598 #if defined(__BIG_ENDIAN)
 599         u8 flags;
 600 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0)
 601 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0
 602 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4)
 603 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4
 604 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7)
 605 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7
 606         u8 opcode;
 607         u16 oper16;
 608 #elif defined(__LITTLE_ENDIAN)
 609         u16 oper16;
 610         u8 opcode;
 611         u8 flags;
 612 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0)
 613 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0
 614 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4)
 615 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4
 616 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7)
 617 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7
 618 #endif
 619         u32 cid;
 620         u32 reserved2[6];
 621 };
 622
 623 /*
 624  * bnx2x structures
 625  */
 626
 627 /*
 628  * The iscsi aggregative context of Cstorm
 629  */
 630 struct cstorm_iscsi_ag_context {
 631         u32 agg_vars1;
 632 #define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0)
 633 #define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0
 634 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8)
 635 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8
 636 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9)
 637 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9
 638 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10)
 639 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10
 640 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11)
 641 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11
 642 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12)
 643 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12
 644 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13)
 645 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13
 646 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14)
 647 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 14
 648 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16)
 649 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16
 650 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18)
 651 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18
 652 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19)
 653 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 19
 654 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20)
 655 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN_SHIFT 20
 656 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21)
 657 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 21
 658 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22)
 659 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 22
 660 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23)
 661 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23
 662 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26)
 663 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26
 664 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28)
 665 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28
 666 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30)
 667 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30
 668 #if defined(__BIG_ENDIAN)
 669         u8 __aux1_th;
 670         u8 __aux1_val;
 671         u16 __agg_vars2;
 672 #elif defined(__LITTLE_ENDIAN)
 673         u16 __agg_vars2;
 674         u8 __aux1_val;
 675         u8 __aux1_th;
 676 #endif
 677         u32 rel_seq;
 678         u32 rel_seq_th;
 679 #if defined(__BIG_ENDIAN)
 680         u16 hq_cons;
 681         u16 hq_prod;
 682 #elif defined(__LITTLE_ENDIAN)
 683         u16 hq_prod;
 684         u16 hq_cons;
 685 #endif
 686 #if defined(__BIG_ENDIAN)
 687         u8 __reserved62;
 688         u8 __reserved61;
 689         u8 __reserved60;
 690         u8 __reserved59;
 691 #elif defined(__LITTLE_ENDIAN)
 692         u8 __reserved59;
 693         u8 __reserved60;
 694         u8 __reserved61;
 695         u8 __reserved62;
 696 #endif
 697 #if defined(__BIG_ENDIAN)
 698         u16 __reserved64;
 699         u16 cq_u_prod;
 700 #elif defined(__LITTLE_ENDIAN)
 701         u16 cq_u_prod;
 702         u16 __reserved64;
 703 #endif
 704         u32 __cq_u_prod1;
 705 #if defined(__BIG_ENDIAN)
 706         u16 __agg_vars3;
 707         u16 cq_u_pend;
 708 #elif defined(__LITTLE_ENDIAN)
 709         u16 cq_u_pend;
 710         u16 __agg_vars3;
 711 #endif
 712 #if defined(__BIG_ENDIAN)
 713         u16 __aux2_th;
 714         u16 aux2_val;
 715 #elif defined(__LITTLE_ENDIAN)
 716         u16 aux2_val;
 717         u16 __aux2_th;
 718 #endif
 719 };
 720
 721 /*
 722  * The fcoe extra aggregative context section of Tstorm
 723  */
 724 struct tstorm_fcoe_extra_ag_context_section {
 725         u32 __agg_val1;
 726 #if defined(__BIG_ENDIAN)
 727         u8 __tcp_agg_vars2;
 728         u8 __agg_val3;
 729         u16 __agg_val2;
 730 #elif defined(__LITTLE_ENDIAN)
 731         u16 __agg_val2;
 732         u8 __agg_val3;
 733         u8 __tcp_agg_vars2;
 734 #endif
 735 #if defined(__BIG_ENDIAN)
 736         u16 __agg_val5;
 737         u8 __agg_val6;
 738         u8 __tcp_agg_vars3;
 739 #elif defined(__LITTLE_ENDIAN)
 740         u8 __tcp_agg_vars3;
 741         u8 __agg_val6;
 742         u16 __agg_val5;
 743 #endif
 744         u32 __lcq_prod;
 745         u32 rtt_seq;
 746         u32 rtt_time;
 747         u32 __reserved66;
 748         u32 wnd_right_edge;
 749         u32 tcp_agg_vars1;
 750 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
 751 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
 752 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
 753 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
 754 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
 755 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
 756 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
 757 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
 758 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
 759 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
 760 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
 761 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
 762 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
 763 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
 764 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9)
 765 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9
 766 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
 767 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
 768 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
 769 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
 770 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
 771 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
 772 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
 773 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
 774 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
 775 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
 776 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
 777 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
 778 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
 779 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
 780 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
 781 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
 782 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
 783 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
 784 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
 785 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
 786 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
 787 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
 788 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
 789 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
 790 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
 791 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
 792         u32 snd_max;
 793         u32 __lcq_cons;
 794         u32 __reserved2;
 795 };
 796
 797 /*
 798  * The fcoe aggregative context of Tstorm
 799  */
 800 struct tstorm_fcoe_ag_context {
 801 #if defined(__BIG_ENDIAN)
 802         u16 ulp_credit;
 803         u8 agg_vars1;
 804 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
 805 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
 806 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
 807 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
 808 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
 809 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
 810 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
 811 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
 812 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
 813 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
 814 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
 815 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
 816 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
 817 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
 818         u8 state;
 819 #elif defined(__LITTLE_ENDIAN)
 820         u8 state;
 821         u8 agg_vars1;
 822 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
 823 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
 824 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
 825 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
 826 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
 827 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
 828 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
 829 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
 830 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
 831 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
 832 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
 833 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
 834 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
 835 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
 836         u16 ulp_credit;
 837 #endif
 838 #if defined(__BIG_ENDIAN)
 839         u16 __agg_val4;
 840         u16 agg_vars2;
 841 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
 842 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
 843 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
 844 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
 845 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
 846 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
 847 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
 848 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
 849 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
 850 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
 851 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
 852 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
 853 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
 854 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
 855 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
 856 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
 857 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
 858 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
 859 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
 860 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
 861 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
 862 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
 863 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
 864 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
 865 #elif defined(__LITTLE_ENDIAN)
 866         u16 agg_vars2;
 867 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
 868 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
 869 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
 870 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
 871 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
 872 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
 873 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
 874 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
 875 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
 876 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
 877 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
 878 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
 879 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
 880 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
 881 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
 882 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
 883 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
 884 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
 885 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
 886 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
 887 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
 888 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
 889 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
 890 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
 891         u16 __agg_val4;
 892 #endif
 893         struct tstorm_fcoe_extra_ag_context_section __extra_section;
 894 };
 895
 896
 897
 898 /*
 899  * The tcp aggregative context section of Tstorm
 900  */
 901 struct tstorm_tcp_tcp_ag_context_section {
 902         u32 __agg_val1;
 903 #if defined(__BIG_ENDIAN)
 904         u8 __tcp_agg_vars2;
 905         u8 __agg_val3;
 906         u16 __agg_val2;
 907 #elif defined(__LITTLE_ENDIAN)
 908         u16 __agg_val2;
 909         u8 __agg_val3;
 910         u8 __tcp_agg_vars2;
 911 #endif
 912 #if defined(__BIG_ENDIAN)
 913         u16 __agg_val5;
 914         u8 __agg_val6;
 915         u8 __tcp_agg_vars3;
 916 #elif defined(__LITTLE_ENDIAN)
 917         u8 __tcp_agg_vars3;
 918         u8 __agg_val6;
 919         u16 __agg_val5;
 920 #endif
 921         u32 snd_nxt;
 922         u32 rtt_seq;
 923         u32 rtt_time;
 924         u32 __reserved66;
 925         u32 wnd_right_edge;
 926         u32 tcp_agg_vars1;
 927 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
 928 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
 929 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
 930 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
 931 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
 932 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
 933 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
 934 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
 935 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
 936 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
 937 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
 938 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
 939 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
 940 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
 941 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9)
 942 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
 943 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
 944 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
 945 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
 946 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
 947 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
 948 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
 949 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
 950 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
 951 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
 952 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
 953 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
 954 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
 955 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
 956 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
 957 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
 958 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
 959 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
 960 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
 961 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
 962 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
 963 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
 964 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
 965 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
 966 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
 967 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
 968 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
 969         u32 snd_max;
 970         u32 snd_una;
 971         u32 __reserved2;
 972 };
 973
 974 /*
 975  * The iscsi aggregative context of Tstorm
 976  */
 977 struct tstorm_iscsi_ag_context {
 978 #if defined(__BIG_ENDIAN)
 979         u16 ulp_credit;
 980         u8 agg_vars1;
 981 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
 982 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
 983 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
 984 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
 985 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
 986 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
 987 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
 988 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
 989 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
 990 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
 991 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6)
 992 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
 993 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7)
 994 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
 995         u8 state;
 996 #elif defined(__LITTLE_ENDIAN)
 997         u8 state;
 998         u8 agg_vars1;
 999 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1000 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1001 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1002 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1003 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1004 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1005 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1006 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1007 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4)
1008 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
1009 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6)
1010 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
1011 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7)
1012 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
1013         u16 ulp_credit;
1014 #endif
1015 #if defined(__BIG_ENDIAN)
1016         u16 __agg_val4;
1017         u16 agg_vars2;
1018 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0)
1019 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
1020 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1)
1021 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
1022 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2)
1023 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
1024 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4)
1025 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
1026 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6)
1027 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
1028 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8)
1029 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
1030 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10)
1031 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
1032 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
1033 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
1034 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12)
1035 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
1036 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13)
1037 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
1038 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
1039 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
1040 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
1041 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
1042 #elif defined(__LITTLE_ENDIAN)
1043         u16 agg_vars2;
1044 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0)
1045 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
1046 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1)
1047 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
1048 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2)
1049 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
1050 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4)
1051 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
1052 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6)
1053 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
1054 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8)
1055 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
1056 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10)
1057 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
1058 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11)
1059 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
1060 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12)
1061 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
1062 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13)
1063 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
1064 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
1065 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
1066 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
1067 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
1068         u16 __agg_val4;
1069 #endif
1070         struct tstorm_tcp_tcp_ag_context_section tcp;
1071 };
1072
1073
1074
1075 /*
1076  * The fcoe aggregative context of Ustorm
1077  */
1078 struct ustorm_fcoe_ag_context {
1079 #if defined(__BIG_ENDIAN)
1080         u8 __aux_counter_flags;
1081         u8 agg_vars2;
1082 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
1083 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
1084 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
1085 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
1086 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1087 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1088 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1089 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1090         u8 agg_vars1;
1091 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1092 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1093 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1094 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1095 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1096 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1097 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1098 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1099 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
1100 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
1101 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1102 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1103         u8 state;
1104 #elif defined(__LITTLE_ENDIAN)
1105         u8 state;
1106         u8 agg_vars1;
1107 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1108 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1109 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1110 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1111 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1112 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1113 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1114 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1115 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
1116 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
1117 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1118 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1119         u8 agg_vars2;
1120 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
1121 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
1122 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
1123 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
1124 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1125 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1126 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1127 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1128         u8 __aux_counter_flags;
1129 #endif
1130 #if defined(__BIG_ENDIAN)
1131         u8 cdu_usage;
1132         u8 agg_misc2;
1133         u16 pbf_tx_seq_ack;
1134 #elif defined(__LITTLE_ENDIAN)
1135         u16 pbf_tx_seq_ack;
1136         u8 agg_misc2;
1137         u8 cdu_usage;
1138 #endif
1139         u32 agg_misc4;
1140 #if defined(__BIG_ENDIAN)
1141         u8 agg_val3_th;
1142         u8 agg_val3;
1143         u16 agg_misc3;
1144 #elif defined(__LITTLE_ENDIAN)
1145         u16 agg_misc3;
1146         u8 agg_val3;
1147         u8 agg_val3_th;
1148 #endif
1149         u32 expired_task_id;
1150         u32 agg_misc4_th;
1151 #if defined(__BIG_ENDIAN)
1152         u16 cq_prod;
1153         u16 cq_cons;
1154 #elif defined(__LITTLE_ENDIAN)
1155         u16 cq_cons;
1156         u16 cq_prod;
1157 #endif
1158 #if defined(__BIG_ENDIAN)
1159         u16 __reserved2;
1160         u8 decision_rules;
1161 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
1162 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
1163 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1164 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1165 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
1166 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
1167 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
1168 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
1169         u8 decision_rule_enable_bits;
1170 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
1171 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
1172 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1173 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1174 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
1175 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
1176 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1177 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1178 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
1179 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
1180 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
1181 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
1182 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1183 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1184 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1185 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1186 #elif defined(__LITTLE_ENDIAN)
1187         u8 decision_rule_enable_bits;
1188 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
1189 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
1190 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1191 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1192 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
1193 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
1194 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1195 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1196 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
1197 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
1198 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
1199 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
1200 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1201 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1202 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1203 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1204         u8 decision_rules;
1205 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
1206 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
1207 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1208 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1209 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
1210 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
1211 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
1212 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
1213         u16 __reserved2;
1214 #endif
1215 };
1216
1217
1218 /*
1219  * The iscsi aggregative context of Ustorm
1220  */
1221 struct ustorm_iscsi_ag_context {
1222 #if defined(__BIG_ENDIAN)
1223         u8 __aux_counter_flags;
1224         u8 agg_vars2;
1225 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0)
1226 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
1227 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2)
1228 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
1229 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1230 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1231 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1232 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1233         u8 agg_vars1;
1234 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1235 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1236 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1237 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1238 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1239 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1240 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1241 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1242 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4)
1243 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
1244 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1245 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1246         u8 state;
1247 #elif defined(__LITTLE_ENDIAN)
1248         u8 state;
1249         u8 agg_vars1;
1250 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1251 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1252 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1253 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1254 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1255 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1256 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1257 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1258 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4)
1259 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
1260 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1261 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1262         u8 agg_vars2;
1263 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0)
1264 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
1265 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2)
1266 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
1267 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1268 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1269 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1270 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1271         u8 __aux_counter_flags;
1272 #endif
1273 #if defined(__BIG_ENDIAN)
1274         u8 cdu_usage;
1275         u8 agg_misc2;
1276         u16 __cq_local_comp_itt_val;
1277 #elif defined(__LITTLE_ENDIAN)
1278         u16 __cq_local_comp_itt_val;
1279         u8 agg_misc2;
1280         u8 cdu_usage;
1281 #endif
1282         u32 agg_misc4;
1283 #if defined(__BIG_ENDIAN)
1284         u8 agg_val3_th;
1285         u8 agg_val3;
1286         u16 agg_misc3;
1287 #elif defined(__LITTLE_ENDIAN)
1288         u16 agg_misc3;
1289         u8 agg_val3;
1290         u8 agg_val3_th;
1291 #endif
1292         u32 agg_val1;
1293         u32 agg_misc4_th;
1294 #if defined(__BIG_ENDIAN)
1295         u16 agg_val2_th;
1296         u16 agg_val2;
1297 #elif defined(__LITTLE_ENDIAN)
1298         u16 agg_val2;
1299         u16 agg_val2_th;
1300 #endif
1301 #if defined(__BIG_ENDIAN)
1302         u16 __reserved2;
1303         u8 decision_rules;
1304 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
1305 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
1306 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1307 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1308 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
1309 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
1310 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7)
1311 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
1312         u8 decision_rule_enable_bits;
1313 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0)
1314 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
1315 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1316 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1317 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2)
1318 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
1319 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1320 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1321 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4)
1322 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
1323 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5)
1324 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
1325 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1326 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1327 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1328 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1329 #elif defined(__LITTLE_ENDIAN)
1330         u8 decision_rule_enable_bits;
1331 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0)
1332 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
1333 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1334 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1335 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2)
1336 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
1337 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1338 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1339 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4)
1340 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
1341 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5)
1342 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
1343 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1344 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1345 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1346 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1347         u8 decision_rules;
1348 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0)
1349 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
1350 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1351 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1352 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6)
1353 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
1354 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7)
1355 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
1356         u16 __reserved2;
1357 #endif
1358 };
1359
1360
1361 /*
1362  * The fcoe aggregative context section of Xstorm
1363  */
1364 struct xstorm_fcoe_extra_ag_context_section {
1365 #if defined(__BIG_ENDIAN)
1366         u8 tcp_agg_vars1;
1367 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
1368 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
1369 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1370 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1371 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1372 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1373 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
1374 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
1375 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
1376 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
1377         u8 __reserved_da_cnt;
1378         u16 __mtu;
1379 #elif defined(__LITTLE_ENDIAN)
1380         u16 __mtu;
1381         u8 __reserved_da_cnt;
1382         u8 tcp_agg_vars1;
1383 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
1384 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
1385 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1386 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1387 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1388 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1389 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
1390 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
1391 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
1392 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
1393 #endif
1394         u32 snd_nxt;
1395         u32 tx_wnd;
1396         u32 __reserved55;
1397         u32 local_adv_wnd;
1398 #if defined(__BIG_ENDIAN)
1399         u8 __agg_val8_th;
1400         u8 __tx_dest;
1401         u16 tcp_agg_vars2;
1402 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
1403 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
1404 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
1405 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
1406 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
1407 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
1408 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1409 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1410 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1411 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1412 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
1413 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
1414 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
1415 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
1416 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1417 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1418 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
1419 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
1420 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1421 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1422 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1423 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1424 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1425 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1426 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1427 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1428 #elif defined(__LITTLE_ENDIAN)
1429         u16 tcp_agg_vars2;
1430 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
1431 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
1432 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
1433 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
1434 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
1435 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
1436 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1437 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1438 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1439 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1440 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
1441 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
1442 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
1443 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
1444 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1445 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1446 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
1447 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
1448 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1449 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1450 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1451 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1452 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1453 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1454 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1455 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1456         u8 __tx_dest;
1457         u8 __agg_val8_th;
1458 #endif
1459         u32 __sq_base_addr_lo;
1460         u32 __sq_base_addr_hi;
1461         u32 __xfrq_base_addr_lo;
1462         u32 __xfrq_base_addr_hi;
1463 #if defined(__BIG_ENDIAN)
1464         u16 __xfrq_cons;
1465         u16 __xfrq_prod;
1466 #elif defined(__LITTLE_ENDIAN)
1467         u16 __xfrq_prod;
1468         u16 __xfrq_cons;
1469 #endif
1470 #if defined(__BIG_ENDIAN)
1471         u8 __tcp_agg_vars5;
1472         u8 __tcp_agg_vars4;
1473         u8 __tcp_agg_vars3;
1474         u8 __reserved_force_pure_ack_cnt;
1475 #elif defined(__LITTLE_ENDIAN)
1476         u8 __reserved_force_pure_ack_cnt;
1477         u8 __tcp_agg_vars3;
1478         u8 __tcp_agg_vars4;
1479         u8 __tcp_agg_vars5;
1480 #endif
1481         u32 __tcp_agg_vars6;
1482 #if defined(__BIG_ENDIAN)
1483         u16 __agg_misc6;
1484         u16 __tcp_agg_vars7;
1485 #elif defined(__LITTLE_ENDIAN)
1486         u16 __tcp_agg_vars7;
1487         u16 __agg_misc6;
1488 #endif
1489         u32 __agg_val10;
1490         u32 __agg_val10_th;
1491 #if defined(__BIG_ENDIAN)
1492         u16 __reserved3;
1493         u8 __reserved2;
1494         u8 __da_only_cnt;
1495 #elif defined(__LITTLE_ENDIAN)
1496         u8 __da_only_cnt;
1497         u8 __reserved2;
1498         u16 __reserved3;
1499 #endif
1500 };
1501
1502 /*
1503  * The fcoe aggregative context of Xstorm
1504  */
1505 struct xstorm_fcoe_ag_context {
1506 #if defined(__BIG_ENDIAN)
1507         u16 agg_val1;
1508         u8 agg_vars1;
1509 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1510 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1511 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1512 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1513 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
1514 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
1515 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
1516 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
1517 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1518 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1519 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
1520 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
1521 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1522 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1523 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
1524 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
1525         u8 __state;
1526 #elif defined(__LITTLE_ENDIAN)
1527         u8 __state;
1528         u8 agg_vars1;
1529 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1530 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1531 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1532 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1533 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
1534 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
1535 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
1536 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
1537 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1538 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1539 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
1540 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
1541 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1542 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1543 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
1544 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
1545         u16 agg_val1;
1546 #endif
1547 #if defined(__BIG_ENDIAN)
1548         u8 cdu_reserved;
1549         u8 __agg_vars4;
1550         u8 agg_vars3;
1551 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1552 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1553 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
1554 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
1555         u8 agg_vars2;
1556 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
1557 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
1558 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1559 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1560 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1561 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1562 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1563 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1564 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1565 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1566 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1567 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1568 #elif defined(__LITTLE_ENDIAN)
1569         u8 agg_vars2;
1570 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
1571 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
1572 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1573 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1574 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1575 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1576 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1577 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1578 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1579 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1580 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1581 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1582         u8 agg_vars3;
1583 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1584 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1585 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
1586 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
1587         u8 __agg_vars4;
1588         u8 cdu_reserved;
1589 #endif
1590         u32 more_to_send;
1591 #if defined(__BIG_ENDIAN)
1592         u16 agg_vars5;
1593 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
1594 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
1595 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
1596 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
1597 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
1598 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
1599 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
1600 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
1601         u16 sq_cons;
1602 #elif defined(__LITTLE_ENDIAN)
1603         u16 sq_cons;
1604         u16 agg_vars5;
1605 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
1606 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
1607 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
1608 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
1609 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
1610 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
1611 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
1612 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
1613 #endif
1614         struct xstorm_fcoe_extra_ag_context_section __extra_section;
1615 #if defined(__BIG_ENDIAN)
1616         u16 agg_vars7;
1617 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
1618 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
1619 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
1620 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
1621 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
1622 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
1623 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
1624 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
1625 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
1626 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
1627 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
1628 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
1629 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
1630 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
1631 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
1632 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
1633 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
1634 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
1635 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
1636 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
1637 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
1638 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
1639         u8 agg_val3_th;
1640         u8 agg_vars6;
1641 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
1642 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
1643 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
1644 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
1645 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
1646 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
1647 #elif defined(__LITTLE_ENDIAN)
1648         u8 agg_vars6;
1649 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
1650 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
1651 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
1652 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
1653 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
1654 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
1655         u8 agg_val3_th;
1656         u16 agg_vars7;
1657 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
1658 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
1659 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
1660 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
1661 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
1662 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
1663 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
1664 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
1665 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
1666 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
1667 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
1668 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
1669 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
1670 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
1671 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
1672 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
1673 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
1674 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
1675 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
1676 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
1677 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
1678 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
1679 #endif
1680 #if defined(__BIG_ENDIAN)
1681         u16 __agg_val11_th;
1682         u16 __agg_val11;
1683 #elif defined(__LITTLE_ENDIAN)
1684         u16 __agg_val11;
1685         u16 __agg_val11_th;
1686 #endif
1687 #if defined(__BIG_ENDIAN)
1688         u8 __reserved1;
1689         u8 __agg_val6_th;
1690         u16 __agg_val9;
1691 #elif defined(__LITTLE_ENDIAN)
1692         u16 __agg_val9;
1693         u8 __agg_val6_th;
1694         u8 __reserved1;
1695 #endif
1696 #if defined(__BIG_ENDIAN)
1697         u16 confq_cons;
1698         u16 confq_prod;
1699 #elif defined(__LITTLE_ENDIAN)
1700         u16 confq_prod;
1701         u16 confq_cons;
1702 #endif
1703         u32 agg_vars8;
1704 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
1705 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0
1706 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
1707 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24
1708 #if defined(__BIG_ENDIAN)
1709         u16 agg_misc0;
1710         u16 sq_prod;
1711 #elif defined(__LITTLE_ENDIAN)
1712         u16 sq_prod;
1713         u16 agg_misc0;
1714 #endif
1715 #if defined(__BIG_ENDIAN)
1716         u8 agg_val3;
1717         u8 agg_val6;
1718         u8 agg_val5_th;
1719         u8 agg_val5;
1720 #elif defined(__LITTLE_ENDIAN)
1721         u8 agg_val5;
1722         u8 agg_val5_th;
1723         u8 agg_val6;
1724         u8 agg_val3;
1725 #endif
1726 #if defined(__BIG_ENDIAN)
1727         u16 __agg_misc1;
1728         u16 agg_limit1;
1729 #elif defined(__LITTLE_ENDIAN)
1730         u16 agg_limit1;
1731         u16 __agg_misc1;
1732 #endif
1733         u32 completion_seq;
1734         u32 confq_pbl_base_lo;
1735         u32 confq_pbl_base_hi;
1736 };
1737
1738
1739
1740 /*
1741  * The tcp aggregative context section of Xstorm
1742  */
1743 struct xstorm_tcp_tcp_ag_context_section {
1744 #if defined(__BIG_ENDIAN)
1745         u8 tcp_agg_vars1;
1746 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
1747 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
1748 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1749 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1750 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1751 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1752 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
1753 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
1754 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
1755 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
1756         u8 __da_cnt;
1757         u16 mss;
1758 #elif defined(__LITTLE_ENDIAN)
1759         u16 mss;
1760         u8 __da_cnt;
1761         u8 tcp_agg_vars1;
1762 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0)
1763 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
1764 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1765 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1766 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4)
1767 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
1768 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6)
1769 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
1770 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7)
1771 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
1772 #endif
1773         u32 snd_nxt;
1774         u32 tx_wnd;
1775         u32 snd_una;
1776         u32 local_adv_wnd;
1777 #if defined(__BIG_ENDIAN)
1778         u8 __agg_val8_th;
1779         u8 __tx_dest;
1780         u16 tcp_agg_vars2;
1781 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
1782 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
1783 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
1784 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
1785 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
1786 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
1787 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1788 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1789 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1790 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1791 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
1792 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
1793 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
1794 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
1795 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1796 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1797 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
1798 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
1799 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1800 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1801 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1802 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1803 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1804 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1805 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1806 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1807 #elif defined(__LITTLE_ENDIAN)
1808         u16 tcp_agg_vars2;
1809 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0)
1810 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
1811 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1)
1812 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
1813 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2)
1814 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
1815 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1816 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1817 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1818 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1819 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5)
1820 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
1821 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6)
1822 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
1823 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7)
1824 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
1825 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8)
1826 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
1827 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1828 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1829 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1830 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1831 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1832 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1833 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14)
1834 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
1835         u8 __tx_dest;
1836         u8 __agg_val8_th;
1837 #endif
1838         u32 ack_to_far_end;
1839         u32 rto_timer;
1840         u32 ka_timer;
1841         u32 ts_to_echo;
1842 #if defined(__BIG_ENDIAN)
1843         u16 __agg_val7_th;
1844         u16 __agg_val7;
1845 #elif defined(__LITTLE_ENDIAN)
1846         u16 __agg_val7;
1847         u16 __agg_val7_th;
1848 #endif
1849 #if defined(__BIG_ENDIAN)
1850         u8 __tcp_agg_vars5;
1851         u8 __tcp_agg_vars4;
1852         u8 __tcp_agg_vars3;
1853         u8 __force_pure_ack_cnt;
1854 #elif defined(__LITTLE_ENDIAN)
1855         u8 __force_pure_ack_cnt;
1856         u8 __tcp_agg_vars3;
1857         u8 __tcp_agg_vars4;
1858         u8 __tcp_agg_vars5;
1859 #endif
1860         u32 tcp_agg_vars6;
1861 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0)
1862 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
1863 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1)
1864 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1
1865 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2)
1866 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2
1867 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3)
1868 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3
1869 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4)
1870 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4
1871 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5)
1872 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5
1873 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6)
1874 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6
1875 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8)
1876 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8
1877 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10)
1878 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10
1879 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12)
1880 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12
1881 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14)
1882 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14
1883 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16)
1884 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16
1885 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18)
1886 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18
1887 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20)
1888 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20
1889 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22)
1890 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22
1891 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24)
1892 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24
1893 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26)
1894 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26
1895 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27)
1896 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27
1897 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28)
1898 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28
1899 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29)
1900 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29
1901 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30)
1902 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30
1903 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31)
1904 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31
1905 #if defined(__BIG_ENDIAN)
1906         u16 __agg_misc6;
1907         u16 __tcp_agg_vars7;
1908 #elif defined(__LITTLE_ENDIAN)
1909         u16 __tcp_agg_vars7;
1910         u16 __agg_misc6;
1911 #endif
1912         u32 __agg_val10;
1913         u32 __agg_val10_th;
1914 #if defined(__BIG_ENDIAN)
1915         u16 __reserved3;
1916         u8 __reserved2;
1917         u8 __da_only_cnt;
1918 #elif defined(__LITTLE_ENDIAN)
1919         u8 __da_only_cnt;
1920         u8 __reserved2;
1921         u16 __reserved3;
1922 #endif
1923 };
1924
1925 /*
1926  * The iscsi aggregative context of Xstorm
1927  */
1928 struct xstorm_iscsi_ag_context {
1929 #if defined(__BIG_ENDIAN)
1930         u16 agg_val1;
1931         u8 agg_vars1;
1932 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1933 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1934 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1935 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1936 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1937 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1938 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1939 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1940 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1941 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1942 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5)
1943 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
1944 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1945 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1946 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
1947 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
1948         u8 state;
1949 #elif defined(__LITTLE_ENDIAN)
1950         u8 state;
1951         u8 agg_vars1;
1952 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1953 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1954 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1955 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1956 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1957 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1958 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1959 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1960 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1961 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1962 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5)
1963 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
1964 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1965 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1966 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
1967 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
1968         u16 agg_val1;
1969 #endif
1970 #if defined(__BIG_ENDIAN)
1971         u8 cdu_reserved;
1972         u8 __agg_vars4;
1973         u8 agg_vars3;
1974 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1975 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1976 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
1977 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
1978         u8 agg_vars2;
1979 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0)
1980 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
1981 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1982 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1983 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1984 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1985 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1986 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1987 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1988 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1989 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1990 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1991 #elif defined(__LITTLE_ENDIAN)
1992         u8 agg_vars2;
1993 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0)
1994 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
1995 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1996 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1997 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1998 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1999 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4)
2000 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
2001 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
2002 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
2003 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7)
2004 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
2005         u8 agg_vars3;
2006 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
2007 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
2008 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
2009 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
2010         u8 __agg_vars4;
2011         u8 cdu_reserved;
2012 #endif
2013         u32 more_to_send;
2014 #if defined(__BIG_ENDIAN)
2015         u16 agg_vars5;
2016 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2017 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2018 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2019 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2020 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2021 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2022 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2023 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2024         u16 sq_cons;
2025 #elif defined(__LITTLE_ENDIAN)
2026         u16 sq_cons;
2027         u16 agg_vars5;
2028 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2029 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2030 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2031 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2032 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2033 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2034 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2035 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2036 #endif
2037         struct xstorm_tcp_tcp_ag_context_section tcp;
2038 #if defined(__BIG_ENDIAN)
2039         u16 agg_vars7;
2040 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2041 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2042 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2043 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2044 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2045 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2046 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2047 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2048 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8)
2049 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
2050 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2051 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2052 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2053 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2054 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2055 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2056 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2057 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2058 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2059 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2060 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2061 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2062         u8 agg_val3_th;
2063         u8 agg_vars6;
2064 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2065 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2066 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2067 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2068 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2069 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2070 #elif defined(__LITTLE_ENDIAN)
2071         u8 agg_vars6;
2072 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2073 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2074 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2075 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2076 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2077 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2078         u8 agg_val3_th;
2079         u16 agg_vars7;
2080 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2081 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2082 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2083 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2084 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2085 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2086 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2087 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2088 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8)
2089 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
2090 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2091 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2092 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2093 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2094 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2095 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2096 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2097 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2098 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2099 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2100 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2101 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2102 #endif
2103 #if defined(__BIG_ENDIAN)
2104         u16 __agg_val11_th;
2105         u16 __gen_data;
2106 #elif defined(__LITTLE_ENDIAN)
2107         u16 __gen_data;
2108         u16 __agg_val11_th;
2109 #endif
2110 #if defined(__BIG_ENDIAN)
2111         u8 __reserved1;
2112         u8 __agg_val6_th;
2113         u16 __agg_val9;
2114 #elif defined(__LITTLE_ENDIAN)
2115         u16 __agg_val9;
2116         u8 __agg_val6_th;
2117         u8 __reserved1;
2118 #endif
2119 #if defined(__BIG_ENDIAN)
2120         u16 hq_prod;
2121         u16 hq_cons;
2122 #elif defined(__LITTLE_ENDIAN)
2123         u16 hq_cons;
2124         u16 hq_prod;
2125 #endif
2126         u32 agg_vars8;
2127 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
2128 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0
2129 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
2130 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24
2131 #if defined(__BIG_ENDIAN)
2132         u16 r2tq_prod;
2133         u16 sq_prod;
2134 #elif defined(__LITTLE_ENDIAN)
2135         u16 sq_prod;
2136         u16 r2tq_prod;
2137 #endif
2138 #if defined(__BIG_ENDIAN)
2139         u8 agg_val3;
2140         u8 agg_val6;
2141         u8 agg_val5_th;
2142         u8 agg_val5;
2143 #elif defined(__LITTLE_ENDIAN)
2144         u8 agg_val5;
2145         u8 agg_val5_th;
2146         u8 agg_val6;
2147         u8 agg_val3;
2148 #endif
2149 #if defined(__BIG_ENDIAN)
2150         u16 __agg_misc1;
2151         u16 agg_limit1;
2152 #elif defined(__LITTLE_ENDIAN)
2153         u16 agg_limit1;
2154         u16 __agg_misc1;
2155 #endif
2156         u32 hq_cons_tcp_seq;
2157         u32 exp_stat_sn;
2158         u32 rst_seq_num;
2159 };
2160
2161
2162 /*
2163  * The L5cm aggregative context of XStorm
2164  */
2165 struct xstorm_l5cm_ag_context {
2166 #if defined(__BIG_ENDIAN)
2167         u16 agg_val1;
2168         u8 agg_vars1;
2169 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
2170 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
2171 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
2172 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
2173 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
2174 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
2175 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
2176 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
2177 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
2178 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
2179 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN (0x1<<5)
2180 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN_SHIFT 5
2181 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
2182 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
2183 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
2184 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
2185         u8 state;
2186 #elif defined(__LITTLE_ENDIAN)
2187         u8 state;
2188         u8 agg_vars1;
2189 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
2190 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
2191 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
2192 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
2193 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
2194 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
2195 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
2196 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
2197 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
2198 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
2199 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN (0x1<<5)
2200 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN_SHIFT 5
2201 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
2202 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
2203 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7)
2204 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
2205         u16 agg_val1;
2206 #endif
2207 #if defined(__BIG_ENDIAN)
2208         u8 cdu_reserved;
2209         u8 __agg_vars4;
2210         u8 agg_vars3;
2211 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
2212 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
2213 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
2214 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
2215         u8 agg_vars2;
2216 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF (0x3<<0)
2217 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_SHIFT 0
2218 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
2219 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
2220 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG (0x1<<3)
2221 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG_SHIFT 3
2222 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG (0x1<<4)
2223 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG_SHIFT 4
2224 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
2225 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1_SHIFT 5
2226 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN (0x1<<7)
2227 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN_SHIFT 7
2228 #elif defined(__LITTLE_ENDIAN)
2229         u8 agg_vars2;
2230 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF (0x3<<0)
2231 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_SHIFT 0
2232 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
2233 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
2234 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG (0x1<<3)
2235 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG_SHIFT 3
2236 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG (0x1<<4)
2237 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG_SHIFT 4
2238 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
2239 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1_SHIFT 5
2240 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN (0x1<<7)
2241 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN_SHIFT 7
2242         u8 agg_vars3;
2243 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
2244 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
2245 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF (0x3<<6)
2246 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
2247         u8 __agg_vars4;
2248         u8 cdu_reserved;
2249 #endif
2250         u32 more_to_send;
2251 #if defined(__BIG_ENDIAN)
2252         u16 agg_vars5;
2253 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2254 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2255 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2256 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2257 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2258 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2259 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2260 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2261         u16 agg_val4_th;
2262 #elif defined(__LITTLE_ENDIAN)
2263         u16 agg_val4_th;
2264         u16 agg_vars5;
2265 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
2266 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5_SHIFT 0
2267 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
2268 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
2269 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
2270 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
2271 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2 (0x3<<14)
2272 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2_SHIFT 14
2273 #endif
2274         struct xstorm_tcp_tcp_ag_context_section tcp;
2275 #if defined(__BIG_ENDIAN)
2276         u16 agg_vars7;
2277 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2278 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2279 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2280 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2281 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2282 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2283 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2284 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2285 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF (0x3<<8)
2286 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF_SHIFT 8
2287 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2288 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2289 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2290 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2291 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2292 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2293 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2294 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2295 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2296 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2297 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2298 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2299         u8 agg_val3_th;
2300         u8 agg_vars6;
2301 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2302 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2303 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2304 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2305 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2306 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2307 #elif defined(__LITTLE_ENDIAN)
2308         u8 agg_vars6;
2309 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
2310 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6_SHIFT 0
2311 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7 (0x7<<3)
2312 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7_SHIFT 3
2313 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4 (0x3<<6)
2314 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4_SHIFT 6
2315         u8 agg_val3_th;
2316         u16 agg_vars7;
2317 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
2318 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
2319 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG (0x1<<3)
2320 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG_SHIFT 3
2321 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4)
2322 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
2323 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
2324 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3_SHIFT 6
2325 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF (0x3<<8)
2326 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF_SHIFT 8
2327 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10)
2328 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
2329 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
2330 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
2331 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG (0x1<<12)
2332 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG_SHIFT 12
2333 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG (0x1<<13)
2334 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG_SHIFT 13
2335 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG (0x1<<14)
2336 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG_SHIFT 14
2337 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15)
2338 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
2339 #endif
2340 #if defined(__BIG_ENDIAN)
2341         u16 __agg_val11_th;
2342         u16 __gen_data;
2343 #elif defined(__LITTLE_ENDIAN)
2344         u16 __gen_data;
2345         u16 __agg_val11_th;
2346 #endif
2347 #if defined(__BIG_ENDIAN)
2348         u8 __reserved1;
2349         u8 __agg_val6_th;
2350         u16 __agg_val9;
2351 #elif defined(__LITTLE_ENDIAN)
2352         u16 __agg_val9;
2353         u8 __agg_val6_th;
2354         u8 __reserved1;
2355 #endif
2356 #if defined(__BIG_ENDIAN)
2357         u16 agg_val2_th;
2358         u16 agg_val2;
2359 #elif defined(__LITTLE_ENDIAN)
2360         u16 agg_val2;
2361         u16 agg_val2_th;
2362 #endif
2363         u32 agg_vars8;
2364 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)
2365 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC2_SHIFT 0
2366 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
2367 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC3_SHIFT 24
2368 #if defined(__BIG_ENDIAN)
2369         u16 agg_misc0;
2370         u16 agg_val4;
2371 #elif defined(__LITTLE_ENDIAN)
2372         u16 agg_val4;
2373         u16 agg_misc0;
2374 #endif
2375 #if defined(__BIG_ENDIAN)
2376         u8 agg_val3;
2377         u8 agg_val6;
2378         u8 agg_val5_th;
2379         u8 agg_val5;
2380 #elif defined(__LITTLE_ENDIAN)
2381         u8 agg_val5;
2382         u8 agg_val5_th;
2383         u8 agg_val6;
2384         u8 agg_val3;
2385 #endif
2386 #if defined(__BIG_ENDIAN)
2387         u16 __agg_misc1;
2388         u16 agg_limit1;
2389 #elif defined(__LITTLE_ENDIAN)
2390         u16 agg_limit1;
2391         u16 __agg_misc1;
2392 #endif
2393         u32 completion_seq;
2394         u32 agg_misc4;
2395         u32 rst_seq_num;
2396 };
2397
2398 /*
2399  * ABTS info $$KEEP_ENDIANNESS$$
2400  */
2401 struct fcoe_abts_info {
2402         __le16 aborted_task_id;
2403         __le16 reserved0;
2404         __le32 reserved1;
2405 };
2406
2407
2408 /*
2409  * Fixed size structure in order to plant it in Union structure
2410  * $$KEEP_ENDIANNESS$$
2411  */
2412 struct fcoe_abts_rsp_union {
2413         u8 r_ctl;
2414         u8 rsrv[3];
2415         __le32 abts_rsp_payload[7];
2416 };
2417
2418
2419 /*
2420  * 4 regs size $$KEEP_ENDIANNESS$$
2421  */
2422 struct fcoe_bd_ctx {
2423         __le32 buf_addr_hi;
2424         __le32 buf_addr_lo;
2425         __le16 buf_len;
2426         __le16 rsrv0;
2427         __le16 flags;
2428         __le16 rsrv1;
2429 };
2430
2431
2432 /*
2433  * FCoE cached sges context $$KEEP_ENDIANNESS$$
2434  */
2435 struct fcoe_cached_sge_ctx {
2436         struct regpair cur_buf_addr;
2437         __le16 cur_buf_rem;
2438         __le16 second_buf_rem;
2439         struct regpair second_buf_addr;
2440 };
2441
2442
2443 /*
2444  * Cleanup info $$KEEP_ENDIANNESS$$
2445  */
2446 struct fcoe_cleanup_info {
2447         __le16 cleaned_task_id;
2448         __le16 rolled_tx_seq_cnt;
2449         __le32 rolled_tx_data_offset;
2450 };
2451
2452
2453 /*
2454  * Fcp RSP flags $$KEEP_ENDIANNESS$$
2455  */
2456 struct fcoe_fcp_rsp_flags {
2457         u8 flags;
2458 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
2459 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
2460 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
2461 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
2462 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
2463 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
2464 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
2465 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
2466 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
2467 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
2468 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
2469 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
2470 };
2471
2472 /*
2473  * Fcp RSP payload $$KEEP_ENDIANNESS$$
2474  */
2475 struct fcoe_fcp_rsp_payload {
2476         struct regpair reserved0;
2477         __le32 fcp_resid;
2478         u8 scsi_status_code;
2479         struct fcoe_fcp_rsp_flags fcp_flags;
2480         __le16 retry_delay_timer;
2481         __le32 fcp_rsp_len;
2482         __le32 fcp_sns_len;
2483 };
2484
2485 /*
2486  * Fixed size structure in order to plant it in Union structure
2487  * $$KEEP_ENDIANNESS$$
2488  */
2489 struct fcoe_fcp_rsp_union {
2490         struct fcoe_fcp_rsp_payload payload;
2491         struct regpair reserved0;
2492 };
2493
2494 /*
2495  * FC header $$KEEP_ENDIANNESS$$
2496  */
2497 struct fcoe_fc_hdr {
2498         u8 s_id[3];
2499         u8 cs_ctl;
2500         u8 d_id[3];
2501         u8 r_ctl;
2502         __le16 seq_cnt;
2503         u8 df_ctl;
2504         u8 seq_id;
2505         u8 f_ctl[3];
2506         u8 type;
2507         __le32 parameters;
2508         __le16 rx_id;
2509         __le16 ox_id;
2510 };
2511
2512 /*
2513  * FC header union $$KEEP_ENDIANNESS$$
2514  */
2515 struct fcoe_mp_rsp_union {
2516         struct fcoe_fc_hdr fc_hdr;
2517         __le32 mp_payload_len;
2518         __le32 rsrv;
2519 };
2520
2521 /*
2522  * Completion information $$KEEP_ENDIANNESS$$
2523  */
2524 union fcoe_comp_flow_info {
2525         struct fcoe_fcp_rsp_union fcp_rsp;
2526         struct fcoe_abts_rsp_union abts_rsp;
2527         struct fcoe_mp_rsp_union mp_rsp;
2528         __le32 opaque[8];
2529 };
2530
2531
2532 /*
2533  * External ABTS info $$KEEP_ENDIANNESS$$
2534  */
2535 struct fcoe_ext_abts_info {
2536         __le32 rsrv0[6];
2537         struct fcoe_abts_info ctx;
2538 };
2539
2540
2541 /*
2542  * External cleanup info $$KEEP_ENDIANNESS$$
2543  */
2544 struct fcoe_ext_cleanup_info {
2545         __le32 rsrv0[6];
2546         struct fcoe_cleanup_info ctx;
2547 };
2548
2549
2550 /*
2551  * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$
2552  */
2553 struct fcoe_fw_tx_seq_ctx {
2554         __le32 data_offset;
2555         __le16 seq_cnt;
2556         __le16 rsrv0;
2557 };
2558
2559 /*
2560  * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$
2561  */
2562 struct fcoe_ext_fw_tx_seq_ctx {
2563         __le32 rsrv0[6];
2564         struct fcoe_fw_tx_seq_ctx ctx;
2565 };
2566
2567
2568 /*
2569  * FCoE multiple sges context $$KEEP_ENDIANNESS$$
2570  */
2571 struct fcoe_mul_sges_ctx {
2572         struct regpair cur_sge_addr;
2573         __le16 cur_sge_off;
2574         u8 cur_sge_idx;
2575         u8 sgl_size;
2576 };
2577
2578 /*
2579  * FCoE external multiple sges context $$KEEP_ENDIANNESS$$
2580  */
2581 struct fcoe_ext_mul_sges_ctx {
2582         struct fcoe_mul_sges_ctx mul_sgl;
2583         struct regpair rsrv0;
2584 };
2585
2586
2587 /*
2588  * FCP CMD payload $$KEEP_ENDIANNESS$$
2589  */
2590 struct fcoe_fcp_cmd_payload {
2591         __le32 opaque[8];
2592 };
2593
2594
2595
2596
2597
2598 /*
2599  * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$
2600  */
2601 struct fcoe_fcp_xfr_rdy_payload {
2602         __le32 burst_len;
2603         __le32 data_ro;
2604 };
2605
2606
2607 /*
2608  * FC frame $$KEEP_ENDIANNESS$$
2609  */
2610 struct fcoe_fc_frame {
2611         struct fcoe_fc_hdr fc_hdr;
2612         __le32 reserved0[2];
2613 };
2614
2615
2616
2617
2618 /*
2619  * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$
2620  */
2621 union fcoe_kcqe_params {
2622         __le32 reserved0[4];
2623 };
2624
2625 /*
2626  * FCoE KCQ CQE $$KEEP_ENDIANNESS$$
2627  */
2628 struct fcoe_kcqe {
2629         __le32 fcoe_conn_id;
2630         __le32 completion_status;
2631         __le32 fcoe_conn_context_id;
2632         union fcoe_kcqe_params params;
2633         __le16 qe_self_seq;
2634         u8 op_code;
2635         u8 flags;
2636 #define FCOE_KCQE_RESERVED0 (0x7<<0)
2637 #define FCOE_KCQE_RESERVED0_SHIFT 0
2638 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
2639 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
2640 #define FCOE_KCQE_LAYER_CODE (0x7<<4)
2641 #define FCOE_KCQE_LAYER_CODE_SHIFT 4
2642 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
2643 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
2644 };
2645
2646
2647
2648 /*
2649  * FCoE KWQE header $$KEEP_ENDIANNESS$$
2650  */
2651 struct fcoe_kwqe_header {
2652         u8 op_code;
2653         u8 flags;
2654 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
2655 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
2656 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
2657 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
2658 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
2659 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
2660 };
2661
2662 /*
2663  * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$
2664  */
2665 struct fcoe_kwqe_init1 {
2666         __le16 num_tasks;
2667         struct fcoe_kwqe_header hdr;
2668         __le32 task_list_pbl_addr_lo;
2669         __le32 task_list_pbl_addr_hi;
2670         __le32 dummy_buffer_addr_lo;
2671         __le32 dummy_buffer_addr_hi;
2672         __le16 sq_num_wqes;
2673         __le16 rq_num_wqes;
2674         __le16 rq_buffer_log_size;
2675         __le16 cq_num_wqes;
2676         __le16 mtu;
2677         u8 num_sessions_log;
2678         u8 flags;
2679 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
2680 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
2681 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
2682 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
2683 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
2684 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
2685 };
2686
2687 /*
2688  * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$
2689  */
2690 struct fcoe_kwqe_init2 {
2691         u8 hsi_major_version;
2692         u8 hsi_minor_version;
2693         struct fcoe_kwqe_header hdr;
2694         __le32 hash_tbl_pbl_addr_lo;
2695         __le32 hash_tbl_pbl_addr_hi;
2696         __le32 t2_hash_tbl_addr_lo;
2697         __le32 t2_hash_tbl_addr_hi;
2698         __le32 t2_ptr_hash_tbl_addr_lo;
2699         __le32 t2_ptr_hash_tbl_addr_hi;
2700         __le32 free_list_count;
2701 };
2702
2703 /*
2704  * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$
2705  */
2706 struct fcoe_kwqe_init3 {
2707         __le16 reserved0;
2708         struct fcoe_kwqe_header hdr;
2709         __le32 error_bit_map_lo;
2710         __le32 error_bit_map_hi;
2711         u8 perf_config;
2712         u8 reserved21[3];
2713         __le32 reserved2[4];
2714 };
2715
2716 /*
2717  * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$
2718  */
2719 struct fcoe_kwqe_conn_offload1 {
2720         __le16 fcoe_conn_id;
2721         struct fcoe_kwqe_header hdr;
2722         __le32 sq_addr_lo;
2723         __le32 sq_addr_hi;
2724         __le32 rq_pbl_addr_lo;
2725         __le32 rq_pbl_addr_hi;
2726         __le32 rq_first_pbe_addr_lo;
2727         __le32 rq_first_pbe_addr_hi;
2728         __le16 rq_prod;
2729         __le16 reserved0;
2730 };
2731
2732 /*
2733  * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$
2734  */
2735 struct fcoe_kwqe_conn_offload2 {
2736         __le16 tx_max_fc_pay_len;
2737         struct fcoe_kwqe_header hdr;
2738         __le32 cq_addr_lo;
2739         __le32 cq_addr_hi;
2740         __le32 xferq_addr_lo;
2741         __le32 xferq_addr_hi;
2742         __le32 conn_db_addr_lo;
2743         __le32 conn_db_addr_hi;
2744         __le32 reserved1;
2745 };
2746
2747 /*
2748  * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$
2749  */
2750 struct fcoe_kwqe_conn_offload3 {
2751         __le16 vlan_tag;
2752 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
2753 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
2754 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
2755 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
2756 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
2757 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
2758         struct fcoe_kwqe_header hdr;
2759         u8 s_id[3];
2760         u8 tx_max_conc_seqs_c3;
2761         u8 d_id[3];
2762         u8 flags;
2763 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
2764 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
2765 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
2766 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
2767 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
2768 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
2769 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
2770 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
2771 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
2772 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
2773 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
2774 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
2775 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
2776 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
2777 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
2778 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
2779         __le32 reserved;
2780         __le32 confq_first_pbe_addr_lo;
2781         __le32 confq_first_pbe_addr_hi;
2782         __le16 tx_total_conc_seqs;
2783         __le16 rx_max_fc_pay_len;
2784         __le16 rx_total_conc_seqs;
2785         u8 rx_max_conc_seqs_c3;
2786         u8 rx_open_seqs_exch_c3;
2787 };
2788
2789 /*
2790  * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$
2791  */
2792 struct fcoe_kwqe_conn_offload4 {
2793         u8 e_d_tov_timer_val;
2794         u8 reserved2;
2795         struct fcoe_kwqe_header hdr;
2796         u8 src_mac_addr_lo[2];
2797         u8 src_mac_addr_mid[2];
2798         u8 src_mac_addr_hi[2];
2799         u8 dst_mac_addr_hi[2];
2800         u8 dst_mac_addr_lo[2];
2801         u8 dst_mac_addr_mid[2];
2802         __le32 lcq_addr_lo;
2803         __le32 lcq_addr_hi;
2804         __le32 confq_pbl_base_addr_lo;
2805         __le32 confq_pbl_base_addr_hi;
2806 };
2807
2808 /*
2809  * FCoE connection enable request $$KEEP_ENDIANNESS$$
2810  */
2811 struct fcoe_kwqe_conn_enable_disable {
2812         __le16 reserved0;
2813         struct fcoe_kwqe_header hdr;
2814         u8 src_mac_addr_lo[2];
2815         u8 src_mac_addr_mid[2];
2816         u8 src_mac_addr_hi[2];
2817         u16 vlan_tag;
2818 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
2819 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
2820 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
2821 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
2822 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
2823 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
2824         u8 dst_mac_addr_lo[2];
2825         u8 dst_mac_addr_mid[2];
2826         u8 dst_mac_addr_hi[2];
2827         __le16 reserved1;
2828         u8 s_id[3];
2829         u8 vlan_flag;
2830         u8 d_id[3];
2831         u8 reserved3;
2832         __le32 context_id;
2833         __le32 conn_id;
2834         __le32 reserved4;
2835 };
2836
2837 /*
2838  * FCoE connection destroy request $$KEEP_ENDIANNESS$$
2839  */
2840 struct fcoe_kwqe_conn_destroy {
2841         __le16 reserved0;
2842         struct fcoe_kwqe_header hdr;
2843         __le32 context_id;
2844         __le32 conn_id;
2845         __le32 reserved1[5];
2846 };
2847
2848 /*
2849  * FCoe destroy request $$KEEP_ENDIANNESS$$
2850  */
2851 struct fcoe_kwqe_destroy {
2852         __le16 reserved0;
2853         struct fcoe_kwqe_header hdr;
2854         __le32 reserved1[7];
2855 };
2856
2857 /*
2858  * FCoe statistics request $$KEEP_ENDIANNESS$$
2859  */
2860 struct fcoe_kwqe_stat {
2861         __le16 reserved0;
2862         struct fcoe_kwqe_header hdr;
2863         __le32 stat_params_addr_lo;
2864         __le32 stat_params_addr_hi;
2865         __le32 reserved1[5];
2866 };
2867
2868 /*
2869  * FCoE KWQ WQE $$KEEP_ENDIANNESS$$
2870  */
2871 union fcoe_kwqe {
2872         struct fcoe_kwqe_init1 init1;
2873         struct fcoe_kwqe_init2 init2;
2874         struct fcoe_kwqe_init3 init3;
2875         struct fcoe_kwqe_conn_offload1 conn_offload1;
2876         struct fcoe_kwqe_conn_offload2 conn_offload2;
2877         struct fcoe_kwqe_conn_offload3 conn_offload3;
2878         struct fcoe_kwqe_conn_offload4 conn_offload4;
2879         struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
2880         struct fcoe_kwqe_conn_destroy conn_destroy;
2881         struct fcoe_kwqe_destroy destroy;
2882         struct fcoe_kwqe_stat statistics;
2883 };
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900 /*
2901  * TX SGL context $$KEEP_ENDIANNESS$$
2902  */
2903 union fcoe_sgl_union_ctx {
2904         struct fcoe_cached_sge_ctx cached_sge;
2905         struct fcoe_ext_mul_sges_ctx sgl;
2906         __le32 opaque[5];
2907 };
2908
2909 /*
2910  * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$
2911  */
2912 struct fcoe_read_flow_info {
2913         union fcoe_sgl_union_ctx sgl_ctx;
2914         __le32 rsrv0[3];
2915 };
2916
2917
2918 /*
2919  * Fcoe stat context $$KEEP_ENDIANNESS$$
2920  */
2921 struct fcoe_s_stat_ctx {
2922         u8 flags;
2923 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
2924 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
2925 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
2926 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
2927 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
2928 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
2929 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
2930 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
2931 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
2932 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
2933 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
2934 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
2935 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
2936 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
2937 };
2938
2939 /*
2940  * Fcoe rx seq context $$KEEP_ENDIANNESS$$
2941  */
2942 struct fcoe_rx_seq_ctx {
2943         u8 seq_id;
2944         struct fcoe_s_stat_ctx s_stat;
2945         __le16 seq_cnt;
2946         __le32 low_exp_ro;
2947         __le32 high_exp_ro;
2948 };
2949
2950
2951 /*
2952  * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$
2953  */
2954 union fcoe_rx_wr_union_ctx {
2955         struct fcoe_read_flow_info read_info;
2956         union fcoe_comp_flow_info comp_info;
2957         __le32 opaque[8];
2958 };
2959
2960
2961
2962 /*
2963  * FCoE SQ element $$KEEP_ENDIANNESS$$
2964  */
2965 struct fcoe_sqe {
2966         __le16 wqe;
2967 #define FCOE_SQE_TASK_ID (0x7FFF<<0)
2968 #define FCOE_SQE_TASK_ID_SHIFT 0
2969 #define FCOE_SQE_TOGGLE_BIT (0x1<<15)
2970 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15
2971 };
2972
2973
2974
2975 /*
2976  * 14 regs $$KEEP_ENDIANNESS$$
2977  */
2978 struct fcoe_tce_tx_only {
2979         union fcoe_sgl_union_ctx sgl_ctx;
2980         __le32 rsrv0;
2981 };
2982
2983 /*
2984  * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$
2985  */
2986 union fcoe_tx_wr_rx_rd_union_ctx {
2987         struct fcoe_fc_frame tx_frame;
2988         struct fcoe_fcp_cmd_payload fcp_cmd;
2989         struct fcoe_ext_cleanup_info cleanup;
2990         struct fcoe_ext_abts_info abts;
2991         struct fcoe_ext_fw_tx_seq_ctx tx_seq;
2992         __le32 opaque[8];
2993 };
2994
2995 /*
2996  * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$
2997  */
2998 struct fcoe_tce_tx_wr_rx_rd_const {
2999         u8 init_flags;
3000 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0)
3001 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
3002 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3)
3003 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3
3004 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4)
3005 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4
3006 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5)
3007 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5
3008 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7)
3009 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7
3010         u8 tx_flags;
3011 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0)
3012 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
3013 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1)
3014 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1
3015 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5)
3016 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
3017 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6)
3018 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
3019 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7)
3020 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7
3021         __le16 rsrv3;
3022         __le32 verify_tx_seq;
3023 };
3024
3025 /*
3026  * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$
3027  */
3028 struct fcoe_tce_tx_wr_rx_rd {
3029         union fcoe_tx_wr_rx_rd_union_ctx union_ctx;
3030         struct fcoe_tce_tx_wr_rx_rd_const const_ctx;
3031 };
3032
3033 /*
3034  * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$
3035  */
3036 struct fcoe_tce_rx_wr_tx_rd_const {
3037         __le32 data_2_trns;
3038         __le32 init_flags;
3039 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0)
3040 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
3041 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24)
3042 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24
3043 };
3044
3045 /*
3046  * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$
3047  */
3048 struct fcoe_tce_rx_wr_tx_rd_var {
3049         __le16 rx_flags;
3050 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0)
3051 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
3052 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4)
3053 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4
3054 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7)
3055 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7
3056 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8)
3057 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8
3058 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12)
3059 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12
3060 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13)
3061 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13
3062 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14)
3063 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14
3064 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15)
3065 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15
3066         __le16 rx_id;
3067         struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy;
3068 };
3069
3070 /*
3071  * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$
3072  */
3073 struct fcoe_tce_rx_wr_tx_rd {
3074         struct fcoe_tce_rx_wr_tx_rd_const const_ctx;
3075         struct fcoe_tce_rx_wr_tx_rd_var var_ctx;
3076 };
3077
3078 /*
3079  * tce_rx_only $$KEEP_ENDIANNESS$$
3080  */
3081 struct fcoe_tce_rx_only {
3082         struct fcoe_rx_seq_ctx rx_seq_ctx;
3083         union fcoe_rx_wr_union_ctx union_ctx;
3084 };
3085
3086 /*
3087  * task_ctx_entry $$KEEP_ENDIANNESS$$
3088  */
3089 struct fcoe_task_ctx_entry {
3090         struct fcoe_tce_tx_only txwr_only;
3091         struct fcoe_tce_tx_wr_rx_rd txwr_rxrd;
3092         struct fcoe_tce_rx_wr_tx_rd rxwr_txrd;
3093         struct fcoe_tce_rx_only rxwr_only;
3094 };
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105 /*
3106  * FCoE XFRQ element $$KEEP_ENDIANNESS$$
3107  */
3108 struct fcoe_xfrqe {
3109         __le16 wqe;
3110 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
3111 #define FCOE_XFRQE_TASK_ID_SHIFT 0
3112 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
3113 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
3114 };
3115
3116
3117 /*
3118  * Cached SGEs $$KEEP_ENDIANNESS$$
3119  */
3120 struct common_fcoe_sgl {
3121         struct fcoe_bd_ctx sge[3];
3122 };
3123
3124
3125 /*
3126  * FCoE SQ\XFRQ element
3127  */
3128 struct fcoe_cached_wqe {
3129         struct fcoe_sqe sqe;
3130         struct fcoe_xfrqe xfrqe;
3131 };
3132
3133
3134 /*
3135  * FCoE connection enable\disable params passed by driver to FW in FCoE enable
3136  * ramrod $$KEEP_ENDIANNESS$$
3137  */
3138 struct fcoe_conn_enable_disable_ramrod_params {
3139         struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe;
3140 };
3141
3142
3143 /*
3144  * FCoE connection offload params passed by driver to FW in FCoE offload ramrod
3145  * $$KEEP_ENDIANNESS$$
3146  */
3147 struct fcoe_conn_offload_ramrod_params {
3148         struct fcoe_kwqe_conn_offload1 offload_kwqe1;
3149         struct fcoe_kwqe_conn_offload2 offload_kwqe2;
3150         struct fcoe_kwqe_conn_offload3 offload_kwqe3;
3151         struct fcoe_kwqe_conn_offload4 offload_kwqe4;
3152 };
3153
3154
3155 struct ustorm_fcoe_mng_ctx {
3156 #if defined(__BIG_ENDIAN)
3157         u8 mid_seq_proc_flag;
3158         u8 tce_in_cam_flag;
3159         u8 tce_on_ior_flag;
3160         u8 en_cached_tce_flag;
3161 #elif defined(__LITTLE_ENDIAN)
3162         u8 en_cached_tce_flag;
3163         u8 tce_on_ior_flag;
3164         u8 tce_in_cam_flag;
3165         u8 mid_seq_proc_flag;
3166 #endif
3167 #if defined(__BIG_ENDIAN)
3168         u8 tce_cam_addr;
3169         u8 cached_conn_flag;
3170         u16 rsrv0;
3171 #elif defined(__LITTLE_ENDIAN)
3172         u16 rsrv0;
3173         u8 cached_conn_flag;
3174         u8 tce_cam_addr;
3175 #endif
3176 #if defined(__BIG_ENDIAN)
3177         u16 dma_tce_ram_addr;
3178         u16 tce_ram_addr;
3179 #elif defined(__LITTLE_ENDIAN)
3180         u16 tce_ram_addr;
3181         u16 dma_tce_ram_addr;
3182 #endif
3183 #if defined(__BIG_ENDIAN)
3184         u16 ox_id;
3185         u16 wr_done_seq;
3186 #elif defined(__LITTLE_ENDIAN)
3187         u16 wr_done_seq;
3188         u16 ox_id;
3189 #endif
3190         struct regpair task_addr;
3191 };
3192
3193 /*
3194  * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and
3195  * used in FCoE context section
3196  */
3197 struct ustorm_fcoe_params {
3198 #if defined(__BIG_ENDIAN)
3199         u16 fcoe_conn_id;
3200         u16 flags;
3201 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
3202 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
3203 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
3204 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
3205 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
3206 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
3207 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
3208 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
3209 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
3210 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
3211 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
3212 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
3213 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
3214 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
3215 #define USTORM_FCOE_PARAMS_RSRV0 (0x1FF<<7)
3216 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 7
3217 #elif defined(__LITTLE_ENDIAN)
3218         u16 flags;
3219 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
3220 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
3221 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
3222 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
3223 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
3224 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
3225 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
3226 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
3227 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
3228 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
3229 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
3230 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
3231 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
3232 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
3233 #define USTORM_FCOE_PARAMS_RSRV0 (0x1FF<<7)
3234 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 7
3235         u16 fcoe_conn_id;
3236 #endif
3237 #if defined(__BIG_ENDIAN)
3238         u8 hc_csdm_byte_en;
3239         u8 func_id;
3240         u8 port_id;
3241         u8 vnic_id;
3242 #elif defined(__LITTLE_ENDIAN)
3243         u8 vnic_id;
3244         u8 port_id;
3245         u8 func_id;
3246         u8 hc_csdm_byte_en;
3247 #endif
3248 #if defined(__BIG_ENDIAN)
3249         u16 rx_total_conc_seqs;
3250         u16 rx_max_fc_pay_len;
3251 #elif defined(__LITTLE_ENDIAN)
3252         u16 rx_max_fc_pay_len;
3253         u16 rx_total_conc_seqs;
3254 #endif
3255 #if defined(__BIG_ENDIAN)
3256         u8 task_pbe_idx_off;
3257         u8 task_in_page_log_size;
3258         u16 rx_max_conc_seqs;
3259 #elif defined(__LITTLE_ENDIAN)
3260         u16 rx_max_conc_seqs;
3261         u8 task_in_page_log_size;
3262         u8 task_pbe_idx_off;
3263 #endif
3264 };
3265
3266 /*
3267  * FCoE 16-bits index structure
3268  */
3269 struct fcoe_idx16_fields {
3270         u16 fields;
3271 #define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0)
3272 #define FCOE_IDX16_FIELDS_IDX_SHIFT 0
3273 #define FCOE_IDX16_FIELDS_MSB (0x1<<15)
3274 #define FCOE_IDX16_FIELDS_MSB_SHIFT 15
3275 };
3276
3277 /*
3278  * FCoE 16-bits index union
3279  */
3280 union fcoe_idx16_field_union {
3281         struct fcoe_idx16_fields fields;
3282         u16 val;
3283 };
3284
3285 /*
3286  * Parameters required for placement according to SGL
3287  */
3288 struct ustorm_fcoe_data_place_mng {
3289 #if defined(__BIG_ENDIAN)
3290         u16 sge_off;
3291         u8 num_sges;
3292         u8 sge_idx;
3293 #elif defined(__LITTLE_ENDIAN)
3294         u8 sge_idx;
3295         u8 num_sges;
3296         u16 sge_off;
3297 #endif
3298 };
3299
3300 /*
3301  * Parameters required for placement according to SGL
3302  */
3303 struct ustorm_fcoe_data_place {
3304         struct ustorm_fcoe_data_place_mng cached_mng;
3305         struct fcoe_bd_ctx cached_sge[2];
3306 };
3307
3308 /*
3309  * TX processing shall write and RX processing shall read from this section
3310  */
3311 union fcoe_u_tce_tx_wr_rx_rd_union {
3312         struct fcoe_abts_info abts;
3313         struct fcoe_cleanup_info cleanup;
3314         struct fcoe_fw_tx_seq_ctx tx_seq_ctx;
3315         u32 opaque[2];
3316 };
3317
3318 /*
3319  * TX processing shall write and RX processing shall read from this section
3320  */
3321 struct fcoe_u_tce_tx_wr_rx_rd {
3322         union fcoe_u_tce_tx_wr_rx_rd_union union_ctx;
3323         struct fcoe_tce_tx_wr_rx_rd_const const_ctx;
3324 };
3325
3326 struct ustorm_fcoe_tce {
3327         struct fcoe_u_tce_tx_wr_rx_rd txwr_rxrd;
3328         struct fcoe_tce_rx_wr_tx_rd rxwr_txrd;
3329         struct fcoe_tce_rx_only rxwr;
3330 };
3331
3332 struct ustorm_fcoe_cache_ctx {
3333         u32 rsrv0;
3334         struct ustorm_fcoe_data_place data_place;
3335         struct ustorm_fcoe_tce tce;
3336 };
3337
3338 /*
3339  * Ustorm FCoE Storm Context
3340  */
3341 struct ustorm_fcoe_st_context {
3342         struct ustorm_fcoe_mng_ctx mng_ctx;
3343         struct ustorm_fcoe_params fcoe_params;
3344         struct regpair cq_base_addr;
3345         struct regpair rq_pbl_base;
3346         struct regpair rq_cur_page_addr;
3347         struct regpair confq_pbl_base_addr;
3348         struct regpair conn_db_base;
3349         struct regpair xfrq_base_addr;
3350         struct regpair lcq_base_addr;
3351 #if defined(__BIG_ENDIAN)
3352         union fcoe_idx16_field_union rq_cons;
3353         union fcoe_idx16_field_union rq_prod;
3354 #elif defined(__LITTLE_ENDIAN)
3355         union fcoe_idx16_field_union rq_prod;
3356         union fcoe_idx16_field_union rq_cons;
3357 #endif
3358 #if defined(__BIG_ENDIAN)
3359         u16 xfrq_prod;
3360         u16 cq_cons;
3361 #elif defined(__LITTLE_ENDIAN)
3362         u16 cq_cons;
3363         u16 xfrq_prod;
3364 #endif
3365 #if defined(__BIG_ENDIAN)
3366         u16 lcq_cons;
3367         u16 hc_cram_address;
3368 #elif defined(__LITTLE_ENDIAN)
3369         u16 hc_cram_address;
3370         u16 lcq_cons;
3371 #endif
3372 #if defined(__BIG_ENDIAN)
3373         u16 sq_xfrq_lcq_confq_size;
3374         u16 confq_prod;
3375 #elif defined(__LITTLE_ENDIAN)
3376         u16 confq_prod;
3377         u16 sq_xfrq_lcq_confq_size;
3378 #endif
3379 #if defined(__BIG_ENDIAN)
3380         u8 hc_csdm_agg_int;
3381         u8 rsrv2;
3382         u8 available_rqes;
3383         u8 sp_q_flush_cnt;
3384 #elif defined(__LITTLE_ENDIAN)
3385         u8 sp_q_flush_cnt;
3386         u8 available_rqes;
3387         u8 rsrv2;
3388         u8 hc_csdm_agg_int;
3389 #endif
3390 #if defined(__BIG_ENDIAN)
3391         u16 num_pend_tasks;
3392         u16 pbf_ack_ram_addr;
3393 #elif defined(__LITTLE_ENDIAN)
3394         u16 pbf_ack_ram_addr;
3395         u16 num_pend_tasks;
3396 #endif
3397         struct ustorm_fcoe_cache_ctx cache_ctx;
3398 };
3399
3400 /*
3401  * The FCoE non-aggregative context of Tstorm
3402  */
3403 struct tstorm_fcoe_st_context {
3404         struct regpair reserved0;
3405         struct regpair reserved1;
3406 };
3407
3408 /*
3409  * Ethernet context section
3410  */
3411 struct xstorm_fcoe_eth_context_section {
3412 #if defined(__BIG_ENDIAN)
3413         u8 remote_addr_4;
3414         u8 remote_addr_5;
3415         u8 local_addr_0;
3416         u8 local_addr_1;
3417 #elif defined(__LITTLE_ENDIAN)
3418         u8 local_addr_1;
3419         u8 local_addr_0;
3420         u8 remote_addr_5;
3421         u8 remote_addr_4;
3422 #endif
3423 #if defined(__BIG_ENDIAN)
3424         u8 remote_addr_0;
3425         u8 remote_addr_1;
3426         u8 remote_addr_2;
3427         u8 remote_addr_3;
3428 #elif defined(__LITTLE_ENDIAN)
3429         u8 remote_addr_3;
3430         u8 remote_addr_2;
3431         u8 remote_addr_1;
3432         u8 remote_addr_0;
3433 #endif
3434 #if defined(__BIG_ENDIAN)
3435         u16 reserved_vlan_type;
3436         u16 params;
3437 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
3438 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
3439 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
3440 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
3441 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
3442 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
3443 #elif defined(__LITTLE_ENDIAN)
3444         u16 params;
3445 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
3446 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
3447 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
3448 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
3449 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
3450 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
3451         u16 reserved_vlan_type;
3452 #endif
3453 #if defined(__BIG_ENDIAN)
3454         u8 local_addr_2;
3455         u8 local_addr_3;
3456         u8 local_addr_4;
3457         u8 local_addr_5;
3458 #elif defined(__LITTLE_ENDIAN)
3459         u8 local_addr_5;
3460         u8 local_addr_4;
3461         u8 local_addr_3;
3462         u8 local_addr_2;
3463 #endif
3464 };
3465
3466 /*
3467  * Flags used in FCoE context section - 1 byte
3468  */
3469 struct xstorm_fcoe_context_flags {
3470         u8 flags;
3471 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0)
3472 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0
3473 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2)
3474 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2
3475 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3)
3476 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ_SHIFT 3
3477 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4)
3478 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4
3479 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5)
3480 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5
3481 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6)
3482 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6
3483 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7)
3484 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN_SHIFT 7
3485 };
3486
3487 struct xstorm_fcoe_tce {
3488         struct fcoe_tce_tx_only txwr;
3489         struct fcoe_tce_tx_wr_rx_rd txwr_rxrd;
3490 };
3491
3492 /*
3493  * FCP_DATA parameters required for transmission
3494  */
3495 struct xstorm_fcoe_fcp_data {
3496         u32 io_rem;
3497 #if defined(__BIG_ENDIAN)
3498         u16 cached_sge_off;
3499         u8 cached_num_sges;
3500         u8 cached_sge_idx;
3501 #elif defined(__LITTLE_ENDIAN)
3502         u8 cached_sge_idx;
3503         u8 cached_num_sges;
3504         u16 cached_sge_off;
3505 #endif
3506         u32 buf_addr_hi_0;
3507         u32 buf_addr_lo_0;
3508 #if defined(__BIG_ENDIAN)
3509         u16 num_of_pending_tasks;
3510         u16 buf_len_0;
3511 #elif defined(__LITTLE_ENDIAN)
3512         u16 buf_len_0;
3513         u16 num_of_pending_tasks;
3514 #endif
3515         u32 buf_addr_hi_1;
3516         u32 buf_addr_lo_1;
3517 #if defined(__BIG_ENDIAN)
3518         u16 task_pbe_idx_off;
3519         u16 buf_len_1;
3520 #elif defined(__LITTLE_ENDIAN)
3521         u16 buf_len_1;
3522         u16 task_pbe_idx_off;
3523 #endif
3524         u32 buf_addr_hi_2;
3525         u32 buf_addr_lo_2;
3526 #if defined(__BIG_ENDIAN)
3527         u16 ox_id;
3528         u16 buf_len_2;
3529 #elif defined(__LITTLE_ENDIAN)
3530         u16 buf_len_2;
3531         u16 ox_id;
3532 #endif
3533 };
3534
3535 /*
3536  * vlan configuration
3537  */
3538 struct xstorm_fcoe_vlan_conf {
3539         u8 vlan_conf;
3540 #define XSTORM_FCOE_VLAN_CONF_PRIORITY (0x7<<0)
3541 #define XSTORM_FCOE_VLAN_CONF_PRIORITY_SHIFT 0
3542 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3)
3543 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG_SHIFT 3
3544 #define XSTORM_FCOE_VLAN_CONF_RESERVED (0xF<<4)
3545 #define XSTORM_FCOE_VLAN_CONF_RESERVED_SHIFT 4
3546 };
3547
3548 /*
3549  * FCoE 16-bits vlan structure
3550  */
3551 struct fcoe_vlan_fields {
3552         u16 fields;
3553 #define FCOE_VLAN_FIELDS_VID (0xFFF<<0)
3554 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
3555 #define FCOE_VLAN_FIELDS_CLI (0x1<<12)
3556 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
3557 #define FCOE_VLAN_FIELDS_PRI (0x7<<13)
3558 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
3559 };
3560
3561 /*
3562  * FCoE 16-bits vlan union
3563  */
3564 union fcoe_vlan_field_union {
3565         struct fcoe_vlan_fields fields;
3566         u16 val;
3567 };
3568
3569 /*
3570  * FCoE 16-bits vlan, vif union
3571  */
3572 union fcoe_vlan_vif_field_union {
3573         union fcoe_vlan_field_union vlan;
3574         u16 vif;
3575 };
3576
3577 /*
3578  * FCoE context section
3579  */
3580 struct xstorm_fcoe_context_section {
3581 #if defined(__BIG_ENDIAN)
3582         u8 cs_ctl;
3583         u8 s_id[3];
3584 #elif defined(__LITTLE_ENDIAN)
3585         u8 s_id[3];
3586         u8 cs_ctl;
3587 #endif
3588 #if defined(__BIG_ENDIAN)
3589         u8 rctl;
3590         u8 d_id[3];
3591 #elif defined(__LITTLE_ENDIAN)
3592         u8 d_id[3];
3593         u8 rctl;
3594 #endif
3595 #if defined(__BIG_ENDIAN)
3596         u16 sq_xfrq_lcq_confq_size;
3597         u16 tx_max_fc_pay_len;
3598 #elif defined(__LITTLE_ENDIAN)
3599         u16 tx_max_fc_pay_len;
3600         u16 sq_xfrq_lcq_confq_size;
3601 #endif
3602         u32 lcq_prod;
3603 #if defined(__BIG_ENDIAN)
3604         u8 port_id;
3605         u8 func_id;
3606         u8 seq_id;
3607         struct xstorm_fcoe_context_flags tx_flags;
3608 #elif defined(__LITTLE_ENDIAN)
3609         struct xstorm_fcoe_context_flags tx_flags;
3610         u8 seq_id;
3611         u8 func_id;
3612         u8 port_id;
3613 #endif
3614 #if defined(__BIG_ENDIAN)
3615         u16 mtu;
3616         u8 func_mode;
3617         u8 vnic_id;
3618 #elif defined(__LITTLE_ENDIAN)
3619         u8 vnic_id;
3620         u8 func_mode;
3621         u16 mtu;
3622 #endif
3623         struct regpair confq_curr_page_addr;
3624         struct fcoe_cached_wqe cached_wqe[8];
3625         struct regpair lcq_base_addr;
3626         struct xstorm_fcoe_tce tce;
3627         struct xstorm_fcoe_fcp_data fcp_data;
3628 #if defined(__BIG_ENDIAN)
3629         u8 tx_max_conc_seqs_c3;
3630         u8 vlan_flag;
3631         u8 dcb_val;
3632         u8 data_pb_cmd_size;
3633 #elif defined(__LITTLE_ENDIAN)
3634         u8 data_pb_cmd_size;
3635         u8 dcb_val;
3636         u8 vlan_flag;
3637         u8 tx_max_conc_seqs_c3;
3638 #endif
3639 #if defined(__BIG_ENDIAN)
3640         u16 fcoe_tx_stat_params_ram_addr;
3641         u16 fcoe_tx_fc_seq_ram_addr;
3642 #elif defined(__LITTLE_ENDIAN)
3643         u16 fcoe_tx_fc_seq_ram_addr;
3644         u16 fcoe_tx_stat_params_ram_addr;
3645 #endif
3646 #if defined(__BIG_ENDIAN)
3647         u8 fcp_cmd_line_credit;
3648         u8 eth_hdr_size;
3649         u16 pbf_addr;
3650 #elif defined(__LITTLE_ENDIAN)
3651         u16 pbf_addr;
3652         u8 eth_hdr_size;
3653         u8 fcp_cmd_line_credit;
3654 #endif
3655 #if defined(__BIG_ENDIAN)
3656         union fcoe_vlan_vif_field_union multi_func_val;
3657         u8 page_log_size;
3658         struct xstorm_fcoe_vlan_conf orig_vlan_conf;
3659 #elif defined(__LITTLE_ENDIAN)
3660         struct xstorm_fcoe_vlan_conf orig_vlan_conf;
3661         u8 page_log_size;
3662         union fcoe_vlan_vif_field_union multi_func_val;
3663 #endif
3664 #if defined(__BIG_ENDIAN)
3665         u16 fcp_cmd_frame_size;
3666         u16 pbf_addr_ff;
3667 #elif defined(__LITTLE_ENDIAN)
3668         u16 pbf_addr_ff;
3669         u16 fcp_cmd_frame_size;
3670 #endif
3671 #if defined(__BIG_ENDIAN)
3672         u8 vlan_num;
3673         u8 cos;
3674         u8 cache_xfrq_cons;
3675         u8 cache_sq_cons;
3676 #elif defined(__LITTLE_ENDIAN)
3677         u8 cache_sq_cons;
3678         u8 cache_xfrq_cons;
3679         u8 cos;
3680         u8 vlan_num;
3681 #endif
3682         u32 verify_tx_seq;
3683 };
3684
3685 /*
3686  * Xstorm FCoE Storm Context
3687  */
3688 struct xstorm_fcoe_st_context {
3689         struct xstorm_fcoe_eth_context_section eth;
3690         struct xstorm_fcoe_context_section fcoe;
3691 };
3692
3693 /*
3694  * Fcoe connection context
3695  */
3696 struct fcoe_context {
3697         struct ustorm_fcoe_st_context ustorm_st_context;
3698         struct tstorm_fcoe_st_context tstorm_st_context;
3699         struct xstorm_fcoe_ag_context xstorm_ag_context;
3700         struct tstorm_fcoe_ag_context tstorm_ag_context;
3701         struct ustorm_fcoe_ag_context ustorm_ag_context;
3702         struct timers_block_context timers_context;
3703         struct xstorm_fcoe_st_context xstorm_st_context;
3704 };
3705
3706 /*
3707  * FCoE init params passed by driver to FW in FCoE init ramrod
3708  * $$KEEP_ENDIANNESS$$
3709  */
3710 struct fcoe_init_ramrod_params {
3711         struct fcoe_kwqe_init1 init_kwqe1;
3712         struct fcoe_kwqe_init2 init_kwqe2;
3713         struct fcoe_kwqe_init3 init_kwqe3;
3714         struct regpair eq_pbl_base;
3715         __le32 eq_pbl_size;
3716         __le32 reserved2;
3717         __le16 eq_prod;
3718         __le16 sb_num;
3719         u8 sb_id;
3720         u8 reserved0;
3721         __le16 reserved1;
3722 };
3723
3724 /*
3725  * FCoE statistics params buffer passed by driver to FW in FCoE statistics
3726  * ramrod $$KEEP_ENDIANNESS$$
3727  */
3728 struct fcoe_stat_ramrod_params {
3729         struct fcoe_kwqe_stat stat_kwqe;
3730 };
3731
3732 /*
3733  * CQ DB CQ producer and pending completion counter
3734  */
3735 struct iscsi_cq_db_prod_pnd_cmpltn_cnt {
3736 #if defined(__BIG_ENDIAN)
3737         u16 cntr;
3738         u16 prod;
3739 #elif defined(__LITTLE_ENDIAN)
3740         u16 prod;
3741         u16 cntr;
3742 #endif
3743 };
3744
3745 /*
3746  * CQ DB pending completion ITT array
3747  */
3748 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr {
3749         struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8];
3750 };
3751
3752 /*
3753  * Cstorm CQ sequence to notify array, updated by driver
3754  */
3755 struct iscsi_cq_db_sqn_2_notify_arr {
3756         u16 sqn[8];
3757 };
3758
3759 /*
3760  * Cstorm iSCSI Storm Context
3761  */
3762 struct cstorm_iscsi_st_context {
3763         struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr;
3764         struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr;
3765         struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr;
3766         struct regpair hq_pbl_base;
3767         struct regpair hq_curr_pbe;
3768         struct regpair task_pbl_base;
3769         struct regpair cq_db_base;
3770 #if defined(__BIG_ENDIAN)
3771         u16 hq_bd_itt;
3772         u16 iscsi_conn_id;
3773 #elif defined(__LITTLE_ENDIAN)
3774         u16 iscsi_conn_id;
3775         u16 hq_bd_itt;
3776 #endif
3777         u32 hq_bd_data_segment_len;
3778         u32 hq_bd_buffer_offset;
3779 #if defined(__BIG_ENDIAN)
3780         u8 rsrv;
3781         u8 cq_proc_en_bit_map;
3782         u8 cq_pend_comp_itt_valid_bit_map;
3783         u8 hq_bd_opcode;
3784 #elif defined(__LITTLE_ENDIAN)
3785         u8 hq_bd_opcode;
3786         u8 cq_pend_comp_itt_valid_bit_map;
3787         u8 cq_proc_en_bit_map;
3788         u8 rsrv;
3789 #endif
3790         u32 hq_tcp_seq;
3791 #if defined(__BIG_ENDIAN)
3792         u16 flags;
3793 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0)
3794 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
3795 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1)
3796 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
3797 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2)
3798 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
3799 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3)
3800 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
3801 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4)
3802 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
3803 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5)
3804 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
3805         u16 hq_cons;
3806 #elif defined(__LITTLE_ENDIAN)
3807         u16 hq_cons;
3808         u16 flags;
3809 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0)
3810 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
3811 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1)
3812 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
3813 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2)
3814 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
3815 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3)
3816 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
3817 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4)
3818 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
3819 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5)
3820 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
3821 #endif
3822         struct regpair rsrv1;
3823 };
3824
3825
3826 /*
3827  * SCSI read/write SQ WQE
3828  */
3829 struct iscsi_cmd_pdu_hdr_little_endian {
3830 #if defined(__BIG_ENDIAN)
3831         u8 opcode;
3832         u8 op_attr;
3833 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0)
3834 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
3835 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3)
3836 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
3837 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5)
3838 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
3839 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6)
3840 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
3841 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
3842 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
3843         u16 rsrv0;
3844 #elif defined(__LITTLE_ENDIAN)
3845         u16 rsrv0;
3846         u8 op_attr;
3847 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0)
3848 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
3849 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3)
3850 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
3851 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5)
3852 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
3853 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6)
3854 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
3855 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
3856 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
3857         u8 opcode;
3858 #endif
3859         u32 data_fields;
3860 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
3861 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
3862 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
3863 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
3864         struct regpair lun;
3865         u32 itt;
3866         u32 expected_data_transfer_length;
3867         u32 cmd_sn;
3868         u32 exp_stat_sn;
3869         u32 scsi_command_block[4];
3870 };
3871
3872
3873 /*
3874  * Buffer per connection, used in Tstorm
3875  */
3876 struct iscsi_conn_buf {
3877         struct regpair reserved[8];
3878 };
3879
3880
3881 /*
3882  * iSCSI context region, used only in iSCSI
3883  */
3884 struct ustorm_iscsi_rq_db {
3885         struct regpair pbl_base;
3886         struct regpair curr_pbe;
3887 };
3888
3889 /*
3890  * iSCSI context region, used only in iSCSI
3891  */
3892 struct ustorm_iscsi_r2tq_db {
3893         struct regpair pbl_base;
3894         struct regpair curr_pbe;
3895 };
3896
3897 /*
3898  * iSCSI context region, used only in iSCSI
3899  */
3900 struct ustorm_iscsi_cq_db {
3901 #if defined(__BIG_ENDIAN)
3902         u16 cq_sn;
3903         u16 prod;
3904 #elif defined(__LITTLE_ENDIAN)
3905         u16 prod;
3906         u16 cq_sn;
3907 #endif
3908         struct regpair curr_pbe;
3909 };
3910
3911 /*
3912  * iSCSI context region, used only in iSCSI
3913  */
3914 struct rings_db {
3915         struct ustorm_iscsi_rq_db rq;
3916         struct ustorm_iscsi_r2tq_db r2tq;
3917         struct ustorm_iscsi_cq_db cq[8];
3918 #if defined(__BIG_ENDIAN)
3919         u16 rq_prod;
3920         u16 r2tq_prod;
3921 #elif defined(__LITTLE_ENDIAN)
3922         u16 r2tq_prod;
3923         u16 rq_prod;
3924 #endif
3925         struct regpair cq_pbl_base;
3926 };
3927
3928 /*
3929  * iSCSI context region, used only in iSCSI
3930  */
3931 struct ustorm_iscsi_placement_db {
3932         u32 sgl_base_lo;
3933         u32 sgl_base_hi;
3934         u32 local_sge_0_address_hi;
3935         u32 local_sge_0_address_lo;
3936 #if defined(__BIG_ENDIAN)
3937         u16 curr_sge_offset;
3938         u16 local_sge_0_size;
3939 #elif defined(__LITTLE_ENDIAN)
3940         u16 local_sge_0_size;
3941         u16 curr_sge_offset;
3942 #endif
3943         u32 local_sge_1_address_hi;
3944         u32 local_sge_1_address_lo;
3945 #if defined(__BIG_ENDIAN)
3946         u8 exp_padding_2b;
3947         u8 nal_len_3b;
3948         u16 local_sge_1_size;
3949 #elif defined(__LITTLE_ENDIAN)
3950         u16 local_sge_1_size;
3951         u8 nal_len_3b;
3952         u8 exp_padding_2b;
3953 #endif
3954 #if defined(__BIG_ENDIAN)
3955         u8 sgl_size;
3956         u8 local_sge_index_2b;
3957         u16 reserved7;
3958 #elif defined(__LITTLE_ENDIAN)
3959         u16 reserved7;
3960         u8 local_sge_index_2b;
3961         u8 sgl_size;
3962 #endif
3963         u32 rem_pdu;
3964         u32 place_db_bitfield_1;
3965 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0)
3966 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0
3967 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24)
3968 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24
3969         u32 place_db_bitfield_2;
3970 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0)
3971 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0
3972 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24)
3973 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24
3974         u32 nal;
3975 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0)
3976 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0
3977 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24)
3978 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 24
3979 };
3980
3981 /*
3982  * Ustorm iSCSI Storm Context
3983  */
3984 struct ustorm_iscsi_st_context {
3985         u32 exp_stat_sn;
3986         u32 exp_data_sn;
3987         struct rings_db ring;
3988         struct regpair task_pbl_base;
3989         struct regpair tce_phy_addr;
3990         struct ustorm_iscsi_placement_db place_db;
3991         u32 reserved8;
3992         u32 rem_rcv_len;
3993 #if defined(__BIG_ENDIAN)
3994         u16 hdr_itt;
3995         u16 iscsi_conn_id;
3996 #elif defined(__LITTLE_ENDIAN)
3997         u16 iscsi_conn_id;
3998         u16 hdr_itt;
3999 #endif
4000         u32 nal_bytes;
4001 #if defined(__BIG_ENDIAN)
4002         u8 hdr_second_byte_union;
4003         u8 bitfield_0;
4004 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0)
4005 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
4006 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1)
4007 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
4008 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2)
4009 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
4010 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3)
4011 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
4012         u8 task_pdu_cache_index;
4013         u8 task_pbe_cache_index;
4014 #elif defined(__LITTLE_ENDIAN)
4015         u8 task_pbe_cache_index;
4016         u8 task_pdu_cache_index;
4017         u8 bitfield_0;
4018 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0)
4019 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
4020 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1)
4021 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
4022 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2)
4023 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
4024 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3)
4025 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
4026         u8 hdr_second_byte_union;
4027 #endif
4028 #if defined(__BIG_ENDIAN)
4029         u16 reserved3;
4030         u8 reserved2;
4031         u8 acDecrement;
4032 #elif defined(__LITTLE_ENDIAN)
4033         u8 acDecrement;
4034         u8 reserved2;
4035         u16 reserved3;
4036 #endif
4037         u32 task_stat;
4038 #if defined(__BIG_ENDIAN)
4039         u8 hdr_opcode;
4040         u8 num_cqs;
4041         u16 reserved5;
4042 #elif defined(__LITTLE_ENDIAN)
4043         u16 reserved5;
4044         u8 num_cqs;
4045         u8 hdr_opcode;
4046 #endif
4047         u32 negotiated_rx;
4048 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0)
4049 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0
4050 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24)
4051 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24
4052         u32 negotiated_rx_and_flags;
4053 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0)
4054 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0
4055 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24)
4056 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24
4057 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25)
4058 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25
4059 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26)
4060 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26
4061 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27)
4062 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27
4063 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28)
4064 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28
4065 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29)
4066 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29
4067 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31)
4068 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31
4069 };
4070
4071 /*
4072  * TCP context region, shared in TOE, RDMA and ISCSI
4073  */
4074 struct tstorm_tcp_st_context_section {
4075         u32 flags1;
4076 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0)
4077 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0
4078 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24)
4079 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24
4080 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25)
4081 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25
4082 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26)
4083 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26
4084 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27)
4085 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27
4086 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28)
4087 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28
4088 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29)
4089 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29
4090 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30)
4091 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30
4092 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31)
4093 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31
4094         u32 flags2;
4095 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0)
4096 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0
4097 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24)
4098 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24
4099 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25)
4100 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25
4101 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26)
4102 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26
4103 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27)
4104 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27
4105 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28)
4106 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28
4107 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29)
4108 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29
4109 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30)
4110 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30
4111 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31)
4112 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31
4113 #if defined(__BIG_ENDIAN)
4114         u16 mss;
4115         u8 tcp_sm_state;
4116         u8 rto_exp;
4117 #elif defined(__LITTLE_ENDIAN)
4118         u8 rto_exp;
4119         u8 tcp_sm_state;
4120         u16 mss;
4121 #endif
4122         u32 rcv_nxt;
4123         u32 timestamp_recent;
4124         u32 timestamp_recent_time;
4125         u32 cwnd;
4126         u32 ss_thresh;
4127         u32 cwnd_accum;
4128         u32 prev_seg_seq;
4129         u32 expected_rel_seq;
4130         u32 recover;
4131 #if defined(__BIG_ENDIAN)
4132         u8 retransmit_count;
4133         u8 ka_max_probe_count;
4134         u8 persist_probe_count;
4135         u8 ka_probe_count;
4136 #elif defined(__LITTLE_ENDIAN)
4137         u8 ka_probe_count;
4138         u8 persist_probe_count;
4139         u8 ka_max_probe_count;
4140         u8 retransmit_count;
4141 #endif
4142 #if defined(__BIG_ENDIAN)
4143         u8 statistics_counter_id;
4144         u8 ooo_support_mode;
4145         u8 snd_wnd_scale;
4146         u8 dup_ack_count;
4147 #elif defined(__LITTLE_ENDIAN)
4148         u8 dup_ack_count;
4149         u8 snd_wnd_scale;
4150         u8 ooo_support_mode;
4151         u8 statistics_counter_id;
4152 #endif
4153         u32 retransmit_start_time;
4154         u32 ka_timeout;
4155         u32 ka_interval;
4156         u32 isle_start_seq;
4157         u32 isle_end_seq;
4158 #if defined(__BIG_ENDIAN)
4159         u16 second_isle_address;
4160         u16 recent_seg_wnd;
4161 #elif defined(__LITTLE_ENDIAN)
4162         u16 recent_seg_wnd;
4163         u16 second_isle_address;
4164 #endif
4165 #if defined(__BIG_ENDIAN)
4166         u8 max_isles_ever_happened;
4167         u8 isles_number;
4168         u16 last_isle_address;
4169 #elif defined(__LITTLE_ENDIAN)
4170         u16 last_isle_address;
4171         u8 isles_number;
4172         u8 max_isles_ever_happened;
4173 #endif
4174         u32 max_rt_time;
4175 #if defined(__BIG_ENDIAN)
4176         u16 lsb_mac_address;
4177         u16 vlan_id;
4178 #elif defined(__LITTLE_ENDIAN)
4179         u16 vlan_id;
4180         u16 lsb_mac_address;
4181 #endif
4182 #if defined(__BIG_ENDIAN)
4183         u16 msb_mac_address;
4184         u16 mid_mac_address;
4185 #elif defined(__LITTLE_ENDIAN)
4186         u16 mid_mac_address;
4187         u16 msb_mac_address;
4188 #endif
4189         u32 rightmost_received_seq;
4190 };
4191
4192 /*
4193  * Termination variables
4194  */
4195 struct iscsi_term_vars {
4196         u8 BitMap;
4197 #define ISCSI_TERM_VARS_TCP_STATE (0xF<<0)
4198 #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0
4199 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4)
4200 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4
4201 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5)
4202 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5
4203 #define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6)
4204 #define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6
4205 #define ISCSI_TERM_VARS_RSRV (0x1<<7)
4206 #define ISCSI_TERM_VARS_RSRV_SHIFT 7
4207 };
4208
4209 /*
4210  * iSCSI context region, used only in iSCSI
4211  */
4212 struct tstorm_iscsi_st_context_section {
4213         u32 nalPayload;
4214         u32 b2nh;
4215 #if defined(__BIG_ENDIAN)
4216         u16 rq_cons;
4217         u8 flags;
4218 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0)
4219 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
4220 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1)
4221 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
4222 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2)
4223 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
4224 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3)
4225 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
4226 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4)
4227 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
4228 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5)
4229 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
4230 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7)
4231 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
4232         u8 hdr_bytes_2_fetch;
4233 #elif defined(__LITTLE_ENDIAN)
4234         u8 hdr_bytes_2_fetch;
4235         u8 flags;
4236 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0)
4237 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
4238 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1)
4239 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
4240 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2)
4241 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
4242 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3)
4243 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
4244 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4)
4245 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
4246 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5)
4247 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
4248 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7)
4249 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
4250         u16 rq_cons;
4251 #endif
4252         struct regpair rq_db_phy_addr;
4253 #if defined(__BIG_ENDIAN)
4254         struct iscsi_term_vars term_vars;
4255         u8 rsrv1;
4256         u16 iscsi_conn_id;
4257 #elif defined(__LITTLE_ENDIAN)
4258         u16 iscsi_conn_id;
4259         u8 rsrv1;
4260         struct iscsi_term_vars term_vars;
4261 #endif
4262         u32 process_nxt;
4263 };
4264
4265 /*
4266  * The iSCSI non-aggregative context of Tstorm
4267  */
4268 struct tstorm_iscsi_st_context {
4269         struct tstorm_tcp_st_context_section tcp;
4270         struct tstorm_iscsi_st_context_section iscsi;
4271 };
4272
4273 /*
4274  * Ethernet context section, shared in TOE, RDMA and ISCSI
4275  */
4276 struct xstorm_eth_context_section {
4277 #if defined(__BIG_ENDIAN)
4278         u8 remote_addr_4;
4279         u8 remote_addr_5;
4280         u8 local_addr_0;
4281         u8 local_addr_1;
4282 #elif defined(__LITTLE_ENDIAN)
4283         u8 local_addr_1;
4284         u8 local_addr_0;
4285         u8 remote_addr_5;
4286         u8 remote_addr_4;
4287 #endif
4288 #if defined(__BIG_ENDIAN)
4289         u8 remote_addr_0;
4290         u8 remote_addr_1;
4291         u8 remote_addr_2;
4292         u8 remote_addr_3;
4293 #elif defined(__LITTLE_ENDIAN)
4294         u8 remote_addr_3;
4295         u8 remote_addr_2;
4296         u8 remote_addr_1;
4297         u8 remote_addr_0;
4298 #endif
4299 #if defined(__BIG_ENDIAN)
4300         u16 reserved_vlan_type;
4301         u16 params;
4302 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
4303 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
4304 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
4305 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
4306 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
4307 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
4308 #elif defined(__LITTLE_ENDIAN)
4309         u16 params;
4310 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
4311 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
4312 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12)
4313 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
4314 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
4315 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
4316         u16 reserved_vlan_type;
4317 #endif
4318 #if defined(__BIG_ENDIAN)
4319         u8 local_addr_2;
4320         u8 local_addr_3;
4321         u8 local_addr_4;
4322         u8 local_addr_5;
4323 #elif defined(__LITTLE_ENDIAN)
4324         u8 local_addr_5;
4325         u8 local_addr_4;
4326         u8 local_addr_3;
4327         u8 local_addr_2;
4328 #endif
4329 };
4330
4331 /*
4332  * IpV4 context section, shared in TOE, RDMA and ISCSI
4333  */
4334 struct xstorm_ip_v4_context_section {
4335 #if defined(__BIG_ENDIAN)
4336         u16 __pbf_hdr_cmd_rsvd_id;
4337         u16 __pbf_hdr_cmd_rsvd_flags_offset;
4338 #elif defined(__LITTLE_ENDIAN)
4339         u16 __pbf_hdr_cmd_rsvd_flags_offset;
4340         u16 __pbf_hdr_cmd_rsvd_id;
4341 #endif
4342 #if defined(__BIG_ENDIAN)
4343         u8 __pbf_hdr_cmd_rsvd_ver_ihl;
4344         u8 tos;
4345         u16 __pbf_hdr_cmd_rsvd_length;
4346 #elif defined(__LITTLE_ENDIAN)
4347         u16 __pbf_hdr_cmd_rsvd_length;
4348         u8 tos;
4349         u8 __pbf_hdr_cmd_rsvd_ver_ihl;
4350 #endif
4351         u32 ip_local_addr;
4352 #if defined(__BIG_ENDIAN)
4353         u8 ttl;
4354         u8 __pbf_hdr_cmd_rsvd_protocol;
4355         u16 __pbf_hdr_cmd_rsvd_csum;
4356 #elif defined(__LITTLE_ENDIAN)
4357         u16 __pbf_hdr_cmd_rsvd_csum;
4358         u8 __pbf_hdr_cmd_rsvd_protocol;
4359         u8 ttl;
4360 #endif
4361         u32 __pbf_hdr_cmd_rsvd_1;
4362         u32 ip_remote_addr;
4363 };
4364
4365 /*
4366  * context section, shared in TOE, RDMA and ISCSI
4367  */
4368 struct xstorm_padded_ip_v4_context_section {
4369         struct xstorm_ip_v4_context_section ip_v4;
4370         u32 reserved1[4];
4371 };
4372
4373 /*
4374  * IpV6 context section, shared in TOE, RDMA and ISCSI
4375  */
4376 struct xstorm_ip_v6_context_section {
4377 #if defined(__BIG_ENDIAN)
4378         u16 pbf_hdr_cmd_rsvd_payload_len;
4379         u8 pbf_hdr_cmd_rsvd_nxt_hdr;
4380         u8 hop_limit;
4381 #elif defined(__LITTLE_ENDIAN)
4382         u8 hop_limit;
4383         u8 pbf_hdr_cmd_rsvd_nxt_hdr;
4384         u16 pbf_hdr_cmd_rsvd_payload_len;
4385 #endif
4386         u32 priority_flow_label;
4387 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0)
4388 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0
4389 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20)
4390 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20
4391 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28)
4392 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28
4393         u32 ip_local_addr_lo_hi;
4394         u32 ip_local_addr_lo_lo;
4395         u32 ip_local_addr_hi_hi;
4396         u32 ip_local_addr_hi_lo;
4397         u32 ip_remote_addr_lo_hi;
4398         u32 ip_remote_addr_lo_lo;
4399         u32 ip_remote_addr_hi_hi;
4400         u32 ip_remote_addr_hi_lo;
4401 };
4402
4403 union xstorm_ip_context_section_types {
4404         struct xstorm_padded_ip_v4_context_section padded_ip_v4;
4405         struct xstorm_ip_v6_context_section ip_v6;
4406 };
4407
4408 /*
4409  * TCP context section, shared in TOE, RDMA and ISCSI
4410  */
4411 struct xstorm_tcp_context_section {
4412         u32 snd_max;
4413 #if defined(__BIG_ENDIAN)
4414         u16 remote_port;
4415         u16 local_port;
4416 #elif defined(__LITTLE_ENDIAN)
4417         u16 local_port;
4418         u16 remote_port;
4419 #endif
4420 #if defined(__BIG_ENDIAN)
4421         u8 original_nagle_1b;
4422         u8 ts_enabled;
4423         u16 tcp_params;
4424 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0)
4425 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
4426 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8)
4427 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
4428 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9)
4429 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
4430 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10)
4431 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
4432 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11)
4433 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
4434 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12)
4435 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
4436 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13)
4437 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
4438 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14)
4439 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
4440 #elif defined(__LITTLE_ENDIAN)
4441         u16 tcp_params;
4442 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0)
4443 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
4444 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8)
4445 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
4446 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9)
4447 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
4448 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10)
4449 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
4450 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11)
4451 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
4452 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12)
4453 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
4454 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13)
4455 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
4456 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14)
4457 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
4458         u8 ts_enabled;
4459         u8 original_nagle_1b;
4460 #endif
4461 #if defined(__BIG_ENDIAN)
4462         u16 pseudo_csum;
4463         u16 window_scaling_factor;
4464 #elif defined(__LITTLE_ENDIAN)
4465         u16 window_scaling_factor;
4466         u16 pseudo_csum;
4467 #endif
4468 #if defined(__BIG_ENDIAN)
4469         u16 reserved2;
4470         u8 statistics_counter_id;
4471         u8 statistics_params;
4472 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0)
4473 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
4474 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1)
4475 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
4476 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2)
4477 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
4478 #elif defined(__LITTLE_ENDIAN)
4479         u8 statistics_params;
4480 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0)
4481 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
4482 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1)
4483 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
4484 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2)
4485 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
4486         u8 statistics_counter_id;
4487         u16 reserved2;
4488 #endif
4489         u32 ts_time_diff;
4490         u32 __next_timer_expir;
4491 };
4492
4493 /*
4494  * Common context section, shared in TOE, RDMA and ISCSI
4495  */
4496 struct xstorm_common_context_section {
4497         struct xstorm_eth_context_section ethernet;
4498         union xstorm_ip_context_section_types ip_union;
4499         struct xstorm_tcp_context_section tcp;
4500 #if defined(__BIG_ENDIAN)
4501         u8 __dcb_val;
4502         u8 flags;
4503 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0)
4504 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
4505 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1)
4506 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
4507 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4)
4508 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
4509 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5)
4510 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
4511         u8 reserved;
4512         u8 ip_version_1b;
4513 #elif defined(__LITTLE_ENDIAN)
4514         u8 ip_version_1b;
4515         u8 reserved;
4516         u8 flags;
4517 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0)
4518 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
4519 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1)
4520 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
4521 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4)
4522 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
4523 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5)
4524 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
4525         u8 __dcb_val;
4526 #endif
4527 };
4528
4529 /*
4530  * Flags used in ISCSI context section
4531  */
4532 struct xstorm_iscsi_context_flags {
4533         u8 flags;
4534 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0)
4535 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0
4536 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1)
4537 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1
4538 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2)
4539 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2
4540 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3)
4541 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3
4542 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4)
4543 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4
4544 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5)
4545 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5
4546 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6)
4547 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6
4548 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7)
4549 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7
4550 };
4551
4552 struct iscsi_task_context_entry_x {
4553         u32 data_out_buffer_offset;
4554         u32 itt;
4555         u32 data_sn;
4556 };
4557
4558 struct iscsi_task_context_entry_xuc_x_write_only {
4559         u32 tx_r2t_sn;
4560 };
4561
4562 struct iscsi_task_context_entry_xuc_xu_write_both {
4563         u32 sgl_base_lo;
4564         u32 sgl_base_hi;
4565 #if defined(__BIG_ENDIAN)
4566         u8 sgl_size;
4567         u8 sge_index;
4568         u16 sge_offset;
4569 #elif defined(__LITTLE_ENDIAN)
4570         u16 sge_offset;
4571         u8 sge_index;
4572         u8 sgl_size;
4573 #endif
4574 };
4575
4576 /*
4577  * iSCSI context section
4578  */
4579 struct xstorm_iscsi_context_section {
4580         u32 first_burst_length;
4581         u32 max_send_pdu_length;
4582         struct regpair sq_pbl_base;
4583         struct regpair sq_curr_pbe;
4584         struct regpair hq_pbl_base;
4585         struct regpair hq_curr_pbe_base;
4586         struct regpair r2tq_pbl_base;
4587         struct regpair r2tq_curr_pbe_base;
4588         struct regpair task_pbl_base;
4589 #if defined(__BIG_ENDIAN)
4590         u16 data_out_count;
4591         struct xstorm_iscsi_context_flags flags;
4592         u8 task_pbl_cache_idx;
4593 #elif defined(__LITTLE_ENDIAN)
4594         u8 task_pbl_cache_idx;
4595         struct xstorm_iscsi_context_flags flags;
4596         u16 data_out_count;
4597 #endif
4598         u32 seq_more_2_send;
4599         u32 pdu_more_2_send;
4600         struct iscsi_task_context_entry_x temp_tce_x;
4601         struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr;
4602         struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr;
4603         struct regpair lun;
4604         u32 exp_data_transfer_len_ttt;
4605         u32 pdu_data_2_rxmit;
4606         u32 rxmit_bytes_2_dr;
4607 #if defined(__BIG_ENDIAN)
4608         u16 rxmit_sge_offset;
4609         u16 hq_rxmit_cons;
4610 #elif defined(__LITTLE_ENDIAN)
4611         u16 hq_rxmit_cons;
4612         u16 rxmit_sge_offset;
4613 #endif
4614 #if defined(__BIG_ENDIAN)
4615         u16 r2tq_cons;
4616         u8 rxmit_flags;
4617 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0)
4618 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
4619 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1)
4620 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
4621 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2)
4622 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
4623 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3)
4624 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
4625 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4)
4626 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
4627 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5)
4628 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
4629 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7)
4630 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
4631         u8 rxmit_sge_idx;
4632 #elif defined(__LITTLE_ENDIAN)
4633         u8 rxmit_sge_idx;
4634         u8 rxmit_flags;
4635 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0)
4636 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
4637 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1)
4638 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
4639 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2)
4640 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
4641 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3)
4642 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
4643 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4)
4644 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
4645 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5)
4646 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
4647 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7)
4648 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
4649         u16 r2tq_cons;
4650 #endif
4651         u32 hq_rxmit_tcp_seq;
4652 };
4653
4654 /*
4655  * Xstorm iSCSI Storm Context
4656  */
4657 struct xstorm_iscsi_st_context {
4658         struct xstorm_common_context_section common;
4659         struct xstorm_iscsi_context_section iscsi;
4660 };
4661
4662 /*
4663  * Iscsi connection context
4664  */
4665 struct iscsi_context {
4666         struct ustorm_iscsi_st_context ustorm_st_context;
4667         struct tstorm_iscsi_st_context tstorm_st_context;
4668         struct xstorm_iscsi_ag_context xstorm_ag_context;
4669         struct tstorm_iscsi_ag_context tstorm_ag_context;
4670         struct cstorm_iscsi_ag_context cstorm_ag_context;
4671         struct ustorm_iscsi_ag_context ustorm_ag_context;
4672         struct timers_block_context timers_context;
4673         struct regpair upb_context;
4674         struct xstorm_iscsi_st_context xstorm_st_context;
4675         struct regpair xpb_context;
4676         struct cstorm_iscsi_st_context cstorm_st_context;
4677 };
4678
4679
4680 /*
4681  * PDU header of an iSCSI DATA-OUT
4682  */
4683 struct iscsi_data_pdu_hdr_little_endian {
4684 #if defined(__BIG_ENDIAN)
4685         u8 opcode;
4686         u8 op_attr;
4687 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4688 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4689 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
4690 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
4691         u16 rsrv0;
4692 #elif defined(__LITTLE_ENDIAN)
4693         u16 rsrv0;
4694         u8 op_attr;
4695 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4696 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4697 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7)
4698 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
4699         u8 opcode;
4700 #endif
4701         u32 data_fields;
4702 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4703 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4704 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4705 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4706         struct regpair lun;
4707         u32 itt;
4708         u32 ttt;
4709         u32 rsrv2;
4710         u32 exp_stat_sn;
4711         u32 rsrv3;
4712         u32 data_sn;
4713         u32 buffer_offset;
4714         u32 rsrv4;
4715 };
4716
4717
4718 /*
4719  * PDU header of an iSCSI login request
4720  */
4721 struct iscsi_login_req_hdr_little_endian {
4722 #if defined(__BIG_ENDIAN)
4723         u8 opcode;
4724         u8 op_attr;
4725 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0)
4726 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
4727 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2)
4728 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
4729 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4)
4730 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
4731 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4732 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4733 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7)
4734 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
4735         u8 version_max;
4736         u8 version_min;
4737 #elif defined(__LITTLE_ENDIAN)
4738         u8 version_min;
4739         u8 version_max;
4740         u8 op_attr;
4741 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0)
4742 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
4743 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2)
4744 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
4745 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4)
4746 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
4747 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4748 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4749 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7)
4750 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
4751         u8 opcode;
4752 #endif
4753         u32 data_fields;
4754 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4755 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4756 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4757 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4758         u32 isid_lo;
4759 #if defined(__BIG_ENDIAN)
4760         u16 isid_hi;
4761         u16 tsih;
4762 #elif defined(__LITTLE_ENDIAN)
4763         u16 tsih;
4764         u16 isid_hi;
4765 #endif
4766         u32 itt;
4767 #if defined(__BIG_ENDIAN)
4768         u16 cid;
4769         u16 rsrv1;
4770 #elif defined(__LITTLE_ENDIAN)
4771         u16 rsrv1;
4772         u16 cid;
4773 #endif
4774         u32 cmd_sn;
4775         u32 exp_stat_sn;
4776         u32 rsrv2[4];
4777 };
4778
4779 /*
4780  * PDU header of an iSCSI logout request
4781  */
4782 struct iscsi_logout_req_hdr_little_endian {
4783 #if defined(__BIG_ENDIAN)
4784         u8 opcode;
4785         u8 op_attr;
4786 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0)
4787 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
4788 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4789 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4790         u16 rsrv0;
4791 #elif defined(__LITTLE_ENDIAN)
4792         u16 rsrv0;
4793         u8 op_attr;
4794 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0)
4795 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
4796 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4797 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4798         u8 opcode;
4799 #endif
4800         u32 data_fields;
4801 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4802 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4803 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4804 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4805         u32 rsrv2[2];
4806         u32 itt;
4807 #if defined(__BIG_ENDIAN)
4808         u16 cid;
4809         u16 rsrv1;
4810 #elif defined(__LITTLE_ENDIAN)
4811         u16 rsrv1;
4812         u16 cid;
4813 #endif
4814         u32 cmd_sn;
4815         u32 exp_stat_sn;
4816         u32 rsrv3[4];
4817 };
4818
4819 /*
4820  * PDU header of an iSCSI TMF request
4821  */
4822 struct iscsi_tmf_req_hdr_little_endian {
4823 #if defined(__BIG_ENDIAN)
4824         u8 opcode;
4825         u8 op_attr;
4826 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0)
4827 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
4828 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4829 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4830         u16 rsrv0;
4831 #elif defined(__LITTLE_ENDIAN)
4832         u16 rsrv0;
4833         u8 op_attr;
4834 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0)
4835 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
4836 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7)
4837 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
4838         u8 opcode;
4839 #endif
4840         u32 data_fields;
4841 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4842 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4843 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4844 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4845         struct regpair lun;
4846         u32 itt;
4847         u32 referenced_task_tag;
4848         u32 cmd_sn;
4849         u32 exp_stat_sn;
4850         u32 ref_cmd_sn;
4851         u32 exp_data_sn;
4852         u32 rsrv2[2];
4853 };
4854
4855 /*
4856  * PDU header of an iSCSI Text request
4857  */
4858 struct iscsi_text_req_hdr_little_endian {
4859 #if defined(__BIG_ENDIAN)
4860         u8 opcode;
4861         u8 op_attr;
4862 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0)
4863 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4864 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4865 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4866 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7)
4867 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
4868         u16 rsrv0;
4869 #elif defined(__LITTLE_ENDIAN)
4870         u16 rsrv0;
4871         u8 op_attr;
4872 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0)
4873 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4874 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6)
4875 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
4876 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7)
4877 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
4878         u8 opcode;
4879 #endif
4880         u32 data_fields;
4881 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4882 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4883 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4884 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4885         struct regpair lun;
4886         u32 itt;
4887         u32 ttt;
4888         u32 cmd_sn;
4889         u32 exp_stat_sn;
4890         u32 rsrv3[4];
4891 };
4892
4893 /*
4894  * PDU header of an iSCSI Nop-Out
4895  */
4896 struct iscsi_nop_out_hdr_little_endian {
4897 #if defined(__BIG_ENDIAN)
4898         u8 opcode;
4899         u8 op_attr;
4900 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4901 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4902 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7)
4903 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
4904         u16 rsrv0;
4905 #elif defined(__LITTLE_ENDIAN)
4906         u16 rsrv0;
4907         u8 op_attr;
4908 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0)
4909 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
4910 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7)
4911 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
4912         u8 opcode;
4913 #endif
4914         u32 data_fields;
4915 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)
4916 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
4917 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24)
4918 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
4919         struct regpair lun;
4920         u32 itt;
4921         u32 ttt;
4922         u32 cmd_sn;
4923         u32 exp_stat_sn;
4924         u32 rsrv3[4];
4925 };
4926
4927 /*
4928  * iscsi pdu headers in little endian form.
4929  */
4930 union iscsi_pdu_headers_little_endian {
4931         u32 fullHeaderSize[12];
4932         struct iscsi_cmd_pdu_hdr_little_endian command_pdu_hdr;
4933         struct iscsi_data_pdu_hdr_little_endian data_out_pdu_hdr;
4934         struct iscsi_login_req_hdr_little_endian login_req_pdu_hdr;
4935         struct iscsi_logout_req_hdr_little_endian logout_req_pdu_hdr;
4936         struct iscsi_tmf_req_hdr_little_endian tmf_req_pdu_hdr;
4937         struct iscsi_text_req_hdr_little_endian text_req_pdu_hdr;
4938         struct iscsi_nop_out_hdr_little_endian nop_out_pdu_hdr;
4939 };
4940
4941 struct iscsi_hq_bd {
4942         union iscsi_pdu_headers_little_endian pdu_header;
4943 #if defined(__BIG_ENDIAN)
4944         u16 reserved1;
4945         u16 lcl_cmp_flg;
4946 #elif defined(__LITTLE_ENDIAN)
4947         u16 lcl_cmp_flg;
4948         u16 reserved1;
4949 #endif
4950         u32 sgl_base_lo;
4951         u32 sgl_base_hi;
4952 #if defined(__BIG_ENDIAN)
4953         u8 sgl_size;
4954         u8 sge_index;
4955         u16 sge_offset;
4956 #elif defined(__LITTLE_ENDIAN)
4957         u16 sge_offset;
4958         u8 sge_index;
4959         u8 sgl_size;
4960 #endif
4961 };
4962
4963
4964 /*
4965  * CQE data for L2 OOO connection $$KEEP_ENDIANNESS$$
4966  */
4967 struct iscsi_l2_ooo_data {
4968         __le32 iscsi_cid;
4969         u8 drop_isle;
4970         u8 drop_size;
4971         u8 ooo_opcode;
4972         u8 ooo_isle;
4973         u8 reserved[8];
4974 };
4975
4976
4977
4978
4979
4980
4981 struct iscsi_task_context_entry_xuc_c_write_only {
4982         u32 total_data_acked;
4983 };
4984
4985 struct iscsi_task_context_r2t_table_entry {
4986         u32 ttt;
4987         u32 desired_data_len;
4988 };
4989
4990 struct iscsi_task_context_entry_xuc_u_write_only {
4991         u32 exp_r2t_sn;
4992         struct iscsi_task_context_r2t_table_entry r2t_table[4];
4993 #if defined(__BIG_ENDIAN)
4994         u16 data_in_count;
4995         u8 cq_id;
4996         u8 valid_1b;
4997 #elif defined(__LITTLE_ENDIAN)
4998         u8 valid_1b;
4999         u8 cq_id;
5000         u16 data_in_count;
5001 #endif
5002 };
5003
5004 struct iscsi_task_context_entry_xuc {
5005         struct iscsi_task_context_entry_xuc_c_write_only write_c;
5006         u32 exp_data_transfer_len;
5007         struct iscsi_task_context_entry_xuc_x_write_only write_x;
5008         u32 lun_lo;
5009         struct iscsi_task_context_entry_xuc_xu_write_both write_xu;
5010         u32 lun_hi;
5011         struct iscsi_task_context_entry_xuc_u_write_only write_u;
5012 };
5013
5014 struct iscsi_task_context_entry_u {
5015         u32 exp_r2t_buff_offset;
5016         u32 rem_rcv_len;
5017         u32 exp_data_sn;
5018 };
5019
5020 struct iscsi_task_context_entry {
5021         struct iscsi_task_context_entry_x tce_x;
5022 #if defined(__BIG_ENDIAN)
5023         u16 data_out_count;
5024         u16 rsrv0;
5025 #elif defined(__LITTLE_ENDIAN)
5026         u16 rsrv0;
5027         u16 data_out_count;
5028 #endif
5029         struct iscsi_task_context_entry_xuc tce_xuc;
5030         struct iscsi_task_context_entry_u tce_u;
5031         u32 rsrv1[7];
5032 };
5033
5034
5035
5036
5037
5038
5039
5040
5041 struct iscsi_task_context_entry_xuc_x_init_only {
5042         struct regpair lun;
5043         u32 exp_data_transfer_len;
5044 };
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060
5061
5062 /*
5063  * ipv6 structure
5064  */
5065 struct ip_v6_addr {
5066         u32 ip_addr_lo_lo;
5067         u32 ip_addr_lo_hi;
5068         u32 ip_addr_hi_lo;
5069         u32 ip_addr_hi_hi;
5070 };
5071
5072
5073
5074 /*
5075  * l5cm- connection identification params
5076  */
5077 struct l5cm_conn_addr_params {
5078         u32 pmtu;
5079 #if defined(__BIG_ENDIAN)
5080         u8 remote_addr_3;
5081         u8 remote_addr_2;
5082         u8 remote_addr_1;
5083         u8 remote_addr_0;
5084 #elif defined(__LITTLE_ENDIAN)
5085         u8 remote_addr_0;
5086         u8 remote_addr_1;
5087         u8 remote_addr_2;
5088         u8 remote_addr_3;
5089 #endif
5090 #if defined(__BIG_ENDIAN)
5091         u16 params;
5092 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0)
5093 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0
5094 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1)
5095 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1
5096         u8 remote_addr_5;
5097         u8 remote_addr_4;
5098 #elif defined(__LITTLE_ENDIAN)
5099         u8 remote_addr_4;
5100         u8 remote_addr_5;
5101         u16 params;
5102 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0)
5103 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0
5104 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1)
5105 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1
5106 #endif
5107         struct ip_v6_addr local_ip_addr;
5108         struct ip_v6_addr remote_ip_addr;
5109         u32 ipv6_flow_label_20b;
5110         u32 reserved1;
5111 #if defined(__BIG_ENDIAN)
5112         u16 remote_tcp_port;
5113         u16 local_tcp_port;
5114 #elif defined(__LITTLE_ENDIAN)
5115         u16 local_tcp_port;
5116         u16 remote_tcp_port;
5117 #endif
5118 };
5119
5120 /*
5121  * l5cm-xstorm connection buffer
5122  */
5123 struct l5cm_xstorm_conn_buffer {
5124 #if defined(__BIG_ENDIAN)
5125         u16 rsrv1;
5126         u16 params;
5127 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0)
5128 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0
5129 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5130 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1
5131 #elif defined(__LITTLE_ENDIAN)
5132         u16 params;
5133 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0)
5134 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0
5135 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5136 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1
5137         u16 rsrv1;
5138 #endif
5139 #if defined(__BIG_ENDIAN)
5140         u16 mss;
5141         u16 pseudo_header_checksum;
5142 #elif defined(__LITTLE_ENDIAN)
5143         u16 pseudo_header_checksum;
5144         u16 mss;
5145 #endif
5146         u32 rcv_buf;
5147         u32 rsrv2;
5148         struct regpair context_addr;
5149 };
5150
5151 /*
5152  * l5cm-tstorm connection buffer
5153  */
5154 struct l5cm_tstorm_conn_buffer {
5155         u32 rsrv1[2];
5156 #if defined(__BIG_ENDIAN)
5157         u16 params;
5158 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0)
5159 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0
5160 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5161 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1
5162         u8 ka_max_probe_count;
5163         u8 ka_enable;
5164 #elif defined(__LITTLE_ENDIAN)
5165         u8 ka_enable;
5166         u8 ka_max_probe_count;
5167         u16 params;
5168 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0)
5169 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0
5170 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1)
5171 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1
5172 #endif
5173         u32 ka_timeout;
5174         u32 ka_interval;
5175         u32 max_rt_time;
5176 };
5177
5178 /*
5179  * l5cm connection buffer for active side
5180  */
5181 struct l5cm_active_conn_buffer {
5182         struct l5cm_conn_addr_params conn_addr_buf;
5183         struct l5cm_xstorm_conn_buffer xstorm_conn_buffer;
5184         struct l5cm_tstorm_conn_buffer tstorm_conn_buffer;
5185 };
5186
5187
5188
5189 /*
5190  * The l5cm opaque buffer passed in add new connection ramrod passive side
5191  */
5192 struct l5cm_hash_input_string {
5193         u32 __opaque1;
5194 #if defined(__BIG_ENDIAN)
5195         u16 __opaque3;
5196         u16 __opaque2;
5197 #elif defined(__LITTLE_ENDIAN)
5198         u16 __opaque2;
5199         u16 __opaque3;
5200 #endif
5201         struct ip_v6_addr __opaque4;
5202         struct ip_v6_addr __opaque5;
5203         u32 __opaque6;
5204         u32 __opaque7[5];
5205 };
5206
5207
5208 /*
5209  * syn cookie component
5210  */
5211 struct l5cm_syn_cookie_comp {
5212         u32 __opaque;
5213 };
5214
5215 /*
5216  * data related to listeners of a TCP port
5217  */
5218 struct l5cm_port_listener_data {
5219         u8 params;
5220 #define L5CM_PORT_LISTENER_DATA_ENABLE (0x1<<0)
5221 #define L5CM_PORT_LISTENER_DATA_ENABLE_SHIFT 0
5222 #define L5CM_PORT_LISTENER_DATA_IP_INDEX (0xF<<1)
5223 #define L5CM_PORT_LISTENER_DATA_IP_INDEX_SHIFT 1
5224 #define L5CM_PORT_LISTENER_DATA_NET_FILTER (0x1<<5)
5225 #define L5CM_PORT_LISTENER_DATA_NET_FILTER_SHIFT 5
5226 #define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE (0x1<<6)
5227 #define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE_SHIFT 6
5228 #define L5CM_PORT_LISTENER_DATA_MPA_MODE (0x1<<7)
5229 #define L5CM_PORT_LISTENER_DATA_MPA_MODE_SHIFT 7
5230 };
5231
5232 /*
5233  * Opaque structure passed from U to X when final ack arrives
5234  */
5235 struct l5cm_opaque_buf {
5236         u32 __opaque1;
5237         u32 __opaque2;
5238         u32 __opaque3;
5239         u32 __opaque4;
5240         struct l5cm_syn_cookie_comp __opaque5;
5241 #if defined(__BIG_ENDIAN)
5242         u16 rsrv2;
5243         u8 rsrv;
5244         struct l5cm_port_listener_data __opaque6;
5245 #elif defined(__LITTLE_ENDIAN)
5246         struct l5cm_port_listener_data __opaque6;
5247         u8 rsrv;
5248         u16 rsrv2;
5249 #endif
5250 };
5251
5252
5253 /*
5254  * l5cm slow path element
5255  */
5256 struct l5cm_packet_size {
5257         u32 size;
5258         u32 rsrv;
5259 };
5260
5261
5262 /*
5263  * The final-ack union structure in PCS entry after final ack arrived
5264  */
5265 struct l5cm_pcse_ack {
5266         struct l5cm_xstorm_conn_buffer tx_socket_params;
5267         struct l5cm_opaque_buf opaque_buf;
5268         struct l5cm_tstorm_conn_buffer rx_socket_params;
5269 };
5270
5271
5272 /*
5273  * The syn union structure in PCS entry after syn arrived
5274  */
5275 struct l5cm_pcse_syn {
5276         struct l5cm_opaque_buf opaque_buf;
5277         u32 rsrv[12];
5278 };
5279
5280
5281 /*
5282  * pcs entry data for passive connections
5283  */
5284 struct l5cm_pcs_attributes {
5285 #if defined(__BIG_ENDIAN)
5286         u16 pcs_id;
5287         u8 status;
5288         u8 flags;
5289 #define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0)
5290 #define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0
5291 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1)
5292 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1
5293 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2)
5294 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2
5295 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3)
5296 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3
5297 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4)
5298 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4
5299 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5)
5300 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5
5301 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6)
5302 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6
5303 #define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7)
5304 #define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7
5305 #elif defined(__LITTLE_ENDIAN)
5306         u8 flags;
5307 #define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0)
5308 #define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0
5309 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1)
5310 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1
5311 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2)
5312 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2
5313 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3)
5314 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3
5315 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4)
5316 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4
5317 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5)
5318 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5
5319 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6)
5320 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6
5321 #define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7)
5322 #define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7
5323         u8 status;
5324         u16 pcs_id;
5325 #endif
5326 };
5327
5328
5329 union l5cm_seg_params {
5330         struct l5cm_pcse_syn syn_seg_params;
5331         struct l5cm_pcse_ack ack_seg_params;
5332 };
5333
5334 /*
5335  * pcs entry data for passive connections
5336  */
5337 struct l5cm_pcs_hdr {
5338         struct l5cm_hash_input_string hash_input_string;
5339         struct l5cm_conn_addr_params conn_addr_buf;
5340         u32 cid;
5341         u32 hash_result;
5342         union l5cm_seg_params seg_params;
5343         struct l5cm_pcs_attributes att;
5344 #if defined(__BIG_ENDIAN)
5345         u16 rsrv;
5346         u16 rx_seg_size;
5347 #elif defined(__LITTLE_ENDIAN)
5348         u16 rx_seg_size;
5349         u16 rsrv;
5350 #endif
5351 };
5352
5353 /*
5354  * pcs entry for passive connections
5355  */
5356 struct l5cm_pcs_entry {
5357         struct l5cm_pcs_hdr hdr;
5358         u8 rx_segment[1516];
5359 };
5360
5361
5362
5363
5364 /*
5365  * l5cm connection parameters
5366  */
5367 union l5cm_reduce_param_union {
5368         u32 opaque1;
5369         u32 opaque2;
5370 };
5371
5372 /*
5373  * l5cm connection parameters
5374  */
5375 struct l5cm_reduce_conn {
5376         union l5cm_reduce_param_union opaque1;
5377         u32 opaque2;
5378 };
5379
5380 /*
5381  * l5cm slow path element
5382  */
5383 union l5cm_specific_data {
5384         u8 protocol_data[8];
5385         struct regpair phy_address;
5386         struct l5cm_packet_size packet_size;
5387         struct l5cm_reduce_conn reduced_conn;
5388 };
5389
5390 /*
5391  * l5 slow path element
5392  */
5393 struct l5cm_spe {
5394         struct spe_hdr hdr;
5395         union l5cm_specific_data data;
5396 };
5397
5398
5399
5400
5401 /*
5402  * Termination variables
5403  */
5404 struct l5cm_term_vars {
5405         u8 BitMap;
5406 #define L5CM_TERM_VARS_TCP_STATE (0xF<<0)
5407 #define L5CM_TERM_VARS_TCP_STATE_SHIFT 0
5408 #define L5CM_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4)
5409 #define L5CM_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4
5410 #define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5)
5411 #define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5
5412 #define L5CM_TERM_VARS_TERM_ON_CHIP (0x1<<6)
5413 #define L5CM_TERM_VARS_TERM_ON_CHIP_SHIFT 6
5414 #define L5CM_TERM_VARS_RSRV (0x1<<7)
5415 #define L5CM_TERM_VARS_RSRV_SHIFT 7
5416 };
5417
5418
5419
5420
5421 /*
5422  * Tstorm Tcp flags
5423  */
5424 struct tstorm_l5cm_tcp_flags {
5425         u16 flags;
5426 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0)
5427 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0
5428 #define TSTORM_L5CM_TCP_FLAGS_RSRV0 (0x1<<12)
5429 #define TSTORM_L5CM_TCP_FLAGS_RSRV0_SHIFT 12
5430 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13)
5431 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13
5432 #define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14)
5433 #define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14
5434 };
5435
5436
5437 /*
5438  * Xstorm Tcp flags
5439  */
5440 struct xstorm_l5cm_tcp_flags {
5441         u8 flags;
5442 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED (0x1<<0)
5443 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED_SHIFT 0
5444 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<1)
5445 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 1
5446 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN (0x1<<2)
5447 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN_SHIFT 2
5448 #define XSTORM_L5CM_TCP_FLAGS_RSRV (0x1F<<3)
5449 #define XSTORM_L5CM_TCP_FLAGS_RSRV_SHIFT 3
5450 };
5451
5452
5453
5454 /*
5455  * Out-of-order states
5456  */
5457 enum tcp_ooo_event {
5458         TCP_EVENT_ADD_PEN = 0,
5459         TCP_EVENT_ADD_NEW_ISLE = 1,
5460         TCP_EVENT_ADD_ISLE_RIGHT = 2,
5461         TCP_EVENT_ADD_ISLE_LEFT = 3,
5462         TCP_EVENT_JOIN = 4,
5463         TCP_EVENT_NOP = 5,
5464         MAX_TCP_OOO_EVENT
5465 };
5466
5467
5468 /*
5469  * OOO support modes
5470  */
5471 enum tcp_tstorm_ooo {
5472         TCP_TSTORM_OOO_DROP_AND_PROC_ACK = 0,
5473         TCP_TSTORM_OOO_SEND_PURE_ACK = 1,
5474         TCP_TSTORM_OOO_SUPPORTED = 2,
5475         MAX_TCP_TSTORM_OOO
5476 };
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486 #endif /* __5710_HSI_CNIC_LE__ */