Pileus Git - ~andy/linux/blob - drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2012 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_vfpf.h"
  63 #include "bnx2x_sriov.h"
  64 #include "bnx2x_dcb.h"
  65 #include "bnx2x_sp.h"
  66
  67 #include <linux/firmware.h>
  68 #include "bnx2x_fw_file_hdr.h"
  69 /* FW files */
  70 #define FW_FILE_VERSION                                 \
  71         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  73         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  74         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  75 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  77 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  78
  79 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
  80
  81 /* Time in jiffies before concluding the transmitter is hung */
  82 #define TX_TIMEOUT              (5*HZ)
  83
  84 static char version[] =
  85         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  86         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  87
  88 MODULE_AUTHOR("Eliezer Tamir");
  89 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  90                    "BCM57710/57711/57711E/"
  91                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  92                    "57840/57840_MF Driver");
  93 MODULE_LICENSE("GPL");
  94 MODULE_VERSION(DRV_MODULE_VERSION);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  97 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  98
  99
 100 int num_queues;
 101 module_param(num_queues, int, 0);
 102 MODULE_PARM_DESC(num_queues,
 103                  " Set number of queues (default is as a number of CPUs)");
 104
 105 static int disable_tpa;
 106 module_param(disable_tpa, int, 0);
 107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 108
 109 #define INT_MODE_INTx                   1
 110 #define INT_MODE_MSI                    2
 111 int int_mode;
 112 module_param(int_mode, int, 0);
 113 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 114                                 "(1 INT#x; 2 MSI)");
 115
 116 static int dropless_fc;
 117 module_param(dropless_fc, int, 0);
 118 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 119
 120 static int mrrs = -1;
 121 module_param(mrrs, int, 0);
 122 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 123
 124 static int debug;
 125 module_param(debug, int, 0);
 126 MODULE_PARM_DESC(debug, " Default debug msglevel");
 127
 128
 129
 130 struct workqueue_struct *bnx2x_wq;
 131
 132 enum bnx2x_board_type {
 133         BCM57710 = 0,
 134         BCM57711,
 135         BCM57711E,
 136         BCM57712,
 137         BCM57712_MF,
 138         BCM57712_VF,
 139         BCM57800,
 140         BCM57800_MF,
 141         BCM57800_VF,
 142         BCM57810,
 143         BCM57810_MF,
 144         BCM57810_VF,
 145         BCM57840_4_10,
 146         BCM57840_2_20,
 147         BCM57840_MF,
 148         BCM57840_VF,
 149         BCM57811,
 150         BCM57811_MF,
 151         BCM57840_O,
 152         BCM57840_MFO,
 153         BCM57811_VF
 154 };
 155
 156 /* indexed by board_type, above */
 157 static struct {
 158         char *name;
 159 } board_info[] = {
 160         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 161         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 162         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 163         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 164         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 165         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 166         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 167         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 168         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 169         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 170         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 171         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 173         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 174         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 175         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 176         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 177         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 178         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 179         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 180         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 181 };
 182
 183 #ifndef PCI_DEVICE_ID_NX2_57710
 184 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 185 #endif
 186 #ifndef PCI_DEVICE_ID_NX2_57711
 187 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 188 #endif
 189 #ifndef PCI_DEVICE_ID_NX2_57711E
 190 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57712
 193 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 196 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 199 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57800
 202 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 205 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 208 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57810
 211 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 214 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57840_O
 217 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 220 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 223 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 226 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 229 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 230 #endif
 231 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 232 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 233 #endif
 234 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 235 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 236 #endif
 237 #ifndef PCI_DEVICE_ID_NX2_57811
 238 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 239 #endif
 240 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 241 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 242 #endif
 243 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 244 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 245 #endif
 246
 247 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 248         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 249         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 250         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 251         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 269         { 0 }
 270 };
 271
 272 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 273
 274 /* Global resources for unloading a previously loaded device */
 275 #define BNX2X_PREV_WAIT_NEEDED 1
 276 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 277 static LIST_HEAD(bnx2x_prev_list);
 278 /****************************************************************************
 279 * General service functions
 280 ****************************************************************************/
 281
 282 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 283                                        u32 addr, dma_addr_t mapping)
 284 {
 285         REG_WR(bp,  addr, U64_LO(mapping));
 286         REG_WR(bp,  addr + 4, U64_HI(mapping));
 287 }
 288
 289 static void storm_memset_spq_addr(struct bnx2x *bp,
 290                                   dma_addr_t mapping, u16 abs_fid)
 291 {
 292         u32 addr = XSEM_REG_FAST_MEMORY +
 293                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 294
 295         __storm_memset_dma_mapping(bp, addr, mapping);
 296 }
 297
 298 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 299                                   u16 pf_id)
 300 {
 301         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 302                 pf_id);
 303         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 304                 pf_id);
 305         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 306                 pf_id);
 307         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 308                 pf_id);
 309 }
 310
 311 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 312                                  u8 enable)
 313 {
 314         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 315                 enable);
 316         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 317                 enable);
 318         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 319                 enable);
 320         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 321                 enable);
 322 }
 323
 324 static void storm_memset_eq_data(struct bnx2x *bp,
 325                                  struct event_ring_data *eq_data,
 326                                 u16 pfid)
 327 {
 328         size_t size = sizeof(struct event_ring_data);
 329
 330         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 331
 332         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 333 }
 334
 335 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 336                                  u16 pfid)
 337 {
 338         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 339         REG_WR16(bp, addr, eq_prod);
 340 }
 341
 342 /* used only at init
 343  * locking is done by mcp
 344  */
 345 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 346 {
 347         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 348         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 349         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 350                                PCICFG_VENDOR_ID_OFFSET);
 351 }
 352
 353 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 354 {
 355         u32 val;
 356
 357         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 358         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 359         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 360                                PCICFG_VENDOR_ID_OFFSET);
 361
 362         return val;
 363 }
 364
 365 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 366 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 367 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 368 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 369 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 370
 371 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
 372 {
 373         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 374
 375         switch (dmae->opcode & DMAE_COMMAND_DST) {
 376         case DMAE_CMD_DST_PCI:
 377                 if (src_type == DMAE_CMD_SRC_PCI)
 378                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 379                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 380                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 381                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 382                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 383                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 384                            dmae->comp_val);
 385                 else
 386                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 387                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 388                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 389                            dmae->opcode, dmae->src_addr_lo >> 2,
 390                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 391                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 392                            dmae->comp_val);
 393                 break;
 394         case DMAE_CMD_DST_GRC:
 395                 if (src_type == DMAE_CMD_SRC_PCI)
 396                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 397                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 398                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 399                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 400                            dmae->len, dmae->dst_addr_lo >> 2,
 401                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 402                            dmae->comp_val);
 403                 else
 404                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 405                            "src [%08x], len [%d*4], dst [%08x]\n"
 406                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 407                            dmae->opcode, dmae->src_addr_lo >> 2,
 408                            dmae->len, dmae->dst_addr_lo >> 2,
 409                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 410                            dmae->comp_val);
 411                 break;
 412         default:
 413                 if (src_type == DMAE_CMD_SRC_PCI)
 414                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 415                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 416                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 417                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 418                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 419                            dmae->comp_val);
 420                 else
 421                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 422                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 423                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 424                            dmae->opcode, dmae->src_addr_lo >> 2,
 425                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 426                            dmae->comp_val);
 427                 break;
 428         }
 429 }
 430
 431 /* copy command into DMAE command memory and set DMAE command go */
 432 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 433 {
 434         u32 cmd_offset;
 435         int i;
 436
 437         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 438         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 439                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 440         }
 441         REG_WR(bp, dmae_reg_go_c[idx], 1);
 442 }
 443
 444 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 445 {
 446         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 447                            DMAE_CMD_C_ENABLE);
 448 }
 449
 450 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 451 {
 452         return opcode & ~DMAE_CMD_SRC_RESET;
 453 }
 454
 455 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 456                              bool with_comp, u8 comp_type)
 457 {
 458         u32 opcode = 0;
 459
 460         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 461                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 462
 463         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 464
 465         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 466         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 467                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 468         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 469
 470 #ifdef __BIG_ENDIAN
 471         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 472 #else
 473         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 474 #endif
 475         if (with_comp)
 476                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 477         return opcode;
 478 }
 479
 480 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 481                                       struct dmae_command *dmae,
 482                                       u8 src_type, u8 dst_type)
 483 {
 484         memset(dmae, 0, sizeof(struct dmae_command));
 485
 486         /* set the opcode */
 487         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 488                                          true, DMAE_COMP_PCI);
 489
 490         /* fill in the completion parameters */
 491         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 492         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 493         dmae->comp_val = DMAE_COMP_VAL;
 494 }
 495
 496 /* issue a dmae command over the init-channel and wait for completion */
 497 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
 498 {
 499         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 500         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 501         int rc = 0;
 502
 503         /*
 504          * Lock the dmae channel. Disable BHs to prevent a dead-lock
 505          * as long as this code is called both from syscall context and
 506          * from ndo_set_rx_mode() flow that may be called from BH.
 507          */
 508         spin_lock_bh(&bp->dmae_lock);
 509
 510         /* reset completion */
 511         *wb_comp = 0;
 512
 513         /* post the command on the channel used for initializations */
 514         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 515
 516         /* wait for completion */
 517         udelay(5);
 518         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 519
 520                 if (!cnt ||
 521                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 522                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 523                         BNX2X_ERR("DMAE timeout!\n");
 524                         rc = DMAE_TIMEOUT;
 525                         goto unlock;
 526                 }
 527                 cnt--;
 528                 udelay(50);
 529         }
 530         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 531                 BNX2X_ERR("DMAE PCI error!\n");
 532                 rc = DMAE_PCI_ERROR;
 533         }
 534
 535 unlock:
 536         spin_unlock_bh(&bp->dmae_lock);
 537         return rc;
 538 }
 539
 540 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 541                       u32 len32)
 542 {
 543         struct dmae_command dmae;
 544
 545         if (!bp->dmae_ready) {
 546                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 547
 548                 if (CHIP_IS_E1(bp))
 549                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 550                 else
 551                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 552                 return;
 553         }
 554
 555         /* set opcode and fixed command fields */
 556         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 557
 558         /* fill in addresses and len */
 559         dmae.src_addr_lo = U64_LO(dma_addr);
 560         dmae.src_addr_hi = U64_HI(dma_addr);
 561         dmae.dst_addr_lo = dst_addr >> 2;
 562         dmae.dst_addr_hi = 0;
 563         dmae.len = len32;
 564
 565         /* issue the command and wait for completion */
 566         bnx2x_issue_dmae_with_comp(bp, &dmae);
 567 }
 568
 569 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 570 {
 571         struct dmae_command dmae;
 572
 573         if (!bp->dmae_ready) {
 574                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 575                 int i;
 576
 577                 if (CHIP_IS_E1(bp))
 578                         for (i = 0; i < len32; i++)
 579                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 580                 else
 581                         for (i = 0; i < len32; i++)
 582                                 data[i] = REG_RD(bp, src_addr + i*4);
 583
 584                 return;
 585         }
 586
 587         /* set opcode and fixed command fields */
 588         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 589
 590         /* fill in addresses and len */
 591         dmae.src_addr_lo = src_addr >> 2;
 592         dmae.src_addr_hi = 0;
 593         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 594         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 595         dmae.len = len32;
 596
 597         /* issue the command and wait for completion */
 598         bnx2x_issue_dmae_with_comp(bp, &dmae);
 599 }
 600
 601 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 602                                       u32 addr, u32 len)
 603 {
 604         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 605         int offset = 0;
 606
 607         while (len > dmae_wr_max) {
 608                 bnx2x_write_dmae(bp, phys_addr + offset,
 609                                  addr + offset, dmae_wr_max);
 610                 offset += dmae_wr_max * 4;
 611                 len -= dmae_wr_max;
 612         }
 613
 614         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 615 }
 616
 617 static int bnx2x_mc_assert(struct bnx2x *bp)
 618 {
 619         char last_idx;
 620         int i, rc = 0;
 621         u32 row0, row1, row2, row3;
 622
 623         /* XSTORM */
 624         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 625                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 626         if (last_idx)
 627                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 628
 629         /* print the asserts */
 630         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 631
 632                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 633                               XSTORM_ASSERT_LIST_OFFSET(i));
 634                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 635                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 636                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 637                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 638                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 639                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 640
 641                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 642                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 643                                   i, row3, row2, row1, row0);
 644                         rc++;
 645                 } else {
 646                         break;
 647                 }
 648         }
 649
 650         /* TSTORM */
 651         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 652                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 653         if (last_idx)
 654                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 655
 656         /* print the asserts */
 657         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 658
 659                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 660                               TSTORM_ASSERT_LIST_OFFSET(i));
 661                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 662                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 663                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 664                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 665                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 666                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 667
 668                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 669                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 670                                   i, row3, row2, row1, row0);
 671                         rc++;
 672                 } else {
 673                         break;
 674                 }
 675         }
 676
 677         /* CSTORM */
 678         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 679                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 680         if (last_idx)
 681                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 682
 683         /* print the asserts */
 684         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 685
 686                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 687                               CSTORM_ASSERT_LIST_OFFSET(i));
 688                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 689                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 690                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 691                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 692                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 693                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 694
 695                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 696                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 697                                   i, row3, row2, row1, row0);
 698                         rc++;
 699                 } else {
 700                         break;
 701                 }
 702         }
 703
 704         /* USTORM */
 705         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 706                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 707         if (last_idx)
 708                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 709
 710         /* print the asserts */
 711         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 712
 713                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 714                               USTORM_ASSERT_LIST_OFFSET(i));
 715                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 716                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 717                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 718                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 719                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 720                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 721
 722                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 723                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 724                                   i, row3, row2, row1, row0);
 725                         rc++;
 726                 } else {
 727                         break;
 728                 }
 729         }
 730
 731         return rc;
 732 }
 733
 734 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 735 {
 736         u32 addr, val;
 737         u32 mark, offset;
 738         __be32 data[9];
 739         int word;
 740         u32 trace_shmem_base;
 741         if (BP_NOMCP(bp)) {
 742                 BNX2X_ERR("NO MCP - can not dump\n");
 743                 return;
 744         }
 745         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 746                 (bp->common.bc_ver & 0xff0000) >> 16,
 747                 (bp->common.bc_ver & 0xff00) >> 8,
 748                 (bp->common.bc_ver & 0xff));
 749
 750         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 751         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 752                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 753
 754         if (BP_PATH(bp) == 0)
 755                 trace_shmem_base = bp->common.shmem_base;
 756         else
 757                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 758         addr = trace_shmem_base - 0x800;
 759
 760         /* validate TRCB signature */
 761         mark = REG_RD(bp, addr);
 762         if (mark != MFW_TRACE_SIGNATURE) {
 763                 BNX2X_ERR("Trace buffer signature is missing.");
 764                 return ;
 765         }
 766
 767         /* read cyclic buffer pointer */
 768         addr += 4;
 769         mark = REG_RD(bp, addr);
 770         mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
 771                         + ((mark + 0x3) & ~0x3) - 0x08000000;
 772         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 773
 774         printk("%s", lvl);
 775         for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
 776                 for (word = 0; word < 8; word++)
 777                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 778                 data[8] = 0x0;
 779                 pr_cont("%s", (char *)data);
 780         }
 781         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 782                 for (word = 0; word < 8; word++)
 783                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 784                 data[8] = 0x0;
 785                 pr_cont("%s", (char *)data);
 786         }
 787         printk("%s" "end of fw dump\n", lvl);
 788 }
 789
 790 static void bnx2x_fw_dump(struct bnx2x *bp)
 791 {
 792         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 793 }
 794
 795 void bnx2x_panic_dump(struct bnx2x *bp)
 796 {
 797         int i;
 798         u16 j;
 799         struct hc_sp_status_block_data sp_sb_data;
 800         int func = BP_FUNC(bp);
 801 #ifdef BNX2X_STOP_ON_ERROR
 802         u16 start = 0, end = 0;
 803         u8 cos;
 804 #endif
 805
 806         bp->stats_state = STATS_STATE_DISABLED;
 807         bp->eth_stats.unrecoverable_error++;
 808         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 809
 810         BNX2X_ERR("begin crash dump -----------------\n");
 811
 812         /* Indices */
 813         /* Common */
 814         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 815                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 816                   bp->spq_prod_idx, bp->stats_counter);
 817         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 818                   bp->def_status_blk->atten_status_block.attn_bits,
 819                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 820                   bp->def_status_blk->atten_status_block.status_block_id,
 821                   bp->def_status_blk->atten_status_block.attn_bits_index);
 822         BNX2X_ERR("     def (");
 823         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 824                 pr_cont("0x%x%s",
 825                         bp->def_status_blk->sp_sb.index_values[i],
 826                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 827
 828         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 829                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 830                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 831                         i*sizeof(u32));
 832
 833         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 834                sp_sb_data.igu_sb_id,
 835                sp_sb_data.igu_seg_id,
 836                sp_sb_data.p_func.pf_id,
 837                sp_sb_data.p_func.vnic_id,
 838                sp_sb_data.p_func.vf_id,
 839                sp_sb_data.p_func.vf_valid,
 840                sp_sb_data.state);
 841
 842
 843         for_each_eth_queue(bp, i) {
 844                 struct bnx2x_fastpath *fp = &bp->fp[i];
 845                 int loop;
 846                 struct hc_status_block_data_e2 sb_data_e2;
 847                 struct hc_status_block_data_e1x sb_data_e1x;
 848                 struct hc_status_block_sm  *hc_sm_p =
 849                         CHIP_IS_E1x(bp) ?
 850                         sb_data_e1x.common.state_machine :
 851                         sb_data_e2.common.state_machine;
 852                 struct hc_index_data *hc_index_p =
 853                         CHIP_IS_E1x(bp) ?
 854                         sb_data_e1x.index_data :
 855                         sb_data_e2.index_data;
 856                 u8 data_size, cos;
 857                 u32 *sb_data_p;
 858                 struct bnx2x_fp_txdata txdata;
 859
 860                 /* Rx */
 861                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 862                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 863                           fp->rx_comp_prod,
 864                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 865                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 866                           fp->rx_sge_prod, fp->last_max_sge,
 867                           le16_to_cpu(fp->fp_hc_idx));
 868
 869                 /* Tx */
 870                 for_each_cos_in_tx_queue(fp, cos)
 871                 {
 872                         txdata = *fp->txdata_ptr[cos];
 873                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 874                                   i, txdata.tx_pkt_prod,
 875                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 876                                   txdata.tx_bd_cons,
 877                                   le16_to_cpu(*txdata.tx_cons_sb));
 878                 }
 879
 880                 loop = CHIP_IS_E1x(bp) ?
 881                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 882
 883                 /* host sb data */
 884
 885                 if (IS_FCOE_FP(fp))
 886                         continue;
 887
 888                 BNX2X_ERR("     run indexes (");
 889                 for (j = 0; j < HC_SB_MAX_SM; j++)
 890                         pr_cont("0x%x%s",
 891                                fp->sb_running_index[j],
 892                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 893
 894                 BNX2X_ERR("     indexes (");
 895                 for (j = 0; j < loop; j++)
 896                         pr_cont("0x%x%s",
 897                                fp->sb_index_values[j],
 898                                (j == loop - 1) ? ")" : " ");
 899                 /* fw sb data */
 900                 data_size = CHIP_IS_E1x(bp) ?
 901                         sizeof(struct hc_status_block_data_e1x) :
 902                         sizeof(struct hc_status_block_data_e2);
 903                 data_size /= sizeof(u32);
 904                 sb_data_p = CHIP_IS_E1x(bp) ?
 905                         (u32 *)&sb_data_e1x :
 906                         (u32 *)&sb_data_e2;
 907                 /* copy sb data in here */
 908                 for (j = 0; j < data_size; j++)
 909                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 910                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
 911                                 j * sizeof(u32));
 912
 913                 if (!CHIP_IS_E1x(bp)) {
 914                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 915                                 sb_data_e2.common.p_func.pf_id,
 916                                 sb_data_e2.common.p_func.vf_id,
 917                                 sb_data_e2.common.p_func.vf_valid,
 918                                 sb_data_e2.common.p_func.vnic_id,
 919                                 sb_data_e2.common.same_igu_sb_1b,
 920                                 sb_data_e2.common.state);
 921                 } else {
 922                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 923                                 sb_data_e1x.common.p_func.pf_id,
 924                                 sb_data_e1x.common.p_func.vf_id,
 925                                 sb_data_e1x.common.p_func.vf_valid,
 926                                 sb_data_e1x.common.p_func.vnic_id,
 927                                 sb_data_e1x.common.same_igu_sb_1b,
 928                                 sb_data_e1x.common.state);
 929                 }
 930
 931                 /* SB_SMs data */
 932                 for (j = 0; j < HC_SB_MAX_SM; j++) {
 933                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
 934                                 j, hc_sm_p[j].__flags,
 935                                 hc_sm_p[j].igu_sb_id,
 936                                 hc_sm_p[j].igu_seg_id,
 937                                 hc_sm_p[j].time_to_expire,
 938                                 hc_sm_p[j].timer_value);
 939                 }
 940
 941                 /* Indecies data */
 942                 for (j = 0; j < loop; j++) {
 943                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
 944                                hc_index_p[j].flags,
 945                                hc_index_p[j].timeout);
 946                 }
 947         }
 948
 949 #ifdef BNX2X_STOP_ON_ERROR
 950         /* Rings */
 951         /* Rx */
 952         for_each_valid_rx_queue(bp, i) {
 953                 struct bnx2x_fastpath *fp = &bp->fp[i];
 954
 955                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
 956                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
 957                 for (j = start; j != end; j = RX_BD(j + 1)) {
 958                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
 959                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
 960
 961                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
 962                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
 963                 }
 964
 965                 start = RX_SGE(fp->rx_sge_prod);
 966                 end = RX_SGE(fp->last_max_sge);
 967                 for (j = start; j != end; j = RX_SGE(j + 1)) {
 968                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
 969                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
 970
 971                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
 972                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
 973                 }
 974
 975                 start = RCQ_BD(fp->rx_comp_cons - 10);
 976                 end = RCQ_BD(fp->rx_comp_cons + 503);
 977                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
 978                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
 979
 980                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
 981                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
 982                 }
 983         }
 984
 985         /* Tx */
 986         for_each_valid_tx_queue(bp, i) {
 987                 struct bnx2x_fastpath *fp = &bp->fp[i];
 988                 for_each_cos_in_tx_queue(fp, cos) {
 989                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
 990
 991                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
 992                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
 993                         for (j = start; j != end; j = TX_BD(j + 1)) {
 994                                 struct sw_tx_bd *sw_bd =
 995                                         &txdata->tx_buf_ring[j];
 996
 997                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
 998                                           i, cos, j, sw_bd->skb,
 999                                           sw_bd->first_bd);
1000                         }
1001
1002                         start = TX_BD(txdata->tx_bd_cons - 10);
1003                         end = TX_BD(txdata->tx_bd_cons + 254);
1004                         for (j = start; j != end; j = TX_BD(j + 1)) {
1005                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1006
1007                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1008                                           i, cos, j, tx_bd[0], tx_bd[1],
1009                                           tx_bd[2], tx_bd[3]);
1010                         }
1011                 }
1012         }
1013 #endif
1014         bnx2x_fw_dump(bp);
1015         bnx2x_mc_assert(bp);
1016         BNX2X_ERR("end crash dump -----------------\n");
1017 }
1018
1019 /*
1020  * FLR Support for E2
1021  *
1022  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1023  * initialization.
1024  */
1025 #define FLR_WAIT_USEC           10000   /* 10 miliseconds */
1026 #define FLR_WAIT_INTERVAL       50      /* usec */
1027 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1028
1029 struct pbf_pN_buf_regs {
1030         int pN;
1031         u32 init_crd;
1032         u32 crd;
1033         u32 crd_freed;
1034 };
1035
1036 struct pbf_pN_cmd_regs {
1037         int pN;
1038         u32 lines_occup;
1039         u32 lines_freed;
1040 };
1041
1042 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1043                                      struct pbf_pN_buf_regs *regs,
1044                                      u32 poll_count)
1045 {
1046         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1047         u32 cur_cnt = poll_count;
1048
1049         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1050         crd = crd_start = REG_RD(bp, regs->crd);
1051         init_crd = REG_RD(bp, regs->init_crd);
1052
1053         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1054         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1055         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1056
1057         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1058                (init_crd - crd_start))) {
1059                 if (cur_cnt--) {
1060                         udelay(FLR_WAIT_INTERVAL);
1061                         crd = REG_RD(bp, regs->crd);
1062                         crd_freed = REG_RD(bp, regs->crd_freed);
1063                 } else {
1064                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1065                            regs->pN);
1066                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1067                            regs->pN, crd);
1068                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1069                            regs->pN, crd_freed);
1070                         break;
1071                 }
1072         }
1073         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1074            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1075 }
1076
1077 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1078                                      struct pbf_pN_cmd_regs *regs,
1079                                      u32 poll_count)
1080 {
1081         u32 occup, to_free, freed, freed_start;
1082         u32 cur_cnt = poll_count;
1083
1084         occup = to_free = REG_RD(bp, regs->lines_occup);
1085         freed = freed_start = REG_RD(bp, regs->lines_freed);
1086
1087         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1088         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1089
1090         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1091                 if (cur_cnt--) {
1092                         udelay(FLR_WAIT_INTERVAL);
1093                         occup = REG_RD(bp, regs->lines_occup);
1094                         freed = REG_RD(bp, regs->lines_freed);
1095                 } else {
1096                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1097                            regs->pN);
1098                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1099                            regs->pN, occup);
1100                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1101                            regs->pN, freed);
1102                         break;
1103                 }
1104         }
1105         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1106            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1107 }
1108
1109 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1110                                     u32 expected, u32 poll_count)
1111 {
1112         u32 cur_cnt = poll_count;
1113         u32 val;
1114
1115         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1116                 udelay(FLR_WAIT_INTERVAL);
1117
1118         return val;
1119 }
1120
1121 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1122                                     char *msg, u32 poll_cnt)
1123 {
1124         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1125         if (val != 0) {
1126                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1127                 return 1;
1128         }
1129         return 0;
1130 }
1131
1132 /* Common routines with VF FLR cleanup */
1133 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1134 {
1135         /* adjust polling timeout */
1136         if (CHIP_REV_IS_EMUL(bp))
1137                 return FLR_POLL_CNT * 2000;
1138
1139         if (CHIP_REV_IS_FPGA(bp))
1140                 return FLR_POLL_CNT * 120;
1141
1142         return FLR_POLL_CNT;
1143 }
1144
1145 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1146 {
1147         struct pbf_pN_cmd_regs cmd_regs[] = {
1148                 {0, (CHIP_IS_E3B0(bp)) ?
1149                         PBF_REG_TQ_OCCUPANCY_Q0 :
1150                         PBF_REG_P0_TQ_OCCUPANCY,
1151                     (CHIP_IS_E3B0(bp)) ?
1152                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1153                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1154                 {1, (CHIP_IS_E3B0(bp)) ?
1155                         PBF_REG_TQ_OCCUPANCY_Q1 :
1156                         PBF_REG_P1_TQ_OCCUPANCY,
1157                     (CHIP_IS_E3B0(bp)) ?
1158                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1159                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1160                 {4, (CHIP_IS_E3B0(bp)) ?
1161                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1162                         PBF_REG_P4_TQ_OCCUPANCY,
1163                     (CHIP_IS_E3B0(bp)) ?
1164                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1165                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1166         };
1167
1168         struct pbf_pN_buf_regs buf_regs[] = {
1169                 {0, (CHIP_IS_E3B0(bp)) ?
1170                         PBF_REG_INIT_CRD_Q0 :
1171                         PBF_REG_P0_INIT_CRD ,
1172                     (CHIP_IS_E3B0(bp)) ?
1173                         PBF_REG_CREDIT_Q0 :
1174                         PBF_REG_P0_CREDIT,
1175                     (CHIP_IS_E3B0(bp)) ?
1176                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1177                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1178                 {1, (CHIP_IS_E3B0(bp)) ?
1179                         PBF_REG_INIT_CRD_Q1 :
1180                         PBF_REG_P1_INIT_CRD,
1181                     (CHIP_IS_E3B0(bp)) ?
1182                         PBF_REG_CREDIT_Q1 :
1183                         PBF_REG_P1_CREDIT,
1184                     (CHIP_IS_E3B0(bp)) ?
1185                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1186                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1187                 {4, (CHIP_IS_E3B0(bp)) ?
1188                         PBF_REG_INIT_CRD_LB_Q :
1189                         PBF_REG_P4_INIT_CRD,
1190                     (CHIP_IS_E3B0(bp)) ?
1191                         PBF_REG_CREDIT_LB_Q :
1192                         PBF_REG_P4_CREDIT,
1193                     (CHIP_IS_E3B0(bp)) ?
1194                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1195                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1196         };
1197
1198         int i;
1199
1200         /* Verify the command queues are flushed P0, P1, P4 */
1201         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1202                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1203
1204
1205         /* Verify the transmission buffers are flushed P0, P1, P4 */
1206         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1207                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1208 }
1209
1210 #define OP_GEN_PARAM(param) \
1211         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1212
1213 #define OP_GEN_TYPE(type) \
1214         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1215
1216 #define OP_GEN_AGG_VECT(index) \
1217         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1218
1219
1220 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1221 {
1222         struct sdm_op_gen op_gen = {0};
1223
1224         u32 comp_addr = BAR_CSTRORM_INTMEM +
1225                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1226         int ret = 0;
1227
1228         if (REG_RD(bp, comp_addr)) {
1229                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1230                 return 1;
1231         }
1232
1233         op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1234         op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1235         op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1236         op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1237
1238         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1239         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1240
1241         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1242                 BNX2X_ERR("FW final cleanup did not succeed\n");
1243                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1244                    (REG_RD(bp, comp_addr)));
1245                 bnx2x_panic();
1246                 return 1;
1247         }
1248         /* Zero completion for nxt FLR */
1249         REG_WR(bp, comp_addr, 0);
1250
1251         return ret;
1252 }
1253
1254 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1255 {
1256         u16 status;
1257
1258         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1259         return status & PCI_EXP_DEVSTA_TRPND;
1260 }
1261
1262 /* PF FLR specific routines
1263 */
1264 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1265 {
1266
1267         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1268         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1269                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1270                         "CFC PF usage counter timed out",
1271                         poll_cnt))
1272                 return 1;
1273
1274
1275         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1276         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1277                         DORQ_REG_PF_USAGE_CNT,
1278                         "DQ PF usage counter timed out",
1279                         poll_cnt))
1280                 return 1;
1281
1282         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1283         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1284                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1285                         "QM PF usage counter timed out",
1286                         poll_cnt))
1287                 return 1;
1288
1289         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1290         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1291                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1292                         "Timers VNIC usage counter timed out",
1293                         poll_cnt))
1294                 return 1;
1295         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1296                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1297                         "Timers NUM_SCANS usage counter timed out",
1298                         poll_cnt))
1299                 return 1;
1300
1301         /* Wait DMAE PF usage counter to zero */
1302         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1303                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1304                         "DMAE dommand register timed out",
1305                         poll_cnt))
1306                 return 1;
1307
1308         return 0;
1309 }
1310
1311 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1312 {
1313         u32 val;
1314
1315         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1316         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1317
1318         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1319         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1320
1321         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1322         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1323
1324         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1325         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1326
1327         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1328         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1329
1330         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1331         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1332
1333         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1334         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1335
1336         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1337         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1338            val);
1339 }
1340
1341 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1342 {
1343         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1344
1345         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1346
1347         /* Re-enable PF target read access */
1348         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1349
1350         /* Poll HW usage counters */
1351         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1352         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1353                 return -EBUSY;
1354
1355         /* Zero the igu 'trailing edge' and 'leading edge' */
1356
1357         /* Send the FW cleanup command */
1358         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1359                 return -EBUSY;
1360
1361         /* ATC cleanup */
1362
1363         /* Verify TX hw is flushed */
1364         bnx2x_tx_hw_flushed(bp, poll_cnt);
1365
1366         /* Wait 100ms (not adjusted according to platform) */
1367         msleep(100);
1368
1369         /* Verify no pending pci transactions */
1370         if (bnx2x_is_pcie_pending(bp->pdev))
1371                 BNX2X_ERR("PCIE Transactions still pending\n");
1372
1373         /* Debug */
1374         bnx2x_hw_enable_status(bp);
1375
1376         /*
1377          * Master enable - Due to WB DMAE writes performed before this
1378          * register is re-initialized as part of the regular function init
1379          */
1380         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1381
1382         return 0;
1383 }
1384
1385 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1386 {
1387         int port = BP_PORT(bp);
1388         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1389         u32 val = REG_RD(bp, addr);
1390         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1391         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1392         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1393
1394         if (msix) {
1395                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1396                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1397                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1398                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1399                 if (single_msix)
1400                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1401         } else if (msi) {
1402                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1403                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1404                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1405                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1406         } else {
1407                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1408                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1409                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1410                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1411
1412                 if (!CHIP_IS_E1(bp)) {
1413                         DP(NETIF_MSG_IFUP,
1414                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1415
1416                         REG_WR(bp, addr, val);
1417
1418                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1419                 }
1420         }
1421
1422         if (CHIP_IS_E1(bp))
1423                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1424
1425         DP(NETIF_MSG_IFUP,
1426            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1427            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1428
1429         REG_WR(bp, addr, val);
1430         /*
1431          * Ensure that HC_CONFIG is written before leading/trailing edge config
1432          */
1433         mmiowb();
1434         barrier();
1435
1436         if (!CHIP_IS_E1(bp)) {
1437                 /* init leading/trailing edge */
1438                 if (IS_MF(bp)) {
1439                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1440                         if (bp->port.pmf)
1441                                 /* enable nig and gpio3 attention */
1442                                 val |= 0x1100;
1443                 } else
1444                         val = 0xffff;
1445
1446                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1447                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1448         }
1449
1450         /* Make sure that interrupts are indeed enabled from here on */
1451         mmiowb();
1452 }
1453
1454 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1455 {
1456         u32 val;
1457         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1458         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1459         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1460
1461         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1462
1463         if (msix) {
1464                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1465                          IGU_PF_CONF_SINGLE_ISR_EN);
1466                 val |= (IGU_PF_CONF_FUNC_EN |
1467                         IGU_PF_CONF_MSI_MSIX_EN |
1468                         IGU_PF_CONF_ATTN_BIT_EN);
1469
1470                 if (single_msix)
1471                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1472         } else if (msi) {
1473                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1474                 val |= (IGU_PF_CONF_FUNC_EN |
1475                         IGU_PF_CONF_MSI_MSIX_EN |
1476                         IGU_PF_CONF_ATTN_BIT_EN |
1477                         IGU_PF_CONF_SINGLE_ISR_EN);
1478         } else {
1479                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1480                 val |= (IGU_PF_CONF_FUNC_EN |
1481                         IGU_PF_CONF_INT_LINE_EN |
1482                         IGU_PF_CONF_ATTN_BIT_EN |
1483                         IGU_PF_CONF_SINGLE_ISR_EN);
1484         }
1485
1486         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1487            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1488
1489         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1490
1491         if (val & IGU_PF_CONF_INT_LINE_EN)
1492                 pci_intx(bp->pdev, true);
1493
1494         barrier();
1495
1496         /* init leading/trailing edge */
1497         if (IS_MF(bp)) {
1498                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1499                 if (bp->port.pmf)
1500                         /* enable nig and gpio3 attention */
1501                         val |= 0x1100;
1502         } else
1503                 val = 0xffff;
1504
1505         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1506         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1507
1508         /* Make sure that interrupts are indeed enabled from here on */
1509         mmiowb();
1510 }
1511
1512 void bnx2x_int_enable(struct bnx2x *bp)
1513 {
1514         if (bp->common.int_block == INT_BLOCK_HC)
1515                 bnx2x_hc_int_enable(bp);
1516         else
1517                 bnx2x_igu_int_enable(bp);
1518 }
1519
1520 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1521 {
1522         int port = BP_PORT(bp);
1523         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1524         u32 val = REG_RD(bp, addr);
1525
1526         /*
1527          * in E1 we must use only PCI configuration space to disable
1528          * MSI/MSIX capablility
1529          * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1530          */
1531         if (CHIP_IS_E1(bp)) {
1532                 /*  Since IGU_PF_CONF_MSI_MSIX_EN still always on
1533                  *  Use mask register to prevent from HC sending interrupts
1534                  *  after we exit the function
1535                  */
1536                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1537
1538                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1539                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
1540                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1541         } else
1542                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1543                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1544                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
1545                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1546
1547         DP(NETIF_MSG_IFDOWN,
1548            "write %x to HC %d (addr 0x%x)\n",
1549            val, port, addr);
1550
1551         /* flush all outstanding writes */
1552         mmiowb();
1553
1554         REG_WR(bp, addr, val);
1555         if (REG_RD(bp, addr) != val)
1556                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1557 }
1558
1559 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1560 {
1561         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1562
1563         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1564                  IGU_PF_CONF_INT_LINE_EN |
1565                  IGU_PF_CONF_ATTN_BIT_EN);
1566
1567         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1568
1569         /* flush all outstanding writes */
1570         mmiowb();
1571
1572         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1573         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1574                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1575 }
1576
1577 static void bnx2x_int_disable(struct bnx2x *bp)
1578 {
1579         if (bp->common.int_block == INT_BLOCK_HC)
1580                 bnx2x_hc_int_disable(bp);
1581         else
1582                 bnx2x_igu_int_disable(bp);
1583 }
1584
1585 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1586 {
1587         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1588         int i, offset;
1589
1590         if (disable_hw)
1591                 /* prevent the HW from sending interrupts */
1592                 bnx2x_int_disable(bp);
1593
1594         /* make sure all ISRs are done */
1595         if (msix) {
1596                 synchronize_irq(bp->msix_table[0].vector);
1597                 offset = 1;
1598                 if (CNIC_SUPPORT(bp))
1599                         offset++;
1600                 for_each_eth_queue(bp, i)
1601                         synchronize_irq(bp->msix_table[offset++].vector);
1602         } else
1603                 synchronize_irq(bp->pdev->irq);
1604
1605         /* make sure sp_task is not running */
1606         cancel_delayed_work(&bp->sp_task);
1607         cancel_delayed_work(&bp->period_task);
1608         flush_workqueue(bnx2x_wq);
1609 }
1610
1611 /* fast path */
1612
1613 /*
1614  * General service functions
1615  */
1616
1617 /* Return true if succeeded to acquire the lock */
1618 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1619 {
1620         u32 lock_status;
1621         u32 resource_bit = (1 << resource);
1622         int func = BP_FUNC(bp);
1623         u32 hw_lock_control_reg;
1624
1625         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1626            "Trying to take a lock on resource %d\n", resource);
1627
1628         /* Validating that the resource is within range */
1629         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1630                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1631                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1632                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1633                 return false;
1634         }
1635
1636         if (func <= 5)
1637                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1638         else
1639                 hw_lock_control_reg =
1640                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1641
1642         /* Try to acquire the lock */
1643         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1644         lock_status = REG_RD(bp, hw_lock_control_reg);
1645         if (lock_status & resource_bit)
1646                 return true;
1647
1648         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1649            "Failed to get a lock on resource %d\n", resource);
1650         return false;
1651 }
1652
1653 /**
1654  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1655  *
1656  * @bp: driver handle
1657  *
1658  * Returns the recovery leader resource id according to the engine this function
1659  * belongs to. Currently only only 2 engines is supported.
1660  */
1661 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1662 {
1663         if (BP_PATH(bp))
1664                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1665         else
1666                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1667 }
1668
1669 /**
1670  * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1671  *
1672  * @bp: driver handle
1673  *
1674  * Tries to aquire a leader lock for current engine.
1675  */
1676 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1677 {
1678         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1679 }
1680
1681 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1682
1683 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1684 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1685 {
1686         /* Set the interrupt occurred bit for the sp-task to recognize it
1687          * must ack the interrupt and transition according to the IGU
1688          * state machine.
1689          */
1690         atomic_set(&bp->interrupt_occurred, 1);
1691
1692         /* The sp_task must execute only after this bit
1693          * is set, otherwise we will get out of sync and miss all
1694          * further interrupts. Hence, the barrier.
1695          */
1696         smp_wmb();
1697
1698         /* schedule sp_task to workqueue */
1699         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1700 }
1701
1702 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1703 {
1704         struct bnx2x *bp = fp->bp;
1705         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1706         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1707         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1708         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1709
1710         DP(BNX2X_MSG_SP,
1711            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1712            fp->index, cid, command, bp->state,
1713            rr_cqe->ramrod_cqe.ramrod_type);
1714
1715         /* If cid is within VF range, replace the slowpath object with the
1716          * one corresponding to this VF
1717          */
1718         if (cid >= BNX2X_FIRST_VF_CID  &&
1719             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1720                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1721
1722         switch (command) {
1723         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1724                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1725                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1726                 break;
1727
1728         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1729                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1730                 drv_cmd = BNX2X_Q_CMD_SETUP;
1731                 break;
1732
1733         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1734                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1735                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1736                 break;
1737
1738         case (RAMROD_CMD_ID_ETH_HALT):
1739                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1740                 drv_cmd = BNX2X_Q_CMD_HALT;
1741                 break;
1742
1743         case (RAMROD_CMD_ID_ETH_TERMINATE):
1744                 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1745                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1746                 break;
1747
1748         case (RAMROD_CMD_ID_ETH_EMPTY):
1749                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1750                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1751                 break;
1752
1753         default:
1754                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1755                           command, fp->index);
1756                 return;
1757         }
1758
1759         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1760             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1761                 /* q_obj->complete_cmd() failure means that this was
1762                  * an unexpected completion.
1763                  *
1764                  * In this case we don't want to increase the bp->spq_left
1765                  * because apparently we haven't sent this command the first
1766                  * place.
1767                  */
1768 #ifdef BNX2X_STOP_ON_ERROR
1769                 bnx2x_panic();
1770 #else
1771                 return;
1772 #endif
1773         /* SRIOV: reschedule any 'in_progress' operations */
1774         bnx2x_iov_sp_event(bp, cid, true);
1775
1776         smp_mb__before_atomic_inc();
1777         atomic_inc(&bp->cq_spq_left);
1778         /* push the change in bp->spq_left and towards the memory */
1779         smp_mb__after_atomic_inc();
1780
1781         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1782
1783         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1784             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1785                 /* if Q update ramrod is completed for last Q in AFEX vif set
1786                  * flow, then ACK MCP at the end
1787                  *
1788                  * mark pending ACK to MCP bit.
1789                  * prevent case that both bits are cleared.
1790                  * At the end of load/unload driver checks that
1791                  * sp_state is cleaerd, and this order prevents
1792                  * races
1793                  */
1794                 smp_mb__before_clear_bit();
1795                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1796                 wmb();
1797                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1798                 smp_mb__after_clear_bit();
1799
1800                 /* schedule the sp task as mcp ack is required */
1801                 bnx2x_schedule_sp_task(bp);
1802         }
1803
1804         return;
1805 }
1806
1807 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1808 {
1809         struct bnx2x *bp = netdev_priv(dev_instance);
1810         u16 status = bnx2x_ack_int(bp);
1811         u16 mask;
1812         int i;
1813         u8 cos;
1814
1815         /* Return here if interrupt is shared and it's not for us */
1816         if (unlikely(status == 0)) {
1817                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1818                 return IRQ_NONE;
1819         }
1820         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1821
1822 #ifdef BNX2X_STOP_ON_ERROR
1823         if (unlikely(bp->panic))
1824                 return IRQ_HANDLED;
1825 #endif
1826
1827         for_each_eth_queue(bp, i) {
1828                 struct bnx2x_fastpath *fp = &bp->fp[i];
1829
1830                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1831                 if (status & mask) {
1832                         /* Handle Rx or Tx according to SB id */
1833                         prefetch(fp->rx_cons_sb);
1834                         for_each_cos_in_tx_queue(fp, cos)
1835                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1836                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1837                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1838                         status &= ~mask;
1839                 }
1840         }
1841
1842         if (CNIC_SUPPORT(bp)) {
1843                 mask = 0x2;
1844                 if (status & (mask | 0x1)) {
1845                         struct cnic_ops *c_ops = NULL;
1846
1847                         if (likely(bp->state == BNX2X_STATE_OPEN)) {
1848                                 rcu_read_lock();
1849                                 c_ops = rcu_dereference(bp->cnic_ops);
1850                                 if (c_ops)
1851                                         c_ops->cnic_handler(bp->cnic_data,
1852                                                             NULL);
1853                                 rcu_read_unlock();
1854                         }
1855
1856                         status &= ~mask;
1857                 }
1858         }
1859
1860         if (unlikely(status & 0x1)) {
1861
1862                 /* schedule sp task to perform default status block work, ack
1863                  * attentions and enable interrupts.
1864                  */
1865                 bnx2x_schedule_sp_task(bp);
1866
1867                 status &= ~0x1;
1868                 if (!status)
1869                         return IRQ_HANDLED;
1870         }
1871
1872         if (unlikely(status))
1873                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1874                    status);
1875
1876         return IRQ_HANDLED;
1877 }
1878
1879 /* Link */
1880
1881 /*
1882  * General service functions
1883  */
1884
1885 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1886 {
1887         u32 lock_status;
1888         u32 resource_bit = (1 << resource);
1889         int func = BP_FUNC(bp);
1890         u32 hw_lock_control_reg;
1891         int cnt;
1892
1893         /* Validating that the resource is within range */
1894         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1895                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1896                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1897                 return -EINVAL;
1898         }
1899
1900         if (func <= 5) {
1901                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1902         } else {
1903                 hw_lock_control_reg =
1904                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1905         }
1906
1907         /* Validating that the resource is not already taken */
1908         lock_status = REG_RD(bp, hw_lock_control_reg);
1909         if (lock_status & resource_bit) {
1910                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1911                    lock_status, resource_bit);
1912                 return -EEXIST;
1913         }
1914
1915         /* Try for 5 second every 5ms */
1916         for (cnt = 0; cnt < 1000; cnt++) {
1917                 /* Try to acquire the lock */
1918                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1919                 lock_status = REG_RD(bp, hw_lock_control_reg);
1920                 if (lock_status & resource_bit)
1921                         return 0;
1922
1923                 msleep(5);
1924         }
1925         BNX2X_ERR("Timeout\n");
1926         return -EAGAIN;
1927 }
1928
1929 int bnx2x_release_leader_lock(struct bnx2x *bp)
1930 {
1931         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1932 }
1933
1934 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1935 {
1936         u32 lock_status;
1937         u32 resource_bit = (1 << resource);
1938         int func = BP_FUNC(bp);
1939         u32 hw_lock_control_reg;
1940
1941         /* Validating that the resource is within range */
1942         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1943                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1944                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1945                 return -EINVAL;
1946         }
1947
1948         if (func <= 5) {
1949                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1950         } else {
1951                 hw_lock_control_reg =
1952                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1953         }
1954
1955         /* Validating that the resource is currently taken */
1956         lock_status = REG_RD(bp, hw_lock_control_reg);
1957         if (!(lock_status & resource_bit)) {
1958                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1959                    lock_status, resource_bit);
1960                 return -EFAULT;
1961         }
1962
1963         REG_WR(bp, hw_lock_control_reg, resource_bit);
1964         return 0;
1965 }
1966
1967
1968 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1969 {
1970         /* The GPIO should be swapped if swap register is set and active */
1971         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1972                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1973         int gpio_shift = gpio_num +
1974                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1975         u32 gpio_mask = (1 << gpio_shift);
1976         u32 gpio_reg;
1977         int value;
1978
1979         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1980                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1981                 return -EINVAL;
1982         }
1983
1984         /* read GPIO value */
1985         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1986
1987         /* get the requested pin value */
1988         if ((gpio_reg & gpio_mask) == gpio_mask)
1989                 value = 1;
1990         else
1991                 value = 0;
1992
1993         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
1994
1995         return value;
1996 }
1997
1998 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1999 {
2000         /* The GPIO should be swapped if swap register is set and active */
2001         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2002                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2003         int gpio_shift = gpio_num +
2004                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2005         u32 gpio_mask = (1 << gpio_shift);
2006         u32 gpio_reg;
2007
2008         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2009                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2010                 return -EINVAL;
2011         }
2012
2013         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2014         /* read GPIO and mask except the float bits */
2015         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2016
2017         switch (mode) {
2018         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2019                 DP(NETIF_MSG_LINK,
2020                    "Set GPIO %d (shift %d) -> output low\n",
2021                    gpio_num, gpio_shift);
2022                 /* clear FLOAT and set CLR */
2023                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2024                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2025                 break;
2026
2027         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2028                 DP(NETIF_MSG_LINK,
2029                    "Set GPIO %d (shift %d) -> output high\n",
2030                    gpio_num, gpio_shift);
2031                 /* clear FLOAT and set SET */
2032                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2033                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2034                 break;
2035
2036         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2037                 DP(NETIF_MSG_LINK,
2038                    "Set GPIO %d (shift %d) -> input\n",
2039                    gpio_num, gpio_shift);
2040                 /* set FLOAT */
2041                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2042                 break;
2043
2044         default:
2045                 break;
2046         }
2047
2048         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2049         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2050
2051         return 0;
2052 }
2053
2054 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2055 {
2056         u32 gpio_reg = 0;
2057         int rc = 0;
2058
2059         /* Any port swapping should be handled by caller. */
2060
2061         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2062         /* read GPIO and mask except the float bits */
2063         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2064         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2065         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2066         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2067
2068         switch (mode) {
2069         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2070                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2071                 /* set CLR */
2072                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2073                 break;
2074
2075         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2076                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2077                 /* set SET */
2078                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2079                 break;
2080
2081         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2082                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2083                 /* set FLOAT */
2084                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2085                 break;
2086
2087         default:
2088                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2089                 rc = -EINVAL;
2090                 break;
2091         }
2092
2093         if (rc == 0)
2094                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2095
2096         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2097
2098         return rc;
2099 }
2100
2101 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2102 {
2103         /* The GPIO should be swapped if swap register is set and active */
2104         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2105                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2106         int gpio_shift = gpio_num +
2107                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2108         u32 gpio_mask = (1 << gpio_shift);
2109         u32 gpio_reg;
2110
2111         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2112                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2113                 return -EINVAL;
2114         }
2115
2116         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2117         /* read GPIO int */
2118         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2119
2120         switch (mode) {
2121         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2122                 DP(NETIF_MSG_LINK,
2123                    "Clear GPIO INT %d (shift %d) -> output low\n",
2124                    gpio_num, gpio_shift);
2125                 /* clear SET and set CLR */
2126                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2127                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2128                 break;
2129
2130         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2131                 DP(NETIF_MSG_LINK,
2132                    "Set GPIO INT %d (shift %d) -> output high\n",
2133                    gpio_num, gpio_shift);
2134                 /* clear CLR and set SET */
2135                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2136                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2137                 break;
2138
2139         default:
2140                 break;
2141         }
2142
2143         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2144         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2145
2146         return 0;
2147 }
2148
2149 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2150 {
2151         u32 spio_reg;
2152
2153         /* Only 2 SPIOs are configurable */
2154         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2155                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2156                 return -EINVAL;
2157         }
2158
2159         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2160         /* read SPIO and mask except the float bits */
2161         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2162
2163         switch (mode) {
2164         case MISC_SPIO_OUTPUT_LOW:
2165                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2166                 /* clear FLOAT and set CLR */
2167                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2168                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2169                 break;
2170
2171         case MISC_SPIO_OUTPUT_HIGH:
2172                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2173                 /* clear FLOAT and set SET */
2174                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2175                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2176                 break;
2177
2178         case MISC_SPIO_INPUT_HI_Z:
2179                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2180                 /* set FLOAT */
2181                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2182                 break;
2183
2184         default:
2185                 break;
2186         }
2187
2188         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2189         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2190
2191         return 0;
2192 }
2193
2194 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2195 {
2196         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2197         switch (bp->link_vars.ieee_fc &
2198                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2199         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2200                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2201                                                    ADVERTISED_Pause);
2202                 break;
2203
2204         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2205                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2206                                                   ADVERTISED_Pause);
2207                 break;
2208
2209         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2210                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2211                 break;
2212
2213         default:
2214                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2215                                                    ADVERTISED_Pause);
2216                 break;
2217         }
2218 }
2219
2220 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2221 {
2222         /* Initialize link parameters structure variables
2223          * It is recommended to turn off RX FC for jumbo frames
2224          *  for better performance
2225          */
2226         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2227                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2228         else
2229                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2230 }
2231
2232 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2233 {
2234         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2235         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2236
2237         if (!BP_NOMCP(bp)) {
2238                 bnx2x_set_requested_fc(bp);
2239                 bnx2x_acquire_phy_lock(bp);
2240
2241                 if (load_mode == LOAD_DIAG) {
2242                         struct link_params *lp = &bp->link_params;
2243                         lp->loopback_mode = LOOPBACK_XGXS;
2244                         /* do PHY loopback at 10G speed, if possible */
2245                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2246                                 if (lp->speed_cap_mask[cfx_idx] &
2247                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2248                                         lp->req_line_speed[cfx_idx] =
2249                                         SPEED_10000;
2250                                 else
2251                                         lp->req_line_speed[cfx_idx] =
2252                                         SPEED_1000;
2253                         }
2254                 }
2255
2256                 if (load_mode == LOAD_LOOPBACK_EXT) {
2257                         struct link_params *lp = &bp->link_params;
2258                         lp->loopback_mode = LOOPBACK_EXT;
2259                 }
2260
2261                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2262
2263                 bnx2x_release_phy_lock(bp);
2264
2265                 bnx2x_calc_fc_adv(bp);
2266
2267                 if (bp->link_vars.link_up) {
2268                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2269                         bnx2x_link_report(bp);
2270                 }
2271                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2272                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2273                 return rc;
2274         }
2275         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2276         return -EINVAL;
2277 }
2278
2279 void bnx2x_link_set(struct bnx2x *bp)
2280 {
2281         if (!BP_NOMCP(bp)) {
2282                 bnx2x_acquire_phy_lock(bp);
2283                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2284                 bnx2x_release_phy_lock(bp);
2285
2286                 bnx2x_calc_fc_adv(bp);
2287         } else
2288                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2289 }
2290
2291 static void bnx2x__link_reset(struct bnx2x *bp)
2292 {
2293         if (!BP_NOMCP(bp)) {
2294                 bnx2x_acquire_phy_lock(bp);
2295                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2296                 bnx2x_release_phy_lock(bp);
2297         } else
2298                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2299 }
2300
2301 void bnx2x_force_link_reset(struct bnx2x *bp)
2302 {
2303         bnx2x_acquire_phy_lock(bp);
2304         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2305         bnx2x_release_phy_lock(bp);
2306 }
2307
2308 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2309 {
2310         u8 rc = 0;
2311
2312         if (!BP_NOMCP(bp)) {
2313                 bnx2x_acquire_phy_lock(bp);
2314                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2315                                      is_serdes);
2316                 bnx2x_release_phy_lock(bp);
2317         } else
2318                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2319
2320         return rc;
2321 }
2322
2323
2324 /* Calculates the sum of vn_min_rates.
2325    It's needed for further normalizing of the min_rates.
2326    Returns:
2327      sum of vn_min_rates.
2328        or
2329      0 - if all the min_rates are 0.
2330      In the later case fainess algorithm should be deactivated.
2331      If not all min_rates are zero then those that are zeroes will be set to 1.
2332  */
2333 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2334                                       struct cmng_init_input *input)
2335 {
2336         int all_zero = 1;
2337         int vn;
2338
2339         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2340                 u32 vn_cfg = bp->mf_config[vn];
2341                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2342                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2343
2344                 /* Skip hidden vns */
2345                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2346                         vn_min_rate = 0;
2347                 /* If min rate is zero - set it to 1 */
2348                 else if (!vn_min_rate)
2349                         vn_min_rate = DEF_MIN_RATE;
2350                 else
2351                         all_zero = 0;
2352
2353                 input->vnic_min_rate[vn] = vn_min_rate;
2354         }
2355
2356         /* if ETS or all min rates are zeros - disable fairness */
2357         if (BNX2X_IS_ETS_ENABLED(bp)) {
2358                 input->flags.cmng_enables &=
2359                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2360                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2361         } else if (all_zero) {
2362                 input->flags.cmng_enables &=
2363                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2364                 DP(NETIF_MSG_IFUP,
2365                    "All MIN values are zeroes fairness will be disabled\n");
2366         } else
2367                 input->flags.cmng_enables |=
2368                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2369 }
2370
2371 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2372                                     struct cmng_init_input *input)
2373 {
2374         u16 vn_max_rate;
2375         u32 vn_cfg = bp->mf_config[vn];
2376
2377         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2378                 vn_max_rate = 0;
2379         else {
2380                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2381
2382                 if (IS_MF_SI(bp)) {
2383                         /* maxCfg in percents of linkspeed */
2384                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2385                 } else /* SD modes */
2386                         /* maxCfg is absolute in 100Mb units */
2387                         vn_max_rate = maxCfg * 100;
2388         }
2389
2390         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2391
2392         input->vnic_max_rate[vn] = vn_max_rate;
2393 }
2394
2395
2396 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2397 {
2398         if (CHIP_REV_IS_SLOW(bp))
2399                 return CMNG_FNS_NONE;
2400         if (IS_MF(bp))
2401                 return CMNG_FNS_MINMAX;
2402
2403         return CMNG_FNS_NONE;
2404 }
2405
2406 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2407 {
2408         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2409
2410         if (BP_NOMCP(bp))
2411                 return; /* what should be the default bvalue in this case */
2412
2413         /* For 2 port configuration the absolute function number formula
2414          * is:
2415          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2416          *
2417          *      and there are 4 functions per port
2418          *
2419          * For 4 port configuration it is
2420          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2421          *
2422          *      and there are 2 functions per port
2423          */
2424         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2425                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2426
2427                 if (func >= E1H_FUNC_MAX)
2428                         break;
2429
2430                 bp->mf_config[vn] =
2431                         MF_CFG_RD(bp, func_mf_config[func].config);
2432         }
2433         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2434                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2435                 bp->flags |= MF_FUNC_DIS;
2436         } else {
2437                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2438                 bp->flags &= ~MF_FUNC_DIS;
2439         }
2440 }
2441
2442 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2443 {
2444         struct cmng_init_input input;
2445         memset(&input, 0, sizeof(struct cmng_init_input));
2446
2447         input.port_rate = bp->link_vars.line_speed;
2448
2449         if (cmng_type == CMNG_FNS_MINMAX) {
2450                 int vn;
2451
2452                 /* read mf conf from shmem */
2453                 if (read_cfg)
2454                         bnx2x_read_mf_cfg(bp);
2455
2456                 /* vn_weight_sum and enable fairness if not 0 */
2457                 bnx2x_calc_vn_min(bp, &input);
2458
2459                 /* calculate and set min-max rate for each vn */
2460                 if (bp->port.pmf)
2461                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2462                                 bnx2x_calc_vn_max(bp, vn, &input);
2463
2464                 /* always enable rate shaping and fairness */
2465                 input.flags.cmng_enables |=
2466                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2467
2468                 bnx2x_init_cmng(&input, &bp->cmng);
2469                 return;
2470         }
2471
2472         /* rate shaping and fairness are disabled */
2473         DP(NETIF_MSG_IFUP,
2474            "rate shaping and fairness are disabled\n");
2475 }
2476
2477 static void storm_memset_cmng(struct bnx2x *bp,
2478                               struct cmng_init *cmng,
2479                               u8 port)
2480 {
2481         int vn;
2482         size_t size = sizeof(struct cmng_struct_per_port);
2483
2484         u32 addr = BAR_XSTRORM_INTMEM +
2485                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2486
2487         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2488
2489         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2490                 int func = func_by_vn(bp, vn);
2491
2492                 addr = BAR_XSTRORM_INTMEM +
2493                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2494                 size = sizeof(struct rate_shaping_vars_per_vn);
2495                 __storm_memset_struct(bp, addr, size,
2496                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2497
2498                 addr = BAR_XSTRORM_INTMEM +
2499                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2500                 size = sizeof(struct fairness_vars_per_vn);
2501                 __storm_memset_struct(bp, addr, size,
2502                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2503         }
2504 }
2505
2506 /* This function is called upon link interrupt */
2507 static void bnx2x_link_attn(struct bnx2x *bp)
2508 {
2509         /* Make sure that we are synced with the current statistics */
2510         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2511
2512         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2513
2514         if (bp->link_vars.link_up) {
2515
2516                 /* dropless flow control */
2517                 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2518                         int port = BP_PORT(bp);
2519                         u32 pause_enabled = 0;
2520
2521                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2522                                 pause_enabled = 1;
2523
2524                         REG_WR(bp, BAR_USTRORM_INTMEM +
2525                                USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2526                                pause_enabled);
2527                 }
2528
2529                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2530                         struct host_port_stats *pstats;
2531
2532                         pstats = bnx2x_sp(bp, port_stats);
2533                         /* reset old mac stats */
2534                         memset(&(pstats->mac_stx[0]), 0,
2535                                sizeof(struct mac_stx));
2536                 }
2537                 if (bp->state == BNX2X_STATE_OPEN)
2538                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2539         }
2540
2541         if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2542                 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2543
2544                 if (cmng_fns != CMNG_FNS_NONE) {
2545                         bnx2x_cmng_fns_init(bp, false, cmng_fns);
2546                         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2547                 } else
2548                         /* rate shaping and fairness are disabled */
2549                         DP(NETIF_MSG_IFUP,
2550                            "single function mode without fairness\n");
2551         }
2552
2553         __bnx2x_link_report(bp);
2554
2555         if (IS_MF(bp))
2556                 bnx2x_link_sync_notify(bp);
2557 }
2558
2559 void bnx2x__link_status_update(struct bnx2x *bp)
2560 {
2561         if (bp->state != BNX2X_STATE_OPEN)
2562                 return;
2563
2564         /* read updated dcb configuration */
2565         if (IS_PF(bp)) {
2566                 bnx2x_dcbx_pmf_update(bp);
2567                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2568                 if (bp->link_vars.link_up)
2569                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2570                 else
2571                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2572                         /* indicate link status */
2573                 bnx2x_link_report(bp);
2574
2575         } else { /* VF */
2576                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2577                                           SUPPORTED_10baseT_Full |
2578                                           SUPPORTED_100baseT_Half |
2579                                           SUPPORTED_100baseT_Full |
2580                                           SUPPORTED_1000baseT_Full |
2581                                           SUPPORTED_2500baseX_Full |
2582                                           SUPPORTED_10000baseT_Full |
2583                                           SUPPORTED_TP |
2584                                           SUPPORTED_FIBRE |
2585                                           SUPPORTED_Autoneg |
2586                                           SUPPORTED_Pause |
2587                                           SUPPORTED_Asym_Pause);
2588                 bp->port.advertising[0] = bp->port.supported[0];
2589
2590                 bp->link_params.bp = bp;
2591                 bp->link_params.port = BP_PORT(bp);
2592                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2593                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2594                 bp->link_params.req_line_speed[0] = SPEED_10000;
2595                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2596                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2597                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2598                 bp->link_vars.line_speed = SPEED_10000;
2599                 bp->link_vars.link_status =
2600                         (LINK_STATUS_LINK_UP |
2601                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2602                 bp->link_vars.link_up = 1;
2603                 bp->link_vars.duplex = DUPLEX_FULL;
2604                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2605                 __bnx2x_link_report(bp);
2606                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2607         }
2608 }
2609
2610 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2611                                   u16 vlan_val, u8 allowed_prio)
2612 {
2613         struct bnx2x_func_state_params func_params = {0};
2614         struct bnx2x_func_afex_update_params *f_update_params =
2615                 &func_params.params.afex_update;
2616
2617         func_params.f_obj = &bp->func_obj;
2618         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2619
2620         /* no need to wait for RAMROD completion, so don't
2621          * set RAMROD_COMP_WAIT flag
2622          */
2623
2624         f_update_params->vif_id = vifid;
2625         f_update_params->afex_default_vlan = vlan_val;
2626         f_update_params->allowed_priorities = allowed_prio;
2627
2628         /* if ramrod can not be sent, response to MCP immediately */
2629         if (bnx2x_func_state_change(bp, &func_params) < 0)
2630                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2631
2632         return 0;
2633 }
2634
2635 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2636                                           u16 vif_index, u8 func_bit_map)
2637 {
2638         struct bnx2x_func_state_params func_params = {0};
2639         struct bnx2x_func_afex_viflists_params *update_params =
2640                 &func_params.params.afex_viflists;
2641         int rc;
2642         u32 drv_msg_code;
2643
2644         /* validate only LIST_SET and LIST_GET are received from switch */
2645         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2646                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2647                           cmd_type);
2648
2649         func_params.f_obj = &bp->func_obj;
2650         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2651
2652         /* set parameters according to cmd_type */
2653         update_params->afex_vif_list_command = cmd_type;
2654         update_params->vif_list_index = cpu_to_le16(vif_index);
2655         update_params->func_bit_map =
2656                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2657         update_params->func_to_clear = 0;
2658         drv_msg_code =
2659                 (cmd_type == VIF_LIST_RULE_GET) ?
2660                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2661                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2662
2663         /* if ramrod can not be sent, respond to MCP immediately for
2664          * SET and GET requests (other are not triggered from MCP)
2665          */
2666         rc = bnx2x_func_state_change(bp, &func_params);
2667         if (rc < 0)
2668                 bnx2x_fw_command(bp, drv_msg_code, 0);
2669
2670         return 0;
2671 }
2672
2673 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2674 {
2675         struct afex_stats afex_stats;
2676         u32 func = BP_ABS_FUNC(bp);
2677         u32 mf_config;
2678         u16 vlan_val;
2679         u32 vlan_prio;
2680         u16 vif_id;
2681         u8 allowed_prio;
2682         u8 vlan_mode;
2683         u32 addr_to_write, vifid, addrs, stats_type, i;
2684
2685         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2686                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2687                 DP(BNX2X_MSG_MCP,
2688                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2689                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2690         }
2691
2692         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2693                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2694                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2695                 DP(BNX2X_MSG_MCP,
2696                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2697                    vifid, addrs);
2698                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2699                                                addrs);
2700         }
2701
2702         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2703                 addr_to_write = SHMEM2_RD(bp,
2704                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2705                 stats_type = SHMEM2_RD(bp,
2706                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2707
2708                 DP(BNX2X_MSG_MCP,
2709                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2710                    addr_to_write);
2711
2712                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2713
2714                 /* write response to scratchpad, for MCP */
2715                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2716                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2717                                *(((u32 *)(&afex_stats))+i));
2718
2719                 /* send ack message to MCP */
2720                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2721         }
2722
2723         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2724                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2725                 bp->mf_config[BP_VN(bp)] = mf_config;
2726                 DP(BNX2X_MSG_MCP,
2727                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2728                    mf_config);
2729
2730                 /* if VIF_SET is "enabled" */
2731                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2732                         /* set rate limit directly to internal RAM */
2733                         struct cmng_init_input cmng_input;
2734                         struct rate_shaping_vars_per_vn m_rs_vn;
2735                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2736                         u32 addr = BAR_XSTRORM_INTMEM +
2737                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2738
2739                         bp->mf_config[BP_VN(bp)] = mf_config;
2740
2741                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2742                         m_rs_vn.vn_counter.rate =
2743                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2744                         m_rs_vn.vn_counter.quota =
2745                                 (m_rs_vn.vn_counter.rate *
2746                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2747
2748                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2749
2750                         /* read relevant values from mf_cfg struct in shmem */
2751                         vif_id =
2752                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2753                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2754                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2755                         vlan_val =
2756                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2757                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2758                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2759                         vlan_prio = (mf_config &
2760                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2761                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2762                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2763                         vlan_mode =
2764                                 (MF_CFG_RD(bp,
2765                                            func_mf_config[func].afex_config) &
2766                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2767                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2768                         allowed_prio =
2769                                 (MF_CFG_RD(bp,
2770                                            func_mf_config[func].afex_config) &
2771                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2772                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2773
2774                         /* send ramrod to FW, return in case of failure */
2775                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2776                                                    allowed_prio))
2777                                 return;
2778
2779                         bp->afex_def_vlan_tag = vlan_val;
2780                         bp->afex_vlan_mode = vlan_mode;
2781                 } else {
2782                         /* notify link down because BP->flags is disabled */
2783                         bnx2x_link_report(bp);
2784
2785                         /* send INVALID VIF ramrod to FW */
2786                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2787
2788                         /* Reset the default afex VLAN */
2789                         bp->afex_def_vlan_tag = -1;
2790                 }
2791         }
2792 }
2793
2794 static void bnx2x_pmf_update(struct bnx2x *bp)
2795 {
2796         int port = BP_PORT(bp);
2797         u32 val;
2798
2799         bp->port.pmf = 1;
2800         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2801
2802         /*
2803          * We need the mb() to ensure the ordering between the writing to
2804          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2805          */
2806         smp_mb();
2807
2808         /* queue a periodic task */
2809         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2810
2811         bnx2x_dcbx_pmf_update(bp);
2812
2813         /* enable nig attention */
2814         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2815         if (bp->common.int_block == INT_BLOCK_HC) {
2816                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2817                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2818         } else if (!CHIP_IS_E1x(bp)) {
2819                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2820                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2821         }
2822
2823         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2824 }
2825
2826 /* end of Link */
2827
2828 /* slow path */
2829
2830 /*
2831  * General service functions
2832  */
2833
2834 /* send the MCP a request, block until there is a reply */
2835 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2836 {
2837         int mb_idx = BP_FW_MB_IDX(bp);
2838         u32 seq;
2839         u32 rc = 0;
2840         u32 cnt = 1;
2841         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2842
2843         mutex_lock(&bp->fw_mb_mutex);
2844         seq = ++bp->fw_seq;
2845         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2846         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2847
2848         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2849                         (command | seq), param);
2850
2851         do {
2852                 /* let the FW do it's magic ... */
2853                 msleep(delay);
2854
2855                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2856
2857                 /* Give the FW up to 5 second (500*10ms) */
2858         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2859
2860         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2861            cnt*delay, rc, seq);
2862
2863         /* is this a reply to our command? */
2864         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2865                 rc &= FW_MSG_CODE_MASK;
2866         else {
2867                 /* FW BUG! */
2868                 BNX2X_ERR("FW failed to respond!\n");
2869                 bnx2x_fw_dump(bp);
2870                 rc = 0;
2871         }
2872         mutex_unlock(&bp->fw_mb_mutex);
2873
2874         return rc;
2875 }
2876
2877
2878 static void storm_memset_func_cfg(struct bnx2x *bp,
2879                                  struct tstorm_eth_function_common_config *tcfg,
2880                                  u16 abs_fid)
2881 {
2882         size_t size = sizeof(struct tstorm_eth_function_common_config);
2883
2884         u32 addr = BAR_TSTRORM_INTMEM +
2885                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2886
2887         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2888 }
2889
2890 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2891 {
2892         if (CHIP_IS_E1x(bp)) {
2893                 struct tstorm_eth_function_common_config tcfg = {0};
2894
2895                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2896         }
2897
2898         /* Enable the function in the FW */
2899         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2900         storm_memset_func_en(bp, p->func_id, 1);
2901
2902         /* spq */
2903         if (p->func_flgs & FUNC_FLG_SPQ) {
2904                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2905                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2906                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2907         }
2908 }
2909
2910 /**
2911  * bnx2x_get_tx_only_flags - Return common flags
2912  *
2913  * @bp          device handle
2914  * @fp          queue handle
2915  * @zero_stats  TRUE if statistics zeroing is needed
2916  *
2917  * Return the flags that are common for the Tx-only and not normal connections.
2918  */
2919 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2920                                             struct bnx2x_fastpath *fp,
2921                                             bool zero_stats)
2922 {
2923         unsigned long flags = 0;
2924
2925         /* PF driver will always initialize the Queue to an ACTIVE state */
2926         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2927
2928         /* tx only connections collect statistics (on the same index as the
2929          *  parent connection). The statistics are zeroed when the parent
2930          *  connection is initialized.
2931          */
2932
2933         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2934         if (zero_stats)
2935                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2936
2937
2938         return flags;
2939 }
2940
2941 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2942                                        struct bnx2x_fastpath *fp,
2943                                        bool leading)
2944 {
2945         unsigned long flags = 0;
2946
2947         /* calculate other queue flags */
2948         if (IS_MF_SD(bp))
2949                 __set_bit(BNX2X_Q_FLG_OV, &flags);
2950
2951         if (IS_FCOE_FP(fp)) {
2952                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2953                 /* For FCoE - force usage of default priority (for afex) */
2954                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2955         }
2956
2957         if (!fp->disable_tpa) {
2958                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2959                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2960                 if (fp->mode == TPA_MODE_GRO)
2961                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2962         }
2963
2964         if (leading) {
2965                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2966                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2967         }
2968
2969         /* Always set HW VLAN stripping */
2970         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2971
2972         /* configure silent vlan removal */
2973         if (IS_MF_AFEX(bp))
2974                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2975
2976
2977         return flags | bnx2x_get_common_flags(bp, fp, true);
2978 }
2979
2980 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2981         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2982         u8 cos)
2983 {
2984         gen_init->stat_id = bnx2x_stats_id(fp);
2985         gen_init->spcl_id = fp->cl_id;
2986
2987         /* Always use mini-jumbo MTU for FCoE L2 ring */
2988         if (IS_FCOE_FP(fp))
2989                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2990         else
2991                 gen_init->mtu = bp->dev->mtu;
2992
2993         gen_init->cos = cos;
2994 }
2995
2996 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2997         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2998         struct bnx2x_rxq_setup_params *rxq_init)
2999 {
3000         u8 max_sge = 0;
3001         u16 sge_sz = 0;
3002         u16 tpa_agg_size = 0;
3003
3004         if (!fp->disable_tpa) {
3005                 pause->sge_th_lo = SGE_TH_LO(bp);
3006                 pause->sge_th_hi = SGE_TH_HI(bp);
3007
3008                 /* validate SGE ring has enough to cross high threshold */
3009                 WARN_ON(bp->dropless_fc &&
3010                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3011                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3012
3013                 tpa_agg_size = min_t(u32,
3014                         (min_t(u32, 8, MAX_SKB_FRAGS) *
3015                         SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
3016                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3017                         SGE_PAGE_SHIFT;
3018                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3019                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3020                 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
3021                                     0xffff);
3022         }
3023
3024         /* pause - not for e1 */
3025         if (!CHIP_IS_E1(bp)) {
3026                 pause->bd_th_lo = BD_TH_LO(bp);
3027                 pause->bd_th_hi = BD_TH_HI(bp);
3028
3029                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3030                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3031                 /*
3032                  * validate that rings have enough entries to cross
3033                  * high thresholds
3034                  */
3035                 WARN_ON(bp->dropless_fc &&
3036                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3037                                 bp->rx_ring_size);
3038                 WARN_ON(bp->dropless_fc &&
3039                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3040                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3041
3042                 pause->pri_map = 1;
3043         }
3044
3045         /* rxq setup */
3046         rxq_init->dscr_map = fp->rx_desc_mapping;
3047         rxq_init->sge_map = fp->rx_sge_mapping;
3048         rxq_init->rcq_map = fp->rx_comp_mapping;
3049         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3050
3051         /* This should be a maximum number of data bytes that may be
3052          * placed on the BD (not including paddings).
3053          */
3054         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3055                 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3056
3057         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3058         rxq_init->tpa_agg_sz = tpa_agg_size;
3059         rxq_init->sge_buf_sz = sge_sz;
3060         rxq_init->max_sges_pkt = max_sge;
3061         rxq_init->rss_engine_id = BP_FUNC(bp);
3062         rxq_init->mcast_engine_id = BP_FUNC(bp);
3063
3064         /* Maximum number or simultaneous TPA aggregation for this Queue.
3065          *
3066          * For PF Clients it should be the maximum avaliable number.
3067          * VF driver(s) may want to define it to a smaller value.
3068          */
3069         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3070
3071         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3072         rxq_init->fw_sb_id = fp->fw_sb_id;
3073
3074         if (IS_FCOE_FP(fp))
3075                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3076         else
3077                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3078         /* configure silent vlan removal
3079          * if multi function mode is afex, then mask default vlan
3080          */
3081         if (IS_MF_AFEX(bp)) {
3082                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3083                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3084         }
3085 }
3086
3087 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3088         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3089         u8 cos)
3090 {
3091         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3092         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3093         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3094         txq_init->fw_sb_id = fp->fw_sb_id;
3095
3096         /*
3097          * set the tss leading client id for TX classfication ==
3098          * leading RSS client id
3099          */
3100         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3101
3102         if (IS_FCOE_FP(fp)) {
3103                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3104                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3105         }
3106 }
3107
3108 static void bnx2x_pf_init(struct bnx2x *bp)
3109 {
3110         struct bnx2x_func_init_params func_init = {0};
3111         struct event_ring_data eq_data = { {0} };
3112         u16 flags;
3113
3114         if (!CHIP_IS_E1x(bp)) {
3115                 /* reset IGU PF statistics: MSIX + ATTN */
3116                 /* PF */
3117                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3118                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3119                            (CHIP_MODE_IS_4_PORT(bp) ?
3120                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3121                 /* ATTN */
3122                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3123                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3124                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3125                            (CHIP_MODE_IS_4_PORT(bp) ?
3126                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3127         }
3128
3129         /* function setup flags */
3130         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3131
3132         /* This flag is relevant for E1x only.
3133          * E2 doesn't have a TPA configuration in a function level.
3134          */
3135         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3136
3137         func_init.func_flgs = flags;
3138         func_init.pf_id = BP_FUNC(bp);
3139         func_init.func_id = BP_FUNC(bp);
3140         func_init.spq_map = bp->spq_mapping;
3141         func_init.spq_prod = bp->spq_prod_idx;
3142
3143         bnx2x_func_init(bp, &func_init);
3144
3145         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3146
3147         /*
3148          * Congestion management values depend on the link rate
3149          * There is no active link so initial link rate is set to 10 Gbps.
3150          * When the link comes up The congestion management values are
3151          * re-calculated according to the actual link rate.
3152          */
3153         bp->link_vars.line_speed = SPEED_10000;
3154         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3155
3156         /* Only the PMF sets the HW */
3157         if (bp->port.pmf)
3158                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3159
3160         /* init Event Queue */
3161         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3162         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3163         eq_data.producer = bp->eq_prod;
3164         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3165         eq_data.sb_id = DEF_SB_ID;
3166         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3167 }
3168
3169
3170 static void bnx2x_e1h_disable(struct bnx2x *bp)
3171 {
3172         int port = BP_PORT(bp);
3173
3174         bnx2x_tx_disable(bp);
3175
3176         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3177 }
3178
3179 static void bnx2x_e1h_enable(struct bnx2x *bp)
3180 {
3181         int port = BP_PORT(bp);
3182
3183         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3184
3185         /* Tx queue should be only reenabled */
3186         netif_tx_wake_all_queues(bp->dev);
3187
3188         /*
3189          * Should not call netif_carrier_on since it will be called if the link
3190          * is up when checking for link state
3191          */
3192 }
3193
3194 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3195
3196 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3197 {
3198         struct eth_stats_info *ether_stat =
3199                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3200
3201         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3202                 ETH_STAT_INFO_VERSION_LEN);
3203
3204         bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3205                                         DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3206                                         ether_stat->mac_local);
3207
3208         ether_stat->mtu_size = bp->dev->mtu;
3209
3210         if (bp->dev->features & NETIF_F_RXCSUM)
3211                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3212         if (bp->dev->features & NETIF_F_TSO)
3213                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3214         ether_stat->feature_flags |= bp->common.boot_mode;
3215
3216         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3217
3218         ether_stat->txq_size = bp->tx_ring_size;
3219         ether_stat->rxq_size = bp->rx_ring_size;
3220 }
3221
3222 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3223 {
3224         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3225         struct fcoe_stats_info *fcoe_stat =
3226                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3227
3228         if (!CNIC_LOADED(bp))
3229                 return;
3230
3231         memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3232                bp->fip_mac, ETH_ALEN);
3233
3234         fcoe_stat->qos_priority =
3235                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3236
3237         /* insert FCoE stats from ramrod response */
3238         if (!NO_FCOE(bp)) {
3239                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3240                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3241                         tstorm_queue_statistics;
3242
3243                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3244                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3245                         xstorm_queue_statistics;
3246
3247                 struct fcoe_statistics_params *fw_fcoe_stat =
3248                         &bp->fw_stats_data->fcoe;
3249
3250                 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3251                        fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3252
3253                 ADD_64(fcoe_stat->rx_bytes_hi,
3254                        fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3255                        fcoe_stat->rx_bytes_lo,
3256                        fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3257
3258                 ADD_64(fcoe_stat->rx_bytes_hi,
3259                        fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3260                        fcoe_stat->rx_bytes_lo,
3261                        fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3262
3263                 ADD_64(fcoe_stat->rx_bytes_hi,
3264                        fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3265                        fcoe_stat->rx_bytes_lo,
3266                        fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3267
3268                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3269                        fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3270
3271                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3272                        fcoe_q_tstorm_stats->rcv_ucast_pkts);
3273
3274                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3275                        fcoe_q_tstorm_stats->rcv_bcast_pkts);
3276
3277                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3278                        fcoe_q_tstorm_stats->rcv_mcast_pkts);
3279
3280                 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3281                        fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3282
3283                 ADD_64(fcoe_stat->tx_bytes_hi,
3284                        fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3285                        fcoe_stat->tx_bytes_lo,
3286                        fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3287
3288                 ADD_64(fcoe_stat->tx_bytes_hi,
3289                        fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3290                        fcoe_stat->tx_bytes_lo,
3291                        fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3292
3293                 ADD_64(fcoe_stat->tx_bytes_hi,
3294                        fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3295                        fcoe_stat->tx_bytes_lo,
3296                        fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3297
3298                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3299                        fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3300
3301                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3302                        fcoe_q_xstorm_stats->ucast_pkts_sent);
3303
3304                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3305                        fcoe_q_xstorm_stats->bcast_pkts_sent);
3306
3307                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3308                        fcoe_q_xstorm_stats->mcast_pkts_sent);
3309         }
3310
3311         /* ask L5 driver to add data to the struct */
3312         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3313 }
3314
3315 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3316 {
3317         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3318         struct iscsi_stats_info *iscsi_stat =
3319                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3320
3321         if (!CNIC_LOADED(bp))
3322                 return;
3323
3324         memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3325                bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3326
3327         iscsi_stat->qos_priority =
3328                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3329
3330         /* ask L5 driver to add data to the struct */
3331         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3332 }
3333
3334 /* called due to MCP event (on pmf):
3335  *      reread new bandwidth configuration
3336  *      configure FW
3337  *      notify others function about the change
3338  */
3339 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3340 {
3341         if (bp->link_vars.link_up) {
3342                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3343                 bnx2x_link_sync_notify(bp);
3344         }
3345         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3346 }
3347
3348 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3349 {
3350         bnx2x_config_mf_bw(bp);
3351         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3352 }
3353
3354 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3355 {
3356         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3357         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3358 }
3359
3360 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3361 {
3362         enum drv_info_opcode op_code;
3363         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3364
3365         /* if drv_info version supported by MFW doesn't match - send NACK */
3366         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3367                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3368                 return;
3369         }
3370
3371         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3372                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3373
3374         memset(&bp->slowpath->drv_info_to_mcp, 0,
3375                sizeof(union drv_info_to_mcp));
3376
3377         switch (op_code) {
3378         case ETH_STATS_OPCODE:
3379                 bnx2x_drv_info_ether_stat(bp);
3380                 break;
3381         case FCOE_STATS_OPCODE:
3382                 bnx2x_drv_info_fcoe_stat(bp);
3383                 break;
3384         case ISCSI_STATS_OPCODE:
3385                 bnx2x_drv_info_iscsi_stat(bp);
3386                 break;
3387         default:
3388                 /* if op code isn't supported - send NACK */
3389                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3390                 return;
3391         }
3392
3393         /* if we got drv_info attn from MFW then these fields are defined in
3394          * shmem2 for sure
3395          */
3396         SHMEM2_WR(bp, drv_info_host_addr_lo,
3397                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3398         SHMEM2_WR(bp, drv_info_host_addr_hi,
3399                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3400
3401         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3402 }
3403
3404 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3405 {
3406         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3407
3408         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3409
3410                 /*
3411                  * This is the only place besides the function initialization
3412                  * where the bp->flags can change so it is done without any
3413                  * locks
3414                  */
3415                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3416                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3417                         bp->flags |= MF_FUNC_DIS;
3418
3419                         bnx2x_e1h_disable(bp);
3420                 } else {
3421                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3422                         bp->flags &= ~MF_FUNC_DIS;
3423
3424                         bnx2x_e1h_enable(bp);
3425                 }
3426                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3427         }
3428         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3429                 bnx2x_config_mf_bw(bp);
3430                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3431         }
3432
3433         /* Report results to MCP */
3434         if (dcc_event)
3435                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3436         else
3437                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3438 }
3439
3440 /* must be called under the spq lock */
3441 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3442 {
3443         struct eth_spe *next_spe = bp->spq_prod_bd;
3444
3445         if (bp->spq_prod_bd == bp->spq_last_bd) {
3446                 bp->spq_prod_bd = bp->spq;
3447                 bp->spq_prod_idx = 0;
3448                 DP(BNX2X_MSG_SP, "end of spq\n");
3449         } else {
3450                 bp->spq_prod_bd++;
3451                 bp->spq_prod_idx++;
3452         }
3453         return next_spe;
3454 }
3455
3456 /* must be called under the spq lock */
3457 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3458 {
3459         int func = BP_FUNC(bp);
3460
3461         /*
3462          * Make sure that BD data is updated before writing the producer:
3463          * BD data is written to the memory, the producer is read from the
3464          * memory, thus we need a full memory barrier to ensure the ordering.
3465          */
3466         mb();
3467
3468         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3469                  bp->spq_prod_idx);
3470         mmiowb();
3471 }
3472
3473 /**
3474  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3475  *
3476  * @cmd:        command to check
3477  * @cmd_type:   command type
3478  */
3479 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3480 {
3481         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3482             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3483             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3484             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3485             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3486             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3487             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3488                 return true;
3489         else
3490                 return false;
3491
3492 }
3493
3494
3495 /**
3496  * bnx2x_sp_post - place a single command on an SP ring
3497  *
3498  * @bp:         driver handle
3499  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3500  * @cid:        SW CID the command is related to
3501  * @data_hi:    command private data address (high 32 bits)
3502  * @data_lo:    command private data address (low 32 bits)
3503  * @cmd_type:   command type (e.g. NONE, ETH)
3504  *
3505  * SP data is handled as if it's always an address pair, thus data fields are
3506  * not swapped to little endian in upper functions. Instead this function swaps
3507  * data as if it's two u32 fields.
3508  */
3509 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3510                   u32 data_hi, u32 data_lo, int cmd_type)
3511 {
3512         struct eth_spe *spe;
3513         u16 type;
3514         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3515
3516 #ifdef BNX2X_STOP_ON_ERROR
3517         if (unlikely(bp->panic)) {
3518                 BNX2X_ERR("Can't post SP when there is panic\n");
3519                 return -EIO;
3520         }
3521 #endif
3522
3523         spin_lock_bh(&bp->spq_lock);
3524
3525         if (common) {
3526                 if (!atomic_read(&bp->eq_spq_left)) {
3527                         BNX2X_ERR("BUG! EQ ring full!\n");
3528                         spin_unlock_bh(&bp->spq_lock);
3529                         bnx2x_panic();
3530                         return -EBUSY;
3531                 }
3532         } else if (!atomic_read(&bp->cq_spq_left)) {
3533                         BNX2X_ERR("BUG! SPQ ring full!\n");
3534                         spin_unlock_bh(&bp->spq_lock);
3535                         bnx2x_panic();
3536                         return -EBUSY;
3537         }
3538
3539         spe = bnx2x_sp_get_next(bp);
3540
3541         /* CID needs port number to be encoded int it */
3542         spe->hdr.conn_and_cmd_data =
3543                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3544                                     HW_CID(bp, cid));
3545
3546         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3547
3548         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3549                  SPE_HDR_FUNCTION_ID);
3550
3551         spe->hdr.type = cpu_to_le16(type);
3552
3553         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3554         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3555
3556         /*
3557          * It's ok if the actual decrement is issued towards the memory
3558          * somewhere between the spin_lock and spin_unlock. Thus no
3559          * more explict memory barrier is needed.
3560          */
3561         if (common)
3562                 atomic_dec(&bp->eq_spq_left);
3563         else
3564                 atomic_dec(&bp->cq_spq_left);
3565
3566
3567         DP(BNX2X_MSG_SP,
3568            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3569            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3570            (u32)(U64_LO(bp->spq_mapping) +
3571            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3572            HW_CID(bp, cid), data_hi, data_lo, type,
3573            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3574
3575         bnx2x_sp_prod_update(bp);
3576         spin_unlock_bh(&bp->spq_lock);
3577         return 0;
3578 }
3579
3580 /* acquire split MCP access lock register */
3581 static int bnx2x_acquire_alr(struct bnx2x *bp)
3582 {
3583         u32 j, val;
3584         int rc = 0;
3585
3586         might_sleep();
3587         for (j = 0; j < 1000; j++) {
3588                 val = (1UL << 31);
3589                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3590                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3591                 if (val & (1L << 31))
3592                         break;
3593
3594                 msleep(5);
3595         }
3596         if (!(val & (1L << 31))) {
3597                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3598                 rc = -EBUSY;
3599         }
3600
3601         return rc;
3602 }
3603
3604 /* release split MCP access lock register */
3605 static void bnx2x_release_alr(struct bnx2x *bp)
3606 {
3607         REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3608 }
3609
3610 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3611 #define BNX2X_DEF_SB_IDX        0x0002
3612
3613 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3614 {
3615         struct host_sp_status_block *def_sb = bp->def_status_blk;
3616         u16 rc = 0;
3617
3618         barrier(); /* status block is written to by the chip */
3619         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3620                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3621                 rc |= BNX2X_DEF_SB_ATT_IDX;
3622         }
3623
3624         if (bp->def_idx != def_sb->sp_sb.running_index) {
3625                 bp->def_idx = def_sb->sp_sb.running_index;
3626                 rc |= BNX2X_DEF_SB_IDX;
3627         }
3628
3629         /* Do not reorder: indecies reading should complete before handling */
3630         barrier();
3631         return rc;
3632 }
3633
3634 /*
3635  * slow path service functions
3636  */
3637
3638 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3639 {
3640         int port = BP_PORT(bp);
3641         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3642                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3643         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3644                                        NIG_REG_MASK_INTERRUPT_PORT0;
3645         u32 aeu_mask;
3646         u32 nig_mask = 0;
3647         u32 reg_addr;
3648
3649         if (bp->attn_state & asserted)
3650                 BNX2X_ERR("IGU ERROR\n");
3651
3652         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3653         aeu_mask = REG_RD(bp, aeu_addr);
3654
3655         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3656            aeu_mask, asserted);
3657         aeu_mask &= ~(asserted & 0x3ff);
3658         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3659
3660         REG_WR(bp, aeu_addr, aeu_mask);
3661         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3662
3663         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3664         bp->attn_state |= asserted;
3665         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3666
3667         if (asserted & ATTN_HARD_WIRED_MASK) {
3668                 if (asserted & ATTN_NIG_FOR_FUNC) {
3669
3670                         bnx2x_acquire_phy_lock(bp);
3671
3672                         /* save nig interrupt mask */
3673                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3674
3675                         /* If nig_mask is not set, no need to call the update
3676                          * function.
3677                          */
3678                         if (nig_mask) {
3679                                 REG_WR(bp, nig_int_mask_addr, 0);
3680
3681                                 bnx2x_link_attn(bp);
3682                         }
3683
3684                         /* handle unicore attn? */
3685                 }
3686                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3687                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3688
3689                 if (asserted & GPIO_2_FUNC)
3690                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3691
3692                 if (asserted & GPIO_3_FUNC)
3693                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3694
3695                 if (asserted & GPIO_4_FUNC)
3696                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3697
3698                 if (port == 0) {
3699                         if (asserted & ATTN_GENERAL_ATTN_1) {
3700                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3701                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3702                         }
3703                         if (asserted & ATTN_GENERAL_ATTN_2) {
3704                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3705                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3706                         }
3707                         if (asserted & ATTN_GENERAL_ATTN_3) {
3708                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3709                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3710                         }
3711                 } else {
3712                         if (asserted & ATTN_GENERAL_ATTN_4) {
3713                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3714                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3715                         }
3716                         if (asserted & ATTN_GENERAL_ATTN_5) {
3717                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3718                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3719                         }
3720                         if (asserted & ATTN_GENERAL_ATTN_6) {
3721                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3722                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3723                         }
3724                 }
3725
3726         } /* if hardwired */
3727
3728         if (bp->common.int_block == INT_BLOCK_HC)
3729                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3730                             COMMAND_REG_ATTN_BITS_SET);
3731         else
3732                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3733
3734         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3735            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3736         REG_WR(bp, reg_addr, asserted);
3737
3738         /* now set back the mask */
3739         if (asserted & ATTN_NIG_FOR_FUNC) {
3740                 /* Verify that IGU ack through BAR was written before restoring
3741                  * NIG mask. This loop should exit after 2-3 iterations max.
3742                  */
3743                 if (bp->common.int_block != INT_BLOCK_HC) {
3744                         u32 cnt = 0, igu_acked;
3745                         do {
3746                                 igu_acked = REG_RD(bp,
3747                                                    IGU_REG_ATTENTION_ACK_BITS);
3748                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3749                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3750                         if (!igu_acked)
3751                                 DP(NETIF_MSG_HW,
3752                                    "Failed to verify IGU ack on time\n");
3753                         barrier();
3754                 }
3755                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3756                 bnx2x_release_phy_lock(bp);
3757         }
3758 }
3759
3760 static void bnx2x_fan_failure(struct bnx2x *bp)
3761 {
3762         int port = BP_PORT(bp);
3763         u32 ext_phy_config;
3764         /* mark the failure */
3765         ext_phy_config =
3766                 SHMEM_RD(bp,
3767                          dev_info.port_hw_config[port].external_phy_config);
3768
3769         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3770         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3771         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3772                  ext_phy_config);
3773
3774         /* log the failure */
3775         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3776                             "Please contact OEM Support for assistance\n");
3777
3778         /*
3779          * Scheudle device reset (unload)
3780          * This is due to some boards consuming sufficient power when driver is
3781          * up to overheat if fan fails.
3782          */
3783         smp_mb__before_clear_bit();
3784         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3785         smp_mb__after_clear_bit();
3786         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3787
3788 }
3789
3790 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3791 {
3792         int port = BP_PORT(bp);
3793         int reg_offset;
3794         u32 val;
3795
3796         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3797                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3798
3799         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3800
3801                 val = REG_RD(bp, reg_offset);
3802                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3803                 REG_WR(bp, reg_offset, val);
3804
3805                 BNX2X_ERR("SPIO5 hw attention\n");
3806
3807                 /* Fan failure attention */
3808                 bnx2x_hw_reset_phy(&bp->link_params);
3809                 bnx2x_fan_failure(bp);
3810         }
3811
3812         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3813                 bnx2x_acquire_phy_lock(bp);
3814                 bnx2x_handle_module_detect_int(&bp->link_params);
3815                 bnx2x_release_phy_lock(bp);
3816         }
3817
3818         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3819
3820                 val = REG_RD(bp, reg_offset);
3821                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3822                 REG_WR(bp, reg_offset, val);
3823
3824                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3825                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3826                 bnx2x_panic();
3827         }
3828 }
3829
3830 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3831 {
3832         u32 val;
3833
3834         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3835
3836                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3837                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3838                 /* DORQ discard attention */
3839                 if (val & 0x2)
3840                         BNX2X_ERR("FATAL error from DORQ\n");
3841         }
3842
3843         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3844
3845                 int port = BP_PORT(bp);
3846                 int reg_offset;
3847
3848                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3849                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3850
3851                 val = REG_RD(bp, reg_offset);
3852                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3853                 REG_WR(bp, reg_offset, val);
3854
3855                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3856                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3857                 bnx2x_panic();
3858         }
3859 }
3860
3861 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3862 {
3863         u32 val;
3864
3865         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3866
3867                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3868                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3869                 /* CFC error attention */
3870                 if (val & 0x2)
3871                         BNX2X_ERR("FATAL error from CFC\n");
3872         }
3873
3874         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3875                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3876                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3877                 /* RQ_USDMDP_FIFO_OVERFLOW */
3878                 if (val & 0x18000)
3879                         BNX2X_ERR("FATAL error from PXP\n");
3880
3881                 if (!CHIP_IS_E1x(bp)) {
3882                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3883                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3884                 }
3885         }
3886
3887         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3888
3889                 int port = BP_PORT(bp);
3890                 int reg_offset;
3891
3892                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3893                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3894
3895                 val = REG_RD(bp, reg_offset);
3896                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3897                 REG_WR(bp, reg_offset, val);
3898
3899                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3900                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3901                 bnx2x_panic();
3902         }
3903 }
3904
3905 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3906 {
3907         u32 val;
3908
3909         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3910
3911                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3912                         int func = BP_FUNC(bp);
3913
3914                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3915                         bnx2x_read_mf_cfg(bp);
3916                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3917                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3918                         val = SHMEM_RD(bp,
3919                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3920                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3921                                 bnx2x_dcc_event(bp,
3922                                             (val & DRV_STATUS_DCC_EVENT_MASK));
3923
3924                         if (val & DRV_STATUS_SET_MF_BW)
3925                                 bnx2x_set_mf_bw(bp);
3926
3927                         if (val & DRV_STATUS_DRV_INFO_REQ)
3928                                 bnx2x_handle_drv_info_req(bp);
3929
3930                         if (val & DRV_STATUS_VF_DISABLED)
3931                                 bnx2x_vf_handle_flr_event(bp);
3932
3933                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3934                                 bnx2x_pmf_update(bp);
3935
3936                         if (bp->port.pmf &&
3937                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3938                                 bp->dcbx_enabled > 0)
3939                                 /* start dcbx state machine */
3940                                 bnx2x_dcbx_set_params(bp,
3941                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
3942                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
3943                                 bnx2x_handle_afex_cmd(bp,
3944                                         val & DRV_STATUS_AFEX_EVENT_MASK);
3945                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3946                                 bnx2x_handle_eee_event(bp);
3947                         if (bp->link_vars.periodic_flags &
3948                             PERIODIC_FLAGS_LINK_EVENT) {
3949                                 /*  sync with link */
3950                                 bnx2x_acquire_phy_lock(bp);
3951                                 bp->link_vars.periodic_flags &=
3952                                         ~PERIODIC_FLAGS_LINK_EVENT;
3953                                 bnx2x_release_phy_lock(bp);
3954                                 if (IS_MF(bp))
3955                                         bnx2x_link_sync_notify(bp);
3956                                 bnx2x_link_report(bp);
3957                         }
3958                         /* Always call it here: bnx2x_link_report() will
3959                          * prevent the link indication duplication.
3960                          */
3961                         bnx2x__link_status_update(bp);
3962                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3963
3964                         BNX2X_ERR("MC assert!\n");
3965                         bnx2x_mc_assert(bp);
3966                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3967                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3968                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3969                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3970                         bnx2x_panic();
3971
3972                 } else if (attn & BNX2X_MCP_ASSERT) {
3973
3974                         BNX2X_ERR("MCP assert!\n");
3975                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3976                         bnx2x_fw_dump(bp);
3977
3978                 } else
3979                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3980         }
3981
3982         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3983                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3984                 if (attn & BNX2X_GRC_TIMEOUT) {
3985                         val = CHIP_IS_E1(bp) ? 0 :
3986                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3987                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
3988                 }
3989                 if (attn & BNX2X_GRC_RSV) {
3990                         val = CHIP_IS_E1(bp) ? 0 :
3991                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3992                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
3993                 }
3994                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3995         }
3996 }
3997
3998 /*
3999  * Bits map:
4000  * 0-7   - Engine0 load counter.
4001  * 8-15  - Engine1 load counter.
4002  * 16    - Engine0 RESET_IN_PROGRESS bit.
4003  * 17    - Engine1 RESET_IN_PROGRESS bit.
4004  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4005  *         on the engine
4006  * 19    - Engine1 ONE_IS_LOADED.
4007  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4008  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4009  *         just the one belonging to its engine).
4010  *
4011  */
4012 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4013
4014 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4015 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4016 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4017 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4018 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4019 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4020 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4021
4022 /*
4023  * Set the GLOBAL_RESET bit.
4024  *
4025  * Should be run under rtnl lock
4026  */
4027 void bnx2x_set_reset_global(struct bnx2x *bp)
4028 {
4029         u32 val;
4030         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4031         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4032         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4033         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4034 }
4035
4036 /*
4037  * Clear the GLOBAL_RESET bit.
4038  *
4039  * Should be run under rtnl lock
4040  */
4041 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4042 {
4043         u32 val;
4044         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4045         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4046         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4047         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4048 }
4049
4050 /*
4051  * Checks the GLOBAL_RESET bit.
4052  *
4053  * should be run under rtnl lock
4054  */
4055 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4056 {
4057         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4058
4059         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4060         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4061 }
4062
4063 /*
4064  * Clear RESET_IN_PROGRESS bit for the current engine.
4065  *
4066  * Should be run under rtnl lock
4067  */
4068 static void bnx2x_set_reset_done(struct bnx2x *bp)
4069 {
4070         u32 val;
4071         u32 bit = BP_PATH(bp) ?
4072                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4073         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4074         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4075
4076         /* Clear the bit */
4077         val &= ~bit;
4078         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4079
4080         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4081 }
4082
4083 /*
4084  * Set RESET_IN_PROGRESS for the current engine.
4085  *
4086  * should be run under rtnl lock
4087  */
4088 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4089 {
4090         u32 val;
4091         u32 bit = BP_PATH(bp) ?
4092                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4093         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4094         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4095
4096         /* Set the bit */
4097         val |= bit;
4098         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4099         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4100 }
4101
4102 /*
4103  * Checks the RESET_IN_PROGRESS bit for the given engine.
4104  * should be run under rtnl lock
4105  */
4106 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4107 {
4108         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4109         u32 bit = engine ?
4110                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4111
4112         /* return false if bit is set */
4113         return (val & bit) ? false : true;
4114 }
4115
4116 /*
4117  * set pf load for the current pf.
4118  *
4119  * should be run under rtnl lock
4120  */
4121 void bnx2x_set_pf_load(struct bnx2x *bp)
4122 {
4123         u32 val1, val;
4124         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4125                              BNX2X_PATH0_LOAD_CNT_MASK;
4126         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4127                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4128
4129         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4130         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4131
4132         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4133
4134         /* get the current counter value */
4135         val1 = (val & mask) >> shift;
4136
4137         /* set bit of that PF */
4138         val1 |= (1 << bp->pf_num);
4139
4140         /* clear the old value */
4141         val &= ~mask;
4142
4143         /* set the new one */
4144         val |= ((val1 << shift) & mask);
4145
4146         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4147         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4148 }
4149
4150 /**
4151  * bnx2x_clear_pf_load - clear pf load mark
4152  *
4153  * @bp:         driver handle
4154  *
4155  * Should be run under rtnl lock.
4156  * Decrements the load counter for the current engine. Returns
4157  * whether other functions are still loaded
4158  */
4159 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4160 {
4161         u32 val1, val;
4162         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4163                              BNX2X_PATH0_LOAD_CNT_MASK;
4164         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4165                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4166
4167         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4168         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4169         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4170
4171         /* get the current counter value */
4172         val1 = (val & mask) >> shift;
4173
4174         /* clear bit of that PF */
4175         val1 &= ~(1 << bp->pf_num);
4176
4177         /* clear the old value */
4178         val &= ~mask;
4179
4180         /* set the new one */
4181         val |= ((val1 << shift) & mask);
4182
4183         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4184         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4185         return val1 != 0;
4186 }
4187
4188 /*
4189  * Read the load status for the current engine.
4190  *
4191  * should be run under rtnl lock
4192  */
4193 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4194 {
4195         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4196                              BNX2X_PATH0_LOAD_CNT_MASK);
4197         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4198                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4199         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4200
4201         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4202
4203         val = (val & mask) >> shift;
4204
4205         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4206            engine, val);
4207
4208         return val != 0;
4209 }
4210
4211 static void _print_next_block(int idx, const char *blk)
4212 {
4213         pr_cont("%s%s", idx ? ", " : "", blk);
4214 }
4215
4216 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4217                                            bool print)
4218 {
4219         int i = 0;
4220         u32 cur_bit = 0;
4221         for (i = 0; sig; i++) {
4222                 cur_bit = ((u32)0x1 << i);
4223                 if (sig & cur_bit) {
4224                         switch (cur_bit) {
4225                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4226                                 if (print)
4227                                         _print_next_block(par_num++, "BRB");
4228                                 break;
4229                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4230                                 if (print)
4231                                         _print_next_block(par_num++, "PARSER");
4232                                 break;
4233                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4234                                 if (print)
4235                                         _print_next_block(par_num++, "TSDM");
4236                                 break;
4237                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4238                                 if (print)
4239                                         _print_next_block(par_num++,
4240                                                           "SEARCHER");
4241                                 break;
4242                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4243                                 if (print)
4244                                         _print_next_block(par_num++, "TCM");
4245                                 break;
4246                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4247                                 if (print)
4248                                         _print_next_block(par_num++, "TSEMI");
4249                                 break;
4250                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4251                                 if (print)
4252                                         _print_next_block(par_num++, "XPB");
4253                                 break;
4254                         }
4255
4256                         /* Clear the bit */
4257                         sig &= ~cur_bit;
4258                 }
4259         }
4260
4261         return par_num;
4262 }
4263
4264 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4265                                            bool *global, bool print)
4266 {
4267         int i = 0;
4268         u32 cur_bit = 0;
4269         for (i = 0; sig; i++) {
4270                 cur_bit = ((u32)0x1 << i);
4271                 if (sig & cur_bit) {
4272                         switch (cur_bit) {
4273                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4274                                 if (print)
4275                                         _print_next_block(par_num++, "PBF");
4276                                 break;
4277                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4278                                 if (print)
4279                                         _print_next_block(par_num++, "QM");
4280                                 break;
4281                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4282                                 if (print)
4283                                         _print_next_block(par_num++, "TM");
4284                                 break;
4285                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4286                                 if (print)
4287                                         _print_next_block(par_num++, "XSDM");
4288                                 break;
4289                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4290                                 if (print)
4291                                         _print_next_block(par_num++, "XCM");
4292                                 break;
4293                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4294                                 if (print)
4295                                         _print_next_block(par_num++, "XSEMI");
4296                                 break;
4297                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4298                                 if (print)
4299                                         _print_next_block(par_num++,
4300                                                           "DOORBELLQ");
4301                                 break;
4302                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4303                                 if (print)
4304                                         _print_next_block(par_num++, "NIG");
4305                                 break;
4306                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4307                                 if (print)
4308                                         _print_next_block(par_num++,
4309                                                           "VAUX PCI CORE");
4310                                 *global = true;
4311                                 break;
4312                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4313                                 if (print)
4314                                         _print_next_block(par_num++, "DEBUG");
4315                                 break;
4316                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4317                                 if (print)
4318                                         _print_next_block(par_num++, "USDM");
4319                                 break;
4320                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4321                                 if (print)
4322                                         _print_next_block(par_num++, "UCM");
4323                                 break;
4324                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4325                                 if (print)
4326                                         _print_next_block(par_num++, "USEMI");
4327                                 break;
4328                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4329                                 if (print)
4330                                         _print_next_block(par_num++, "UPB");
4331                                 break;
4332                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4333                                 if (print)
4334                                         _print_next_block(par_num++, "CSDM");
4335                                 break;
4336                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4337                                 if (print)
4338                                         _print_next_block(par_num++, "CCM");
4339                                 break;
4340                         }
4341
4342                         /* Clear the bit */
4343                         sig &= ~cur_bit;
4344                 }
4345         }
4346
4347         return par_num;
4348 }
4349
4350 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4351                                            bool print)
4352 {
4353         int i = 0;
4354         u32 cur_bit = 0;
4355         for (i = 0; sig; i++) {
4356                 cur_bit = ((u32)0x1 << i);
4357                 if (sig & cur_bit) {
4358                         switch (cur_bit) {
4359                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4360                                 if (print)
4361                                         _print_next_block(par_num++, "CSEMI");
4362                                 break;
4363                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4364                                 if (print)
4365                                         _print_next_block(par_num++, "PXP");
4366                                 break;
4367                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4368                                 if (print)
4369                                         _print_next_block(par_num++,
4370                                         "PXPPCICLOCKCLIENT");
4371                                 break;
4372                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4373                                 if (print)
4374                                         _print_next_block(par_num++, "CFC");
4375                                 break;
4376                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4377                                 if (print)
4378                                         _print_next_block(par_num++, "CDU");
4379                                 break;
4380                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4381                                 if (print)
4382                                         _print_next_block(par_num++, "DMAE");
4383                                 break;
4384                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4385                                 if (print)
4386                                         _print_next_block(par_num++, "IGU");
4387                                 break;
4388                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4389                                 if (print)
4390                                         _print_next_block(par_num++, "MISC");
4391                                 break;
4392                         }
4393
4394                         /* Clear the bit */
4395                         sig &= ~cur_bit;
4396                 }
4397         }
4398
4399         return par_num;
4400 }
4401
4402 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4403                                            bool *global, bool print)
4404 {
4405         int i = 0;
4406         u32 cur_bit = 0;
4407         for (i = 0; sig; i++) {
4408                 cur_bit = ((u32)0x1 << i);
4409                 if (sig & cur_bit) {
4410                         switch (cur_bit) {
4411                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4412                                 if (print)
4413                                         _print_next_block(par_num++, "MCP ROM");
4414                                 *global = true;
4415                                 break;
4416                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4417                                 if (print)
4418                                         _print_next_block(par_num++,
4419                                                           "MCP UMP RX");
4420                                 *global = true;
4421                                 break;
4422                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4423                                 if (print)
4424                                         _print_next_block(par_num++,
4425                                                           "MCP UMP TX");
4426                                 *global = true;
4427                                 break;
4428                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4429                                 if (print)
4430                                         _print_next_block(par_num++,
4431                                                           "MCP SCPAD");
4432                                 *global = true;
4433                                 break;
4434                         }
4435
4436                         /* Clear the bit */
4437                         sig &= ~cur_bit;
4438                 }
4439         }
4440
4441         return par_num;
4442 }
4443
4444 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4445                                            bool print)
4446 {
4447         int i = 0;
4448         u32 cur_bit = 0;
4449         for (i = 0; sig; i++) {
4450                 cur_bit = ((u32)0x1 << i);
4451                 if (sig & cur_bit) {
4452                         switch (cur_bit) {
4453                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4454                                 if (print)
4455                                         _print_next_block(par_num++, "PGLUE_B");
4456                                 break;
4457                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4458                                 if (print)
4459                                         _print_next_block(par_num++, "ATC");
4460                                 break;
4461                         }
4462
4463                         /* Clear the bit */
4464                         sig &= ~cur_bit;
4465                 }
4466         }
4467
4468         return par_num;
4469 }
4470
4471 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4472                               u32 *sig)
4473 {
4474         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4475             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4476             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4477             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4478             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4479                 int par_num = 0;
4480                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4481                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4482                           sig[0] & HW_PRTY_ASSERT_SET_0,
4483                           sig[1] & HW_PRTY_ASSERT_SET_1,
4484                           sig[2] & HW_PRTY_ASSERT_SET_2,
4485                           sig[3] & HW_PRTY_ASSERT_SET_3,
4486                           sig[4] & HW_PRTY_ASSERT_SET_4);
4487                 if (print)
4488                         netdev_err(bp->dev,
4489                                    "Parity errors detected in blocks: ");
4490                 par_num = bnx2x_check_blocks_with_parity0(
4491                         sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4492                 par_num = bnx2x_check_blocks_with_parity1(
4493                         sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4494                 par_num = bnx2x_check_blocks_with_parity2(
4495                         sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4496                 par_num = bnx2x_check_blocks_with_parity3(
4497                         sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4498                 par_num = bnx2x_check_blocks_with_parity4(
4499                         sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4500
4501                 if (print)
4502                         pr_cont("\n");
4503
4504                 return true;
4505         } else
4506                 return false;
4507 }
4508
4509 /**
4510  * bnx2x_chk_parity_attn - checks for parity attentions.
4511  *
4512  * @bp:         driver handle
4513  * @global:     true if there was a global attention
4514  * @print:      show parity attention in syslog
4515  */
4516 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4517 {
4518         struct attn_route attn = { {0} };
4519         int port = BP_PORT(bp);
4520
4521         attn.sig[0] = REG_RD(bp,
4522                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4523                              port*4);
4524         attn.sig[1] = REG_RD(bp,
4525                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4526                              port*4);
4527         attn.sig[2] = REG_RD(bp,
4528                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4529                              port*4);
4530         attn.sig[3] = REG_RD(bp,
4531                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4532                              port*4);
4533
4534         if (!CHIP_IS_E1x(bp))
4535                 attn.sig[4] = REG_RD(bp,
4536                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4537                                      port*4);
4538
4539         return bnx2x_parity_attn(bp, global, print, attn.sig);
4540 }
4541
4542
4543 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4544 {
4545         u32 val;
4546         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4547
4548                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4549                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4550                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4551                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4552                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4553                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4554                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4555                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4556                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4557                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4558                 if (val &
4559                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4560                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4561                 if (val &
4562                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4563                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4564                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4565                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4566                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4567                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4568                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4569                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4570         }
4571         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4572                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4573                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4574                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4575                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4576                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4577                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4578                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4579                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4580                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4581                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4582                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4583                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4584                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4585                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4586         }
4587
4588         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4589                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4590                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4591                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4592                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4593         }
4594
4595 }
4596
4597 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4598 {
4599         struct attn_route attn, *group_mask;
4600         int port = BP_PORT(bp);
4601         int index;
4602         u32 reg_addr;
4603         u32 val;
4604         u32 aeu_mask;
4605         bool global = false;
4606
4607         /* need to take HW lock because MCP or other port might also
4608            try to handle this event */
4609         bnx2x_acquire_alr(bp);
4610
4611         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4612 #ifndef BNX2X_STOP_ON_ERROR
4613                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4614                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4615                 /* Disable HW interrupts */
4616                 bnx2x_int_disable(bp);
4617                 /* In case of parity errors don't handle attentions so that
4618                  * other function would "see" parity errors.
4619                  */
4620 #else
4621                 bnx2x_panic();
4622 #endif
4623                 bnx2x_release_alr(bp);
4624                 return;
4625         }
4626
4627         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4628         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4629         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4630         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4631         if (!CHIP_IS_E1x(bp))
4632                 attn.sig[4] =
4633                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4634         else
4635                 attn.sig[4] = 0;
4636
4637         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4638            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4639
4640         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4641                 if (deasserted & (1 << index)) {
4642                         group_mask = &bp->attn_group[index];
4643
4644                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4645                            index,
4646                            group_mask->sig[0], group_mask->sig[1],
4647                            group_mask->sig[2], group_mask->sig[3],
4648                            group_mask->sig[4]);
4649
4650                         bnx2x_attn_int_deasserted4(bp,
4651                                         attn.sig[4] & group_mask->sig[4]);
4652                         bnx2x_attn_int_deasserted3(bp,
4653                                         attn.sig[3] & group_mask->sig[3]);
4654                         bnx2x_attn_int_deasserted1(bp,
4655                                         attn.sig[1] & group_mask->sig[1]);
4656                         bnx2x_attn_int_deasserted2(bp,
4657                                         attn.sig[2] & group_mask->sig[2]);
4658                         bnx2x_attn_int_deasserted0(bp,
4659                                         attn.sig[0] & group_mask->sig[0]);
4660                 }
4661         }
4662
4663         bnx2x_release_alr(bp);
4664
4665         if (bp->common.int_block == INT_BLOCK_HC)
4666                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4667                             COMMAND_REG_ATTN_BITS_CLR);
4668         else
4669                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4670
4671         val = ~deasserted;
4672         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4673            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4674         REG_WR(bp, reg_addr, val);
4675
4676         if (~bp->attn_state & deasserted)
4677                 BNX2X_ERR("IGU ERROR\n");
4678
4679         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4680                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4681
4682         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4683         aeu_mask = REG_RD(bp, reg_addr);
4684
4685         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4686            aeu_mask, deasserted);
4687         aeu_mask |= (deasserted & 0x3ff);
4688         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4689
4690         REG_WR(bp, reg_addr, aeu_mask);
4691         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4692
4693         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4694         bp->attn_state &= ~deasserted;
4695         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4696 }
4697
4698 static void bnx2x_attn_int(struct bnx2x *bp)
4699 {
4700         /* read local copy of bits */
4701         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4702                                                                 attn_bits);
4703         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4704                                                                 attn_bits_ack);
4705         u32 attn_state = bp->attn_state;
4706
4707         /* look for changed bits */
4708         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4709         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4710
4711         DP(NETIF_MSG_HW,
4712            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4713            attn_bits, attn_ack, asserted, deasserted);
4714
4715         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4716                 BNX2X_ERR("BAD attention state\n");
4717
4718         /* handle bits that were raised */
4719         if (asserted)
4720                 bnx2x_attn_int_asserted(bp, asserted);
4721
4722         if (deasserted)
4723                 bnx2x_attn_int_deasserted(bp, deasserted);
4724 }
4725
4726 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4727                       u16 index, u8 op, u8 update)
4728 {
4729         u32 igu_addr = bp->igu_base_addr;
4730         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4731         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4732                              igu_addr);
4733 }
4734
4735 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4736 {
4737         /* No memory barriers */
4738         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4739         mmiowb(); /* keep prod updates ordered */
4740 }
4741
4742 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4743                                       union event_ring_elem *elem)
4744 {
4745         u8 err = elem->message.error;
4746
4747         if (!bp->cnic_eth_dev.starting_cid  ||
4748             (cid < bp->cnic_eth_dev.starting_cid &&
4749             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4750                 return 1;
4751
4752         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4753
4754         if (unlikely(err)) {
4755
4756                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4757                           cid);
4758                 bnx2x_panic_dump(bp);
4759         }
4760         bnx2x_cnic_cfc_comp(bp, cid, err);
4761         return 0;
4762 }
4763
4764 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4765 {
4766         struct bnx2x_mcast_ramrod_params rparam;
4767         int rc;
4768
4769         memset(&rparam, 0, sizeof(rparam));
4770
4771         rparam.mcast_obj = &bp->mcast_obj;
4772
4773         netif_addr_lock_bh(bp->dev);
4774
4775         /* Clear pending state for the last command */
4776         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4777
4778         /* If there are pending mcast commands - send them */
4779         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4780                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4781                 if (rc < 0)
4782                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4783                                   rc);
4784         }
4785
4786         netif_addr_unlock_bh(bp->dev);
4787 }
4788
4789 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4790                                             union event_ring_elem *elem)
4791 {
4792         unsigned long ramrod_flags = 0;
4793         int rc = 0;
4794         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4795         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4796
4797         /* Always push next commands out, don't wait here */
4798         __set_bit(RAMROD_CONT, &ramrod_flags);
4799
4800         switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4801         case BNX2X_FILTER_MAC_PENDING:
4802                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4803                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4804                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4805                 else
4806                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4807
4808                 break;
4809         case BNX2X_FILTER_MCAST_PENDING:
4810                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4811                 /* This is only relevant for 57710 where multicast MACs are
4812                  * configured as unicast MACs using the same ramrod.
4813                  */
4814                 bnx2x_handle_mcast_eqe(bp);
4815                 return;
4816         default:
4817                 BNX2X_ERR("Unsupported classification command: %d\n",
4818                           elem->message.data.eth_event.echo);
4819                 return;
4820         }
4821
4822         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4823
4824         if (rc < 0)
4825                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4826         else if (rc > 0)
4827                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4828
4829 }
4830
4831 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4832
4833 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4834 {
4835         netif_addr_lock_bh(bp->dev);
4836
4837         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4838
4839         /* Send rx_mode command again if was requested */
4840         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4841                 bnx2x_set_storm_rx_mode(bp);
4842         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4843                                     &bp->sp_state))
4844                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4845         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4846                                     &bp->sp_state))
4847                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4848
4849         netif_addr_unlock_bh(bp->dev);
4850 }
4851
4852 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4853                                               union event_ring_elem *elem)
4854 {
4855         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4856                 DP(BNX2X_MSG_SP,
4857                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4858                    elem->message.data.vif_list_event.func_bit_map);
4859                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4860                         elem->message.data.vif_list_event.func_bit_map);
4861         } else if (elem->message.data.vif_list_event.echo ==
4862                    VIF_LIST_RULE_SET) {
4863                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4864                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4865         }
4866 }
4867
4868 /* called with rtnl_lock */
4869 static void bnx2x_after_function_update(struct bnx2x *bp)
4870 {
4871         int q, rc;
4872         struct bnx2x_fastpath *fp;
4873         struct bnx2x_queue_state_params queue_params = {NULL};
4874         struct bnx2x_queue_update_params *q_update_params =
4875                 &queue_params.params.update;
4876
4877         /* Send Q update command with afex vlan removal values  for all Qs */
4878         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4879
4880         /* set silent vlan removal values according to vlan mode */
4881         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4882                   &q_update_params->update_flags);
4883         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4884                   &q_update_params->update_flags);
4885         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4886
4887         /* in access mode mark mask and value are 0 to strip all vlans */
4888         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4889                 q_update_params->silent_removal_value = 0;
4890                 q_update_params->silent_removal_mask = 0;
4891         } else {
4892                 q_update_params->silent_removal_value =
4893                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4894                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4895         }
4896
4897         for_each_eth_queue(bp, q) {
4898                 /* Set the appropriate Queue object */
4899                 fp = &bp->fp[q];
4900                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4901
4902                 /* send the ramrod */
4903                 rc = bnx2x_queue_state_change(bp, &queue_params);
4904                 if (rc < 0)
4905                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4906                                   q);
4907         }
4908
4909         if (!NO_FCOE(bp)) {
4910                 fp = &bp->fp[FCOE_IDX(bp)];
4911                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4912
4913                 /* clear pending completion bit */
4914                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4915
4916                 /* mark latest Q bit */
4917                 smp_mb__before_clear_bit();
4918                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4919                 smp_mb__after_clear_bit();
4920
4921                 /* send Q update ramrod for FCoE Q */
4922                 rc = bnx2x_queue_state_change(bp, &queue_params);
4923                 if (rc < 0)
4924                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4925                                   q);
4926         } else {
4927                 /* If no FCoE ring - ACK MCP now */
4928                 bnx2x_link_report(bp);
4929                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4930         }
4931 }
4932
4933 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4934         struct bnx2x *bp, u32 cid)
4935 {
4936         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4937
4938         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4939                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4940         else
4941                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4942 }
4943
4944 static void bnx2x_eq_int(struct bnx2x *bp)
4945 {
4946         u16 hw_cons, sw_cons, sw_prod;
4947         union event_ring_elem *elem;
4948         u8 echo;
4949         u32 cid;
4950         u8 opcode;
4951         int rc, spqe_cnt = 0;
4952         struct bnx2x_queue_sp_obj *q_obj;
4953         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4954         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4955
4956         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4957
4958         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4959          * when we get the the next-page we nned to adjust so the loop
4960          * condition below will be met. The next element is the size of a
4961          * regular element and hence incrementing by 1
4962          */
4963         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4964                 hw_cons++;
4965
4966         /* This function may never run in parallel with itself for a
4967          * specific bp, thus there is no need in "paired" read memory
4968          * barrier here.
4969          */
4970         sw_cons = bp->eq_cons;
4971         sw_prod = bp->eq_prod;
4972
4973         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
4974                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4975
4976         for (; sw_cons != hw_cons;
4977               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4978
4979
4980                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4981
4982                 rc = bnx2x_iov_eq_sp_event(bp, elem);
4983                 if (!rc) {
4984                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
4985                            rc);
4986                         goto next_spqe;
4987                 }
4988                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4989                 opcode = elem->message.opcode;
4990
4991
4992                 /* handle eq element */
4993                 switch (opcode) {
4994                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
4995                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
4996                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
4997                         continue;
4998
4999                 case EVENT_RING_OPCODE_STAT_QUERY:
5000                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5001                            "got statistics comp event %d\n",
5002                            bp->stats_comp++);
5003                         /* nothing to do with stats comp */
5004                         goto next_spqe;
5005
5006                 case EVENT_RING_OPCODE_CFC_DEL:
5007                         /* handle according to cid range */
5008                         /*
5009                          * we may want to verify here that the bp state is
5010                          * HALTING
5011                          */
5012                         DP(BNX2X_MSG_SP,
5013                            "got delete ramrod for MULTI[%d]\n", cid);
5014
5015                         if (CNIC_LOADED(bp) &&
5016                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5017                                 goto next_spqe;
5018
5019                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5020
5021                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5022                                 break;
5023
5024
5025
5026                         goto next_spqe;
5027
5028                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5029                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5030                         if (f_obj->complete_cmd(bp, f_obj,
5031                                                 BNX2X_F_CMD_TX_STOP))
5032                                 break;
5033                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5034                         goto next_spqe;
5035
5036                 case EVENT_RING_OPCODE_START_TRAFFIC:
5037                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5038                         if (f_obj->complete_cmd(bp, f_obj,
5039                                                 BNX2X_F_CMD_TX_START))
5040                                 break;
5041                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5042                         goto next_spqe;
5043
5044                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5045                         echo = elem->message.data.function_update_event.echo;
5046                         if (echo == SWITCH_UPDATE) {
5047                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5048                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5049                                 if (f_obj->complete_cmd(
5050                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5051                                         break;
5052
5053                         } else {
5054                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5055                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5056                                 f_obj->complete_cmd(bp, f_obj,
5057                                                     BNX2X_F_CMD_AFEX_UPDATE);
5058
5059                                 /* We will perform the Queues update from
5060                                  * sp_rtnl task as all Queue SP operations
5061                                  * should run under rtnl_lock.
5062                                  */
5063                                 smp_mb__before_clear_bit();
5064                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5065                                         &bp->sp_rtnl_state);
5066                                 smp_mb__after_clear_bit();
5067
5068                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5069                         }
5070
5071                         goto next_spqe;
5072
5073                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5074                         f_obj->complete_cmd(bp, f_obj,
5075                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5076                         bnx2x_after_afex_vif_lists(bp, elem);
5077                         goto next_spqe;
5078                 case EVENT_RING_OPCODE_FUNCTION_START:
5079                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5080                            "got FUNC_START ramrod\n");
5081                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5082                                 break;
5083
5084                         goto next_spqe;
5085
5086                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5087                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5088                            "got FUNC_STOP ramrod\n");
5089                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5090                                 break;
5091
5092                         goto next_spqe;
5093                 }
5094
5095                 switch (opcode | bp->state) {
5096                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5097                       BNX2X_STATE_OPEN):
5098                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5099                       BNX2X_STATE_OPENING_WAIT4_PORT):
5100                         cid = elem->message.data.eth_event.echo &
5101                                 BNX2X_SWCID_MASK;
5102                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5103                            cid);
5104                         rss_raw->clear_pending(rss_raw);
5105                         break;
5106
5107                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5108                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5109                 case (EVENT_RING_OPCODE_SET_MAC |
5110                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5111                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5112                       BNX2X_STATE_OPEN):
5113                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5114                       BNX2X_STATE_DIAG):
5115                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5116                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5117                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5118                         bnx2x_handle_classification_eqe(bp, elem);
5119                         break;
5120
5121                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5122                       BNX2X_STATE_OPEN):
5123                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5124                       BNX2X_STATE_DIAG):
5125                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5126                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5127                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5128                         bnx2x_handle_mcast_eqe(bp);
5129                         break;
5130
5131                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5132                       BNX2X_STATE_OPEN):
5133                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5134                       BNX2X_STATE_DIAG):
5135                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5136                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5137                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5138                         bnx2x_handle_rx_mode_eqe(bp);
5139                         break;
5140                 default:
5141                         /* unknown event log error and continue */
5142                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5143                                   elem->message.opcode, bp->state);
5144                 }
5145 next_spqe:
5146                 spqe_cnt++;
5147         } /* for */
5148
5149         smp_mb__before_atomic_inc();
5150         atomic_add(spqe_cnt, &bp->eq_spq_left);
5151
5152         bp->eq_cons = sw_cons;
5153         bp->eq_prod = sw_prod;
5154         /* Make sure that above mem writes were issued towards the memory */
5155         smp_wmb();
5156
5157         /* update producer */
5158         bnx2x_update_eq_prod(bp, bp->eq_prod);
5159 }
5160
5161 static void bnx2x_sp_task(struct work_struct *work)
5162 {
5163         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5164
5165         DP(BNX2X_MSG_SP, "sp task invoked\n");
5166
5167         /* make sure the atomic interupt_occurred has been written */
5168         smp_rmb();
5169         if (atomic_read(&bp->interrupt_occurred)) {
5170
5171                 /* what work needs to be performed? */
5172                 u16 status = bnx2x_update_dsb_idx(bp);
5173
5174                 DP(BNX2X_MSG_SP, "status %x\n", status);
5175                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5176                 atomic_set(&bp->interrupt_occurred, 0);
5177
5178                 /* HW attentions */
5179                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5180                         bnx2x_attn_int(bp);
5181                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5182                 }
5183
5184                 /* SP events: STAT_QUERY and others */
5185                 if (status & BNX2X_DEF_SB_IDX) {
5186                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5187
5188                 if (FCOE_INIT(bp) &&
5189                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5190                                 /* Prevent local bottom-halves from running as
5191                                  * we are going to change the local NAPI list.
5192                                  */
5193                                 local_bh_disable();
5194                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5195                                 local_bh_enable();
5196                         }
5197
5198                         /* Handle EQ completions */
5199                         bnx2x_eq_int(bp);
5200                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5201                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5202
5203                         status &= ~BNX2X_DEF_SB_IDX;
5204                 }
5205
5206                 /* if status is non zero then perhaps something went wrong */
5207                 if (unlikely(status))
5208                         DP(BNX2X_MSG_SP,
5209                            "got an unknown interrupt! (status 0x%x)\n", status);
5210
5211                 /* ack status block only if something was actually handled */
5212                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5213                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5214
5215         }
5216
5217         /* must be called after the EQ processing (since eq leads to sriov
5218          * ramrod completion flows).
5219          * This flow may have been scheduled by the arrival of a ramrod
5220          * completion, or by the sriov code rescheduling itself.
5221          */
5222         bnx2x_iov_sp_task(bp);
5223
5224         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5225         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5226                                &bp->sp_state)) {
5227                 bnx2x_link_report(bp);
5228                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5229         }
5230 }
5231
5232 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5233 {
5234         struct net_device *dev = dev_instance;
5235         struct bnx2x *bp = netdev_priv(dev);
5236
5237         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5238                      IGU_INT_DISABLE, 0);
5239
5240 #ifdef BNX2X_STOP_ON_ERROR
5241         if (unlikely(bp->panic))
5242                 return IRQ_HANDLED;
5243 #endif
5244
5245         if (CNIC_LOADED(bp)) {
5246                 struct cnic_ops *c_ops;
5247
5248                 rcu_read_lock();
5249                 c_ops = rcu_dereference(bp->cnic_ops);
5250                 if (c_ops)
5251                         c_ops->cnic_handler(bp->cnic_data, NULL);
5252                 rcu_read_unlock();
5253         }
5254
5255         /* schedule sp task to perform default status block work, ack
5256          * attentions and enable interrupts.
5257          */
5258         bnx2x_schedule_sp_task(bp);
5259
5260         return IRQ_HANDLED;
5261 }
5262
5263 /* end of slow path */
5264
5265
5266 void bnx2x_drv_pulse(struct bnx2x *bp)
5267 {
5268         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5269                  bp->fw_drv_pulse_wr_seq);
5270 }
5271
5272 /* crc is the first field in the bulletin board. compute the crc over the
5273  * entire bulletin board excluding the crc field itself
5274  */
5275 u32 bnx2x_crc_vf_bulletin(struct bnx2x *bp,
5276                           struct pf_vf_bulletin_content *bulletin)
5277 {
5278         return crc32(BULLETIN_CRC_SEED,
5279                  ((u8 *)bulletin) + sizeof(bulletin->crc),
5280                  BULLETIN_CONTENT_SIZE - sizeof(bulletin->crc));
5281 }
5282
5283 /* Check for new posts on the bulletin board */
5284 enum sample_bulletin_result bnx2x_sample_bulletin(struct bnx2x *bp)
5285 {
5286         struct pf_vf_bulletin_content bulletin = bp->pf2vf_bulletin->content;
5287         int attempts;
5288
5289         /* bulletin board hasn't changed since last sample */
5290         if (bp->old_bulletin.version == bulletin.version)
5291                 return PFVF_BULLETIN_UNCHANGED;
5292
5293         /* validate crc of new bulletin board */
5294         if (bp->old_bulletin.version != bp->pf2vf_bulletin->content.version) {
5295                 /* sampling structure in mid post may result with corrupted data
5296                  * validate crc to ensure coherency.
5297                  */
5298                 for (attempts = 0; attempts < BULLETIN_ATTEMPTS; attempts++) {
5299                         bulletin = bp->pf2vf_bulletin->content;
5300                         if (bulletin.crc == bnx2x_crc_vf_bulletin(bp,
5301                                                                   &bulletin))
5302                                 break;
5303
5304                         BNX2X_ERR("bad crc on bulletin board. contained %x computed %x\n",
5305                                   bulletin.crc,
5306                                   bnx2x_crc_vf_bulletin(bp, &bulletin));
5307                 }
5308                 if (attempts >= BULLETIN_ATTEMPTS) {
5309                         BNX2X_ERR("pf to vf bulletin board crc was wrong %d consecutive times. Aborting\n",
5310                                   attempts);
5311                         return PFVF_BULLETIN_CRC_ERR;
5312                 }
5313         }
5314
5315         /* the mac address in bulletin board is valid and is new */
5316         if (bulletin.valid_bitmap & 1 << MAC_ADDR_VALID &&
5317             memcmp(bulletin.mac, bp->old_bulletin.mac, ETH_ALEN)) {
5318                 /* update new mac to net device */
5319                 memcpy(bp->dev->dev_addr, bulletin.mac, ETH_ALEN);
5320         }
5321
5322         /* copy new bulletin board to bp */
5323         bp->old_bulletin = bulletin;
5324
5325         return PFVF_BULLETIN_UPDATED;
5326 }
5327
5328 static void bnx2x_timer(unsigned long data)
5329 {
5330         struct bnx2x *bp = (struct bnx2x *) data;
5331
5332         if (!netif_running(bp->dev))
5333                 return;
5334
5335         if (IS_PF(bp) &&
5336             !BP_NOMCP(bp)) {
5337                 int mb_idx = BP_FW_MB_IDX(bp);
5338                 u32 drv_pulse;
5339                 u32 mcp_pulse;
5340
5341                 ++bp->fw_drv_pulse_wr_seq;
5342                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5343                 /* TBD - add SYSTEM_TIME */
5344                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5345                 bnx2x_drv_pulse(bp);
5346
5347                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5348                              MCP_PULSE_SEQ_MASK);
5349                 /* The delta between driver pulse and mcp response
5350                  * should be 1 (before mcp response) or 0 (after mcp response)
5351                  */
5352                 if ((drv_pulse != mcp_pulse) &&
5353                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5354                         /* someone lost a heartbeat... */
5355                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5356                                   drv_pulse, mcp_pulse);
5357                 }
5358         }
5359
5360         if (bp->state == BNX2X_STATE_OPEN)
5361                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5362
5363         /* sample pf vf bulletin board for new posts from pf */
5364         if (IS_VF(bp))
5365                 bnx2x_sample_bulletin(bp);
5366
5367         mod_timer(&bp->timer, jiffies + bp->current_interval);
5368 }
5369
5370 /* end of Statistics */
5371
5372 /* nic init */
5373
5374 /*
5375  * nic init service functions
5376  */
5377
5378 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5379 {
5380         u32 i;
5381         if (!(len%4) && !(addr%4))
5382                 for (i = 0; i < len; i += 4)
5383                         REG_WR(bp, addr + i, fill);
5384         else
5385                 for (i = 0; i < len; i++)
5386                         REG_WR8(bp, addr + i, fill);
5387
5388 }
5389
5390 /* helper: writes FP SP data to FW - data_size in dwords */
5391 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5392                                 int fw_sb_id,
5393                                 u32 *sb_data_p,
5394                                 u32 data_size)
5395 {
5396         int index;
5397         for (index = 0; index < data_size; index++)
5398                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5399                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5400                         sizeof(u32)*index,
5401                         *(sb_data_p + index));
5402 }
5403
5404 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5405 {
5406         u32 *sb_data_p;
5407         u32 data_size = 0;
5408         struct hc_status_block_data_e2 sb_data_e2;
5409         struct hc_status_block_data_e1x sb_data_e1x;
5410
5411         /* disable the function first */
5412         if (!CHIP_IS_E1x(bp)) {
5413                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5414                 sb_data_e2.common.state = SB_DISABLED;
5415                 sb_data_e2.common.p_func.vf_valid = false;
5416                 sb_data_p = (u32 *)&sb_data_e2;
5417                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5418         } else {
5419                 memset(&sb_data_e1x, 0,
5420                        sizeof(struct hc_status_block_data_e1x));
5421                 sb_data_e1x.common.state = SB_DISABLED;
5422                 sb_data_e1x.common.p_func.vf_valid = false;
5423                 sb_data_p = (u32 *)&sb_data_e1x;
5424                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5425         }
5426         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5427
5428         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5429                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5430                         CSTORM_STATUS_BLOCK_SIZE);
5431         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5432                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5433                         CSTORM_SYNC_BLOCK_SIZE);
5434 }
5435
5436 /* helper:  writes SP SB data to FW */
5437 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5438                 struct hc_sp_status_block_data *sp_sb_data)
5439 {
5440         int func = BP_FUNC(bp);
5441         int i;
5442         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5443                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5444                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5445                         i*sizeof(u32),
5446                         *((u32 *)sp_sb_data + i));
5447 }
5448
5449 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5450 {
5451         int func = BP_FUNC(bp);
5452         struct hc_sp_status_block_data sp_sb_data;
5453         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5454
5455         sp_sb_data.state = SB_DISABLED;
5456         sp_sb_data.p_func.vf_valid = false;
5457
5458         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5459
5460         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5461                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5462                         CSTORM_SP_STATUS_BLOCK_SIZE);
5463         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5464                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5465                         CSTORM_SP_SYNC_BLOCK_SIZE);
5466
5467 }
5468
5469
5470 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5471                                            int igu_sb_id, int igu_seg_id)
5472 {
5473         hc_sm->igu_sb_id = igu_sb_id;
5474         hc_sm->igu_seg_id = igu_seg_id;
5475         hc_sm->timer_value = 0xFF;
5476         hc_sm->time_to_expire = 0xFFFFFFFF;
5477 }
5478
5479
5480 /* allocates state machine ids. */
5481 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5482 {
5483         /* zero out state machine indices */
5484         /* rx indices */
5485         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5486
5487         /* tx indices */
5488         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5489         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5490         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5491         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5492
5493         /* map indices */
5494         /* rx indices */
5495         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5496                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5497
5498         /* tx indices */
5499         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5500                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5501         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5502                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5503         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5504                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5505         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5506                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5507 }
5508
5509 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5510                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5511 {
5512         int igu_seg_id;
5513
5514         struct hc_status_block_data_e2 sb_data_e2;
5515         struct hc_status_block_data_e1x sb_data_e1x;
5516         struct hc_status_block_sm  *hc_sm_p;
5517         int data_size;
5518         u32 *sb_data_p;
5519
5520         if (CHIP_INT_MODE_IS_BC(bp))
5521                 igu_seg_id = HC_SEG_ACCESS_NORM;
5522         else
5523                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5524
5525         bnx2x_zero_fp_sb(bp, fw_sb_id);
5526
5527         if (!CHIP_IS_E1x(bp)) {
5528                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5529                 sb_data_e2.common.state = SB_ENABLED;
5530                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5531                 sb_data_e2.common.p_func.vf_id = vfid;
5532                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5533                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5534                 sb_data_e2.common.same_igu_sb_1b = true;
5535                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5536                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5537                 hc_sm_p = sb_data_e2.common.state_machine;
5538                 sb_data_p = (u32 *)&sb_data_e2;
5539                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5540                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5541         } else {
5542                 memset(&sb_data_e1x, 0,
5543                        sizeof(struct hc_status_block_data_e1x));
5544                 sb_data_e1x.common.state = SB_ENABLED;
5545                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5546                 sb_data_e1x.common.p_func.vf_id = 0xff;
5547                 sb_data_e1x.common.p_func.vf_valid = false;
5548                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5549                 sb_data_e1x.common.same_igu_sb_1b = true;
5550                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5551                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5552                 hc_sm_p = sb_data_e1x.common.state_machine;
5553                 sb_data_p = (u32 *)&sb_data_e1x;
5554                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5555                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5556         }
5557
5558         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5559                                        igu_sb_id, igu_seg_id);
5560         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5561                                        igu_sb_id, igu_seg_id);
5562
5563         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5564
5565         /* write indecies to HW */
5566         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5567 }
5568
5569 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5570                                      u16 tx_usec, u16 rx_usec)
5571 {
5572         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5573                                     false, rx_usec);
5574         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5575                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5576                                        tx_usec);
5577         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5578                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5579                                        tx_usec);
5580         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5581                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5582                                        tx_usec);
5583 }
5584
5585 static void bnx2x_init_def_sb(struct bnx2x *bp)
5586 {
5587         struct host_sp_status_block *def_sb = bp->def_status_blk;
5588         dma_addr_t mapping = bp->def_status_blk_mapping;
5589         int igu_sp_sb_index;
5590         int igu_seg_id;
5591         int port = BP_PORT(bp);
5592         int func = BP_FUNC(bp);
5593         int reg_offset, reg_offset_en5;
5594         u64 section;
5595         int index;
5596         struct hc_sp_status_block_data sp_sb_data;
5597         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5598
5599         if (CHIP_INT_MODE_IS_BC(bp)) {
5600                 igu_sp_sb_index = DEF_SB_IGU_ID;
5601                 igu_seg_id = HC_SEG_ACCESS_DEF;
5602         } else {
5603                 igu_sp_sb_index = bp->igu_dsb_id;
5604                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5605         }
5606
5607         /* ATTN */
5608         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5609                                             atten_status_block);
5610         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5611
5612         bp->attn_state = 0;
5613
5614         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5615                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5616         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5617                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5618         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5619                 int sindex;
5620                 /* take care of sig[0]..sig[4] */
5621                 for (sindex = 0; sindex < 4; sindex++)
5622                         bp->attn_group[index].sig[sindex] =
5623                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5624
5625                 if (!CHIP_IS_E1x(bp))
5626                         /*
5627                          * enable5 is separate from the rest of the registers,
5628                          * and therefore the address skip is 4
5629                          * and not 16 between the different groups
5630                          */
5631                         bp->attn_group[index].sig[4] = REG_RD(bp,
5632                                         reg_offset_en5 + 0x4*index);
5633                 else
5634                         bp->attn_group[index].sig[4] = 0;
5635         }
5636
5637         if (bp->common.int_block == INT_BLOCK_HC) {
5638                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5639                                      HC_REG_ATTN_MSG0_ADDR_L);
5640
5641                 REG_WR(bp, reg_offset, U64_LO(section));
5642                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5643         } else if (!CHIP_IS_E1x(bp)) {
5644                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5645                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5646         }
5647
5648         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5649                                             sp_sb);
5650
5651         bnx2x_zero_sp_sb(bp);
5652
5653         sp_sb_data.state                = SB_ENABLED;
5654         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5655         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5656         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5657         sp_sb_data.igu_seg_id           = igu_seg_id;
5658         sp_sb_data.p_func.pf_id         = func;
5659         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5660         sp_sb_data.p_func.vf_id         = 0xff;
5661
5662         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5663
5664         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5665 }
5666
5667 void bnx2x_update_coalesce(struct bnx2x *bp)
5668 {
5669         int i;
5670
5671         for_each_eth_queue(bp, i)
5672                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5673                                          bp->tx_ticks, bp->rx_ticks);
5674 }
5675
5676 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5677 {
5678         spin_lock_init(&bp->spq_lock);
5679         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5680
5681         bp->spq_prod_idx = 0;
5682         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5683         bp->spq_prod_bd = bp->spq;
5684         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5685 }
5686
5687 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5688 {
5689         int i;
5690         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5691                 union event_ring_elem *elem =
5692                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5693
5694                 elem->next_page.addr.hi =
5695                         cpu_to_le32(U64_HI(bp->eq_mapping +
5696                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5697                 elem->next_page.addr.lo =
5698                         cpu_to_le32(U64_LO(bp->eq_mapping +
5699                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5700         }
5701         bp->eq_cons = 0;
5702         bp->eq_prod = NUM_EQ_DESC;
5703         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5704         /* we want a warning message before it gets rought... */
5705         atomic_set(&bp->eq_spq_left,
5706                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5707 }
5708
5709
5710 /* called with netif_addr_lock_bh() */
5711 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5712                          unsigned long rx_mode_flags,
5713                          unsigned long rx_accept_flags,
5714                          unsigned long tx_accept_flags,
5715                          unsigned long ramrod_flags)
5716 {
5717         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5718         int rc;
5719
5720         memset(&ramrod_param, 0, sizeof(ramrod_param));
5721
5722         /* Prepare ramrod parameters */
5723         ramrod_param.cid = 0;
5724         ramrod_param.cl_id = cl_id;
5725         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5726         ramrod_param.func_id = BP_FUNC(bp);
5727
5728         ramrod_param.pstate = &bp->sp_state;
5729         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5730
5731         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5732         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5733
5734         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5735
5736         ramrod_param.ramrod_flags = ramrod_flags;
5737         ramrod_param.rx_mode_flags = rx_mode_flags;
5738
5739         ramrod_param.rx_accept_flags = rx_accept_flags;
5740         ramrod_param.tx_accept_flags = tx_accept_flags;
5741
5742         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5743         if (rc < 0) {
5744                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5745                 return;
5746         }
5747 }
5748
5749 /* called with netif_addr_lock_bh() */
5750 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5751 {
5752         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5753         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5754
5755         if (!NO_FCOE(bp))
5756
5757                 /* Configure rx_mode of FCoE Queue */
5758                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5759
5760         switch (bp->rx_mode) {
5761         case BNX2X_RX_MODE_NONE:
5762                 /*
5763                  * 'drop all' supersedes any accept flags that may have been
5764                  * passed to the function.
5765                  */
5766                 break;
5767         case BNX2X_RX_MODE_NORMAL:
5768                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5769                 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5770                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5771
5772                 /* internal switching mode */
5773                 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5774                 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5775                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5776
5777                 break;
5778         case BNX2X_RX_MODE_ALLMULTI:
5779                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5780                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5781                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5782
5783                 /* internal switching mode */
5784                 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5785                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5786                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5787
5788                 break;
5789         case BNX2X_RX_MODE_PROMISC:
5790                 /* According to deffinition of SI mode, iface in promisc mode
5791                  * should receive matched and unmatched (in resolution of port)
5792                  * unicast packets.
5793                  */
5794                 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5795                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5796                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5797                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5798
5799                 /* internal switching mode */
5800                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5801                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5802
5803                 if (IS_MF_SI(bp))
5804                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5805                 else
5806                         __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5807
5808                 break;
5809         default:
5810                 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5811                 return;
5812         }
5813
5814         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5815                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5816                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5817         }
5818
5819         __set_bit(RAMROD_RX, &ramrod_flags);
5820         __set_bit(RAMROD_TX, &ramrod_flags);
5821
5822         bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5823                             tx_accept_flags, ramrod_flags);
5824 }
5825
5826 static void bnx2x_init_internal_common(struct bnx2x *bp)
5827 {
5828         int i;
5829
5830         if (IS_MF_SI(bp))
5831                 /*
5832                  * In switch independent mode, the TSTORM needs to accept
5833                  * packets that failed classification, since approximate match
5834                  * mac addresses aren't written to NIG LLH
5835                  */
5836                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5837                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5838         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5839                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5840                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5841
5842         /* Zero this manually as its initialization is
5843            currently missing in the initTool */
5844         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5845                 REG_WR(bp, BAR_USTRORM_INTMEM +
5846                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
5847         if (!CHIP_IS_E1x(bp)) {
5848                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5849                         CHIP_INT_MODE_IS_BC(bp) ?
5850                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5851         }
5852 }
5853
5854 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5855 {
5856         switch (load_code) {
5857         case FW_MSG_CODE_DRV_LOAD_COMMON:
5858         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5859                 bnx2x_init_internal_common(bp);
5860                 /* no break */
5861
5862         case FW_MSG_CODE_DRV_LOAD_PORT:
5863                 /* nothing to do */
5864                 /* no break */
5865
5866         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5867                 /* internal memory per function is
5868                    initialized inside bnx2x_pf_init */
5869                 break;
5870
5871         default:
5872                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5873                 break;
5874         }
5875 }
5876
5877 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5878 {
5879         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5880 }
5881
5882 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5883 {
5884         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5885 }
5886
5887 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5888 {
5889         if (CHIP_IS_E1x(fp->bp))
5890                 return BP_L_ID(fp->bp) + fp->index;
5891         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
5892                 return bnx2x_fp_igu_sb_id(fp);
5893 }
5894
5895 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5896 {
5897         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5898         u8 cos;
5899         unsigned long q_type = 0;
5900         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5901         fp->rx_queue = fp_idx;
5902         fp->cid = fp_idx;
5903         fp->cl_id = bnx2x_fp_cl_id(fp);
5904         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5905         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5906         /* qZone id equals to FW (per path) client id */
5907         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
5908
5909         /* init shortcut */
5910         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5911
5912         /* Setup SB indicies */
5913         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5914
5915         /* Configure Queue State object */
5916         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5917         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5918
5919         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5920
5921         /* init tx data */
5922         for_each_cos_in_tx_queue(fp, cos) {
5923                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5924                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5925                                   FP_COS_TO_TXQ(fp, cos, bp),
5926                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
5927                 cids[cos] = fp->txdata_ptr[cos]->cid;
5928         }
5929
5930         /* nothing more for vf to do here */
5931         if (IS_VF(bp))
5932                 return;
5933
5934         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5935                       fp->fw_sb_id, fp->igu_sb_id);
5936         bnx2x_update_fpsb_idx(fp);
5937         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5938                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5939                              bnx2x_sp_mapping(bp, q_rdata), q_type);
5940
5941         /**
5942          * Configure classification DBs: Always enable Tx switching
5943          */
5944         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5945
5946         DP(NETIF_MSG_IFUP,
5947            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
5948            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5949            fp->igu_sb_id);
5950 }
5951
5952 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5953 {
5954         int i;
5955
5956         for (i = 1; i <= NUM_TX_RINGS; i++) {
5957                 struct eth_tx_next_bd *tx_next_bd =
5958                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5959
5960                 tx_next_bd->addr_hi =
5961                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5962                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5963                 tx_next_bd->addr_lo =
5964                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5965                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5966         }
5967
5968         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5969         txdata->tx_db.data.zero_fill1 = 0;
5970         txdata->tx_db.data.prod = 0;
5971
5972         txdata->tx_pkt_prod = 0;
5973         txdata->tx_pkt_cons = 0;
5974         txdata->tx_bd_prod = 0;
5975         txdata->tx_bd_cons = 0;
5976         txdata->tx_pkt = 0;
5977 }
5978
5979 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5980 {
5981         int i;
5982
5983         for_each_tx_queue_cnic(bp, i)
5984                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
5985 }
5986 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5987 {
5988         int i;
5989         u8 cos;
5990
5991         for_each_eth_queue(bp, i)
5992                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5993                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5994 }
5995
5996 void bnx2x_nic_init_cnic(struct bnx2x *bp)
5997 {
5998         if (!NO_FCOE(bp))
5999                 bnx2x_init_fcoe_fp(bp);
6000
6001         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6002                       BNX2X_VF_ID_INVALID, false,
6003                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6004
6005         /* ensure status block indices were read */
6006         rmb();
6007         bnx2x_init_rx_rings_cnic(bp);
6008         bnx2x_init_tx_rings_cnic(bp);
6009
6010         /* flush all */
6011         mb();
6012         mmiowb();
6013 }
6014
6015 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
6016 {
6017         int i;
6018
6019         for_each_eth_queue(bp, i)
6020                 bnx2x_init_eth_fp(bp, i);
6021
6022         /* ensure status block indices were read */
6023         rmb();
6024         bnx2x_init_rx_rings(bp);
6025         bnx2x_init_tx_rings(bp);
6026
6027         if (IS_VF(bp))
6028                 return;
6029
6030         /* Initialize MOD_ABS interrupts */
6031         bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6032                                bp->common.shmem_base, bp->common.shmem2_base,
6033                                BP_PORT(bp));
6034
6035         bnx2x_init_def_sb(bp);
6036         bnx2x_update_dsb_idx(bp);
6037         bnx2x_init_sp_ring(bp);
6038         bnx2x_init_eq_ring(bp);
6039         bnx2x_init_internal(bp, load_code);
6040         bnx2x_pf_init(bp);
6041         bnx2x_stats_init(bp);
6042
6043         /* flush all before enabling interrupts */
6044         mb();
6045         mmiowb();
6046
6047         bnx2x_int_enable(bp);
6048
6049         /* Check for SPIO5 */
6050         bnx2x_attn_int_deasserted0(bp,
6051                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6052                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6053 }
6054
6055 /* end of nic init */
6056
6057 /*
6058  * gzip service functions
6059  */
6060
6061 static int bnx2x_gunzip_init(struct bnx2x *bp)
6062 {
6063         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6064                                             &bp->gunzip_mapping, GFP_KERNEL);
6065         if (bp->gunzip_buf  == NULL)
6066                 goto gunzip_nomem1;
6067
6068         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6069         if (bp->strm  == NULL)
6070                 goto gunzip_nomem2;
6071
6072         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6073         if (bp->strm->workspace == NULL)
6074                 goto gunzip_nomem3;
6075
6076         return 0;
6077
6078 gunzip_nomem3:
6079         kfree(bp->strm);
6080         bp->strm = NULL;
6081
6082 gunzip_nomem2:
6083         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6084                           bp->gunzip_mapping);
6085         bp->gunzip_buf = NULL;
6086
6087 gunzip_nomem1:
6088         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6089         return -ENOMEM;
6090 }
6091
6092 static void bnx2x_gunzip_end(struct bnx2x *bp)
6093 {
6094         if (bp->strm) {
6095                 vfree(bp->strm->workspace);
6096                 kfree(bp->strm);
6097                 bp->strm = NULL;
6098         }
6099
6100         if (bp->gunzip_buf) {
6101                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6102                                   bp->gunzip_mapping);
6103                 bp->gunzip_buf = NULL;
6104         }
6105 }
6106
6107 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6108 {
6109         int n, rc;
6110
6111         /* check gzip header */
6112         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6113                 BNX2X_ERR("Bad gzip header\n");
6114                 return -EINVAL;
6115         }
6116
6117         n = 10;
6118
6119 #define FNAME                           0x8
6120
6121         if (zbuf[3] & FNAME)
6122                 while ((zbuf[n++] != 0) && (n < len));
6123
6124         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6125         bp->strm->avail_in = len - n;
6126         bp->strm->next_out = bp->gunzip_buf;
6127         bp->strm->avail_out = FW_BUF_SIZE;
6128
6129         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6130         if (rc != Z_OK)
6131                 return rc;
6132
6133         rc = zlib_inflate(bp->strm, Z_FINISH);
6134         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6135                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6136                            bp->strm->msg);
6137
6138         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6139         if (bp->gunzip_outlen & 0x3)
6140                 netdev_err(bp->dev,
6141                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6142                                 bp->gunzip_outlen);
6143         bp->gunzip_outlen >>= 2;
6144
6145         zlib_inflateEnd(bp->strm);
6146
6147         if (rc == Z_STREAM_END)
6148                 return 0;
6149
6150         return rc;
6151 }
6152
6153 /* nic load/unload */
6154
6155 /*
6156  * General service functions
6157  */
6158
6159 /* send a NIG loopback debug packet */
6160 static void bnx2x_lb_pckt(struct bnx2x *bp)
6161 {
6162         u32 wb_write[3];
6163
6164         /* Ethernet source and destination addresses */
6165         wb_write[0] = 0x55555555;
6166         wb_write[1] = 0x55555555;
6167         wb_write[2] = 0x20;             /* SOP */
6168         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6169
6170         /* NON-IP protocol */
6171         wb_write[0] = 0x09000000;
6172         wb_write[1] = 0x55555555;
6173         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6174         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6175 }
6176
6177 /* some of the internal memories
6178  * are not directly readable from the driver
6179  * to test them we send debug packets
6180  */
6181 static int bnx2x_int_mem_test(struct bnx2x *bp)
6182 {
6183         int factor;
6184         int count, i;
6185         u32 val = 0;
6186
6187         if (CHIP_REV_IS_FPGA(bp))
6188                 factor = 120;
6189         else if (CHIP_REV_IS_EMUL(bp))
6190                 factor = 200;
6191         else
6192                 factor = 1;
6193
6194         /* Disable inputs of parser neighbor blocks */
6195         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6196         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6197         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6198         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6199
6200         /*  Write 0 to parser credits for CFC search request */
6201         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6202
6203         /* send Ethernet packet */
6204         bnx2x_lb_pckt(bp);
6205
6206         /* TODO do i reset NIG statistic? */
6207         /* Wait until NIG register shows 1 packet of size 0x10 */
6208         count = 1000 * factor;
6209         while (count) {
6210
6211                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6212                 val = *bnx2x_sp(bp, wb_data[0]);
6213                 if (val == 0x10)
6214                         break;
6215
6216                 msleep(10);
6217                 count--;
6218         }
6219         if (val != 0x10) {
6220                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6221                 return -1;
6222         }
6223
6224         /* Wait until PRS register shows 1 packet */
6225         count = 1000 * factor;
6226         while (count) {
6227                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6228                 if (val == 1)
6229                         break;
6230
6231                 msleep(10);
6232                 count--;
6233         }
6234         if (val != 0x1) {
6235                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6236                 return -2;
6237         }
6238
6239         /* Reset and init BRB, PRS */
6240         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6241         msleep(50);
6242         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6243         msleep(50);
6244         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6245         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6246
6247         DP(NETIF_MSG_HW, "part2\n");
6248
6249         /* Disable inputs of parser neighbor blocks */
6250         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6251         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6252         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6253         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6254
6255         /* Write 0 to parser credits for CFC search request */
6256         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6257
6258         /* send 10 Ethernet packets */
6259         for (i = 0; i < 10; i++)
6260                 bnx2x_lb_pckt(bp);
6261
6262         /* Wait until NIG register shows 10 + 1
6263            packets of size 11*0x10 = 0xb0 */
6264         count = 1000 * factor;
6265         while (count) {
6266
6267                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6268                 val = *bnx2x_sp(bp, wb_data[0]);
6269                 if (val == 0xb0)
6270                         break;
6271
6272                 msleep(10);
6273                 count--;
6274         }
6275         if (val != 0xb0) {
6276                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6277                 return -3;
6278         }
6279
6280         /* Wait until PRS register shows 2 packets */
6281         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6282         if (val != 2)
6283                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6284
6285         /* Write 1 to parser credits for CFC search request */
6286         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6287
6288         /* Wait until PRS register shows 3 packets */
6289         msleep(10 * factor);
6290         /* Wait until NIG register shows 1 packet of size 0x10 */
6291         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6292         if (val != 3)
6293                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6294
6295         /* clear NIG EOP FIFO */
6296         for (i = 0; i < 11; i++)
6297                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6298         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6299         if (val != 1) {
6300                 BNX2X_ERR("clear of NIG failed\n");
6301                 return -4;
6302         }
6303
6304         /* Reset and init BRB, PRS, NIG */
6305         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6306         msleep(50);
6307         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6308         msleep(50);
6309         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6310         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6311         if (!CNIC_SUPPORT(bp))
6312                 /* set NIC mode */
6313                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6314
6315         /* Enable inputs of parser neighbor blocks */
6316         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6317         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6318         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6319         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6320
6321         DP(NETIF_MSG_HW, "done\n");
6322
6323         return 0; /* OK */
6324 }
6325
6326 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6327 {
6328         u32 val;
6329
6330         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6331         if (!CHIP_IS_E1x(bp))
6332                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6333         else
6334                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6335         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6336         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6337         /*
6338          * mask read length error interrupts in brb for parser
6339          * (parsing unit and 'checksum and crc' unit)
6340          * these errors are legal (PU reads fixed length and CAC can cause
6341          * read length error on truncated packets)
6342          */
6343         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6344         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6345         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6346         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6347         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6348         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6349 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6350 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6351         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6352         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6353         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6354 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6355 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6356         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6357         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6358         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6359         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6360 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6361 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6362
6363         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6364                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6365                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6366         if (!CHIP_IS_E1x(bp))
6367                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6368                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6369         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6370
6371         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6372         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6373         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6374 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6375
6376         if (!CHIP_IS_E1x(bp))
6377                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6378                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6379
6380         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6381         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6382 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6383         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6384 }
6385
6386 static void bnx2x_reset_common(struct bnx2x *bp)
6387 {
6388         u32 val = 0x1400;
6389
6390         /* reset_common */
6391         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6392                0xd3ffff7f);
6393
6394         if (CHIP_IS_E3(bp)) {
6395                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6396                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6397         }
6398
6399         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6400 }
6401
6402 static void bnx2x_setup_dmae(struct bnx2x *bp)
6403 {
6404         bp->dmae_ready = 0;
6405         spin_lock_init(&bp->dmae_lock);
6406 }
6407
6408 static void bnx2x_init_pxp(struct bnx2x *bp)
6409 {
6410         u16 devctl;
6411         int r_order, w_order;
6412
6413         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6414         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6415         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6416         if (bp->mrrs == -1)
6417                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6418         else {
6419                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6420                 r_order = bp->mrrs;
6421         }
6422
6423         bnx2x_init_pxp_arb(bp, r_order, w_order);
6424 }
6425
6426 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6427 {
6428         int is_required;
6429         u32 val;
6430         int port;
6431
6432         if (BP_NOMCP(bp))
6433                 return;
6434
6435         is_required = 0;
6436         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6437               SHARED_HW_CFG_FAN_FAILURE_MASK;
6438
6439         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6440                 is_required = 1;
6441
6442         /*
6443          * The fan failure mechanism is usually related to the PHY type since
6444          * the power consumption of the board is affected by the PHY. Currently,
6445          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6446          */
6447         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6448                 for (port = PORT_0; port < PORT_MAX; port++) {
6449                         is_required |=
6450                                 bnx2x_fan_failure_det_req(
6451                                         bp,
6452                                         bp->common.shmem_base,
6453                                         bp->common.shmem2_base,
6454                                         port);
6455                 }
6456
6457         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6458
6459         if (is_required == 0)
6460                 return;
6461
6462         /* Fan failure is indicated by SPIO 5 */
6463         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6464
6465         /* set to active low mode */
6466         val = REG_RD(bp, MISC_REG_SPIO_INT);
6467         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6468         REG_WR(bp, MISC_REG_SPIO_INT, val);
6469
6470         /* enable interrupt to signal the IGU */
6471         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6472         val |= MISC_SPIO_SPIO5;
6473         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6474 }
6475
6476 void bnx2x_pf_disable(struct bnx2x *bp)
6477 {
6478         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6479         val &= ~IGU_PF_CONF_FUNC_EN;
6480
6481         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6482         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6483         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6484 }
6485
6486 static void bnx2x__common_init_phy(struct bnx2x *bp)
6487 {
6488         u32 shmem_base[2], shmem2_base[2];
6489         /* Avoid common init in case MFW supports LFA */
6490         if (SHMEM2_RD(bp, size) >
6491             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6492                 return;
6493         shmem_base[0] =  bp->common.shmem_base;
6494         shmem2_base[0] = bp->common.shmem2_base;
6495         if (!CHIP_IS_E1x(bp)) {
6496                 shmem_base[1] =
6497                         SHMEM2_RD(bp, other_shmem_base_addr);
6498                 shmem2_base[1] =
6499                         SHMEM2_RD(bp, other_shmem2_base_addr);
6500         }
6501         bnx2x_acquire_phy_lock(bp);
6502         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6503                               bp->common.chip_id);
6504         bnx2x_release_phy_lock(bp);
6505 }
6506
6507 /**
6508  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6509  *
6510  * @bp:         driver handle
6511  */
6512 static int bnx2x_init_hw_common(struct bnx2x *bp)
6513 {
6514         u32 val;
6515
6516         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6517
6518         /*
6519          * take the UNDI lock to protect undi_unload flow from accessing
6520          * registers while we're resetting the chip
6521          */
6522         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6523
6524         bnx2x_reset_common(bp);
6525         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6526
6527         val = 0xfffc;
6528         if (CHIP_IS_E3(bp)) {
6529                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6530                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6531         }
6532         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6533
6534         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6535
6536         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6537
6538         if (!CHIP_IS_E1x(bp)) {
6539                 u8 abs_func_id;
6540
6541                 /**
6542                  * 4-port mode or 2-port mode we need to turn of master-enable
6543                  * for everyone, after that, turn it back on for self.
6544                  * so, we disregard multi-function or not, and always disable
6545                  * for all functions on the given path, this means 0,2,4,6 for
6546                  * path 0 and 1,3,5,7 for path 1
6547                  */
6548                 for (abs_func_id = BP_PATH(bp);
6549                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6550                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6551                                 REG_WR(bp,
6552                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6553                                     1);
6554                                 continue;
6555                         }
6556
6557                         bnx2x_pretend_func(bp, abs_func_id);
6558                         /* clear pf enable */
6559                         bnx2x_pf_disable(bp);
6560                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6561                 }
6562         }
6563
6564         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6565         if (CHIP_IS_E1(bp)) {
6566                 /* enable HW interrupt from PXP on USDM overflow
6567                    bit 16 on INT_MASK_0 */
6568                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6569         }
6570
6571         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6572         bnx2x_init_pxp(bp);
6573
6574 #ifdef __BIG_ENDIAN
6575         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6576         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6577         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6578         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6579         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6580         /* make sure this value is 0 */
6581         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6582
6583 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6584         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6585         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6586         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6587         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6588 #endif
6589
6590         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6591
6592         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6593                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6594
6595         /* let the HW do it's magic ... */
6596         msleep(100);
6597         /* finish PXP init */
6598         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6599         if (val != 1) {
6600                 BNX2X_ERR("PXP2 CFG failed\n");
6601                 return -EBUSY;
6602         }
6603         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6604         if (val != 1) {
6605                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6606                 return -EBUSY;
6607         }
6608
6609         /* Timers bug workaround E2 only. We need to set the entire ILT to
6610          * have entries with value "0" and valid bit on.
6611          * This needs to be done by the first PF that is loaded in a path
6612          * (i.e. common phase)
6613          */
6614         if (!CHIP_IS_E1x(bp)) {
6615 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6616  * (i.e. vnic3) to start even if it is marked as "scan-off".
6617  * This occurs when a different function (func2,3) is being marked
6618  * as "scan-off". Real-life scenario for example: if a driver is being
6619  * load-unloaded while func6,7 are down. This will cause the timer to access
6620  * the ilt, translate to a logical address and send a request to read/write.
6621  * Since the ilt for the function that is down is not valid, this will cause
6622  * a translation error which is unrecoverable.
6623  * The Workaround is intended to make sure that when this happens nothing fatal
6624  * will occur. The workaround:
6625  *      1.  First PF driver which loads on a path will:
6626  *              a.  After taking the chip out of reset, by using pretend,
6627  *                  it will write "0" to the following registers of
6628  *                  the other vnics.
6629  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6630  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6631  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6632  *                  And for itself it will write '1' to
6633  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6634  *                  dmae-operations (writing to pram for example.)
6635  *                  note: can be done for only function 6,7 but cleaner this
6636  *                        way.
6637  *              b.  Write zero+valid to the entire ILT.
6638  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6639  *                  VNIC3 (of that port). The range allocated will be the
6640  *                  entire ILT. This is needed to prevent  ILT range error.
6641  *      2.  Any PF driver load flow:
6642  *              a.  ILT update with the physical addresses of the allocated
6643  *                  logical pages.
6644  *              b.  Wait 20msec. - note that this timeout is needed to make
6645  *                  sure there are no requests in one of the PXP internal
6646  *                  queues with "old" ILT addresses.
6647  *              c.  PF enable in the PGLC.
6648  *              d.  Clear the was_error of the PF in the PGLC. (could have
6649  *                  occured while driver was down)
6650  *              e.  PF enable in the CFC (WEAK + STRONG)
6651  *              f.  Timers scan enable
6652  *      3.  PF driver unload flow:
6653  *              a.  Clear the Timers scan_en.
6654  *              b.  Polling for scan_on=0 for that PF.
6655  *              c.  Clear the PF enable bit in the PXP.
6656  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6657  *              e.  Write zero+valid to all ILT entries (The valid bit must
6658  *                  stay set)
6659  *              f.  If this is VNIC 3 of a port then also init
6660  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6661  *                  to the last enrty in the ILT.
6662  *
6663  *      Notes:
6664  *      Currently the PF error in the PGLC is non recoverable.
6665  *      In the future the there will be a recovery routine for this error.
6666  *      Currently attention is masked.
6667  *      Having an MCP lock on the load/unload process does not guarantee that
6668  *      there is no Timer disable during Func6/7 enable. This is because the
6669  *      Timers scan is currently being cleared by the MCP on FLR.
6670  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6671  *      there is error before clearing it. But the flow above is simpler and
6672  *      more general.
6673  *      All ILT entries are written by zero+valid and not just PF6/7
6674  *      ILT entries since in the future the ILT entries allocation for
6675  *      PF-s might be dynamic.
6676  */
6677                 struct ilt_client_info ilt_cli;
6678                 struct bnx2x_ilt ilt;
6679                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6680                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6681
6682                 /* initialize dummy TM client */
6683                 ilt_cli.start = 0;
6684                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6685                 ilt_cli.client_num = ILT_CLIENT_TM;
6686
6687                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6688                  * Step 2: set the timers first/last ilt entry to point
6689                  * to the entire range to prevent ILT range error for 3rd/4th
6690                  * vnic (this code assumes existance of the vnic)
6691                  *
6692                  * both steps performed by call to bnx2x_ilt_client_init_op()
6693                  * with dummy TM client
6694                  *
6695                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6696                  * and his brother are split registers
6697                  */
6698                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6699                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6700                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6701
6702                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6703                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6704                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6705         }
6706
6707
6708         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6709         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6710
6711         if (!CHIP_IS_E1x(bp)) {
6712                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6713                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6714                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6715
6716                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6717
6718                 /* let the HW do it's magic ... */
6719                 do {
6720                         msleep(200);
6721                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6722                 } while (factor-- && (val != 1));
6723
6724                 if (val != 1) {
6725                         BNX2X_ERR("ATC_INIT failed\n");
6726                         return -EBUSY;
6727                 }
6728         }
6729
6730         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6731
6732         bnx2x_iov_init_dmae(bp);
6733
6734         /* clean the DMAE memory */
6735         bp->dmae_ready = 1;
6736         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6737
6738         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6739
6740         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6741
6742         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6743
6744         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6745
6746         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6747         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6748         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6749         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6750
6751         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6752
6753
6754         /* QM queues pointers table */
6755         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6756
6757         /* soft reset pulse */
6758         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6759         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6760
6761         if (CNIC_SUPPORT(bp))
6762                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6763
6764         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6765         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6766         if (!CHIP_REV_IS_SLOW(bp))
6767                 /* enable hw interrupt from doorbell Q */
6768                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6769
6770         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6771
6772         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6773         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6774
6775         if (!CHIP_IS_E1(bp))
6776                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6777
6778         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6779                 if (IS_MF_AFEX(bp)) {
6780                         /* configure that VNTag and VLAN headers must be
6781                          * received in afex mode
6782                          */
6783                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6784                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6785                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6786                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6787                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6788                 } else {
6789                         /* Bit-map indicating which L2 hdrs may appear
6790                          * after the basic Ethernet header
6791                          */
6792                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6793                                bp->path_has_ovlan ? 7 : 6);
6794                 }
6795         }
6796
6797         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6798         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6799         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6800         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6801
6802         if (!CHIP_IS_E1x(bp)) {
6803                 /* reset VFC memories */
6804                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6805                            VFC_MEMORIES_RST_REG_CAM_RST |
6806                            VFC_MEMORIES_RST_REG_RAM_RST);
6807                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6808                            VFC_MEMORIES_RST_REG_CAM_RST |
6809                            VFC_MEMORIES_RST_REG_RAM_RST);
6810
6811                 msleep(20);
6812         }
6813
6814         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6815         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6816         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6817         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6818
6819         /* sync semi rtc */
6820         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6821                0x80000000);
6822         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6823                0x80000000);
6824
6825         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6826         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6827         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6828
6829         if (!CHIP_IS_E1x(bp)) {
6830                 if (IS_MF_AFEX(bp)) {
6831                         /* configure that VNTag and VLAN headers must be
6832                          * sent in afex mode
6833                          */
6834                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6835                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6836                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6837                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6838                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6839                 } else {
6840                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6841                                bp->path_has_ovlan ? 7 : 6);
6842                 }
6843         }
6844
6845         REG_WR(bp, SRC_REG_SOFT_RST, 1);
6846
6847         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6848
6849         if (CNIC_SUPPORT(bp)) {
6850                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6851                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6852                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6853                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6854                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6855                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6856                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6857                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6858                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6859                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6860         }
6861         REG_WR(bp, SRC_REG_SOFT_RST, 0);
6862
6863         if (sizeof(union cdu_context) != 1024)
6864                 /* we currently assume that a context is 1024 bytes */
6865                 dev_alert(&bp->pdev->dev,
6866                           "please adjust the size of cdu_context(%ld)\n",
6867                           (long)sizeof(union cdu_context));
6868
6869         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6870         val = (4 << 24) + (0 << 12) + 1024;
6871         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6872
6873         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6874         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6875         /* enable context validation interrupt from CFC */
6876         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6877
6878         /* set the thresholds to prevent CFC/CDU race */
6879         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6880
6881         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6882
6883         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6884                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6885
6886         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6887         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6888
6889         /* Reset PCIE errors for debug */
6890         REG_WR(bp, 0x2814, 0xffffffff);
6891         REG_WR(bp, 0x3820, 0xffffffff);
6892
6893         if (!CHIP_IS_E1x(bp)) {
6894                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6895                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6896                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6897                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6898                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6899                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6900                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6901                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6902                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6903                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6904                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6905         }
6906
6907         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6908         if (!CHIP_IS_E1(bp)) {
6909                 /* in E3 this done in per-port section */
6910                 if (!CHIP_IS_E3(bp))
6911                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6912         }
6913         if (CHIP_IS_E1H(bp))
6914                 /* not applicable for E2 (and above ...) */
6915                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6916
6917         if (CHIP_REV_IS_SLOW(bp))
6918                 msleep(200);
6919
6920         /* finish CFC init */
6921         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6922         if (val != 1) {
6923                 BNX2X_ERR("CFC LL_INIT failed\n");
6924                 return -EBUSY;
6925         }
6926         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6927         if (val != 1) {
6928                 BNX2X_ERR("CFC AC_INIT failed\n");
6929                 return -EBUSY;
6930         }
6931         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6932         if (val != 1) {
6933                 BNX2X_ERR("CFC CAM_INIT failed\n");
6934                 return -EBUSY;
6935         }
6936         REG_WR(bp, CFC_REG_DEBUG0, 0);
6937
6938         if (CHIP_IS_E1(bp)) {
6939                 /* read NIG statistic
6940                    to see if this is our first up since powerup */
6941                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6942                 val = *bnx2x_sp(bp, wb_data[0]);
6943
6944                 /* do internal memory self test */
6945                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6946                         BNX2X_ERR("internal mem self test failed\n");
6947                         return -EBUSY;
6948                 }
6949         }
6950
6951         bnx2x_setup_fan_failure_detection(bp);
6952
6953         /* clear PXP2 attentions */
6954         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6955
6956         bnx2x_enable_blocks_attention(bp);
6957         bnx2x_enable_blocks_parity(bp);
6958
6959         if (!BP_NOMCP(bp)) {
6960                 if (CHIP_IS_E1x(bp))
6961                         bnx2x__common_init_phy(bp);
6962         } else
6963                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6964
6965         return 0;
6966 }
6967
6968 /**
6969  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6970  *
6971  * @bp:         driver handle
6972  */
6973 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6974 {
6975         int rc = bnx2x_init_hw_common(bp);
6976
6977         if (rc)
6978                 return rc;
6979
6980         /* In E2 2-PORT mode, same ext phy is used for the two paths */
6981         if (!BP_NOMCP(bp))
6982                 bnx2x__common_init_phy(bp);
6983
6984         return 0;
6985 }
6986
6987 static int bnx2x_init_hw_port(struct bnx2x *bp)
6988 {
6989         int port = BP_PORT(bp);
6990         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6991         u32 low, high;
6992         u32 val;
6993
6994
6995         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
6996
6997         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6998
6999         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7000         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7001         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7002
7003         /* Timers bug workaround: disables the pf_master bit in pglue at
7004          * common phase, we need to enable it here before any dmae access are
7005          * attempted. Therefore we manually added the enable-master to the
7006          * port phase (it also happens in the function phase)
7007          */
7008         if (!CHIP_IS_E1x(bp))
7009                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7010
7011         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7012         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7013         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7014         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7015
7016         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7017         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7018         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7019         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7020
7021         /* QM cid (connection) count */
7022         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7023
7024         if (CNIC_SUPPORT(bp)) {
7025                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7026                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7027                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7028         }
7029
7030         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7031
7032         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7033
7034         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7035
7036                 if (IS_MF(bp))
7037                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7038                 else if (bp->dev->mtu > 4096) {
7039                         if (bp->flags & ONE_PORT_FLAG)
7040                                 low = 160;
7041                         else {
7042                                 val = bp->dev->mtu;
7043                                 /* (24*1024 + val*4)/256 */
7044                                 low = 96 + (val/64) +
7045                                                 ((val % 64) ? 1 : 0);
7046                         }
7047                 } else
7048                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7049                 high = low + 56;        /* 14*1024/256 */
7050                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7051                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7052         }
7053
7054         if (CHIP_MODE_IS_4_PORT(bp))
7055                 REG_WR(bp, (BP_PORT(bp) ?
7056                             BRB1_REG_MAC_GUARANTIED_1 :
7057                             BRB1_REG_MAC_GUARANTIED_0), 40);
7058
7059
7060         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7061         if (CHIP_IS_E3B0(bp)) {
7062                 if (IS_MF_AFEX(bp)) {
7063                         /* configure headers for AFEX mode */
7064                         REG_WR(bp, BP_PORT(bp) ?
7065                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7066                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7067                         REG_WR(bp, BP_PORT(bp) ?
7068                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7069                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7070                         REG_WR(bp, BP_PORT(bp) ?
7071                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7072                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7073                 } else {
7074                         /* Ovlan exists only if we are in multi-function +
7075                          * switch-dependent mode, in switch-independent there
7076                          * is no ovlan headers
7077                          */
7078                         REG_WR(bp, BP_PORT(bp) ?
7079                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7080                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7081                                (bp->path_has_ovlan ? 7 : 6));
7082                 }
7083         }
7084
7085         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7086         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7087         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7088         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7089
7090         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7091         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7092         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7093         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7094
7095         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7096         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7097
7098         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7099
7100         if (CHIP_IS_E1x(bp)) {
7101                 /* configure PBF to work without PAUSE mtu 9000 */
7102                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7103
7104                 /* update threshold */
7105                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7106                 /* update init credit */
7107                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7108
7109                 /* probe changes */
7110                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7111                 udelay(50);
7112                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7113         }
7114
7115         if (CNIC_SUPPORT(bp))
7116                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7117
7118         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7119         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7120
7121         if (CHIP_IS_E1(bp)) {
7122                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7123                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7124         }
7125         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7126
7127         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7128
7129         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7130         /* init aeu_mask_attn_func_0/1:
7131          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7132          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7133          *             bits 4-7 are used for "per vn group attention" */
7134         val = IS_MF(bp) ? 0xF7 : 0x7;
7135         /* Enable DCBX attention for all but E1 */
7136         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7137         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7138
7139         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7140
7141         if (!CHIP_IS_E1x(bp)) {
7142                 /* Bit-map indicating which L2 hdrs may appear after the
7143                  * basic Ethernet header
7144                  */
7145                 if (IS_MF_AFEX(bp))
7146                         REG_WR(bp, BP_PORT(bp) ?
7147                                NIG_REG_P1_HDRS_AFTER_BASIC :
7148                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7149                 else
7150                         REG_WR(bp, BP_PORT(bp) ?
7151                                NIG_REG_P1_HDRS_AFTER_BASIC :
7152                                NIG_REG_P0_HDRS_AFTER_BASIC,
7153                                IS_MF_SD(bp) ? 7 : 6);
7154
7155                 if (CHIP_IS_E3(bp))
7156                         REG_WR(bp, BP_PORT(bp) ?
7157                                    NIG_REG_LLH1_MF_MODE :
7158                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7159         }
7160         if (!CHIP_IS_E3(bp))
7161                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7162
7163         if (!CHIP_IS_E1(bp)) {
7164                 /* 0x2 disable mf_ov, 0x1 enable */
7165                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7166                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7167
7168                 if (!CHIP_IS_E1x(bp)) {
7169                         val = 0;
7170                         switch (bp->mf_mode) {
7171                         case MULTI_FUNCTION_SD:
7172                                 val = 1;
7173                                 break;
7174                         case MULTI_FUNCTION_SI:
7175                         case MULTI_FUNCTION_AFEX:
7176                                 val = 2;
7177                                 break;
7178                         }
7179
7180                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7181                                                   NIG_REG_LLH0_CLS_TYPE), val);
7182                 }
7183                 {
7184                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7185                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7186                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7187                 }
7188         }
7189
7190
7191         /* If SPIO5 is set to generate interrupts, enable it for this port */
7192         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7193         if (val & MISC_SPIO_SPIO5) {
7194                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7195                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7196                 val = REG_RD(bp, reg_addr);
7197                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7198                 REG_WR(bp, reg_addr, val);
7199         }
7200
7201         return 0;
7202 }
7203
7204 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7205 {
7206         int reg;
7207         u32 wb_write[2];
7208
7209         if (CHIP_IS_E1(bp))
7210                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7211         else
7212                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7213
7214         wb_write[0] = ONCHIP_ADDR1(addr);
7215         wb_write[1] = ONCHIP_ADDR2(addr);
7216         REG_WR_DMAE(bp, reg, wb_write, 2);
7217 }
7218
7219 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7220 {
7221         u32 data, ctl, cnt = 100;
7222         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7223         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7224         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7225         u32 sb_bit =  1 << (idu_sb_id%32);
7226         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7227         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7228
7229         /* Not supported in BC mode */
7230         if (CHIP_INT_MODE_IS_BC(bp))
7231                 return;
7232
7233         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7234                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7235                 IGU_REGULAR_CLEANUP_SET                         |
7236                 IGU_REGULAR_BCLEANUP;
7237
7238         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7239               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7240               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7241
7242         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7243                          data, igu_addr_data);
7244         REG_WR(bp, igu_addr_data, data);
7245         mmiowb();
7246         barrier();
7247         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7248                           ctl, igu_addr_ctl);
7249         REG_WR(bp, igu_addr_ctl, ctl);
7250         mmiowb();
7251         barrier();
7252
7253         /* wait for clean up to finish */
7254         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7255                 msleep(20);
7256
7257
7258         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7259                 DP(NETIF_MSG_HW,
7260                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7261                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7262         }
7263 }
7264
7265 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7266 {
7267         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7268 }
7269
7270 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7271 {
7272         u32 i, base = FUNC_ILT_BASE(func);
7273         for (i = base; i < base + ILT_PER_FUNC; i++)
7274                 bnx2x_ilt_wr(bp, i, 0);
7275 }
7276
7277
7278 static void bnx2x_init_searcher(struct bnx2x *bp)
7279 {
7280         int port = BP_PORT(bp);
7281         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7282         /* T1 hash bits value determines the T1 number of entries */
7283         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7284 }
7285
7286 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7287 {
7288         int rc;
7289         struct bnx2x_func_state_params func_params = {NULL};
7290         struct bnx2x_func_switch_update_params *switch_update_params =
7291                 &func_params.params.switch_update;
7292
7293         /* Prepare parameters for function state transitions */
7294         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7295         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7296
7297         func_params.f_obj = &bp->func_obj;
7298         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7299
7300         /* Function parameters */
7301         switch_update_params->suspend = suspend;
7302
7303         rc = bnx2x_func_state_change(bp, &func_params);
7304
7305         return rc;
7306 }
7307
7308 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7309 {
7310         int rc, i, port = BP_PORT(bp);
7311         int vlan_en = 0, mac_en[NUM_MACS];
7312
7313
7314         /* Close input from network */
7315         if (bp->mf_mode == SINGLE_FUNCTION) {
7316                 bnx2x_set_rx_filter(&bp->link_params, 0);
7317         } else {
7318                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7319                                    NIG_REG_LLH0_FUNC_EN);
7320                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7321                           NIG_REG_LLH0_FUNC_EN, 0);
7322                 for (i = 0; i < NUM_MACS; i++) {
7323                         mac_en[i] = REG_RD(bp, port ?
7324                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7325                                               4 * i) :
7326                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7327                                               4 * i));
7328                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7329                                               4 * i) :
7330                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7331                 }
7332         }
7333
7334         /* Close BMC to host */
7335         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7336                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7337
7338         /* Suspend Tx switching to the PF. Completion of this ramrod
7339          * further guarantees that all the packets of that PF / child
7340          * VFs in BRB were processed by the Parser, so it is safe to
7341          * change the NIC_MODE register.
7342          */
7343         rc = bnx2x_func_switch_update(bp, 1);
7344         if (rc) {
7345                 BNX2X_ERR("Can't suspend tx-switching!\n");
7346                 return rc;
7347         }
7348
7349         /* Change NIC_MODE register */
7350         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7351
7352         /* Open input from network */
7353         if (bp->mf_mode == SINGLE_FUNCTION) {
7354                 bnx2x_set_rx_filter(&bp->link_params, 1);
7355         } else {
7356                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7357                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7358                 for (i = 0; i < NUM_MACS; i++) {
7359                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7360                                               4 * i) :
7361                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7362                                   mac_en[i]);
7363                 }
7364         }
7365
7366         /* Enable BMC to host */
7367         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7368                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7369
7370         /* Resume Tx switching to the PF */
7371         rc = bnx2x_func_switch_update(bp, 0);
7372         if (rc) {
7373                 BNX2X_ERR("Can't resume tx-switching!\n");
7374                 return rc;
7375         }
7376
7377         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7378         return 0;
7379 }
7380
7381 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7382 {
7383         int rc;
7384
7385         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7386
7387         if (CONFIGURE_NIC_MODE(bp)) {
7388                 /* Configrue searcher as part of function hw init */
7389                 bnx2x_init_searcher(bp);
7390
7391                 /* Reset NIC mode */
7392                 rc = bnx2x_reset_nic_mode(bp);
7393                 if (rc)
7394                         BNX2X_ERR("Can't change NIC mode!\n");
7395                 return rc;
7396         }
7397
7398         return 0;
7399 }
7400
7401 static int bnx2x_init_hw_func(struct bnx2x *bp)
7402 {
7403         int port = BP_PORT(bp);
7404         int func = BP_FUNC(bp);
7405         int init_phase = PHASE_PF0 + func;
7406         struct bnx2x_ilt *ilt = BP_ILT(bp);
7407         u16 cdu_ilt_start;
7408         u32 addr, val;
7409         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7410         int i, main_mem_width, rc;
7411
7412         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7413
7414         /* FLR cleanup - hmmm */
7415         if (!CHIP_IS_E1x(bp)) {
7416                 rc = bnx2x_pf_flr_clnup(bp);
7417                 if (rc)
7418                         return rc;
7419         }
7420
7421         /* set MSI reconfigure capability */
7422         if (bp->common.int_block == INT_BLOCK_HC) {
7423                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7424                 val = REG_RD(bp, addr);
7425                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7426                 REG_WR(bp, addr, val);
7427         }
7428
7429         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7430         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7431
7432         ilt = BP_ILT(bp);
7433         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7434
7435         if (IS_SRIOV(bp))
7436                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7437         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7438
7439         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7440          * those of the VFs, so start line should be reset
7441          */
7442         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7443         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7444                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7445                 ilt->lines[cdu_ilt_start + i].page_mapping =
7446                         bp->context[i].cxt_mapping;
7447                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7448         }
7449
7450         bnx2x_ilt_init_op(bp, INITOP_SET);
7451
7452         if (!CONFIGURE_NIC_MODE(bp)) {
7453                 bnx2x_init_searcher(bp);
7454                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7455                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7456         } else {
7457                 /* Set NIC mode */
7458                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7459                 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7460
7461         }
7462
7463         if (!CHIP_IS_E1x(bp)) {
7464                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7465
7466                 /* Turn on a single ISR mode in IGU if driver is going to use
7467                  * INT#x or MSI
7468                  */
7469                 if (!(bp->flags & USING_MSIX_FLAG))
7470                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7471                 /*
7472                  * Timers workaround bug: function init part.
7473                  * Need to wait 20msec after initializing ILT,
7474                  * needed to make sure there are no requests in
7475                  * one of the PXP internal queues with "old" ILT addresses
7476                  */
7477                 msleep(20);
7478                 /*
7479                  * Master enable - Due to WB DMAE writes performed before this
7480                  * register is re-initialized as part of the regular function
7481                  * init
7482                  */
7483                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7484                 /* Enable the function in IGU */
7485                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7486         }
7487
7488         bp->dmae_ready = 1;
7489
7490         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7491
7492         if (!CHIP_IS_E1x(bp))
7493                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7494
7495         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7496         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7497         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7498         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7499         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7500         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7501         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7502         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7503         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7504         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7505         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7506         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7507         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7508
7509         if (!CHIP_IS_E1x(bp))
7510                 REG_WR(bp, QM_REG_PF_EN, 1);
7511
7512         if (!CHIP_IS_E1x(bp)) {
7513                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7514                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7515                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7516                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7517         }
7518         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7519
7520         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7521         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7522
7523         bnx2x_iov_init_dq(bp);
7524
7525         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7526         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7527         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7528         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7529         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7530         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7531         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7532         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7533         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7534         if (!CHIP_IS_E1x(bp))
7535                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7536
7537         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7538
7539         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7540
7541         if (!CHIP_IS_E1x(bp))
7542                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7543
7544         if (IS_MF(bp)) {
7545                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7546                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7547         }
7548
7549         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7550
7551         /* HC init per function */
7552         if (bp->common.int_block == INT_BLOCK_HC) {
7553                 if (CHIP_IS_E1H(bp)) {
7554                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7555
7556                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7557                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7558                 }
7559                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7560
7561         } else {
7562                 int num_segs, sb_idx, prod_offset;
7563
7564                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7565
7566                 if (!CHIP_IS_E1x(bp)) {
7567                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7568                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7569                 }
7570
7571                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7572
7573                 if (!CHIP_IS_E1x(bp)) {
7574                         int dsb_idx = 0;
7575                         /**
7576                          * Producer memory:
7577                          * E2 mode: address 0-135 match to the mapping memory;
7578                          * 136 - PF0 default prod; 137 - PF1 default prod;
7579                          * 138 - PF2 default prod; 139 - PF3 default prod;
7580                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7581                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7582                          * 144-147 reserved.
7583                          *
7584                          * E1.5 mode - In backward compatible mode;
7585                          * for non default SB; each even line in the memory
7586                          * holds the U producer and each odd line hold
7587                          * the C producer. The first 128 producers are for
7588                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7589                          * producers are for the DSB for each PF.
7590                          * Each PF has five segments: (the order inside each
7591                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7592                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7593                          * 144-147 attn prods;
7594                          */
7595                         /* non-default-status-blocks */
7596                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7597                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7598                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7599                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7600                                         num_segs;
7601
7602                                 for (i = 0; i < num_segs; i++) {
7603                                         addr = IGU_REG_PROD_CONS_MEMORY +
7604                                                         (prod_offset + i) * 4;
7605                                         REG_WR(bp, addr, 0);
7606                                 }
7607                                 /* send consumer update with value 0 */
7608                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7609                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7610                                 bnx2x_igu_clear_sb(bp,
7611                                                    bp->igu_base_sb + sb_idx);
7612                         }
7613
7614                         /* default-status-blocks */
7615                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7616                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7617
7618                         if (CHIP_MODE_IS_4_PORT(bp))
7619                                 dsb_idx = BP_FUNC(bp);
7620                         else
7621                                 dsb_idx = BP_VN(bp);
7622
7623                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7624                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7625                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7626
7627                         /*
7628                          * igu prods come in chunks of E1HVN_MAX (4) -
7629                          * does not matters what is the current chip mode
7630                          */
7631                         for (i = 0; i < (num_segs * E1HVN_MAX);
7632                              i += E1HVN_MAX) {
7633                                 addr = IGU_REG_PROD_CONS_MEMORY +
7634                                                         (prod_offset + i)*4;
7635                                 REG_WR(bp, addr, 0);
7636                         }
7637                         /* send consumer update with 0 */
7638                         if (CHIP_INT_MODE_IS_BC(bp)) {
7639                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7640                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7641                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7642                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7643                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7644                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7645                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7646                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7647                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7648                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7649                         } else {
7650                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7651                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7652                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7653                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7654                         }
7655                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7656
7657                         /* !!! these should become driver const once
7658                            rf-tool supports split-68 const */
7659                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7660                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7661                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7662                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7663                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7664                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7665                 }
7666         }
7667
7668         /* Reset PCIE errors for debug */
7669         REG_WR(bp, 0x2114, 0xffffffff);
7670         REG_WR(bp, 0x2120, 0xffffffff);
7671
7672         if (CHIP_IS_E1x(bp)) {
7673                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7674                 main_mem_base = HC_REG_MAIN_MEMORY +
7675                                 BP_PORT(bp) * (main_mem_size * 4);
7676                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7677                 main_mem_width = 8;
7678
7679                 val = REG_RD(bp, main_mem_prty_clr);
7680                 if (val)
7681                         DP(NETIF_MSG_HW,
7682                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7683                            val);
7684
7685                 /* Clear "false" parity errors in MSI-X table */
7686                 for (i = main_mem_base;
7687                      i < main_mem_base + main_mem_size * 4;
7688                      i += main_mem_width) {
7689                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7690                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7691                                          i, main_mem_width / 4);
7692                 }
7693                 /* Clear HC parity attention */
7694                 REG_RD(bp, main_mem_prty_clr);
7695         }
7696
7697 #ifdef BNX2X_STOP_ON_ERROR
7698         /* Enable STORMs SP logging */
7699         REG_WR8(bp, BAR_USTRORM_INTMEM +
7700                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7701         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7702                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7703         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7704                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7705         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7706                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7707 #endif
7708
7709         bnx2x_phy_probe(&bp->link_params);
7710
7711         return 0;
7712 }
7713
7714
7715 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7716 {
7717         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7718
7719         if (!CHIP_IS_E1x(bp))
7720                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7721                                sizeof(struct host_hc_status_block_e2));
7722         else
7723                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7724                                sizeof(struct host_hc_status_block_e1x));
7725
7726         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7727 }
7728
7729 void bnx2x_free_mem(struct bnx2x *bp)
7730 {
7731         int i;
7732
7733         /* fastpath */
7734         bnx2x_free_fp_mem(bp);
7735         /* end of fastpath */
7736
7737         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7738                        sizeof(struct host_sp_status_block));
7739
7740         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7741                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7742
7743         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7744                        sizeof(struct bnx2x_slowpath));
7745
7746         for (i = 0; i < L2_ILT_LINES(bp); i++)
7747                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7748                                bp->context[i].size);
7749         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7750
7751         BNX2X_FREE(bp->ilt->lines);
7752
7753         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7754
7755         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7756                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7757 }
7758
7759
7760 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7761 {
7762         if (!CHIP_IS_E1x(bp))
7763                 /* size = the status block + ramrod buffers */
7764                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7765                                 sizeof(struct host_hc_status_block_e2));
7766         else
7767                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7768                                 &bp->cnic_sb_mapping,
7769                                 sizeof(struct
7770                                        host_hc_status_block_e1x));
7771
7772         if (CONFIGURE_NIC_MODE(bp))
7773                 /* allocate searcher T2 table, as it wan't allocated before */
7774                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7775
7776         /* write address to which L5 should insert its values */
7777         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7778                 &bp->slowpath->drv_info_to_mcp;
7779
7780         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7781                 goto alloc_mem_err;
7782
7783         return 0;
7784
7785 alloc_mem_err:
7786         bnx2x_free_mem_cnic(bp);
7787         BNX2X_ERR("Can't allocate memory\n");
7788         return -ENOMEM;
7789 }
7790
7791 int bnx2x_alloc_mem(struct bnx2x *bp)
7792 {
7793         int i, allocated, context_size;
7794
7795         if (!CONFIGURE_NIC_MODE(bp))
7796                 /* allocate searcher T2 table */
7797                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7798
7799         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7800                         sizeof(struct host_sp_status_block));
7801
7802         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7803                         sizeof(struct bnx2x_slowpath));
7804
7805         /* Allocate memory for CDU context:
7806          * This memory is allocated separately and not in the generic ILT
7807          * functions because CDU differs in few aspects:
7808          * 1. There are multiple entities allocating memory for context -
7809          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7810          * its own ILT lines.
7811          * 2. Since CDU page-size is not a single 4KB page (which is the case
7812          * for the other ILT clients), to be efficient we want to support
7813          * allocation of sub-page-size in the last entry.
7814          * 3. Context pointers are used by the driver to pass to FW / update
7815          * the context (for the other ILT clients the pointers are used just to
7816          * free the memory during unload).
7817          */
7818         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7819
7820         for (i = 0, allocated = 0; allocated < context_size; i++) {
7821                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7822                                           (context_size - allocated));
7823                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7824                                 &bp->context[i].cxt_mapping,
7825                                 bp->context[i].size);
7826                 allocated += bp->context[i].size;
7827         }
7828         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7829
7830         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7831                 goto alloc_mem_err;
7832
7833         if (bnx2x_iov_alloc_mem(bp))
7834                 goto alloc_mem_err;
7835
7836         /* Slow path ring */
7837         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7838
7839         /* EQ */
7840         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7841                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
7842
7843         return 0;
7844
7845 alloc_mem_err:
7846         bnx2x_free_mem(bp);
7847         BNX2X_ERR("Can't allocate memory\n");
7848         return -ENOMEM;
7849 }
7850
7851 /*
7852  * Init service functions
7853  */
7854
7855 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7856                       struct bnx2x_vlan_mac_obj *obj, bool set,
7857                       int mac_type, unsigned long *ramrod_flags)
7858 {
7859         int rc;
7860         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7861
7862         memset(&ramrod_param, 0, sizeof(ramrod_param));
7863
7864         /* Fill general parameters */
7865         ramrod_param.vlan_mac_obj = obj;
7866         ramrod_param.ramrod_flags = *ramrod_flags;
7867
7868         /* Fill a user request section if needed */
7869         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7870                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7871
7872                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7873
7874                 /* Set the command: ADD or DEL */
7875                 if (set)
7876                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7877                 else
7878                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7879         }
7880
7881         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7882
7883         if (rc == -EEXIST) {
7884                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7885                 /* do not treat adding same MAC as error */
7886                 rc = 0;
7887         } else if (rc < 0)
7888                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7889
7890         return rc;
7891 }
7892
7893 int bnx2x_del_all_macs(struct bnx2x *bp,
7894                        struct bnx2x_vlan_mac_obj *mac_obj,
7895                        int mac_type, bool wait_for_comp)
7896 {
7897         int rc;
7898         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7899
7900         /* Wait for completion of requested */
7901         if (wait_for_comp)
7902                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7903
7904         /* Set the mac type of addresses we want to clear */
7905         __set_bit(mac_type, &vlan_mac_flags);
7906
7907         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7908         if (rc < 0)
7909                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7910
7911         return rc;
7912 }
7913
7914 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7915 {
7916         unsigned long ramrod_flags = 0;
7917
7918         if (is_zero_ether_addr(bp->dev->dev_addr) &&
7919             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7920                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7921                    "Ignoring Zero MAC for STORAGE SD mode\n");
7922                 return 0;
7923         }
7924
7925         DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7926
7927         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7928         /* Eth MAC is set on RSS leading client (fp[0]) */
7929         return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7930                                  set, BNX2X_ETH_MAC, &ramrod_flags);
7931 }
7932
7933 int bnx2x_setup_leading(struct bnx2x *bp)
7934 {
7935         return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7936 }
7937
7938 /**
7939  * bnx2x_set_int_mode - configure interrupt mode
7940  *
7941  * @bp:         driver handle
7942  *
7943  * In case of MSI-X it will also try to enable MSI-X.
7944  */
7945 int bnx2x_set_int_mode(struct bnx2x *bp)
7946 {
7947         int rc = 0;
7948
7949         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7950                 return -EINVAL;
7951
7952         switch (int_mode) {
7953         case BNX2X_INT_MODE_MSIX:
7954                 /* attempt to enable msix */
7955                 rc = bnx2x_enable_msix(bp);
7956
7957                 /* msix attained */
7958                 if (!rc)
7959                         return 0;
7960
7961                 /* vfs use only msix */
7962                 if (rc && IS_VF(bp))
7963                         return rc;
7964
7965                 /* failed to enable multiple MSI-X */
7966                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7967                                bp->num_queues,
7968                                1 + bp->num_cnic_queues);
7969
7970                 /* falling through... */
7971         case BNX2X_INT_MODE_MSI:
7972                 bnx2x_enable_msi(bp);
7973
7974                 /* falling through... */
7975         case BNX2X_INT_MODE_INTX:
7976                 bp->num_ethernet_queues = 1;
7977                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7978                 BNX2X_DEV_INFO("set number of queues to 1\n");
7979                 break;
7980         default:
7981                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7982                 return -EINVAL;
7983         }
7984         return 0;
7985 }
7986
7987 /* must be called prior to any HW initializations */
7988 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7989 {
7990         if (IS_SRIOV(bp))
7991                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
7992         return L2_ILT_LINES(bp);
7993 }
7994
7995 void bnx2x_ilt_set_info(struct bnx2x *bp)
7996 {
7997         struct ilt_client_info *ilt_client;
7998         struct bnx2x_ilt *ilt = BP_ILT(bp);
7999         u16 line = 0;
8000
8001         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8002         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8003
8004         /* CDU */
8005         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8006         ilt_client->client_num = ILT_CLIENT_CDU;
8007         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8008         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8009         ilt_client->start = line;
8010         line += bnx2x_cid_ilt_lines(bp);
8011
8012         if (CNIC_SUPPORT(bp))
8013                 line += CNIC_ILT_LINES;
8014         ilt_client->end = line - 1;
8015
8016         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8017            ilt_client->start,
8018            ilt_client->end,
8019            ilt_client->page_size,
8020            ilt_client->flags,
8021            ilog2(ilt_client->page_size >> 12));
8022
8023         /* QM */
8024         if (QM_INIT(bp->qm_cid_count)) {
8025                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8026                 ilt_client->client_num = ILT_CLIENT_QM;
8027                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8028                 ilt_client->flags = 0;
8029                 ilt_client->start = line;
8030
8031                 /* 4 bytes for each cid */
8032                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8033                                                          QM_ILT_PAGE_SZ);
8034
8035                 ilt_client->end = line - 1;
8036
8037                 DP(NETIF_MSG_IFUP,
8038                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8039                    ilt_client->start,
8040                    ilt_client->end,
8041                    ilt_client->page_size,
8042                    ilt_client->flags,
8043                    ilog2(ilt_client->page_size >> 12));
8044
8045         }
8046
8047         if (CNIC_SUPPORT(bp)) {
8048                 /* SRC */
8049                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8050                 ilt_client->client_num = ILT_CLIENT_SRC;
8051                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8052                 ilt_client->flags = 0;
8053                 ilt_client->start = line;
8054                 line += SRC_ILT_LINES;
8055                 ilt_client->end = line - 1;
8056
8057                 DP(NETIF_MSG_IFUP,
8058                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8059                    ilt_client->start,
8060                    ilt_client->end,
8061                    ilt_client->page_size,
8062                    ilt_client->flags,
8063                    ilog2(ilt_client->page_size >> 12));
8064
8065                 /* TM */
8066                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8067                 ilt_client->client_num = ILT_CLIENT_TM;
8068                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8069                 ilt_client->flags = 0;
8070                 ilt_client->start = line;
8071                 line += TM_ILT_LINES;
8072                 ilt_client->end = line - 1;
8073
8074                 DP(NETIF_MSG_IFUP,
8075                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8076                    ilt_client->start,
8077                    ilt_client->end,
8078                    ilt_client->page_size,
8079                    ilt_client->flags,
8080                    ilog2(ilt_client->page_size >> 12));
8081         }
8082
8083         BUG_ON(line > ILT_MAX_LINES);
8084 }
8085
8086 /**
8087  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8088  *
8089  * @bp:                 driver handle
8090  * @fp:                 pointer to fastpath
8091  * @init_params:        pointer to parameters structure
8092  *
8093  * parameters configured:
8094  *      - HC configuration
8095  *      - Queue's CDU context
8096  */
8097 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8098         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8099 {
8100
8101         u8 cos;
8102         int cxt_index, cxt_offset;
8103
8104         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8105         if (!IS_FCOE_FP(fp)) {
8106                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8107                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8108
8109                 /* If HC is supporterd, enable host coalescing in the transition
8110                  * to INIT state.
8111                  */
8112                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8113                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8114
8115                 /* HC rate */
8116                 init_params->rx.hc_rate = bp->rx_ticks ?
8117                         (1000000 / bp->rx_ticks) : 0;
8118                 init_params->tx.hc_rate = bp->tx_ticks ?
8119                         (1000000 / bp->tx_ticks) : 0;
8120
8121                 /* FW SB ID */
8122                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8123                         fp->fw_sb_id;
8124
8125                 /*
8126                  * CQ index among the SB indices: FCoE clients uses the default
8127                  * SB, therefore it's different.
8128                  */
8129                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8130                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8131         }
8132
8133         /* set maximum number of COSs supported by this queue */
8134         init_params->max_cos = fp->max_cos;
8135
8136         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8137             fp->index, init_params->max_cos);
8138
8139         /* set the context pointers queue object */
8140         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8141                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8142                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8143                                 ILT_PAGE_CIDS);
8144                 init_params->cxts[cos] =
8145                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8146         }
8147 }
8148
8149 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8150                         struct bnx2x_queue_state_params *q_params,
8151                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8152                         int tx_index, bool leading)
8153 {
8154         memset(tx_only_params, 0, sizeof(*tx_only_params));
8155
8156         /* Set the command */
8157         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8158
8159         /* Set tx-only QUEUE flags: don't zero statistics */
8160         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8161
8162         /* choose the index of the cid to send the slow path on */
8163         tx_only_params->cid_index = tx_index;
8164
8165         /* Set general TX_ONLY_SETUP parameters */
8166         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8167
8168         /* Set Tx TX_ONLY_SETUP parameters */
8169         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8170
8171         DP(NETIF_MSG_IFUP,
8172            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8173            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8174            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8175            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8176
8177         /* send the ramrod */
8178         return bnx2x_queue_state_change(bp, q_params);
8179 }
8180
8181
8182 /**
8183  * bnx2x_setup_queue - setup queue
8184  *
8185  * @bp:         driver handle
8186  * @fp:         pointer to fastpath
8187  * @leading:    is leading
8188  *
8189  * This function performs 2 steps in a Queue state machine
8190  *      actually: 1) RESET->INIT 2) INIT->SETUP
8191  */
8192
8193 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8194                        bool leading)
8195 {
8196         struct bnx2x_queue_state_params q_params = {NULL};
8197         struct bnx2x_queue_setup_params *setup_params =
8198                                                 &q_params.params.setup;
8199         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8200                                                 &q_params.params.tx_only;
8201         int rc;
8202         u8 tx_index;
8203
8204         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8205
8206         /* reset IGU state skip FCoE L2 queue */
8207         if (!IS_FCOE_FP(fp))
8208                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8209                              IGU_INT_ENABLE, 0);
8210
8211         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8212         /* We want to wait for completion in this context */
8213         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8214
8215         /* Prepare the INIT parameters */
8216         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8217
8218         /* Set the command */
8219         q_params.cmd = BNX2X_Q_CMD_INIT;
8220
8221         /* Change the state to INIT */
8222         rc = bnx2x_queue_state_change(bp, &q_params);
8223         if (rc) {
8224                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8225                 return rc;
8226         }
8227
8228         DP(NETIF_MSG_IFUP, "init complete\n");
8229
8230
8231         /* Now move the Queue to the SETUP state... */
8232         memset(setup_params, 0, sizeof(*setup_params));
8233
8234         /* Set QUEUE flags */
8235         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8236
8237         /* Set general SETUP parameters */
8238         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8239                                 FIRST_TX_COS_INDEX);
8240
8241         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8242                             &setup_params->rxq_params);
8243
8244         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8245                            FIRST_TX_COS_INDEX);
8246
8247         /* Set the command */
8248         q_params.cmd = BNX2X_Q_CMD_SETUP;
8249
8250         if (IS_FCOE_FP(fp))
8251                 bp->fcoe_init = true;
8252
8253         /* Change the state to SETUP */
8254         rc = bnx2x_queue_state_change(bp, &q_params);
8255         if (rc) {
8256                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8257                 return rc;
8258         }
8259
8260         /* loop through the relevant tx-only indices */
8261         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8262               tx_index < fp->max_cos;
8263               tx_index++) {
8264
8265                 /* prepare and send tx-only ramrod*/
8266                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8267                                           tx_only_params, tx_index, leading);
8268                 if (rc) {
8269                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8270                                   fp->index, tx_index);
8271                         return rc;
8272                 }
8273         }
8274
8275         return rc;
8276 }
8277
8278 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8279 {
8280         struct bnx2x_fastpath *fp = &bp->fp[index];
8281         struct bnx2x_fp_txdata *txdata;
8282         struct bnx2x_queue_state_params q_params = {NULL};
8283         int rc, tx_index;
8284
8285         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8286
8287         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8288         /* We want to wait for completion in this context */
8289         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8290
8291
8292         /* close tx-only connections */
8293         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8294              tx_index < fp->max_cos;
8295              tx_index++){
8296
8297                 /* ascertain this is a normal queue*/
8298                 txdata = fp->txdata_ptr[tx_index];
8299
8300                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8301                                                         txdata->txq_index);
8302
8303                 /* send halt terminate on tx-only connection */
8304                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8305                 memset(&q_params.params.terminate, 0,
8306                        sizeof(q_params.params.terminate));
8307                 q_params.params.terminate.cid_index = tx_index;
8308
8309                 rc = bnx2x_queue_state_change(bp, &q_params);
8310                 if (rc)
8311                         return rc;
8312
8313                 /* send halt terminate on tx-only connection */
8314                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8315                 memset(&q_params.params.cfc_del, 0,
8316                        sizeof(q_params.params.cfc_del));
8317                 q_params.params.cfc_del.cid_index = tx_index;
8318                 rc = bnx2x_queue_state_change(bp, &q_params);
8319                 if (rc)
8320                         return rc;
8321         }
8322         /* Stop the primary connection: */
8323         /* ...halt the connection */
8324         q_params.cmd = BNX2X_Q_CMD_HALT;
8325         rc = bnx2x_queue_state_change(bp, &q_params);
8326         if (rc)
8327                 return rc;
8328
8329         /* ...terminate the connection */
8330         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8331         memset(&q_params.params.terminate, 0,
8332                sizeof(q_params.params.terminate));
8333         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8334         rc = bnx2x_queue_state_change(bp, &q_params);
8335         if (rc)
8336                 return rc;
8337         /* ...delete cfc entry */
8338         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8339         memset(&q_params.params.cfc_del, 0,
8340                sizeof(q_params.params.cfc_del));
8341         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8342         return bnx2x_queue_state_change(bp, &q_params);
8343 }
8344
8345
8346 static void bnx2x_reset_func(struct bnx2x *bp)
8347 {
8348         int port = BP_PORT(bp);
8349         int func = BP_FUNC(bp);
8350         int i;
8351
8352         /* Disable the function in the FW */
8353         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8354         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8355         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8356         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8357
8358         /* FP SBs */
8359         for_each_eth_queue(bp, i) {
8360                 struct bnx2x_fastpath *fp = &bp->fp[i];
8361                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8362                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8363                            SB_DISABLED);
8364         }
8365
8366         if (CNIC_LOADED(bp))
8367                 /* CNIC SB */
8368                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8369                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8370                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8371
8372         /* SP SB */
8373         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8374                    CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8375                    SB_DISABLED);
8376
8377         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8378                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8379                        0);
8380
8381         /* Configure IGU */
8382         if (bp->common.int_block == INT_BLOCK_HC) {
8383                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8384                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8385         } else {
8386                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8387                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8388         }
8389
8390         if (CNIC_LOADED(bp)) {
8391                 /* Disable Timer scan */
8392                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8393                 /*
8394                  * Wait for at least 10ms and up to 2 second for the timers
8395                  * scan to complete
8396                  */
8397                 for (i = 0; i < 200; i++) {
8398                         msleep(10);
8399                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8400                                 break;
8401                 }
8402         }
8403         /* Clear ILT */
8404         bnx2x_clear_func_ilt(bp, func);
8405
8406         /* Timers workaround bug for E2: if this is vnic-3,
8407          * we need to set the entire ilt range for this timers.
8408          */
8409         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8410                 struct ilt_client_info ilt_cli;
8411                 /* use dummy TM client */
8412                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8413                 ilt_cli.start = 0;
8414                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8415                 ilt_cli.client_num = ILT_CLIENT_TM;
8416
8417                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8418         }
8419
8420         /* this assumes that reset_port() called before reset_func()*/
8421         if (!CHIP_IS_E1x(bp))
8422                 bnx2x_pf_disable(bp);
8423
8424         bp->dmae_ready = 0;
8425 }
8426
8427 static void bnx2x_reset_port(struct bnx2x *bp)
8428 {
8429         int port = BP_PORT(bp);
8430         u32 val;
8431
8432         /* Reset physical Link */
8433         bnx2x__link_reset(bp);
8434
8435         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8436
8437         /* Do not rcv packets to BRB */
8438         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8439         /* Do not direct rcv packets that are not for MCP to the BRB */
8440         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8441                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8442
8443         /* Configure AEU */
8444         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8445
8446         msleep(100);
8447         /* Check for BRB port occupancy */
8448         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8449         if (val)
8450                 DP(NETIF_MSG_IFDOWN,
8451                    "BRB1 is not empty  %d blocks are occupied\n", val);
8452
8453         /* TODO: Close Doorbell port? */
8454 }
8455
8456 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8457 {
8458         struct bnx2x_func_state_params func_params = {NULL};
8459
8460         /* Prepare parameters for function state transitions */
8461         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8462
8463         func_params.f_obj = &bp->func_obj;
8464         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8465
8466         func_params.params.hw_init.load_phase = load_code;
8467
8468         return bnx2x_func_state_change(bp, &func_params);
8469 }
8470
8471 static int bnx2x_func_stop(struct bnx2x *bp)
8472 {
8473         struct bnx2x_func_state_params func_params = {NULL};
8474         int rc;
8475
8476         /* Prepare parameters for function state transitions */
8477         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8478         func_params.f_obj = &bp->func_obj;
8479         func_params.cmd = BNX2X_F_CMD_STOP;
8480
8481         /*
8482          * Try to stop the function the 'good way'. If fails (in case
8483          * of a parity error during bnx2x_chip_cleanup()) and we are
8484          * not in a debug mode, perform a state transaction in order to
8485          * enable further HW_RESET transaction.
8486          */
8487         rc = bnx2x_func_state_change(bp, &func_params);
8488         if (rc) {
8489 #ifdef BNX2X_STOP_ON_ERROR
8490                 return rc;
8491 #else
8492                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8493                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8494                 return bnx2x_func_state_change(bp, &func_params);
8495 #endif
8496         }
8497
8498         return 0;
8499 }
8500
8501 /**
8502  * bnx2x_send_unload_req - request unload mode from the MCP.
8503  *
8504  * @bp:                 driver handle
8505  * @unload_mode:        requested function's unload mode
8506  *
8507  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8508  */
8509 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8510 {
8511         u32 reset_code = 0;
8512         int port = BP_PORT(bp);
8513
8514         /* Select the UNLOAD request mode */
8515         if (unload_mode == UNLOAD_NORMAL)
8516                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8517
8518         else if (bp->flags & NO_WOL_FLAG)
8519                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8520
8521         else if (bp->wol) {
8522                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8523                 u8 *mac_addr = bp->dev->dev_addr;
8524                 u32 val;
8525                 u16 pmc;
8526
8527                 /* The mac address is written to entries 1-4 to
8528                  * preserve entry 0 which is used by the PMF
8529                  */
8530                 u8 entry = (BP_VN(bp) + 1)*8;
8531
8532                 val = (mac_addr[0] << 8) | mac_addr[1];
8533                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8534
8535                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8536                       (mac_addr[4] << 8) | mac_addr[5];
8537                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8538
8539                 /* Enable the PME and clear the status */
8540                 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8541                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8542                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8543
8544                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8545
8546         } else
8547                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8548
8549         /* Send the request to the MCP */
8550         if (!BP_NOMCP(bp))
8551                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8552         else {
8553                 int path = BP_PATH(bp);
8554
8555                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8556                    path, load_count[path][0], load_count[path][1],
8557                    load_count[path][2]);
8558                 load_count[path][0]--;
8559                 load_count[path][1 + port]--;
8560                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8561                    path, load_count[path][0], load_count[path][1],
8562                    load_count[path][2]);
8563                 if (load_count[path][0] == 0)
8564                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8565                 else if (load_count[path][1 + port] == 0)
8566                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8567                 else
8568                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8569         }
8570
8571         return reset_code;
8572 }
8573
8574 /**
8575  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8576  *
8577  * @bp:         driver handle
8578  * @keep_link:          true iff link should be kept up
8579  */
8580 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8581 {
8582         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8583
8584         /* Report UNLOAD_DONE to MCP */
8585         if (!BP_NOMCP(bp))
8586                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8587 }
8588
8589 static int bnx2x_func_wait_started(struct bnx2x *bp)
8590 {
8591         int tout = 50;
8592         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8593
8594         if (!bp->port.pmf)
8595                 return 0;
8596
8597         /*
8598          * (assumption: No Attention from MCP at this stage)
8599          * PMF probably in the middle of TXdisable/enable transaction
8600          * 1. Sync IRS for default SB
8601          * 2. Sync SP queue - this guarantes us that attention handling started
8602          * 3. Wait, that TXdisable/enable transaction completes
8603          *
8604          * 1+2 guranty that if DCBx attention was scheduled it already changed
8605          * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8606          * received complettion for the transaction the state is TX_STOPPED.
8607          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8608          * transaction.
8609          */
8610
8611         /* make sure default SB ISR is done */
8612         if (msix)
8613                 synchronize_irq(bp->msix_table[0].vector);
8614         else
8615                 synchronize_irq(bp->pdev->irq);
8616
8617         flush_workqueue(bnx2x_wq);
8618
8619         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8620                                 BNX2X_F_STATE_STARTED && tout--)
8621                 msleep(20);
8622
8623         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8624                                                 BNX2X_F_STATE_STARTED) {
8625 #ifdef BNX2X_STOP_ON_ERROR
8626                 BNX2X_ERR("Wrong function state\n");
8627                 return -EBUSY;
8628 #else
8629                 /*
8630                  * Failed to complete the transaction in a "good way"
8631                  * Force both transactions with CLR bit
8632                  */
8633                 struct bnx2x_func_state_params func_params = {NULL};
8634
8635                 DP(NETIF_MSG_IFDOWN,
8636                    "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8637
8638                 func_params.f_obj = &bp->func_obj;
8639                 __set_bit(RAMROD_DRV_CLR_ONLY,
8640                                         &func_params.ramrod_flags);
8641
8642                 /* STARTED-->TX_ST0PPED */
8643                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8644                 bnx2x_func_state_change(bp, &func_params);
8645
8646                 /* TX_ST0PPED-->STARTED */
8647                 func_params.cmd = BNX2X_F_CMD_TX_START;
8648                 return bnx2x_func_state_change(bp, &func_params);
8649 #endif
8650         }
8651
8652         return 0;
8653 }
8654
8655 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8656 {
8657         int port = BP_PORT(bp);
8658         int i, rc = 0;
8659         u8 cos;
8660         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8661         u32 reset_code;
8662
8663         /* Wait until tx fastpath tasks complete */
8664         for_each_tx_queue(bp, i) {
8665                 struct bnx2x_fastpath *fp = &bp->fp[i];
8666
8667                 for_each_cos_in_tx_queue(fp, cos)
8668                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8669 #ifdef BNX2X_STOP_ON_ERROR
8670                 if (rc)
8671                         return;
8672 #endif
8673         }
8674
8675         /* Give HW time to discard old tx messages */
8676         usleep_range(1000, 1000);
8677
8678         /* Clean all ETH MACs */
8679         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8680                                 false);
8681         if (rc < 0)
8682                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8683
8684         /* Clean up UC list  */
8685         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8686                                 true);
8687         if (rc < 0)
8688                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8689                           rc);
8690
8691         /* Disable LLH */
8692         if (!CHIP_IS_E1(bp))
8693                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8694
8695         /* Set "drop all" (stop Rx).
8696          * We need to take a netif_addr_lock() here in order to prevent
8697          * a race between the completion code and this code.
8698          */
8699         netif_addr_lock_bh(bp->dev);
8700         /* Schedule the rx_mode command */
8701         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8702                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8703         else
8704                 bnx2x_set_storm_rx_mode(bp);
8705
8706         /* Cleanup multicast configuration */
8707         rparam.mcast_obj = &bp->mcast_obj;
8708         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8709         if (rc < 0)
8710                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8711
8712         netif_addr_unlock_bh(bp->dev);
8713
8714         bnx2x_iov_chip_cleanup(bp);
8715
8716
8717         /*
8718          * Send the UNLOAD_REQUEST to the MCP. This will return if
8719          * this function should perform FUNC, PORT or COMMON HW
8720          * reset.
8721          */
8722         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8723
8724         /*
8725          * (assumption: No Attention from MCP at this stage)
8726          * PMF probably in the middle of TXdisable/enable transaction
8727          */
8728         rc = bnx2x_func_wait_started(bp);
8729         if (rc) {
8730                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8731 #ifdef BNX2X_STOP_ON_ERROR
8732                 return;
8733 #endif
8734         }
8735
8736         /* Close multi and leading connections
8737          * Completions for ramrods are collected in a synchronous way
8738          */
8739         for_each_eth_queue(bp, i)
8740                 if (bnx2x_stop_queue(bp, i))
8741 #ifdef BNX2X_STOP_ON_ERROR
8742                         return;
8743 #else
8744                         goto unload_error;
8745 #endif
8746
8747         if (CNIC_LOADED(bp)) {
8748                 for_each_cnic_queue(bp, i)
8749                         if (bnx2x_stop_queue(bp, i))
8750 #ifdef BNX2X_STOP_ON_ERROR
8751                                 return;
8752 #else
8753                                 goto unload_error;
8754 #endif
8755         }
8756
8757         /* If SP settings didn't get completed so far - something
8758          * very wrong has happen.
8759          */
8760         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8761                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8762
8763 #ifndef BNX2X_STOP_ON_ERROR
8764 unload_error:
8765 #endif
8766         rc = bnx2x_func_stop(bp);
8767         if (rc) {
8768                 BNX2X_ERR("Function stop failed!\n");
8769 #ifdef BNX2X_STOP_ON_ERROR
8770                 return;
8771 #endif
8772         }
8773
8774         /* Disable HW interrupts, NAPI */
8775         bnx2x_netif_stop(bp, 1);
8776         /* Delete all NAPI objects */
8777         bnx2x_del_all_napi(bp);
8778         if (CNIC_LOADED(bp))
8779                 bnx2x_del_all_napi_cnic(bp);
8780
8781         /* Release IRQs */
8782         bnx2x_free_irq(bp);
8783
8784         /* Reset the chip */
8785         rc = bnx2x_reset_hw(bp, reset_code);
8786         if (rc)
8787                 BNX2X_ERR("HW_RESET failed\n");
8788
8789
8790         /* Report UNLOAD_DONE to MCP */
8791         bnx2x_send_unload_done(bp, keep_link);
8792 }
8793
8794 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8795 {
8796         u32 val;
8797
8798         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8799
8800         if (CHIP_IS_E1(bp)) {
8801                 int port = BP_PORT(bp);
8802                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8803                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8804
8805                 val = REG_RD(bp, addr);
8806                 val &= ~(0x300);
8807                 REG_WR(bp, addr, val);
8808         } else {
8809                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8810                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8811                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8812                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8813         }
8814 }
8815
8816 /* Close gates #2, #3 and #4: */
8817 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8818 {
8819         u32 val;
8820
8821         /* Gates #2 and #4a are closed/opened for "not E1" only */
8822         if (!CHIP_IS_E1(bp)) {
8823                 /* #4 */
8824                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8825                 /* #2 */
8826                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8827         }
8828
8829         /* #3 */
8830         if (CHIP_IS_E1x(bp)) {
8831                 /* Prevent interrupts from HC on both ports */
8832                 val = REG_RD(bp, HC_REG_CONFIG_1);
8833                 REG_WR(bp, HC_REG_CONFIG_1,
8834                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8835                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8836
8837                 val = REG_RD(bp, HC_REG_CONFIG_0);
8838                 REG_WR(bp, HC_REG_CONFIG_0,
8839                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8840                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8841         } else {
8842                 /* Prevent incomming interrupts in IGU */
8843                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8844
8845                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8846                        (!close) ?
8847                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8848                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8849         }
8850
8851         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8852                 close ? "closing" : "opening");
8853         mmiowb();
8854 }
8855
8856 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
8857
8858 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8859 {
8860         /* Do some magic... */
8861         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8862         *magic_val = val & SHARED_MF_CLP_MAGIC;
8863         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8864 }
8865
8866 /**
8867  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8868  *
8869  * @bp:         driver handle
8870  * @magic_val:  old value of the `magic' bit.
8871  */
8872 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8873 {
8874         /* Restore the `magic' bit value... */
8875         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8876         MF_CFG_WR(bp, shared_mf_config.clp_mb,
8877                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8878 }
8879
8880 /**
8881  * bnx2x_reset_mcp_prep - prepare for MCP reset.
8882  *
8883  * @bp:         driver handle
8884  * @magic_val:  old value of 'magic' bit.
8885  *
8886  * Takes care of CLP configurations.
8887  */
8888 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8889 {
8890         u32 shmem;
8891         u32 validity_offset;
8892
8893         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8894
8895         /* Set `magic' bit in order to save MF config */
8896         if (!CHIP_IS_E1(bp))
8897                 bnx2x_clp_reset_prep(bp, magic_val);
8898
8899         /* Get shmem offset */
8900         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8901         validity_offset =
8902                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8903
8904         /* Clear validity map flags */
8905         if (shmem > 0)
8906                 REG_WR(bp, shmem + validity_offset, 0);
8907 }
8908
8909 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
8910 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
8911
8912 /**
8913  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8914  *
8915  * @bp: driver handle
8916  */
8917 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8918 {
8919         /* special handling for emulation and FPGA,
8920            wait 10 times longer */
8921         if (CHIP_REV_IS_SLOW(bp))
8922                 msleep(MCP_ONE_TIMEOUT*10);
8923         else
8924                 msleep(MCP_ONE_TIMEOUT);
8925 }
8926
8927 /*
8928  * initializes bp->common.shmem_base and waits for validity signature to appear
8929  */
8930 static int bnx2x_init_shmem(struct bnx2x *bp)
8931 {
8932         int cnt = 0;
8933         u32 val = 0;
8934
8935         do {
8936                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8937                 if (bp->common.shmem_base) {
8938                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8939                         if (val & SHR_MEM_VALIDITY_MB)
8940                                 return 0;
8941                 }
8942
8943                 bnx2x_mcp_wait_one(bp);
8944
8945         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8946
8947         BNX2X_ERR("BAD MCP validity signature\n");
8948
8949         return -ENODEV;
8950 }
8951
8952 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8953 {
8954         int rc = bnx2x_init_shmem(bp);
8955
8956         /* Restore the `magic' bit value */
8957         if (!CHIP_IS_E1(bp))
8958                 bnx2x_clp_reset_done(bp, magic_val);
8959
8960         return rc;
8961 }
8962
8963 static void bnx2x_pxp_prep(struct bnx2x *bp)
8964 {
8965         if (!CHIP_IS_E1(bp)) {
8966                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8967                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8968                 mmiowb();
8969         }
8970 }
8971
8972 /*
8973  * Reset the whole chip except for:
8974  *      - PCIE core
8975  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8976  *              one reset bit)
8977  *      - IGU
8978  *      - MISC (including AEU)
8979  *      - GRC
8980  *      - RBCN, RBCP
8981  */
8982 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8983 {
8984         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8985         u32 global_bits2, stay_reset2;
8986
8987         /*
8988          * Bits that have to be set in reset_mask2 if we want to reset 'global'
8989          * (per chip) blocks.
8990          */
8991         global_bits2 =
8992                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8993                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8994
8995         /* Don't reset the following blocks.
8996          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
8997          *            reset, as in 4 port device they might still be owned
8998          *            by the MCP (there is only one leader per path).
8999          */
9000         not_reset_mask1 =
9001                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9002                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9003                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9004
9005         not_reset_mask2 =
9006                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9007                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9008                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9009                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9010                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9011                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9012                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9013                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9014                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9015                 MISC_REGISTERS_RESET_REG_2_PGLC |
9016                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9017                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9018                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9019                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9020                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9021                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9022
9023         /*
9024          * Keep the following blocks in reset:
9025          *  - all xxMACs are handled by the bnx2x_link code.
9026          */
9027         stay_reset2 =
9028                 MISC_REGISTERS_RESET_REG_2_XMAC |
9029                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9030
9031         /* Full reset masks according to the chip */
9032         reset_mask1 = 0xffffffff;
9033
9034         if (CHIP_IS_E1(bp))
9035                 reset_mask2 = 0xffff;
9036         else if (CHIP_IS_E1H(bp))
9037                 reset_mask2 = 0x1ffff;
9038         else if (CHIP_IS_E2(bp))
9039                 reset_mask2 = 0xfffff;
9040         else /* CHIP_IS_E3 */
9041                 reset_mask2 = 0x3ffffff;
9042
9043         /* Don't reset global blocks unless we need to */
9044         if (!global)
9045                 reset_mask2 &= ~global_bits2;
9046
9047         /*
9048          * In case of attention in the QM, we need to reset PXP
9049          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9050          * because otherwise QM reset would release 'close the gates' shortly
9051          * before resetting the PXP, then the PSWRQ would send a write
9052          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9053          * read the payload data from PSWWR, but PSWWR would not
9054          * respond. The write queue in PGLUE would stuck, dmae commands
9055          * would not return. Therefore it's important to reset the second
9056          * reset register (containing the
9057          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9058          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9059          * bit).
9060          */
9061         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9062                reset_mask2 & (~not_reset_mask2));
9063
9064         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9065                reset_mask1 & (~not_reset_mask1));
9066
9067         barrier();
9068         mmiowb();
9069
9070         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9071                reset_mask2 & (~stay_reset2));
9072
9073         barrier();
9074         mmiowb();
9075
9076         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9077         mmiowb();
9078 }
9079
9080 /**
9081  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9082  * It should get cleared in no more than 1s.
9083  *
9084  * @bp: driver handle
9085  *
9086  * It should get cleared in no more than 1s. Returns 0 if
9087  * pending writes bit gets cleared.
9088  */
9089 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9090 {
9091         u32 cnt = 1000;
9092         u32 pend_bits = 0;
9093
9094         do {
9095                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9096
9097                 if (pend_bits == 0)
9098                         break;
9099
9100                 usleep_range(1000, 1000);
9101         } while (cnt-- > 0);
9102
9103         if (cnt <= 0) {
9104                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9105                           pend_bits);
9106                 return -EBUSY;
9107         }
9108
9109         return 0;
9110 }
9111
9112 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9113 {
9114         int cnt = 1000;
9115         u32 val = 0;
9116         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9117                 u32 tags_63_32 = 0;
9118
9119
9120         /* Empty the Tetris buffer, wait for 1s */
9121         do {
9122                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9123                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9124                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9125                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9126                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9127                 if (CHIP_IS_E3(bp))
9128                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9129
9130                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9131                     ((port_is_idle_0 & 0x1) == 0x1) &&
9132                     ((port_is_idle_1 & 0x1) == 0x1) &&
9133                     (pgl_exp_rom2 == 0xffffffff) &&
9134                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9135                         break;
9136                 usleep_range(1000, 1000);
9137         } while (cnt-- > 0);
9138
9139         if (cnt <= 0) {
9140                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9141                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9142                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9143                           pgl_exp_rom2);
9144                 return -EAGAIN;
9145         }
9146
9147         barrier();
9148
9149         /* Close gates #2, #3 and #4 */
9150         bnx2x_set_234_gates(bp, true);
9151
9152         /* Poll for IGU VQs for 57712 and newer chips */
9153         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9154                 return -EAGAIN;
9155
9156
9157         /* TBD: Indicate that "process kill" is in progress to MCP */
9158
9159         /* Clear "unprepared" bit */
9160         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9161         barrier();
9162
9163         /* Make sure all is written to the chip before the reset */
9164         mmiowb();
9165
9166         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9167          * PSWHST, GRC and PSWRD Tetris buffer.
9168          */
9169         usleep_range(1000, 1000);
9170
9171         /* Prepare to chip reset: */
9172         /* MCP */
9173         if (global)
9174                 bnx2x_reset_mcp_prep(bp, &val);
9175
9176         /* PXP */
9177         bnx2x_pxp_prep(bp);
9178         barrier();
9179
9180         /* reset the chip */
9181         bnx2x_process_kill_chip_reset(bp, global);
9182         barrier();
9183
9184         /* Recover after reset: */
9185         /* MCP */
9186         if (global && bnx2x_reset_mcp_comp(bp, val))
9187                 return -EAGAIN;
9188
9189         /* TBD: Add resetting the NO_MCP mode DB here */
9190
9191         /* Open the gates #2, #3 and #4 */
9192         bnx2x_set_234_gates(bp, false);
9193
9194         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9195          * reset state, re-enable attentions. */
9196
9197         return 0;
9198 }
9199
9200 static int bnx2x_leader_reset(struct bnx2x *bp)
9201 {
9202         int rc = 0;
9203         bool global = bnx2x_reset_is_global(bp);
9204         u32 load_code;
9205
9206         /* if not going to reset MCP - load "fake" driver to reset HW while
9207          * driver is owner of the HW
9208          */
9209         if (!global && !BP_NOMCP(bp)) {
9210                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9211                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9212                 if (!load_code) {
9213                         BNX2X_ERR("MCP response failure, aborting\n");
9214                         rc = -EAGAIN;
9215                         goto exit_leader_reset;
9216                 }
9217                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9218                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9219                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9220                         rc = -EAGAIN;
9221                         goto exit_leader_reset2;
9222                 }
9223                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9224                 if (!load_code) {
9225                         BNX2X_ERR("MCP response failure, aborting\n");
9226                         rc = -EAGAIN;
9227                         goto exit_leader_reset2;
9228                 }
9229         }
9230
9231         /* Try to recover after the failure */
9232         if (bnx2x_process_kill(bp, global)) {
9233                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9234                           BP_PATH(bp));
9235                 rc = -EAGAIN;
9236                 goto exit_leader_reset2;
9237         }
9238
9239         /*
9240          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9241          * state.
9242          */
9243         bnx2x_set_reset_done(bp);
9244         if (global)
9245                 bnx2x_clear_reset_global(bp);
9246
9247 exit_leader_reset2:
9248         /* unload "fake driver" if it was loaded */
9249         if (!global && !BP_NOMCP(bp)) {
9250                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9251                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9252         }
9253 exit_leader_reset:
9254         bp->is_leader = 0;
9255         bnx2x_release_leader_lock(bp);
9256         smp_mb();
9257         return rc;
9258 }
9259
9260 static void bnx2x_recovery_failed(struct bnx2x *bp)
9261 {
9262         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9263
9264         /* Disconnect this device */
9265         netif_device_detach(bp->dev);
9266
9267         /*
9268          * Block ifup for all function on this engine until "process kill"
9269          * or power cycle.
9270          */
9271         bnx2x_set_reset_in_progress(bp);
9272
9273         /* Shut down the power */
9274         bnx2x_set_power_state(bp, PCI_D3hot);
9275
9276         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9277
9278         smp_mb();
9279 }
9280
9281 /*
9282  * Assumption: runs under rtnl lock. This together with the fact
9283  * that it's called only from bnx2x_sp_rtnl() ensure that it
9284  * will never be called when netif_running(bp->dev) is false.
9285  */
9286 static void bnx2x_parity_recover(struct bnx2x *bp)
9287 {
9288         bool global = false;
9289         u32 error_recovered, error_unrecovered;
9290         bool is_parity;
9291
9292         DP(NETIF_MSG_HW, "Handling parity\n");
9293         while (1) {
9294                 switch (bp->recovery_state) {
9295                 case BNX2X_RECOVERY_INIT:
9296                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9297                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9298                         WARN_ON(!is_parity);
9299
9300                         /* Try to get a LEADER_LOCK HW lock */
9301                         if (bnx2x_trylock_leader_lock(bp)) {
9302                                 bnx2x_set_reset_in_progress(bp);
9303                                 /*
9304                                  * Check if there is a global attention and if
9305                                  * there was a global attention, set the global
9306                                  * reset bit.
9307                                  */
9308
9309                                 if (global)
9310                                         bnx2x_set_reset_global(bp);
9311
9312                                 bp->is_leader = 1;
9313                         }
9314
9315                         /* Stop the driver */
9316                         /* If interface has been removed - break */
9317                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9318                                 return;
9319
9320                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9321
9322                         /* Ensure "is_leader", MCP command sequence and
9323                          * "recovery_state" update values are seen on other
9324                          * CPUs.
9325                          */
9326                         smp_mb();
9327                         break;
9328
9329                 case BNX2X_RECOVERY_WAIT:
9330                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9331                         if (bp->is_leader) {
9332                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9333                                 bool other_load_status =
9334                                         bnx2x_get_load_status(bp, other_engine);
9335                                 bool load_status =
9336                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9337                                 global = bnx2x_reset_is_global(bp);
9338
9339                                 /*
9340                                  * In case of a parity in a global block, let
9341                                  * the first leader that performs a
9342                                  * leader_reset() reset the global blocks in
9343                                  * order to clear global attentions. Otherwise
9344                                  * the the gates will remain closed for that
9345                                  * engine.
9346                                  */
9347                                 if (load_status ||
9348                                     (global && other_load_status)) {
9349                                         /* Wait until all other functions get
9350                                          * down.
9351                                          */
9352                                         schedule_delayed_work(&bp->sp_rtnl_task,
9353                                                                 HZ/10);
9354                                         return;
9355                                 } else {
9356                                         /* If all other functions got down -
9357                                          * try to bring the chip back to
9358                                          * normal. In any case it's an exit
9359                                          * point for a leader.
9360                                          */
9361                                         if (bnx2x_leader_reset(bp)) {
9362                                                 bnx2x_recovery_failed(bp);
9363                                                 return;
9364                                         }
9365
9366                                         /* If we are here, means that the
9367                                          * leader has succeeded and doesn't
9368                                          * want to be a leader any more. Try
9369                                          * to continue as a none-leader.
9370                                          */
9371                                         break;
9372                                 }
9373                         } else { /* non-leader */
9374                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9375                                         /* Try to get a LEADER_LOCK HW lock as
9376                                          * long as a former leader may have
9377                                          * been unloaded by the user or
9378                                          * released a leadership by another
9379                                          * reason.
9380                                          */
9381                                         if (bnx2x_trylock_leader_lock(bp)) {
9382                                                 /* I'm a leader now! Restart a
9383                                                  * switch case.
9384                                                  */
9385                                                 bp->is_leader = 1;
9386                                                 break;
9387                                         }
9388
9389                                         schedule_delayed_work(&bp->sp_rtnl_task,
9390                                                                 HZ/10);
9391                                         return;
9392
9393                                 } else {
9394                                         /*
9395                                          * If there was a global attention, wait
9396                                          * for it to be cleared.
9397                                          */
9398                                         if (bnx2x_reset_is_global(bp)) {
9399                                                 schedule_delayed_work(
9400                                                         &bp->sp_rtnl_task,
9401                                                         HZ/10);
9402                                                 return;
9403                                         }
9404
9405                                         error_recovered =
9406                                           bp->eth_stats.recoverable_error;
9407                                         error_unrecovered =
9408                                           bp->eth_stats.unrecoverable_error;
9409                                         bp->recovery_state =
9410                                                 BNX2X_RECOVERY_NIC_LOADING;
9411                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9412                                                 error_unrecovered++;
9413                                                 netdev_err(bp->dev,
9414                                                            "Recovery failed. Power cycle needed\n");
9415                                                 /* Disconnect this device */
9416                                                 netif_device_detach(bp->dev);
9417                                                 /* Shut down the power */
9418                                                 bnx2x_set_power_state(
9419                                                         bp, PCI_D3hot);
9420                                                 smp_mb();
9421                                         } else {
9422                                                 bp->recovery_state =
9423                                                         BNX2X_RECOVERY_DONE;
9424                                                 error_recovered++;
9425                                                 smp_mb();
9426                                         }
9427                                         bp->eth_stats.recoverable_error =
9428                                                 error_recovered;
9429                                         bp->eth_stats.unrecoverable_error =
9430                                                 error_unrecovered;
9431
9432                                         return;
9433                                 }
9434                         }
9435                 default:
9436                         return;
9437                 }
9438         }
9439 }
9440
9441 static int bnx2x_close(struct net_device *dev);
9442
9443 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9444  * scheduled on a general queue in order to prevent a dead lock.
9445  */
9446 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9447 {
9448         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9449
9450         rtnl_lock();
9451
9452         if (!netif_running(bp->dev)) {
9453                 rtnl_unlock();
9454                 return;
9455         }
9456
9457         /* if stop on error is defined no recovery flows should be executed */
9458 #ifdef BNX2X_STOP_ON_ERROR
9459         BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9460                   "you will need to reboot when done\n");
9461         goto sp_rtnl_not_reset;
9462 #endif
9463
9464         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9465                 /*
9466                  * Clear all pending SP commands as we are going to reset the
9467                  * function anyway.
9468                  */
9469                 bp->sp_rtnl_state = 0;
9470                 smp_mb();
9471
9472                 bnx2x_parity_recover(bp);
9473
9474                 rtnl_unlock();
9475                 return;
9476         }
9477
9478         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9479                 /*
9480                  * Clear all pending SP commands as we are going to reset the
9481                  * function anyway.
9482                  */
9483                 bp->sp_rtnl_state = 0;
9484                 smp_mb();
9485
9486                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9487                 bnx2x_nic_load(bp, LOAD_NORMAL);
9488
9489                 rtnl_unlock();
9490                 return;
9491         }
9492 #ifdef BNX2X_STOP_ON_ERROR
9493 sp_rtnl_not_reset:
9494 #endif
9495         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9496                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9497         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9498                 bnx2x_after_function_update(bp);
9499         /*
9500          * in case of fan failure we need to reset id if the "stop on error"
9501          * debug flag is set, since we trying to prevent permanent overheating
9502          * damage
9503          */
9504         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9505                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9506                 netif_device_detach(bp->dev);
9507                 bnx2x_close(bp->dev);
9508                 rtnl_unlock();
9509                 return;
9510         }
9511
9512         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9513                 DP(BNX2X_MSG_SP,
9514                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9515                 bnx2x_vfpf_set_mcast(bp->dev);
9516         }
9517
9518         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9519                                &bp->sp_rtnl_state)) {
9520                 DP(BNX2X_MSG_SP,
9521                    "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9522                 bnx2x_vfpf_storm_rx_mode(bp);
9523         }
9524
9525         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9526          * can be called from other contexts as well)
9527          */
9528
9529         rtnl_unlock();
9530
9531         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9532                                                &bp->sp_rtnl_state)) {
9533                 int rc = 0;
9534
9535                 /* disbale sriov in case it is still enabled */
9536                 pci_disable_sriov(bp->pdev);
9537                 DP(BNX2X_MSG_IOV, "sriov disabled\n");
9538
9539                 /* enable sriov */
9540                 DP(BNX2X_MSG_IOV, "vf num (%d)\n", (bp->vfdb->sriov.nr_virtfn));
9541                 rc = pci_enable_sriov(bp->pdev, (bp->vfdb->sriov.nr_virtfn));
9542                 if (rc)
9543                         BNX2X_ERR("pci_enable_sriov failed with %d\n", rc);
9544                 else
9545                         DP(BNX2X_MSG_IOV, "sriov enabled\n");
9546         }
9547 }
9548
9549 /* end of nic load/unload */
9550
9551 static void bnx2x_period_task(struct work_struct *work)
9552 {
9553         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9554
9555         if (!netif_running(bp->dev))
9556                 goto period_task_exit;
9557
9558         if (CHIP_REV_IS_SLOW(bp)) {
9559                 BNX2X_ERR("period task called on emulation, ignoring\n");
9560                 goto period_task_exit;
9561         }
9562
9563         bnx2x_acquire_phy_lock(bp);
9564         /*
9565          * The barrier is needed to ensure the ordering between the writing to
9566          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9567          * the reading here.
9568          */
9569         smp_mb();
9570         if (bp->port.pmf) {
9571                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9572
9573                 /* Re-queue task in 1 sec */
9574                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9575         }
9576
9577         bnx2x_release_phy_lock(bp);
9578 period_task_exit:
9579         return;
9580 }
9581
9582 /*
9583  * Init service functions
9584  */
9585
9586 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9587 {
9588         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9589         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9590         return base + (BP_ABS_FUNC(bp)) * stride;
9591 }
9592
9593 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9594 {
9595         u32 reg = bnx2x_get_pretend_reg(bp);
9596
9597         /* Flush all outstanding writes */
9598         mmiowb();
9599
9600         /* Pretend to be function 0 */
9601         REG_WR(bp, reg, 0);
9602         REG_RD(bp, reg);        /* Flush the GRC transaction (in the chip) */
9603
9604         /* From now we are in the "like-E1" mode */
9605         bnx2x_int_disable(bp);
9606
9607         /* Flush all outstanding writes */
9608         mmiowb();
9609
9610         /* Restore the original function */
9611         REG_WR(bp, reg, BP_ABS_FUNC(bp));
9612         REG_RD(bp, reg);
9613 }
9614
9615 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9616 {
9617         if (CHIP_IS_E1(bp))
9618                 bnx2x_int_disable(bp);
9619         else
9620                 bnx2x_undi_int_disable_e1h(bp);
9621 }
9622
9623 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9624 {
9625         u32 val, base_addr, offset, mask, reset_reg;
9626         bool mac_stopped = false;
9627         u8 port = BP_PORT(bp);
9628
9629         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9630
9631         if (!CHIP_IS_E3(bp)) {
9632                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9633                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9634                 if ((mask & reset_reg) && val) {
9635                         u32 wb_data[2];
9636                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9637                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9638                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9639                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9640                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9641
9642                         /*
9643                          * use rd/wr since we cannot use dmae. This is safe
9644                          * since MCP won't access the bus due to the request
9645                          * to unload, and no function on the path can be
9646                          * loaded at this time.
9647                          */
9648                         wb_data[0] = REG_RD(bp, base_addr + offset);
9649                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9650                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9651                         REG_WR(bp, base_addr + offset, wb_data[0]);
9652                         REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9653
9654                 }
9655                 BNX2X_DEV_INFO("Disable emac Rx\n");
9656                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9657
9658                 mac_stopped = true;
9659         } else {
9660                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9661                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9662                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9663                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9664                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9665                                val & ~(1 << 1));
9666                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9667                                val | (1 << 1));
9668                         REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9669                         mac_stopped = true;
9670                 }
9671                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9672                 if (mask & reset_reg) {
9673                         BNX2X_DEV_INFO("Disable umac Rx\n");
9674                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9675                         REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9676                         mac_stopped = true;
9677                 }
9678         }
9679
9680         if (mac_stopped)
9681                 msleep(20);
9682
9683 }
9684
9685 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9686 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9687 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9688 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9689
9690 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9691 {
9692         u16 rcq, bd;
9693         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9694
9695         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9696         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9697
9698         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9699         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9700
9701         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9702                        port, bd, rcq);
9703 }
9704
9705 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9706 {
9707         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9708                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9709         if (!rc) {
9710                 BNX2X_ERR("MCP response failure, aborting\n");
9711                 return -EBUSY;
9712         }
9713
9714         return 0;
9715 }
9716
9717 static struct bnx2x_prev_path_list *
9718                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9719 {
9720         struct bnx2x_prev_path_list *tmp_list;
9721
9722         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9723                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9724                     bp->pdev->bus->number == tmp_list->bus &&
9725                     BP_PATH(bp) == tmp_list->path)
9726                         return tmp_list;
9727
9728         return NULL;
9729 }
9730
9731 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9732 {
9733         struct bnx2x_prev_path_list *tmp_list;
9734         int rc = false;
9735
9736         if (down_trylock(&bnx2x_prev_sem))
9737                 return false;
9738
9739         list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9740                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9741                     bp->pdev->bus->number == tmp_list->bus &&
9742                     BP_PATH(bp) == tmp_list->path) {
9743                         rc = true;
9744                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9745                                        BP_PATH(bp));
9746                         break;
9747                 }
9748         }
9749
9750         up(&bnx2x_prev_sem);
9751
9752         return rc;
9753 }
9754
9755 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9756 {
9757         struct bnx2x_prev_path_list *tmp_list;
9758         int rc;
9759
9760         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9761         if (!tmp_list) {
9762                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9763                 return -ENOMEM;
9764         }
9765
9766         tmp_list->bus = bp->pdev->bus->number;
9767         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9768         tmp_list->path = BP_PATH(bp);
9769         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9770
9771         rc = down_interruptible(&bnx2x_prev_sem);
9772         if (rc) {
9773                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9774                 kfree(tmp_list);
9775         } else {
9776                 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9777                                 BP_PATH(bp));
9778                 list_add(&tmp_list->list, &bnx2x_prev_list);
9779                 up(&bnx2x_prev_sem);
9780         }
9781
9782         return rc;
9783 }
9784
9785 static int bnx2x_do_flr(struct bnx2x *bp)
9786 {
9787         int i;
9788         u16 status;
9789         struct pci_dev *dev = bp->pdev;
9790
9791
9792         if (CHIP_IS_E1x(bp)) {
9793                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9794                 return -EINVAL;
9795         }
9796
9797         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9798         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9799                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9800                           bp->common.bc_ver);
9801                 return -EINVAL;
9802         }
9803
9804         /* Wait for Transaction Pending bit clean */
9805         for (i = 0; i < 4; i++) {
9806                 if (i)
9807                         msleep((1 << (i - 1)) * 100);
9808
9809                 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9810                 if (!(status & PCI_EXP_DEVSTA_TRPND))
9811                         goto clear;
9812         }
9813
9814         dev_err(&dev->dev,
9815                 "transaction is not cleared; proceeding with reset anyway\n");
9816
9817 clear:
9818
9819         BNX2X_DEV_INFO("Initiating FLR\n");
9820         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9821
9822         return 0;
9823 }
9824
9825 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9826 {
9827         int rc;
9828
9829         BNX2X_DEV_INFO("Uncommon unload Flow\n");
9830
9831         /* Test if previous unload process was already finished for this path */
9832         if (bnx2x_prev_is_path_marked(bp))
9833                 return bnx2x_prev_mcp_done(bp);
9834
9835         /* If function has FLR capabilities, and existing FW version matches
9836          * the one required, then FLR will be sufficient to clean any residue
9837          * left by previous driver
9838          */
9839         rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9840
9841         if (!rc) {
9842                 /* fw version is good */
9843                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9844                 rc = bnx2x_do_flr(bp);
9845         }
9846
9847         if (!rc) {
9848                 /* FLR was performed */
9849                 BNX2X_DEV_INFO("FLR successful\n");
9850                 return 0;
9851         }
9852
9853         BNX2X_DEV_INFO("Could not FLR\n");
9854
9855         /* Close the MCP request, return failure*/
9856         rc = bnx2x_prev_mcp_done(bp);
9857         if (!rc)
9858                 rc = BNX2X_PREV_WAIT_NEEDED;
9859
9860         return rc;
9861 }
9862
9863 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9864 {
9865         u32 reset_reg, tmp_reg = 0, rc;
9866         bool prev_undi = false;
9867         /* It is possible a previous function received 'common' answer,
9868          * but hasn't loaded yet, therefore creating a scenario of
9869          * multiple functions receiving 'common' on the same path.
9870          */
9871         BNX2X_DEV_INFO("Common unload Flow\n");
9872
9873         if (bnx2x_prev_is_path_marked(bp))
9874                 return bnx2x_prev_mcp_done(bp);
9875
9876         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9877
9878         /* Reset should be performed after BRB is emptied */
9879         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9880                 u32 timer_count = 1000;
9881
9882                 /* Close the MAC Rx to prevent BRB from filling up */
9883                 bnx2x_prev_unload_close_mac(bp);
9884
9885                 /* Check if the UNDI driver was previously loaded
9886                  * UNDI driver initializes CID offset for normal bell to 0x7
9887                  */
9888                 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9889                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9890                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9891                         if (tmp_reg == 0x7) {
9892                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
9893                                 prev_undi = true;
9894                                 /* clear the UNDI indication */
9895                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9896                         }
9897                 }
9898                 /* wait until BRB is empty */
9899                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9900                 while (timer_count) {
9901                         u32 prev_brb = tmp_reg;
9902
9903                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9904                         if (!tmp_reg)
9905                                 break;
9906
9907                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9908
9909                         /* reset timer as long as BRB actually gets emptied */
9910                         if (prev_brb > tmp_reg)
9911                                 timer_count = 1000;
9912                         else
9913                                 timer_count--;
9914
9915                         /* If UNDI resides in memory, manually increment it */
9916                         if (prev_undi)
9917                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9918
9919                         udelay(10);
9920                 }
9921
9922                 if (!timer_count)
9923                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9924
9925         }
9926
9927         /* No packets are in the pipeline, path is ready for reset */
9928         bnx2x_reset_common(bp);
9929
9930         rc = bnx2x_prev_mark_path(bp, prev_undi);
9931         if (rc) {
9932                 bnx2x_prev_mcp_done(bp);
9933                 return rc;
9934         }
9935
9936         return bnx2x_prev_mcp_done(bp);
9937 }
9938
9939 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9940  * and boot began, or when kdump kernel was loaded. Either case would invalidate
9941  * the addresses of the transaction, resulting in was-error bit set in the pci
9942  * causing all hw-to-host pcie transactions to timeout. If this happened we want
9943  * to clear the interrupt which detected this from the pglueb and the was done
9944  * bit
9945  */
9946 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9947 {
9948         if (!CHIP_IS_E1x(bp)) {
9949                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9950                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9951                         BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9952                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9953                                1 << BP_FUNC(bp));
9954                 }
9955         }
9956 }
9957
9958 static int bnx2x_prev_unload(struct bnx2x *bp)
9959 {
9960         int time_counter = 10;
9961         u32 rc, fw, hw_lock_reg, hw_lock_val;
9962         struct bnx2x_prev_path_list *prev_list;
9963         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9964
9965         /* clear hw from errors which may have resulted from an interrupted
9966          * dmae transaction.
9967          */
9968         bnx2x_prev_interrupted_dmae(bp);
9969
9970         /* Release previously held locks */
9971         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9972                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9973                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9974
9975         hw_lock_val = (REG_RD(bp, hw_lock_reg));
9976         if (hw_lock_val) {
9977                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9978                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9979                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9980                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9981                 }
9982
9983                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9984                 REG_WR(bp, hw_lock_reg, 0xffffffff);
9985         } else
9986                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9987
9988         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9989                 BNX2X_DEV_INFO("Release previously held alr\n");
9990                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9991         }
9992
9993
9994         do {
9995                 /* Lock MCP using an unload request */
9996                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9997                 if (!fw) {
9998                         BNX2X_ERR("MCP response failure, aborting\n");
9999                         rc = -EBUSY;
10000                         break;
10001                 }
10002
10003                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
10004                         rc = bnx2x_prev_unload_common(bp);
10005                         break;
10006                 }
10007
10008                 /* non-common reply from MCP night require looping */
10009                 rc = bnx2x_prev_unload_uncommon(bp);
10010                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10011                         break;
10012
10013                 msleep(20);
10014         } while (--time_counter);
10015
10016         if (!time_counter || rc) {
10017                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10018                 rc = -EBUSY;
10019         }
10020
10021         /* Mark function if its port was used to boot from SAN */
10022         prev_list = bnx2x_prev_path_get_entry(bp);
10023         if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
10024                 bp->link_params.feature_config_flags |=
10025                         FEATURE_CONFIG_BOOT_FROM_SAN;
10026
10027         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10028
10029         return rc;
10030 }
10031
10032 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10033 {
10034         u32 val, val2, val3, val4, id, boot_mode;
10035         u16 pmc;
10036
10037         /* Get the chip revision id and number. */
10038         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10039         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10040         id = ((val & 0xffff) << 16);
10041         val = REG_RD(bp, MISC_REG_CHIP_REV);
10042         id |= ((val & 0xf) << 12);
10043         val = REG_RD(bp, MISC_REG_CHIP_METAL);
10044         id |= ((val & 0xff) << 4);
10045         val = REG_RD(bp, MISC_REG_BOND_ID);
10046         id |= (val & 0xf);
10047         bp->common.chip_id = id;
10048
10049         /* force 57811 according to MISC register */
10050         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10051                 if (CHIP_IS_57810(bp))
10052                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10053                                 (bp->common.chip_id & 0x0000FFFF);
10054                 else if (CHIP_IS_57810_MF(bp))
10055                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10056                                 (bp->common.chip_id & 0x0000FFFF);
10057                 bp->common.chip_id |= 0x1;
10058         }
10059
10060         /* Set doorbell size */
10061         bp->db_size = (1 << BNX2X_DB_SHIFT);
10062
10063         if (!CHIP_IS_E1x(bp)) {
10064                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10065                 if ((val & 1) == 0)
10066                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10067                 else
10068                         val = (val >> 1) & 1;
10069                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10070                                                        "2_PORT_MODE");
10071                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10072                                                  CHIP_2_PORT_MODE;
10073
10074                 if (CHIP_MODE_IS_4_PORT(bp))
10075                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10076                 else
10077                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10078         } else {
10079                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10080                 bp->pfid = bp->pf_num;                  /* 0..7 */
10081         }
10082
10083         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10084
10085         bp->link_params.chip_id = bp->common.chip_id;
10086         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10087
10088         val = (REG_RD(bp, 0x2874) & 0x55);
10089         if ((bp->common.chip_id & 0x1) ||
10090             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10091                 bp->flags |= ONE_PORT_FLAG;
10092                 BNX2X_DEV_INFO("single port device\n");
10093         }
10094
10095         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10096         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10097                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10098         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10099                        bp->common.flash_size, bp->common.flash_size);
10100
10101         bnx2x_init_shmem(bp);
10102
10103
10104
10105         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10106                                         MISC_REG_GENERIC_CR_1 :
10107                                         MISC_REG_GENERIC_CR_0));
10108
10109         bp->link_params.shmem_base = bp->common.shmem_base;
10110         bp->link_params.shmem2_base = bp->common.shmem2_base;
10111         if (SHMEM2_RD(bp, size) >
10112             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10113                 bp->link_params.lfa_base =
10114                 REG_RD(bp, bp->common.shmem2_base +
10115                        (u32)offsetof(struct shmem2_region,
10116                                      lfa_host_addr[BP_PORT(bp)]));
10117         else
10118                 bp->link_params.lfa_base = 0;
10119         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10120                        bp->common.shmem_base, bp->common.shmem2_base);
10121
10122         if (!bp->common.shmem_base) {
10123                 BNX2X_DEV_INFO("MCP not active\n");
10124                 bp->flags |= NO_MCP_FLAG;
10125                 return;
10126         }
10127
10128         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10129         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10130
10131         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10132                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10133                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10134
10135         bp->link_params.feature_config_flags = 0;
10136         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10137         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10138                 bp->link_params.feature_config_flags |=
10139                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10140         else
10141                 bp->link_params.feature_config_flags &=
10142                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10143
10144         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10145         bp->common.bc_ver = val;
10146         BNX2X_DEV_INFO("bc_ver %X\n", val);
10147         if (val < BNX2X_BC_VER) {
10148                 /* for now only warn
10149                  * later we might need to enforce this */
10150                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10151                           BNX2X_BC_VER, val);
10152         }
10153         bp->link_params.feature_config_flags |=
10154                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10155                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10156
10157         bp->link_params.feature_config_flags |=
10158                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10159                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10160         bp->link_params.feature_config_flags |=
10161                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10162                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10163         bp->link_params.feature_config_flags |=
10164                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10165                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10166
10167         bp->link_params.feature_config_flags |=
10168                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10169                 FEATURE_CONFIG_MT_SUPPORT : 0;
10170
10171         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10172                         BC_SUPPORTS_PFC_STATS : 0;
10173
10174         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10175                         BC_SUPPORTS_FCOE_FEATURES : 0;
10176
10177         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10178                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10179         boot_mode = SHMEM_RD(bp,
10180                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10181                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10182         switch (boot_mode) {
10183         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10184                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10185                 break;
10186         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10187                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10188                 break;
10189         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10190                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10191                 break;
10192         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10193                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10194                 break;
10195         }
10196
10197         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10198         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10199
10200         BNX2X_DEV_INFO("%sWoL capable\n",
10201                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10202
10203         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10204         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10205         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10206         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10207
10208         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10209                  val, val2, val3, val4);
10210 }
10211
10212 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10213 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10214
10215 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10216 {
10217         int pfid = BP_FUNC(bp);
10218         int igu_sb_id;
10219         u32 val;
10220         u8 fid, igu_sb_cnt = 0;
10221
10222         bp->igu_base_sb = 0xff;
10223         if (CHIP_INT_MODE_IS_BC(bp)) {
10224                 int vn = BP_VN(bp);
10225                 igu_sb_cnt = bp->igu_sb_cnt;
10226                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10227                         FP_SB_MAX_E1x;
10228
10229                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10230                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10231
10232                 return 0;
10233         }
10234
10235         /* IGU in normal mode - read CAM */
10236         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10237              igu_sb_id++) {
10238                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10239                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10240                         continue;
10241                 fid = IGU_FID(val);
10242                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10243                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10244                                 continue;
10245                         if (IGU_VEC(val) == 0)
10246                                 /* default status block */
10247                                 bp->igu_dsb_id = igu_sb_id;
10248                         else {
10249                                 if (bp->igu_base_sb == 0xff)
10250                                         bp->igu_base_sb = igu_sb_id;
10251                                 igu_sb_cnt++;
10252                         }
10253                 }
10254         }
10255
10256 #ifdef CONFIG_PCI_MSI
10257         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10258          * optional that number of CAM entries will not be equal to the value
10259          * advertised in PCI.
10260          * Driver should use the minimal value of both as the actual status
10261          * block count
10262          */
10263         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10264 #endif
10265
10266         if (igu_sb_cnt == 0) {
10267                 BNX2X_ERR("CAM configuration error\n");
10268                 return -EINVAL;
10269         }
10270
10271         return 0;
10272 }
10273
10274 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10275 {
10276         int cfg_size = 0, idx, port = BP_PORT(bp);
10277
10278         /* Aggregation of supported attributes of all external phys */
10279         bp->port.supported[0] = 0;
10280         bp->port.supported[1] = 0;
10281         switch (bp->link_params.num_phys) {
10282         case 1:
10283                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10284                 cfg_size = 1;
10285                 break;
10286         case 2:
10287                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10288                 cfg_size = 1;
10289                 break;
10290         case 3:
10291                 if (bp->link_params.multi_phy_config &
10292                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10293                         bp->port.supported[1] =
10294                                 bp->link_params.phy[EXT_PHY1].supported;
10295                         bp->port.supported[0] =
10296                                 bp->link_params.phy[EXT_PHY2].supported;
10297                 } else {
10298                         bp->port.supported[0] =
10299                                 bp->link_params.phy[EXT_PHY1].supported;
10300                         bp->port.supported[1] =
10301                                 bp->link_params.phy[EXT_PHY2].supported;
10302                 }
10303                 cfg_size = 2;
10304                 break;
10305         }
10306
10307         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10308                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10309                            SHMEM_RD(bp,
10310                            dev_info.port_hw_config[port].external_phy_config),
10311                            SHMEM_RD(bp,
10312                            dev_info.port_hw_config[port].external_phy_config2));
10313                         return;
10314         }
10315
10316         if (CHIP_IS_E3(bp))
10317                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10318         else {
10319                 switch (switch_cfg) {
10320                 case SWITCH_CFG_1G:
10321                         bp->port.phy_addr = REG_RD(
10322                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10323                         break;
10324                 case SWITCH_CFG_10G:
10325                         bp->port.phy_addr = REG_RD(
10326                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10327                         break;
10328                 default:
10329                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10330                                   bp->port.link_config[0]);
10331                         return;
10332                 }
10333         }
10334         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10335         /* mask what we support according to speed_cap_mask per configuration */
10336         for (idx = 0; idx < cfg_size; idx++) {
10337                 if (!(bp->link_params.speed_cap_mask[idx] &
10338                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10339                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10340
10341                 if (!(bp->link_params.speed_cap_mask[idx] &
10342                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10343                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10344
10345                 if (!(bp->link_params.speed_cap_mask[idx] &
10346                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10347                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10348
10349                 if (!(bp->link_params.speed_cap_mask[idx] &
10350                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10351                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10352
10353                 if (!(bp->link_params.speed_cap_mask[idx] &
10354                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10355                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10356                                                      SUPPORTED_1000baseT_Full);
10357
10358                 if (!(bp->link_params.speed_cap_mask[idx] &
10359                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10360                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10361
10362                 if (!(bp->link_params.speed_cap_mask[idx] &
10363                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10364                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10365
10366         }
10367
10368         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10369                        bp->port.supported[1]);
10370 }
10371
10372 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10373 {
10374         u32 link_config, idx, cfg_size = 0;
10375         bp->port.advertising[0] = 0;
10376         bp->port.advertising[1] = 0;
10377         switch (bp->link_params.num_phys) {
10378         case 1:
10379         case 2:
10380                 cfg_size = 1;
10381                 break;
10382         case 3:
10383                 cfg_size = 2;
10384                 break;
10385         }
10386         for (idx = 0; idx < cfg_size; idx++) {
10387                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10388                 link_config = bp->port.link_config[idx];
10389                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10390                 case PORT_FEATURE_LINK_SPEED_AUTO:
10391                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10392                                 bp->link_params.req_line_speed[idx] =
10393                                         SPEED_AUTO_NEG;
10394                                 bp->port.advertising[idx] |=
10395                                         bp->port.supported[idx];
10396                                 if (bp->link_params.phy[EXT_PHY1].type ==
10397                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10398                                         bp->port.advertising[idx] |=
10399                                         (SUPPORTED_100baseT_Half |
10400                                          SUPPORTED_100baseT_Full);
10401                         } else {
10402                                 /* force 10G, no AN */
10403                                 bp->link_params.req_line_speed[idx] =
10404                                         SPEED_10000;
10405                                 bp->port.advertising[idx] |=
10406                                         (ADVERTISED_10000baseT_Full |
10407                                          ADVERTISED_FIBRE);
10408                                 continue;
10409                         }
10410                         break;
10411
10412                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10413                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10414                                 bp->link_params.req_line_speed[idx] =
10415                                         SPEED_10;
10416                                 bp->port.advertising[idx] |=
10417                                         (ADVERTISED_10baseT_Full |
10418                                          ADVERTISED_TP);
10419                         } else {
10420                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10421                                             link_config,
10422                                     bp->link_params.speed_cap_mask[idx]);
10423                                 return;
10424                         }
10425                         break;
10426
10427                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10428                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10429                                 bp->link_params.req_line_speed[idx] =
10430                                         SPEED_10;
10431                                 bp->link_params.req_duplex[idx] =
10432                                         DUPLEX_HALF;
10433                                 bp->port.advertising[idx] |=
10434                                         (ADVERTISED_10baseT_Half |
10435                                          ADVERTISED_TP);
10436                         } else {
10437                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10438                                             link_config,
10439                                           bp->link_params.speed_cap_mask[idx]);
10440                                 return;
10441                         }
10442                         break;
10443
10444                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10445                         if (bp->port.supported[idx] &
10446                             SUPPORTED_100baseT_Full) {
10447                                 bp->link_params.req_line_speed[idx] =
10448                                         SPEED_100;
10449                                 bp->port.advertising[idx] |=
10450                                         (ADVERTISED_100baseT_Full |
10451                                          ADVERTISED_TP);
10452                         } else {
10453                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10454                                             link_config,
10455                                           bp->link_params.speed_cap_mask[idx]);
10456                                 return;
10457                         }
10458                         break;
10459
10460                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10461                         if (bp->port.supported[idx] &
10462                             SUPPORTED_100baseT_Half) {
10463                                 bp->link_params.req_line_speed[idx] =
10464                                                                 SPEED_100;
10465                                 bp->link_params.req_duplex[idx] =
10466                                                                 DUPLEX_HALF;
10467                                 bp->port.advertising[idx] |=
10468                                         (ADVERTISED_100baseT_Half |
10469                                          ADVERTISED_TP);
10470                         } else {
10471                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10472                                     link_config,
10473                                     bp->link_params.speed_cap_mask[idx]);
10474                                 return;
10475                         }
10476                         break;
10477
10478                 case PORT_FEATURE_LINK_SPEED_1G:
10479                         if (bp->port.supported[idx] &
10480                             SUPPORTED_1000baseT_Full) {
10481                                 bp->link_params.req_line_speed[idx] =
10482                                         SPEED_1000;
10483                                 bp->port.advertising[idx] |=
10484                                         (ADVERTISED_1000baseT_Full |
10485                                          ADVERTISED_TP);
10486                         } else {
10487                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10488                                     link_config,
10489                                     bp->link_params.speed_cap_mask[idx]);
10490                                 return;
10491                         }
10492                         break;
10493
10494                 case PORT_FEATURE_LINK_SPEED_2_5G:
10495                         if (bp->port.supported[idx] &
10496                             SUPPORTED_2500baseX_Full) {
10497                                 bp->link_params.req_line_speed[idx] =
10498                                         SPEED_2500;
10499                                 bp->port.advertising[idx] |=
10500                                         (ADVERTISED_2500baseX_Full |
10501                                                 ADVERTISED_TP);
10502                         } else {
10503                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10504                                     link_config,
10505                                     bp->link_params.speed_cap_mask[idx]);
10506                                 return;
10507                         }
10508                         break;
10509
10510                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10511                         if (bp->port.supported[idx] &
10512                             SUPPORTED_10000baseT_Full) {
10513                                 bp->link_params.req_line_speed[idx] =
10514                                         SPEED_10000;
10515                                 bp->port.advertising[idx] |=
10516                                         (ADVERTISED_10000baseT_Full |
10517                                                 ADVERTISED_FIBRE);
10518                         } else {
10519                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10520                                     link_config,
10521                                     bp->link_params.speed_cap_mask[idx]);
10522                                 return;
10523                         }
10524                         break;
10525                 case PORT_FEATURE_LINK_SPEED_20G:
10526                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10527
10528                         break;
10529                 default:
10530                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10531                                   link_config);
10532                                 bp->link_params.req_line_speed[idx] =
10533                                                         SPEED_AUTO_NEG;
10534                                 bp->port.advertising[idx] =
10535                                                 bp->port.supported[idx];
10536                         break;
10537                 }
10538
10539                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10540                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10541                 if (bp->link_params.req_flow_ctrl[idx] ==
10542                     BNX2X_FLOW_CTRL_AUTO) {
10543                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10544                                 bp->link_params.req_flow_ctrl[idx] =
10545                                                         BNX2X_FLOW_CTRL_NONE;
10546                         else
10547                                 bnx2x_set_requested_fc(bp);
10548                 }
10549
10550                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10551                                bp->link_params.req_line_speed[idx],
10552                                bp->link_params.req_duplex[idx],
10553                                bp->link_params.req_flow_ctrl[idx],
10554                                bp->port.advertising[idx]);
10555         }
10556 }
10557
10558 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10559 {
10560         mac_hi = cpu_to_be16(mac_hi);
10561         mac_lo = cpu_to_be32(mac_lo);
10562         memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10563         memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10564 }
10565
10566 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10567 {
10568         int port = BP_PORT(bp);
10569         u32 config;
10570         u32 ext_phy_type, ext_phy_config, eee_mode;
10571
10572         bp->link_params.bp = bp;
10573         bp->link_params.port = port;
10574
10575         bp->link_params.lane_config =
10576                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10577
10578         bp->link_params.speed_cap_mask[0] =
10579                 SHMEM_RD(bp,
10580                          dev_info.port_hw_config[port].speed_capability_mask);
10581         bp->link_params.speed_cap_mask[1] =
10582                 SHMEM_RD(bp,
10583                          dev_info.port_hw_config[port].speed_capability_mask2);
10584         bp->port.link_config[0] =
10585                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10586
10587         bp->port.link_config[1] =
10588                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10589
10590         bp->link_params.multi_phy_config =
10591                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10592         /* If the device is capable of WoL, set the default state according
10593          * to the HW
10594          */
10595         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10596         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10597                    (config & PORT_FEATURE_WOL_ENABLED));
10598
10599         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10600                        bp->link_params.lane_config,
10601                        bp->link_params.speed_cap_mask[0],
10602                        bp->port.link_config[0]);
10603
10604         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10605                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10606         bnx2x_phy_probe(&bp->link_params);
10607         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10608
10609         bnx2x_link_settings_requested(bp);
10610
10611         /*
10612          * If connected directly, work with the internal PHY, otherwise, work
10613          * with the external PHY
10614          */
10615         ext_phy_config =
10616                 SHMEM_RD(bp,
10617                          dev_info.port_hw_config[port].external_phy_config);
10618         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10619         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10620                 bp->mdio.prtad = bp->port.phy_addr;
10621
10622         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10623                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10624                 bp->mdio.prtad =
10625                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10626
10627         /* Configure link feature according to nvram value */
10628         eee_mode = (((SHMEM_RD(bp, dev_info.
10629                       port_feature_config[port].eee_power_mode)) &
10630                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10631                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10632         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10633                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10634                                            EEE_MODE_ENABLE_LPI |
10635                                            EEE_MODE_OUTPUT_TIME;
10636         } else {
10637                 bp->link_params.eee_mode = 0;
10638         }
10639 }
10640
10641 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10642 {
10643         u32 no_flags = NO_ISCSI_FLAG;
10644         int port = BP_PORT(bp);
10645         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10646                                 drv_lic_key[port].max_iscsi_conn);
10647
10648         if (!CNIC_SUPPORT(bp)) {
10649                 bp->flags |= no_flags;
10650                 return;
10651         }
10652
10653         /* Get the number of maximum allowed iSCSI connections */
10654         bp->cnic_eth_dev.max_iscsi_conn =
10655                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10656                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10657
10658         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10659                        bp->cnic_eth_dev.max_iscsi_conn);
10660
10661         /*
10662          * If maximum allowed number of connections is zero -
10663          * disable the feature.
10664          */
10665         if (!bp->cnic_eth_dev.max_iscsi_conn)
10666                 bp->flags |= no_flags;
10667
10668 }
10669
10670 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10671 {
10672         /* Port info */
10673         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10674                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10675         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10676                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10677
10678         /* Node info */
10679         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10680                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10681         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10682                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10683 }
10684 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10685 {
10686         int port = BP_PORT(bp);
10687         int func = BP_ABS_FUNC(bp);
10688         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10689                                 drv_lic_key[port].max_fcoe_conn);
10690
10691         if (!CNIC_SUPPORT(bp)) {
10692                 bp->flags |= NO_FCOE_FLAG;
10693                 return;
10694         }
10695
10696         /* Get the number of maximum allowed FCoE connections */
10697         bp->cnic_eth_dev.max_fcoe_conn =
10698                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10699                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10700
10701         /* Read the WWN: */
10702         if (!IS_MF(bp)) {
10703                 /* Port info */
10704                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10705                         SHMEM_RD(bp,
10706                                 dev_info.port_hw_config[port].
10707                                  fcoe_wwn_port_name_upper);
10708                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10709                         SHMEM_RD(bp,
10710                                 dev_info.port_hw_config[port].
10711                                  fcoe_wwn_port_name_lower);
10712
10713                 /* Node info */
10714                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10715                         SHMEM_RD(bp,
10716                                 dev_info.port_hw_config[port].
10717                                  fcoe_wwn_node_name_upper);
10718                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10719                         SHMEM_RD(bp,
10720                                 dev_info.port_hw_config[port].
10721                                  fcoe_wwn_node_name_lower);
10722         } else if (!IS_MF_SD(bp)) {
10723                 /*
10724                  * Read the WWN info only if the FCoE feature is enabled for
10725                  * this function.
10726                  */
10727                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10728                         bnx2x_get_ext_wwn_info(bp, func);
10729
10730         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10731                 bnx2x_get_ext_wwn_info(bp, func);
10732         }
10733
10734         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10735
10736         /*
10737          * If maximum allowed number of connections is zero -
10738          * disable the feature.
10739          */
10740         if (!bp->cnic_eth_dev.max_fcoe_conn)
10741                 bp->flags |= NO_FCOE_FLAG;
10742 }
10743
10744 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10745 {
10746         /*
10747          * iSCSI may be dynamically disabled but reading
10748          * info here we will decrease memory usage by driver
10749          * if the feature is disabled for good
10750          */
10751         bnx2x_get_iscsi_info(bp);
10752         bnx2x_get_fcoe_info(bp);
10753 }
10754
10755 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10756 {
10757         u32 val, val2;
10758         int func = BP_ABS_FUNC(bp);
10759         int port = BP_PORT(bp);
10760         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10761         u8 *fip_mac = bp->fip_mac;
10762
10763         if (IS_MF(bp)) {
10764                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10765                  * FCoE MAC then the appropriate feature should be disabled.
10766                  * In non SD mode features configuration comes from struct
10767                  * func_ext_config.
10768                  */
10769                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10770                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10771                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10772                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10773                                                  iscsi_mac_addr_upper);
10774                                 val = MF_CFG_RD(bp, func_ext_config[func].
10775                                                 iscsi_mac_addr_lower);
10776                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10777                                 BNX2X_DEV_INFO
10778                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10779                         } else {
10780                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10781                         }
10782
10783                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10784                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10785                                                  fcoe_mac_addr_upper);
10786                                 val = MF_CFG_RD(bp, func_ext_config[func].
10787                                                 fcoe_mac_addr_lower);
10788                                 bnx2x_set_mac_buf(fip_mac, val, val2);
10789                                 BNX2X_DEV_INFO
10790                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
10791                         } else {
10792                                 bp->flags |= NO_FCOE_FLAG;
10793                         }
10794
10795                         bp->mf_ext_config = cfg;
10796
10797                 } else { /* SD MODE */
10798                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10799                                 /* use primary mac as iscsi mac */
10800                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10801
10802                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10803                                 BNX2X_DEV_INFO
10804                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10805                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10806                                 /* use primary mac as fip mac */
10807                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10808                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
10809                                 BNX2X_DEV_INFO
10810                                         ("Read FIP MAC: %pM\n", fip_mac);
10811                         }
10812                 }
10813
10814                 if (IS_MF_STORAGE_SD(bp))
10815                         /* Zero primary MAC configuration */
10816                         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10817
10818                 if (IS_MF_FCOE_AFEX(bp))
10819                         /* use FIP MAC as primary MAC */
10820                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10821
10822         } else {
10823                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10824                                 iscsi_mac_upper);
10825                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10826                                iscsi_mac_lower);
10827                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10828
10829                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10830                                 fcoe_fip_mac_upper);
10831                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10832                                fcoe_fip_mac_lower);
10833                 bnx2x_set_mac_buf(fip_mac, val, val2);
10834         }
10835
10836         /* Disable iSCSI OOO if MAC configuration is invalid. */
10837         if (!is_valid_ether_addr(iscsi_mac)) {
10838                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10839                 memset(iscsi_mac, 0, ETH_ALEN);
10840         }
10841
10842         /* Disable FCoE if MAC configuration is invalid. */
10843         if (!is_valid_ether_addr(fip_mac)) {
10844                 bp->flags |= NO_FCOE_FLAG;
10845                 memset(bp->fip_mac, 0, ETH_ALEN);
10846         }
10847 }
10848
10849 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10850 {
10851         u32 val, val2;
10852         int func = BP_ABS_FUNC(bp);
10853         int port = BP_PORT(bp);
10854
10855         /* Zero primary MAC configuration */
10856         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10857
10858         if (BP_NOMCP(bp)) {
10859                 BNX2X_ERROR("warning: random MAC workaround active\n");
10860                 eth_hw_addr_random(bp->dev);
10861         } else if (IS_MF(bp)) {
10862                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10863                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10864                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10865                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10866                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10867
10868                 if (CNIC_SUPPORT(bp))
10869                         bnx2x_get_cnic_mac_hwinfo(bp);
10870         } else {
10871                 /* in SF read MACs from port configuration */
10872                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10873                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10874                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10875
10876                 if (CNIC_SUPPORT(bp))
10877                         bnx2x_get_cnic_mac_hwinfo(bp);
10878         }
10879
10880         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10881         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10882
10883         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10884                 dev_err(&bp->pdev->dev,
10885                         "bad Ethernet MAC address configuration: %pM\n"
10886                         "change it manually before bringing up the appropriate network interface\n",
10887                         bp->dev->dev_addr);
10888 }
10889
10890 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10891 {
10892         int tmp;
10893         u32 cfg;
10894
10895         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10896                 /* Take function: tmp = func */
10897                 tmp = BP_ABS_FUNC(bp);
10898                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10899                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10900         } else {
10901                 /* Take port: tmp = port */
10902                 tmp = BP_PORT(bp);
10903                 cfg = SHMEM_RD(bp,
10904                                dev_info.port_hw_config[tmp].generic_features);
10905                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10906         }
10907         return cfg;
10908 }
10909
10910 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10911 {
10912         int /*abs*/func = BP_ABS_FUNC(bp);
10913         int vn;
10914         u32 val = 0;
10915         int rc = 0;
10916
10917         bnx2x_get_common_hwinfo(bp);
10918
10919         /*
10920          * initialize IGU parameters
10921          */
10922         if (CHIP_IS_E1x(bp)) {
10923                 bp->common.int_block = INT_BLOCK_HC;
10924
10925                 bp->igu_dsb_id = DEF_SB_IGU_ID;
10926                 bp->igu_base_sb = 0;
10927         } else {
10928                 bp->common.int_block = INT_BLOCK_IGU;
10929
10930                 /* do not allow device reset during IGU info preocessing */
10931                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10932
10933                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10934
10935                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10936                         int tout = 5000;
10937
10938                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
10939
10940                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10941                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10942                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10943
10944                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10945                                 tout--;
10946                                 usleep_range(1000, 1000);
10947                         }
10948
10949                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10950                                 dev_err(&bp->pdev->dev,
10951                                         "FORCING Normal Mode failed!!!\n");
10952                                 bnx2x_release_hw_lock(bp,
10953                                                       HW_LOCK_RESOURCE_RESET);
10954                                 return -EPERM;
10955                         }
10956                 }
10957
10958                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10959                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10960                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10961                 } else
10962                         BNX2X_DEV_INFO("IGU Normal Mode\n");
10963
10964                 rc = bnx2x_get_igu_cam_info(bp);
10965                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10966                 if (rc)
10967                         return rc;
10968         }
10969
10970         /*
10971          * set base FW non-default (fast path) status block id, this value is
10972          * used to initialize the fw_sb_id saved on the fp/queue structure to
10973          * determine the id used by the FW.
10974          */
10975         if (CHIP_IS_E1x(bp))
10976                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10977         else /*
10978               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10979               * the same queue are indicated on the same IGU SB). So we prefer
10980               * FW and IGU SBs to be the same value.
10981               */
10982                 bp->base_fw_ndsb = bp->igu_base_sb;
10983
10984         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
10985                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10986                        bp->igu_sb_cnt, bp->base_fw_ndsb);
10987
10988         /*
10989          * Initialize MF configuration
10990          */
10991
10992         bp->mf_ov = 0;
10993         bp->mf_mode = 0;
10994         vn = BP_VN(bp);
10995
10996         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10997                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10998                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
10999                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11000
11001                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11002                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11003                 else
11004                         bp->common.mf_cfg_base = bp->common.shmem_base +
11005                                 offsetof(struct shmem_region, func_mb) +
11006                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11007                 /*
11008                  * get mf configuration:
11009                  * 1. existence of MF configuration
11010                  * 2. MAC address must be legal (check only upper bytes)
11011                  *    for  Switch-Independent mode;
11012                  *    OVLAN must be legal for Switch-Dependent mode
11013                  * 3. SF_MODE configures specific MF mode
11014                  */
11015                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11016                         /* get mf configuration */
11017                         val = SHMEM_RD(bp,
11018                                        dev_info.shared_feature_config.config);
11019                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11020
11021                         switch (val) {
11022                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11023                                 val = MF_CFG_RD(bp, func_mf_config[func].
11024                                                 mac_upper);
11025                                 /* check for legal mac (upper bytes)*/
11026                                 if (val != 0xffff) {
11027                                         bp->mf_mode = MULTI_FUNCTION_SI;
11028                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11029                                                    func_mf_config[func].config);
11030                                 } else
11031                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11032                                 break;
11033                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11034                                 if ((!CHIP_IS_E1x(bp)) &&
11035                                     (MF_CFG_RD(bp, func_mf_config[func].
11036                                                mac_upper) != 0xffff) &&
11037                                     (SHMEM2_HAS(bp,
11038                                                 afex_driver_support))) {
11039                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11040                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11041                                                 func_mf_config[func].config);
11042                                 } else {
11043                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11044                                 }
11045                                 break;
11046                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11047                                 /* get OV configuration */
11048                                 val = MF_CFG_RD(bp,
11049                                         func_mf_config[FUNC_0].e1hov_tag);
11050                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11051
11052                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11053                                         bp->mf_mode = MULTI_FUNCTION_SD;
11054                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11055                                                 func_mf_config[func].config);
11056                                 } else
11057                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11058                                 break;
11059                         default:
11060                                 /* Unknown configuration: reset mf_config */
11061                                 bp->mf_config[vn] = 0;
11062                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11063                         }
11064                 }
11065
11066                 BNX2X_DEV_INFO("%s function mode\n",
11067                                IS_MF(bp) ? "multi" : "single");
11068
11069                 switch (bp->mf_mode) {
11070                 case MULTI_FUNCTION_SD:
11071                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11072                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11073                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11074                                 bp->mf_ov = val;
11075                                 bp->path_has_ovlan = true;
11076
11077                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11078                                                func, bp->mf_ov, bp->mf_ov);
11079                         } else {
11080                                 dev_err(&bp->pdev->dev,
11081                                         "No valid MF OV for func %d, aborting\n",
11082                                         func);
11083                                 return -EPERM;
11084                         }
11085                         break;
11086                 case MULTI_FUNCTION_AFEX:
11087                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11088                         break;
11089                 case MULTI_FUNCTION_SI:
11090                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11091                                        func);
11092                         break;
11093                 default:
11094                         if (vn) {
11095                                 dev_err(&bp->pdev->dev,
11096                                         "VN %d is in a single function mode, aborting\n",
11097                                         vn);
11098                                 return -EPERM;
11099                         }
11100                         break;
11101                 }
11102
11103                 /* check if other port on the path needs ovlan:
11104                  * Since MF configuration is shared between ports
11105                  * Possible mixed modes are only
11106                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11107                  */
11108                 if (CHIP_MODE_IS_4_PORT(bp) &&
11109                     !bp->path_has_ovlan &&
11110                     !IS_MF(bp) &&
11111                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11112                         u8 other_port = !BP_PORT(bp);
11113                         u8 other_func = BP_PATH(bp) + 2*other_port;
11114                         val = MF_CFG_RD(bp,
11115                                         func_mf_config[other_func].e1hov_tag);
11116                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11117                                 bp->path_has_ovlan = true;
11118                 }
11119         }
11120
11121         /* adjust igu_sb_cnt to MF for E1x */
11122         if (CHIP_IS_E1x(bp) && IS_MF(bp))
11123                 bp->igu_sb_cnt /= E1HVN_MAX;
11124
11125         /* port info */
11126         bnx2x_get_port_hwinfo(bp);
11127
11128         /* Get MAC addresses */
11129         bnx2x_get_mac_hwinfo(bp);
11130
11131         bnx2x_get_cnic_info(bp);
11132
11133         return rc;
11134 }
11135
11136 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11137 {
11138         int cnt, i, block_end, rodi;
11139         char vpd_start[BNX2X_VPD_LEN+1];
11140         char str_id_reg[VENDOR_ID_LEN+1];
11141         char str_id_cap[VENDOR_ID_LEN+1];
11142         char *vpd_data;
11143         char *vpd_extended_data = NULL;
11144         u8 len;
11145
11146         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11147         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11148
11149         if (cnt < BNX2X_VPD_LEN)
11150                 goto out_not_found;
11151
11152         /* VPD RO tag should be first tag after identifier string, hence
11153          * we should be able to find it in first BNX2X_VPD_LEN chars
11154          */
11155         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11156                              PCI_VPD_LRDT_RO_DATA);
11157         if (i < 0)
11158                 goto out_not_found;
11159
11160         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11161                     pci_vpd_lrdt_size(&vpd_start[i]);
11162
11163         i += PCI_VPD_LRDT_TAG_SIZE;
11164
11165         if (block_end > BNX2X_VPD_LEN) {
11166                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11167                 if (vpd_extended_data  == NULL)
11168                         goto out_not_found;
11169
11170                 /* read rest of vpd image into vpd_extended_data */
11171                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11172                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11173                                    block_end - BNX2X_VPD_LEN,
11174                                    vpd_extended_data + BNX2X_VPD_LEN);
11175                 if (cnt < (block_end - BNX2X_VPD_LEN))
11176                         goto out_not_found;
11177                 vpd_data = vpd_extended_data;
11178         } else
11179                 vpd_data = vpd_start;
11180
11181         /* now vpd_data holds full vpd content in both cases */
11182
11183         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11184                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11185         if (rodi < 0)
11186                 goto out_not_found;
11187
11188         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11189
11190         if (len != VENDOR_ID_LEN)
11191                 goto out_not_found;
11192
11193         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11194
11195         /* vendor specific info */
11196         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11197         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11198         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11199             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11200
11201                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11202                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11203                 if (rodi >= 0) {
11204                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11205
11206                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11207
11208                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11209                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11210                                 bp->fw_ver[len] = ' ';
11211                         }
11212                 }
11213                 kfree(vpd_extended_data);
11214                 return;
11215         }
11216 out_not_found:
11217         kfree(vpd_extended_data);
11218         return;
11219 }
11220
11221 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11222 {
11223         u32 flags = 0;
11224
11225         if (CHIP_REV_IS_FPGA(bp))
11226                 SET_FLAGS(flags, MODE_FPGA);
11227         else if (CHIP_REV_IS_EMUL(bp))
11228                 SET_FLAGS(flags, MODE_EMUL);
11229         else
11230                 SET_FLAGS(flags, MODE_ASIC);
11231
11232         if (CHIP_MODE_IS_4_PORT(bp))
11233                 SET_FLAGS(flags, MODE_PORT4);
11234         else
11235                 SET_FLAGS(flags, MODE_PORT2);
11236
11237         if (CHIP_IS_E2(bp))
11238                 SET_FLAGS(flags, MODE_E2);
11239         else if (CHIP_IS_E3(bp)) {
11240                 SET_FLAGS(flags, MODE_E3);
11241                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11242                         SET_FLAGS(flags, MODE_E3_A0);
11243                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11244                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11245         }
11246
11247         if (IS_MF(bp)) {
11248                 SET_FLAGS(flags, MODE_MF);
11249                 switch (bp->mf_mode) {
11250                 case MULTI_FUNCTION_SD:
11251                         SET_FLAGS(flags, MODE_MF_SD);
11252                         break;
11253                 case MULTI_FUNCTION_SI:
11254                         SET_FLAGS(flags, MODE_MF_SI);
11255                         break;
11256                 case MULTI_FUNCTION_AFEX:
11257                         SET_FLAGS(flags, MODE_MF_AFEX);
11258                         break;
11259                 }
11260         } else
11261                 SET_FLAGS(flags, MODE_SF);
11262
11263 #if defined(__LITTLE_ENDIAN)
11264         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11265 #else /*(__BIG_ENDIAN)*/
11266         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11267 #endif
11268         INIT_MODE_FLAGS(bp) = flags;
11269 }
11270
11271 static int bnx2x_init_bp(struct bnx2x *bp)
11272 {
11273         int func;
11274         int rc;
11275
11276         mutex_init(&bp->port.phy_mutex);
11277         mutex_init(&bp->fw_mb_mutex);
11278         spin_lock_init(&bp->stats_lock);
11279
11280
11281         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11282         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11283         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11284         if (IS_PF(bp)) {
11285                 rc = bnx2x_get_hwinfo(bp);
11286                 if (rc)
11287                         return rc;
11288         } else {
11289                 random_ether_addr(bp->dev->dev_addr);
11290         }
11291
11292         bnx2x_set_modes_bitmap(bp);
11293
11294         rc = bnx2x_alloc_mem_bp(bp);
11295         if (rc)
11296                 return rc;
11297
11298         bnx2x_read_fwinfo(bp);
11299
11300         func = BP_FUNC(bp);
11301
11302         /* need to reset chip if undi was active */
11303         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11304                 /* init fw_seq */
11305                 bp->fw_seq =
11306                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11307                                                         DRV_MSG_SEQ_NUMBER_MASK;
11308                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11309
11310                 bnx2x_prev_unload(bp);
11311         }
11312
11313
11314         if (CHIP_REV_IS_FPGA(bp))
11315                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11316
11317         if (BP_NOMCP(bp) && (func == 0))
11318                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11319
11320         bp->disable_tpa = disable_tpa;
11321         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11322
11323         /* Set TPA flags */
11324         if (bp->disable_tpa) {
11325                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11326                 bp->dev->features &= ~NETIF_F_LRO;
11327         } else {
11328                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11329                 bp->dev->features |= NETIF_F_LRO;
11330         }
11331
11332         if (CHIP_IS_E1(bp))
11333                 bp->dropless_fc = 0;
11334         else
11335                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11336
11337         bp->mrrs = mrrs;
11338
11339         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11340         if (IS_VF(bp))
11341                 bp->rx_ring_size = MAX_RX_AVAIL;
11342
11343         /* make sure that the numbers are in the right granularity */
11344         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11345         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11346
11347         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11348
11349         init_timer(&bp->timer);
11350         bp->timer.expires = jiffies + bp->current_interval;
11351         bp->timer.data = (unsigned long) bp;
11352         bp->timer.function = bnx2x_timer;
11353
11354         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11355             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11356             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11357             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11358                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11359                 bnx2x_dcbx_init_params(bp);
11360         } else {
11361                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11362         }
11363
11364         if (CHIP_IS_E1x(bp))
11365                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11366         else
11367                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11368
11369         /* multiple tx priority */
11370         if (IS_VF(bp))
11371                 bp->max_cos = 1;
11372         else if (CHIP_IS_E1x(bp))
11373                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11374         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11375                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11376         else if (CHIP_IS_E3B0(bp))
11377                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11378         else
11379                 BNX2X_ERR("unknown chip %x revision %x\n",
11380                           CHIP_NUM(bp), CHIP_REV(bp));
11381         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11382
11383         /* We need at least one default status block for slow-path events,
11384          * second status block for the L2 queue, and a third status block for
11385          * CNIC if supproted.
11386          */
11387         if (CNIC_SUPPORT(bp))
11388                 bp->min_msix_vec_cnt = 3;
11389         else
11390                 bp->min_msix_vec_cnt = 2;
11391         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11392
11393         return rc;
11394 }
11395
11396
11397 /****************************************************************************
11398 * General service functions
11399 ****************************************************************************/
11400
11401 /*
11402  * net_device service functions
11403  */
11404
11405 static int bnx2x_open_epilog(struct bnx2x *bp)
11406 {
11407         /* Enable sriov via delayed work. This must be done via delayed work
11408          * because it causes the probe of the vf devices to be run, which invoke
11409          * register_netdevice which must have rtnl lock taken. As we are holding
11410          * the lock right now, that could only work if the probe would not take
11411          * the lock. However, as the probe of the vf may be called from other
11412          * contexts as well (such as passthrough to vm failes) it can't assume
11413          * the lock is being held for it. Using delayed work here allows the
11414          * probe code to simply take the lock (i.e. wait for it to be released
11415          * if it is being held).
11416          */
11417         smp_mb__before_clear_bit();
11418         set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, &bp->sp_rtnl_state);
11419         smp_mb__after_clear_bit();
11420         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11421
11422         return 0;
11423 }
11424
11425 /* called with rtnl_lock */
11426 static int bnx2x_open(struct net_device *dev)
11427 {
11428         struct bnx2x *bp = netdev_priv(dev);
11429         bool global = false;
11430         int other_engine = BP_PATH(bp) ? 0 : 1;
11431         bool other_load_status, load_status;
11432         int rc;
11433
11434         bp->stats_init = true;
11435
11436         netif_carrier_off(dev);
11437
11438         bnx2x_set_power_state(bp, PCI_D0);
11439
11440         /* If parity had happen during the unload, then attentions
11441          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11442          * want the first function loaded on the current engine to
11443          * complete the recovery.
11444          * Parity recovery is only relevant for PF driver.
11445          */
11446         if (IS_PF(bp)) {
11447                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11448                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11449                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11450                     bnx2x_chk_parity_attn(bp, &global, true)) {
11451                         do {
11452                                 /* If there are attentions and they are in a
11453                                  * global blocks, set the GLOBAL_RESET bit
11454                                  * regardless whether it will be this function
11455                                  * that will complete the recovery or not.
11456                                  */
11457                                 if (global)
11458                                         bnx2x_set_reset_global(bp);
11459
11460                                 /* Only the first function on the current
11461                                  * engine should try to recover in open. In case
11462                                  * of attentions in global blocks only the first
11463                                  * in the chip should try to recover.
11464                                  */
11465                                 if ((!load_status &&
11466                                      (!global || !other_load_status)) &&
11467                                       bnx2x_trylock_leader_lock(bp) &&
11468                                       !bnx2x_leader_reset(bp)) {
11469                                         netdev_info(bp->dev,
11470                                                     "Recovered in open\n");
11471                                         break;
11472                                 }
11473
11474                                 /* recovery has failed... */
11475                                 bnx2x_set_power_state(bp, PCI_D3hot);
11476                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11477
11478                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11479                                           "If you still see this message after a few retries then power cycle is required.\n");
11480
11481                                 return -EAGAIN;
11482                         } while (0);
11483                 }
11484         }
11485
11486         bp->recovery_state = BNX2X_RECOVERY_DONE;
11487         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11488         if (rc)
11489                 return rc;
11490         return bnx2x_open_epilog(bp);
11491 }
11492
11493 /* called with rtnl_lock */
11494 static int bnx2x_close(struct net_device *dev)
11495 {
11496         struct bnx2x *bp = netdev_priv(dev);
11497
11498         /* Unload the driver, release IRQs */
11499         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11500
11501         /* Power off */
11502         bnx2x_set_power_state(bp, PCI_D3hot);
11503
11504         return 0;
11505 }
11506
11507 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11508                                       struct bnx2x_mcast_ramrod_params *p)
11509 {
11510         int mc_count = netdev_mc_count(bp->dev);
11511         struct bnx2x_mcast_list_elem *mc_mac =
11512                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11513         struct netdev_hw_addr *ha;
11514
11515         if (!mc_mac)
11516                 return -ENOMEM;
11517
11518         INIT_LIST_HEAD(&p->mcast_list);
11519
11520         netdev_for_each_mc_addr(ha, bp->dev) {
11521                 mc_mac->mac = bnx2x_mc_addr(ha);
11522                 list_add_tail(&mc_mac->link, &p->mcast_list);
11523                 mc_mac++;
11524         }
11525
11526         p->mcast_list_len = mc_count;
11527
11528         return 0;
11529 }
11530
11531 static void bnx2x_free_mcast_macs_list(
11532         struct bnx2x_mcast_ramrod_params *p)
11533 {
11534         struct bnx2x_mcast_list_elem *mc_mac =
11535                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11536                                  link);
11537
11538         WARN_ON(!mc_mac);
11539         kfree(mc_mac);
11540 }
11541
11542 /**
11543  * bnx2x_set_uc_list - configure a new unicast MACs list.
11544  *
11545  * @bp: driver handle
11546  *
11547  * We will use zero (0) as a MAC type for these MACs.
11548  */
11549 static int bnx2x_set_uc_list(struct bnx2x *bp)
11550 {
11551         int rc;
11552         struct net_device *dev = bp->dev;
11553         struct netdev_hw_addr *ha;
11554         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11555         unsigned long ramrod_flags = 0;
11556
11557         /* First schedule a cleanup up of old configuration */
11558         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11559         if (rc < 0) {
11560                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11561                 return rc;
11562         }
11563
11564         netdev_for_each_uc_addr(ha, dev) {
11565                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11566                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11567                 if (rc == -EEXIST) {
11568                         DP(BNX2X_MSG_SP,
11569                            "Failed to schedule ADD operations: %d\n", rc);
11570                         /* do not treat adding same MAC as error */
11571                         rc = 0;
11572
11573                 } else if (rc < 0) {
11574
11575                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11576                                   rc);
11577                         return rc;
11578                 }
11579         }
11580
11581         /* Execute the pending commands */
11582         __set_bit(RAMROD_CONT, &ramrod_flags);
11583         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11584                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11585 }
11586
11587 static int bnx2x_set_mc_list(struct bnx2x *bp)
11588 {
11589         struct net_device *dev = bp->dev;
11590         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11591         int rc = 0;
11592
11593         rparam.mcast_obj = &bp->mcast_obj;
11594
11595         /* first, clear all configured multicast MACs */
11596         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11597         if (rc < 0) {
11598                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11599                 return rc;
11600         }
11601
11602         /* then, configure a new MACs list */
11603         if (netdev_mc_count(dev)) {
11604                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11605                 if (rc) {
11606                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11607                                   rc);
11608                         return rc;
11609                 }
11610
11611                 /* Now add the new MACs */
11612                 rc = bnx2x_config_mcast(bp, &rparam,
11613                                         BNX2X_MCAST_CMD_ADD);
11614                 if (rc < 0)
11615                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11616                                   rc);
11617
11618                 bnx2x_free_mcast_macs_list(&rparam);
11619         }
11620
11621         return rc;
11622 }
11623
11624
11625 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11626 void bnx2x_set_rx_mode(struct net_device *dev)
11627 {
11628         struct bnx2x *bp = netdev_priv(dev);
11629         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11630
11631         if (bp->state != BNX2X_STATE_OPEN) {
11632                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11633                 return;
11634         }
11635
11636         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11637
11638         if (dev->flags & IFF_PROMISC)
11639                 rx_mode = BNX2X_RX_MODE_PROMISC;
11640         else if ((dev->flags & IFF_ALLMULTI) ||
11641                  ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11642                   CHIP_IS_E1(bp)))
11643                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11644         else {
11645                 if (IS_PF(bp)) {
11646                         /* some multicasts */
11647                         if (bnx2x_set_mc_list(bp) < 0)
11648                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11649
11650                         if (bnx2x_set_uc_list(bp) < 0)
11651                                 rx_mode = BNX2X_RX_MODE_PROMISC;
11652                 } else {
11653                         /* configuring mcast to a vf involves sleeping (when we
11654                          * wait for the pf's response). Since this function is
11655                          * called from non sleepable context we must schedule
11656                          * a work item for this purpose
11657                          */
11658                         smp_mb__before_clear_bit();
11659                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11660                                 &bp->sp_rtnl_state);
11661                         smp_mb__after_clear_bit();
11662                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11663                 }
11664         }
11665
11666         bp->rx_mode = rx_mode;
11667         /* handle ISCSI SD mode */
11668         if (IS_MF_ISCSI_SD(bp))
11669                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11670
11671         /* Schedule the rx_mode command */
11672         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11673                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11674                 return;
11675         }
11676
11677         if (IS_PF(bp)) {
11678                 bnx2x_set_storm_rx_mode(bp);
11679         } else {
11680                 /* configuring rx mode to storms in a vf involves sleeping (when
11681                  * we wait for the pf's response). Since this function is
11682                  * called from non sleepable context we must schedule
11683                  * a work item for this purpose
11684                  */
11685                 smp_mb__before_clear_bit();
11686                 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11687                         &bp->sp_rtnl_state);
11688                 smp_mb__after_clear_bit();
11689                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11690         }
11691 }
11692
11693 /* called with rtnl_lock */
11694 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11695                            int devad, u16 addr)
11696 {
11697         struct bnx2x *bp = netdev_priv(netdev);
11698         u16 value;
11699         int rc;
11700
11701         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11702            prtad, devad, addr);
11703
11704         /* The HW expects different devad if CL22 is used */
11705         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11706
11707         bnx2x_acquire_phy_lock(bp);
11708         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11709         bnx2x_release_phy_lock(bp);
11710         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11711
11712         if (!rc)
11713                 rc = value;
11714         return rc;
11715 }
11716
11717 /* called with rtnl_lock */
11718 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11719                             u16 addr, u16 value)
11720 {
11721         struct bnx2x *bp = netdev_priv(netdev);
11722         int rc;
11723
11724         DP(NETIF_MSG_LINK,
11725            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11726            prtad, devad, addr, value);
11727
11728         /* The HW expects different devad if CL22 is used */
11729         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11730
11731         bnx2x_acquire_phy_lock(bp);
11732         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11733         bnx2x_release_phy_lock(bp);
11734         return rc;
11735 }
11736
11737 /* called with rtnl_lock */
11738 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11739 {
11740         struct bnx2x *bp = netdev_priv(dev);
11741         struct mii_ioctl_data *mdio = if_mii(ifr);
11742
11743         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11744            mdio->phy_id, mdio->reg_num, mdio->val_in);
11745
11746         if (!netif_running(dev))
11747                 return -EAGAIN;
11748
11749         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11750 }
11751
11752 #ifdef CONFIG_NET_POLL_CONTROLLER
11753 static void poll_bnx2x(struct net_device *dev)
11754 {
11755         struct bnx2x *bp = netdev_priv(dev);
11756         int i;
11757
11758         for_each_eth_queue(bp, i) {
11759                 struct bnx2x_fastpath *fp = &bp->fp[i];
11760                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11761         }
11762 }
11763 #endif
11764
11765 static int bnx2x_validate_addr(struct net_device *dev)
11766 {
11767         struct bnx2x *bp = netdev_priv(dev);
11768
11769         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11770                 BNX2X_ERR("Non-valid Ethernet address\n");
11771                 return -EADDRNOTAVAIL;
11772         }
11773         return 0;
11774 }
11775
11776 static const struct net_device_ops bnx2x_netdev_ops = {
11777         .ndo_open               = bnx2x_open,
11778         .ndo_stop               = bnx2x_close,
11779         .ndo_start_xmit         = bnx2x_start_xmit,
11780         .ndo_select_queue       = bnx2x_select_queue,
11781         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
11782         .ndo_set_mac_address    = bnx2x_change_mac_addr,
11783         .ndo_validate_addr      = bnx2x_validate_addr,
11784         .ndo_do_ioctl           = bnx2x_ioctl,
11785         .ndo_change_mtu         = bnx2x_change_mtu,
11786         .ndo_fix_features       = bnx2x_fix_features,
11787         .ndo_set_features       = bnx2x_set_features,
11788         .ndo_tx_timeout         = bnx2x_tx_timeout,
11789 #ifdef CONFIG_NET_POLL_CONTROLLER
11790         .ndo_poll_controller    = poll_bnx2x,
11791 #endif
11792         .ndo_setup_tc           = bnx2x_setup_tc,
11793         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
11794 #ifdef NETDEV_FCOE_WWNN
11795         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
11796 #endif
11797 };
11798
11799 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11800 {
11801         struct device *dev = &bp->pdev->dev;
11802
11803         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11804                 bp->flags |= USING_DAC_FLAG;
11805                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11806                         dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11807                         return -EIO;
11808                 }
11809         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11810                 dev_err(dev, "System does not support DMA, aborting\n");
11811                 return -EIO;
11812         }
11813
11814         return 0;
11815 }
11816
11817 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11818                           struct net_device *dev, unsigned long board_type)
11819 {
11820         int rc;
11821         u32 pci_cfg_dword;
11822         bool chip_is_e1x = (board_type == BCM57710 ||
11823                             board_type == BCM57711 ||
11824                             board_type == BCM57711E);
11825
11826         SET_NETDEV_DEV(dev, &pdev->dev);
11827
11828         bp->dev = dev;
11829         bp->pdev = pdev;
11830
11831         rc = pci_enable_device(pdev);
11832         if (rc) {
11833                 dev_err(&bp->pdev->dev,
11834                         "Cannot enable PCI device, aborting\n");
11835                 goto err_out;
11836         }
11837
11838         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11839                 dev_err(&bp->pdev->dev,
11840                         "Cannot find PCI device base address, aborting\n");
11841                 rc = -ENODEV;
11842                 goto err_out_disable;
11843         }
11844
11845         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11846                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
11847                 rc = -ENODEV;
11848                 goto err_out_disable;
11849         }
11850
11851         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11852         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11853             PCICFG_REVESION_ID_ERROR_VAL) {
11854                 pr_err("PCI device error, probably due to fan failure, aborting\n");
11855                 rc = -ENODEV;
11856                 goto err_out_disable;
11857         }
11858
11859         if (atomic_read(&pdev->enable_cnt) == 1) {
11860                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11861                 if (rc) {
11862                         dev_err(&bp->pdev->dev,
11863                                 "Cannot obtain PCI resources, aborting\n");
11864                         goto err_out_disable;
11865                 }
11866
11867                 pci_set_master(pdev);
11868                 pci_save_state(pdev);
11869         }
11870
11871         if (IS_PF(bp)) {
11872                 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11873                 if (bp->pm_cap == 0) {
11874                         dev_err(&bp->pdev->dev,
11875                                 "Cannot find power management capability, aborting\n");
11876                         rc = -EIO;
11877                         goto err_out_release;
11878                 }
11879         }
11880
11881         if (!pci_is_pcie(pdev)) {
11882                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11883                 rc = -EIO;
11884                 goto err_out_release;
11885         }
11886
11887         rc = bnx2x_set_coherency_mask(bp);
11888         if (rc)
11889                 goto err_out_release;
11890
11891         dev->mem_start = pci_resource_start(pdev, 0);
11892         dev->base_addr = dev->mem_start;
11893         dev->mem_end = pci_resource_end(pdev, 0);
11894
11895         dev->irq = pdev->irq;
11896
11897         bp->regview = pci_ioremap_bar(pdev, 0);
11898         if (!bp->regview) {
11899                 dev_err(&bp->pdev->dev,
11900                         "Cannot map register space, aborting\n");
11901                 rc = -ENOMEM;
11902                 goto err_out_release;
11903         }
11904
11905         /* In E1/E1H use pci device function given by kernel.
11906          * In E2/E3 read physical function from ME register since these chips
11907          * support Physical Device Assignment where kernel BDF maybe arbitrary
11908          * (depending on hypervisor).
11909          */
11910         if (chip_is_e1x)
11911                 bp->pf_num = PCI_FUNC(pdev->devfn);
11912         else {/* chip is E2/3*/
11913                 pci_read_config_dword(bp->pdev,
11914                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
11915                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11916                     ME_REG_ABS_PF_NUM_SHIFT);
11917         }
11918         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11919
11920         bnx2x_set_power_state(bp, PCI_D0);
11921
11922         /* clean indirect addresses */
11923         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11924                                PCICFG_VENDOR_ID_OFFSET);
11925         /*
11926          * Clean the following indirect addresses for all functions since it
11927          * is not used by the driver.
11928          */
11929         if (IS_PF(bp)) {
11930                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11931                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11932                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11933                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11934
11935                 if (chip_is_e1x) {
11936                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11937                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11938                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11939                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11940                 }
11941
11942                 /* Enable internal target-read (in case we are probed after PF
11943                  * FLR). Must be done prior to any BAR read access. Only for
11944                  * 57712 and up
11945                  */
11946                 if (!chip_is_e1x)
11947                         REG_WR(bp,
11948                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11949         }
11950
11951         dev->watchdog_timeo = TX_TIMEOUT;
11952
11953         dev->netdev_ops = &bnx2x_netdev_ops;
11954         bnx2x_set_ethtool_ops(dev);
11955
11956         dev->priv_flags |= IFF_UNICAST_FLT;
11957
11958         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11959                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11960                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11961                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11962
11963         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11964                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11965
11966         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11967         if (bp->flags & USING_DAC_FLAG)
11968                 dev->features |= NETIF_F_HIGHDMA;
11969
11970         /* Add Loopback capability to the device */
11971         dev->hw_features |= NETIF_F_LOOPBACK;
11972
11973 #ifdef BCM_DCBNL
11974         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11975 #endif
11976
11977         /* get_port_hwinfo() will set prtad and mmds properly */
11978         bp->mdio.prtad = MDIO_PRTAD_NONE;
11979         bp->mdio.mmds = 0;
11980         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11981         bp->mdio.dev = dev;
11982         bp->mdio.mdio_read = bnx2x_mdio_read;
11983         bp->mdio.mdio_write = bnx2x_mdio_write;
11984
11985         return 0;
11986
11987 err_out_release:
11988         if (atomic_read(&pdev->enable_cnt) == 1)
11989                 pci_release_regions(pdev);
11990
11991 err_out_disable:
11992         pci_disable_device(pdev);
11993         pci_set_drvdata(pdev, NULL);
11994
11995 err_out:
11996         return rc;
11997 }
11998
11999 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
12000 {
12001         u32 val = 0;
12002
12003         pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12004         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12005
12006         /* return value of 1=2.5GHz 2=5GHz */
12007         *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12008 }
12009
12010 static int bnx2x_check_firmware(struct bnx2x *bp)
12011 {
12012         const struct firmware *firmware = bp->firmware;
12013         struct bnx2x_fw_file_hdr *fw_hdr;
12014         struct bnx2x_fw_file_section *sections;
12015         u32 offset, len, num_ops;
12016         u16 *ops_offsets;
12017         int i;
12018         const u8 *fw_ver;
12019
12020         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12021                 BNX2X_ERR("Wrong FW size\n");
12022                 return -EINVAL;
12023         }
12024
12025         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12026         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12027
12028         /* Make sure none of the offsets and sizes make us read beyond
12029          * the end of the firmware data */
12030         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12031                 offset = be32_to_cpu(sections[i].offset);
12032                 len = be32_to_cpu(sections[i].len);
12033                 if (offset + len > firmware->size) {
12034                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12035                         return -EINVAL;
12036                 }
12037         }
12038
12039         /* Likewise for the init_ops offsets */
12040         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12041         ops_offsets = (u16 *)(firmware->data + offset);
12042         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12043
12044         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12045                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12046                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12047                         return -EINVAL;
12048                 }
12049         }
12050
12051         /* Check FW version */
12052         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12053         fw_ver = firmware->data + offset;
12054         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12055             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12056             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12057             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12058                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12059                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12060                        BCM_5710_FW_MAJOR_VERSION,
12061                        BCM_5710_FW_MINOR_VERSION,
12062                        BCM_5710_FW_REVISION_VERSION,
12063                        BCM_5710_FW_ENGINEERING_VERSION);
12064                 return -EINVAL;
12065         }
12066
12067         return 0;
12068 }
12069
12070 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12071 {
12072         const __be32 *source = (const __be32 *)_source;
12073         u32 *target = (u32 *)_target;
12074         u32 i;
12075
12076         for (i = 0; i < n/4; i++)
12077                 target[i] = be32_to_cpu(source[i]);
12078 }
12079
12080 /*
12081    Ops array is stored in the following format:
12082    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12083  */
12084 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12085 {
12086         const __be32 *source = (const __be32 *)_source;
12087         struct raw_op *target = (struct raw_op *)_target;
12088         u32 i, j, tmp;
12089
12090         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12091                 tmp = be32_to_cpu(source[j]);
12092                 target[i].op = (tmp >> 24) & 0xff;
12093                 target[i].offset = tmp & 0xffffff;
12094                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12095         }
12096 }
12097
12098 /* IRO array is stored in the following format:
12099  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12100  */
12101 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12102 {
12103         const __be32 *source = (const __be32 *)_source;
12104         struct iro *target = (struct iro *)_target;
12105         u32 i, j, tmp;
12106
12107         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12108                 target[i].base = be32_to_cpu(source[j]);
12109                 j++;
12110                 tmp = be32_to_cpu(source[j]);
12111                 target[i].m1 = (tmp >> 16) & 0xffff;
12112                 target[i].m2 = tmp & 0xffff;
12113                 j++;
12114                 tmp = be32_to_cpu(source[j]);
12115                 target[i].m3 = (tmp >> 16) & 0xffff;
12116                 target[i].size = tmp & 0xffff;
12117                 j++;
12118         }
12119 }
12120
12121 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12122 {
12123         const __be16 *source = (const __be16 *)_source;
12124         u16 *target = (u16 *)_target;
12125         u32 i;
12126
12127         for (i = 0; i < n/2; i++)
12128                 target[i] = be16_to_cpu(source[i]);
12129 }
12130
12131 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12132 do {                                                                    \
12133         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12134         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12135         if (!bp->arr)                                                   \
12136                 goto lbl;                                               \
12137         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12138              (u8 *)bp->arr, len);                                       \
12139 } while (0)
12140
12141 static int bnx2x_init_firmware(struct bnx2x *bp)
12142 {
12143         const char *fw_file_name;
12144         struct bnx2x_fw_file_hdr *fw_hdr;
12145         int rc;
12146
12147         if (bp->firmware)
12148                 return 0;
12149
12150         if (CHIP_IS_E1(bp))
12151                 fw_file_name = FW_FILE_NAME_E1;
12152         else if (CHIP_IS_E1H(bp))
12153                 fw_file_name = FW_FILE_NAME_E1H;
12154         else if (!CHIP_IS_E1x(bp))
12155                 fw_file_name = FW_FILE_NAME_E2;
12156         else {
12157                 BNX2X_ERR("Unsupported chip revision\n");
12158                 return -EINVAL;
12159         }
12160         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12161
12162         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12163         if (rc) {
12164                 BNX2X_ERR("Can't load firmware file %s\n",
12165                           fw_file_name);
12166                 goto request_firmware_exit;
12167         }
12168
12169         rc = bnx2x_check_firmware(bp);
12170         if (rc) {
12171                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12172                 goto request_firmware_exit;
12173         }
12174
12175         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12176
12177         /* Initialize the pointers to the init arrays */
12178         /* Blob */
12179         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12180
12181         /* Opcodes */
12182         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12183
12184         /* Offsets */
12185         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12186                             be16_to_cpu_n);
12187
12188         /* STORMs firmware */
12189         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12190                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12191         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12192                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12193         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12194                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12195         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12196                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12197         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12198                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12199         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12200                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12201         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12202                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12203         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12204                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12205         /* IRO */
12206         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12207
12208         return 0;
12209
12210 iro_alloc_err:
12211         kfree(bp->init_ops_offsets);
12212 init_offsets_alloc_err:
12213         kfree(bp->init_ops);
12214 init_ops_alloc_err:
12215         kfree(bp->init_data);
12216 request_firmware_exit:
12217         release_firmware(bp->firmware);
12218         bp->firmware = NULL;
12219
12220         return rc;
12221 }
12222
12223 static void bnx2x_release_firmware(struct bnx2x *bp)
12224 {
12225         kfree(bp->init_ops_offsets);
12226         kfree(bp->init_ops);
12227         kfree(bp->init_data);
12228         release_firmware(bp->firmware);
12229         bp->firmware = NULL;
12230 }
12231
12232
12233 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12234         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12235         .init_hw_cmn      = bnx2x_init_hw_common,
12236         .init_hw_port     = bnx2x_init_hw_port,
12237         .init_hw_func     = bnx2x_init_hw_func,
12238
12239         .reset_hw_cmn     = bnx2x_reset_common,
12240         .reset_hw_port    = bnx2x_reset_port,
12241         .reset_hw_func    = bnx2x_reset_func,
12242
12243         .gunzip_init      = bnx2x_gunzip_init,
12244         .gunzip_end       = bnx2x_gunzip_end,
12245
12246         .init_fw          = bnx2x_init_firmware,
12247         .release_fw       = bnx2x_release_firmware,
12248 };
12249
12250 void bnx2x__init_func_obj(struct bnx2x *bp)
12251 {
12252         /* Prepare DMAE related driver resources */
12253         bnx2x_setup_dmae(bp);
12254
12255         bnx2x_init_func_obj(bp, &bp->func_obj,
12256                             bnx2x_sp(bp, func_rdata),
12257                             bnx2x_sp_mapping(bp, func_rdata),
12258                             bnx2x_sp(bp, func_afex_rdata),
12259                             bnx2x_sp_mapping(bp, func_afex_rdata),
12260                             &bnx2x_func_sp_drv);
12261 }
12262
12263 /* must be called after sriov-enable */
12264 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12265 {
12266         int cid_count = BNX2X_L2_MAX_CID(bp);
12267
12268         if (IS_SRIOV(bp))
12269                 cid_count += BNX2X_VF_CIDS;
12270
12271         if (CNIC_SUPPORT(bp))
12272                 cid_count += CNIC_CID_MAX;
12273
12274         return roundup(cid_count, QM_CID_ROUND);
12275 }
12276
12277 /**
12278  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12279  *
12280  * @dev:        pci device
12281  *
12282  */
12283 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12284                                      int cnic_cnt, bool is_vf)
12285 {
12286         int pos, index;
12287         u16 control = 0;
12288
12289         pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12290
12291         /*
12292          * If MSI-X is not supported - return number of SBs needed to support
12293          * one fast path queue: one FP queue + SB for CNIC
12294          */
12295         if (!pos) {
12296                 dev_info(&pdev->dev, "no msix capability found\n");
12297                 return 1 + cnic_cnt;
12298         }
12299         dev_info(&pdev->dev, "msix capability found\n");
12300
12301         /*
12302          * The value in the PCI configuration space is the index of the last
12303          * entry, namely one less than the actual size of the table, which is
12304          * exactly what we want to return from this function: number of all SBs
12305          * without the default SB.
12306          * For VFs there is no default SB, then we return (index+1).
12307          */
12308         pci_read_config_word(pdev, pos  + PCI_MSI_FLAGS, &control);
12309
12310         index = control & PCI_MSIX_FLAGS_QSIZE;
12311
12312         return is_vf ? index + 1 : index;
12313 }
12314
12315 static int set_max_cos_est(int chip_id)
12316 {
12317         switch (chip_id) {
12318         case BCM57710:
12319         case BCM57711:
12320         case BCM57711E:
12321                 return BNX2X_MULTI_TX_COS_E1X;
12322         case BCM57712:
12323         case BCM57712_MF:
12324         case BCM57712_VF:
12325                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12326         case BCM57800:
12327         case BCM57800_MF:
12328         case BCM57800_VF:
12329         case BCM57810:
12330         case BCM57810_MF:
12331         case BCM57840_4_10:
12332         case BCM57840_2_20:
12333         case BCM57840_O:
12334         case BCM57840_MFO:
12335         case BCM57810_VF:
12336         case BCM57840_MF:
12337         case BCM57840_VF:
12338         case BCM57811:
12339         case BCM57811_MF:
12340         case BCM57811_VF:
12341                 return BNX2X_MULTI_TX_COS_E3B0;
12342                 return 1;
12343         default:
12344                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12345                 return -ENODEV;
12346         }
12347 }
12348
12349 static int set_is_vf(int chip_id)
12350 {
12351         switch (chip_id) {
12352         case BCM57712_VF:
12353         case BCM57800_VF:
12354         case BCM57810_VF:
12355         case BCM57840_VF:
12356         case BCM57811_VF:
12357                 return true;
12358         default:
12359                 return false;
12360         }
12361 }
12362
12363 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12364
12365 static int bnx2x_init_one(struct pci_dev *pdev,
12366                                     const struct pci_device_id *ent)
12367 {
12368         struct net_device *dev = NULL;
12369         struct bnx2x *bp;
12370         int pcie_width, pcie_speed;
12371         int rc, max_non_def_sbs;
12372         int rx_count, tx_count, rss_count, doorbell_size;
12373         int max_cos_est;
12374         bool is_vf;
12375         int cnic_cnt;
12376
12377         /* An estimated maximum supported CoS number according to the chip
12378          * version.
12379          * We will try to roughly estimate the maximum number of CoSes this chip
12380          * may support in order to minimize the memory allocated for Tx
12381          * netdev_queue's. This number will be accurately calculated during the
12382          * initialization of bp->max_cos based on the chip versions AND chip
12383          * revision in the bnx2x_init_bp().
12384          */
12385         max_cos_est = set_max_cos_est(ent->driver_data);
12386         if (max_cos_est < 0)
12387                 return max_cos_est;
12388         is_vf = set_is_vf(ent->driver_data);
12389         cnic_cnt = is_vf ? 0 : 1;
12390
12391         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12392
12393         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12394         rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12395
12396         if (rss_count < 1)
12397                 return -EINVAL;
12398
12399         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12400         rx_count = rss_count + cnic_cnt;
12401
12402         /* Maximum number of netdev Tx queues:
12403          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12404          */
12405         tx_count = rss_count * max_cos_est + cnic_cnt;
12406
12407         /* dev zeroed in init_etherdev */
12408         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12409         if (!dev)
12410                 return -ENOMEM;
12411
12412         bp = netdev_priv(dev);
12413
12414         bp->flags = 0;
12415         if (is_vf)
12416                 bp->flags |= IS_VF_FLAG;
12417
12418         bp->igu_sb_cnt = max_non_def_sbs;
12419         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12420         bp->msg_enable = debug;
12421         bp->cnic_support = cnic_cnt;
12422         bp->cnic_probe = bnx2x_cnic_probe;
12423
12424         pci_set_drvdata(pdev, dev);
12425
12426         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12427         if (rc < 0) {
12428                 free_netdev(dev);
12429                 return rc;
12430         }
12431
12432         BNX2X_DEV_INFO("This is a %s function\n",
12433                        IS_PF(bp) ? "physical" : "virtual");
12434         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12435         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12436         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12437                           tx_count, rx_count);
12438
12439         rc = bnx2x_init_bp(bp);
12440         if (rc)
12441                 goto init_one_exit;
12442
12443         /* Map doorbells here as we need the real value of bp->max_cos which
12444          * is initialized in bnx2x_init_bp() to determine the number of
12445          * l2 connections.
12446          */
12447         if (IS_VF(bp)) {
12448                 /* vf doorbells are embedded within the regview */
12449                 bp->doorbells = bp->regview + PXP_VF_ADDR_DB_START;
12450
12451                 /* allocate vf2pf mailbox for vf to pf channel */
12452                 BNX2X_PCI_ALLOC(bp->vf2pf_mbox, &bp->vf2pf_mbox_mapping,
12453                                 sizeof(struct bnx2x_vf_mbx_msg));
12454
12455                 /* allocate pf 2 vf bulletin board */
12456                 BNX2X_PCI_ALLOC(bp->pf2vf_bulletin, &bp->pf2vf_bulletin_mapping,
12457                                 sizeof(union pf_vf_bulletin));
12458
12459         } else {
12460                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12461                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12462                         dev_err(&bp->pdev->dev,
12463                                 "Cannot map doorbells, bar size too small, aborting\n");
12464                         rc = -ENOMEM;
12465                         goto init_one_exit;
12466                 }
12467                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12468                                                 doorbell_size);
12469         }
12470         if (!bp->doorbells) {
12471                 dev_err(&bp->pdev->dev,
12472                         "Cannot map doorbell space, aborting\n");
12473                 rc = -ENOMEM;
12474                 goto init_one_exit;
12475         }
12476
12477         if (IS_VF(bp)) {
12478                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12479                 if (rc)
12480                         goto init_one_exit;
12481         }
12482
12483         /* Enable SRIOV if capability found in configuration space.
12484          * Once the generic SR-IOV framework makes it in from the
12485          * pci tree this will be revised, to allow dynamic control
12486          * over the number of VFs. Right now, change the num of vfs
12487          * param below to enable SR-IOV.
12488          */
12489         rc = bnx2x_iov_init_one(bp, int_mode, 0/*num vfs*/);
12490         if (rc)
12491                 goto init_one_exit;
12492
12493         /* calc qm_cid_count */
12494         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12495         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12496
12497         /* disable FCOE L2 queue for E1x*/
12498         if (CHIP_IS_E1x(bp))
12499                 bp->flags |= NO_FCOE_FLAG;
12500
12501         /* disable FCOE for 57840 device, until FW supports it */
12502         switch (ent->driver_data) {
12503         case BCM57840_O:
12504         case BCM57840_4_10:
12505         case BCM57840_2_20:
12506         case BCM57840_MFO:
12507         case BCM57840_MF:
12508                 bp->flags |= NO_FCOE_FLAG;
12509         }
12510
12511         /* Set bp->num_queues for MSI-X mode*/
12512         bnx2x_set_num_queues(bp);
12513
12514         /* Configure interrupt mode: try to enable MSI-X/MSI if
12515          * needed.
12516          */
12517         rc = bnx2x_set_int_mode(bp);
12518         if (rc) {
12519                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12520                 goto init_one_exit;
12521         }
12522
12523         /* register the net device */
12524         rc = register_netdev(dev);
12525         if (rc) {
12526                 dev_err(&pdev->dev, "Cannot register net device\n");
12527                 goto init_one_exit;
12528         }
12529         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12530
12531
12532         if (!NO_FCOE(bp)) {
12533                 /* Add storage MAC address */
12534                 rtnl_lock();
12535                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12536                 rtnl_unlock();
12537         }
12538
12539         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12540         BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12541                        pcie_width, pcie_speed);
12542
12543         BNX2X_DEV_INFO(
12544                 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12545                     board_info[ent->driver_data].name,
12546                     (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12547                     pcie_width,
12548                     ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12549                      (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12550                     "5GHz (Gen2)" : "2.5GHz",
12551                     dev->base_addr, bp->pdev->irq, dev->dev_addr);
12552
12553         return 0;
12554
12555 alloc_mem_err:
12556         BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping,
12557                        sizeof(struct bnx2x_vf_mbx_msg));
12558         rc = -ENOMEM;
12559
12560 init_one_exit:
12561         if (bp->regview)
12562                 iounmap(bp->regview);
12563
12564         if (IS_PF(bp) && bp->doorbells)
12565                 iounmap(bp->doorbells);
12566
12567         free_netdev(dev);
12568
12569         if (atomic_read(&pdev->enable_cnt) == 1)
12570                 pci_release_regions(pdev);
12571
12572         pci_disable_device(pdev);
12573         pci_set_drvdata(pdev, NULL);
12574
12575         return rc;
12576 }
12577
12578 static void bnx2x_remove_one(struct pci_dev *pdev)
12579 {
12580         struct net_device *dev = pci_get_drvdata(pdev);
12581         struct bnx2x *bp;
12582
12583         if (!dev) {
12584                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12585                 return;
12586         }
12587         bp = netdev_priv(dev);
12588
12589         /* Delete storage MAC address */
12590         if (!NO_FCOE(bp)) {
12591                 rtnl_lock();
12592                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12593                 rtnl_unlock();
12594         }
12595
12596 #ifdef BCM_DCBNL
12597         /* Delete app tlvs from dcbnl */
12598         bnx2x_dcbnl_update_applist(bp, true);
12599 #endif
12600
12601         unregister_netdev(dev);
12602
12603         /* Power on: we can't let PCI layer write to us while we are in D3 */
12604         if (IS_PF(bp))
12605                 bnx2x_set_power_state(bp, PCI_D0);
12606
12607         /* Disable MSI/MSI-X */
12608         bnx2x_disable_msi(bp);
12609
12610         /* Power off */
12611         if (IS_PF(bp))
12612                 bnx2x_set_power_state(bp, PCI_D3hot);
12613
12614         /* Make sure RESET task is not scheduled before continuing */
12615         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12616
12617         bnx2x_iov_remove_one(bp);
12618
12619         /* send message via vfpf channel to release the resources of this vf */
12620         if (IS_VF(bp))
12621                 bnx2x_vfpf_release(bp);
12622
12623         if (bp->regview)
12624                 iounmap(bp->regview);
12625
12626         /* for vf doorbells are part of the regview and were unmapped along with
12627          * it. FW is only loaded by PF.
12628          */
12629         if (IS_PF(bp)) {
12630                 if (bp->doorbells)
12631                         iounmap(bp->doorbells);
12632
12633                 bnx2x_release_firmware(bp);
12634         }
12635         bnx2x_free_mem_bp(bp);
12636
12637         free_netdev(dev);
12638
12639         if (atomic_read(&pdev->enable_cnt) == 1)
12640                 pci_release_regions(pdev);
12641
12642         pci_disable_device(pdev);
12643         pci_set_drvdata(pdev, NULL);
12644 }
12645
12646 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12647 {
12648         int i;
12649
12650         bp->state = BNX2X_STATE_ERROR;
12651
12652         bp->rx_mode = BNX2X_RX_MODE_NONE;
12653
12654         if (CNIC_LOADED(bp))
12655                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12656
12657         /* Stop Tx */
12658         bnx2x_tx_disable(bp);
12659
12660         bnx2x_netif_stop(bp, 0);
12661         /* Delete all NAPI objects */
12662         bnx2x_del_all_napi(bp);
12663         if (CNIC_LOADED(bp))
12664                 bnx2x_del_all_napi_cnic(bp);
12665
12666         del_timer_sync(&bp->timer);
12667
12668         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12669
12670         /* Release IRQs */
12671         bnx2x_free_irq(bp);
12672
12673         /* Free SKBs, SGEs, TPA pool and driver internals */
12674         bnx2x_free_skbs(bp);
12675
12676         for_each_rx_queue(bp, i)
12677                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12678
12679         bnx2x_free_mem(bp);
12680
12681         bp->state = BNX2X_STATE_CLOSED;
12682
12683         netif_carrier_off(bp->dev);
12684
12685         return 0;
12686 }
12687
12688 static void bnx2x_eeh_recover(struct bnx2x *bp)
12689 {
12690         u32 val;
12691
12692         mutex_init(&bp->port.phy_mutex);
12693
12694
12695         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12696         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12697                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12698                 BNX2X_ERR("BAD MCP validity signature\n");
12699 }
12700
12701 /**
12702  * bnx2x_io_error_detected - called when PCI error is detected
12703  * @pdev: Pointer to PCI device
12704  * @state: The current pci connection state
12705  *
12706  * This function is called after a PCI bus error affecting
12707  * this device has been detected.
12708  */
12709 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12710                                                 pci_channel_state_t state)
12711 {
12712         struct net_device *dev = pci_get_drvdata(pdev);
12713         struct bnx2x *bp = netdev_priv(dev);
12714
12715         rtnl_lock();
12716
12717         netif_device_detach(dev);
12718
12719         if (state == pci_channel_io_perm_failure) {
12720                 rtnl_unlock();
12721                 return PCI_ERS_RESULT_DISCONNECT;
12722         }
12723
12724         if (netif_running(dev))
12725                 bnx2x_eeh_nic_unload(bp);
12726
12727         pci_disable_device(pdev);
12728
12729         rtnl_unlock();
12730
12731         /* Request a slot reset */
12732         return PCI_ERS_RESULT_NEED_RESET;
12733 }
12734
12735 /**
12736  * bnx2x_io_slot_reset - called after the PCI bus has been reset
12737  * @pdev: Pointer to PCI device
12738  *
12739  * Restart the card from scratch, as if from a cold-boot.
12740  */
12741 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12742 {
12743         struct net_device *dev = pci_get_drvdata(pdev);
12744         struct bnx2x *bp = netdev_priv(dev);
12745
12746         rtnl_lock();
12747
12748         if (pci_enable_device(pdev)) {
12749                 dev_err(&pdev->dev,
12750                         "Cannot re-enable PCI device after reset\n");
12751                 rtnl_unlock();
12752                 return PCI_ERS_RESULT_DISCONNECT;
12753         }
12754
12755         pci_set_master(pdev);
12756         pci_restore_state(pdev);
12757
12758         if (netif_running(dev))
12759                 bnx2x_set_power_state(bp, PCI_D0);
12760
12761         rtnl_unlock();
12762
12763         return PCI_ERS_RESULT_RECOVERED;
12764 }
12765
12766 /**
12767  * bnx2x_io_resume - called when traffic can start flowing again
12768  * @pdev: Pointer to PCI device
12769  *
12770  * This callback is called when the error recovery driver tells us that
12771  * its OK to resume normal operation.
12772  */
12773 static void bnx2x_io_resume(struct pci_dev *pdev)
12774 {
12775         struct net_device *dev = pci_get_drvdata(pdev);
12776         struct bnx2x *bp = netdev_priv(dev);
12777
12778         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12779                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12780                 return;
12781         }
12782
12783         rtnl_lock();
12784
12785         bnx2x_eeh_recover(bp);
12786
12787         if (netif_running(dev))
12788                 bnx2x_nic_load(bp, LOAD_NORMAL);
12789
12790         netif_device_attach(dev);
12791
12792         rtnl_unlock();
12793 }
12794
12795 static const struct pci_error_handlers bnx2x_err_handler = {
12796         .error_detected = bnx2x_io_error_detected,
12797         .slot_reset     = bnx2x_io_slot_reset,
12798         .resume         = bnx2x_io_resume,
12799 };
12800
12801 static struct pci_driver bnx2x_pci_driver = {
12802         .name        = DRV_MODULE_NAME,
12803         .id_table    = bnx2x_pci_tbl,
12804         .probe       = bnx2x_init_one,
12805         .remove      = bnx2x_remove_one,
12806         .suspend     = bnx2x_suspend,
12807         .resume      = bnx2x_resume,
12808         .err_handler = &bnx2x_err_handler,
12809 };
12810
12811 static int __init bnx2x_init(void)
12812 {
12813         int ret;
12814
12815         pr_info("%s", version);
12816
12817         bnx2x_wq = create_singlethread_workqueue("bnx2x");
12818         if (bnx2x_wq == NULL) {
12819                 pr_err("Cannot create workqueue\n");
12820                 return -ENOMEM;
12821         }
12822
12823         ret = pci_register_driver(&bnx2x_pci_driver);
12824         if (ret) {
12825                 pr_err("Cannot register driver\n");
12826                 destroy_workqueue(bnx2x_wq);
12827         }
12828         return ret;
12829 }
12830
12831 static void __exit bnx2x_cleanup(void)
12832 {
12833         struct list_head *pos, *q;
12834         pci_unregister_driver(&bnx2x_pci_driver);
12835
12836         destroy_workqueue(bnx2x_wq);
12837
12838         /* Free globablly allocated resources */
12839         list_for_each_safe(pos, q, &bnx2x_prev_list) {
12840                 struct bnx2x_prev_path_list *tmp =
12841                         list_entry(pos, struct bnx2x_prev_path_list, list);
12842                 list_del(pos);
12843                 kfree(tmp);
12844         }
12845 }
12846
12847 void bnx2x_notify_link_changed(struct bnx2x *bp)
12848 {
12849         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12850 }
12851
12852 module_init(bnx2x_init);
12853 module_exit(bnx2x_cleanup);
12854
12855 /**
12856  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12857  *
12858  * @bp:         driver handle
12859  * @set:        set or clear the CAM entry
12860  *
12861  * This function will wait until the ramdord completion returns.
12862  * Return 0 if success, -ENODEV if ramrod doesn't return.
12863  */
12864 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12865 {
12866         unsigned long ramrod_flags = 0;
12867
12868         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12869         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12870                                  &bp->iscsi_l2_mac_obj, true,
12871                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12872 }
12873
12874 /* count denotes the number of new completions we have seen */
12875 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12876 {
12877         struct eth_spe *spe;
12878         int cxt_index, cxt_offset;
12879
12880 #ifdef BNX2X_STOP_ON_ERROR
12881         if (unlikely(bp->panic))
12882                 return;
12883 #endif
12884
12885         spin_lock_bh(&bp->spq_lock);
12886         BUG_ON(bp->cnic_spq_pending < count);
12887         bp->cnic_spq_pending -= count;
12888
12889
12890         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12891                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12892                                 & SPE_HDR_CONN_TYPE) >>
12893                                 SPE_HDR_CONN_TYPE_SHIFT;
12894                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12895                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12896
12897                 /* Set validation for iSCSI L2 client before sending SETUP
12898                  *  ramrod
12899                  */
12900                 if (type == ETH_CONNECTION_TYPE) {
12901                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12902                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12903                                         ILT_PAGE_CIDS;
12904                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12905                                         (cxt_index * ILT_PAGE_CIDS);
12906                                 bnx2x_set_ctx_validation(bp,
12907                                         &bp->context[cxt_index].
12908                                                          vcxt[cxt_offset].eth,
12909                                         BNX2X_ISCSI_ETH_CID(bp));
12910                         }
12911                 }
12912
12913                 /*
12914                  * There may be not more than 8 L2, not more than 8 L5 SPEs
12915                  * and in the air. We also check that number of outstanding
12916                  * COMMON ramrods is not more than the EQ and SPQ can
12917                  * accommodate.
12918                  */
12919                 if (type == ETH_CONNECTION_TYPE) {
12920                         if (!atomic_read(&bp->cq_spq_left))
12921                                 break;
12922                         else
12923                                 atomic_dec(&bp->cq_spq_left);
12924                 } else if (type == NONE_CONNECTION_TYPE) {
12925                         if (!atomic_read(&bp->eq_spq_left))
12926                                 break;
12927                         else
12928                                 atomic_dec(&bp->eq_spq_left);
12929                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12930                            (type == FCOE_CONNECTION_TYPE)) {
12931                         if (bp->cnic_spq_pending >=
12932                             bp->cnic_eth_dev.max_kwqe_pending)
12933                                 break;
12934                         else
12935                                 bp->cnic_spq_pending++;
12936                 } else {
12937                         BNX2X_ERR("Unknown SPE type: %d\n", type);
12938                         bnx2x_panic();
12939                         break;
12940                 }
12941
12942                 spe = bnx2x_sp_get_next(bp);
12943                 *spe = *bp->cnic_kwq_cons;
12944
12945                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12946                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12947
12948                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12949                         bp->cnic_kwq_cons = bp->cnic_kwq;
12950                 else
12951                         bp->cnic_kwq_cons++;
12952         }
12953         bnx2x_sp_prod_update(bp);
12954         spin_unlock_bh(&bp->spq_lock);
12955 }
12956
12957 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12958                                struct kwqe_16 *kwqes[], u32 count)
12959 {
12960         struct bnx2x *bp = netdev_priv(dev);
12961         int i;
12962
12963 #ifdef BNX2X_STOP_ON_ERROR
12964         if (unlikely(bp->panic)) {
12965                 BNX2X_ERR("Can't post to SP queue while panic\n");
12966                 return -EIO;
12967         }
12968 #endif
12969
12970         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12971             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12972                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12973                 return -EAGAIN;
12974         }
12975
12976         spin_lock_bh(&bp->spq_lock);
12977
12978         for (i = 0; i < count; i++) {
12979                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12980
12981                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12982                         break;
12983
12984                 *bp->cnic_kwq_prod = *spe;
12985
12986                 bp->cnic_kwq_pending++;
12987
12988                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12989                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
12990                    spe->data.update_data_addr.hi,
12991                    spe->data.update_data_addr.lo,
12992                    bp->cnic_kwq_pending);
12993
12994                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12995                         bp->cnic_kwq_prod = bp->cnic_kwq;
12996                 else
12997                         bp->cnic_kwq_prod++;
12998         }
12999
13000         spin_unlock_bh(&bp->spq_lock);
13001
13002         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13003                 bnx2x_cnic_sp_post(bp, 0);
13004
13005         return i;
13006 }
13007
13008 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13009 {
13010         struct cnic_ops *c_ops;
13011         int rc = 0;
13012
13013         mutex_lock(&bp->cnic_mutex);
13014         c_ops = rcu_dereference_protected(bp->cnic_ops,
13015                                           lockdep_is_held(&bp->cnic_mutex));
13016         if (c_ops)
13017                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13018         mutex_unlock(&bp->cnic_mutex);
13019
13020         return rc;
13021 }
13022
13023 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13024 {
13025         struct cnic_ops *c_ops;
13026         int rc = 0;
13027
13028         rcu_read_lock();
13029         c_ops = rcu_dereference(bp->cnic_ops);
13030         if (c_ops)
13031                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13032         rcu_read_unlock();
13033
13034         return rc;
13035 }
13036
13037 /*
13038  * for commands that have no data
13039  */
13040 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13041 {
13042         struct cnic_ctl_info ctl = {0};
13043
13044         ctl.cmd = cmd;
13045
13046         return bnx2x_cnic_ctl_send(bp, &ctl);
13047 }
13048
13049 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13050 {
13051         struct cnic_ctl_info ctl = {0};
13052
13053         /* first we tell CNIC and only then we count this as a completion */
13054         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13055         ctl.data.comp.cid = cid;
13056         ctl.data.comp.error = err;
13057
13058         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13059         bnx2x_cnic_sp_post(bp, 0);
13060 }
13061
13062
13063 /* Called with netif_addr_lock_bh() taken.
13064  * Sets an rx_mode config for an iSCSI ETH client.
13065  * Doesn't block.
13066  * Completion should be checked outside.
13067  */
13068 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13069 {
13070         unsigned long accept_flags = 0, ramrod_flags = 0;
13071         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13072         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13073
13074         if (start) {
13075                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13076                  * because it's the only way for UIO Queue to accept
13077                  * multicasts (in non-promiscuous mode only one Queue per
13078                  * function will receive multicast packets (leading in our
13079                  * case).
13080                  */
13081                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13082                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13083                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13084                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13085
13086                 /* Clear STOP_PENDING bit if START is requested */
13087                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13088
13089                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13090         } else
13091                 /* Clear START_PENDING bit if STOP is requested */
13092                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13093
13094         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13095                 set_bit(sched_state, &bp->sp_state);
13096         else {
13097                 __set_bit(RAMROD_RX, &ramrod_flags);
13098                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13099                                     ramrod_flags);
13100         }
13101 }
13102
13103
13104 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13105 {
13106         struct bnx2x *bp = netdev_priv(dev);
13107         int rc = 0;
13108
13109         switch (ctl->cmd) {
13110         case DRV_CTL_CTXTBL_WR_CMD: {
13111                 u32 index = ctl->data.io.offset;
13112                 dma_addr_t addr = ctl->data.io.dma_addr;
13113
13114                 bnx2x_ilt_wr(bp, index, addr);
13115                 break;
13116         }
13117
13118         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13119                 int count = ctl->data.credit.credit_count;
13120
13121                 bnx2x_cnic_sp_post(bp, count);
13122                 break;
13123         }
13124
13125         /* rtnl_lock is held.  */
13126         case DRV_CTL_START_L2_CMD: {
13127                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13128                 unsigned long sp_bits = 0;
13129
13130                 /* Configure the iSCSI classification object */
13131                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13132                                    cp->iscsi_l2_client_id,
13133                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13134                                    bnx2x_sp(bp, mac_rdata),
13135                                    bnx2x_sp_mapping(bp, mac_rdata),
13136                                    BNX2X_FILTER_MAC_PENDING,
13137                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13138                                    &bp->macs_pool);
13139
13140                 /* Set iSCSI MAC address */
13141                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13142                 if (rc)
13143                         break;
13144
13145                 mmiowb();
13146                 barrier();
13147
13148                 /* Start accepting on iSCSI L2 ring */
13149
13150                 netif_addr_lock_bh(dev);
13151                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13152                 netif_addr_unlock_bh(dev);
13153
13154                 /* bits to wait on */
13155                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13156                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13157
13158                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13159                         BNX2X_ERR("rx_mode completion timed out!\n");
13160
13161                 break;
13162         }
13163
13164         /* rtnl_lock is held.  */
13165         case DRV_CTL_STOP_L2_CMD: {
13166                 unsigned long sp_bits = 0;
13167
13168                 /* Stop accepting on iSCSI L2 ring */
13169                 netif_addr_lock_bh(dev);
13170                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13171                 netif_addr_unlock_bh(dev);
13172
13173                 /* bits to wait on */
13174                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13175                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13176
13177                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13178                         BNX2X_ERR("rx_mode completion timed out!\n");
13179
13180                 mmiowb();
13181                 barrier();
13182
13183                 /* Unset iSCSI L2 MAC */
13184                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13185                                         BNX2X_ISCSI_ETH_MAC, true);
13186                 break;
13187         }
13188         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13189                 int count = ctl->data.credit.credit_count;
13190
13191                 smp_mb__before_atomic_inc();
13192                 atomic_add(count, &bp->cq_spq_left);
13193                 smp_mb__after_atomic_inc();
13194                 break;
13195         }
13196         case DRV_CTL_ULP_REGISTER_CMD: {
13197                 int ulp_type = ctl->data.register_data.ulp_type;
13198
13199                 if (CHIP_IS_E3(bp)) {
13200                         int idx = BP_FW_MB_IDX(bp);
13201                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13202                         int path = BP_PATH(bp);
13203                         int port = BP_PORT(bp);
13204                         int i;
13205                         u32 scratch_offset;
13206                         u32 *host_addr;
13207
13208                         /* first write capability to shmem2 */
13209                         if (ulp_type == CNIC_ULP_ISCSI)
13210                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13211                         else if (ulp_type == CNIC_ULP_FCOE)
13212                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13213                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13214
13215                         if ((ulp_type != CNIC_ULP_FCOE) ||
13216                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13217                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13218                                 break;
13219
13220                         /* if reached here - should write fcoe capabilities */
13221                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13222                         if (!scratch_offset)
13223                                 break;
13224                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13225                                                    fcoe_features[path][port]);
13226                         host_addr = (u32 *) &(ctl->data.register_data.
13227                                               fcoe_features);
13228                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13229                              i += 4)
13230                                 REG_WR(bp, scratch_offset + i,
13231                                        *(host_addr + i/4));
13232                 }
13233                 break;
13234         }
13235
13236         case DRV_CTL_ULP_UNREGISTER_CMD: {
13237                 int ulp_type = ctl->data.ulp_type;
13238
13239                 if (CHIP_IS_E3(bp)) {
13240                         int idx = BP_FW_MB_IDX(bp);
13241                         u32 cap;
13242
13243                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13244                         if (ulp_type == CNIC_ULP_ISCSI)
13245                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13246                         else if (ulp_type == CNIC_ULP_FCOE)
13247                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13248                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13249                 }
13250                 break;
13251         }
13252
13253         default:
13254                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13255                 rc = -EINVAL;
13256         }
13257
13258         return rc;
13259 }
13260
13261 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13262 {
13263         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13264
13265         if (bp->flags & USING_MSIX_FLAG) {
13266                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13267                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13268                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13269         } else {
13270                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13271                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13272         }
13273         if (!CHIP_IS_E1x(bp))
13274                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13275         else
13276                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13277
13278         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13279         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13280         cp->irq_arr[1].status_blk = bp->def_status_blk;
13281         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13282         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13283
13284         cp->num_irq = 2;
13285 }
13286
13287 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13288 {
13289         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13290
13291
13292         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13293                              bnx2x_cid_ilt_lines(bp);
13294         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13295         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13296         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13297
13298         if (NO_ISCSI_OOO(bp))
13299                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13300 }
13301
13302 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13303                                void *data)
13304 {
13305         struct bnx2x *bp = netdev_priv(dev);
13306         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13307         int rc;
13308
13309         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13310
13311         if (ops == NULL) {
13312                 BNX2X_ERR("NULL ops received\n");
13313                 return -EINVAL;
13314         }
13315
13316         if (!CNIC_SUPPORT(bp)) {
13317                 BNX2X_ERR("Can't register CNIC when not supported\n");
13318                 return -EOPNOTSUPP;
13319         }
13320
13321         if (!CNIC_LOADED(bp)) {
13322                 rc = bnx2x_load_cnic(bp);
13323                 if (rc) {
13324                         BNX2X_ERR("CNIC-related load failed\n");
13325                         return rc;
13326                 }
13327
13328         }
13329
13330         bp->cnic_enabled = true;
13331
13332         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13333         if (!bp->cnic_kwq)
13334                 return -ENOMEM;
13335
13336         bp->cnic_kwq_cons = bp->cnic_kwq;
13337         bp->cnic_kwq_prod = bp->cnic_kwq;
13338         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13339
13340         bp->cnic_spq_pending = 0;
13341         bp->cnic_kwq_pending = 0;
13342
13343         bp->cnic_data = data;
13344
13345         cp->num_irq = 0;
13346         cp->drv_state |= CNIC_DRV_STATE_REGD;
13347         cp->iro_arr = bp->iro_arr;
13348
13349         bnx2x_setup_cnic_irq_info(bp);
13350
13351         rcu_assign_pointer(bp->cnic_ops, ops);
13352
13353         return 0;
13354 }
13355
13356 static int bnx2x_unregister_cnic(struct net_device *dev)
13357 {
13358         struct bnx2x *bp = netdev_priv(dev);
13359         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13360
13361         mutex_lock(&bp->cnic_mutex);
13362         cp->drv_state = 0;
13363         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13364         mutex_unlock(&bp->cnic_mutex);
13365         synchronize_rcu();
13366         kfree(bp->cnic_kwq);
13367         bp->cnic_kwq = NULL;
13368
13369         return 0;
13370 }
13371
13372 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13373 {
13374         struct bnx2x *bp = netdev_priv(dev);
13375         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13376
13377         /* If both iSCSI and FCoE are disabled - return NULL in
13378          * order to indicate CNIC that it should not try to work
13379          * with this device.
13380          */
13381         if (NO_ISCSI(bp) && NO_FCOE(bp))
13382                 return NULL;
13383
13384         cp->drv_owner = THIS_MODULE;
13385         cp->chip_id = CHIP_ID(bp);
13386         cp->pdev = bp->pdev;
13387         cp->io_base = bp->regview;
13388         cp->io_base2 = bp->doorbells;
13389         cp->max_kwqe_pending = 8;
13390         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13391         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13392                              bnx2x_cid_ilt_lines(bp);
13393         cp->ctx_tbl_len = CNIC_ILT_LINES;
13394         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13395         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13396         cp->drv_ctl = bnx2x_drv_ctl;
13397         cp->drv_register_cnic = bnx2x_register_cnic;
13398         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13399         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13400         cp->iscsi_l2_client_id =
13401                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13402         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13403
13404         if (NO_ISCSI_OOO(bp))
13405                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13406
13407         if (NO_ISCSI(bp))
13408                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13409
13410         if (NO_FCOE(bp))
13411                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13412
13413         BNX2X_DEV_INFO(
13414                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13415            cp->ctx_blk_size,
13416            cp->ctx_tbl_offset,
13417            cp->ctx_tbl_len,
13418            cp->starting_cid);
13419         return cp;
13420 }
13421
13422 int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping)
13423 {
13424         struct cstorm_vf_zone_data __iomem *zone_data =
13425                 REG_ADDR(bp, PXP_VF_ADDR_CSDM_GLOBAL_START);
13426         int tout = 600, interval = 100; /* wait for 60 seconds */
13427
13428         if (*done) {
13429                 BNX2X_ERR("done was non zero before message to pf was sent\n");
13430                 WARN_ON(true);
13431                 return -EINVAL;
13432         }
13433
13434         /* Write message address */
13435         writel(U64_LO(msg_mapping),
13436                &zone_data->non_trigger.vf_pf_channel.msg_addr_lo);
13437         writel(U64_HI(msg_mapping),
13438                &zone_data->non_trigger.vf_pf_channel.msg_addr_hi);
13439
13440         /* make sure the address is written before FW accesses it */
13441         wmb();
13442
13443         /* Trigger the PF FW */
13444         writeb(1, &zone_data->trigger.vf_pf_channel.addr_valid);
13445
13446         /* Wait for PF to complete */
13447         while ((tout >= 0) && (!*done)) {
13448                 msleep(interval);
13449                 tout -= 1;
13450
13451                 /* progress indicator - HV can take its own sweet time in
13452                  * answering VFs...
13453                  */
13454                 DP_CONT(BNX2X_MSG_IOV, ".");
13455         }
13456
13457         if (!*done) {
13458                 BNX2X_ERR("PF response has timed out\n");
13459                 return -EAGAIN;
13460         }
13461         DP(BNX2X_MSG_SP, "Got a response from PF\n");
13462         return 0;
13463 }
13464
13465 int bnx2x_get_vf_id(struct bnx2x *bp, u32 *vf_id)
13466 {
13467         u32 me_reg;
13468         int tout = 10, interval = 100; /* Wait for 1 sec */
13469
13470         do {
13471                 /* pxp traps vf read of doorbells and returns me reg value */
13472                 me_reg = readl(bp->doorbells);
13473                 if (GOOD_ME_REG(me_reg))
13474                         break;
13475
13476                 msleep(interval);
13477
13478                 BNX2X_ERR("Invalid ME register value: 0x%08x\n. Is pf driver up?",
13479                           me_reg);
13480         } while (tout-- > 0);
13481
13482         if (!GOOD_ME_REG(me_reg)) {
13483                 BNX2X_ERR("Invalid ME register value: 0x%08x\n", me_reg);
13484                 return -EINVAL;
13485         }
13486
13487         BNX2X_ERR("valid ME register value: 0x%08x\n", me_reg);
13488
13489         *vf_id = (me_reg & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT;
13490
13491         return 0;
13492 }
13493
13494 int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count)
13495 {
13496         int rc = 0, attempts = 0;
13497         struct vfpf_acquire_tlv *req = &bp->vf2pf_mbox->req.acquire;
13498         struct pfvf_acquire_resp_tlv *resp = &bp->vf2pf_mbox->resp.acquire_resp;
13499         u32 vf_id;
13500         bool resources_acquired = false;
13501
13502         /* clear mailbox and prep first tlv */
13503         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_ACQUIRE, sizeof(*req));
13504
13505         if (bnx2x_get_vf_id(bp, &vf_id))
13506                 return -EAGAIN;
13507
13508         req->vfdev_info.vf_id = vf_id;
13509         req->vfdev_info.vf_os = 0;
13510
13511         req->resc_request.num_rxqs = rx_count;
13512         req->resc_request.num_txqs = tx_count;
13513         req->resc_request.num_sbs = bp->igu_sb_cnt;
13514         req->resc_request.num_mac_filters = VF_ACQUIRE_MAC_FILTERS;
13515         req->resc_request.num_mc_filters = VF_ACQUIRE_MC_FILTERS;
13516
13517         /* pf 2 vf bulletin board address */
13518         req->bulletin_addr = bp->pf2vf_bulletin_mapping;
13519
13520         /* add list termination tlv */
13521         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13522                       sizeof(struct channel_list_end_tlv));
13523
13524         /* output tlvs list */
13525         bnx2x_dp_tlv_list(bp, req);
13526
13527         while (!resources_acquired) {
13528                 DP(BNX2X_MSG_SP, "attempting to acquire resources\n");
13529
13530                 /* send acquire request */
13531                 rc = bnx2x_send_msg2pf(bp,
13532                                        &resp->hdr.status,
13533                                        bp->vf2pf_mbox_mapping);
13534
13535                 /* PF timeout */
13536                 if (rc)
13537                         return rc;
13538
13539                 /* copy acquire response from buffer to bp */
13540                 memcpy(&bp->acquire_resp, resp, sizeof(bp->acquire_resp));
13541
13542                 attempts++;
13543
13544                 /* test whether the PF accepted our request. If not, humble the
13545                  * the request and try again.
13546                  */
13547                 if (bp->acquire_resp.hdr.status == PFVF_STATUS_SUCCESS) {
13548                         DP(BNX2X_MSG_SP, "resources acquired\n");
13549                         resources_acquired = true;
13550                 } else if (bp->acquire_resp.hdr.status ==
13551                            PFVF_STATUS_NO_RESOURCE &&
13552                            attempts < VF_ACQUIRE_THRESH) {
13553                         DP(BNX2X_MSG_SP,
13554                            "PF unwilling to fulfill resource request. Try PF recommended amount\n");
13555
13556                         /* humble our request */
13557                         req->resc_request.num_txqs =
13558                                 bp->acquire_resp.resc.num_txqs;
13559                         req->resc_request.num_rxqs =
13560                                 bp->acquire_resp.resc.num_rxqs;
13561                         req->resc_request.num_sbs =
13562                                 bp->acquire_resp.resc.num_sbs;
13563                         req->resc_request.num_mac_filters =
13564                                 bp->acquire_resp.resc.num_mac_filters;
13565                         req->resc_request.num_vlan_filters =
13566                                 bp->acquire_resp.resc.num_vlan_filters;
13567                         req->resc_request.num_mc_filters =
13568                                 bp->acquire_resp.resc.num_mc_filters;
13569
13570                         /* Clear response buffer */
13571                         memset(&bp->vf2pf_mbox->resp, 0,
13572                                sizeof(union pfvf_tlvs));
13573                 } else {
13574                         /* PF reports error */
13575                         BNX2X_ERR("Failed to get the requested amount of resources: %d. Breaking...\n",
13576                                   bp->acquire_resp.hdr.status);
13577                         return -EAGAIN;
13578                 }
13579         }
13580
13581         /* get HW info */
13582         bp->common.chip_id |= (bp->acquire_resp.pfdev_info.chip_num & 0xffff);
13583         bp->link_params.chip_id = bp->common.chip_id;
13584         bp->db_size = bp->acquire_resp.pfdev_info.db_size;
13585         bp->common.int_block = INT_BLOCK_IGU;
13586         bp->common.chip_port_mode = CHIP_2_PORT_MODE;
13587         bp->igu_dsb_id = -1;
13588         bp->mf_ov = 0;
13589         bp->mf_mode = 0;
13590         bp->common.flash_size = 0;
13591         bp->flags |=
13592                 NO_WOL_FLAG | NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG | NO_FCOE_FLAG;
13593         bp->igu_sb_cnt = 1;
13594         bp->igu_base_sb = bp->acquire_resp.resc.hw_sbs[0].hw_sb_id;
13595         strlcpy(bp->fw_ver, bp->acquire_resp.pfdev_info.fw_ver,
13596                 sizeof(bp->fw_ver));
13597
13598         if (is_valid_ether_addr(bp->acquire_resp.resc.current_mac_addr))
13599                 memcpy(bp->dev->dev_addr,
13600                        bp->acquire_resp.resc.current_mac_addr,
13601                        ETH_ALEN);
13602
13603         return 0;
13604 }
13605
13606 int bnx2x_vfpf_release(struct bnx2x *bp)
13607 {
13608         struct vfpf_release_tlv *req = &bp->vf2pf_mbox->req.release;
13609         struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13610         u32 rc = 0, vf_id;
13611
13612         /* clear mailbox and prep first tlv */
13613         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_RELEASE, sizeof(*req));
13614
13615         if (bnx2x_get_vf_id(bp, &vf_id))
13616                 return -EAGAIN;
13617
13618         req->vf_id = vf_id;
13619
13620         /* add list termination tlv */
13621         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13622                       sizeof(struct channel_list_end_tlv));
13623
13624         /* output tlvs list */
13625         bnx2x_dp_tlv_list(bp, req);
13626
13627         /* send release request */
13628         rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13629
13630         if (rc)
13631                 /* PF timeout */
13632                 return rc;
13633         if (resp->hdr.status == PFVF_STATUS_SUCCESS) {
13634                 /* PF released us */
13635                 DP(BNX2X_MSG_SP, "vf released\n");
13636         } else {
13637                 /* PF reports error */
13638                 BNX2X_ERR("PF failed our release request - are we out of sync? response status: %d\n",
13639                           resp->hdr.status);
13640                 return -EAGAIN;
13641         }
13642
13643         return 0;
13644 }
13645
13646 /* Tell PF about SB addresses */
13647 int bnx2x_vfpf_init(struct bnx2x *bp)
13648 {
13649         struct vfpf_init_tlv *req = &bp->vf2pf_mbox->req.init;
13650         struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13651         int rc, i;
13652
13653         /* clear mailbox and prep first tlv */
13654         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_INIT, sizeof(*req));
13655
13656         /* status blocks */
13657         for_each_eth_queue(bp, i)
13658                 req->sb_addr[i] = (dma_addr_t)bnx2x_fp(bp, i,
13659                                                        status_blk_mapping);
13660
13661         /* statistics - requests only supports single queue for now */
13662         req->stats_addr = bp->fw_stats_data_mapping +
13663                           offsetof(struct bnx2x_fw_stats_data, queue_stats);
13664
13665         /* add list termination tlv */
13666         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13667                       sizeof(struct channel_list_end_tlv));
13668
13669         /* output tlvs list */
13670         bnx2x_dp_tlv_list(bp, req);
13671
13672         rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13673         if (rc)
13674                 return rc;
13675
13676         if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13677                 BNX2X_ERR("INIT VF failed: %d. Breaking...\n",
13678                           resp->hdr.status);
13679                 return -EAGAIN;
13680         }
13681
13682         DP(BNX2X_MSG_SP, "INIT VF Succeeded\n");
13683         return 0;
13684 }
13685
13686 /* CLOSE VF - opposite to INIT_VF */
13687 void bnx2x_vfpf_close_vf(struct bnx2x *bp)
13688 {
13689         struct vfpf_close_tlv *req = &bp->vf2pf_mbox->req.close;
13690         struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13691         int i, rc;
13692         u32 vf_id;
13693
13694         /* If we haven't got a valid VF id, there is no sense to
13695          * continue with sending messages
13696          */
13697         if (bnx2x_get_vf_id(bp, &vf_id))
13698                 goto free_irq;
13699
13700         /* Close the queues */
13701         for_each_queue(bp, i)
13702                 bnx2x_vfpf_teardown_queue(bp, i);
13703
13704         /* clear mailbox and prep first tlv */
13705         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_CLOSE, sizeof(*req));
13706
13707         req->vf_id = vf_id;
13708
13709         /* add list termination tlv */
13710         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13711                       sizeof(struct channel_list_end_tlv));
13712
13713         /* output tlvs list */
13714         bnx2x_dp_tlv_list(bp, req);
13715
13716         rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13717
13718         if (rc)
13719                 BNX2X_ERR("Sending CLOSE failed. rc was: %d\n", rc);
13720
13721         else if (resp->hdr.status != PFVF_STATUS_SUCCESS)
13722                 BNX2X_ERR("Sending CLOSE failed: pf response was %d\n",
13723                           resp->hdr.status);
13724
13725 free_irq:
13726         /* Disable HW interrupts, NAPI */
13727         bnx2x_netif_stop(bp, 0);
13728         /* Delete all NAPI objects */
13729         bnx2x_del_all_napi(bp);
13730
13731         /* Release IRQs */
13732         bnx2x_free_irq(bp);
13733 }
13734
13735 /* ask the pf to open a queue for the vf */
13736 int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx)
13737 {
13738         struct vfpf_setup_q_tlv *req = &bp->vf2pf_mbox->req.setup_q;
13739         struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13740         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
13741         u16 tpa_agg_size = 0, flags = 0;
13742         int rc;
13743
13744         /* clear mailbox and prep first tlv */
13745         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SETUP_Q, sizeof(*req));
13746
13747         /* select tpa mode to request */
13748         if (!fp->disable_tpa) {
13749                 flags |= VFPF_QUEUE_FLG_TPA;
13750                 flags |= VFPF_QUEUE_FLG_TPA_IPV6;
13751                 if (fp->mode == TPA_MODE_GRO)
13752                         flags |= VFPF_QUEUE_FLG_TPA_GRO;
13753                 tpa_agg_size = TPA_AGG_SIZE;
13754         }
13755
13756         /* calculate queue flags */
13757         flags |= VFPF_QUEUE_FLG_STATS;
13758         flags |= VFPF_QUEUE_FLG_CACHE_ALIGN;
13759         flags |= IS_MF_SD(bp) ? VFPF_QUEUE_FLG_OV : 0;
13760         flags |= VFPF_QUEUE_FLG_VLAN;
13761         DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
13762
13763         /* Common */
13764         req->vf_qid = fp_idx;
13765         req->param_valid = VFPF_RXQ_VALID | VFPF_TXQ_VALID;
13766
13767         /* Rx */
13768         req->rxq.rcq_addr = fp->rx_comp_mapping;
13769         req->rxq.rcq_np_addr = fp->rx_comp_mapping + BCM_PAGE_SIZE;
13770         req->rxq.rxq_addr = fp->rx_desc_mapping;
13771         req->rxq.sge_addr = fp->rx_sge_mapping;
13772         req->rxq.vf_sb = fp_idx;
13773         req->rxq.sb_index = HC_INDEX_ETH_RX_CQ_CONS;
13774         req->rxq.hc_rate = bp->rx_ticks ? 1000000/bp->rx_ticks : 0;
13775         req->rxq.mtu = bp->dev->mtu;
13776         req->rxq.buf_sz = fp->rx_buf_size;
13777         req->rxq.sge_buf_sz = BCM_PAGE_SIZE * PAGES_PER_SGE;
13778         req->rxq.tpa_agg_sz = tpa_agg_size;
13779         req->rxq.max_sge_pkt = SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT;
13780         req->rxq.max_sge_pkt = ((req->rxq.max_sge_pkt + PAGES_PER_SGE - 1) &
13781                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
13782         req->rxq.flags = flags;
13783         req->rxq.drop_flags = 0;
13784         req->rxq.cache_line_log = BNX2X_RX_ALIGN_SHIFT;
13785         req->rxq.stat_id = -1; /* No stats at the moment */
13786
13787         /* Tx */
13788         req->txq.txq_addr = fp->txdata_ptr[FIRST_TX_COS_INDEX]->tx_desc_mapping;
13789         req->txq.vf_sb = fp_idx;
13790         req->txq.sb_index = HC_INDEX_ETH_TX_CQ_CONS_COS0;
13791         req->txq.hc_rate = bp->tx_ticks ? 1000000/bp->tx_ticks : 0;
13792         req->txq.flags = flags;
13793         req->txq.traffic_type = LLFC_TRAFFIC_TYPE_NW;
13794
13795         /* add list termination tlv */
13796         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13797                       sizeof(struct channel_list_end_tlv));
13798
13799         /* output tlvs list */
13800         bnx2x_dp_tlv_list(bp, req);
13801
13802         rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13803         if (rc)
13804                 BNX2X_ERR("Sending SETUP_Q message for queue[%d] failed!\n",
13805                           fp_idx);
13806
13807         if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13808                 BNX2X_ERR("Status of SETUP_Q for queue[%d] is %d\n",
13809                           fp_idx, resp->hdr.status);
13810                 return -EINVAL;
13811         }
13812         return rc;
13813 }
13814
13815 int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx)
13816 {
13817         struct vfpf_q_op_tlv *req = &bp->vf2pf_mbox->req.q_op;
13818         struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13819         int rc;
13820
13821         /* clear mailbox and prep first tlv */
13822         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_TEARDOWN_Q,
13823                         sizeof(*req));
13824
13825         req->vf_qid = qidx;
13826
13827         /* add list termination tlv */
13828         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13829                       sizeof(struct channel_list_end_tlv));
13830
13831         /* output tlvs list */
13832         bnx2x_dp_tlv_list(bp, req);
13833
13834         rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13835
13836         if (rc) {
13837                 BNX2X_ERR("Sending TEARDOWN for queue %d failed: %d\n", qidx,
13838                           rc);
13839                 return rc;
13840         }
13841
13842         /* PF failed the transaction */
13843         if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13844                 BNX2X_ERR("TEARDOWN for queue %d failed: %d\n", qidx,
13845                           resp->hdr.status);
13846                 return -EINVAL;
13847         }
13848
13849         return 0;
13850 }
13851
13852 /* request pf to add a mac for the vf */
13853 int bnx2x_vfpf_set_mac(struct bnx2x *bp)
13854 {
13855         struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13856         struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13857         int rc;
13858
13859         /* clear mailbox and prep first tlv */
13860         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13861                         sizeof(*req));
13862
13863         req->flags = VFPF_SET_Q_FILTERS_MAC_VLAN_CHANGED;
13864         req->vf_qid = 0;
13865         req->n_mac_vlan_filters = 1;
13866         req->filters[0].flags =
13867                 VFPF_Q_FILTER_DEST_MAC_VALID | VFPF_Q_FILTER_SET_MAC;
13868
13869         /* sample bulletin board for new mac */
13870         bnx2x_sample_bulletin(bp);
13871
13872         /* copy mac from device to request */
13873         memcpy(req->filters[0].mac, bp->dev->dev_addr, ETH_ALEN);
13874
13875         /* add list termination tlv */
13876         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13877                       sizeof(struct channel_list_end_tlv));
13878
13879         /* output tlvs list */
13880         bnx2x_dp_tlv_list(bp, req);
13881
13882         /* send message to pf */
13883         rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13884         if (rc) {
13885                 BNX2X_ERR("failed to send message to pf. rc was %d\n", rc);
13886                 return rc;
13887         }
13888
13889         /* failure may mean PF was configured with a new mac for us */
13890         while (resp->hdr.status == PFVF_STATUS_FAILURE) {
13891                 DP(BNX2X_MSG_IOV,
13892                    "vfpf SET MAC failed. Check bulletin board for new posts\n");
13893
13894                 /* check if bulletin board was updated */
13895                 if (bnx2x_sample_bulletin(bp) == PFVF_BULLETIN_UPDATED) {
13896                         /* copy mac from device to request */
13897                         memcpy(req->filters[0].mac, bp->dev->dev_addr,
13898                                ETH_ALEN);
13899
13900                         /* send message to pf */
13901                         rc = bnx2x_send_msg2pf(bp, &resp->hdr.status,
13902                                                bp->vf2pf_mbox_mapping);
13903                 } else {
13904                         /* no new info in bulletin */
13905                         break;
13906                 }
13907         }
13908
13909         if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13910                 BNX2X_ERR("vfpf SET MAC failed: %d\n", resp->hdr.status);
13911                 return -EINVAL;
13912         }
13913
13914         return 0;
13915 }
13916
13917 int bnx2x_vfpf_set_mcast(struct net_device *dev)
13918 {
13919         struct bnx2x *bp = netdev_priv(dev);
13920         struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13921         struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13922         int rc, i = 0;
13923         struct netdev_hw_addr *ha;
13924
13925         if (bp->state != BNX2X_STATE_OPEN) {
13926                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
13927                 return -EINVAL;
13928         }
13929
13930         /* clear mailbox and prep first tlv */
13931         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13932                         sizeof(*req));
13933
13934         /* Get Rx mode requested */
13935         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
13936
13937         netdev_for_each_mc_addr(ha, dev) {
13938                 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
13939                    bnx2x_mc_addr(ha));
13940                 memcpy(req->multicast[i], bnx2x_mc_addr(ha), ETH_ALEN);
13941                 i++;
13942         }
13943
13944         /* We support four PFVF_MAX_MULTICAST_PER_VF mcast
13945          * addresses tops
13946          */
13947         if (i >= PFVF_MAX_MULTICAST_PER_VF) {
13948                 DP(NETIF_MSG_IFUP,
13949                    "VF supports not more than %d multicast MAC addresses\n",
13950                    PFVF_MAX_MULTICAST_PER_VF);
13951                 return -EINVAL;
13952         }
13953
13954         req->n_multicast = i;
13955         req->flags |= VFPF_SET_Q_FILTERS_MULTICAST_CHANGED;
13956         req->vf_qid = 0;
13957
13958         /* add list termination tlv */
13959         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13960                       sizeof(struct channel_list_end_tlv));
13961
13962         /* output tlvs list */
13963         bnx2x_dp_tlv_list(bp, req);
13964
13965         rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13966         if (rc) {
13967                 BNX2X_ERR("Sending a message failed: %d\n", rc);
13968                 return rc;
13969         }
13970
13971         if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
13972                 BNX2X_ERR("Set Rx mode/multicast failed: %d\n",
13973                           resp->hdr.status);
13974                 return -EINVAL;
13975         }
13976
13977         return 0;
13978 }
13979
13980 int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp)
13981 {
13982         int mode = bp->rx_mode;
13983         struct vfpf_set_q_filters_tlv *req = &bp->vf2pf_mbox->req.set_q_filters;
13984         struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13985         int rc;
13986
13987         /* clear mailbox and prep first tlv */
13988         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_SET_Q_FILTERS,
13989                         sizeof(*req));
13990
13991         DP(NETIF_MSG_IFUP, "Rx mode is %d\n", mode);
13992
13993         switch (mode) {
13994         case BNX2X_RX_MODE_NONE: /* no Rx */
13995                 req->rx_mask = VFPF_RX_MASK_ACCEPT_NONE;
13996                 break;
13997         case BNX2X_RX_MODE_NORMAL:
13998                 req->rx_mask = VFPF_RX_MASK_ACCEPT_MATCHED_MULTICAST;
13999                 req->rx_mask |= VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST;
14000                 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
14001                 break;
14002         case BNX2X_RX_MODE_ALLMULTI:
14003                 req->rx_mask = VFPF_RX_MASK_ACCEPT_ALL_MULTICAST;
14004                 req->rx_mask |= VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST;
14005                 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
14006                 break;
14007         case BNX2X_RX_MODE_PROMISC:
14008                 req->rx_mask = VFPF_RX_MASK_ACCEPT_ALL_UNICAST;
14009                 req->rx_mask |= VFPF_RX_MASK_ACCEPT_ALL_MULTICAST;
14010                 req->rx_mask |= VFPF_RX_MASK_ACCEPT_BROADCAST;
14011                 break;
14012         default:
14013                 BNX2X_ERR("BAD rx mode (%d)\n", mode);
14014                 return -EINVAL;
14015         }
14016
14017         req->flags |= VFPF_SET_Q_FILTERS_RX_MASK_CHANGED;
14018         req->vf_qid = 0;
14019
14020         /* add list termination tlv */
14021         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
14022                       sizeof(struct channel_list_end_tlv));
14023
14024         /* output tlvs list */
14025         bnx2x_dp_tlv_list(bp, req);
14026
14027         rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
14028         if (rc)
14029                 BNX2X_ERR("Sending a message failed: %d\n", rc);
14030
14031         if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
14032                 BNX2X_ERR("Set Rx mode failed: %d\n", resp->hdr.status);
14033                 return -EINVAL;
14034         }
14035
14036         return rc;
14037 }