Pileus Git - ~andy/linux/blob - drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_vfpf.h"
  63 #include "bnx2x_dcb.h"
  64 #include "bnx2x_sp.h"
  65
  66 #include <linux/firmware.h>
  67 #include "bnx2x_fw_file_hdr.h"
  68 /* FW files */
  69 #define FW_FILE_VERSION                                 \
  70         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  71         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  73         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  74 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  75 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  77
  78 /* Time in jiffies before concluding the transmitter is hung */
  79 #define TX_TIMEOUT              (5*HZ)
  80
  81 static char version[] =
  82         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  83         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  84
  85 MODULE_AUTHOR("Eliezer Tamir");
  86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  87                    "BCM57710/57711/57711E/"
  88                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  89                    "57840/57840_MF Driver");
  90 MODULE_LICENSE("GPL");
  91 MODULE_VERSION(DRV_MODULE_VERSION);
  92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  95
  96 int num_queues;
  97 module_param(num_queues, int, 0);
  98 MODULE_PARM_DESC(num_queues,
  99                  " Set number of queues (default is as a number of CPUs)");
 100
 101 static int disable_tpa;
 102 module_param(disable_tpa, int, 0);
 103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 104
 105 int int_mode;
 106 module_param(int_mode, int, 0);
 107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 108                                 "(1 INT#x; 2 MSI)");
 109
 110 static int dropless_fc;
 111 module_param(dropless_fc, int, 0);
 112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 113
 114 static int mrrs = -1;
 115 module_param(mrrs, int, 0);
 116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 117
 118 static int debug;
 119 module_param(debug, int, 0);
 120 MODULE_PARM_DESC(debug, " Default debug msglevel");
 121
 122 struct workqueue_struct *bnx2x_wq;
 123
 124 struct bnx2x_mac_vals {
 125         u32 xmac_addr;
 126         u32 xmac_val;
 127         u32 emac_addr;
 128         u32 emac_val;
 129         u32 umac_addr;
 130         u32 umac_val;
 131         u32 bmac_addr;
 132         u32 bmac_val[2];
 133 };
 134
 135 enum bnx2x_board_type {
 136         BCM57710 = 0,
 137         BCM57711,
 138         BCM57711E,
 139         BCM57712,
 140         BCM57712_MF,
 141         BCM57712_VF,
 142         BCM57800,
 143         BCM57800_MF,
 144         BCM57800_VF,
 145         BCM57810,
 146         BCM57810_MF,
 147         BCM57810_VF,
 148         BCM57840_4_10,
 149         BCM57840_2_20,
 150         BCM57840_MF,
 151         BCM57840_VF,
 152         BCM57811,
 153         BCM57811_MF,
 154         BCM57840_O,
 155         BCM57840_MFO,
 156         BCM57811_VF
 157 };
 158
 159 /* indexed by board_type, above */
 160 static struct {
 161         char *name;
 162 } board_info[] = {
 163         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 164         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 165         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 166         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 167         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 168         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 169         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 170         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 171         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 173         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 174         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 175         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 176         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 177         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 178         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 179         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 180         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 181         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 182         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 183         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 184 };
 185
 186 #ifndef PCI_DEVICE_ID_NX2_57710
 187 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 188 #endif
 189 #ifndef PCI_DEVICE_ID_NX2_57711
 190 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57711E
 193 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57712
 196 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 199 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 202 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57800
 205 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 208 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 211 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57810
 214 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 217 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57840_O
 220 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 223 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 226 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 229 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 230 #endif
 231 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 232 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 233 #endif
 234 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 235 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 236 #endif
 237 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 238 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 239 #endif
 240 #ifndef PCI_DEVICE_ID_NX2_57811
 241 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 242 #endif
 243 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 244 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 245 #endif
 246 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 247 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 248 #endif
 249
 250 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 251         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 272         { 0 }
 273 };
 274
 275 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 276
 277 /* Global resources for unloading a previously loaded device */
 278 #define BNX2X_PREV_WAIT_NEEDED 1
 279 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 280 static LIST_HEAD(bnx2x_prev_list);
 281 /****************************************************************************
 282 * General service functions
 283 ****************************************************************************/
 284
 285 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 286                                        u32 addr, dma_addr_t mapping)
 287 {
 288         REG_WR(bp,  addr, U64_LO(mapping));
 289         REG_WR(bp,  addr + 4, U64_HI(mapping));
 290 }
 291
 292 static void storm_memset_spq_addr(struct bnx2x *bp,
 293                                   dma_addr_t mapping, u16 abs_fid)
 294 {
 295         u32 addr = XSEM_REG_FAST_MEMORY +
 296                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 297
 298         __storm_memset_dma_mapping(bp, addr, mapping);
 299 }
 300
 301 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 302                                   u16 pf_id)
 303 {
 304         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 305                 pf_id);
 306         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 307                 pf_id);
 308         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 309                 pf_id);
 310         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 311                 pf_id);
 312 }
 313
 314 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 315                                  u8 enable)
 316 {
 317         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 318                 enable);
 319         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 320                 enable);
 321         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 322                 enable);
 323         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 324                 enable);
 325 }
 326
 327 static void storm_memset_eq_data(struct bnx2x *bp,
 328                                  struct event_ring_data *eq_data,
 329                                 u16 pfid)
 330 {
 331         size_t size = sizeof(struct event_ring_data);
 332
 333         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 334
 335         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 336 }
 337
 338 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 339                                  u16 pfid)
 340 {
 341         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 342         REG_WR16(bp, addr, eq_prod);
 343 }
 344
 345 /* used only at init
 346  * locking is done by mcp
 347  */
 348 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 349 {
 350         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 351         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 352         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 353                                PCICFG_VENDOR_ID_OFFSET);
 354 }
 355
 356 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 357 {
 358         u32 val;
 359
 360         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 361         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 363                                PCICFG_VENDOR_ID_OFFSET);
 364
 365         return val;
 366 }
 367
 368 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 369 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 370 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 371 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 372 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 373
 374 static void bnx2x_dp_dmae(struct bnx2x *bp,
 375                           struct dmae_command *dmae, int msglvl)
 376 {
 377         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 378         int i;
 379
 380         switch (dmae->opcode & DMAE_COMMAND_DST) {
 381         case DMAE_CMD_DST_PCI:
 382                 if (src_type == DMAE_CMD_SRC_PCI)
 383                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 384                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 385                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 386                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 387                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 388                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 389                            dmae->comp_val);
 390                 else
 391                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 392                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 393                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 394                            dmae->opcode, dmae->src_addr_lo >> 2,
 395                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 396                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 397                            dmae->comp_val);
 398                 break;
 399         case DMAE_CMD_DST_GRC:
 400                 if (src_type == DMAE_CMD_SRC_PCI)
 401                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 402                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 403                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 404                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 405                            dmae->len, dmae->dst_addr_lo >> 2,
 406                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 407                            dmae->comp_val);
 408                 else
 409                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 410                            "src [%08x], len [%d*4], dst [%08x]\n"
 411                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 412                            dmae->opcode, dmae->src_addr_lo >> 2,
 413                            dmae->len, dmae->dst_addr_lo >> 2,
 414                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 415                            dmae->comp_val);
 416                 break;
 417         default:
 418                 if (src_type == DMAE_CMD_SRC_PCI)
 419                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 420                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 421                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 422                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 423                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 424                            dmae->comp_val);
 425                 else
 426                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 427                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 428                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 429                            dmae->opcode, dmae->src_addr_lo >> 2,
 430                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 431                            dmae->comp_val);
 432                 break;
 433         }
 434
 435         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 436                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 437                    i, *(((u32 *)dmae) + i));
 438 }
 439
 440 /* copy command into DMAE command memory and set DMAE command go */
 441 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 442 {
 443         u32 cmd_offset;
 444         int i;
 445
 446         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 447         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 448                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 449         }
 450         REG_WR(bp, dmae_reg_go_c[idx], 1);
 451 }
 452
 453 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 454 {
 455         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 456                            DMAE_CMD_C_ENABLE);
 457 }
 458
 459 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 460 {
 461         return opcode & ~DMAE_CMD_SRC_RESET;
 462 }
 463
 464 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 465                              bool with_comp, u8 comp_type)
 466 {
 467         u32 opcode = 0;
 468
 469         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 470                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 471
 472         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 473
 474         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 475         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 476                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 477         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 478
 479 #ifdef __BIG_ENDIAN
 480         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 481 #else
 482         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 483 #endif
 484         if (with_comp)
 485                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 486         return opcode;
 487 }
 488
 489 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 490                                       struct dmae_command *dmae,
 491                                       u8 src_type, u8 dst_type)
 492 {
 493         memset(dmae, 0, sizeof(struct dmae_command));
 494
 495         /* set the opcode */
 496         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 497                                          true, DMAE_COMP_PCI);
 498
 499         /* fill in the completion parameters */
 500         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 501         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 502         dmae->comp_val = DMAE_COMP_VAL;
 503 }
 504
 505 /* issue a dmae command over the init-channel and wait for completion */
 506 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
 507 {
 508         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 509         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 510         int rc = 0;
 511
 512         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 513
 514         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 515          * as long as this code is called both from syscall context and
 516          * from ndo_set_rx_mode() flow that may be called from BH.
 517          */
 518         spin_lock_bh(&bp->dmae_lock);
 519
 520         /* reset completion */
 521         *wb_comp = 0;
 522
 523         /* post the command on the channel used for initializations */
 524         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 525
 526         /* wait for completion */
 527         udelay(5);
 528         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 529
 530                 if (!cnt ||
 531                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 532                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 533                         BNX2X_ERR("DMAE timeout!\n");
 534                         rc = DMAE_TIMEOUT;
 535                         goto unlock;
 536                 }
 537                 cnt--;
 538                 udelay(50);
 539         }
 540         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 541                 BNX2X_ERR("DMAE PCI error!\n");
 542                 rc = DMAE_PCI_ERROR;
 543         }
 544
 545 unlock:
 546         spin_unlock_bh(&bp->dmae_lock);
 547         return rc;
 548 }
 549
 550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 551                       u32 len32)
 552 {
 553         int rc;
 554         struct dmae_command dmae;
 555
 556         if (!bp->dmae_ready) {
 557                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 558
 559                 if (CHIP_IS_E1(bp))
 560                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 561                 else
 562                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 563                 return;
 564         }
 565
 566         /* set opcode and fixed command fields */
 567         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 568
 569         /* fill in addresses and len */
 570         dmae.src_addr_lo = U64_LO(dma_addr);
 571         dmae.src_addr_hi = U64_HI(dma_addr);
 572         dmae.dst_addr_lo = dst_addr >> 2;
 573         dmae.dst_addr_hi = 0;
 574         dmae.len = len32;
 575
 576         /* issue the command and wait for completion */
 577         rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
 578         if (rc) {
 579                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 580                 bnx2x_panic();
 581         }
 582 }
 583
 584 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 585 {
 586         int rc;
 587         struct dmae_command dmae;
 588
 589         if (!bp->dmae_ready) {
 590                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 591                 int i;
 592
 593                 if (CHIP_IS_E1(bp))
 594                         for (i = 0; i < len32; i++)
 595                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 596                 else
 597                         for (i = 0; i < len32; i++)
 598                                 data[i] = REG_RD(bp, src_addr + i*4);
 599
 600                 return;
 601         }
 602
 603         /* set opcode and fixed command fields */
 604         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 605
 606         /* fill in addresses and len */
 607         dmae.src_addr_lo = src_addr >> 2;
 608         dmae.src_addr_hi = 0;
 609         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 610         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 611         dmae.len = len32;
 612
 613         /* issue the command and wait for completion */
 614         rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
 615         if (rc) {
 616                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 617                 bnx2x_panic();
 618         };
 619 }
 620
 621 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 622                                       u32 addr, u32 len)
 623 {
 624         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 625         int offset = 0;
 626
 627         while (len > dmae_wr_max) {
 628                 bnx2x_write_dmae(bp, phys_addr + offset,
 629                                  addr + offset, dmae_wr_max);
 630                 offset += dmae_wr_max * 4;
 631                 len -= dmae_wr_max;
 632         }
 633
 634         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 635 }
 636
 637 static int bnx2x_mc_assert(struct bnx2x *bp)
 638 {
 639         char last_idx;
 640         int i, rc = 0;
 641         u32 row0, row1, row2, row3;
 642
 643         /* XSTORM */
 644         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 645                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 646         if (last_idx)
 647                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 648
 649         /* print the asserts */
 650         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 651
 652                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 653                               XSTORM_ASSERT_LIST_OFFSET(i));
 654                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 655                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 656                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 657                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 658                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 659                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 660
 661                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 662                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 663                                   i, row3, row2, row1, row0);
 664                         rc++;
 665                 } else {
 666                         break;
 667                 }
 668         }
 669
 670         /* TSTORM */
 671         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 672                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 673         if (last_idx)
 674                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 675
 676         /* print the asserts */
 677         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 678
 679                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 680                               TSTORM_ASSERT_LIST_OFFSET(i));
 681                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 682                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 683                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 684                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 685                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 686                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 687
 688                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 689                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 690                                   i, row3, row2, row1, row0);
 691                         rc++;
 692                 } else {
 693                         break;
 694                 }
 695         }
 696
 697         /* CSTORM */
 698         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 699                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 700         if (last_idx)
 701                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 702
 703         /* print the asserts */
 704         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 705
 706                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 707                               CSTORM_ASSERT_LIST_OFFSET(i));
 708                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 709                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 710                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 711                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 712                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 713                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 714
 715                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 716                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 717                                   i, row3, row2, row1, row0);
 718                         rc++;
 719                 } else {
 720                         break;
 721                 }
 722         }
 723
 724         /* USTORM */
 725         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 726                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 727         if (last_idx)
 728                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 729
 730         /* print the asserts */
 731         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 732
 733                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 734                               USTORM_ASSERT_LIST_OFFSET(i));
 735                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 736                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 737                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 738                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 739                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 740                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 741
 742                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 743                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 744                                   i, row3, row2, row1, row0);
 745                         rc++;
 746                 } else {
 747                         break;
 748                 }
 749         }
 750
 751         return rc;
 752 }
 753
 754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 755 {
 756         u32 addr, val;
 757         u32 mark, offset;
 758         __be32 data[9];
 759         int word;
 760         u32 trace_shmem_base;
 761         if (BP_NOMCP(bp)) {
 762                 BNX2X_ERR("NO MCP - can not dump\n");
 763                 return;
 764         }
 765         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 766                 (bp->common.bc_ver & 0xff0000) >> 16,
 767                 (bp->common.bc_ver & 0xff00) >> 8,
 768                 (bp->common.bc_ver & 0xff));
 769
 770         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 771         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 772                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 773
 774         if (BP_PATH(bp) == 0)
 775                 trace_shmem_base = bp->common.shmem_base;
 776         else
 777                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 778         addr = trace_shmem_base - 0x800;
 779
 780         /* validate TRCB signature */
 781         mark = REG_RD(bp, addr);
 782         if (mark != MFW_TRACE_SIGNATURE) {
 783                 BNX2X_ERR("Trace buffer signature is missing.");
 784                 return ;
 785         }
 786
 787         /* read cyclic buffer pointer */
 788         addr += 4;
 789         mark = REG_RD(bp, addr);
 790         mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
 791                         + ((mark + 0x3) & ~0x3) - 0x08000000;
 792         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 793
 794         printk("%s", lvl);
 795
 796         /* dump buffer after the mark */
 797         for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
 798                 for (word = 0; word < 8; word++)
 799                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 800                 data[8] = 0x0;
 801                 pr_cont("%s", (char *)data);
 802         }
 803
 804         /* dump buffer before the mark */
 805         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 806                 for (word = 0; word < 8; word++)
 807                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 808                 data[8] = 0x0;
 809                 pr_cont("%s", (char *)data);
 810         }
 811         printk("%s" "end of fw dump\n", lvl);
 812 }
 813
 814 static void bnx2x_fw_dump(struct bnx2x *bp)
 815 {
 816         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 817 }
 818
 819 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 820 {
 821         int port = BP_PORT(bp);
 822         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 823         u32 val = REG_RD(bp, addr);
 824
 825         /* in E1 we must use only PCI configuration space to disable
 826          * MSI/MSIX capability
 827          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 828          */
 829         if (CHIP_IS_E1(bp)) {
 830                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 831                  * Use mask register to prevent from HC sending interrupts
 832                  * after we exit the function
 833                  */
 834                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 835
 836                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 837                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 838                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 839         } else
 840                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 841                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 842                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 843                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 844
 845         DP(NETIF_MSG_IFDOWN,
 846            "write %x to HC %d (addr 0x%x)\n",
 847            val, port, addr);
 848
 849         /* flush all outstanding writes */
 850         mmiowb();
 851
 852         REG_WR(bp, addr, val);
 853         if (REG_RD(bp, addr) != val)
 854                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 855 }
 856
 857 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 858 {
 859         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 860
 861         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 862                  IGU_PF_CONF_INT_LINE_EN |
 863                  IGU_PF_CONF_ATTN_BIT_EN);
 864
 865         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 866
 867         /* flush all outstanding writes */
 868         mmiowb();
 869
 870         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 871         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 872                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 873 }
 874
 875 static void bnx2x_int_disable(struct bnx2x *bp)
 876 {
 877         if (bp->common.int_block == INT_BLOCK_HC)
 878                 bnx2x_hc_int_disable(bp);
 879         else
 880                 bnx2x_igu_int_disable(bp);
 881 }
 882
 883 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 884 {
 885         int i;
 886         u16 j;
 887         struct hc_sp_status_block_data sp_sb_data;
 888         int func = BP_FUNC(bp);
 889 #ifdef BNX2X_STOP_ON_ERROR
 890         u16 start = 0, end = 0;
 891         u8 cos;
 892 #endif
 893         if (disable_int)
 894                 bnx2x_int_disable(bp);
 895
 896         bp->stats_state = STATS_STATE_DISABLED;
 897         bp->eth_stats.unrecoverable_error++;
 898         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 899
 900         BNX2X_ERR("begin crash dump -----------------\n");
 901
 902         /* Indices */
 903         /* Common */
 904         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 905                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 906                   bp->spq_prod_idx, bp->stats_counter);
 907         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 908                   bp->def_status_blk->atten_status_block.attn_bits,
 909                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 910                   bp->def_status_blk->atten_status_block.status_block_id,
 911                   bp->def_status_blk->atten_status_block.attn_bits_index);
 912         BNX2X_ERR("     def (");
 913         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 914                 pr_cont("0x%x%s",
 915                         bp->def_status_blk->sp_sb.index_values[i],
 916                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 917
 918         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 919                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 920                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 921                         i*sizeof(u32));
 922
 923         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 924                sp_sb_data.igu_sb_id,
 925                sp_sb_data.igu_seg_id,
 926                sp_sb_data.p_func.pf_id,
 927                sp_sb_data.p_func.vnic_id,
 928                sp_sb_data.p_func.vf_id,
 929                sp_sb_data.p_func.vf_valid,
 930                sp_sb_data.state);
 931
 932         for_each_eth_queue(bp, i) {
 933                 struct bnx2x_fastpath *fp = &bp->fp[i];
 934                 int loop;
 935                 struct hc_status_block_data_e2 sb_data_e2;
 936                 struct hc_status_block_data_e1x sb_data_e1x;
 937                 struct hc_status_block_sm  *hc_sm_p =
 938                         CHIP_IS_E1x(bp) ?
 939                         sb_data_e1x.common.state_machine :
 940                         sb_data_e2.common.state_machine;
 941                 struct hc_index_data *hc_index_p =
 942                         CHIP_IS_E1x(bp) ?
 943                         sb_data_e1x.index_data :
 944                         sb_data_e2.index_data;
 945                 u8 data_size, cos;
 946                 u32 *sb_data_p;
 947                 struct bnx2x_fp_txdata txdata;
 948
 949                 /* Rx */
 950                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 951                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 952                           fp->rx_comp_prod,
 953                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 954                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 955                           fp->rx_sge_prod, fp->last_max_sge,
 956                           le16_to_cpu(fp->fp_hc_idx));
 957
 958                 /* Tx */
 959                 for_each_cos_in_tx_queue(fp, cos)
 960                 {
 961                         txdata = *fp->txdata_ptr[cos];
 962                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 963                                   i, txdata.tx_pkt_prod,
 964                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 965                                   txdata.tx_bd_cons,
 966                                   le16_to_cpu(*txdata.tx_cons_sb));
 967                 }
 968
 969                 loop = CHIP_IS_E1x(bp) ?
 970                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 971
 972                 /* host sb data */
 973
 974                 if (IS_FCOE_FP(fp))
 975                         continue;
 976
 977                 BNX2X_ERR("     run indexes (");
 978                 for (j = 0; j < HC_SB_MAX_SM; j++)
 979                         pr_cont("0x%x%s",
 980                                fp->sb_running_index[j],
 981                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 982
 983                 BNX2X_ERR("     indexes (");
 984                 for (j = 0; j < loop; j++)
 985                         pr_cont("0x%x%s",
 986                                fp->sb_index_values[j],
 987                                (j == loop - 1) ? ")" : " ");
 988                 /* fw sb data */
 989                 data_size = CHIP_IS_E1x(bp) ?
 990                         sizeof(struct hc_status_block_data_e1x) :
 991                         sizeof(struct hc_status_block_data_e2);
 992                 data_size /= sizeof(u32);
 993                 sb_data_p = CHIP_IS_E1x(bp) ?
 994                         (u32 *)&sb_data_e1x :
 995                         (u32 *)&sb_data_e2;
 996                 /* copy sb data in here */
 997                 for (j = 0; j < data_size; j++)
 998                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 999                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1000                                 j * sizeof(u32));
1001
1002                 if (!CHIP_IS_E1x(bp)) {
1003                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1004                                 sb_data_e2.common.p_func.pf_id,
1005                                 sb_data_e2.common.p_func.vf_id,
1006                                 sb_data_e2.common.p_func.vf_valid,
1007                                 sb_data_e2.common.p_func.vnic_id,
1008                                 sb_data_e2.common.same_igu_sb_1b,
1009                                 sb_data_e2.common.state);
1010                 } else {
1011                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1012                                 sb_data_e1x.common.p_func.pf_id,
1013                                 sb_data_e1x.common.p_func.vf_id,
1014                                 sb_data_e1x.common.p_func.vf_valid,
1015                                 sb_data_e1x.common.p_func.vnic_id,
1016                                 sb_data_e1x.common.same_igu_sb_1b,
1017                                 sb_data_e1x.common.state);
1018                 }
1019
1020                 /* SB_SMs data */
1021                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1022                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1023                                 j, hc_sm_p[j].__flags,
1024                                 hc_sm_p[j].igu_sb_id,
1025                                 hc_sm_p[j].igu_seg_id,
1026                                 hc_sm_p[j].time_to_expire,
1027                                 hc_sm_p[j].timer_value);
1028                 }
1029
1030                 /* Indices data */
1031                 for (j = 0; j < loop; j++) {
1032                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1033                                hc_index_p[j].flags,
1034                                hc_index_p[j].timeout);
1035                 }
1036         }
1037
1038 #ifdef BNX2X_STOP_ON_ERROR
1039
1040         /* event queue */
1041         BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1042         for (i = 0; i < NUM_EQ_DESC; i++) {
1043                 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1044
1045                 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1046                           i, bp->eq_ring[i].message.opcode,
1047                           bp->eq_ring[i].message.error);
1048                 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1049         }
1050
1051         /* Rings */
1052         /* Rx */
1053         for_each_valid_rx_queue(bp, i) {
1054                 struct bnx2x_fastpath *fp = &bp->fp[i];
1055
1056                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1057                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1058                 for (j = start; j != end; j = RX_BD(j + 1)) {
1059                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1060                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1061
1062                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1063                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1064                 }
1065
1066                 start = RX_SGE(fp->rx_sge_prod);
1067                 end = RX_SGE(fp->last_max_sge);
1068                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1069                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1070                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1071
1072                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1073                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1074                 }
1075
1076                 start = RCQ_BD(fp->rx_comp_cons - 10);
1077                 end = RCQ_BD(fp->rx_comp_cons + 503);
1078                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1079                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1080
1081                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1082                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1083                 }
1084         }
1085
1086         /* Tx */
1087         for_each_valid_tx_queue(bp, i) {
1088                 struct bnx2x_fastpath *fp = &bp->fp[i];
1089                 for_each_cos_in_tx_queue(fp, cos) {
1090                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1091
1092                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1093                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1094                         for (j = start; j != end; j = TX_BD(j + 1)) {
1095                                 struct sw_tx_bd *sw_bd =
1096                                         &txdata->tx_buf_ring[j];
1097
1098                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1099                                           i, cos, j, sw_bd->skb,
1100                                           sw_bd->first_bd);
1101                         }
1102
1103                         start = TX_BD(txdata->tx_bd_cons - 10);
1104                         end = TX_BD(txdata->tx_bd_cons + 254);
1105                         for (j = start; j != end; j = TX_BD(j + 1)) {
1106                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1107
1108                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1109                                           i, cos, j, tx_bd[0], tx_bd[1],
1110                                           tx_bd[2], tx_bd[3]);
1111                         }
1112                 }
1113         }
1114 #endif
1115         bnx2x_fw_dump(bp);
1116         bnx2x_mc_assert(bp);
1117         BNX2X_ERR("end crash dump -----------------\n");
1118 }
1119
1120 /*
1121  * FLR Support for E2
1122  *
1123  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1124  * initialization.
1125  */
1126 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1127 #define FLR_WAIT_INTERVAL       50      /* usec */
1128 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1129
1130 struct pbf_pN_buf_regs {
1131         int pN;
1132         u32 init_crd;
1133         u32 crd;
1134         u32 crd_freed;
1135 };
1136
1137 struct pbf_pN_cmd_regs {
1138         int pN;
1139         u32 lines_occup;
1140         u32 lines_freed;
1141 };
1142
1143 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1144                                      struct pbf_pN_buf_regs *regs,
1145                                      u32 poll_count)
1146 {
1147         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1148         u32 cur_cnt = poll_count;
1149
1150         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1151         crd = crd_start = REG_RD(bp, regs->crd);
1152         init_crd = REG_RD(bp, regs->init_crd);
1153
1154         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1155         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1156         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1157
1158         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1159                (init_crd - crd_start))) {
1160                 if (cur_cnt--) {
1161                         udelay(FLR_WAIT_INTERVAL);
1162                         crd = REG_RD(bp, regs->crd);
1163                         crd_freed = REG_RD(bp, regs->crd_freed);
1164                 } else {
1165                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1166                            regs->pN);
1167                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1168                            regs->pN, crd);
1169                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1170                            regs->pN, crd_freed);
1171                         break;
1172                 }
1173         }
1174         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1175            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1176 }
1177
1178 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1179                                      struct pbf_pN_cmd_regs *regs,
1180                                      u32 poll_count)
1181 {
1182         u32 occup, to_free, freed, freed_start;
1183         u32 cur_cnt = poll_count;
1184
1185         occup = to_free = REG_RD(bp, regs->lines_occup);
1186         freed = freed_start = REG_RD(bp, regs->lines_freed);
1187
1188         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1189         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1190
1191         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1192                 if (cur_cnt--) {
1193                         udelay(FLR_WAIT_INTERVAL);
1194                         occup = REG_RD(bp, regs->lines_occup);
1195                         freed = REG_RD(bp, regs->lines_freed);
1196                 } else {
1197                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1198                            regs->pN);
1199                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1200                            regs->pN, occup);
1201                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1202                            regs->pN, freed);
1203                         break;
1204                 }
1205         }
1206         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1207            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1208 }
1209
1210 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1211                                     u32 expected, u32 poll_count)
1212 {
1213         u32 cur_cnt = poll_count;
1214         u32 val;
1215
1216         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1217                 udelay(FLR_WAIT_INTERVAL);
1218
1219         return val;
1220 }
1221
1222 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1223                                     char *msg, u32 poll_cnt)
1224 {
1225         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1226         if (val != 0) {
1227                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1228                 return 1;
1229         }
1230         return 0;
1231 }
1232
1233 /* Common routines with VF FLR cleanup */
1234 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1235 {
1236         /* adjust polling timeout */
1237         if (CHIP_REV_IS_EMUL(bp))
1238                 return FLR_POLL_CNT * 2000;
1239
1240         if (CHIP_REV_IS_FPGA(bp))
1241                 return FLR_POLL_CNT * 120;
1242
1243         return FLR_POLL_CNT;
1244 }
1245
1246 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1247 {
1248         struct pbf_pN_cmd_regs cmd_regs[] = {
1249                 {0, (CHIP_IS_E3B0(bp)) ?
1250                         PBF_REG_TQ_OCCUPANCY_Q0 :
1251                         PBF_REG_P0_TQ_OCCUPANCY,
1252                     (CHIP_IS_E3B0(bp)) ?
1253                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1254                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1255                 {1, (CHIP_IS_E3B0(bp)) ?
1256                         PBF_REG_TQ_OCCUPANCY_Q1 :
1257                         PBF_REG_P1_TQ_OCCUPANCY,
1258                     (CHIP_IS_E3B0(bp)) ?
1259                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1260                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1261                 {4, (CHIP_IS_E3B0(bp)) ?
1262                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1263                         PBF_REG_P4_TQ_OCCUPANCY,
1264                     (CHIP_IS_E3B0(bp)) ?
1265                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1266                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1267         };
1268
1269         struct pbf_pN_buf_regs buf_regs[] = {
1270                 {0, (CHIP_IS_E3B0(bp)) ?
1271                         PBF_REG_INIT_CRD_Q0 :
1272                         PBF_REG_P0_INIT_CRD ,
1273                     (CHIP_IS_E3B0(bp)) ?
1274                         PBF_REG_CREDIT_Q0 :
1275                         PBF_REG_P0_CREDIT,
1276                     (CHIP_IS_E3B0(bp)) ?
1277                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1278                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1279                 {1, (CHIP_IS_E3B0(bp)) ?
1280                         PBF_REG_INIT_CRD_Q1 :
1281                         PBF_REG_P1_INIT_CRD,
1282                     (CHIP_IS_E3B0(bp)) ?
1283                         PBF_REG_CREDIT_Q1 :
1284                         PBF_REG_P1_CREDIT,
1285                     (CHIP_IS_E3B0(bp)) ?
1286                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1287                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1288                 {4, (CHIP_IS_E3B0(bp)) ?
1289                         PBF_REG_INIT_CRD_LB_Q :
1290                         PBF_REG_P4_INIT_CRD,
1291                     (CHIP_IS_E3B0(bp)) ?
1292                         PBF_REG_CREDIT_LB_Q :
1293                         PBF_REG_P4_CREDIT,
1294                     (CHIP_IS_E3B0(bp)) ?
1295                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1296                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1297         };
1298
1299         int i;
1300
1301         /* Verify the command queues are flushed P0, P1, P4 */
1302         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1303                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1304
1305         /* Verify the transmission buffers are flushed P0, P1, P4 */
1306         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1307                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1308 }
1309
1310 #define OP_GEN_PARAM(param) \
1311         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1312
1313 #define OP_GEN_TYPE(type) \
1314         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1315
1316 #define OP_GEN_AGG_VECT(index) \
1317         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1318
1319 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1320 {
1321         u32 op_gen_command = 0;
1322         u32 comp_addr = BAR_CSTRORM_INTMEM +
1323                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1324         int ret = 0;
1325
1326         if (REG_RD(bp, comp_addr)) {
1327                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1328                 return 1;
1329         }
1330
1331         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1332         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1333         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1334         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1335
1336         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1337         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1338
1339         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1340                 BNX2X_ERR("FW final cleanup did not succeed\n");
1341                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1342                    (REG_RD(bp, comp_addr)));
1343                 bnx2x_panic();
1344                 return 1;
1345         }
1346         /* Zero completion for next FLR */
1347         REG_WR(bp, comp_addr, 0);
1348
1349         return ret;
1350 }
1351
1352 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1353 {
1354         u16 status;
1355
1356         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1357         return status & PCI_EXP_DEVSTA_TRPND;
1358 }
1359
1360 /* PF FLR specific routines
1361 */
1362 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1363 {
1364         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1365         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1366                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1367                         "CFC PF usage counter timed out",
1368                         poll_cnt))
1369                 return 1;
1370
1371         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1372         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1373                         DORQ_REG_PF_USAGE_CNT,
1374                         "DQ PF usage counter timed out",
1375                         poll_cnt))
1376                 return 1;
1377
1378         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1379         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1380                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1381                         "QM PF usage counter timed out",
1382                         poll_cnt))
1383                 return 1;
1384
1385         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1386         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1387                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1388                         "Timers VNIC usage counter timed out",
1389                         poll_cnt))
1390                 return 1;
1391         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1392                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1393                         "Timers NUM_SCANS usage counter timed out",
1394                         poll_cnt))
1395                 return 1;
1396
1397         /* Wait DMAE PF usage counter to zero */
1398         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1399                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1400                         "DMAE command register timed out",
1401                         poll_cnt))
1402                 return 1;
1403
1404         return 0;
1405 }
1406
1407 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1408 {
1409         u32 val;
1410
1411         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1412         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1413
1414         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1415         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1416
1417         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1418         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1419
1420         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1421         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1422
1423         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1424         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1425
1426         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1427         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1428
1429         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1430         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1431
1432         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1433         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1434            val);
1435 }
1436
1437 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1438 {
1439         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1440
1441         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1442
1443         /* Re-enable PF target read access */
1444         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1445
1446         /* Poll HW usage counters */
1447         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1448         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1449                 return -EBUSY;
1450
1451         /* Zero the igu 'trailing edge' and 'leading edge' */
1452
1453         /* Send the FW cleanup command */
1454         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1455                 return -EBUSY;
1456
1457         /* ATC cleanup */
1458
1459         /* Verify TX hw is flushed */
1460         bnx2x_tx_hw_flushed(bp, poll_cnt);
1461
1462         /* Wait 100ms (not adjusted according to platform) */
1463         msleep(100);
1464
1465         /* Verify no pending pci transactions */
1466         if (bnx2x_is_pcie_pending(bp->pdev))
1467                 BNX2X_ERR("PCIE Transactions still pending\n");
1468
1469         /* Debug */
1470         bnx2x_hw_enable_status(bp);
1471
1472         /*
1473          * Master enable - Due to WB DMAE writes performed before this
1474          * register is re-initialized as part of the regular function init
1475          */
1476         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1477
1478         return 0;
1479 }
1480
1481 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1482 {
1483         int port = BP_PORT(bp);
1484         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1485         u32 val = REG_RD(bp, addr);
1486         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1487         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1488         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1489
1490         if (msix) {
1491                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1492                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1493                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1494                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1495                 if (single_msix)
1496                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1497         } else if (msi) {
1498                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1499                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1500                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1501                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1502         } else {
1503                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1504                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1505                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1506                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1507
1508                 if (!CHIP_IS_E1(bp)) {
1509                         DP(NETIF_MSG_IFUP,
1510                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1511
1512                         REG_WR(bp, addr, val);
1513
1514                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1515                 }
1516         }
1517
1518         if (CHIP_IS_E1(bp))
1519                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1520
1521         DP(NETIF_MSG_IFUP,
1522            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1523            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1524
1525         REG_WR(bp, addr, val);
1526         /*
1527          * Ensure that HC_CONFIG is written before leading/trailing edge config
1528          */
1529         mmiowb();
1530         barrier();
1531
1532         if (!CHIP_IS_E1(bp)) {
1533                 /* init leading/trailing edge */
1534                 if (IS_MF(bp)) {
1535                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1536                         if (bp->port.pmf)
1537                                 /* enable nig and gpio3 attention */
1538                                 val |= 0x1100;
1539                 } else
1540                         val = 0xffff;
1541
1542                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1543                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1544         }
1545
1546         /* Make sure that interrupts are indeed enabled from here on */
1547         mmiowb();
1548 }
1549
1550 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1551 {
1552         u32 val;
1553         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1554         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1555         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1556
1557         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1558
1559         if (msix) {
1560                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1561                          IGU_PF_CONF_SINGLE_ISR_EN);
1562                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1563                         IGU_PF_CONF_ATTN_BIT_EN);
1564
1565                 if (single_msix)
1566                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1567         } else if (msi) {
1568                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1569                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1570                         IGU_PF_CONF_ATTN_BIT_EN |
1571                         IGU_PF_CONF_SINGLE_ISR_EN);
1572         } else {
1573                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1574                 val |= (IGU_PF_CONF_INT_LINE_EN |
1575                         IGU_PF_CONF_ATTN_BIT_EN |
1576                         IGU_PF_CONF_SINGLE_ISR_EN);
1577         }
1578
1579         /* Clean previous status - need to configure igu prior to ack*/
1580         if ((!msix) || single_msix) {
1581                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1582                 bnx2x_ack_int(bp);
1583         }
1584
1585         val |= IGU_PF_CONF_FUNC_EN;
1586
1587         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1588            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1589
1590         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1591
1592         if (val & IGU_PF_CONF_INT_LINE_EN)
1593                 pci_intx(bp->pdev, true);
1594
1595         barrier();
1596
1597         /* init leading/trailing edge */
1598         if (IS_MF(bp)) {
1599                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1600                 if (bp->port.pmf)
1601                         /* enable nig and gpio3 attention */
1602                         val |= 0x1100;
1603         } else
1604                 val = 0xffff;
1605
1606         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1607         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1608
1609         /* Make sure that interrupts are indeed enabled from here on */
1610         mmiowb();
1611 }
1612
1613 void bnx2x_int_enable(struct bnx2x *bp)
1614 {
1615         if (bp->common.int_block == INT_BLOCK_HC)
1616                 bnx2x_hc_int_enable(bp);
1617         else
1618                 bnx2x_igu_int_enable(bp);
1619 }
1620
1621 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1622 {
1623         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1624         int i, offset;
1625
1626         if (disable_hw)
1627                 /* prevent the HW from sending interrupts */
1628                 bnx2x_int_disable(bp);
1629
1630         /* make sure all ISRs are done */
1631         if (msix) {
1632                 synchronize_irq(bp->msix_table[0].vector);
1633                 offset = 1;
1634                 if (CNIC_SUPPORT(bp))
1635                         offset++;
1636                 for_each_eth_queue(bp, i)
1637                         synchronize_irq(bp->msix_table[offset++].vector);
1638         } else
1639                 synchronize_irq(bp->pdev->irq);
1640
1641         /* make sure sp_task is not running */
1642         cancel_delayed_work(&bp->sp_task);
1643         cancel_delayed_work(&bp->period_task);
1644         flush_workqueue(bnx2x_wq);
1645 }
1646
1647 /* fast path */
1648
1649 /*
1650  * General service functions
1651  */
1652
1653 /* Return true if succeeded to acquire the lock */
1654 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1655 {
1656         u32 lock_status;
1657         u32 resource_bit = (1 << resource);
1658         int func = BP_FUNC(bp);
1659         u32 hw_lock_control_reg;
1660
1661         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1662            "Trying to take a lock on resource %d\n", resource);
1663
1664         /* Validating that the resource is within range */
1665         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1666                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1667                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1668                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1669                 return false;
1670         }
1671
1672         if (func <= 5)
1673                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1674         else
1675                 hw_lock_control_reg =
1676                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1677
1678         /* Try to acquire the lock */
1679         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1680         lock_status = REG_RD(bp, hw_lock_control_reg);
1681         if (lock_status & resource_bit)
1682                 return true;
1683
1684         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1685            "Failed to get a lock on resource %d\n", resource);
1686         return false;
1687 }
1688
1689 /**
1690  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1691  *
1692  * @bp: driver handle
1693  *
1694  * Returns the recovery leader resource id according to the engine this function
1695  * belongs to. Currently only only 2 engines is supported.
1696  */
1697 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1698 {
1699         if (BP_PATH(bp))
1700                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1701         else
1702                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1703 }
1704
1705 /**
1706  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1707  *
1708  * @bp: driver handle
1709  *
1710  * Tries to acquire a leader lock for current engine.
1711  */
1712 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1713 {
1714         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1715 }
1716
1717 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1718
1719 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1720 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1721 {
1722         /* Set the interrupt occurred bit for the sp-task to recognize it
1723          * must ack the interrupt and transition according to the IGU
1724          * state machine.
1725          */
1726         atomic_set(&bp->interrupt_occurred, 1);
1727
1728         /* The sp_task must execute only after this bit
1729          * is set, otherwise we will get out of sync and miss all
1730          * further interrupts. Hence, the barrier.
1731          */
1732         smp_wmb();
1733
1734         /* schedule sp_task to workqueue */
1735         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1736 }
1737
1738 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1739 {
1740         struct bnx2x *bp = fp->bp;
1741         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1742         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1743         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1744         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1745
1746         DP(BNX2X_MSG_SP,
1747            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1748            fp->index, cid, command, bp->state,
1749            rr_cqe->ramrod_cqe.ramrod_type);
1750
1751         /* If cid is within VF range, replace the slowpath object with the
1752          * one corresponding to this VF
1753          */
1754         if (cid >= BNX2X_FIRST_VF_CID  &&
1755             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1756                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1757
1758         switch (command) {
1759         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1760                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1761                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1762                 break;
1763
1764         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1765                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1766                 drv_cmd = BNX2X_Q_CMD_SETUP;
1767                 break;
1768
1769         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1770                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1771                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1772                 break;
1773
1774         case (RAMROD_CMD_ID_ETH_HALT):
1775                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1776                 drv_cmd = BNX2X_Q_CMD_HALT;
1777                 break;
1778
1779         case (RAMROD_CMD_ID_ETH_TERMINATE):
1780                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1781                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1782                 break;
1783
1784         case (RAMROD_CMD_ID_ETH_EMPTY):
1785                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1786                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1787                 break;
1788
1789         default:
1790                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1791                           command, fp->index);
1792                 return;
1793         }
1794
1795         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1796             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1797                 /* q_obj->complete_cmd() failure means that this was
1798                  * an unexpected completion.
1799                  *
1800                  * In this case we don't want to increase the bp->spq_left
1801                  * because apparently we haven't sent this command the first
1802                  * place.
1803                  */
1804 #ifdef BNX2X_STOP_ON_ERROR
1805                 bnx2x_panic();
1806 #else
1807                 return;
1808 #endif
1809         /* SRIOV: reschedule any 'in_progress' operations */
1810         bnx2x_iov_sp_event(bp, cid, true);
1811
1812         smp_mb__before_atomic_inc();
1813         atomic_inc(&bp->cq_spq_left);
1814         /* push the change in bp->spq_left and towards the memory */
1815         smp_mb__after_atomic_inc();
1816
1817         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1818
1819         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1820             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1821                 /* if Q update ramrod is completed for last Q in AFEX vif set
1822                  * flow, then ACK MCP at the end
1823                  *
1824                  * mark pending ACK to MCP bit.
1825                  * prevent case that both bits are cleared.
1826                  * At the end of load/unload driver checks that
1827                  * sp_state is cleared, and this order prevents
1828                  * races
1829                  */
1830                 smp_mb__before_clear_bit();
1831                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1832                 wmb();
1833                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1834                 smp_mb__after_clear_bit();
1835
1836                 /* schedule the sp task as mcp ack is required */
1837                 bnx2x_schedule_sp_task(bp);
1838         }
1839
1840         return;
1841 }
1842
1843 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1844 {
1845         struct bnx2x *bp = netdev_priv(dev_instance);
1846         u16 status = bnx2x_ack_int(bp);
1847         u16 mask;
1848         int i;
1849         u8 cos;
1850
1851         /* Return here if interrupt is shared and it's not for us */
1852         if (unlikely(status == 0)) {
1853                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1854                 return IRQ_NONE;
1855         }
1856         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1857
1858 #ifdef BNX2X_STOP_ON_ERROR
1859         if (unlikely(bp->panic))
1860                 return IRQ_HANDLED;
1861 #endif
1862
1863         for_each_eth_queue(bp, i) {
1864                 struct bnx2x_fastpath *fp = &bp->fp[i];
1865
1866                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1867                 if (status & mask) {
1868                         /* Handle Rx or Tx according to SB id */
1869                         for_each_cos_in_tx_queue(fp, cos)
1870                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1871                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1872                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1873                         status &= ~mask;
1874                 }
1875         }
1876
1877         if (CNIC_SUPPORT(bp)) {
1878                 mask = 0x2;
1879                 if (status & (mask | 0x1)) {
1880                         struct cnic_ops *c_ops = NULL;
1881
1882                         rcu_read_lock();
1883                         c_ops = rcu_dereference(bp->cnic_ops);
1884                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1885                                       CNIC_DRV_STATE_HANDLES_IRQ))
1886                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1887                         rcu_read_unlock();
1888
1889                         status &= ~mask;
1890                 }
1891         }
1892
1893         if (unlikely(status & 0x1)) {
1894
1895                 /* schedule sp task to perform default status block work, ack
1896                  * attentions and enable interrupts.
1897                  */
1898                 bnx2x_schedule_sp_task(bp);
1899
1900                 status &= ~0x1;
1901                 if (!status)
1902                         return IRQ_HANDLED;
1903         }
1904
1905         if (unlikely(status))
1906                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1907                    status);
1908
1909         return IRQ_HANDLED;
1910 }
1911
1912 /* Link */
1913
1914 /*
1915  * General service functions
1916  */
1917
1918 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1919 {
1920         u32 lock_status;
1921         u32 resource_bit = (1 << resource);
1922         int func = BP_FUNC(bp);
1923         u32 hw_lock_control_reg;
1924         int cnt;
1925
1926         /* Validating that the resource is within range */
1927         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1928                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1929                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1930                 return -EINVAL;
1931         }
1932
1933         if (func <= 5) {
1934                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1935         } else {
1936                 hw_lock_control_reg =
1937                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1938         }
1939
1940         /* Validating that the resource is not already taken */
1941         lock_status = REG_RD(bp, hw_lock_control_reg);
1942         if (lock_status & resource_bit) {
1943                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1944                    lock_status, resource_bit);
1945                 return -EEXIST;
1946         }
1947
1948         /* Try for 5 second every 5ms */
1949         for (cnt = 0; cnt < 1000; cnt++) {
1950                 /* Try to acquire the lock */
1951                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1952                 lock_status = REG_RD(bp, hw_lock_control_reg);
1953                 if (lock_status & resource_bit)
1954                         return 0;
1955
1956                 usleep_range(5000, 10000);
1957         }
1958         BNX2X_ERR("Timeout\n");
1959         return -EAGAIN;
1960 }
1961
1962 int bnx2x_release_leader_lock(struct bnx2x *bp)
1963 {
1964         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1965 }
1966
1967 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1968 {
1969         u32 lock_status;
1970         u32 resource_bit = (1 << resource);
1971         int func = BP_FUNC(bp);
1972         u32 hw_lock_control_reg;
1973
1974         /* Validating that the resource is within range */
1975         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1976                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1977                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1978                 return -EINVAL;
1979         }
1980
1981         if (func <= 5) {
1982                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1983         } else {
1984                 hw_lock_control_reg =
1985                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1986         }
1987
1988         /* Validating that the resource is currently taken */
1989         lock_status = REG_RD(bp, hw_lock_control_reg);
1990         if (!(lock_status & resource_bit)) {
1991                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
1992                           lock_status, resource_bit);
1993                 return -EFAULT;
1994         }
1995
1996         REG_WR(bp, hw_lock_control_reg, resource_bit);
1997         return 0;
1998 }
1999
2000 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2001 {
2002         /* The GPIO should be swapped if swap register is set and active */
2003         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2004                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2005         int gpio_shift = gpio_num +
2006                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2007         u32 gpio_mask = (1 << gpio_shift);
2008         u32 gpio_reg;
2009         int value;
2010
2011         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2012                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2013                 return -EINVAL;
2014         }
2015
2016         /* read GPIO value */
2017         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2018
2019         /* get the requested pin value */
2020         if ((gpio_reg & gpio_mask) == gpio_mask)
2021                 value = 1;
2022         else
2023                 value = 0;
2024
2025         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2026
2027         return value;
2028 }
2029
2030 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2031 {
2032         /* The GPIO should be swapped if swap register is set and active */
2033         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2034                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2035         int gpio_shift = gpio_num +
2036                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2037         u32 gpio_mask = (1 << gpio_shift);
2038         u32 gpio_reg;
2039
2040         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2041                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2042                 return -EINVAL;
2043         }
2044
2045         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2046         /* read GPIO and mask except the float bits */
2047         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2048
2049         switch (mode) {
2050         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2051                 DP(NETIF_MSG_LINK,
2052                    "Set GPIO %d (shift %d) -> output low\n",
2053                    gpio_num, gpio_shift);
2054                 /* clear FLOAT and set CLR */
2055                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2056                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2057                 break;
2058
2059         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2060                 DP(NETIF_MSG_LINK,
2061                    "Set GPIO %d (shift %d) -> output high\n",
2062                    gpio_num, gpio_shift);
2063                 /* clear FLOAT and set SET */
2064                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2065                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2066                 break;
2067
2068         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2069                 DP(NETIF_MSG_LINK,
2070                    "Set GPIO %d (shift %d) -> input\n",
2071                    gpio_num, gpio_shift);
2072                 /* set FLOAT */
2073                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2074                 break;
2075
2076         default:
2077                 break;
2078         }
2079
2080         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2081         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2082
2083         return 0;
2084 }
2085
2086 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2087 {
2088         u32 gpio_reg = 0;
2089         int rc = 0;
2090
2091         /* Any port swapping should be handled by caller. */
2092
2093         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2094         /* read GPIO and mask except the float bits */
2095         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2096         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2097         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2098         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2099
2100         switch (mode) {
2101         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2102                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2103                 /* set CLR */
2104                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2105                 break;
2106
2107         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2108                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2109                 /* set SET */
2110                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2111                 break;
2112
2113         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2114                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2115                 /* set FLOAT */
2116                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2117                 break;
2118
2119         default:
2120                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2121                 rc = -EINVAL;
2122                 break;
2123         }
2124
2125         if (rc == 0)
2126                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2127
2128         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2129
2130         return rc;
2131 }
2132
2133 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2134 {
2135         /* The GPIO should be swapped if swap register is set and active */
2136         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2137                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2138         int gpio_shift = gpio_num +
2139                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2140         u32 gpio_mask = (1 << gpio_shift);
2141         u32 gpio_reg;
2142
2143         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2144                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2145                 return -EINVAL;
2146         }
2147
2148         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2149         /* read GPIO int */
2150         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2151
2152         switch (mode) {
2153         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2154                 DP(NETIF_MSG_LINK,
2155                    "Clear GPIO INT %d (shift %d) -> output low\n",
2156                    gpio_num, gpio_shift);
2157                 /* clear SET and set CLR */
2158                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2159                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2160                 break;
2161
2162         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2163                 DP(NETIF_MSG_LINK,
2164                    "Set GPIO INT %d (shift %d) -> output high\n",
2165                    gpio_num, gpio_shift);
2166                 /* clear CLR and set SET */
2167                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2168                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2169                 break;
2170
2171         default:
2172                 break;
2173         }
2174
2175         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2176         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2177
2178         return 0;
2179 }
2180
2181 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2182 {
2183         u32 spio_reg;
2184
2185         /* Only 2 SPIOs are configurable */
2186         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2187                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2188                 return -EINVAL;
2189         }
2190
2191         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2192         /* read SPIO and mask except the float bits */
2193         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2194
2195         switch (mode) {
2196         case MISC_SPIO_OUTPUT_LOW:
2197                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2198                 /* clear FLOAT and set CLR */
2199                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2200                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2201                 break;
2202
2203         case MISC_SPIO_OUTPUT_HIGH:
2204                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2205                 /* clear FLOAT and set SET */
2206                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2207                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2208                 break;
2209
2210         case MISC_SPIO_INPUT_HI_Z:
2211                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2212                 /* set FLOAT */
2213                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2214                 break;
2215
2216         default:
2217                 break;
2218         }
2219
2220         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2221         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2222
2223         return 0;
2224 }
2225
2226 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2227 {
2228         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2229         switch (bp->link_vars.ieee_fc &
2230                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2231         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2232                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2233                                                    ADVERTISED_Pause);
2234                 break;
2235
2236         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2237                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2238                                                   ADVERTISED_Pause);
2239                 break;
2240
2241         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2242                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2243                 break;
2244
2245         default:
2246                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2247                                                    ADVERTISED_Pause);
2248                 break;
2249         }
2250 }
2251
2252 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2253 {
2254         /* Initialize link parameters structure variables
2255          * It is recommended to turn off RX FC for jumbo frames
2256          *  for better performance
2257          */
2258         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2259                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2260         else
2261                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2262 }
2263
2264 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2265 {
2266         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2267         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2268
2269         if (!BP_NOMCP(bp)) {
2270                 bnx2x_set_requested_fc(bp);
2271                 bnx2x_acquire_phy_lock(bp);
2272
2273                 if (load_mode == LOAD_DIAG) {
2274                         struct link_params *lp = &bp->link_params;
2275                         lp->loopback_mode = LOOPBACK_XGXS;
2276                         /* do PHY loopback at 10G speed, if possible */
2277                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2278                                 if (lp->speed_cap_mask[cfx_idx] &
2279                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2280                                         lp->req_line_speed[cfx_idx] =
2281                                         SPEED_10000;
2282                                 else
2283                                         lp->req_line_speed[cfx_idx] =
2284                                         SPEED_1000;
2285                         }
2286                 }
2287
2288                 if (load_mode == LOAD_LOOPBACK_EXT) {
2289                         struct link_params *lp = &bp->link_params;
2290                         lp->loopback_mode = LOOPBACK_EXT;
2291                 }
2292
2293                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2294
2295                 bnx2x_release_phy_lock(bp);
2296
2297                 bnx2x_calc_fc_adv(bp);
2298
2299                 if (bp->link_vars.link_up) {
2300                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2301                         bnx2x_link_report(bp);
2302                 }
2303                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2304                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2305                 return rc;
2306         }
2307         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2308         return -EINVAL;
2309 }
2310
2311 void bnx2x_link_set(struct bnx2x *bp)
2312 {
2313         if (!BP_NOMCP(bp)) {
2314                 bnx2x_acquire_phy_lock(bp);
2315                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2316                 bnx2x_release_phy_lock(bp);
2317
2318                 bnx2x_calc_fc_adv(bp);
2319         } else
2320                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2321 }
2322
2323 static void bnx2x__link_reset(struct bnx2x *bp)
2324 {
2325         if (!BP_NOMCP(bp)) {
2326                 bnx2x_acquire_phy_lock(bp);
2327                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2328                 bnx2x_release_phy_lock(bp);
2329         } else
2330                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2331 }
2332
2333 void bnx2x_force_link_reset(struct bnx2x *bp)
2334 {
2335         bnx2x_acquire_phy_lock(bp);
2336         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2337         bnx2x_release_phy_lock(bp);
2338 }
2339
2340 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2341 {
2342         u8 rc = 0;
2343
2344         if (!BP_NOMCP(bp)) {
2345                 bnx2x_acquire_phy_lock(bp);
2346                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2347                                      is_serdes);
2348                 bnx2x_release_phy_lock(bp);
2349         } else
2350                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2351
2352         return rc;
2353 }
2354
2355 /* Calculates the sum of vn_min_rates.
2356    It's needed for further normalizing of the min_rates.
2357    Returns:
2358      sum of vn_min_rates.
2359        or
2360      0 - if all the min_rates are 0.
2361      In the later case fairness algorithm should be deactivated.
2362      If not all min_rates are zero then those that are zeroes will be set to 1.
2363  */
2364 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2365                                       struct cmng_init_input *input)
2366 {
2367         int all_zero = 1;
2368         int vn;
2369
2370         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2371                 u32 vn_cfg = bp->mf_config[vn];
2372                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2373                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2374
2375                 /* Skip hidden vns */
2376                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2377                         vn_min_rate = 0;
2378                 /* If min rate is zero - set it to 1 */
2379                 else if (!vn_min_rate)
2380                         vn_min_rate = DEF_MIN_RATE;
2381                 else
2382                         all_zero = 0;
2383
2384                 input->vnic_min_rate[vn] = vn_min_rate;
2385         }
2386
2387         /* if ETS or all min rates are zeros - disable fairness */
2388         if (BNX2X_IS_ETS_ENABLED(bp)) {
2389                 input->flags.cmng_enables &=
2390                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2391                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2392         } else if (all_zero) {
2393                 input->flags.cmng_enables &=
2394                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2395                 DP(NETIF_MSG_IFUP,
2396                    "All MIN values are zeroes fairness will be disabled\n");
2397         } else
2398                 input->flags.cmng_enables |=
2399                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2400 }
2401
2402 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2403                                     struct cmng_init_input *input)
2404 {
2405         u16 vn_max_rate;
2406         u32 vn_cfg = bp->mf_config[vn];
2407
2408         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2409                 vn_max_rate = 0;
2410         else {
2411                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2412
2413                 if (IS_MF_SI(bp)) {
2414                         /* maxCfg in percents of linkspeed */
2415                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2416                 } else /* SD modes */
2417                         /* maxCfg is absolute in 100Mb units */
2418                         vn_max_rate = maxCfg * 100;
2419         }
2420
2421         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2422
2423         input->vnic_max_rate[vn] = vn_max_rate;
2424 }
2425
2426 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2427 {
2428         if (CHIP_REV_IS_SLOW(bp))
2429                 return CMNG_FNS_NONE;
2430         if (IS_MF(bp))
2431                 return CMNG_FNS_MINMAX;
2432
2433         return CMNG_FNS_NONE;
2434 }
2435
2436 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2437 {
2438         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2439
2440         if (BP_NOMCP(bp))
2441                 return; /* what should be the default value in this case */
2442
2443         /* For 2 port configuration the absolute function number formula
2444          * is:
2445          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2446          *
2447          *      and there are 4 functions per port
2448          *
2449          * For 4 port configuration it is
2450          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2451          *
2452          *      and there are 2 functions per port
2453          */
2454         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2455                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2456
2457                 if (func >= E1H_FUNC_MAX)
2458                         break;
2459
2460                 bp->mf_config[vn] =
2461                         MF_CFG_RD(bp, func_mf_config[func].config);
2462         }
2463         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2464                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2465                 bp->flags |= MF_FUNC_DIS;
2466         } else {
2467                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2468                 bp->flags &= ~MF_FUNC_DIS;
2469         }
2470 }
2471
2472 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2473 {
2474         struct cmng_init_input input;
2475         memset(&input, 0, sizeof(struct cmng_init_input));
2476
2477         input.port_rate = bp->link_vars.line_speed;
2478
2479         if (cmng_type == CMNG_FNS_MINMAX) {
2480                 int vn;
2481
2482                 /* read mf conf from shmem */
2483                 if (read_cfg)
2484                         bnx2x_read_mf_cfg(bp);
2485
2486                 /* vn_weight_sum and enable fairness if not 0 */
2487                 bnx2x_calc_vn_min(bp, &input);
2488
2489                 /* calculate and set min-max rate for each vn */
2490                 if (bp->port.pmf)
2491                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2492                                 bnx2x_calc_vn_max(bp, vn, &input);
2493
2494                 /* always enable rate shaping and fairness */
2495                 input.flags.cmng_enables |=
2496                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2497
2498                 bnx2x_init_cmng(&input, &bp->cmng);
2499                 return;
2500         }
2501
2502         /* rate shaping and fairness are disabled */
2503         DP(NETIF_MSG_IFUP,
2504            "rate shaping and fairness are disabled\n");
2505 }
2506
2507 static void storm_memset_cmng(struct bnx2x *bp,
2508                               struct cmng_init *cmng,
2509                               u8 port)
2510 {
2511         int vn;
2512         size_t size = sizeof(struct cmng_struct_per_port);
2513
2514         u32 addr = BAR_XSTRORM_INTMEM +
2515                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2516
2517         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2518
2519         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2520                 int func = func_by_vn(bp, vn);
2521
2522                 addr = BAR_XSTRORM_INTMEM +
2523                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2524                 size = sizeof(struct rate_shaping_vars_per_vn);
2525                 __storm_memset_struct(bp, addr, size,
2526                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2527
2528                 addr = BAR_XSTRORM_INTMEM +
2529                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2530                 size = sizeof(struct fairness_vars_per_vn);
2531                 __storm_memset_struct(bp, addr, size,
2532                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2533         }
2534 }
2535
2536 /* This function is called upon link interrupt */
2537 static void bnx2x_link_attn(struct bnx2x *bp)
2538 {
2539         /* Make sure that we are synced with the current statistics */
2540         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2541
2542         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2543
2544         if (bp->link_vars.link_up) {
2545
2546                 /* dropless flow control */
2547                 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2548                         int port = BP_PORT(bp);
2549                         u32 pause_enabled = 0;
2550
2551                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2552                                 pause_enabled = 1;
2553
2554                         REG_WR(bp, BAR_USTRORM_INTMEM +
2555                                USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2556                                pause_enabled);
2557                 }
2558
2559                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2560                         struct host_port_stats *pstats;
2561
2562                         pstats = bnx2x_sp(bp, port_stats);
2563                         /* reset old mac stats */
2564                         memset(&(pstats->mac_stx[0]), 0,
2565                                sizeof(struct mac_stx));
2566                 }
2567                 if (bp->state == BNX2X_STATE_OPEN)
2568                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2569         }
2570
2571         if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2572                 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2573
2574                 if (cmng_fns != CMNG_FNS_NONE) {
2575                         bnx2x_cmng_fns_init(bp, false, cmng_fns);
2576                         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2577                 } else
2578                         /* rate shaping and fairness are disabled */
2579                         DP(NETIF_MSG_IFUP,
2580                            "single function mode without fairness\n");
2581         }
2582
2583         __bnx2x_link_report(bp);
2584
2585         if (IS_MF(bp))
2586                 bnx2x_link_sync_notify(bp);
2587 }
2588
2589 void bnx2x__link_status_update(struct bnx2x *bp)
2590 {
2591         if (bp->state != BNX2X_STATE_OPEN)
2592                 return;
2593
2594         /* read updated dcb configuration */
2595         if (IS_PF(bp)) {
2596                 bnx2x_dcbx_pmf_update(bp);
2597                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2598                 if (bp->link_vars.link_up)
2599                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2600                 else
2601                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2602                         /* indicate link status */
2603                 bnx2x_link_report(bp);
2604
2605         } else { /* VF */
2606                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2607                                           SUPPORTED_10baseT_Full |
2608                                           SUPPORTED_100baseT_Half |
2609                                           SUPPORTED_100baseT_Full |
2610                                           SUPPORTED_1000baseT_Full |
2611                                           SUPPORTED_2500baseX_Full |
2612                                           SUPPORTED_10000baseT_Full |
2613                                           SUPPORTED_TP |
2614                                           SUPPORTED_FIBRE |
2615                                           SUPPORTED_Autoneg |
2616                                           SUPPORTED_Pause |
2617                                           SUPPORTED_Asym_Pause);
2618                 bp->port.advertising[0] = bp->port.supported[0];
2619
2620                 bp->link_params.bp = bp;
2621                 bp->link_params.port = BP_PORT(bp);
2622                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2623                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2624                 bp->link_params.req_line_speed[0] = SPEED_10000;
2625                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2626                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2627                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2628                 bp->link_vars.line_speed = SPEED_10000;
2629                 bp->link_vars.link_status =
2630                         (LINK_STATUS_LINK_UP |
2631                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2632                 bp->link_vars.link_up = 1;
2633                 bp->link_vars.duplex = DUPLEX_FULL;
2634                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2635                 __bnx2x_link_report(bp);
2636                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2637         }
2638 }
2639
2640 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2641                                   u16 vlan_val, u8 allowed_prio)
2642 {
2643         struct bnx2x_func_state_params func_params = {NULL};
2644         struct bnx2x_func_afex_update_params *f_update_params =
2645                 &func_params.params.afex_update;
2646
2647         func_params.f_obj = &bp->func_obj;
2648         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2649
2650         /* no need to wait for RAMROD completion, so don't
2651          * set RAMROD_COMP_WAIT flag
2652          */
2653
2654         f_update_params->vif_id = vifid;
2655         f_update_params->afex_default_vlan = vlan_val;
2656         f_update_params->allowed_priorities = allowed_prio;
2657
2658         /* if ramrod can not be sent, response to MCP immediately */
2659         if (bnx2x_func_state_change(bp, &func_params) < 0)
2660                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2661
2662         return 0;
2663 }
2664
2665 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2666                                           u16 vif_index, u8 func_bit_map)
2667 {
2668         struct bnx2x_func_state_params func_params = {NULL};
2669         struct bnx2x_func_afex_viflists_params *update_params =
2670                 &func_params.params.afex_viflists;
2671         int rc;
2672         u32 drv_msg_code;
2673
2674         /* validate only LIST_SET and LIST_GET are received from switch */
2675         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2676                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2677                           cmd_type);
2678
2679         func_params.f_obj = &bp->func_obj;
2680         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2681
2682         /* set parameters according to cmd_type */
2683         update_params->afex_vif_list_command = cmd_type;
2684         update_params->vif_list_index = vif_index;
2685         update_params->func_bit_map =
2686                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2687         update_params->func_to_clear = 0;
2688         drv_msg_code =
2689                 (cmd_type == VIF_LIST_RULE_GET) ?
2690                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2691                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2692
2693         /* if ramrod can not be sent, respond to MCP immediately for
2694          * SET and GET requests (other are not triggered from MCP)
2695          */
2696         rc = bnx2x_func_state_change(bp, &func_params);
2697         if (rc < 0)
2698                 bnx2x_fw_command(bp, drv_msg_code, 0);
2699
2700         return 0;
2701 }
2702
2703 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2704 {
2705         struct afex_stats afex_stats;
2706         u32 func = BP_ABS_FUNC(bp);
2707         u32 mf_config;
2708         u16 vlan_val;
2709         u32 vlan_prio;
2710         u16 vif_id;
2711         u8 allowed_prio;
2712         u8 vlan_mode;
2713         u32 addr_to_write, vifid, addrs, stats_type, i;
2714
2715         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2716                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2717                 DP(BNX2X_MSG_MCP,
2718                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2719                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2720         }
2721
2722         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2723                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2724                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2725                 DP(BNX2X_MSG_MCP,
2726                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2727                    vifid, addrs);
2728                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2729                                                addrs);
2730         }
2731
2732         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2733                 addr_to_write = SHMEM2_RD(bp,
2734                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2735                 stats_type = SHMEM2_RD(bp,
2736                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2737
2738                 DP(BNX2X_MSG_MCP,
2739                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2740                    addr_to_write);
2741
2742                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2743
2744                 /* write response to scratchpad, for MCP */
2745                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2746                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2747                                *(((u32 *)(&afex_stats))+i));
2748
2749                 /* send ack message to MCP */
2750                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2751         }
2752
2753         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2754                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2755                 bp->mf_config[BP_VN(bp)] = mf_config;
2756                 DP(BNX2X_MSG_MCP,
2757                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2758                    mf_config);
2759
2760                 /* if VIF_SET is "enabled" */
2761                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2762                         /* set rate limit directly to internal RAM */
2763                         struct cmng_init_input cmng_input;
2764                         struct rate_shaping_vars_per_vn m_rs_vn;
2765                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2766                         u32 addr = BAR_XSTRORM_INTMEM +
2767                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2768
2769                         bp->mf_config[BP_VN(bp)] = mf_config;
2770
2771                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2772                         m_rs_vn.vn_counter.rate =
2773                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2774                         m_rs_vn.vn_counter.quota =
2775                                 (m_rs_vn.vn_counter.rate *
2776                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2777
2778                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2779
2780                         /* read relevant values from mf_cfg struct in shmem */
2781                         vif_id =
2782                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2783                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2784                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2785                         vlan_val =
2786                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2787                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2788                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2789                         vlan_prio = (mf_config &
2790                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2791                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2792                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2793                         vlan_mode =
2794                                 (MF_CFG_RD(bp,
2795                                            func_mf_config[func].afex_config) &
2796                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2797                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2798                         allowed_prio =
2799                                 (MF_CFG_RD(bp,
2800                                            func_mf_config[func].afex_config) &
2801                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2802                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2803
2804                         /* send ramrod to FW, return in case of failure */
2805                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2806                                                    allowed_prio))
2807                                 return;
2808
2809                         bp->afex_def_vlan_tag = vlan_val;
2810                         bp->afex_vlan_mode = vlan_mode;
2811                 } else {
2812                         /* notify link down because BP->flags is disabled */
2813                         bnx2x_link_report(bp);
2814
2815                         /* send INVALID VIF ramrod to FW */
2816                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2817
2818                         /* Reset the default afex VLAN */
2819                         bp->afex_def_vlan_tag = -1;
2820                 }
2821         }
2822 }
2823
2824 static void bnx2x_pmf_update(struct bnx2x *bp)
2825 {
2826         int port = BP_PORT(bp);
2827         u32 val;
2828
2829         bp->port.pmf = 1;
2830         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2831
2832         /*
2833          * We need the mb() to ensure the ordering between the writing to
2834          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2835          */
2836         smp_mb();
2837
2838         /* queue a periodic task */
2839         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2840
2841         bnx2x_dcbx_pmf_update(bp);
2842
2843         /* enable nig attention */
2844         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2845         if (bp->common.int_block == INT_BLOCK_HC) {
2846                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2847                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2848         } else if (!CHIP_IS_E1x(bp)) {
2849                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2850                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2851         }
2852
2853         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2854 }
2855
2856 /* end of Link */
2857
2858 /* slow path */
2859
2860 /*
2861  * General service functions
2862  */
2863
2864 /* send the MCP a request, block until there is a reply */
2865 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2866 {
2867         int mb_idx = BP_FW_MB_IDX(bp);
2868         u32 seq;
2869         u32 rc = 0;
2870         u32 cnt = 1;
2871         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2872
2873         mutex_lock(&bp->fw_mb_mutex);
2874         seq = ++bp->fw_seq;
2875         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2876         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2877
2878         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2879                         (command | seq), param);
2880
2881         do {
2882                 /* let the FW do it's magic ... */
2883                 msleep(delay);
2884
2885                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2886
2887                 /* Give the FW up to 5 second (500*10ms) */
2888         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2889
2890         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2891            cnt*delay, rc, seq);
2892
2893         /* is this a reply to our command? */
2894         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2895                 rc &= FW_MSG_CODE_MASK;
2896         else {
2897                 /* FW BUG! */
2898                 BNX2X_ERR("FW failed to respond!\n");
2899                 bnx2x_fw_dump(bp);
2900                 rc = 0;
2901         }
2902         mutex_unlock(&bp->fw_mb_mutex);
2903
2904         return rc;
2905 }
2906
2907 static void storm_memset_func_cfg(struct bnx2x *bp,
2908                                  struct tstorm_eth_function_common_config *tcfg,
2909                                  u16 abs_fid)
2910 {
2911         size_t size = sizeof(struct tstorm_eth_function_common_config);
2912
2913         u32 addr = BAR_TSTRORM_INTMEM +
2914                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2915
2916         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2917 }
2918
2919 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2920 {
2921         if (CHIP_IS_E1x(bp)) {
2922                 struct tstorm_eth_function_common_config tcfg = {0};
2923
2924                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2925         }
2926
2927         /* Enable the function in the FW */
2928         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2929         storm_memset_func_en(bp, p->func_id, 1);
2930
2931         /* spq */
2932         if (p->func_flgs & FUNC_FLG_SPQ) {
2933                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2934                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2935                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2936         }
2937 }
2938
2939 /**
2940  * bnx2x_get_common_flags - Return common flags
2941  *
2942  * @bp          device handle
2943  * @fp          queue handle
2944  * @zero_stats  TRUE if statistics zeroing is needed
2945  *
2946  * Return the flags that are common for the Tx-only and not normal connections.
2947  */
2948 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2949                                             struct bnx2x_fastpath *fp,
2950                                             bool zero_stats)
2951 {
2952         unsigned long flags = 0;
2953
2954         /* PF driver will always initialize the Queue to an ACTIVE state */
2955         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2956
2957         /* tx only connections collect statistics (on the same index as the
2958          * parent connection). The statistics are zeroed when the parent
2959          * connection is initialized.
2960          */
2961
2962         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2963         if (zero_stats)
2964                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2965
2966         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
2967         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
2968
2969 #ifdef BNX2X_STOP_ON_ERROR
2970         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2971 #endif
2972
2973         return flags;
2974 }
2975
2976 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2977                                        struct bnx2x_fastpath *fp,
2978                                        bool leading)
2979 {
2980         unsigned long flags = 0;
2981
2982         /* calculate other queue flags */
2983         if (IS_MF_SD(bp))
2984                 __set_bit(BNX2X_Q_FLG_OV, &flags);
2985
2986         if (IS_FCOE_FP(fp)) {
2987                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2988                 /* For FCoE - force usage of default priority (for afex) */
2989                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2990         }
2991
2992         if (!fp->disable_tpa) {
2993                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2994                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2995                 if (fp->mode == TPA_MODE_GRO)
2996                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2997         }
2998
2999         if (leading) {
3000                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3001                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3002         }
3003
3004         /* Always set HW VLAN stripping */
3005         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3006
3007         /* configure silent vlan removal */
3008         if (IS_MF_AFEX(bp))
3009                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3010
3011         return flags | bnx2x_get_common_flags(bp, fp, true);
3012 }
3013
3014 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3015         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3016         u8 cos)
3017 {
3018         gen_init->stat_id = bnx2x_stats_id(fp);
3019         gen_init->spcl_id = fp->cl_id;
3020
3021         /* Always use mini-jumbo MTU for FCoE L2 ring */
3022         if (IS_FCOE_FP(fp))
3023                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3024         else
3025                 gen_init->mtu = bp->dev->mtu;
3026
3027         gen_init->cos = cos;
3028 }
3029
3030 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3031         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3032         struct bnx2x_rxq_setup_params *rxq_init)
3033 {
3034         u8 max_sge = 0;
3035         u16 sge_sz = 0;
3036         u16 tpa_agg_size = 0;
3037
3038         if (!fp->disable_tpa) {
3039                 pause->sge_th_lo = SGE_TH_LO(bp);
3040                 pause->sge_th_hi = SGE_TH_HI(bp);
3041
3042                 /* validate SGE ring has enough to cross high threshold */
3043                 WARN_ON(bp->dropless_fc &&
3044                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3045                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3046
3047                 tpa_agg_size = TPA_AGG_SIZE;
3048                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3049                         SGE_PAGE_SHIFT;
3050                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3051                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3052                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3053         }
3054
3055         /* pause - not for e1 */
3056         if (!CHIP_IS_E1(bp)) {
3057                 pause->bd_th_lo = BD_TH_LO(bp);
3058                 pause->bd_th_hi = BD_TH_HI(bp);
3059
3060                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3061                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3062                 /*
3063                  * validate that rings have enough entries to cross
3064                  * high thresholds
3065                  */
3066                 WARN_ON(bp->dropless_fc &&
3067                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3068                                 bp->rx_ring_size);
3069                 WARN_ON(bp->dropless_fc &&
3070                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3071                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3072
3073                 pause->pri_map = 1;
3074         }
3075
3076         /* rxq setup */
3077         rxq_init->dscr_map = fp->rx_desc_mapping;
3078         rxq_init->sge_map = fp->rx_sge_mapping;
3079         rxq_init->rcq_map = fp->rx_comp_mapping;
3080         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3081
3082         /* This should be a maximum number of data bytes that may be
3083          * placed on the BD (not including paddings).
3084          */
3085         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3086                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3087
3088         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3089         rxq_init->tpa_agg_sz = tpa_agg_size;
3090         rxq_init->sge_buf_sz = sge_sz;
3091         rxq_init->max_sges_pkt = max_sge;
3092         rxq_init->rss_engine_id = BP_FUNC(bp);
3093         rxq_init->mcast_engine_id = BP_FUNC(bp);
3094
3095         /* Maximum number or simultaneous TPA aggregation for this Queue.
3096          *
3097          * For PF Clients it should be the maximum available number.
3098          * VF driver(s) may want to define it to a smaller value.
3099          */
3100         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3101
3102         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3103         rxq_init->fw_sb_id = fp->fw_sb_id;
3104
3105         if (IS_FCOE_FP(fp))
3106                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3107         else
3108                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3109         /* configure silent vlan removal
3110          * if multi function mode is afex, then mask default vlan
3111          */
3112         if (IS_MF_AFEX(bp)) {
3113                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3114                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3115         }
3116 }
3117
3118 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3119         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3120         u8 cos)
3121 {
3122         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3123         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3124         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3125         txq_init->fw_sb_id = fp->fw_sb_id;
3126
3127         /*
3128          * set the tss leading client id for TX classification ==
3129          * leading RSS client id
3130          */
3131         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3132
3133         if (IS_FCOE_FP(fp)) {
3134                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3135                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3136         }
3137 }
3138
3139 static void bnx2x_pf_init(struct bnx2x *bp)
3140 {
3141         struct bnx2x_func_init_params func_init = {0};
3142         struct event_ring_data eq_data = { {0} };
3143         u16 flags;
3144
3145         if (!CHIP_IS_E1x(bp)) {
3146                 /* reset IGU PF statistics: MSIX + ATTN */
3147                 /* PF */
3148                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3149                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3150                            (CHIP_MODE_IS_4_PORT(bp) ?
3151                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3152                 /* ATTN */
3153                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3154                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3155                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3156                            (CHIP_MODE_IS_4_PORT(bp) ?
3157                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3158         }
3159
3160         /* function setup flags */
3161         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3162
3163         /* This flag is relevant for E1x only.
3164          * E2 doesn't have a TPA configuration in a function level.
3165          */
3166         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3167
3168         func_init.func_flgs = flags;
3169         func_init.pf_id = BP_FUNC(bp);
3170         func_init.func_id = BP_FUNC(bp);
3171         func_init.spq_map = bp->spq_mapping;
3172         func_init.spq_prod = bp->spq_prod_idx;
3173
3174         bnx2x_func_init(bp, &func_init);
3175
3176         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3177
3178         /*
3179          * Congestion management values depend on the link rate
3180          * There is no active link so initial link rate is set to 10 Gbps.
3181          * When the link comes up The congestion management values are
3182          * re-calculated according to the actual link rate.
3183          */
3184         bp->link_vars.line_speed = SPEED_10000;
3185         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3186
3187         /* Only the PMF sets the HW */
3188         if (bp->port.pmf)
3189                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3190
3191         /* init Event Queue - PCI bus guarantees correct endianity*/
3192         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3193         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3194         eq_data.producer = bp->eq_prod;
3195         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3196         eq_data.sb_id = DEF_SB_ID;
3197         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3198 }
3199
3200 static void bnx2x_e1h_disable(struct bnx2x *bp)
3201 {
3202         int port = BP_PORT(bp);
3203
3204         bnx2x_tx_disable(bp);
3205
3206         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3207 }
3208
3209 static void bnx2x_e1h_enable(struct bnx2x *bp)
3210 {
3211         int port = BP_PORT(bp);
3212
3213         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3214
3215         /* Tx queue should be only re-enabled */
3216         netif_tx_wake_all_queues(bp->dev);
3217
3218         /*
3219          * Should not call netif_carrier_on since it will be called if the link
3220          * is up when checking for link state
3221          */
3222 }
3223
3224 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3225
3226 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3227 {
3228         struct eth_stats_info *ether_stat =
3229                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3230         struct bnx2x_vlan_mac_obj *mac_obj =
3231                 &bp->sp_objs->mac_obj;
3232         int i;
3233
3234         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3235                 ETH_STAT_INFO_VERSION_LEN);
3236
3237         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3238          * mac_local field in ether_stat struct. The base address is offset by 2
3239          * bytes to account for the field being 8 bytes but a mac address is
3240          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3241          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3242          * allocated by the ether_stat struct, so the macs will land in their
3243          * proper positions.
3244          */
3245         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3246                 memset(ether_stat->mac_local + i, 0,
3247                        sizeof(ether_stat->mac_local[0]));
3248         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3249                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3250                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3251                                 ETH_ALEN);
3252         ether_stat->mtu_size = bp->dev->mtu;
3253         if (bp->dev->features & NETIF_F_RXCSUM)
3254                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3255         if (bp->dev->features & NETIF_F_TSO)
3256                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3257         ether_stat->feature_flags |= bp->common.boot_mode;
3258
3259         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3260
3261         ether_stat->txq_size = bp->tx_ring_size;
3262         ether_stat->rxq_size = bp->rx_ring_size;
3263 }
3264
3265 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3266 {
3267         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3268         struct fcoe_stats_info *fcoe_stat =
3269                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3270
3271         if (!CNIC_LOADED(bp))
3272                 return;
3273
3274         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3275
3276         fcoe_stat->qos_priority =
3277                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3278
3279         /* insert FCoE stats from ramrod response */
3280         if (!NO_FCOE(bp)) {
3281                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3282                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3283                         tstorm_queue_statistics;
3284
3285                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3286                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3287                         xstorm_queue_statistics;
3288
3289                 struct fcoe_statistics_params *fw_fcoe_stat =
3290                         &bp->fw_stats_data->fcoe;
3291
3292                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3293                           fcoe_stat->rx_bytes_lo,
3294                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3295
3296                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3297                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3298                           fcoe_stat->rx_bytes_lo,
3299                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3300
3301                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3302                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3303                           fcoe_stat->rx_bytes_lo,
3304                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3305
3306                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3307                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3308                           fcoe_stat->rx_bytes_lo,
3309                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3310
3311                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3312                           fcoe_stat->rx_frames_lo,
3313                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3314
3315                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3316                           fcoe_stat->rx_frames_lo,
3317                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3318
3319                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3320                           fcoe_stat->rx_frames_lo,
3321                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3322
3323                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3324                           fcoe_stat->rx_frames_lo,
3325                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3326
3327                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3328                           fcoe_stat->tx_bytes_lo,
3329                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3330
3331                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3332                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3333                           fcoe_stat->tx_bytes_lo,
3334                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3335
3336                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3337                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3338                           fcoe_stat->tx_bytes_lo,
3339                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3340
3341                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3342                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3343                           fcoe_stat->tx_bytes_lo,
3344                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3345
3346                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3347                           fcoe_stat->tx_frames_lo,
3348                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3349
3350                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3351                           fcoe_stat->tx_frames_lo,
3352                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3353
3354                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3355                           fcoe_stat->tx_frames_lo,
3356                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3357
3358                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3359                           fcoe_stat->tx_frames_lo,
3360                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3361         }
3362
3363         /* ask L5 driver to add data to the struct */
3364         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3365 }
3366
3367 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3368 {
3369         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3370         struct iscsi_stats_info *iscsi_stat =
3371                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3372
3373         if (!CNIC_LOADED(bp))
3374                 return;
3375
3376         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3377                ETH_ALEN);
3378
3379         iscsi_stat->qos_priority =
3380                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3381
3382         /* ask L5 driver to add data to the struct */
3383         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3384 }
3385
3386 /* called due to MCP event (on pmf):
3387  *      reread new bandwidth configuration
3388  *      configure FW
3389  *      notify others function about the change
3390  */
3391 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3392 {
3393         if (bp->link_vars.link_up) {
3394                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3395                 bnx2x_link_sync_notify(bp);
3396         }
3397         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3398 }
3399
3400 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3401 {
3402         bnx2x_config_mf_bw(bp);
3403         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3404 }
3405
3406 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3407 {
3408         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3409         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3410 }
3411
3412 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3413 {
3414         enum drv_info_opcode op_code;
3415         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3416
3417         /* if drv_info version supported by MFW doesn't match - send NACK */
3418         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3419                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3420                 return;
3421         }
3422
3423         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3424                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3425
3426         memset(&bp->slowpath->drv_info_to_mcp, 0,
3427                sizeof(union drv_info_to_mcp));
3428
3429         switch (op_code) {
3430         case ETH_STATS_OPCODE:
3431                 bnx2x_drv_info_ether_stat(bp);
3432                 break;
3433         case FCOE_STATS_OPCODE:
3434                 bnx2x_drv_info_fcoe_stat(bp);
3435                 break;
3436         case ISCSI_STATS_OPCODE:
3437                 bnx2x_drv_info_iscsi_stat(bp);
3438                 break;
3439         default:
3440                 /* if op code isn't supported - send NACK */
3441                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3442                 return;
3443         }
3444
3445         /* if we got drv_info attn from MFW then these fields are defined in
3446          * shmem2 for sure
3447          */
3448         SHMEM2_WR(bp, drv_info_host_addr_lo,
3449                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3450         SHMEM2_WR(bp, drv_info_host_addr_hi,
3451                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3452
3453         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3454 }
3455
3456 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3457 {
3458         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3459
3460         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3461
3462                 /*
3463                  * This is the only place besides the function initialization
3464                  * where the bp->flags can change so it is done without any
3465                  * locks
3466                  */
3467                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3468                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3469                         bp->flags |= MF_FUNC_DIS;
3470
3471                         bnx2x_e1h_disable(bp);
3472                 } else {
3473                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3474                         bp->flags &= ~MF_FUNC_DIS;
3475
3476                         bnx2x_e1h_enable(bp);
3477                 }
3478                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3479         }
3480         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3481                 bnx2x_config_mf_bw(bp);
3482                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3483         }
3484
3485         /* Report results to MCP */
3486         if (dcc_event)
3487                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3488         else
3489                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3490 }
3491
3492 /* must be called under the spq lock */
3493 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3494 {
3495         struct eth_spe *next_spe = bp->spq_prod_bd;
3496
3497         if (bp->spq_prod_bd == bp->spq_last_bd) {
3498                 bp->spq_prod_bd = bp->spq;
3499                 bp->spq_prod_idx = 0;
3500                 DP(BNX2X_MSG_SP, "end of spq\n");
3501         } else {
3502                 bp->spq_prod_bd++;
3503                 bp->spq_prod_idx++;
3504         }
3505         return next_spe;
3506 }
3507
3508 /* must be called under the spq lock */
3509 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3510 {
3511         int func = BP_FUNC(bp);
3512
3513         /*
3514          * Make sure that BD data is updated before writing the producer:
3515          * BD data is written to the memory, the producer is read from the
3516          * memory, thus we need a full memory barrier to ensure the ordering.
3517          */
3518         mb();
3519
3520         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3521                  bp->spq_prod_idx);
3522         mmiowb();
3523 }
3524
3525 /**
3526  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3527  *
3528  * @cmd:        command to check
3529  * @cmd_type:   command type
3530  */
3531 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3532 {
3533         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3534             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3535             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3536             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3537             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3538             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3539             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3540                 return true;
3541         else
3542                 return false;
3543 }
3544
3545 /**
3546  * bnx2x_sp_post - place a single command on an SP ring
3547  *
3548  * @bp:         driver handle
3549  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3550  * @cid:        SW CID the command is related to
3551  * @data_hi:    command private data address (high 32 bits)
3552  * @data_lo:    command private data address (low 32 bits)
3553  * @cmd_type:   command type (e.g. NONE, ETH)
3554  *
3555  * SP data is handled as if it's always an address pair, thus data fields are
3556  * not swapped to little endian in upper functions. Instead this function swaps
3557  * data as if it's two u32 fields.
3558  */
3559 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3560                   u32 data_hi, u32 data_lo, int cmd_type)
3561 {
3562         struct eth_spe *spe;
3563         u16 type;
3564         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3565
3566 #ifdef BNX2X_STOP_ON_ERROR
3567         if (unlikely(bp->panic)) {
3568                 BNX2X_ERR("Can't post SP when there is panic\n");
3569                 return -EIO;
3570         }
3571 #endif
3572
3573         spin_lock_bh(&bp->spq_lock);
3574
3575         if (common) {
3576                 if (!atomic_read(&bp->eq_spq_left)) {
3577                         BNX2X_ERR("BUG! EQ ring full!\n");
3578                         spin_unlock_bh(&bp->spq_lock);
3579                         bnx2x_panic();
3580                         return -EBUSY;
3581                 }
3582         } else if (!atomic_read(&bp->cq_spq_left)) {
3583                         BNX2X_ERR("BUG! SPQ ring full!\n");
3584                         spin_unlock_bh(&bp->spq_lock);
3585                         bnx2x_panic();
3586                         return -EBUSY;
3587         }
3588
3589         spe = bnx2x_sp_get_next(bp);
3590
3591         /* CID needs port number to be encoded int it */
3592         spe->hdr.conn_and_cmd_data =
3593                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3594                                     HW_CID(bp, cid));
3595
3596         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3597
3598         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3599                  SPE_HDR_FUNCTION_ID);
3600
3601         spe->hdr.type = cpu_to_le16(type);
3602
3603         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3604         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3605
3606         /*
3607          * It's ok if the actual decrement is issued towards the memory
3608          * somewhere between the spin_lock and spin_unlock. Thus no
3609          * more explicit memory barrier is needed.
3610          */
3611         if (common)
3612                 atomic_dec(&bp->eq_spq_left);
3613         else
3614                 atomic_dec(&bp->cq_spq_left);
3615
3616         DP(BNX2X_MSG_SP,
3617            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3618            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3619            (u32)(U64_LO(bp->spq_mapping) +
3620            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3621            HW_CID(bp, cid), data_hi, data_lo, type,
3622            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3623
3624         bnx2x_sp_prod_update(bp);
3625         spin_unlock_bh(&bp->spq_lock);
3626         return 0;
3627 }
3628
3629 /* acquire split MCP access lock register */
3630 static int bnx2x_acquire_alr(struct bnx2x *bp)
3631 {
3632         u32 j, val;
3633         int rc = 0;
3634
3635         might_sleep();
3636         for (j = 0; j < 1000; j++) {
3637                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3638                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3639                 if (val & MCPR_ACCESS_LOCK_LOCK)
3640                         break;
3641
3642                 usleep_range(5000, 10000);
3643         }
3644         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3645                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3646                 rc = -EBUSY;
3647         }
3648
3649         return rc;
3650 }
3651
3652 /* release split MCP access lock register */
3653 static void bnx2x_release_alr(struct bnx2x *bp)
3654 {
3655         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3656 }
3657
3658 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3659 #define BNX2X_DEF_SB_IDX        0x0002
3660
3661 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3662 {
3663         struct host_sp_status_block *def_sb = bp->def_status_blk;
3664         u16 rc = 0;
3665
3666         barrier(); /* status block is written to by the chip */
3667         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3668                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3669                 rc |= BNX2X_DEF_SB_ATT_IDX;
3670         }
3671
3672         if (bp->def_idx != def_sb->sp_sb.running_index) {
3673                 bp->def_idx = def_sb->sp_sb.running_index;
3674                 rc |= BNX2X_DEF_SB_IDX;
3675         }
3676
3677         /* Do not reorder: indices reading should complete before handling */
3678         barrier();
3679         return rc;
3680 }
3681
3682 /*
3683  * slow path service functions
3684  */
3685
3686 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3687 {
3688         int port = BP_PORT(bp);
3689         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3690                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3691         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3692                                        NIG_REG_MASK_INTERRUPT_PORT0;
3693         u32 aeu_mask;
3694         u32 nig_mask = 0;
3695         u32 reg_addr;
3696
3697         if (bp->attn_state & asserted)
3698                 BNX2X_ERR("IGU ERROR\n");
3699
3700         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3701         aeu_mask = REG_RD(bp, aeu_addr);
3702
3703         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3704            aeu_mask, asserted);
3705         aeu_mask &= ~(asserted & 0x3ff);
3706         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3707
3708         REG_WR(bp, aeu_addr, aeu_mask);
3709         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3710
3711         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3712         bp->attn_state |= asserted;
3713         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3714
3715         if (asserted & ATTN_HARD_WIRED_MASK) {
3716                 if (asserted & ATTN_NIG_FOR_FUNC) {
3717
3718                         bnx2x_acquire_phy_lock(bp);
3719
3720                         /* save nig interrupt mask */
3721                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3722
3723                         /* If nig_mask is not set, no need to call the update
3724                          * function.
3725                          */
3726                         if (nig_mask) {
3727                                 REG_WR(bp, nig_int_mask_addr, 0);
3728
3729                                 bnx2x_link_attn(bp);
3730                         }
3731
3732                         /* handle unicore attn? */
3733                 }
3734                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3735                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3736
3737                 if (asserted & GPIO_2_FUNC)
3738                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3739
3740                 if (asserted & GPIO_3_FUNC)
3741                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3742
3743                 if (asserted & GPIO_4_FUNC)
3744                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3745
3746                 if (port == 0) {
3747                         if (asserted & ATTN_GENERAL_ATTN_1) {
3748                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3749                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3750                         }
3751                         if (asserted & ATTN_GENERAL_ATTN_2) {
3752                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3753                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3754                         }
3755                         if (asserted & ATTN_GENERAL_ATTN_3) {
3756                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3757                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3758                         }
3759                 } else {
3760                         if (asserted & ATTN_GENERAL_ATTN_4) {
3761                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3762                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3763                         }
3764                         if (asserted & ATTN_GENERAL_ATTN_5) {
3765                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3766                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3767                         }
3768                         if (asserted & ATTN_GENERAL_ATTN_6) {
3769                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3770                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3771                         }
3772                 }
3773
3774         } /* if hardwired */
3775
3776         if (bp->common.int_block == INT_BLOCK_HC)
3777                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3778                             COMMAND_REG_ATTN_BITS_SET);
3779         else
3780                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3781
3782         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3783            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3784         REG_WR(bp, reg_addr, asserted);
3785
3786         /* now set back the mask */
3787         if (asserted & ATTN_NIG_FOR_FUNC) {
3788                 /* Verify that IGU ack through BAR was written before restoring
3789                  * NIG mask. This loop should exit after 2-3 iterations max.
3790                  */
3791                 if (bp->common.int_block != INT_BLOCK_HC) {
3792                         u32 cnt = 0, igu_acked;
3793                         do {
3794                                 igu_acked = REG_RD(bp,
3795                                                    IGU_REG_ATTENTION_ACK_BITS);
3796                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3797                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3798                         if (!igu_acked)
3799                                 DP(NETIF_MSG_HW,
3800                                    "Failed to verify IGU ack on time\n");
3801                         barrier();
3802                 }
3803                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3804                 bnx2x_release_phy_lock(bp);
3805         }
3806 }
3807
3808 static void bnx2x_fan_failure(struct bnx2x *bp)
3809 {
3810         int port = BP_PORT(bp);
3811         u32 ext_phy_config;
3812         /* mark the failure */
3813         ext_phy_config =
3814                 SHMEM_RD(bp,
3815                          dev_info.port_hw_config[port].external_phy_config);
3816
3817         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3818         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3819         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3820                  ext_phy_config);
3821
3822         /* log the failure */
3823         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3824                             "Please contact OEM Support for assistance\n");
3825
3826         /* Schedule device reset (unload)
3827          * This is due to some boards consuming sufficient power when driver is
3828          * up to overheat if fan fails.
3829          */
3830         smp_mb__before_clear_bit();
3831         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3832         smp_mb__after_clear_bit();
3833         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3834 }
3835
3836 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3837 {
3838         int port = BP_PORT(bp);
3839         int reg_offset;
3840         u32 val;
3841
3842         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3843                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3844
3845         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3846
3847                 val = REG_RD(bp, reg_offset);
3848                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3849                 REG_WR(bp, reg_offset, val);
3850
3851                 BNX2X_ERR("SPIO5 hw attention\n");
3852
3853                 /* Fan failure attention */
3854                 bnx2x_hw_reset_phy(&bp->link_params);
3855                 bnx2x_fan_failure(bp);
3856         }
3857
3858         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3859                 bnx2x_acquire_phy_lock(bp);
3860                 bnx2x_handle_module_detect_int(&bp->link_params);
3861                 bnx2x_release_phy_lock(bp);
3862         }
3863
3864         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3865
3866                 val = REG_RD(bp, reg_offset);
3867                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3868                 REG_WR(bp, reg_offset, val);
3869
3870                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3871                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3872                 bnx2x_panic();
3873         }
3874 }
3875
3876 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3877 {
3878         u32 val;
3879
3880         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3881
3882                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3883                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3884                 /* DORQ discard attention */
3885                 if (val & 0x2)
3886                         BNX2X_ERR("FATAL error from DORQ\n");
3887         }
3888
3889         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3890
3891                 int port = BP_PORT(bp);
3892                 int reg_offset;
3893
3894                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3895                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3896
3897                 val = REG_RD(bp, reg_offset);
3898                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3899                 REG_WR(bp, reg_offset, val);
3900
3901                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3902                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3903                 bnx2x_panic();
3904         }
3905 }
3906
3907 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3908 {
3909         u32 val;
3910
3911         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3912
3913                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3914                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3915                 /* CFC error attention */
3916                 if (val & 0x2)
3917                         BNX2X_ERR("FATAL error from CFC\n");
3918         }
3919
3920         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3921                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3922                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3923                 /* RQ_USDMDP_FIFO_OVERFLOW */
3924                 if (val & 0x18000)
3925                         BNX2X_ERR("FATAL error from PXP\n");
3926
3927                 if (!CHIP_IS_E1x(bp)) {
3928                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3929                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3930                 }
3931         }
3932
3933         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3934
3935                 int port = BP_PORT(bp);
3936                 int reg_offset;
3937
3938                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3939                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3940
3941                 val = REG_RD(bp, reg_offset);
3942                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3943                 REG_WR(bp, reg_offset, val);
3944
3945                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3946                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3947                 bnx2x_panic();
3948         }
3949 }
3950
3951 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3952 {
3953         u32 val;
3954
3955         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3956
3957                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3958                         int func = BP_FUNC(bp);
3959
3960                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3961                         bnx2x_read_mf_cfg(bp);
3962                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3963                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3964                         val = SHMEM_RD(bp,
3965                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3966                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3967                                 bnx2x_dcc_event(bp,
3968                                             (val & DRV_STATUS_DCC_EVENT_MASK));
3969
3970                         if (val & DRV_STATUS_SET_MF_BW)
3971                                 bnx2x_set_mf_bw(bp);
3972
3973                         if (val & DRV_STATUS_DRV_INFO_REQ)
3974                                 bnx2x_handle_drv_info_req(bp);
3975
3976                         if (val & DRV_STATUS_VF_DISABLED)
3977                                 bnx2x_vf_handle_flr_event(bp);
3978
3979                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3980                                 bnx2x_pmf_update(bp);
3981
3982                         if (bp->port.pmf &&
3983                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3984                                 bp->dcbx_enabled > 0)
3985                                 /* start dcbx state machine */
3986                                 bnx2x_dcbx_set_params(bp,
3987                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
3988                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
3989                                 bnx2x_handle_afex_cmd(bp,
3990                                         val & DRV_STATUS_AFEX_EVENT_MASK);
3991                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3992                                 bnx2x_handle_eee_event(bp);
3993                         if (bp->link_vars.periodic_flags &
3994                             PERIODIC_FLAGS_LINK_EVENT) {
3995                                 /*  sync with link */
3996                                 bnx2x_acquire_phy_lock(bp);
3997                                 bp->link_vars.periodic_flags &=
3998                                         ~PERIODIC_FLAGS_LINK_EVENT;
3999                                 bnx2x_release_phy_lock(bp);
4000                                 if (IS_MF(bp))
4001                                         bnx2x_link_sync_notify(bp);
4002                                 bnx2x_link_report(bp);
4003                         }
4004                         /* Always call it here: bnx2x_link_report() will
4005                          * prevent the link indication duplication.
4006                          */
4007                         bnx2x__link_status_update(bp);
4008                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4009
4010                         BNX2X_ERR("MC assert!\n");
4011                         bnx2x_mc_assert(bp);
4012                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4013                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4014                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4015                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4016                         bnx2x_panic();
4017
4018                 } else if (attn & BNX2X_MCP_ASSERT) {
4019
4020                         BNX2X_ERR("MCP assert!\n");
4021                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4022                         bnx2x_fw_dump(bp);
4023
4024                 } else
4025                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4026         }
4027
4028         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4029                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4030                 if (attn & BNX2X_GRC_TIMEOUT) {
4031                         val = CHIP_IS_E1(bp) ? 0 :
4032                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4033                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4034                 }
4035                 if (attn & BNX2X_GRC_RSV) {
4036                         val = CHIP_IS_E1(bp) ? 0 :
4037                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4038                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4039                 }
4040                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4041         }
4042 }
4043
4044 /*
4045  * Bits map:
4046  * 0-7   - Engine0 load counter.
4047  * 8-15  - Engine1 load counter.
4048  * 16    - Engine0 RESET_IN_PROGRESS bit.
4049  * 17    - Engine1 RESET_IN_PROGRESS bit.
4050  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4051  *         on the engine
4052  * 19    - Engine1 ONE_IS_LOADED.
4053  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4054  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4055  *         just the one belonging to its engine).
4056  *
4057  */
4058 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4059
4060 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4061 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4062 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4063 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4064 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4065 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4066 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4067
4068 /*
4069  * Set the GLOBAL_RESET bit.
4070  *
4071  * Should be run under rtnl lock
4072  */
4073 void bnx2x_set_reset_global(struct bnx2x *bp)
4074 {
4075         u32 val;
4076         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4077         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4078         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4079         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4080 }
4081
4082 /*
4083  * Clear the GLOBAL_RESET bit.
4084  *
4085  * Should be run under rtnl lock
4086  */
4087 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4088 {
4089         u32 val;
4090         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4091         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4092         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4093         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4094 }
4095
4096 /*
4097  * Checks the GLOBAL_RESET bit.
4098  *
4099  * should be run under rtnl lock
4100  */
4101 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4102 {
4103         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4104
4105         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4106         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4107 }
4108
4109 /*
4110  * Clear RESET_IN_PROGRESS bit for the current engine.
4111  *
4112  * Should be run under rtnl lock
4113  */
4114 static void bnx2x_set_reset_done(struct bnx2x *bp)
4115 {
4116         u32 val;
4117         u32 bit = BP_PATH(bp) ?
4118                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4119         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4120         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4121
4122         /* Clear the bit */
4123         val &= ~bit;
4124         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4125
4126         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4127 }
4128
4129 /*
4130  * Set RESET_IN_PROGRESS for the current engine.
4131  *
4132  * should be run under rtnl lock
4133  */
4134 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4135 {
4136         u32 val;
4137         u32 bit = BP_PATH(bp) ?
4138                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4139         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4140         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4141
4142         /* Set the bit */
4143         val |= bit;
4144         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4145         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4146 }
4147
4148 /*
4149  * Checks the RESET_IN_PROGRESS bit for the given engine.
4150  * should be run under rtnl lock
4151  */
4152 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4153 {
4154         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4155         u32 bit = engine ?
4156                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4157
4158         /* return false if bit is set */
4159         return (val & bit) ? false : true;
4160 }
4161
4162 /*
4163  * set pf load for the current pf.
4164  *
4165  * should be run under rtnl lock
4166  */
4167 void bnx2x_set_pf_load(struct bnx2x *bp)
4168 {
4169         u32 val1, val;
4170         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4171                              BNX2X_PATH0_LOAD_CNT_MASK;
4172         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4173                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4174
4175         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4176         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4177
4178         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4179
4180         /* get the current counter value */
4181         val1 = (val & mask) >> shift;
4182
4183         /* set bit of that PF */
4184         val1 |= (1 << bp->pf_num);
4185
4186         /* clear the old value */
4187         val &= ~mask;
4188
4189         /* set the new one */
4190         val |= ((val1 << shift) & mask);
4191
4192         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4193         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4194 }
4195
4196 /**
4197  * bnx2x_clear_pf_load - clear pf load mark
4198  *
4199  * @bp:         driver handle
4200  *
4201  * Should be run under rtnl lock.
4202  * Decrements the load counter for the current engine. Returns
4203  * whether other functions are still loaded
4204  */
4205 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4206 {
4207         u32 val1, val;
4208         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4209                              BNX2X_PATH0_LOAD_CNT_MASK;
4210         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4211                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4212
4213         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4214         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4215         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4216
4217         /* get the current counter value */
4218         val1 = (val & mask) >> shift;
4219
4220         /* clear bit of that PF */
4221         val1 &= ~(1 << bp->pf_num);
4222
4223         /* clear the old value */
4224         val &= ~mask;
4225
4226         /* set the new one */
4227         val |= ((val1 << shift) & mask);
4228
4229         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4230         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4231         return val1 != 0;
4232 }
4233
4234 /*
4235  * Read the load status for the current engine.
4236  *
4237  * should be run under rtnl lock
4238  */
4239 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4240 {
4241         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4242                              BNX2X_PATH0_LOAD_CNT_MASK);
4243         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4244                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4245         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4246
4247         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4248
4249         val = (val & mask) >> shift;
4250
4251         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4252            engine, val);
4253
4254         return val != 0;
4255 }
4256
4257 static void _print_parity(struct bnx2x *bp, u32 reg)
4258 {
4259         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4260 }
4261
4262 static void _print_next_block(int idx, const char *blk)
4263 {
4264         pr_cont("%s%s", idx ? ", " : "", blk);
4265 }
4266
4267 static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4268                                             int par_num, bool print)
4269 {
4270         int i = 0;
4271         u32 cur_bit = 0;
4272         for (i = 0; sig; i++) {
4273                 cur_bit = ((u32)0x1 << i);
4274                 if (sig & cur_bit) {
4275                         switch (cur_bit) {
4276                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4277                                 if (print) {
4278                                         _print_next_block(par_num++, "BRB");
4279                                         _print_parity(bp,
4280                                                       BRB1_REG_BRB1_PRTY_STS);
4281                                 }
4282                                 break;
4283                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4284                                 if (print) {
4285                                         _print_next_block(par_num++, "PARSER");
4286                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4287                                 }
4288                                 break;
4289                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4290                                 if (print) {
4291                                         _print_next_block(par_num++, "TSDM");
4292                                         _print_parity(bp,
4293                                                       TSDM_REG_TSDM_PRTY_STS);
4294                                 }
4295                                 break;
4296                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4297                                 if (print) {
4298                                         _print_next_block(par_num++,
4299                                                           "SEARCHER");
4300                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4301                                 }
4302                                 break;
4303                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4304                                 if (print) {
4305                                         _print_next_block(par_num++, "TCM");
4306                                         _print_parity(bp,
4307                                                       TCM_REG_TCM_PRTY_STS);
4308                                 }
4309                                 break;
4310                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4311                                 if (print) {
4312                                         _print_next_block(par_num++, "TSEMI");
4313                                         _print_parity(bp,
4314                                                       TSEM_REG_TSEM_PRTY_STS_0);
4315                                         _print_parity(bp,
4316                                                       TSEM_REG_TSEM_PRTY_STS_1);
4317                                 }
4318                                 break;
4319                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4320                                 if (print) {
4321                                         _print_next_block(par_num++, "XPB");
4322                                         _print_parity(bp, GRCBASE_XPB +
4323                                                           PB_REG_PB_PRTY_STS);
4324                                 }
4325                                 break;
4326                         }
4327
4328                         /* Clear the bit */
4329                         sig &= ~cur_bit;
4330                 }
4331         }
4332
4333         return par_num;
4334 }
4335
4336 static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4337                                             int par_num, bool *global,
4338                                             bool print)
4339 {
4340         int i = 0;
4341         u32 cur_bit = 0;
4342         for (i = 0; sig; i++) {
4343                 cur_bit = ((u32)0x1 << i);
4344                 if (sig & cur_bit) {
4345                         switch (cur_bit) {
4346                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4347                                 if (print) {
4348                                         _print_next_block(par_num++, "PBF");
4349                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4350                                 }
4351                                 break;
4352                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4353                                 if (print) {
4354                                         _print_next_block(par_num++, "QM");
4355                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4356                                 }
4357                                 break;
4358                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4359                                 if (print) {
4360                                         _print_next_block(par_num++, "TM");
4361                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4362                                 }
4363                                 break;
4364                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4365                                 if (print) {
4366                                         _print_next_block(par_num++, "XSDM");
4367                                         _print_parity(bp,
4368                                                       XSDM_REG_XSDM_PRTY_STS);
4369                                 }
4370                                 break;
4371                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4372                                 if (print) {
4373                                         _print_next_block(par_num++, "XCM");
4374                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4375                                 }
4376                                 break;
4377                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4378                                 if (print) {
4379                                         _print_next_block(par_num++, "XSEMI");
4380                                         _print_parity(bp,
4381                                                       XSEM_REG_XSEM_PRTY_STS_0);
4382                                         _print_parity(bp,
4383                                                       XSEM_REG_XSEM_PRTY_STS_1);
4384                                 }
4385                                 break;
4386                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4387                                 if (print) {
4388                                         _print_next_block(par_num++,
4389                                                           "DOORBELLQ");
4390                                         _print_parity(bp,
4391                                                       DORQ_REG_DORQ_PRTY_STS);
4392                                 }
4393                                 break;
4394                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4395                                 if (print) {
4396                                         _print_next_block(par_num++, "NIG");
4397                                         if (CHIP_IS_E1x(bp)) {
4398                                                 _print_parity(bp,
4399                                                         NIG_REG_NIG_PRTY_STS);
4400                                         } else {
4401                                                 _print_parity(bp,
4402                                                         NIG_REG_NIG_PRTY_STS_0);
4403                                                 _print_parity(bp,
4404                                                         NIG_REG_NIG_PRTY_STS_1);
4405                                         }
4406                                 }
4407                                 break;
4408                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4409                                 if (print)
4410                                         _print_next_block(par_num++,
4411                                                           "VAUX PCI CORE");
4412                                 *global = true;
4413                                 break;
4414                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4415                                 if (print) {
4416                                         _print_next_block(par_num++, "DEBUG");
4417                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4418                                 }
4419                                 break;
4420                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4421                                 if (print) {
4422                                         _print_next_block(par_num++, "USDM");
4423                                         _print_parity(bp,
4424                                                       USDM_REG_USDM_PRTY_STS);
4425                                 }
4426                                 break;
4427                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4428                                 if (print) {
4429                                         _print_next_block(par_num++, "UCM");
4430                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4431                                 }
4432                                 break;
4433                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4434                                 if (print) {
4435                                         _print_next_block(par_num++, "USEMI");
4436                                         _print_parity(bp,
4437                                                       USEM_REG_USEM_PRTY_STS_0);
4438                                         _print_parity(bp,
4439                                                       USEM_REG_USEM_PRTY_STS_1);
4440                                 }
4441                                 break;
4442                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4443                                 if (print) {
4444                                         _print_next_block(par_num++, "UPB");
4445                                         _print_parity(bp, GRCBASE_UPB +
4446                                                           PB_REG_PB_PRTY_STS);
4447                                 }
4448                                 break;
4449                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4450                                 if (print) {
4451                                         _print_next_block(par_num++, "CSDM");
4452                                         _print_parity(bp,
4453                                                       CSDM_REG_CSDM_PRTY_STS);
4454                                 }
4455                                 break;
4456                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4457                                 if (print) {
4458                                         _print_next_block(par_num++, "CCM");
4459                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4460                                 }
4461                                 break;
4462                         }
4463
4464                         /* Clear the bit */
4465                         sig &= ~cur_bit;
4466                 }
4467         }
4468
4469         return par_num;
4470 }
4471
4472 static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4473                                             int par_num, bool print)
4474 {
4475         int i = 0;
4476         u32 cur_bit = 0;
4477         for (i = 0; sig; i++) {
4478                 cur_bit = ((u32)0x1 << i);
4479                 if (sig & cur_bit) {
4480                         switch (cur_bit) {
4481                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4482                                 if (print) {
4483                                         _print_next_block(par_num++, "CSEMI");
4484                                         _print_parity(bp,
4485                                                       CSEM_REG_CSEM_PRTY_STS_0);
4486                                         _print_parity(bp,
4487                                                       CSEM_REG_CSEM_PRTY_STS_1);
4488                                 }
4489                                 break;
4490                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4491                                 if (print) {
4492                                         _print_next_block(par_num++, "PXP");
4493                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4494                                         _print_parity(bp,
4495                                                       PXP2_REG_PXP2_PRTY_STS_0);
4496                                         _print_parity(bp,
4497                                                       PXP2_REG_PXP2_PRTY_STS_1);
4498                                 }
4499                                 break;
4500                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4501                                 if (print)
4502                                         _print_next_block(par_num++,
4503                                         "PXPPCICLOCKCLIENT");
4504                                 break;
4505                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4506                                 if (print) {
4507                                         _print_next_block(par_num++, "CFC");
4508                                         _print_parity(bp,
4509                                                       CFC_REG_CFC_PRTY_STS);
4510                                 }
4511                                 break;
4512                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4513                                 if (print) {
4514                                         _print_next_block(par_num++, "CDU");
4515                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4516                                 }
4517                                 break;
4518                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4519                                 if (print) {
4520                                         _print_next_block(par_num++, "DMAE");
4521                                         _print_parity(bp,
4522                                                       DMAE_REG_DMAE_PRTY_STS);
4523                                 }
4524                                 break;
4525                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4526                                 if (print) {
4527                                         _print_next_block(par_num++, "IGU");
4528                                         if (CHIP_IS_E1x(bp))
4529                                                 _print_parity(bp,
4530                                                         HC_REG_HC_PRTY_STS);
4531                                         else
4532                                                 _print_parity(bp,
4533                                                         IGU_REG_IGU_PRTY_STS);
4534                                 }
4535                                 break;
4536                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4537                                 if (print) {
4538                                         _print_next_block(par_num++, "MISC");
4539                                         _print_parity(bp,
4540                                                       MISC_REG_MISC_PRTY_STS);
4541                                 }
4542                                 break;
4543                         }
4544
4545                         /* Clear the bit */
4546                         sig &= ~cur_bit;
4547                 }
4548         }
4549
4550         return par_num;
4551 }
4552
4553 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4554                                            bool *global, bool print)
4555 {
4556         int i = 0;
4557         u32 cur_bit = 0;
4558         for (i = 0; sig; i++) {
4559                 cur_bit = ((u32)0x1 << i);
4560                 if (sig & cur_bit) {
4561                         switch (cur_bit) {
4562                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4563                                 if (print)
4564                                         _print_next_block(par_num++, "MCP ROM");
4565                                 *global = true;
4566                                 break;
4567                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4568                                 if (print)
4569                                         _print_next_block(par_num++,
4570                                                           "MCP UMP RX");
4571                                 *global = true;
4572                                 break;
4573                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4574                                 if (print)
4575                                         _print_next_block(par_num++,
4576                                                           "MCP UMP TX");
4577                                 *global = true;
4578                                 break;
4579                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4580                                 if (print)
4581                                         _print_next_block(par_num++,
4582                                                           "MCP SCPAD");
4583                                 *global = true;
4584                                 break;
4585                         }
4586
4587                         /* Clear the bit */
4588                         sig &= ~cur_bit;
4589                 }
4590         }
4591
4592         return par_num;
4593 }
4594
4595 static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4596                                             int par_num, bool print)
4597 {
4598         int i = 0;
4599         u32 cur_bit = 0;
4600         for (i = 0; sig; i++) {
4601                 cur_bit = ((u32)0x1 << i);
4602                 if (sig & cur_bit) {
4603                         switch (cur_bit) {
4604                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4605                                 if (print) {
4606                                         _print_next_block(par_num++, "PGLUE_B");
4607                                         _print_parity(bp,
4608                                                 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4609                                 }
4610                                 break;
4611                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4612                                 if (print) {
4613                                         _print_next_block(par_num++, "ATC");
4614                                         _print_parity(bp,
4615                                                       ATC_REG_ATC_PRTY_STS);
4616                                 }
4617                                 break;
4618                         }
4619
4620                         /* Clear the bit */
4621                         sig &= ~cur_bit;
4622                 }
4623         }
4624
4625         return par_num;
4626 }
4627
4628 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4629                               u32 *sig)
4630 {
4631         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4632             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4633             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4634             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4635             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4636                 int par_num = 0;
4637                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4638                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4639                           sig[0] & HW_PRTY_ASSERT_SET_0,
4640                           sig[1] & HW_PRTY_ASSERT_SET_1,
4641                           sig[2] & HW_PRTY_ASSERT_SET_2,
4642                           sig[3] & HW_PRTY_ASSERT_SET_3,
4643                           sig[4] & HW_PRTY_ASSERT_SET_4);
4644                 if (print)
4645                         netdev_err(bp->dev,
4646                                    "Parity errors detected in blocks: ");
4647                 par_num = bnx2x_check_blocks_with_parity0(bp,
4648                         sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4649                 par_num = bnx2x_check_blocks_with_parity1(bp,
4650                         sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4651                 par_num = bnx2x_check_blocks_with_parity2(bp,
4652                         sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4653                 par_num = bnx2x_check_blocks_with_parity3(
4654                         sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4655                 par_num = bnx2x_check_blocks_with_parity4(bp,
4656                         sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4657
4658                 if (print)
4659                         pr_cont("\n");
4660
4661                 return true;
4662         } else
4663                 return false;
4664 }
4665
4666 /**
4667  * bnx2x_chk_parity_attn - checks for parity attentions.
4668  *
4669  * @bp:         driver handle
4670  * @global:     true if there was a global attention
4671  * @print:      show parity attention in syslog
4672  */
4673 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4674 {
4675         struct attn_route attn = { {0} };
4676         int port = BP_PORT(bp);
4677
4678         attn.sig[0] = REG_RD(bp,
4679                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4680                              port*4);
4681         attn.sig[1] = REG_RD(bp,
4682                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4683                              port*4);
4684         attn.sig[2] = REG_RD(bp,
4685                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4686                              port*4);
4687         attn.sig[3] = REG_RD(bp,
4688                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4689                              port*4);
4690
4691         if (!CHIP_IS_E1x(bp))
4692                 attn.sig[4] = REG_RD(bp,
4693                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4694                                      port*4);
4695
4696         return bnx2x_parity_attn(bp, global, print, attn.sig);
4697 }
4698
4699 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4700 {
4701         u32 val;
4702         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4703
4704                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4705                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4706                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4707                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4708                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4709                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4710                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4711                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4712                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4713                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4714                 if (val &
4715                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4716                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4717                 if (val &
4718                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4719                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4720                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4721                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4722                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4723                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4724                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4725                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4726         }
4727         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4728                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4729                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4730                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4731                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4732                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4733                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4734                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4735                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4736                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4737                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4738                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4739                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4740                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4741                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4742         }
4743
4744         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4745                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4746                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4747                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4748                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4749         }
4750 }
4751
4752 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4753 {
4754         struct attn_route attn, *group_mask;
4755         int port = BP_PORT(bp);
4756         int index;
4757         u32 reg_addr;
4758         u32 val;
4759         u32 aeu_mask;
4760         bool global = false;
4761
4762         /* need to take HW lock because MCP or other port might also
4763            try to handle this event */
4764         bnx2x_acquire_alr(bp);
4765
4766         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4767 #ifndef BNX2X_STOP_ON_ERROR
4768                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4769                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4770                 /* Disable HW interrupts */
4771                 bnx2x_int_disable(bp);
4772                 /* In case of parity errors don't handle attentions so that
4773                  * other function would "see" parity errors.
4774                  */
4775 #else
4776                 bnx2x_panic();
4777 #endif
4778                 bnx2x_release_alr(bp);
4779                 return;
4780         }
4781
4782         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4783         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4784         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4785         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4786         if (!CHIP_IS_E1x(bp))
4787                 attn.sig[4] =
4788                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4789         else
4790                 attn.sig[4] = 0;
4791
4792         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4793            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4794
4795         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4796                 if (deasserted & (1 << index)) {
4797                         group_mask = &bp->attn_group[index];
4798
4799                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4800                            index,
4801                            group_mask->sig[0], group_mask->sig[1],
4802                            group_mask->sig[2], group_mask->sig[3],
4803                            group_mask->sig[4]);
4804
4805                         bnx2x_attn_int_deasserted4(bp,
4806                                         attn.sig[4] & group_mask->sig[4]);
4807                         bnx2x_attn_int_deasserted3(bp,
4808                                         attn.sig[3] & group_mask->sig[3]);
4809                         bnx2x_attn_int_deasserted1(bp,
4810                                         attn.sig[1] & group_mask->sig[1]);
4811                         bnx2x_attn_int_deasserted2(bp,
4812                                         attn.sig[2] & group_mask->sig[2]);
4813                         bnx2x_attn_int_deasserted0(bp,
4814                                         attn.sig[0] & group_mask->sig[0]);
4815                 }
4816         }
4817
4818         bnx2x_release_alr(bp);
4819
4820         if (bp->common.int_block == INT_BLOCK_HC)
4821                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4822                             COMMAND_REG_ATTN_BITS_CLR);
4823         else
4824                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4825
4826         val = ~deasserted;
4827         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4828            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4829         REG_WR(bp, reg_addr, val);
4830
4831         if (~bp->attn_state & deasserted)
4832                 BNX2X_ERR("IGU ERROR\n");
4833
4834         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4835                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4836
4837         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4838         aeu_mask = REG_RD(bp, reg_addr);
4839
4840         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4841            aeu_mask, deasserted);
4842         aeu_mask |= (deasserted & 0x3ff);
4843         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4844
4845         REG_WR(bp, reg_addr, aeu_mask);
4846         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4847
4848         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4849         bp->attn_state &= ~deasserted;
4850         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4851 }
4852
4853 static void bnx2x_attn_int(struct bnx2x *bp)
4854 {
4855         /* read local copy of bits */
4856         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4857                                                                 attn_bits);
4858         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4859                                                                 attn_bits_ack);
4860         u32 attn_state = bp->attn_state;
4861
4862         /* look for changed bits */
4863         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4864         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4865
4866         DP(NETIF_MSG_HW,
4867            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4868            attn_bits, attn_ack, asserted, deasserted);
4869
4870         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4871                 BNX2X_ERR("BAD attention state\n");
4872
4873         /* handle bits that were raised */
4874         if (asserted)
4875                 bnx2x_attn_int_asserted(bp, asserted);
4876
4877         if (deasserted)
4878                 bnx2x_attn_int_deasserted(bp, deasserted);
4879 }
4880
4881 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4882                       u16 index, u8 op, u8 update)
4883 {
4884         u32 igu_addr = bp->igu_base_addr;
4885         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4886         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4887                              igu_addr);
4888 }
4889
4890 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4891 {
4892         /* No memory barriers */
4893         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4894         mmiowb(); /* keep prod updates ordered */
4895 }
4896
4897 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4898                                       union event_ring_elem *elem)
4899 {
4900         u8 err = elem->message.error;
4901
4902         if (!bp->cnic_eth_dev.starting_cid  ||
4903             (cid < bp->cnic_eth_dev.starting_cid &&
4904             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4905                 return 1;
4906
4907         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4908
4909         if (unlikely(err)) {
4910
4911                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4912                           cid);
4913                 bnx2x_panic_dump(bp, false);
4914         }
4915         bnx2x_cnic_cfc_comp(bp, cid, err);
4916         return 0;
4917 }
4918
4919 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4920 {
4921         struct bnx2x_mcast_ramrod_params rparam;
4922         int rc;
4923
4924         memset(&rparam, 0, sizeof(rparam));
4925
4926         rparam.mcast_obj = &bp->mcast_obj;
4927
4928         netif_addr_lock_bh(bp->dev);
4929
4930         /* Clear pending state for the last command */
4931         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4932
4933         /* If there are pending mcast commands - send them */
4934         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4935                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4936                 if (rc < 0)
4937                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4938                                   rc);
4939         }
4940
4941         netif_addr_unlock_bh(bp->dev);
4942 }
4943
4944 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4945                                             union event_ring_elem *elem)
4946 {
4947         unsigned long ramrod_flags = 0;
4948         int rc = 0;
4949         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4950         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4951
4952         /* Always push next commands out, don't wait here */
4953         __set_bit(RAMROD_CONT, &ramrod_flags);
4954
4955         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
4956                             >> BNX2X_SWCID_SHIFT) {
4957         case BNX2X_FILTER_MAC_PENDING:
4958                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4959                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4960                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4961                 else
4962                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4963
4964                 break;
4965         case BNX2X_FILTER_MCAST_PENDING:
4966                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4967                 /* This is only relevant for 57710 where multicast MACs are
4968                  * configured as unicast MACs using the same ramrod.
4969                  */
4970                 bnx2x_handle_mcast_eqe(bp);
4971                 return;
4972         default:
4973                 BNX2X_ERR("Unsupported classification command: %d\n",
4974                           elem->message.data.eth_event.echo);
4975                 return;
4976         }
4977
4978         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4979
4980         if (rc < 0)
4981                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4982         else if (rc > 0)
4983                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4984 }
4985
4986 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4987
4988 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4989 {
4990         netif_addr_lock_bh(bp->dev);
4991
4992         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4993
4994         /* Send rx_mode command again if was requested */
4995         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4996                 bnx2x_set_storm_rx_mode(bp);
4997         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4998                                     &bp->sp_state))
4999                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5000         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5001                                     &bp->sp_state))
5002                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5003
5004         netif_addr_unlock_bh(bp->dev);
5005 }
5006
5007 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5008                                               union event_ring_elem *elem)
5009 {
5010         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5011                 DP(BNX2X_MSG_SP,
5012                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5013                    elem->message.data.vif_list_event.func_bit_map);
5014                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5015                         elem->message.data.vif_list_event.func_bit_map);
5016         } else if (elem->message.data.vif_list_event.echo ==
5017                    VIF_LIST_RULE_SET) {
5018                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5019                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5020         }
5021 }
5022
5023 /* called with rtnl_lock */
5024 static void bnx2x_after_function_update(struct bnx2x *bp)
5025 {
5026         int q, rc;
5027         struct bnx2x_fastpath *fp;
5028         struct bnx2x_queue_state_params queue_params = {NULL};
5029         struct bnx2x_queue_update_params *q_update_params =
5030                 &queue_params.params.update;
5031
5032         /* Send Q update command with afex vlan removal values for all Qs */
5033         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5034
5035         /* set silent vlan removal values according to vlan mode */
5036         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5037                   &q_update_params->update_flags);
5038         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5039                   &q_update_params->update_flags);
5040         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5041
5042         /* in access mode mark mask and value are 0 to strip all vlans */
5043         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5044                 q_update_params->silent_removal_value = 0;
5045                 q_update_params->silent_removal_mask = 0;
5046         } else {
5047                 q_update_params->silent_removal_value =
5048                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5049                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5050         }
5051
5052         for_each_eth_queue(bp, q) {
5053                 /* Set the appropriate Queue object */
5054                 fp = &bp->fp[q];
5055                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5056
5057                 /* send the ramrod */
5058                 rc = bnx2x_queue_state_change(bp, &queue_params);
5059                 if (rc < 0)
5060                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5061                                   q);
5062         }
5063
5064         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5065                 fp = &bp->fp[FCOE_IDX(bp)];
5066                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5067
5068                 /* clear pending completion bit */
5069                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5070
5071                 /* mark latest Q bit */
5072                 smp_mb__before_clear_bit();
5073                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5074                 smp_mb__after_clear_bit();
5075
5076                 /* send Q update ramrod for FCoE Q */
5077                 rc = bnx2x_queue_state_change(bp, &queue_params);
5078                 if (rc < 0)
5079                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5080                                   q);
5081         } else {
5082                 /* If no FCoE ring - ACK MCP now */
5083                 bnx2x_link_report(bp);
5084                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5085         }
5086 }
5087
5088 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5089         struct bnx2x *bp, u32 cid)
5090 {
5091         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5092
5093         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5094                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5095         else
5096                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5097 }
5098
5099 static void bnx2x_eq_int(struct bnx2x *bp)
5100 {
5101         u16 hw_cons, sw_cons, sw_prod;
5102         union event_ring_elem *elem;
5103         u8 echo;
5104         u32 cid;
5105         u8 opcode;
5106         int rc, spqe_cnt = 0;
5107         struct bnx2x_queue_sp_obj *q_obj;
5108         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5109         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5110
5111         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5112
5113         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5114          * when we get the next-page we need to adjust so the loop
5115          * condition below will be met. The next element is the size of a
5116          * regular element and hence incrementing by 1
5117          */
5118         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5119                 hw_cons++;
5120
5121         /* This function may never run in parallel with itself for a
5122          * specific bp, thus there is no need in "paired" read memory
5123          * barrier here.
5124          */
5125         sw_cons = bp->eq_cons;
5126         sw_prod = bp->eq_prod;
5127
5128         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5129                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5130
5131         for (; sw_cons != hw_cons;
5132               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5133
5134                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5135
5136                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5137                 if (!rc) {
5138                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5139                            rc);
5140                         goto next_spqe;
5141                 }
5142
5143                 /* elem CID originates from FW; actually LE */
5144                 cid = SW_CID((__force __le32)
5145                              elem->message.data.cfc_del_event.cid);
5146                 opcode = elem->message.opcode;
5147
5148                 /* handle eq element */
5149                 switch (opcode) {
5150                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5151                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5152                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5153                         continue;
5154
5155                 case EVENT_RING_OPCODE_STAT_QUERY:
5156                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5157                            "got statistics comp event %d\n",
5158                            bp->stats_comp++);
5159                         /* nothing to do with stats comp */
5160                         goto next_spqe;
5161
5162                 case EVENT_RING_OPCODE_CFC_DEL:
5163                         /* handle according to cid range */
5164                         /*
5165                          * we may want to verify here that the bp state is
5166                          * HALTING
5167                          */
5168                         DP(BNX2X_MSG_SP,
5169                            "got delete ramrod for MULTI[%d]\n", cid);
5170
5171                         if (CNIC_LOADED(bp) &&
5172                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5173                                 goto next_spqe;
5174
5175                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5176
5177                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5178                                 break;
5179
5180                         goto next_spqe;
5181
5182                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5183                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5184                         if (f_obj->complete_cmd(bp, f_obj,
5185                                                 BNX2X_F_CMD_TX_STOP))
5186                                 break;
5187                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5188                         goto next_spqe;
5189
5190                 case EVENT_RING_OPCODE_START_TRAFFIC:
5191                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5192                         if (f_obj->complete_cmd(bp, f_obj,
5193                                                 BNX2X_F_CMD_TX_START))
5194                                 break;
5195                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5196                         goto next_spqe;
5197
5198                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5199                         echo = elem->message.data.function_update_event.echo;
5200                         if (echo == SWITCH_UPDATE) {
5201                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5202                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5203                                 if (f_obj->complete_cmd(
5204                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5205                                         break;
5206
5207                         } else {
5208                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5209                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5210                                 f_obj->complete_cmd(bp, f_obj,
5211                                                     BNX2X_F_CMD_AFEX_UPDATE);
5212
5213                                 /* We will perform the Queues update from
5214                                  * sp_rtnl task as all Queue SP operations
5215                                  * should run under rtnl_lock.
5216                                  */
5217                                 smp_mb__before_clear_bit();
5218                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5219                                         &bp->sp_rtnl_state);
5220                                 smp_mb__after_clear_bit();
5221
5222                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5223                         }
5224
5225                         goto next_spqe;
5226
5227                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5228                         f_obj->complete_cmd(bp, f_obj,
5229                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5230                         bnx2x_after_afex_vif_lists(bp, elem);
5231                         goto next_spqe;
5232                 case EVENT_RING_OPCODE_FUNCTION_START:
5233                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5234                            "got FUNC_START ramrod\n");
5235                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5236                                 break;
5237
5238                         goto next_spqe;
5239
5240                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5241                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5242                            "got FUNC_STOP ramrod\n");
5243                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5244                                 break;
5245
5246                         goto next_spqe;
5247                 }
5248
5249                 switch (opcode | bp->state) {
5250                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5251                       BNX2X_STATE_OPEN):
5252                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5253                       BNX2X_STATE_OPENING_WAIT4_PORT):
5254                         cid = elem->message.data.eth_event.echo &
5255                                 BNX2X_SWCID_MASK;
5256                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5257                            cid);
5258                         rss_raw->clear_pending(rss_raw);
5259                         break;
5260
5261                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5262                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5263                 case (EVENT_RING_OPCODE_SET_MAC |
5264                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5265                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5266                       BNX2X_STATE_OPEN):
5267                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5268                       BNX2X_STATE_DIAG):
5269                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5270                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5271                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5272                         bnx2x_handle_classification_eqe(bp, elem);
5273                         break;
5274
5275                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5276                       BNX2X_STATE_OPEN):
5277                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5278                       BNX2X_STATE_DIAG):
5279                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5280                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5281                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5282                         bnx2x_handle_mcast_eqe(bp);
5283                         break;
5284
5285                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5286                       BNX2X_STATE_OPEN):
5287                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5288                       BNX2X_STATE_DIAG):
5289                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5290                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5291                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5292                         bnx2x_handle_rx_mode_eqe(bp);
5293                         break;
5294                 default:
5295                         /* unknown event log error and continue */
5296                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5297                                   elem->message.opcode, bp->state);
5298                 }
5299 next_spqe:
5300                 spqe_cnt++;
5301         } /* for */
5302
5303         smp_mb__before_atomic_inc();
5304         atomic_add(spqe_cnt, &bp->eq_spq_left);
5305
5306         bp->eq_cons = sw_cons;
5307         bp->eq_prod = sw_prod;
5308         /* Make sure that above mem writes were issued towards the memory */
5309         smp_wmb();
5310
5311         /* update producer */
5312         bnx2x_update_eq_prod(bp, bp->eq_prod);
5313 }
5314
5315 static void bnx2x_sp_task(struct work_struct *work)
5316 {
5317         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5318
5319         DP(BNX2X_MSG_SP, "sp task invoked\n");
5320
5321         /* make sure the atomic interrupt_occurred has been written */
5322         smp_rmb();
5323         if (atomic_read(&bp->interrupt_occurred)) {
5324
5325                 /* what work needs to be performed? */
5326                 u16 status = bnx2x_update_dsb_idx(bp);
5327
5328                 DP(BNX2X_MSG_SP, "status %x\n", status);
5329                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5330                 atomic_set(&bp->interrupt_occurred, 0);
5331
5332                 /* HW attentions */
5333                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5334                         bnx2x_attn_int(bp);
5335                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5336                 }
5337
5338                 /* SP events: STAT_QUERY and others */
5339                 if (status & BNX2X_DEF_SB_IDX) {
5340                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5341
5342                 if (FCOE_INIT(bp) &&
5343                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5344                                 /* Prevent local bottom-halves from running as
5345                                  * we are going to change the local NAPI list.
5346                                  */
5347                                 local_bh_disable();
5348                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5349                                 local_bh_enable();
5350                         }
5351
5352                         /* Handle EQ completions */
5353                         bnx2x_eq_int(bp);
5354                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5355                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5356
5357                         status &= ~BNX2X_DEF_SB_IDX;
5358                 }
5359
5360                 /* if status is non zero then perhaps something went wrong */
5361                 if (unlikely(status))
5362                         DP(BNX2X_MSG_SP,
5363                            "got an unknown interrupt! (status 0x%x)\n", status);
5364
5365                 /* ack status block only if something was actually handled */
5366                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5367                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5368         }
5369
5370         /* must be called after the EQ processing (since eq leads to sriov
5371          * ramrod completion flows).
5372          * This flow may have been scheduled by the arrival of a ramrod
5373          * completion, or by the sriov code rescheduling itself.
5374          */
5375         bnx2x_iov_sp_task(bp);
5376
5377         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5378         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5379                                &bp->sp_state)) {
5380                 bnx2x_link_report(bp);
5381                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5382         }
5383 }
5384
5385 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5386 {
5387         struct net_device *dev = dev_instance;
5388         struct bnx2x *bp = netdev_priv(dev);
5389
5390         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5391                      IGU_INT_DISABLE, 0);
5392
5393 #ifdef BNX2X_STOP_ON_ERROR
5394         if (unlikely(bp->panic))
5395                 return IRQ_HANDLED;
5396 #endif
5397
5398         if (CNIC_LOADED(bp)) {
5399                 struct cnic_ops *c_ops;
5400
5401                 rcu_read_lock();
5402                 c_ops = rcu_dereference(bp->cnic_ops);
5403                 if (c_ops)
5404                         c_ops->cnic_handler(bp->cnic_data, NULL);
5405                 rcu_read_unlock();
5406         }
5407
5408         /* schedule sp task to perform default status block work, ack
5409          * attentions and enable interrupts.
5410          */
5411         bnx2x_schedule_sp_task(bp);
5412
5413         return IRQ_HANDLED;
5414 }
5415
5416 /* end of slow path */
5417
5418 void bnx2x_drv_pulse(struct bnx2x *bp)
5419 {
5420         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5421                  bp->fw_drv_pulse_wr_seq);
5422 }
5423
5424 static void bnx2x_timer(unsigned long data)
5425 {
5426         struct bnx2x *bp = (struct bnx2x *) data;
5427
5428         if (!netif_running(bp->dev))
5429                 return;
5430
5431         if (IS_PF(bp) &&
5432             !BP_NOMCP(bp)) {
5433                 int mb_idx = BP_FW_MB_IDX(bp);
5434                 u32 drv_pulse;
5435                 u32 mcp_pulse;
5436
5437                 ++bp->fw_drv_pulse_wr_seq;
5438                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5439                 /* TBD - add SYSTEM_TIME */
5440                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5441                 bnx2x_drv_pulse(bp);
5442
5443                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5444                              MCP_PULSE_SEQ_MASK);
5445                 /* The delta between driver pulse and mcp response
5446                  * should be 1 (before mcp response) or 0 (after mcp response)
5447                  */
5448                 if ((drv_pulse != mcp_pulse) &&
5449                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5450                         /* someone lost a heartbeat... */
5451                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5452                                   drv_pulse, mcp_pulse);
5453                 }
5454         }
5455
5456         if (bp->state == BNX2X_STATE_OPEN)
5457                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5458
5459         /* sample pf vf bulletin board for new posts from pf */
5460         if (IS_VF(bp))
5461                 bnx2x_sample_bulletin(bp);
5462
5463         mod_timer(&bp->timer, jiffies + bp->current_interval);
5464 }
5465
5466 /* end of Statistics */
5467
5468 /* nic init */
5469
5470 /*
5471  * nic init service functions
5472  */
5473
5474 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5475 {
5476         u32 i;
5477         if (!(len%4) && !(addr%4))
5478                 for (i = 0; i < len; i += 4)
5479                         REG_WR(bp, addr + i, fill);
5480         else
5481                 for (i = 0; i < len; i++)
5482                         REG_WR8(bp, addr + i, fill);
5483 }
5484
5485 /* helper: writes FP SP data to FW - data_size in dwords */
5486 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5487                                 int fw_sb_id,
5488                                 u32 *sb_data_p,
5489                                 u32 data_size)
5490 {
5491         int index;
5492         for (index = 0; index < data_size; index++)
5493                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5494                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5495                         sizeof(u32)*index,
5496                         *(sb_data_p + index));
5497 }
5498
5499 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5500 {
5501         u32 *sb_data_p;
5502         u32 data_size = 0;
5503         struct hc_status_block_data_e2 sb_data_e2;
5504         struct hc_status_block_data_e1x sb_data_e1x;
5505
5506         /* disable the function first */
5507         if (!CHIP_IS_E1x(bp)) {
5508                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5509                 sb_data_e2.common.state = SB_DISABLED;
5510                 sb_data_e2.common.p_func.vf_valid = false;
5511                 sb_data_p = (u32 *)&sb_data_e2;
5512                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5513         } else {
5514                 memset(&sb_data_e1x, 0,
5515                        sizeof(struct hc_status_block_data_e1x));
5516                 sb_data_e1x.common.state = SB_DISABLED;
5517                 sb_data_e1x.common.p_func.vf_valid = false;
5518                 sb_data_p = (u32 *)&sb_data_e1x;
5519                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5520         }
5521         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5522
5523         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5524                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5525                         CSTORM_STATUS_BLOCK_SIZE);
5526         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5527                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5528                         CSTORM_SYNC_BLOCK_SIZE);
5529 }
5530
5531 /* helper:  writes SP SB data to FW */
5532 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5533                 struct hc_sp_status_block_data *sp_sb_data)
5534 {
5535         int func = BP_FUNC(bp);
5536         int i;
5537         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5538                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5539                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5540                         i*sizeof(u32),
5541                         *((u32 *)sp_sb_data + i));
5542 }
5543
5544 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5545 {
5546         int func = BP_FUNC(bp);
5547         struct hc_sp_status_block_data sp_sb_data;
5548         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5549
5550         sp_sb_data.state = SB_DISABLED;
5551         sp_sb_data.p_func.vf_valid = false;
5552
5553         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5554
5555         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5556                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5557                         CSTORM_SP_STATUS_BLOCK_SIZE);
5558         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5559                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5560                         CSTORM_SP_SYNC_BLOCK_SIZE);
5561 }
5562
5563 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5564                                            int igu_sb_id, int igu_seg_id)
5565 {
5566         hc_sm->igu_sb_id = igu_sb_id;
5567         hc_sm->igu_seg_id = igu_seg_id;
5568         hc_sm->timer_value = 0xFF;
5569         hc_sm->time_to_expire = 0xFFFFFFFF;
5570 }
5571
5572 /* allocates state machine ids. */
5573 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5574 {
5575         /* zero out state machine indices */
5576         /* rx indices */
5577         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5578
5579         /* tx indices */
5580         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5581         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5582         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5583         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5584
5585         /* map indices */
5586         /* rx indices */
5587         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5588                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5589
5590         /* tx indices */
5591         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5592                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5593         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5594                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5595         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5596                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5597         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5598                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5599 }
5600
5601 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5602                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5603 {
5604         int igu_seg_id;
5605
5606         struct hc_status_block_data_e2 sb_data_e2;
5607         struct hc_status_block_data_e1x sb_data_e1x;
5608         struct hc_status_block_sm  *hc_sm_p;
5609         int data_size;
5610         u32 *sb_data_p;
5611
5612         if (CHIP_INT_MODE_IS_BC(bp))
5613                 igu_seg_id = HC_SEG_ACCESS_NORM;
5614         else
5615                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5616
5617         bnx2x_zero_fp_sb(bp, fw_sb_id);
5618
5619         if (!CHIP_IS_E1x(bp)) {
5620                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5621                 sb_data_e2.common.state = SB_ENABLED;
5622                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5623                 sb_data_e2.common.p_func.vf_id = vfid;
5624                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5625                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5626                 sb_data_e2.common.same_igu_sb_1b = true;
5627                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5628                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5629                 hc_sm_p = sb_data_e2.common.state_machine;
5630                 sb_data_p = (u32 *)&sb_data_e2;
5631                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5632                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5633         } else {
5634                 memset(&sb_data_e1x, 0,
5635                        sizeof(struct hc_status_block_data_e1x));
5636                 sb_data_e1x.common.state = SB_ENABLED;
5637                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5638                 sb_data_e1x.common.p_func.vf_id = 0xff;
5639                 sb_data_e1x.common.p_func.vf_valid = false;
5640                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5641                 sb_data_e1x.common.same_igu_sb_1b = true;
5642                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5643                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5644                 hc_sm_p = sb_data_e1x.common.state_machine;
5645                 sb_data_p = (u32 *)&sb_data_e1x;
5646                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5647                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5648         }
5649
5650         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5651                                        igu_sb_id, igu_seg_id);
5652         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5653                                        igu_sb_id, igu_seg_id);
5654
5655         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5656
5657         /* write indices to HW - PCI guarantees endianity of regpairs */
5658         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5659 }
5660
5661 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5662                                      u16 tx_usec, u16 rx_usec)
5663 {
5664         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5665                                     false, rx_usec);
5666         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5667                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5668                                        tx_usec);
5669         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5670                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5671                                        tx_usec);
5672         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5673                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5674                                        tx_usec);
5675 }
5676
5677 static void bnx2x_init_def_sb(struct bnx2x *bp)
5678 {
5679         struct host_sp_status_block *def_sb = bp->def_status_blk;
5680         dma_addr_t mapping = bp->def_status_blk_mapping;
5681         int igu_sp_sb_index;
5682         int igu_seg_id;
5683         int port = BP_PORT(bp);
5684         int func = BP_FUNC(bp);
5685         int reg_offset, reg_offset_en5;
5686         u64 section;
5687         int index;
5688         struct hc_sp_status_block_data sp_sb_data;
5689         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5690
5691         if (CHIP_INT_MODE_IS_BC(bp)) {
5692                 igu_sp_sb_index = DEF_SB_IGU_ID;
5693                 igu_seg_id = HC_SEG_ACCESS_DEF;
5694         } else {
5695                 igu_sp_sb_index = bp->igu_dsb_id;
5696                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5697         }
5698
5699         /* ATTN */
5700         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5701                                             atten_status_block);
5702         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5703
5704         bp->attn_state = 0;
5705
5706         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5707                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5708         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5709                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5710         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5711                 int sindex;
5712                 /* take care of sig[0]..sig[4] */
5713                 for (sindex = 0; sindex < 4; sindex++)
5714                         bp->attn_group[index].sig[sindex] =
5715                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5716
5717                 if (!CHIP_IS_E1x(bp))
5718                         /*
5719                          * enable5 is separate from the rest of the registers,
5720                          * and therefore the address skip is 4
5721                          * and not 16 between the different groups
5722                          */
5723                         bp->attn_group[index].sig[4] = REG_RD(bp,
5724                                         reg_offset_en5 + 0x4*index);
5725                 else
5726                         bp->attn_group[index].sig[4] = 0;
5727         }
5728
5729         if (bp->common.int_block == INT_BLOCK_HC) {
5730                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5731                                      HC_REG_ATTN_MSG0_ADDR_L);
5732
5733                 REG_WR(bp, reg_offset, U64_LO(section));
5734                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5735         } else if (!CHIP_IS_E1x(bp)) {
5736                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5737                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5738         }
5739
5740         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5741                                             sp_sb);
5742
5743         bnx2x_zero_sp_sb(bp);
5744
5745         /* PCI guarantees endianity of regpairs */
5746         sp_sb_data.state                = SB_ENABLED;
5747         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5748         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5749         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5750         sp_sb_data.igu_seg_id           = igu_seg_id;
5751         sp_sb_data.p_func.pf_id         = func;
5752         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5753         sp_sb_data.p_func.vf_id         = 0xff;
5754
5755         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5756
5757         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5758 }
5759
5760 void bnx2x_update_coalesce(struct bnx2x *bp)
5761 {
5762         int i;
5763
5764         for_each_eth_queue(bp, i)
5765                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5766                                          bp->tx_ticks, bp->rx_ticks);
5767 }
5768
5769 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5770 {
5771         spin_lock_init(&bp->spq_lock);
5772         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5773
5774         bp->spq_prod_idx = 0;
5775         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5776         bp->spq_prod_bd = bp->spq;
5777         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5778 }
5779
5780 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5781 {
5782         int i;
5783         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5784                 union event_ring_elem *elem =
5785                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5786
5787                 elem->next_page.addr.hi =
5788                         cpu_to_le32(U64_HI(bp->eq_mapping +
5789                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5790                 elem->next_page.addr.lo =
5791                         cpu_to_le32(U64_LO(bp->eq_mapping +
5792                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5793         }
5794         bp->eq_cons = 0;
5795         bp->eq_prod = NUM_EQ_DESC;
5796         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5797         /* we want a warning message before it gets wrought... */
5798         atomic_set(&bp->eq_spq_left,
5799                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5800 }
5801
5802 /* called with netif_addr_lock_bh() */
5803 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5804                         unsigned long rx_mode_flags,
5805                         unsigned long rx_accept_flags,
5806                         unsigned long tx_accept_flags,
5807                         unsigned long ramrod_flags)
5808 {
5809         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5810         int rc;
5811
5812         memset(&ramrod_param, 0, sizeof(ramrod_param));
5813
5814         /* Prepare ramrod parameters */
5815         ramrod_param.cid = 0;
5816         ramrod_param.cl_id = cl_id;
5817         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5818         ramrod_param.func_id = BP_FUNC(bp);
5819
5820         ramrod_param.pstate = &bp->sp_state;
5821         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5822
5823         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5824         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5825
5826         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5827
5828         ramrod_param.ramrod_flags = ramrod_flags;
5829         ramrod_param.rx_mode_flags = rx_mode_flags;
5830
5831         ramrod_param.rx_accept_flags = rx_accept_flags;
5832         ramrod_param.tx_accept_flags = tx_accept_flags;
5833
5834         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5835         if (rc < 0) {
5836                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5837                 return rc;
5838         }
5839
5840         return 0;
5841 }
5842
5843 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5844                                    unsigned long *rx_accept_flags,
5845                                    unsigned long *tx_accept_flags)
5846 {
5847         /* Clear the flags first */
5848         *rx_accept_flags = 0;
5849         *tx_accept_flags = 0;
5850
5851         switch (rx_mode) {
5852         case BNX2X_RX_MODE_NONE:
5853                 /*
5854                  * 'drop all' supersedes any accept flags that may have been
5855                  * passed to the function.
5856                  */
5857                 break;
5858         case BNX2X_RX_MODE_NORMAL:
5859                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5860                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5861                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5862
5863                 /* internal switching mode */
5864                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5865                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5866                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5867
5868                 break;
5869         case BNX2X_RX_MODE_ALLMULTI:
5870                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5871                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5872                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5873
5874                 /* internal switching mode */
5875                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5876                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5877                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5878
5879                 break;
5880         case BNX2X_RX_MODE_PROMISC:
5881                 /* According to definition of SI mode, iface in promisc mode
5882                  * should receive matched and unmatched (in resolution of port)
5883                  * unicast packets.
5884                  */
5885                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5886                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5887                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5888                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5889
5890                 /* internal switching mode */
5891                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5892                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5893
5894                 if (IS_MF_SI(bp))
5895                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5896                 else
5897                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5898
5899                 break;
5900         default:
5901                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5902                 return -EINVAL;
5903         }
5904
5905         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5906         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5907                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5908                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5909         }
5910
5911         return 0;
5912 }
5913
5914 /* called with netif_addr_lock_bh() */
5915 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5916 {
5917         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5918         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5919         int rc;
5920
5921         if (!NO_FCOE(bp))
5922                 /* Configure rx_mode of FCoE Queue */
5923                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5924
5925         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5926                                      &tx_accept_flags);
5927         if (rc)
5928                 return rc;
5929
5930         __set_bit(RAMROD_RX, &ramrod_flags);
5931         __set_bit(RAMROD_TX, &ramrod_flags);
5932
5933         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5934                                    rx_accept_flags, tx_accept_flags,
5935                                    ramrod_flags);
5936 }
5937
5938 static void bnx2x_init_internal_common(struct bnx2x *bp)
5939 {
5940         int i;
5941
5942         if (IS_MF_SI(bp))
5943                 /*
5944                  * In switch independent mode, the TSTORM needs to accept
5945                  * packets that failed classification, since approximate match
5946                  * mac addresses aren't written to NIG LLH
5947                  */
5948                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5949                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5950         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5951                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5952                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5953
5954         /* Zero this manually as its initialization is
5955            currently missing in the initTool */
5956         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5957                 REG_WR(bp, BAR_USTRORM_INTMEM +
5958                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
5959         if (!CHIP_IS_E1x(bp)) {
5960                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5961                         CHIP_INT_MODE_IS_BC(bp) ?
5962                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5963         }
5964 }
5965
5966 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5967 {
5968         switch (load_code) {
5969         case FW_MSG_CODE_DRV_LOAD_COMMON:
5970         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5971                 bnx2x_init_internal_common(bp);
5972                 /* no break */
5973
5974         case FW_MSG_CODE_DRV_LOAD_PORT:
5975                 /* nothing to do */
5976                 /* no break */
5977
5978         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5979                 /* internal memory per function is
5980                    initialized inside bnx2x_pf_init */
5981                 break;
5982
5983         default:
5984                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5985                 break;
5986         }
5987 }
5988
5989 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5990 {
5991         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5992 }
5993
5994 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5995 {
5996         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5997 }
5998
5999 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6000 {
6001         if (CHIP_IS_E1x(fp->bp))
6002                 return BP_L_ID(fp->bp) + fp->index;
6003         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6004                 return bnx2x_fp_igu_sb_id(fp);
6005 }
6006
6007 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6008 {
6009         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6010         u8 cos;
6011         unsigned long q_type = 0;
6012         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6013         fp->rx_queue = fp_idx;
6014         fp->cid = fp_idx;
6015         fp->cl_id = bnx2x_fp_cl_id(fp);
6016         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6017         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6018         /* qZone id equals to FW (per path) client id */
6019         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6020
6021         /* init shortcut */
6022         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6023
6024         /* Setup SB indices */
6025         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6026
6027         /* Configure Queue State object */
6028         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6029         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6030
6031         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6032
6033         /* init tx data */
6034         for_each_cos_in_tx_queue(fp, cos) {
6035                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6036                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6037                                   FP_COS_TO_TXQ(fp, cos, bp),
6038                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6039                 cids[cos] = fp->txdata_ptr[cos]->cid;
6040         }
6041
6042         /* nothing more for vf to do here */
6043         if (IS_VF(bp))
6044                 return;
6045
6046         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6047                       fp->fw_sb_id, fp->igu_sb_id);
6048         bnx2x_update_fpsb_idx(fp);
6049         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6050                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6051                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6052
6053         /**
6054          * Configure classification DBs: Always enable Tx switching
6055          */
6056         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6057
6058         DP(NETIF_MSG_IFUP,
6059            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6060            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6061            fp->igu_sb_id);
6062 }
6063
6064 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6065 {
6066         int i;
6067
6068         for (i = 1; i <= NUM_TX_RINGS; i++) {
6069                 struct eth_tx_next_bd *tx_next_bd =
6070                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6071
6072                 tx_next_bd->addr_hi =
6073                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6074                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6075                 tx_next_bd->addr_lo =
6076                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6077                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6078         }
6079
6080         *txdata->tx_cons_sb = cpu_to_le16(0);
6081
6082         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6083         txdata->tx_db.data.zero_fill1 = 0;
6084         txdata->tx_db.data.prod = 0;
6085
6086         txdata->tx_pkt_prod = 0;
6087         txdata->tx_pkt_cons = 0;
6088         txdata->tx_bd_prod = 0;
6089         txdata->tx_bd_cons = 0;
6090         txdata->tx_pkt = 0;
6091 }
6092
6093 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6094 {
6095         int i;
6096
6097         for_each_tx_queue_cnic(bp, i)
6098                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6099 }
6100
6101 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6102 {
6103         int i;
6104         u8 cos;
6105
6106         for_each_eth_queue(bp, i)
6107                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6108                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6109 }
6110
6111 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6112 {
6113         if (!NO_FCOE(bp))
6114                 bnx2x_init_fcoe_fp(bp);
6115
6116         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6117                       BNX2X_VF_ID_INVALID, false,
6118                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6119
6120         /* ensure status block indices were read */
6121         rmb();
6122         bnx2x_init_rx_rings_cnic(bp);
6123         bnx2x_init_tx_rings_cnic(bp);
6124
6125         /* flush all */
6126         mb();
6127         mmiowb();
6128 }
6129
6130 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6131 {
6132         int i;
6133
6134         /* Setup NIC internals and enable interrupts */
6135         for_each_eth_queue(bp, i)
6136                 bnx2x_init_eth_fp(bp, i);
6137
6138         /* ensure status block indices were read */
6139         rmb();
6140         bnx2x_init_rx_rings(bp);
6141         bnx2x_init_tx_rings(bp);
6142
6143         if (IS_PF(bp)) {
6144                 /* Initialize MOD_ABS interrupts */
6145                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6146                                        bp->common.shmem_base,
6147                                        bp->common.shmem2_base, BP_PORT(bp));
6148
6149                 /* initialize the default status block and sp ring */
6150                 bnx2x_init_def_sb(bp);
6151                 bnx2x_update_dsb_idx(bp);
6152                 bnx2x_init_sp_ring(bp);
6153         } else {
6154                 bnx2x_memset_stats(bp);
6155         }
6156 }
6157
6158 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6159 {
6160         bnx2x_init_eq_ring(bp);
6161         bnx2x_init_internal(bp, load_code);
6162         bnx2x_pf_init(bp);
6163         bnx2x_stats_init(bp);
6164
6165         /* flush all before enabling interrupts */
6166         mb();
6167         mmiowb();
6168
6169         bnx2x_int_enable(bp);
6170
6171         /* Check for SPIO5 */
6172         bnx2x_attn_int_deasserted0(bp,
6173                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6174                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6175 }
6176
6177 /* gzip service functions */
6178 static int bnx2x_gunzip_init(struct bnx2x *bp)
6179 {
6180         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6181                                             &bp->gunzip_mapping, GFP_KERNEL);
6182         if (bp->gunzip_buf  == NULL)
6183                 goto gunzip_nomem1;
6184
6185         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6186         if (bp->strm  == NULL)
6187                 goto gunzip_nomem2;
6188
6189         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6190         if (bp->strm->workspace == NULL)
6191                 goto gunzip_nomem3;
6192
6193         return 0;
6194
6195 gunzip_nomem3:
6196         kfree(bp->strm);
6197         bp->strm = NULL;
6198
6199 gunzip_nomem2:
6200         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6201                           bp->gunzip_mapping);
6202         bp->gunzip_buf = NULL;
6203
6204 gunzip_nomem1:
6205         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6206         return -ENOMEM;
6207 }
6208
6209 static void bnx2x_gunzip_end(struct bnx2x *bp)
6210 {
6211         if (bp->strm) {
6212                 vfree(bp->strm->workspace);
6213                 kfree(bp->strm);
6214                 bp->strm = NULL;
6215         }
6216
6217         if (bp->gunzip_buf) {
6218                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6219                                   bp->gunzip_mapping);
6220                 bp->gunzip_buf = NULL;
6221         }
6222 }
6223
6224 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6225 {
6226         int n, rc;
6227
6228         /* check gzip header */
6229         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6230                 BNX2X_ERR("Bad gzip header\n");
6231                 return -EINVAL;
6232         }
6233
6234         n = 10;
6235
6236 #define FNAME                           0x8
6237
6238         if (zbuf[3] & FNAME)
6239                 while ((zbuf[n++] != 0) && (n < len));
6240
6241         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6242         bp->strm->avail_in = len - n;
6243         bp->strm->next_out = bp->gunzip_buf;
6244         bp->strm->avail_out = FW_BUF_SIZE;
6245
6246         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6247         if (rc != Z_OK)
6248                 return rc;
6249
6250         rc = zlib_inflate(bp->strm, Z_FINISH);
6251         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6252                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6253                            bp->strm->msg);
6254
6255         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6256         if (bp->gunzip_outlen & 0x3)
6257                 netdev_err(bp->dev,
6258                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6259                                 bp->gunzip_outlen);
6260         bp->gunzip_outlen >>= 2;
6261
6262         zlib_inflateEnd(bp->strm);
6263
6264         if (rc == Z_STREAM_END)
6265                 return 0;
6266
6267         return rc;
6268 }
6269
6270 /* nic load/unload */
6271
6272 /*
6273  * General service functions
6274  */
6275
6276 /* send a NIG loopback debug packet */
6277 static void bnx2x_lb_pckt(struct bnx2x *bp)
6278 {
6279         u32 wb_write[3];
6280
6281         /* Ethernet source and destination addresses */
6282         wb_write[0] = 0x55555555;
6283         wb_write[1] = 0x55555555;
6284         wb_write[2] = 0x20;             /* SOP */
6285         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6286
6287         /* NON-IP protocol */
6288         wb_write[0] = 0x09000000;
6289         wb_write[1] = 0x55555555;
6290         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6291         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6292 }
6293
6294 /* some of the internal memories
6295  * are not directly readable from the driver
6296  * to test them we send debug packets
6297  */
6298 static int bnx2x_int_mem_test(struct bnx2x *bp)
6299 {
6300         int factor;
6301         int count, i;
6302         u32 val = 0;
6303
6304         if (CHIP_REV_IS_FPGA(bp))
6305                 factor = 120;
6306         else if (CHIP_REV_IS_EMUL(bp))
6307                 factor = 200;
6308         else
6309                 factor = 1;
6310
6311         /* Disable inputs of parser neighbor blocks */
6312         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6313         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6314         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6315         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6316
6317         /*  Write 0 to parser credits for CFC search request */
6318         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6319
6320         /* send Ethernet packet */
6321         bnx2x_lb_pckt(bp);
6322
6323         /* TODO do i reset NIG statistic? */
6324         /* Wait until NIG register shows 1 packet of size 0x10 */
6325         count = 1000 * factor;
6326         while (count) {
6327
6328                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6329                 val = *bnx2x_sp(bp, wb_data[0]);
6330                 if (val == 0x10)
6331                         break;
6332
6333                 usleep_range(10000, 20000);
6334                 count--;
6335         }
6336         if (val != 0x10) {
6337                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6338                 return -1;
6339         }
6340
6341         /* Wait until PRS register shows 1 packet */
6342         count = 1000 * factor;
6343         while (count) {
6344                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6345                 if (val == 1)
6346                         break;
6347
6348                 usleep_range(10000, 20000);
6349                 count--;
6350         }
6351         if (val != 0x1) {
6352                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6353                 return -2;
6354         }
6355
6356         /* Reset and init BRB, PRS */
6357         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6358         msleep(50);
6359         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6360         msleep(50);
6361         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6362         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6363
6364         DP(NETIF_MSG_HW, "part2\n");
6365
6366         /* Disable inputs of parser neighbor blocks */
6367         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6368         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6369         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6370         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6371
6372         /* Write 0 to parser credits for CFC search request */
6373         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6374
6375         /* send 10 Ethernet packets */
6376         for (i = 0; i < 10; i++)
6377                 bnx2x_lb_pckt(bp);
6378
6379         /* Wait until NIG register shows 10 + 1
6380            packets of size 11*0x10 = 0xb0 */
6381         count = 1000 * factor;
6382         while (count) {
6383
6384                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6385                 val = *bnx2x_sp(bp, wb_data[0]);
6386                 if (val == 0xb0)
6387                         break;
6388
6389                 usleep_range(10000, 20000);
6390                 count--;
6391         }
6392         if (val != 0xb0) {
6393                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6394                 return -3;
6395         }
6396
6397         /* Wait until PRS register shows 2 packets */
6398         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6399         if (val != 2)
6400                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6401
6402         /* Write 1 to parser credits for CFC search request */
6403         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6404
6405         /* Wait until PRS register shows 3 packets */
6406         msleep(10 * factor);
6407         /* Wait until NIG register shows 1 packet of size 0x10 */
6408         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6409         if (val != 3)
6410                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6411
6412         /* clear NIG EOP FIFO */
6413         for (i = 0; i < 11; i++)
6414                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6415         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6416         if (val != 1) {
6417                 BNX2X_ERR("clear of NIG failed\n");
6418                 return -4;
6419         }
6420
6421         /* Reset and init BRB, PRS, NIG */
6422         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6423         msleep(50);
6424         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6425         msleep(50);
6426         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6427         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6428         if (!CNIC_SUPPORT(bp))
6429                 /* set NIC mode */
6430                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6431
6432         /* Enable inputs of parser neighbor blocks */
6433         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6434         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6435         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6436         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6437
6438         DP(NETIF_MSG_HW, "done\n");
6439
6440         return 0; /* OK */
6441 }
6442
6443 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6444 {
6445         u32 val;
6446
6447         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6448         if (!CHIP_IS_E1x(bp))
6449                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6450         else
6451                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6452         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6453         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6454         /*
6455          * mask read length error interrupts in brb for parser
6456          * (parsing unit and 'checksum and crc' unit)
6457          * these errors are legal (PU reads fixed length and CAC can cause
6458          * read length error on truncated packets)
6459          */
6460         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6461         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6462         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6463         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6464         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6465         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6466 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6467 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6468         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6469         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6470         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6471 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6472 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6473         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6474         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6475         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6476         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6477 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6478 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6479
6480         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6481                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6482                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6483         if (!CHIP_IS_E1x(bp))
6484                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6485                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6486         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6487
6488         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6489         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6490         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6491 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6492
6493         if (!CHIP_IS_E1x(bp))
6494                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6495                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6496
6497         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6498         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6499 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6500         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6501 }
6502
6503 static void bnx2x_reset_common(struct bnx2x *bp)
6504 {
6505         u32 val = 0x1400;
6506
6507         /* reset_common */
6508         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6509                0xd3ffff7f);
6510
6511         if (CHIP_IS_E3(bp)) {
6512                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6513                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6514         }
6515
6516         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6517 }
6518
6519 static void bnx2x_setup_dmae(struct bnx2x *bp)
6520 {
6521         bp->dmae_ready = 0;
6522         spin_lock_init(&bp->dmae_lock);
6523 }
6524
6525 static void bnx2x_init_pxp(struct bnx2x *bp)
6526 {
6527         u16 devctl;
6528         int r_order, w_order;
6529
6530         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6531         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6532         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6533         if (bp->mrrs == -1)
6534                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6535         else {
6536                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6537                 r_order = bp->mrrs;
6538         }
6539
6540         bnx2x_init_pxp_arb(bp, r_order, w_order);
6541 }
6542
6543 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6544 {
6545         int is_required;
6546         u32 val;
6547         int port;
6548
6549         if (BP_NOMCP(bp))
6550                 return;
6551
6552         is_required = 0;
6553         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6554               SHARED_HW_CFG_FAN_FAILURE_MASK;
6555
6556         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6557                 is_required = 1;
6558
6559         /*
6560          * The fan failure mechanism is usually related to the PHY type since
6561          * the power consumption of the board is affected by the PHY. Currently,
6562          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6563          */
6564         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6565                 for (port = PORT_0; port < PORT_MAX; port++) {
6566                         is_required |=
6567                                 bnx2x_fan_failure_det_req(
6568                                         bp,
6569                                         bp->common.shmem_base,
6570                                         bp->common.shmem2_base,
6571                                         port);
6572                 }
6573
6574         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6575
6576         if (is_required == 0)
6577                 return;
6578
6579         /* Fan failure is indicated by SPIO 5 */
6580         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6581
6582         /* set to active low mode */
6583         val = REG_RD(bp, MISC_REG_SPIO_INT);
6584         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6585         REG_WR(bp, MISC_REG_SPIO_INT, val);
6586
6587         /* enable interrupt to signal the IGU */
6588         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6589         val |= MISC_SPIO_SPIO5;
6590         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6591 }
6592
6593 void bnx2x_pf_disable(struct bnx2x *bp)
6594 {
6595         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6596         val &= ~IGU_PF_CONF_FUNC_EN;
6597
6598         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6599         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6600         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6601 }
6602
6603 static void bnx2x__common_init_phy(struct bnx2x *bp)
6604 {
6605         u32 shmem_base[2], shmem2_base[2];
6606         /* Avoid common init in case MFW supports LFA */
6607         if (SHMEM2_RD(bp, size) >
6608             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6609                 return;
6610         shmem_base[0] =  bp->common.shmem_base;
6611         shmem2_base[0] = bp->common.shmem2_base;
6612         if (!CHIP_IS_E1x(bp)) {
6613                 shmem_base[1] =
6614                         SHMEM2_RD(bp, other_shmem_base_addr);
6615                 shmem2_base[1] =
6616                         SHMEM2_RD(bp, other_shmem2_base_addr);
6617         }
6618         bnx2x_acquire_phy_lock(bp);
6619         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6620                               bp->common.chip_id);
6621         bnx2x_release_phy_lock(bp);
6622 }
6623
6624 /**
6625  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6626  *
6627  * @bp:         driver handle
6628  */
6629 static int bnx2x_init_hw_common(struct bnx2x *bp)
6630 {
6631         u32 val;
6632
6633         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6634
6635         /*
6636          * take the RESET lock to protect undi_unload flow from accessing
6637          * registers while we're resetting the chip
6638          */
6639         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6640
6641         bnx2x_reset_common(bp);
6642         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6643
6644         val = 0xfffc;
6645         if (CHIP_IS_E3(bp)) {
6646                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6647                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6648         }
6649         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6650
6651         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6652
6653         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6654
6655         if (!CHIP_IS_E1x(bp)) {
6656                 u8 abs_func_id;
6657
6658                 /**
6659                  * 4-port mode or 2-port mode we need to turn of master-enable
6660                  * for everyone, after that, turn it back on for self.
6661                  * so, we disregard multi-function or not, and always disable
6662                  * for all functions on the given path, this means 0,2,4,6 for
6663                  * path 0 and 1,3,5,7 for path 1
6664                  */
6665                 for (abs_func_id = BP_PATH(bp);
6666                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6667                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6668                                 REG_WR(bp,
6669                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6670                                     1);
6671                                 continue;
6672                         }
6673
6674                         bnx2x_pretend_func(bp, abs_func_id);
6675                         /* clear pf enable */
6676                         bnx2x_pf_disable(bp);
6677                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6678                 }
6679         }
6680
6681         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6682         if (CHIP_IS_E1(bp)) {
6683                 /* enable HW interrupt from PXP on USDM overflow
6684                    bit 16 on INT_MASK_0 */
6685                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6686         }
6687
6688         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6689         bnx2x_init_pxp(bp);
6690
6691 #ifdef __BIG_ENDIAN
6692         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6693         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6694         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6695         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6696         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6697         /* make sure this value is 0 */
6698         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6699
6700 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6701         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6702         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6703         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6704         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6705 #endif
6706
6707         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6708
6709         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6710                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6711
6712         /* let the HW do it's magic ... */
6713         msleep(100);
6714         /* finish PXP init */
6715         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6716         if (val != 1) {
6717                 BNX2X_ERR("PXP2 CFG failed\n");
6718                 return -EBUSY;
6719         }
6720         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6721         if (val != 1) {
6722                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6723                 return -EBUSY;
6724         }
6725
6726         /* Timers bug workaround E2 only. We need to set the entire ILT to
6727          * have entries with value "0" and valid bit on.
6728          * This needs to be done by the first PF that is loaded in a path
6729          * (i.e. common phase)
6730          */
6731         if (!CHIP_IS_E1x(bp)) {
6732 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6733  * (i.e. vnic3) to start even if it is marked as "scan-off".
6734  * This occurs when a different function (func2,3) is being marked
6735  * as "scan-off". Real-life scenario for example: if a driver is being
6736  * load-unloaded while func6,7 are down. This will cause the timer to access
6737  * the ilt, translate to a logical address and send a request to read/write.
6738  * Since the ilt for the function that is down is not valid, this will cause
6739  * a translation error which is unrecoverable.
6740  * The Workaround is intended to make sure that when this happens nothing fatal
6741  * will occur. The workaround:
6742  *      1.  First PF driver which loads on a path will:
6743  *              a.  After taking the chip out of reset, by using pretend,
6744  *                  it will write "0" to the following registers of
6745  *                  the other vnics.
6746  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6747  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6748  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6749  *                  And for itself it will write '1' to
6750  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6751  *                  dmae-operations (writing to pram for example.)
6752  *                  note: can be done for only function 6,7 but cleaner this
6753  *                        way.
6754  *              b.  Write zero+valid to the entire ILT.
6755  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6756  *                  VNIC3 (of that port). The range allocated will be the
6757  *                  entire ILT. This is needed to prevent  ILT range error.
6758  *      2.  Any PF driver load flow:
6759  *              a.  ILT update with the physical addresses of the allocated
6760  *                  logical pages.
6761  *              b.  Wait 20msec. - note that this timeout is needed to make
6762  *                  sure there are no requests in one of the PXP internal
6763  *                  queues with "old" ILT addresses.
6764  *              c.  PF enable in the PGLC.
6765  *              d.  Clear the was_error of the PF in the PGLC. (could have
6766  *                  occurred while driver was down)
6767  *              e.  PF enable in the CFC (WEAK + STRONG)
6768  *              f.  Timers scan enable
6769  *      3.  PF driver unload flow:
6770  *              a.  Clear the Timers scan_en.
6771  *              b.  Polling for scan_on=0 for that PF.
6772  *              c.  Clear the PF enable bit in the PXP.
6773  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6774  *              e.  Write zero+valid to all ILT entries (The valid bit must
6775  *                  stay set)
6776  *              f.  If this is VNIC 3 of a port then also init
6777  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6778  *                  to the last entry in the ILT.
6779  *
6780  *      Notes:
6781  *      Currently the PF error in the PGLC is non recoverable.
6782  *      In the future the there will be a recovery routine for this error.
6783  *      Currently attention is masked.
6784  *      Having an MCP lock on the load/unload process does not guarantee that
6785  *      there is no Timer disable during Func6/7 enable. This is because the
6786  *      Timers scan is currently being cleared by the MCP on FLR.
6787  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6788  *      there is error before clearing it. But the flow above is simpler and
6789  *      more general.
6790  *      All ILT entries are written by zero+valid and not just PF6/7
6791  *      ILT entries since in the future the ILT entries allocation for
6792  *      PF-s might be dynamic.
6793  */
6794                 struct ilt_client_info ilt_cli;
6795                 struct bnx2x_ilt ilt;
6796                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6797                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6798
6799                 /* initialize dummy TM client */
6800                 ilt_cli.start = 0;
6801                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6802                 ilt_cli.client_num = ILT_CLIENT_TM;
6803
6804                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6805                  * Step 2: set the timers first/last ilt entry to point
6806                  * to the entire range to prevent ILT range error for 3rd/4th
6807                  * vnic (this code assumes existence of the vnic)
6808                  *
6809                  * both steps performed by call to bnx2x_ilt_client_init_op()
6810                  * with dummy TM client
6811                  *
6812                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6813                  * and his brother are split registers
6814                  */
6815                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6816                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6817                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6818
6819                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6820                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6821                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6822         }
6823
6824         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6825         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6826
6827         if (!CHIP_IS_E1x(bp)) {
6828                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6829                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6830                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6831
6832                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6833
6834                 /* let the HW do it's magic ... */
6835                 do {
6836                         msleep(200);
6837                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6838                 } while (factor-- && (val != 1));
6839
6840                 if (val != 1) {
6841                         BNX2X_ERR("ATC_INIT failed\n");
6842                         return -EBUSY;
6843                 }
6844         }
6845
6846         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6847
6848         bnx2x_iov_init_dmae(bp);
6849
6850         /* clean the DMAE memory */
6851         bp->dmae_ready = 1;
6852         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6853
6854         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6855
6856         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6857
6858         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6859
6860         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6861
6862         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6863         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6864         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6865         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6866
6867         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6868
6869         /* QM queues pointers table */
6870         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6871
6872         /* soft reset pulse */
6873         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6874         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6875
6876         if (CNIC_SUPPORT(bp))
6877                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6878
6879         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6880         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6881         if (!CHIP_REV_IS_SLOW(bp))
6882                 /* enable hw interrupt from doorbell Q */
6883                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6884
6885         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6886
6887         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6888         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6889
6890         if (!CHIP_IS_E1(bp))
6891                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6892
6893         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6894                 if (IS_MF_AFEX(bp)) {
6895                         /* configure that VNTag and VLAN headers must be
6896                          * received in afex mode
6897                          */
6898                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6899                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6900                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6901                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6902                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6903                 } else {
6904                         /* Bit-map indicating which L2 hdrs may appear
6905                          * after the basic Ethernet header
6906                          */
6907                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6908                                bp->path_has_ovlan ? 7 : 6);
6909                 }
6910         }
6911
6912         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6913         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6914         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6915         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6916
6917         if (!CHIP_IS_E1x(bp)) {
6918                 /* reset VFC memories */
6919                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6920                            VFC_MEMORIES_RST_REG_CAM_RST |
6921                            VFC_MEMORIES_RST_REG_RAM_RST);
6922                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6923                            VFC_MEMORIES_RST_REG_CAM_RST |
6924                            VFC_MEMORIES_RST_REG_RAM_RST);
6925
6926                 msleep(20);
6927         }
6928
6929         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6930         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6931         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6932         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6933
6934         /* sync semi rtc */
6935         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6936                0x80000000);
6937         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6938                0x80000000);
6939
6940         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6941         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6942         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6943
6944         if (!CHIP_IS_E1x(bp)) {
6945                 if (IS_MF_AFEX(bp)) {
6946                         /* configure that VNTag and VLAN headers must be
6947                          * sent in afex mode
6948                          */
6949                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6950                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6951                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6952                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6953                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6954                 } else {
6955                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6956                                bp->path_has_ovlan ? 7 : 6);
6957                 }
6958         }
6959
6960         REG_WR(bp, SRC_REG_SOFT_RST, 1);
6961
6962         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6963
6964         if (CNIC_SUPPORT(bp)) {
6965                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6966                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6967                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6968                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6969                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6970                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6971                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6972                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6973                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6974                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6975         }
6976         REG_WR(bp, SRC_REG_SOFT_RST, 0);
6977
6978         if (sizeof(union cdu_context) != 1024)
6979                 /* we currently assume that a context is 1024 bytes */
6980                 dev_alert(&bp->pdev->dev,
6981                           "please adjust the size of cdu_context(%ld)\n",
6982                           (long)sizeof(union cdu_context));
6983
6984         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6985         val = (4 << 24) + (0 << 12) + 1024;
6986         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6987
6988         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6989         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6990         /* enable context validation interrupt from CFC */
6991         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6992
6993         /* set the thresholds to prevent CFC/CDU race */
6994         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6995
6996         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6997
6998         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6999                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7000
7001         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7002         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7003
7004         /* Reset PCIE errors for debug */
7005         REG_WR(bp, 0x2814, 0xffffffff);
7006         REG_WR(bp, 0x3820, 0xffffffff);
7007
7008         if (!CHIP_IS_E1x(bp)) {
7009                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7010                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7011                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7012                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7013                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7014                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7015                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7016                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7017                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7018                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7019                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7020         }
7021
7022         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7023         if (!CHIP_IS_E1(bp)) {
7024                 /* in E3 this done in per-port section */
7025                 if (!CHIP_IS_E3(bp))
7026                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7027         }
7028         if (CHIP_IS_E1H(bp))
7029                 /* not applicable for E2 (and above ...) */
7030                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7031
7032         if (CHIP_REV_IS_SLOW(bp))
7033                 msleep(200);
7034
7035         /* finish CFC init */
7036         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7037         if (val != 1) {
7038                 BNX2X_ERR("CFC LL_INIT failed\n");
7039                 return -EBUSY;
7040         }
7041         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7042         if (val != 1) {
7043                 BNX2X_ERR("CFC AC_INIT failed\n");
7044                 return -EBUSY;
7045         }
7046         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7047         if (val != 1) {
7048                 BNX2X_ERR("CFC CAM_INIT failed\n");
7049                 return -EBUSY;
7050         }
7051         REG_WR(bp, CFC_REG_DEBUG0, 0);
7052
7053         if (CHIP_IS_E1(bp)) {
7054                 /* read NIG statistic
7055                    to see if this is our first up since powerup */
7056                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7057                 val = *bnx2x_sp(bp, wb_data[0]);
7058
7059                 /* do internal memory self test */
7060                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7061                         BNX2X_ERR("internal mem self test failed\n");
7062                         return -EBUSY;
7063                 }
7064         }
7065
7066         bnx2x_setup_fan_failure_detection(bp);
7067
7068         /* clear PXP2 attentions */
7069         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7070
7071         bnx2x_enable_blocks_attention(bp);
7072         bnx2x_enable_blocks_parity(bp);
7073
7074         if (!BP_NOMCP(bp)) {
7075                 if (CHIP_IS_E1x(bp))
7076                         bnx2x__common_init_phy(bp);
7077         } else
7078                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7079
7080         return 0;
7081 }
7082
7083 /**
7084  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7085  *
7086  * @bp:         driver handle
7087  */
7088 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7089 {
7090         int rc = bnx2x_init_hw_common(bp);
7091
7092         if (rc)
7093                 return rc;
7094
7095         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7096         if (!BP_NOMCP(bp))
7097                 bnx2x__common_init_phy(bp);
7098
7099         return 0;
7100 }
7101
7102 static int bnx2x_init_hw_port(struct bnx2x *bp)
7103 {
7104         int port = BP_PORT(bp);
7105         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7106         u32 low, high;
7107         u32 val;
7108
7109         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7110
7111         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7112
7113         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7114         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7115         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7116
7117         /* Timers bug workaround: disables the pf_master bit in pglue at
7118          * common phase, we need to enable it here before any dmae access are
7119          * attempted. Therefore we manually added the enable-master to the
7120          * port phase (it also happens in the function phase)
7121          */
7122         if (!CHIP_IS_E1x(bp))
7123                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7124
7125         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7126         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7127         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7128         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7129
7130         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7131         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7132         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7133         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7134
7135         /* QM cid (connection) count */
7136         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7137
7138         if (CNIC_SUPPORT(bp)) {
7139                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7140                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7141                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7142         }
7143
7144         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7145
7146         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7147
7148         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7149
7150                 if (IS_MF(bp))
7151                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7152                 else if (bp->dev->mtu > 4096) {
7153                         if (bp->flags & ONE_PORT_FLAG)
7154                                 low = 160;
7155                         else {
7156                                 val = bp->dev->mtu;
7157                                 /* (24*1024 + val*4)/256 */
7158                                 low = 96 + (val/64) +
7159                                                 ((val % 64) ? 1 : 0);
7160                         }
7161                 } else
7162                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7163                 high = low + 56;        /* 14*1024/256 */
7164                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7165                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7166         }
7167
7168         if (CHIP_MODE_IS_4_PORT(bp))
7169                 REG_WR(bp, (BP_PORT(bp) ?
7170                             BRB1_REG_MAC_GUARANTIED_1 :
7171                             BRB1_REG_MAC_GUARANTIED_0), 40);
7172
7173         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7174         if (CHIP_IS_E3B0(bp)) {
7175                 if (IS_MF_AFEX(bp)) {
7176                         /* configure headers for AFEX mode */
7177                         REG_WR(bp, BP_PORT(bp) ?
7178                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7179                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7180                         REG_WR(bp, BP_PORT(bp) ?
7181                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7182                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7183                         REG_WR(bp, BP_PORT(bp) ?
7184                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7185                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7186                 } else {
7187                         /* Ovlan exists only if we are in multi-function +
7188                          * switch-dependent mode, in switch-independent there
7189                          * is no ovlan headers
7190                          */
7191                         REG_WR(bp, BP_PORT(bp) ?
7192                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7193                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7194                                (bp->path_has_ovlan ? 7 : 6));
7195                 }
7196         }
7197
7198         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7199         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7200         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7201         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7202
7203         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7204         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7205         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7206         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7207
7208         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7209         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7210
7211         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7212
7213         if (CHIP_IS_E1x(bp)) {
7214                 /* configure PBF to work without PAUSE mtu 9000 */
7215                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7216
7217                 /* update threshold */
7218                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7219                 /* update init credit */
7220                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7221
7222                 /* probe changes */
7223                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7224                 udelay(50);
7225                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7226         }
7227
7228         if (CNIC_SUPPORT(bp))
7229                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7230
7231         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7232         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7233
7234         if (CHIP_IS_E1(bp)) {
7235                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7236                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7237         }
7238         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7239
7240         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7241
7242         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7243         /* init aeu_mask_attn_func_0/1:
7244          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7245          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7246          *             bits 4-7 are used for "per vn group attention" */
7247         val = IS_MF(bp) ? 0xF7 : 0x7;
7248         /* Enable DCBX attention for all but E1 */
7249         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7250         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7251
7252         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7253
7254         if (!CHIP_IS_E1x(bp)) {
7255                 /* Bit-map indicating which L2 hdrs may appear after the
7256                  * basic Ethernet header
7257                  */
7258                 if (IS_MF_AFEX(bp))
7259                         REG_WR(bp, BP_PORT(bp) ?
7260                                NIG_REG_P1_HDRS_AFTER_BASIC :
7261                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7262                 else
7263                         REG_WR(bp, BP_PORT(bp) ?
7264                                NIG_REG_P1_HDRS_AFTER_BASIC :
7265                                NIG_REG_P0_HDRS_AFTER_BASIC,
7266                                IS_MF_SD(bp) ? 7 : 6);
7267
7268                 if (CHIP_IS_E3(bp))
7269                         REG_WR(bp, BP_PORT(bp) ?
7270                                    NIG_REG_LLH1_MF_MODE :
7271                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7272         }
7273         if (!CHIP_IS_E3(bp))
7274                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7275
7276         if (!CHIP_IS_E1(bp)) {
7277                 /* 0x2 disable mf_ov, 0x1 enable */
7278                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7279                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7280
7281                 if (!CHIP_IS_E1x(bp)) {
7282                         val = 0;
7283                         switch (bp->mf_mode) {
7284                         case MULTI_FUNCTION_SD:
7285                                 val = 1;
7286                                 break;
7287                         case MULTI_FUNCTION_SI:
7288                         case MULTI_FUNCTION_AFEX:
7289                                 val = 2;
7290                                 break;
7291                         }
7292
7293                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7294                                                   NIG_REG_LLH0_CLS_TYPE), val);
7295                 }
7296                 {
7297                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7298                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7299                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7300                 }
7301         }
7302
7303         /* If SPIO5 is set to generate interrupts, enable it for this port */
7304         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7305         if (val & MISC_SPIO_SPIO5) {
7306                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7307                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7308                 val = REG_RD(bp, reg_addr);
7309                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7310                 REG_WR(bp, reg_addr, val);
7311         }
7312
7313         return 0;
7314 }
7315
7316 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7317 {
7318         int reg;
7319         u32 wb_write[2];
7320
7321         if (CHIP_IS_E1(bp))
7322                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7323         else
7324                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7325
7326         wb_write[0] = ONCHIP_ADDR1(addr);
7327         wb_write[1] = ONCHIP_ADDR2(addr);
7328         REG_WR_DMAE(bp, reg, wb_write, 2);
7329 }
7330
7331 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7332 {
7333         u32 data, ctl, cnt = 100;
7334         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7335         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7336         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7337         u32 sb_bit =  1 << (idu_sb_id%32);
7338         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7339         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7340
7341         /* Not supported in BC mode */
7342         if (CHIP_INT_MODE_IS_BC(bp))
7343                 return;
7344
7345         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7346                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7347                 IGU_REGULAR_CLEANUP_SET                         |
7348                 IGU_REGULAR_BCLEANUP;
7349
7350         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7351               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7352               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7353
7354         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7355                          data, igu_addr_data);
7356         REG_WR(bp, igu_addr_data, data);
7357         mmiowb();
7358         barrier();
7359         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7360                           ctl, igu_addr_ctl);
7361         REG_WR(bp, igu_addr_ctl, ctl);
7362         mmiowb();
7363         barrier();
7364
7365         /* wait for clean up to finish */
7366         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7367                 msleep(20);
7368
7369         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7370                 DP(NETIF_MSG_HW,
7371                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7372                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7373         }
7374 }
7375
7376 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7377 {
7378         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7379 }
7380
7381 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7382 {
7383         u32 i, base = FUNC_ILT_BASE(func);
7384         for (i = base; i < base + ILT_PER_FUNC; i++)
7385                 bnx2x_ilt_wr(bp, i, 0);
7386 }
7387
7388 static void bnx2x_init_searcher(struct bnx2x *bp)
7389 {
7390         int port = BP_PORT(bp);
7391         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7392         /* T1 hash bits value determines the T1 number of entries */
7393         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7394 }
7395
7396 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7397 {
7398         int rc;
7399         struct bnx2x_func_state_params func_params = {NULL};
7400         struct bnx2x_func_switch_update_params *switch_update_params =
7401                 &func_params.params.switch_update;
7402
7403         /* Prepare parameters for function state transitions */
7404         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7405         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7406
7407         func_params.f_obj = &bp->func_obj;
7408         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7409
7410         /* Function parameters */
7411         switch_update_params->suspend = suspend;
7412
7413         rc = bnx2x_func_state_change(bp, &func_params);
7414
7415         return rc;
7416 }
7417
7418 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7419 {
7420         int rc, i, port = BP_PORT(bp);
7421         int vlan_en = 0, mac_en[NUM_MACS];
7422
7423         /* Close input from network */
7424         if (bp->mf_mode == SINGLE_FUNCTION) {
7425                 bnx2x_set_rx_filter(&bp->link_params, 0);
7426         } else {
7427                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7428                                    NIG_REG_LLH0_FUNC_EN);
7429                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7430                           NIG_REG_LLH0_FUNC_EN, 0);
7431                 for (i = 0; i < NUM_MACS; i++) {
7432                         mac_en[i] = REG_RD(bp, port ?
7433                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7434                                               4 * i) :
7435                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7436                                               4 * i));
7437                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7438                                               4 * i) :
7439                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7440                 }
7441         }
7442
7443         /* Close BMC to host */
7444         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7445                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7446
7447         /* Suspend Tx switching to the PF. Completion of this ramrod
7448          * further guarantees that all the packets of that PF / child
7449          * VFs in BRB were processed by the Parser, so it is safe to
7450          * change the NIC_MODE register.
7451          */
7452         rc = bnx2x_func_switch_update(bp, 1);
7453         if (rc) {
7454                 BNX2X_ERR("Can't suspend tx-switching!\n");
7455                 return rc;
7456         }
7457
7458         /* Change NIC_MODE register */
7459         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7460
7461         /* Open input from network */
7462         if (bp->mf_mode == SINGLE_FUNCTION) {
7463                 bnx2x_set_rx_filter(&bp->link_params, 1);
7464         } else {
7465                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7466                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7467                 for (i = 0; i < NUM_MACS; i++) {
7468                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7469                                               4 * i) :
7470                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7471                                   mac_en[i]);
7472                 }
7473         }
7474
7475         /* Enable BMC to host */
7476         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7477                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7478
7479         /* Resume Tx switching to the PF */
7480         rc = bnx2x_func_switch_update(bp, 0);
7481         if (rc) {
7482                 BNX2X_ERR("Can't resume tx-switching!\n");
7483                 return rc;
7484         }
7485
7486         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7487         return 0;
7488 }
7489
7490 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7491 {
7492         int rc;
7493
7494         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7495
7496         if (CONFIGURE_NIC_MODE(bp)) {
7497                 /* Configure searcher as part of function hw init */
7498                 bnx2x_init_searcher(bp);
7499
7500                 /* Reset NIC mode */
7501                 rc = bnx2x_reset_nic_mode(bp);
7502                 if (rc)
7503                         BNX2X_ERR("Can't change NIC mode!\n");
7504                 return rc;
7505         }
7506
7507         return 0;
7508 }
7509
7510 static int bnx2x_init_hw_func(struct bnx2x *bp)
7511 {
7512         int port = BP_PORT(bp);
7513         int func = BP_FUNC(bp);
7514         int init_phase = PHASE_PF0 + func;
7515         struct bnx2x_ilt *ilt = BP_ILT(bp);
7516         u16 cdu_ilt_start;
7517         u32 addr, val;
7518         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7519         int i, main_mem_width, rc;
7520
7521         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7522
7523         /* FLR cleanup - hmmm */
7524         if (!CHIP_IS_E1x(bp)) {
7525                 rc = bnx2x_pf_flr_clnup(bp);
7526                 if (rc) {
7527                         bnx2x_fw_dump(bp);
7528                         return rc;
7529                 }
7530         }
7531
7532         /* set MSI reconfigure capability */
7533         if (bp->common.int_block == INT_BLOCK_HC) {
7534                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7535                 val = REG_RD(bp, addr);
7536                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7537                 REG_WR(bp, addr, val);
7538         }
7539
7540         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7541         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7542
7543         ilt = BP_ILT(bp);
7544         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7545
7546         if (IS_SRIOV(bp))
7547                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7548         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7549
7550         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7551          * those of the VFs, so start line should be reset
7552          */
7553         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7554         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7555                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7556                 ilt->lines[cdu_ilt_start + i].page_mapping =
7557                         bp->context[i].cxt_mapping;
7558                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7559         }
7560
7561         bnx2x_ilt_init_op(bp, INITOP_SET);
7562
7563         if (!CONFIGURE_NIC_MODE(bp)) {
7564                 bnx2x_init_searcher(bp);
7565                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7566                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7567         } else {
7568                 /* Set NIC mode */
7569                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7570                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7571         }
7572
7573         if (!CHIP_IS_E1x(bp)) {
7574                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7575
7576                 /* Turn on a single ISR mode in IGU if driver is going to use
7577                  * INT#x or MSI
7578                  */
7579                 if (!(bp->flags & USING_MSIX_FLAG))
7580                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7581                 /*
7582                  * Timers workaround bug: function init part.
7583                  * Need to wait 20msec after initializing ILT,
7584                  * needed to make sure there are no requests in
7585                  * one of the PXP internal queues with "old" ILT addresses
7586                  */
7587                 msleep(20);
7588                 /*
7589                  * Master enable - Due to WB DMAE writes performed before this
7590                  * register is re-initialized as part of the regular function
7591                  * init
7592                  */
7593                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7594                 /* Enable the function in IGU */
7595                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7596         }
7597
7598         bp->dmae_ready = 1;
7599
7600         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7601
7602         if (!CHIP_IS_E1x(bp))
7603                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7604
7605         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7606         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7607         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7608         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7609         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7610         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7611         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7612         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7613         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7614         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7615         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7616         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7617         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7618
7619         if (!CHIP_IS_E1x(bp))
7620                 REG_WR(bp, QM_REG_PF_EN, 1);
7621
7622         if (!CHIP_IS_E1x(bp)) {
7623                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7624                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7625                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7626                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7627         }
7628         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7629
7630         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7631         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7632
7633         bnx2x_iov_init_dq(bp);
7634
7635         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7636         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7637         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7638         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7639         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7640         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7641         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7642         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7643         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7644         if (!CHIP_IS_E1x(bp))
7645                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7646
7647         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7648
7649         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7650
7651         if (!CHIP_IS_E1x(bp))
7652                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7653
7654         if (IS_MF(bp)) {
7655                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7656                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7657         }
7658
7659         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7660
7661         /* HC init per function */
7662         if (bp->common.int_block == INT_BLOCK_HC) {
7663                 if (CHIP_IS_E1H(bp)) {
7664                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7665
7666                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7667                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7668                 }
7669                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7670
7671         } else {
7672                 int num_segs, sb_idx, prod_offset;
7673
7674                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7675
7676                 if (!CHIP_IS_E1x(bp)) {
7677                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7678                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7679                 }
7680
7681                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7682
7683                 if (!CHIP_IS_E1x(bp)) {
7684                         int dsb_idx = 0;
7685                         /**
7686                          * Producer memory:
7687                          * E2 mode: address 0-135 match to the mapping memory;
7688                          * 136 - PF0 default prod; 137 - PF1 default prod;
7689                          * 138 - PF2 default prod; 139 - PF3 default prod;
7690                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7691                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7692                          * 144-147 reserved.
7693                          *
7694                          * E1.5 mode - In backward compatible mode;
7695                          * for non default SB; each even line in the memory
7696                          * holds the U producer and each odd line hold
7697                          * the C producer. The first 128 producers are for
7698                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7699                          * producers are for the DSB for each PF.
7700                          * Each PF has five segments: (the order inside each
7701                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7702                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7703                          * 144-147 attn prods;
7704                          */
7705                         /* non-default-status-blocks */
7706                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7707                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7708                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7709                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7710                                         num_segs;
7711
7712                                 for (i = 0; i < num_segs; i++) {
7713                                         addr = IGU_REG_PROD_CONS_MEMORY +
7714                                                         (prod_offset + i) * 4;
7715                                         REG_WR(bp, addr, 0);
7716                                 }
7717                                 /* send consumer update with value 0 */
7718                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7719                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7720                                 bnx2x_igu_clear_sb(bp,
7721                                                    bp->igu_base_sb + sb_idx);
7722                         }
7723
7724                         /* default-status-blocks */
7725                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7726                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7727
7728                         if (CHIP_MODE_IS_4_PORT(bp))
7729                                 dsb_idx = BP_FUNC(bp);
7730                         else
7731                                 dsb_idx = BP_VN(bp);
7732
7733                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7734                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7735                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7736
7737                         /*
7738                          * igu prods come in chunks of E1HVN_MAX (4) -
7739                          * does not matters what is the current chip mode
7740                          */
7741                         for (i = 0; i < (num_segs * E1HVN_MAX);
7742                              i += E1HVN_MAX) {
7743                                 addr = IGU_REG_PROD_CONS_MEMORY +
7744                                                         (prod_offset + i)*4;
7745                                 REG_WR(bp, addr, 0);
7746                         }
7747                         /* send consumer update with 0 */
7748                         if (CHIP_INT_MODE_IS_BC(bp)) {
7749                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7750                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7751                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7752                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7753                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7754                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7755                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7756                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7757                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7758                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7759                         } else {
7760                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7761                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7762                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7763                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7764                         }
7765                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7766
7767                         /* !!! These should become driver const once
7768                            rf-tool supports split-68 const */
7769                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7770                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7771                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7772                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7773                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7774                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7775                 }
7776         }
7777
7778         /* Reset PCIE errors for debug */
7779         REG_WR(bp, 0x2114, 0xffffffff);
7780         REG_WR(bp, 0x2120, 0xffffffff);
7781
7782         if (CHIP_IS_E1x(bp)) {
7783                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7784                 main_mem_base = HC_REG_MAIN_MEMORY +
7785                                 BP_PORT(bp) * (main_mem_size * 4);
7786                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7787                 main_mem_width = 8;
7788
7789                 val = REG_RD(bp, main_mem_prty_clr);
7790                 if (val)
7791                         DP(NETIF_MSG_HW,
7792                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7793                            val);
7794
7795                 /* Clear "false" parity errors in MSI-X table */
7796                 for (i = main_mem_base;
7797                      i < main_mem_base + main_mem_size * 4;
7798                      i += main_mem_width) {
7799                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7800                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7801                                          i, main_mem_width / 4);
7802                 }
7803                 /* Clear HC parity attention */
7804                 REG_RD(bp, main_mem_prty_clr);
7805         }
7806
7807 #ifdef BNX2X_STOP_ON_ERROR
7808         /* Enable STORMs SP logging */
7809         REG_WR8(bp, BAR_USTRORM_INTMEM +
7810                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7811         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7812                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7813         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7814                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7815         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7816                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7817 #endif
7818
7819         bnx2x_phy_probe(&bp->link_params);
7820
7821         return 0;
7822 }
7823
7824 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7825 {
7826         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7827
7828         if (!CHIP_IS_E1x(bp))
7829                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7830                                sizeof(struct host_hc_status_block_e2));
7831         else
7832                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7833                                sizeof(struct host_hc_status_block_e1x));
7834
7835         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7836 }
7837
7838 void bnx2x_free_mem(struct bnx2x *bp)
7839 {
7840         int i;
7841
7842         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7843                        sizeof(struct host_sp_status_block));
7844
7845         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7846                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7847
7848         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7849                        sizeof(struct bnx2x_slowpath));
7850
7851         for (i = 0; i < L2_ILT_LINES(bp); i++)
7852                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7853                                bp->context[i].size);
7854         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7855
7856         BNX2X_FREE(bp->ilt->lines);
7857
7858         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7859
7860         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7861                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7862
7863         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7864
7865         bnx2x_iov_free_mem(bp);
7866 }
7867
7868 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7869 {
7870         if (!CHIP_IS_E1x(bp))
7871                 /* size = the status block + ramrod buffers */
7872                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7873                                 sizeof(struct host_hc_status_block_e2));
7874         else
7875                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7876                                 &bp->cnic_sb_mapping,
7877                                 sizeof(struct
7878                                        host_hc_status_block_e1x));
7879
7880         if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
7881                 /* allocate searcher T2 table, as it wasn't allocated before */
7882                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7883
7884         /* write address to which L5 should insert its values */
7885         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7886                 &bp->slowpath->drv_info_to_mcp;
7887
7888         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7889                 goto alloc_mem_err;
7890
7891         return 0;
7892
7893 alloc_mem_err:
7894         bnx2x_free_mem_cnic(bp);
7895         BNX2X_ERR("Can't allocate memory\n");
7896         return -ENOMEM;
7897 }
7898
7899 int bnx2x_alloc_mem(struct bnx2x *bp)
7900 {
7901         int i, allocated, context_size;
7902
7903         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
7904                 /* allocate searcher T2 table */
7905                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7906
7907         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7908                         sizeof(struct host_sp_status_block));
7909
7910         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7911                         sizeof(struct bnx2x_slowpath));
7912
7913         /* Allocate memory for CDU context:
7914          * This memory is allocated separately and not in the generic ILT
7915          * functions because CDU differs in few aspects:
7916          * 1. There are multiple entities allocating memory for context -
7917          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7918          * its own ILT lines.
7919          * 2. Since CDU page-size is not a single 4KB page (which is the case
7920          * for the other ILT clients), to be efficient we want to support
7921          * allocation of sub-page-size in the last entry.
7922          * 3. Context pointers are used by the driver to pass to FW / update
7923          * the context (for the other ILT clients the pointers are used just to
7924          * free the memory during unload).
7925          */
7926         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7927
7928         for (i = 0, allocated = 0; allocated < context_size; i++) {
7929                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7930                                           (context_size - allocated));
7931                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7932                                 &bp->context[i].cxt_mapping,
7933                                 bp->context[i].size);
7934                 allocated += bp->context[i].size;
7935         }
7936         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7937
7938         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7939                 goto alloc_mem_err;
7940
7941         if (bnx2x_iov_alloc_mem(bp))
7942                 goto alloc_mem_err;
7943
7944         /* Slow path ring */
7945         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7946
7947         /* EQ */
7948         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7949                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
7950
7951         return 0;
7952
7953 alloc_mem_err:
7954         bnx2x_free_mem(bp);
7955         BNX2X_ERR("Can't allocate memory\n");
7956         return -ENOMEM;
7957 }
7958
7959 /*
7960  * Init service functions
7961  */
7962
7963 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7964                       struct bnx2x_vlan_mac_obj *obj, bool set,
7965                       int mac_type, unsigned long *ramrod_flags)
7966 {
7967         int rc;
7968         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7969
7970         memset(&ramrod_param, 0, sizeof(ramrod_param));
7971
7972         /* Fill general parameters */
7973         ramrod_param.vlan_mac_obj = obj;
7974         ramrod_param.ramrod_flags = *ramrod_flags;
7975
7976         /* Fill a user request section if needed */
7977         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7978                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7979
7980                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7981
7982                 /* Set the command: ADD or DEL */
7983                 if (set)
7984                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7985                 else
7986                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7987         }
7988
7989         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7990
7991         if (rc == -EEXIST) {
7992                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7993                 /* do not treat adding same MAC as error */
7994                 rc = 0;
7995         } else if (rc < 0)
7996                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7997
7998         return rc;
7999 }
8000
8001 int bnx2x_del_all_macs(struct bnx2x *bp,
8002                        struct bnx2x_vlan_mac_obj *mac_obj,
8003                        int mac_type, bool wait_for_comp)
8004 {
8005         int rc;
8006         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8007
8008         /* Wait for completion of requested */
8009         if (wait_for_comp)
8010                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8011
8012         /* Set the mac type of addresses we want to clear */
8013         __set_bit(mac_type, &vlan_mac_flags);
8014
8015         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8016         if (rc < 0)
8017                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8018
8019         return rc;
8020 }
8021
8022 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8023 {
8024         if (is_zero_ether_addr(bp->dev->dev_addr) &&
8025             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8026                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8027                    "Ignoring Zero MAC for STORAGE SD mode\n");
8028                 return 0;
8029         }
8030
8031         if (IS_PF(bp)) {
8032                 unsigned long ramrod_flags = 0;
8033
8034                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8035                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8036                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8037                                          &bp->sp_objs->mac_obj, set,
8038                                          BNX2X_ETH_MAC, &ramrod_flags);
8039         } else { /* vf */
8040                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8041                                              bp->fp->index, true);
8042         }
8043 }
8044
8045 int bnx2x_setup_leading(struct bnx2x *bp)
8046 {
8047         return bnx2x_setup_queue(bp, &bp->fp[0], 1);
8048 }
8049
8050 /**
8051  * bnx2x_set_int_mode - configure interrupt mode
8052  *
8053  * @bp:         driver handle
8054  *
8055  * In case of MSI-X it will also try to enable MSI-X.
8056  */
8057 int bnx2x_set_int_mode(struct bnx2x *bp)
8058 {
8059         int rc = 0;
8060
8061         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
8062                 return -EINVAL;
8063
8064         switch (int_mode) {
8065         case BNX2X_INT_MODE_MSIX:
8066                 /* attempt to enable msix */
8067                 rc = bnx2x_enable_msix(bp);
8068
8069                 /* msix attained */
8070                 if (!rc)
8071                         return 0;
8072
8073                 /* vfs use only msix */
8074                 if (rc && IS_VF(bp))
8075                         return rc;
8076
8077                 /* failed to enable multiple MSI-X */
8078                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8079                                bp->num_queues,
8080                                1 + bp->num_cnic_queues);
8081
8082                 /* falling through... */
8083         case BNX2X_INT_MODE_MSI:
8084                 bnx2x_enable_msi(bp);
8085
8086                 /* falling through... */
8087         case BNX2X_INT_MODE_INTX:
8088                 bp->num_ethernet_queues = 1;
8089                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8090                 BNX2X_DEV_INFO("set number of queues to 1\n");
8091                 break;
8092         default:
8093                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8094                 return -EINVAL;
8095         }
8096         return 0;
8097 }
8098
8099 /* must be called prior to any HW initializations */
8100 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8101 {
8102         if (IS_SRIOV(bp))
8103                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8104         return L2_ILT_LINES(bp);
8105 }
8106
8107 void bnx2x_ilt_set_info(struct bnx2x *bp)
8108 {
8109         struct ilt_client_info *ilt_client;
8110         struct bnx2x_ilt *ilt = BP_ILT(bp);
8111         u16 line = 0;
8112
8113         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8114         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8115
8116         /* CDU */
8117         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8118         ilt_client->client_num = ILT_CLIENT_CDU;
8119         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8120         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8121         ilt_client->start = line;
8122         line += bnx2x_cid_ilt_lines(bp);
8123
8124         if (CNIC_SUPPORT(bp))
8125                 line += CNIC_ILT_LINES;
8126         ilt_client->end = line - 1;
8127
8128         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8129            ilt_client->start,
8130            ilt_client->end,
8131            ilt_client->page_size,
8132            ilt_client->flags,
8133            ilog2(ilt_client->page_size >> 12));
8134
8135         /* QM */
8136         if (QM_INIT(bp->qm_cid_count)) {
8137                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8138                 ilt_client->client_num = ILT_CLIENT_QM;
8139                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8140                 ilt_client->flags = 0;
8141                 ilt_client->start = line;
8142
8143                 /* 4 bytes for each cid */
8144                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8145                                                          QM_ILT_PAGE_SZ);
8146
8147                 ilt_client->end = line - 1;
8148
8149                 DP(NETIF_MSG_IFUP,
8150                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8151                    ilt_client->start,
8152                    ilt_client->end,
8153                    ilt_client->page_size,
8154                    ilt_client->flags,
8155                    ilog2(ilt_client->page_size >> 12));
8156         }
8157
8158         if (CNIC_SUPPORT(bp)) {
8159                 /* SRC */
8160                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8161                 ilt_client->client_num = ILT_CLIENT_SRC;
8162                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8163                 ilt_client->flags = 0;
8164                 ilt_client->start = line;
8165                 line += SRC_ILT_LINES;
8166                 ilt_client->end = line - 1;
8167
8168                 DP(NETIF_MSG_IFUP,
8169                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8170                    ilt_client->start,
8171                    ilt_client->end,
8172                    ilt_client->page_size,
8173                    ilt_client->flags,
8174                    ilog2(ilt_client->page_size >> 12));
8175
8176                 /* TM */
8177                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8178                 ilt_client->client_num = ILT_CLIENT_TM;
8179                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8180                 ilt_client->flags = 0;
8181                 ilt_client->start = line;
8182                 line += TM_ILT_LINES;
8183                 ilt_client->end = line - 1;
8184
8185                 DP(NETIF_MSG_IFUP,
8186                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8187                    ilt_client->start,
8188                    ilt_client->end,
8189                    ilt_client->page_size,
8190                    ilt_client->flags,
8191                    ilog2(ilt_client->page_size >> 12));
8192         }
8193
8194         BUG_ON(line > ILT_MAX_LINES);
8195 }
8196
8197 /**
8198  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8199  *
8200  * @bp:                 driver handle
8201  * @fp:                 pointer to fastpath
8202  * @init_params:        pointer to parameters structure
8203  *
8204  * parameters configured:
8205  *      - HC configuration
8206  *      - Queue's CDU context
8207  */
8208 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8209         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8210 {
8211         u8 cos;
8212         int cxt_index, cxt_offset;
8213
8214         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8215         if (!IS_FCOE_FP(fp)) {
8216                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8217                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8218
8219                 /* If HC is supported, enable host coalescing in the transition
8220                  * to INIT state.
8221                  */
8222                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8223                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8224
8225                 /* HC rate */
8226                 init_params->rx.hc_rate = bp->rx_ticks ?
8227                         (1000000 / bp->rx_ticks) : 0;
8228                 init_params->tx.hc_rate = bp->tx_ticks ?
8229                         (1000000 / bp->tx_ticks) : 0;
8230
8231                 /* FW SB ID */
8232                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8233                         fp->fw_sb_id;
8234
8235                 /*
8236                  * CQ index among the SB indices: FCoE clients uses the default
8237                  * SB, therefore it's different.
8238                  */
8239                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8240                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8241         }
8242
8243         /* set maximum number of COSs supported by this queue */
8244         init_params->max_cos = fp->max_cos;
8245
8246         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8247             fp->index, init_params->max_cos);
8248
8249         /* set the context pointers queue object */
8250         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8251                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8252                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8253                                 ILT_PAGE_CIDS);
8254                 init_params->cxts[cos] =
8255                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8256         }
8257 }
8258
8259 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8260                         struct bnx2x_queue_state_params *q_params,
8261                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8262                         int tx_index, bool leading)
8263 {
8264         memset(tx_only_params, 0, sizeof(*tx_only_params));
8265
8266         /* Set the command */
8267         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8268
8269         /* Set tx-only QUEUE flags: don't zero statistics */
8270         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8271
8272         /* choose the index of the cid to send the slow path on */
8273         tx_only_params->cid_index = tx_index;
8274
8275         /* Set general TX_ONLY_SETUP parameters */
8276         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8277
8278         /* Set Tx TX_ONLY_SETUP parameters */
8279         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8280
8281         DP(NETIF_MSG_IFUP,
8282            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8283            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8284            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8285            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8286
8287         /* send the ramrod */
8288         return bnx2x_queue_state_change(bp, q_params);
8289 }
8290
8291 /**
8292  * bnx2x_setup_queue - setup queue
8293  *
8294  * @bp:         driver handle
8295  * @fp:         pointer to fastpath
8296  * @leading:    is leading
8297  *
8298  * This function performs 2 steps in a Queue state machine
8299  *      actually: 1) RESET->INIT 2) INIT->SETUP
8300  */
8301
8302 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8303                        bool leading)
8304 {
8305         struct bnx2x_queue_state_params q_params = {NULL};
8306         struct bnx2x_queue_setup_params *setup_params =
8307                                                 &q_params.params.setup;
8308         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8309                                                 &q_params.params.tx_only;
8310         int rc;
8311         u8 tx_index;
8312
8313         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8314
8315         /* reset IGU state skip FCoE L2 queue */
8316         if (!IS_FCOE_FP(fp))
8317                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8318                              IGU_INT_ENABLE, 0);
8319
8320         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8321         /* We want to wait for completion in this context */
8322         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8323
8324         /* Prepare the INIT parameters */
8325         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8326
8327         /* Set the command */
8328         q_params.cmd = BNX2X_Q_CMD_INIT;
8329
8330         /* Change the state to INIT */
8331         rc = bnx2x_queue_state_change(bp, &q_params);
8332         if (rc) {
8333                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8334                 return rc;
8335         }
8336
8337         DP(NETIF_MSG_IFUP, "init complete\n");
8338
8339         /* Now move the Queue to the SETUP state... */
8340         memset(setup_params, 0, sizeof(*setup_params));
8341
8342         /* Set QUEUE flags */
8343         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8344
8345         /* Set general SETUP parameters */
8346         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8347                                 FIRST_TX_COS_INDEX);
8348
8349         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8350                             &setup_params->rxq_params);
8351
8352         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8353                            FIRST_TX_COS_INDEX);
8354
8355         /* Set the command */
8356         q_params.cmd = BNX2X_Q_CMD_SETUP;
8357
8358         if (IS_FCOE_FP(fp))
8359                 bp->fcoe_init = true;
8360
8361         /* Change the state to SETUP */
8362         rc = bnx2x_queue_state_change(bp, &q_params);
8363         if (rc) {
8364                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8365                 return rc;
8366         }
8367
8368         /* loop through the relevant tx-only indices */
8369         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8370               tx_index < fp->max_cos;
8371               tx_index++) {
8372
8373                 /* prepare and send tx-only ramrod*/
8374                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8375                                           tx_only_params, tx_index, leading);
8376                 if (rc) {
8377                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8378                                   fp->index, tx_index);
8379                         return rc;
8380                 }
8381         }
8382
8383         return rc;
8384 }
8385
8386 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8387 {
8388         struct bnx2x_fastpath *fp = &bp->fp[index];
8389         struct bnx2x_fp_txdata *txdata;
8390         struct bnx2x_queue_state_params q_params = {NULL};
8391         int rc, tx_index;
8392
8393         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8394
8395         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8396         /* We want to wait for completion in this context */
8397         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8398
8399         /* close tx-only connections */
8400         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8401              tx_index < fp->max_cos;
8402              tx_index++){
8403
8404                 /* ascertain this is a normal queue*/
8405                 txdata = fp->txdata_ptr[tx_index];
8406
8407                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8408                                                         txdata->txq_index);
8409
8410                 /* send halt terminate on tx-only connection */
8411                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8412                 memset(&q_params.params.terminate, 0,
8413                        sizeof(q_params.params.terminate));
8414                 q_params.params.terminate.cid_index = tx_index;
8415
8416                 rc = bnx2x_queue_state_change(bp, &q_params);
8417                 if (rc)
8418                         return rc;
8419
8420                 /* send halt terminate on tx-only connection */
8421                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8422                 memset(&q_params.params.cfc_del, 0,
8423                        sizeof(q_params.params.cfc_del));
8424                 q_params.params.cfc_del.cid_index = tx_index;
8425                 rc = bnx2x_queue_state_change(bp, &q_params);
8426                 if (rc)
8427                         return rc;
8428         }
8429         /* Stop the primary connection: */
8430         /* ...halt the connection */
8431         q_params.cmd = BNX2X_Q_CMD_HALT;
8432         rc = bnx2x_queue_state_change(bp, &q_params);
8433         if (rc)
8434                 return rc;
8435
8436         /* ...terminate the connection */
8437         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8438         memset(&q_params.params.terminate, 0,
8439                sizeof(q_params.params.terminate));
8440         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8441         rc = bnx2x_queue_state_change(bp, &q_params);
8442         if (rc)
8443                 return rc;
8444         /* ...delete cfc entry */
8445         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8446         memset(&q_params.params.cfc_del, 0,
8447                sizeof(q_params.params.cfc_del));
8448         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8449         return bnx2x_queue_state_change(bp, &q_params);
8450 }
8451
8452 static void bnx2x_reset_func(struct bnx2x *bp)
8453 {
8454         int port = BP_PORT(bp);
8455         int func = BP_FUNC(bp);
8456         int i;
8457
8458         /* Disable the function in the FW */
8459         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8460         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8461         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8462         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8463
8464         /* FP SBs */
8465         for_each_eth_queue(bp, i) {
8466                 struct bnx2x_fastpath *fp = &bp->fp[i];
8467                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8468                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8469                            SB_DISABLED);
8470         }
8471
8472         if (CNIC_LOADED(bp))
8473                 /* CNIC SB */
8474                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8475                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8476                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8477
8478         /* SP SB */
8479         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8480                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8481                 SB_DISABLED);
8482
8483         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8484                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8485                        0);
8486
8487         /* Configure IGU */
8488         if (bp->common.int_block == INT_BLOCK_HC) {
8489                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8490                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8491         } else {
8492                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8493                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8494         }
8495
8496         if (CNIC_LOADED(bp)) {
8497                 /* Disable Timer scan */
8498                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8499                 /*
8500                  * Wait for at least 10ms and up to 2 second for the timers
8501                  * scan to complete
8502                  */
8503                 for (i = 0; i < 200; i++) {
8504                         usleep_range(10000, 20000);
8505                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8506                                 break;
8507                 }
8508         }
8509         /* Clear ILT */
8510         bnx2x_clear_func_ilt(bp, func);
8511
8512         /* Timers workaround bug for E2: if this is vnic-3,
8513          * we need to set the entire ilt range for this timers.
8514          */
8515         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8516                 struct ilt_client_info ilt_cli;
8517                 /* use dummy TM client */
8518                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8519                 ilt_cli.start = 0;
8520                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8521                 ilt_cli.client_num = ILT_CLIENT_TM;
8522
8523                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8524         }
8525
8526         /* this assumes that reset_port() called before reset_func()*/
8527         if (!CHIP_IS_E1x(bp))
8528                 bnx2x_pf_disable(bp);
8529
8530         bp->dmae_ready = 0;
8531 }
8532
8533 static void bnx2x_reset_port(struct bnx2x *bp)
8534 {
8535         int port = BP_PORT(bp);
8536         u32 val;
8537
8538         /* Reset physical Link */
8539         bnx2x__link_reset(bp);
8540
8541         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8542
8543         /* Do not rcv packets to BRB */
8544         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8545         /* Do not direct rcv packets that are not for MCP to the BRB */
8546         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8547                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8548
8549         /* Configure AEU */
8550         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8551
8552         msleep(100);
8553         /* Check for BRB port occupancy */
8554         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8555         if (val)
8556                 DP(NETIF_MSG_IFDOWN,
8557                    "BRB1 is not empty  %d blocks are occupied\n", val);
8558
8559         /* TODO: Close Doorbell port? */
8560 }
8561
8562 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8563 {
8564         struct bnx2x_func_state_params func_params = {NULL};
8565
8566         /* Prepare parameters for function state transitions */
8567         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8568
8569         func_params.f_obj = &bp->func_obj;
8570         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8571
8572         func_params.params.hw_init.load_phase = load_code;
8573
8574         return bnx2x_func_state_change(bp, &func_params);
8575 }
8576
8577 static int bnx2x_func_stop(struct bnx2x *bp)
8578 {
8579         struct bnx2x_func_state_params func_params = {NULL};
8580         int rc;
8581
8582         /* Prepare parameters for function state transitions */
8583         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8584         func_params.f_obj = &bp->func_obj;
8585         func_params.cmd = BNX2X_F_CMD_STOP;
8586
8587         /*
8588          * Try to stop the function the 'good way'. If fails (in case
8589          * of a parity error during bnx2x_chip_cleanup()) and we are
8590          * not in a debug mode, perform a state transaction in order to
8591          * enable further HW_RESET transaction.
8592          */
8593         rc = bnx2x_func_state_change(bp, &func_params);
8594         if (rc) {
8595 #ifdef BNX2X_STOP_ON_ERROR
8596                 return rc;
8597 #else
8598                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8599                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8600                 return bnx2x_func_state_change(bp, &func_params);
8601 #endif
8602         }
8603
8604         return 0;
8605 }
8606
8607 /**
8608  * bnx2x_send_unload_req - request unload mode from the MCP.
8609  *
8610  * @bp:                 driver handle
8611  * @unload_mode:        requested function's unload mode
8612  *
8613  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8614  */
8615 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8616 {
8617         u32 reset_code = 0;
8618         int port = BP_PORT(bp);
8619
8620         /* Select the UNLOAD request mode */
8621         if (unload_mode == UNLOAD_NORMAL)
8622                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8623
8624         else if (bp->flags & NO_WOL_FLAG)
8625                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8626
8627         else if (bp->wol) {
8628                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8629                 u8 *mac_addr = bp->dev->dev_addr;
8630                 u32 val;
8631                 u16 pmc;
8632
8633                 /* The mac address is written to entries 1-4 to
8634                  * preserve entry 0 which is used by the PMF
8635                  */
8636                 u8 entry = (BP_VN(bp) + 1)*8;
8637
8638                 val = (mac_addr[0] << 8) | mac_addr[1];
8639                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8640
8641                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8642                       (mac_addr[4] << 8) | mac_addr[5];
8643                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8644
8645                 /* Enable the PME and clear the status */
8646                 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8647                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8648                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8649
8650                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8651
8652         } else
8653                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8654
8655         /* Send the request to the MCP */
8656         if (!BP_NOMCP(bp))
8657                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8658         else {
8659                 int path = BP_PATH(bp);
8660
8661                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8662                    path, load_count[path][0], load_count[path][1],
8663                    load_count[path][2]);
8664                 load_count[path][0]--;
8665                 load_count[path][1 + port]--;
8666                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8667                    path, load_count[path][0], load_count[path][1],
8668                    load_count[path][2]);
8669                 if (load_count[path][0] == 0)
8670                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8671                 else if (load_count[path][1 + port] == 0)
8672                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8673                 else
8674                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8675         }
8676
8677         return reset_code;
8678 }
8679
8680 /**
8681  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8682  *
8683  * @bp:         driver handle
8684  * @keep_link:          true iff link should be kept up
8685  */
8686 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8687 {
8688         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8689
8690         /* Report UNLOAD_DONE to MCP */
8691         if (!BP_NOMCP(bp))
8692                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8693 }
8694
8695 static int bnx2x_func_wait_started(struct bnx2x *bp)
8696 {
8697         int tout = 50;
8698         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8699
8700         if (!bp->port.pmf)
8701                 return 0;
8702
8703         /*
8704          * (assumption: No Attention from MCP at this stage)
8705          * PMF probably in the middle of TX disable/enable transaction
8706          * 1. Sync IRS for default SB
8707          * 2. Sync SP queue - this guarantees us that attention handling started
8708          * 3. Wait, that TX disable/enable transaction completes
8709          *
8710          * 1+2 guarantee that if DCBx attention was scheduled it already changed
8711          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8712          * received completion for the transaction the state is TX_STOPPED.
8713          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8714          * transaction.
8715          */
8716
8717         /* make sure default SB ISR is done */
8718         if (msix)
8719                 synchronize_irq(bp->msix_table[0].vector);
8720         else
8721                 synchronize_irq(bp->pdev->irq);
8722
8723         flush_workqueue(bnx2x_wq);
8724
8725         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8726                                 BNX2X_F_STATE_STARTED && tout--)
8727                 msleep(20);
8728
8729         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8730                                                 BNX2X_F_STATE_STARTED) {
8731 #ifdef BNX2X_STOP_ON_ERROR
8732                 BNX2X_ERR("Wrong function state\n");
8733                 return -EBUSY;
8734 #else
8735                 /*
8736                  * Failed to complete the transaction in a "good way"
8737                  * Force both transactions with CLR bit
8738                  */
8739                 struct bnx2x_func_state_params func_params = {NULL};
8740
8741                 DP(NETIF_MSG_IFDOWN,
8742                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8743
8744                 func_params.f_obj = &bp->func_obj;
8745                 __set_bit(RAMROD_DRV_CLR_ONLY,
8746                                         &func_params.ramrod_flags);
8747
8748                 /* STARTED-->TX_ST0PPED */
8749                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8750                 bnx2x_func_state_change(bp, &func_params);
8751
8752                 /* TX_ST0PPED-->STARTED */
8753                 func_params.cmd = BNX2X_F_CMD_TX_START;
8754                 return bnx2x_func_state_change(bp, &func_params);
8755 #endif
8756         }
8757
8758         return 0;
8759 }
8760
8761 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8762 {
8763         int port = BP_PORT(bp);
8764         int i, rc = 0;
8765         u8 cos;
8766         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8767         u32 reset_code;
8768
8769         /* Wait until tx fastpath tasks complete */
8770         for_each_tx_queue(bp, i) {
8771                 struct bnx2x_fastpath *fp = &bp->fp[i];
8772
8773                 for_each_cos_in_tx_queue(fp, cos)
8774                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8775 #ifdef BNX2X_STOP_ON_ERROR
8776                 if (rc)
8777                         return;
8778 #endif
8779         }
8780
8781         /* Give HW time to discard old tx messages */
8782         usleep_range(1000, 2000);
8783
8784         /* Clean all ETH MACs */
8785         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8786                                 false);
8787         if (rc < 0)
8788                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8789
8790         /* Clean up UC list  */
8791         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8792                                 true);
8793         if (rc < 0)
8794                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8795                           rc);
8796
8797         /* Disable LLH */
8798         if (!CHIP_IS_E1(bp))
8799                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8800
8801         /* Set "drop all" (stop Rx).
8802          * We need to take a netif_addr_lock() here in order to prevent
8803          * a race between the completion code and this code.
8804          */
8805         netif_addr_lock_bh(bp->dev);
8806         /* Schedule the rx_mode command */
8807         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8808                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8809         else
8810                 bnx2x_set_storm_rx_mode(bp);
8811
8812         /* Cleanup multicast configuration */
8813         rparam.mcast_obj = &bp->mcast_obj;
8814         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8815         if (rc < 0)
8816                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8817
8818         netif_addr_unlock_bh(bp->dev);
8819
8820         bnx2x_iov_chip_cleanup(bp);
8821
8822         /*
8823          * Send the UNLOAD_REQUEST to the MCP. This will return if
8824          * this function should perform FUNC, PORT or COMMON HW
8825          * reset.
8826          */
8827         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8828
8829         /*
8830          * (assumption: No Attention from MCP at this stage)
8831          * PMF probably in the middle of TX disable/enable transaction
8832          */
8833         rc = bnx2x_func_wait_started(bp);
8834         if (rc) {
8835                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8836 #ifdef BNX2X_STOP_ON_ERROR
8837                 return;
8838 #endif
8839         }
8840
8841         /* Close multi and leading connections
8842          * Completions for ramrods are collected in a synchronous way
8843          */
8844         for_each_eth_queue(bp, i)
8845                 if (bnx2x_stop_queue(bp, i))
8846 #ifdef BNX2X_STOP_ON_ERROR
8847                         return;
8848 #else
8849                         goto unload_error;
8850 #endif
8851
8852         if (CNIC_LOADED(bp)) {
8853                 for_each_cnic_queue(bp, i)
8854                         if (bnx2x_stop_queue(bp, i))
8855 #ifdef BNX2X_STOP_ON_ERROR
8856                                 return;
8857 #else
8858                                 goto unload_error;
8859 #endif
8860         }
8861
8862         /* If SP settings didn't get completed so far - something
8863          * very wrong has happen.
8864          */
8865         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8866                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8867
8868 #ifndef BNX2X_STOP_ON_ERROR
8869 unload_error:
8870 #endif
8871         rc = bnx2x_func_stop(bp);
8872         if (rc) {
8873                 BNX2X_ERR("Function stop failed!\n");
8874 #ifdef BNX2X_STOP_ON_ERROR
8875                 return;
8876 #endif
8877         }
8878
8879         /* Disable HW interrupts, NAPI */
8880         bnx2x_netif_stop(bp, 1);
8881         /* Delete all NAPI objects */
8882         bnx2x_del_all_napi(bp);
8883         if (CNIC_LOADED(bp))
8884                 bnx2x_del_all_napi_cnic(bp);
8885
8886         /* Release IRQs */
8887         bnx2x_free_irq(bp);
8888
8889         /* Reset the chip */
8890         rc = bnx2x_reset_hw(bp, reset_code);
8891         if (rc)
8892                 BNX2X_ERR("HW_RESET failed\n");
8893
8894         /* Report UNLOAD_DONE to MCP */
8895         bnx2x_send_unload_done(bp, keep_link);
8896 }
8897
8898 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8899 {
8900         u32 val;
8901
8902         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8903
8904         if (CHIP_IS_E1(bp)) {
8905                 int port = BP_PORT(bp);
8906                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8907                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8908
8909                 val = REG_RD(bp, addr);
8910                 val &= ~(0x300);
8911                 REG_WR(bp, addr, val);
8912         } else {
8913                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8914                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8915                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8916                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8917         }
8918 }
8919
8920 /* Close gates #2, #3 and #4: */
8921 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8922 {
8923         u32 val;
8924
8925         /* Gates #2 and #4a are closed/opened for "not E1" only */
8926         if (!CHIP_IS_E1(bp)) {
8927                 /* #4 */
8928                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8929                 /* #2 */
8930                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8931         }
8932
8933         /* #3 */
8934         if (CHIP_IS_E1x(bp)) {
8935                 /* Prevent interrupts from HC on both ports */
8936                 val = REG_RD(bp, HC_REG_CONFIG_1);
8937                 REG_WR(bp, HC_REG_CONFIG_1,
8938                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8939                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8940
8941                 val = REG_RD(bp, HC_REG_CONFIG_0);
8942                 REG_WR(bp, HC_REG_CONFIG_0,
8943                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8944                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8945         } else {
8946                 /* Prevent incoming interrupts in IGU */
8947                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8948
8949                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8950                        (!close) ?
8951                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8952                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8953         }
8954
8955         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8956                 close ? "closing" : "opening");
8957         mmiowb();
8958 }
8959
8960 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
8961
8962 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8963 {
8964         /* Do some magic... */
8965         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8966         *magic_val = val & SHARED_MF_CLP_MAGIC;
8967         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8968 }
8969
8970 /**
8971  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8972  *
8973  * @bp:         driver handle
8974  * @magic_val:  old value of the `magic' bit.
8975  */
8976 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8977 {
8978         /* Restore the `magic' bit value... */
8979         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8980         MF_CFG_WR(bp, shared_mf_config.clp_mb,
8981                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8982 }
8983
8984 /**
8985  * bnx2x_reset_mcp_prep - prepare for MCP reset.
8986  *
8987  * @bp:         driver handle
8988  * @magic_val:  old value of 'magic' bit.
8989  *
8990  * Takes care of CLP configurations.
8991  */
8992 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8993 {
8994         u32 shmem;
8995         u32 validity_offset;
8996
8997         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8998
8999         /* Set `magic' bit in order to save MF config */
9000         if (!CHIP_IS_E1(bp))
9001                 bnx2x_clp_reset_prep(bp, magic_val);
9002
9003         /* Get shmem offset */
9004         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9005         validity_offset =
9006                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9007
9008         /* Clear validity map flags */
9009         if (shmem > 0)
9010                 REG_WR(bp, shmem + validity_offset, 0);
9011 }
9012
9013 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9014 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9015
9016 /**
9017  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9018  *
9019  * @bp: driver handle
9020  */
9021 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9022 {
9023         /* special handling for emulation and FPGA,
9024            wait 10 times longer */
9025         if (CHIP_REV_IS_SLOW(bp))
9026                 msleep(MCP_ONE_TIMEOUT*10);
9027         else
9028                 msleep(MCP_ONE_TIMEOUT);
9029 }
9030
9031 /*
9032  * initializes bp->common.shmem_base and waits for validity signature to appear
9033  */
9034 static int bnx2x_init_shmem(struct bnx2x *bp)
9035 {
9036         int cnt = 0;
9037         u32 val = 0;
9038
9039         do {
9040                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9041                 if (bp->common.shmem_base) {
9042                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9043                         if (val & SHR_MEM_VALIDITY_MB)
9044                                 return 0;
9045                 }
9046
9047                 bnx2x_mcp_wait_one(bp);
9048
9049         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9050
9051         BNX2X_ERR("BAD MCP validity signature\n");
9052
9053         return -ENODEV;
9054 }
9055
9056 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9057 {
9058         int rc = bnx2x_init_shmem(bp);
9059
9060         /* Restore the `magic' bit value */
9061         if (!CHIP_IS_E1(bp))
9062                 bnx2x_clp_reset_done(bp, magic_val);
9063
9064         return rc;
9065 }
9066
9067 static void bnx2x_pxp_prep(struct bnx2x *bp)
9068 {
9069         if (!CHIP_IS_E1(bp)) {
9070                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9071                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9072                 mmiowb();
9073         }
9074 }
9075
9076 /*
9077  * Reset the whole chip except for:
9078  *      - PCIE core
9079  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9080  *              one reset bit)
9081  *      - IGU
9082  *      - MISC (including AEU)
9083  *      - GRC
9084  *      - RBCN, RBCP
9085  */
9086 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9087 {
9088         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9089         u32 global_bits2, stay_reset2;
9090
9091         /*
9092          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9093          * (per chip) blocks.
9094          */
9095         global_bits2 =
9096                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9097                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9098
9099         /* Don't reset the following blocks.
9100          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9101          *            reset, as in 4 port device they might still be owned
9102          *            by the MCP (there is only one leader per path).
9103          */
9104         not_reset_mask1 =
9105                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9106                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9107                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9108
9109         not_reset_mask2 =
9110                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9111                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9112                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9113                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9114                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9115                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9116                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9117                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9118                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9119                 MISC_REGISTERS_RESET_REG_2_PGLC |
9120                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9121                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9122                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9123                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9124                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9125                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9126
9127         /*
9128          * Keep the following blocks in reset:
9129          *  - all xxMACs are handled by the bnx2x_link code.
9130          */
9131         stay_reset2 =
9132                 MISC_REGISTERS_RESET_REG_2_XMAC |
9133                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9134
9135         /* Full reset masks according to the chip */
9136         reset_mask1 = 0xffffffff;
9137
9138         if (CHIP_IS_E1(bp))
9139                 reset_mask2 = 0xffff;
9140         else if (CHIP_IS_E1H(bp))
9141                 reset_mask2 = 0x1ffff;
9142         else if (CHIP_IS_E2(bp))
9143                 reset_mask2 = 0xfffff;
9144         else /* CHIP_IS_E3 */
9145                 reset_mask2 = 0x3ffffff;
9146
9147         /* Don't reset global blocks unless we need to */
9148         if (!global)
9149                 reset_mask2 &= ~global_bits2;
9150
9151         /*
9152          * In case of attention in the QM, we need to reset PXP
9153          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9154          * because otherwise QM reset would release 'close the gates' shortly
9155          * before resetting the PXP, then the PSWRQ would send a write
9156          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9157          * read the payload data from PSWWR, but PSWWR would not
9158          * respond. The write queue in PGLUE would stuck, dmae commands
9159          * would not return. Therefore it's important to reset the second
9160          * reset register (containing the
9161          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9162          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9163          * bit).
9164          */
9165         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9166                reset_mask2 & (~not_reset_mask2));
9167
9168         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9169                reset_mask1 & (~not_reset_mask1));
9170
9171         barrier();
9172         mmiowb();
9173
9174         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9175                reset_mask2 & (~stay_reset2));
9176
9177         barrier();
9178         mmiowb();
9179
9180         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9181         mmiowb();
9182 }
9183
9184 /**
9185  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9186  * It should get cleared in no more than 1s.
9187  *
9188  * @bp: driver handle
9189  *
9190  * It should get cleared in no more than 1s. Returns 0 if
9191  * pending writes bit gets cleared.
9192  */
9193 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9194 {
9195         u32 cnt = 1000;
9196         u32 pend_bits = 0;
9197
9198         do {
9199                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9200
9201                 if (pend_bits == 0)
9202                         break;
9203
9204                 usleep_range(1000, 2000);
9205         } while (cnt-- > 0);
9206
9207         if (cnt <= 0) {
9208                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9209                           pend_bits);
9210                 return -EBUSY;
9211         }
9212
9213         return 0;
9214 }
9215
9216 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9217 {
9218         int cnt = 1000;
9219         u32 val = 0;
9220         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9221         u32 tags_63_32 = 0;
9222
9223         /* Empty the Tetris buffer, wait for 1s */
9224         do {
9225                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9226                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9227                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9228                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9229                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9230                 if (CHIP_IS_E3(bp))
9231                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9232
9233                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9234                     ((port_is_idle_0 & 0x1) == 0x1) &&
9235                     ((port_is_idle_1 & 0x1) == 0x1) &&
9236                     (pgl_exp_rom2 == 0xffffffff) &&
9237                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9238                         break;
9239                 usleep_range(1000, 2000);
9240         } while (cnt-- > 0);
9241
9242         if (cnt <= 0) {
9243                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9244                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9245                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9246                           pgl_exp_rom2);
9247                 return -EAGAIN;
9248         }
9249
9250         barrier();
9251
9252         /* Close gates #2, #3 and #4 */
9253         bnx2x_set_234_gates(bp, true);
9254
9255         /* Poll for IGU VQs for 57712 and newer chips */
9256         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9257                 return -EAGAIN;
9258
9259         /* TBD: Indicate that "process kill" is in progress to MCP */
9260
9261         /* Clear "unprepared" bit */
9262         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9263         barrier();
9264
9265         /* Make sure all is written to the chip before the reset */
9266         mmiowb();
9267
9268         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9269          * PSWHST, GRC and PSWRD Tetris buffer.
9270          */
9271         usleep_range(1000, 2000);
9272
9273         /* Prepare to chip reset: */
9274         /* MCP */
9275         if (global)
9276                 bnx2x_reset_mcp_prep(bp, &val);
9277
9278         /* PXP */
9279         bnx2x_pxp_prep(bp);
9280         barrier();
9281
9282         /* reset the chip */
9283         bnx2x_process_kill_chip_reset(bp, global);
9284         barrier();
9285
9286         /* Recover after reset: */
9287         /* MCP */
9288         if (global && bnx2x_reset_mcp_comp(bp, val))
9289                 return -EAGAIN;
9290
9291         /* TBD: Add resetting the NO_MCP mode DB here */
9292
9293         /* Open the gates #2, #3 and #4 */
9294         bnx2x_set_234_gates(bp, false);
9295
9296         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9297          * reset state, re-enable attentions. */
9298
9299         return 0;
9300 }
9301
9302 static int bnx2x_leader_reset(struct bnx2x *bp)
9303 {
9304         int rc = 0;
9305         bool global = bnx2x_reset_is_global(bp);
9306         u32 load_code;
9307
9308         /* if not going to reset MCP - load "fake" driver to reset HW while
9309          * driver is owner of the HW
9310          */
9311         if (!global && !BP_NOMCP(bp)) {
9312                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9313                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9314                 if (!load_code) {
9315                         BNX2X_ERR("MCP response failure, aborting\n");
9316                         rc = -EAGAIN;
9317                         goto exit_leader_reset;
9318                 }
9319                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9320                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9321                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9322                         rc = -EAGAIN;
9323                         goto exit_leader_reset2;
9324                 }
9325                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9326                 if (!load_code) {
9327                         BNX2X_ERR("MCP response failure, aborting\n");
9328                         rc = -EAGAIN;
9329                         goto exit_leader_reset2;
9330                 }
9331         }
9332
9333         /* Try to recover after the failure */
9334         if (bnx2x_process_kill(bp, global)) {
9335                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9336                           BP_PATH(bp));
9337                 rc = -EAGAIN;
9338                 goto exit_leader_reset2;
9339         }
9340
9341         /*
9342          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9343          * state.
9344          */
9345         bnx2x_set_reset_done(bp);
9346         if (global)
9347                 bnx2x_clear_reset_global(bp);
9348
9349 exit_leader_reset2:
9350         /* unload "fake driver" if it was loaded */
9351         if (!global && !BP_NOMCP(bp)) {
9352                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9353                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9354         }
9355 exit_leader_reset:
9356         bp->is_leader = 0;
9357         bnx2x_release_leader_lock(bp);
9358         smp_mb();
9359         return rc;
9360 }
9361
9362 static void bnx2x_recovery_failed(struct bnx2x *bp)
9363 {
9364         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9365
9366         /* Disconnect this device */
9367         netif_device_detach(bp->dev);
9368
9369         /*
9370          * Block ifup for all function on this engine until "process kill"
9371          * or power cycle.
9372          */
9373         bnx2x_set_reset_in_progress(bp);
9374
9375         /* Shut down the power */
9376         bnx2x_set_power_state(bp, PCI_D3hot);
9377
9378         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9379
9380         smp_mb();
9381 }
9382
9383 /*
9384  * Assumption: runs under rtnl lock. This together with the fact
9385  * that it's called only from bnx2x_sp_rtnl() ensure that it
9386  * will never be called when netif_running(bp->dev) is false.
9387  */
9388 static void bnx2x_parity_recover(struct bnx2x *bp)
9389 {
9390         bool global = false;
9391         u32 error_recovered, error_unrecovered;
9392         bool is_parity;
9393
9394         DP(NETIF_MSG_HW, "Handling parity\n");
9395         while (1) {
9396                 switch (bp->recovery_state) {
9397                 case BNX2X_RECOVERY_INIT:
9398                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9399                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9400                         WARN_ON(!is_parity);
9401
9402                         /* Try to get a LEADER_LOCK HW lock */
9403                         if (bnx2x_trylock_leader_lock(bp)) {
9404                                 bnx2x_set_reset_in_progress(bp);
9405                                 /*
9406                                  * Check if there is a global attention and if
9407                                  * there was a global attention, set the global
9408                                  * reset bit.
9409                                  */
9410
9411                                 if (global)
9412                                         bnx2x_set_reset_global(bp);
9413
9414                                 bp->is_leader = 1;
9415                         }
9416
9417                         /* Stop the driver */
9418                         /* If interface has been removed - break */
9419                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9420                                 return;
9421
9422                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9423
9424                         /* Ensure "is_leader", MCP command sequence and
9425                          * "recovery_state" update values are seen on other
9426                          * CPUs.
9427                          */
9428                         smp_mb();
9429                         break;
9430
9431                 case BNX2X_RECOVERY_WAIT:
9432                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9433                         if (bp->is_leader) {
9434                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9435                                 bool other_load_status =
9436                                         bnx2x_get_load_status(bp, other_engine);
9437                                 bool load_status =
9438                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9439                                 global = bnx2x_reset_is_global(bp);
9440
9441                                 /*
9442                                  * In case of a parity in a global block, let
9443                                  * the first leader that performs a
9444                                  * leader_reset() reset the global blocks in
9445                                  * order to clear global attentions. Otherwise
9446                                  * the gates will remain closed for that
9447                                  * engine.
9448                                  */
9449                                 if (load_status ||
9450                                     (global && other_load_status)) {
9451                                         /* Wait until all other functions get
9452                                          * down.
9453                                          */
9454                                         schedule_delayed_work(&bp->sp_rtnl_task,
9455                                                                 HZ/10);
9456                                         return;
9457                                 } else {
9458                                         /* If all other functions got down -
9459                                          * try to bring the chip back to
9460                                          * normal. In any case it's an exit
9461                                          * point for a leader.
9462                                          */
9463                                         if (bnx2x_leader_reset(bp)) {
9464                                                 bnx2x_recovery_failed(bp);
9465                                                 return;
9466                                         }
9467
9468                                         /* If we are here, means that the
9469                                          * leader has succeeded and doesn't
9470                                          * want to be a leader any more. Try
9471                                          * to continue as a none-leader.
9472                                          */
9473                                         break;
9474                                 }
9475                         } else { /* non-leader */
9476                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9477                                         /* Try to get a LEADER_LOCK HW lock as
9478                                          * long as a former leader may have
9479                                          * been unloaded by the user or
9480                                          * released a leadership by another
9481                                          * reason.
9482                                          */
9483                                         if (bnx2x_trylock_leader_lock(bp)) {
9484                                                 /* I'm a leader now! Restart a
9485                                                  * switch case.
9486                                                  */
9487                                                 bp->is_leader = 1;
9488                                                 break;
9489                                         }
9490
9491                                         schedule_delayed_work(&bp->sp_rtnl_task,
9492                                                                 HZ/10);
9493                                         return;
9494
9495                                 } else {
9496                                         /*
9497                                          * If there was a global attention, wait
9498                                          * for it to be cleared.
9499                                          */
9500                                         if (bnx2x_reset_is_global(bp)) {
9501                                                 schedule_delayed_work(
9502                                                         &bp->sp_rtnl_task,
9503                                                         HZ/10);
9504                                                 return;
9505                                         }
9506
9507                                         error_recovered =
9508                                           bp->eth_stats.recoverable_error;
9509                                         error_unrecovered =
9510                                           bp->eth_stats.unrecoverable_error;
9511                                         bp->recovery_state =
9512                                                 BNX2X_RECOVERY_NIC_LOADING;
9513                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9514                                                 error_unrecovered++;
9515                                                 netdev_err(bp->dev,
9516                                                            "Recovery failed. Power cycle needed\n");
9517                                                 /* Disconnect this device */
9518                                                 netif_device_detach(bp->dev);
9519                                                 /* Shut down the power */
9520                                                 bnx2x_set_power_state(
9521                                                         bp, PCI_D3hot);
9522                                                 smp_mb();
9523                                         } else {
9524                                                 bp->recovery_state =
9525                                                         BNX2X_RECOVERY_DONE;
9526                                                 error_recovered++;
9527                                                 smp_mb();
9528                                         }
9529                                         bp->eth_stats.recoverable_error =
9530                                                 error_recovered;
9531                                         bp->eth_stats.unrecoverable_error =
9532                                                 error_unrecovered;
9533
9534                                         return;
9535                                 }
9536                         }
9537                 default:
9538                         return;
9539                 }
9540         }
9541 }
9542
9543 static int bnx2x_close(struct net_device *dev);
9544
9545 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9546  * scheduled on a general queue in order to prevent a dead lock.
9547  */
9548 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9549 {
9550         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9551
9552         rtnl_lock();
9553
9554         if (!netif_running(bp->dev)) {
9555                 rtnl_unlock();
9556                 return;
9557         }
9558
9559         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9560 #ifdef BNX2X_STOP_ON_ERROR
9561                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9562                           "you will need to reboot when done\n");
9563                 goto sp_rtnl_not_reset;
9564 #endif
9565                 /*
9566                  * Clear all pending SP commands as we are going to reset the
9567                  * function anyway.
9568                  */
9569                 bp->sp_rtnl_state = 0;
9570                 smp_mb();
9571
9572                 bnx2x_parity_recover(bp);
9573
9574                 rtnl_unlock();
9575                 return;
9576         }
9577
9578         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9579 #ifdef BNX2X_STOP_ON_ERROR
9580                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9581                           "you will need to reboot when done\n");
9582                 goto sp_rtnl_not_reset;
9583 #endif
9584
9585                 /*
9586                  * Clear all pending SP commands as we are going to reset the
9587                  * function anyway.
9588                  */
9589                 bp->sp_rtnl_state = 0;
9590                 smp_mb();
9591
9592                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9593                 bnx2x_nic_load(bp, LOAD_NORMAL);
9594
9595                 rtnl_unlock();
9596                 return;
9597         }
9598 #ifdef BNX2X_STOP_ON_ERROR
9599 sp_rtnl_not_reset:
9600 #endif
9601         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9602                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9603         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9604                 bnx2x_after_function_update(bp);
9605         /*
9606          * in case of fan failure we need to reset id if the "stop on error"
9607          * debug flag is set, since we trying to prevent permanent overheating
9608          * damage
9609          */
9610         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9611                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9612                 netif_device_detach(bp->dev);
9613                 bnx2x_close(bp->dev);
9614                 rtnl_unlock();
9615                 return;
9616         }
9617
9618         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9619                 DP(BNX2X_MSG_SP,
9620                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9621                 bnx2x_vfpf_set_mcast(bp->dev);
9622         }
9623
9624         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9625                                &bp->sp_rtnl_state)) {
9626                 DP(BNX2X_MSG_SP,
9627                    "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9628                 bnx2x_vfpf_storm_rx_mode(bp);
9629         }
9630
9631         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9632                                &bp->sp_rtnl_state))
9633                 bnx2x_pf_set_vfs_vlan(bp);
9634
9635         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9636          * can be called from other contexts as well)
9637          */
9638         rtnl_unlock();
9639
9640         /* enable SR-IOV if applicable */
9641         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9642                                                &bp->sp_rtnl_state)) {
9643                 bnx2x_disable_sriov(bp);
9644                 bnx2x_enable_sriov(bp);
9645         }
9646 }
9647
9648 static void bnx2x_period_task(struct work_struct *work)
9649 {
9650         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9651
9652         if (!netif_running(bp->dev))
9653                 goto period_task_exit;
9654
9655         if (CHIP_REV_IS_SLOW(bp)) {
9656                 BNX2X_ERR("period task called on emulation, ignoring\n");
9657                 goto period_task_exit;
9658         }
9659
9660         bnx2x_acquire_phy_lock(bp);
9661         /*
9662          * The barrier is needed to ensure the ordering between the writing to
9663          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9664          * the reading here.
9665          */
9666         smp_mb();
9667         if (bp->port.pmf) {
9668                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9669
9670                 /* Re-queue task in 1 sec */
9671                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9672         }
9673
9674         bnx2x_release_phy_lock(bp);
9675 period_task_exit:
9676         return;
9677 }
9678
9679 /*
9680  * Init service functions
9681  */
9682
9683 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9684 {
9685         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9686         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9687         return base + (BP_ABS_FUNC(bp)) * stride;
9688 }
9689
9690 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9691                                         struct bnx2x_mac_vals *vals)
9692 {
9693         u32 val, base_addr, offset, mask, reset_reg;
9694         bool mac_stopped = false;
9695         u8 port = BP_PORT(bp);
9696
9697         /* reset addresses as they also mark which values were changed */
9698         vals->bmac_addr = 0;
9699         vals->umac_addr = 0;
9700         vals->xmac_addr = 0;
9701         vals->emac_addr = 0;
9702
9703         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9704
9705         if (!CHIP_IS_E3(bp)) {
9706                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9707                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9708                 if ((mask & reset_reg) && val) {
9709                         u32 wb_data[2];
9710                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9711                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9712                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9713                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9714                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9715
9716                         /*
9717                          * use rd/wr since we cannot use dmae. This is safe
9718                          * since MCP won't access the bus due to the request
9719                          * to unload, and no function on the path can be
9720                          * loaded at this time.
9721                          */
9722                         wb_data[0] = REG_RD(bp, base_addr + offset);
9723                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9724                         vals->bmac_addr = base_addr + offset;
9725                         vals->bmac_val[0] = wb_data[0];
9726                         vals->bmac_val[1] = wb_data[1];
9727                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9728                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
9729                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9730                 }
9731                 BNX2X_DEV_INFO("Disable emac Rx\n");
9732                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9733                 vals->emac_val = REG_RD(bp, vals->emac_addr);
9734                 REG_WR(bp, vals->emac_addr, 0);
9735                 mac_stopped = true;
9736         } else {
9737                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9738                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9739                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9740                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9741                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9742                                val & ~(1 << 1));
9743                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9744                                val | (1 << 1));
9745                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9746                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9747                         REG_WR(bp, vals->xmac_addr, 0);
9748                         mac_stopped = true;
9749                 }
9750                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9751                 if (mask & reset_reg) {
9752                         BNX2X_DEV_INFO("Disable umac Rx\n");
9753                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9754                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9755                         vals->umac_val = REG_RD(bp, vals->umac_addr);
9756                         REG_WR(bp, vals->umac_addr, 0);
9757                         mac_stopped = true;
9758                 }
9759         }
9760
9761         if (mac_stopped)
9762                 msleep(20);
9763 }
9764
9765 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9766 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9767 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9768 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9769
9770 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9771 {
9772         u16 rcq, bd;
9773         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9774
9775         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9776         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9777
9778         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9779         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9780
9781         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9782                        port, bd, rcq);
9783 }
9784
9785 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9786 {
9787         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9788                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9789         if (!rc) {
9790                 BNX2X_ERR("MCP response failure, aborting\n");
9791                 return -EBUSY;
9792         }
9793
9794         return 0;
9795 }
9796
9797 static struct bnx2x_prev_path_list *
9798                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9799 {
9800         struct bnx2x_prev_path_list *tmp_list;
9801
9802         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9803                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9804                     bp->pdev->bus->number == tmp_list->bus &&
9805                     BP_PATH(bp) == tmp_list->path)
9806                         return tmp_list;
9807
9808         return NULL;
9809 }
9810
9811 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9812 {
9813         struct bnx2x_prev_path_list *tmp_list;
9814         int rc;
9815
9816         rc = down_interruptible(&bnx2x_prev_sem);
9817         if (rc) {
9818                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9819                 return rc;
9820         }
9821
9822         tmp_list = bnx2x_prev_path_get_entry(bp);
9823         if (tmp_list) {
9824                 tmp_list->aer = 1;
9825                 rc = 0;
9826         } else {
9827                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9828                           BP_PATH(bp));
9829         }
9830
9831         up(&bnx2x_prev_sem);
9832
9833         return rc;
9834 }
9835
9836 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9837 {
9838         struct bnx2x_prev_path_list *tmp_list;
9839         int rc = false;
9840
9841         if (down_trylock(&bnx2x_prev_sem))
9842                 return false;
9843
9844         tmp_list = bnx2x_prev_path_get_entry(bp);
9845         if (tmp_list) {
9846                 if (tmp_list->aer) {
9847                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9848                            BP_PATH(bp));
9849                 } else {
9850                         rc = true;
9851                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9852                                        BP_PATH(bp));
9853                 }
9854         }
9855
9856         up(&bnx2x_prev_sem);
9857
9858         return rc;
9859 }
9860
9861 bool bnx2x_port_after_undi(struct bnx2x *bp)
9862 {
9863         struct bnx2x_prev_path_list *entry;
9864         bool val;
9865
9866         down(&bnx2x_prev_sem);
9867
9868         entry = bnx2x_prev_path_get_entry(bp);
9869         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
9870
9871         up(&bnx2x_prev_sem);
9872
9873         return val;
9874 }
9875
9876 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9877 {
9878         struct bnx2x_prev_path_list *tmp_list;
9879         int rc;
9880
9881         rc = down_interruptible(&bnx2x_prev_sem);
9882         if (rc) {
9883                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9884                 return rc;
9885         }
9886
9887         /* Check whether the entry for this path already exists */
9888         tmp_list = bnx2x_prev_path_get_entry(bp);
9889         if (tmp_list) {
9890                 if (!tmp_list->aer) {
9891                         BNX2X_ERR("Re-Marking the path.\n");
9892                 } else {
9893                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9894                            BP_PATH(bp));
9895                         tmp_list->aer = 0;
9896                 }
9897                 up(&bnx2x_prev_sem);
9898                 return 0;
9899         }
9900         up(&bnx2x_prev_sem);
9901
9902         /* Create an entry for this path and add it */
9903         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9904         if (!tmp_list) {
9905                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9906                 return -ENOMEM;
9907         }
9908
9909         tmp_list->bus = bp->pdev->bus->number;
9910         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9911         tmp_list->path = BP_PATH(bp);
9912         tmp_list->aer = 0;
9913         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9914
9915         rc = down_interruptible(&bnx2x_prev_sem);
9916         if (rc) {
9917                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9918                 kfree(tmp_list);
9919         } else {
9920                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
9921                    BP_PATH(bp));
9922                 list_add(&tmp_list->list, &bnx2x_prev_list);
9923                 up(&bnx2x_prev_sem);
9924         }
9925
9926         return rc;
9927 }
9928
9929 static int bnx2x_do_flr(struct bnx2x *bp)
9930 {
9931         int i;
9932         u16 status;
9933         struct pci_dev *dev = bp->pdev;
9934
9935         if (CHIP_IS_E1x(bp)) {
9936                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9937                 return -EINVAL;
9938         }
9939
9940         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9941         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9942                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9943                           bp->common.bc_ver);
9944                 return -EINVAL;
9945         }
9946
9947         /* Wait for Transaction Pending bit clean */
9948         for (i = 0; i < 4; i++) {
9949                 if (i)
9950                         msleep((1 << (i - 1)) * 100);
9951
9952                 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9953                 if (!(status & PCI_EXP_DEVSTA_TRPND))
9954                         goto clear;
9955         }
9956
9957         dev_err(&dev->dev,
9958                 "transaction is not cleared; proceeding with reset anyway\n");
9959
9960 clear:
9961
9962         BNX2X_DEV_INFO("Initiating FLR\n");
9963         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9964
9965         return 0;
9966 }
9967
9968 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9969 {
9970         int rc;
9971
9972         BNX2X_DEV_INFO("Uncommon unload Flow\n");
9973
9974         /* Test if previous unload process was already finished for this path */
9975         if (bnx2x_prev_is_path_marked(bp))
9976                 return bnx2x_prev_mcp_done(bp);
9977
9978         BNX2X_DEV_INFO("Path is unmarked\n");
9979
9980         /* If function has FLR capabilities, and existing FW version matches
9981          * the one required, then FLR will be sufficient to clean any residue
9982          * left by previous driver
9983          */
9984         rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9985
9986         if (!rc) {
9987                 /* fw version is good */
9988                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9989                 rc = bnx2x_do_flr(bp);
9990         }
9991
9992         if (!rc) {
9993                 /* FLR was performed */
9994                 BNX2X_DEV_INFO("FLR successful\n");
9995                 return 0;
9996         }
9997
9998         BNX2X_DEV_INFO("Could not FLR\n");
9999
10000         /* Close the MCP request, return failure*/
10001         rc = bnx2x_prev_mcp_done(bp);
10002         if (!rc)
10003                 rc = BNX2X_PREV_WAIT_NEEDED;
10004
10005         return rc;
10006 }
10007
10008 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10009 {
10010         u32 reset_reg, tmp_reg = 0, rc;
10011         bool prev_undi = false;
10012         struct bnx2x_mac_vals mac_vals;
10013
10014         /* It is possible a previous function received 'common' answer,
10015          * but hasn't loaded yet, therefore creating a scenario of
10016          * multiple functions receiving 'common' on the same path.
10017          */
10018         BNX2X_DEV_INFO("Common unload Flow\n");
10019
10020         memset(&mac_vals, 0, sizeof(mac_vals));
10021
10022         if (bnx2x_prev_is_path_marked(bp))
10023                 return bnx2x_prev_mcp_done(bp);
10024
10025         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10026
10027         /* Reset should be performed after BRB is emptied */
10028         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10029                 u32 timer_count = 1000;
10030
10031                 /* Close the MAC Rx to prevent BRB from filling up */
10032                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10033
10034                 /* close LLH filters towards the BRB */
10035                 bnx2x_set_rx_filter(&bp->link_params, 0);
10036
10037                 /* Check if the UNDI driver was previously loaded
10038                  * UNDI driver initializes CID offset for normal bell to 0x7
10039                  */
10040                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10041                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10042                         if (tmp_reg == 0x7) {
10043                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10044                                 prev_undi = true;
10045                                 /* clear the UNDI indication */
10046                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10047                                 /* clear possible idle check errors */
10048                                 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10049                         }
10050                 }
10051                 if (!CHIP_IS_E1x(bp))
10052                         /* block FW from writing to host */
10053                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10054
10055                 /* wait until BRB is empty */
10056                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10057                 while (timer_count) {
10058                         u32 prev_brb = tmp_reg;
10059
10060                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10061                         if (!tmp_reg)
10062                                 break;
10063
10064                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10065
10066                         /* reset timer as long as BRB actually gets emptied */
10067                         if (prev_brb > tmp_reg)
10068                                 timer_count = 1000;
10069                         else
10070                                 timer_count--;
10071
10072                         /* If UNDI resides in memory, manually increment it */
10073                         if (prev_undi)
10074                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10075
10076                         udelay(10);
10077                 }
10078
10079                 if (!timer_count)
10080                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10081         }
10082
10083         /* No packets are in the pipeline, path is ready for reset */
10084         bnx2x_reset_common(bp);
10085
10086         if (mac_vals.xmac_addr)
10087                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10088         if (mac_vals.umac_addr)
10089                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10090         if (mac_vals.emac_addr)
10091                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10092         if (mac_vals.bmac_addr) {
10093                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10094                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10095         }
10096
10097         rc = bnx2x_prev_mark_path(bp, prev_undi);
10098         if (rc) {
10099                 bnx2x_prev_mcp_done(bp);
10100                 return rc;
10101         }
10102
10103         return bnx2x_prev_mcp_done(bp);
10104 }
10105
10106 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10107  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10108  * the addresses of the transaction, resulting in was-error bit set in the pci
10109  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10110  * to clear the interrupt which detected this from the pglueb and the was done
10111  * bit
10112  */
10113 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10114 {
10115         if (!CHIP_IS_E1x(bp)) {
10116                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10117                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10118                         DP(BNX2X_MSG_SP,
10119                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10120                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10121                                1 << BP_FUNC(bp));
10122                 }
10123         }
10124 }
10125
10126 static int bnx2x_prev_unload(struct bnx2x *bp)
10127 {
10128         int time_counter = 10;
10129         u32 rc, fw, hw_lock_reg, hw_lock_val;
10130         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10131
10132         /* clear hw from errors which may have resulted from an interrupted
10133          * dmae transaction.
10134          */
10135         bnx2x_prev_interrupted_dmae(bp);
10136
10137         /* Release previously held locks */
10138         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10139                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10140                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10141
10142         hw_lock_val = REG_RD(bp, hw_lock_reg);
10143         if (hw_lock_val) {
10144                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10145                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10146                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10147                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10148                 }
10149
10150                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10151                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10152         } else
10153                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10154
10155         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10156                 BNX2X_DEV_INFO("Release previously held alr\n");
10157                 bnx2x_release_alr(bp);
10158         }
10159
10160         do {
10161                 int aer = 0;
10162                 /* Lock MCP using an unload request */
10163                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10164                 if (!fw) {
10165                         BNX2X_ERR("MCP response failure, aborting\n");
10166                         rc = -EBUSY;
10167                         break;
10168                 }
10169
10170                 rc = down_interruptible(&bnx2x_prev_sem);
10171                 if (rc) {
10172                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10173                                   rc);
10174                 } else {
10175                         /* If Path is marked by EEH, ignore unload status */
10176                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10177                                  bnx2x_prev_path_get_entry(bp)->aer);
10178                         up(&bnx2x_prev_sem);
10179                 }
10180
10181                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10182                         rc = bnx2x_prev_unload_common(bp);
10183                         break;
10184                 }
10185
10186                 /* non-common reply from MCP might require looping */
10187                 rc = bnx2x_prev_unload_uncommon(bp);
10188                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10189                         break;
10190
10191                 msleep(20);
10192         } while (--time_counter);
10193
10194         if (!time_counter || rc) {
10195                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10196                 rc = -EBUSY;
10197         }
10198
10199         /* Mark function if its port was used to boot from SAN */
10200         if (bnx2x_port_after_undi(bp))
10201                 bp->link_params.feature_config_flags |=
10202                         FEATURE_CONFIG_BOOT_FROM_SAN;
10203
10204         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10205
10206         return rc;
10207 }
10208
10209 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10210 {
10211         u32 val, val2, val3, val4, id, boot_mode;
10212         u16 pmc;
10213
10214         /* Get the chip revision id and number. */
10215         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10216         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10217         id = ((val & 0xffff) << 16);
10218         val = REG_RD(bp, MISC_REG_CHIP_REV);
10219         id |= ((val & 0xf) << 12);
10220
10221         /* Metal is read from PCI regs, but we can't access >=0x400 from
10222          * the configuration space (so we need to reg_rd)
10223          */
10224         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10225         id |= (((val >> 24) & 0xf) << 4);
10226         val = REG_RD(bp, MISC_REG_BOND_ID);
10227         id |= (val & 0xf);
10228         bp->common.chip_id = id;
10229
10230         /* force 57811 according to MISC register */
10231         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10232                 if (CHIP_IS_57810(bp))
10233                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10234                                 (bp->common.chip_id & 0x0000FFFF);
10235                 else if (CHIP_IS_57810_MF(bp))
10236                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10237                                 (bp->common.chip_id & 0x0000FFFF);
10238                 bp->common.chip_id |= 0x1;
10239         }
10240
10241         /* Set doorbell size */
10242         bp->db_size = (1 << BNX2X_DB_SHIFT);
10243
10244         if (!CHIP_IS_E1x(bp)) {
10245                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10246                 if ((val & 1) == 0)
10247                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10248                 else
10249                         val = (val >> 1) & 1;
10250                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10251                                                        "2_PORT_MODE");
10252                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10253                                                  CHIP_2_PORT_MODE;
10254
10255                 if (CHIP_MODE_IS_4_PORT(bp))
10256                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10257                 else
10258                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10259         } else {
10260                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10261                 bp->pfid = bp->pf_num;                  /* 0..7 */
10262         }
10263
10264         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10265
10266         bp->link_params.chip_id = bp->common.chip_id;
10267         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10268
10269         val = (REG_RD(bp, 0x2874) & 0x55);
10270         if ((bp->common.chip_id & 0x1) ||
10271             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10272                 bp->flags |= ONE_PORT_FLAG;
10273                 BNX2X_DEV_INFO("single port device\n");
10274         }
10275
10276         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10277         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10278                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10279         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10280                        bp->common.flash_size, bp->common.flash_size);
10281
10282         bnx2x_init_shmem(bp);
10283
10284         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10285                                         MISC_REG_GENERIC_CR_1 :
10286                                         MISC_REG_GENERIC_CR_0));
10287
10288         bp->link_params.shmem_base = bp->common.shmem_base;
10289         bp->link_params.shmem2_base = bp->common.shmem2_base;
10290         if (SHMEM2_RD(bp, size) >
10291             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10292                 bp->link_params.lfa_base =
10293                 REG_RD(bp, bp->common.shmem2_base +
10294                        (u32)offsetof(struct shmem2_region,
10295                                      lfa_host_addr[BP_PORT(bp)]));
10296         else
10297                 bp->link_params.lfa_base = 0;
10298         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10299                        bp->common.shmem_base, bp->common.shmem2_base);
10300
10301         if (!bp->common.shmem_base) {
10302                 BNX2X_DEV_INFO("MCP not active\n");
10303                 bp->flags |= NO_MCP_FLAG;
10304                 return;
10305         }
10306
10307         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10308         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10309
10310         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10311                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10312                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10313
10314         bp->link_params.feature_config_flags = 0;
10315         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10316         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10317                 bp->link_params.feature_config_flags |=
10318                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10319         else
10320                 bp->link_params.feature_config_flags &=
10321                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10322
10323         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10324         bp->common.bc_ver = val;
10325         BNX2X_DEV_INFO("bc_ver %X\n", val);
10326         if (val < BNX2X_BC_VER) {
10327                 /* for now only warn
10328                  * later we might need to enforce this */
10329                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10330                           BNX2X_BC_VER, val);
10331         }
10332         bp->link_params.feature_config_flags |=
10333                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10334                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10335
10336         bp->link_params.feature_config_flags |=
10337                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10338                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10339         bp->link_params.feature_config_flags |=
10340                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10341                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10342         bp->link_params.feature_config_flags |=
10343                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10344                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10345
10346         bp->link_params.feature_config_flags |=
10347                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10348                 FEATURE_CONFIG_MT_SUPPORT : 0;
10349
10350         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10351                         BC_SUPPORTS_PFC_STATS : 0;
10352
10353         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10354                         BC_SUPPORTS_FCOE_FEATURES : 0;
10355
10356         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10357                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10358         boot_mode = SHMEM_RD(bp,
10359                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10360                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10361         switch (boot_mode) {
10362         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10363                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10364                 break;
10365         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10366                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10367                 break;
10368         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10369                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10370                 break;
10371         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10372                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10373                 break;
10374         }
10375
10376         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10377         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10378
10379         BNX2X_DEV_INFO("%sWoL capable\n",
10380                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10381
10382         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10383         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10384         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10385         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10386
10387         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10388                  val, val2, val3, val4);
10389 }
10390
10391 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10392 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10393
10394 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10395 {
10396         int pfid = BP_FUNC(bp);
10397         int igu_sb_id;
10398         u32 val;
10399         u8 fid, igu_sb_cnt = 0;
10400
10401         bp->igu_base_sb = 0xff;
10402         if (CHIP_INT_MODE_IS_BC(bp)) {
10403                 int vn = BP_VN(bp);
10404                 igu_sb_cnt = bp->igu_sb_cnt;
10405                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10406                         FP_SB_MAX_E1x;
10407
10408                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10409                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10410
10411                 return 0;
10412         }
10413
10414         /* IGU in normal mode - read CAM */
10415         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10416              igu_sb_id++) {
10417                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10418                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10419                         continue;
10420                 fid = IGU_FID(val);
10421                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10422                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10423                                 continue;
10424                         if (IGU_VEC(val) == 0)
10425                                 /* default status block */
10426                                 bp->igu_dsb_id = igu_sb_id;
10427                         else {
10428                                 if (bp->igu_base_sb == 0xff)
10429                                         bp->igu_base_sb = igu_sb_id;
10430                                 igu_sb_cnt++;
10431                         }
10432                 }
10433         }
10434
10435 #ifdef CONFIG_PCI_MSI
10436         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10437          * optional that number of CAM entries will not be equal to the value
10438          * advertised in PCI.
10439          * Driver should use the minimal value of both as the actual status
10440          * block count
10441          */
10442         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10443 #endif
10444
10445         if (igu_sb_cnt == 0) {
10446                 BNX2X_ERR("CAM configuration error\n");
10447                 return -EINVAL;
10448         }
10449
10450         return 0;
10451 }
10452
10453 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10454 {
10455         int cfg_size = 0, idx, port = BP_PORT(bp);
10456
10457         /* Aggregation of supported attributes of all external phys */
10458         bp->port.supported[0] = 0;
10459         bp->port.supported[1] = 0;
10460         switch (bp->link_params.num_phys) {
10461         case 1:
10462                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10463                 cfg_size = 1;
10464                 break;
10465         case 2:
10466                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10467                 cfg_size = 1;
10468                 break;
10469         case 3:
10470                 if (bp->link_params.multi_phy_config &
10471                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10472                         bp->port.supported[1] =
10473                                 bp->link_params.phy[EXT_PHY1].supported;
10474                         bp->port.supported[0] =
10475                                 bp->link_params.phy[EXT_PHY2].supported;
10476                 } else {
10477                         bp->port.supported[0] =
10478                                 bp->link_params.phy[EXT_PHY1].supported;
10479                         bp->port.supported[1] =
10480                                 bp->link_params.phy[EXT_PHY2].supported;
10481                 }
10482                 cfg_size = 2;
10483                 break;
10484         }
10485
10486         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10487                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10488                            SHMEM_RD(bp,
10489                            dev_info.port_hw_config[port].external_phy_config),
10490                            SHMEM_RD(bp,
10491                            dev_info.port_hw_config[port].external_phy_config2));
10492                         return;
10493         }
10494
10495         if (CHIP_IS_E3(bp))
10496                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10497         else {
10498                 switch (switch_cfg) {
10499                 case SWITCH_CFG_1G:
10500                         bp->port.phy_addr = REG_RD(
10501                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10502                         break;
10503                 case SWITCH_CFG_10G:
10504                         bp->port.phy_addr = REG_RD(
10505                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10506                         break;
10507                 default:
10508                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10509                                   bp->port.link_config[0]);
10510                         return;
10511                 }
10512         }
10513         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10514         /* mask what we support according to speed_cap_mask per configuration */
10515         for (idx = 0; idx < cfg_size; idx++) {
10516                 if (!(bp->link_params.speed_cap_mask[idx] &
10517                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10518                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10519
10520                 if (!(bp->link_params.speed_cap_mask[idx] &
10521                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10522                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10523
10524                 if (!(bp->link_params.speed_cap_mask[idx] &
10525                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10526                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10527
10528                 if (!(bp->link_params.speed_cap_mask[idx] &
10529                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10530                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10531
10532                 if (!(bp->link_params.speed_cap_mask[idx] &
10533                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10534                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10535                                                      SUPPORTED_1000baseT_Full);
10536
10537                 if (!(bp->link_params.speed_cap_mask[idx] &
10538                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10539                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10540
10541                 if (!(bp->link_params.speed_cap_mask[idx] &
10542                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10543                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10544         }
10545
10546         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10547                        bp->port.supported[1]);
10548 }
10549
10550 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10551 {
10552         u32 link_config, idx, cfg_size = 0;
10553         bp->port.advertising[0] = 0;
10554         bp->port.advertising[1] = 0;
10555         switch (bp->link_params.num_phys) {
10556         case 1:
10557         case 2:
10558                 cfg_size = 1;
10559                 break;
10560         case 3:
10561                 cfg_size = 2;
10562                 break;
10563         }
10564         for (idx = 0; idx < cfg_size; idx++) {
10565                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10566                 link_config = bp->port.link_config[idx];
10567                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10568                 case PORT_FEATURE_LINK_SPEED_AUTO:
10569                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10570                                 bp->link_params.req_line_speed[idx] =
10571                                         SPEED_AUTO_NEG;
10572                                 bp->port.advertising[idx] |=
10573                                         bp->port.supported[idx];
10574                                 if (bp->link_params.phy[EXT_PHY1].type ==
10575                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10576                                         bp->port.advertising[idx] |=
10577                                         (SUPPORTED_100baseT_Half |
10578                                          SUPPORTED_100baseT_Full);
10579                         } else {
10580                                 /* force 10G, no AN */
10581                                 bp->link_params.req_line_speed[idx] =
10582                                         SPEED_10000;
10583                                 bp->port.advertising[idx] |=
10584                                         (ADVERTISED_10000baseT_Full |
10585                                          ADVERTISED_FIBRE);
10586                                 continue;
10587                         }
10588                         break;
10589
10590                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10591                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10592                                 bp->link_params.req_line_speed[idx] =
10593                                         SPEED_10;
10594                                 bp->port.advertising[idx] |=
10595                                         (ADVERTISED_10baseT_Full |
10596                                          ADVERTISED_TP);
10597                         } else {
10598                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10599                                             link_config,
10600                                     bp->link_params.speed_cap_mask[idx]);
10601                                 return;
10602                         }
10603                         break;
10604
10605                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10606                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10607                                 bp->link_params.req_line_speed[idx] =
10608                                         SPEED_10;
10609                                 bp->link_params.req_duplex[idx] =
10610                                         DUPLEX_HALF;
10611                                 bp->port.advertising[idx] |=
10612                                         (ADVERTISED_10baseT_Half |
10613                                          ADVERTISED_TP);
10614                         } else {
10615                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10616                                             link_config,
10617                                           bp->link_params.speed_cap_mask[idx]);
10618                                 return;
10619                         }
10620                         break;
10621
10622                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10623                         if (bp->port.supported[idx] &
10624                             SUPPORTED_100baseT_Full) {
10625                                 bp->link_params.req_line_speed[idx] =
10626                                         SPEED_100;
10627                                 bp->port.advertising[idx] |=
10628                                         (ADVERTISED_100baseT_Full |
10629                                          ADVERTISED_TP);
10630                         } else {
10631                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10632                                             link_config,
10633                                           bp->link_params.speed_cap_mask[idx]);
10634                                 return;
10635                         }
10636                         break;
10637
10638                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10639                         if (bp->port.supported[idx] &
10640                             SUPPORTED_100baseT_Half) {
10641                                 bp->link_params.req_line_speed[idx] =
10642                                                                 SPEED_100;
10643                                 bp->link_params.req_duplex[idx] =
10644                                                                 DUPLEX_HALF;
10645                                 bp->port.advertising[idx] |=
10646                                         (ADVERTISED_100baseT_Half |
10647                                          ADVERTISED_TP);
10648                         } else {
10649                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10650                                     link_config,
10651                                     bp->link_params.speed_cap_mask[idx]);
10652                                 return;
10653                         }
10654                         break;
10655
10656                 case PORT_FEATURE_LINK_SPEED_1G:
10657                         if (bp->port.supported[idx] &
10658                             SUPPORTED_1000baseT_Full) {
10659                                 bp->link_params.req_line_speed[idx] =
10660                                         SPEED_1000;
10661                                 bp->port.advertising[idx] |=
10662                                         (ADVERTISED_1000baseT_Full |
10663                                          ADVERTISED_TP);
10664                         } else {
10665                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10666                                     link_config,
10667                                     bp->link_params.speed_cap_mask[idx]);
10668                                 return;
10669                         }
10670                         break;
10671
10672                 case PORT_FEATURE_LINK_SPEED_2_5G:
10673                         if (bp->port.supported[idx] &
10674                             SUPPORTED_2500baseX_Full) {
10675                                 bp->link_params.req_line_speed[idx] =
10676                                         SPEED_2500;
10677                                 bp->port.advertising[idx] |=
10678                                         (ADVERTISED_2500baseX_Full |
10679                                                 ADVERTISED_TP);
10680                         } else {
10681                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10682                                     link_config,
10683                                     bp->link_params.speed_cap_mask[idx]);
10684                                 return;
10685                         }
10686                         break;
10687
10688                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10689                         if (bp->port.supported[idx] &
10690                             SUPPORTED_10000baseT_Full) {
10691                                 bp->link_params.req_line_speed[idx] =
10692                                         SPEED_10000;
10693                                 bp->port.advertising[idx] |=
10694                                         (ADVERTISED_10000baseT_Full |
10695                                                 ADVERTISED_FIBRE);
10696                         } else {
10697                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10698                                     link_config,
10699                                     bp->link_params.speed_cap_mask[idx]);
10700                                 return;
10701                         }
10702                         break;
10703                 case PORT_FEATURE_LINK_SPEED_20G:
10704                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10705
10706                         break;
10707                 default:
10708                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10709                                   link_config);
10710                                 bp->link_params.req_line_speed[idx] =
10711                                                         SPEED_AUTO_NEG;
10712                                 bp->port.advertising[idx] =
10713                                                 bp->port.supported[idx];
10714                         break;
10715                 }
10716
10717                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10718                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10719                 if (bp->link_params.req_flow_ctrl[idx] ==
10720                     BNX2X_FLOW_CTRL_AUTO) {
10721                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10722                                 bp->link_params.req_flow_ctrl[idx] =
10723                                                         BNX2X_FLOW_CTRL_NONE;
10724                         else
10725                                 bnx2x_set_requested_fc(bp);
10726                 }
10727
10728                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10729                                bp->link_params.req_line_speed[idx],
10730                                bp->link_params.req_duplex[idx],
10731                                bp->link_params.req_flow_ctrl[idx],
10732                                bp->port.advertising[idx]);
10733         }
10734 }
10735
10736 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10737 {
10738         __be16 mac_hi_be = cpu_to_be16(mac_hi);
10739         __be32 mac_lo_be = cpu_to_be32(mac_lo);
10740         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10741         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10742 }
10743
10744 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10745 {
10746         int port = BP_PORT(bp);
10747         u32 config;
10748         u32 ext_phy_type, ext_phy_config, eee_mode;
10749
10750         bp->link_params.bp = bp;
10751         bp->link_params.port = port;
10752
10753         bp->link_params.lane_config =
10754                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10755
10756         bp->link_params.speed_cap_mask[0] =
10757                 SHMEM_RD(bp,
10758                          dev_info.port_hw_config[port].speed_capability_mask) &
10759                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10760         bp->link_params.speed_cap_mask[1] =
10761                 SHMEM_RD(bp,
10762                          dev_info.port_hw_config[port].speed_capability_mask2) &
10763                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10764         bp->port.link_config[0] =
10765                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10766
10767         bp->port.link_config[1] =
10768                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10769
10770         bp->link_params.multi_phy_config =
10771                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10772         /* If the device is capable of WoL, set the default state according
10773          * to the HW
10774          */
10775         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10776         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10777                    (config & PORT_FEATURE_WOL_ENABLED));
10778
10779         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10780             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10781                 bp->flags |= NO_ISCSI_FLAG;
10782         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10783             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10784                 bp->flags |= NO_FCOE_FLAG;
10785
10786         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10787                        bp->link_params.lane_config,
10788                        bp->link_params.speed_cap_mask[0],
10789                        bp->port.link_config[0]);
10790
10791         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10792                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10793         bnx2x_phy_probe(&bp->link_params);
10794         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10795
10796         bnx2x_link_settings_requested(bp);
10797
10798         /*
10799          * If connected directly, work with the internal PHY, otherwise, work
10800          * with the external PHY
10801          */
10802         ext_phy_config =
10803                 SHMEM_RD(bp,
10804                          dev_info.port_hw_config[port].external_phy_config);
10805         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10806         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10807                 bp->mdio.prtad = bp->port.phy_addr;
10808
10809         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10810                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10811                 bp->mdio.prtad =
10812                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10813
10814         /* Configure link feature according to nvram value */
10815         eee_mode = (((SHMEM_RD(bp, dev_info.
10816                       port_feature_config[port].eee_power_mode)) &
10817                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10818                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10819         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10820                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10821                                            EEE_MODE_ENABLE_LPI |
10822                                            EEE_MODE_OUTPUT_TIME;
10823         } else {
10824                 bp->link_params.eee_mode = 0;
10825         }
10826 }
10827
10828 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10829 {
10830         u32 no_flags = NO_ISCSI_FLAG;
10831         int port = BP_PORT(bp);
10832         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10833                                 drv_lic_key[port].max_iscsi_conn);
10834
10835         if (!CNIC_SUPPORT(bp)) {
10836                 bp->flags |= no_flags;
10837                 return;
10838         }
10839
10840         /* Get the number of maximum allowed iSCSI connections */
10841         bp->cnic_eth_dev.max_iscsi_conn =
10842                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10843                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10844
10845         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10846                        bp->cnic_eth_dev.max_iscsi_conn);
10847
10848         /*
10849          * If maximum allowed number of connections is zero -
10850          * disable the feature.
10851          */
10852         if (!bp->cnic_eth_dev.max_iscsi_conn)
10853                 bp->flags |= no_flags;
10854 }
10855
10856 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10857 {
10858         /* Port info */
10859         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10860                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10861         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10862                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10863
10864         /* Node info */
10865         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10866                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10867         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10868                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10869 }
10870
10871 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
10872 {
10873         u8 count = 0;
10874
10875         if (IS_MF(bp)) {
10876                 u8 fid;
10877
10878                 /* iterate over absolute function ids for this path: */
10879                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
10880                         if (IS_MF_SD(bp)) {
10881                                 u32 cfg = MF_CFG_RD(bp,
10882                                                     func_mf_config[fid].config);
10883
10884                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
10885                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
10886                                             FUNC_MF_CFG_PROTOCOL_FCOE))
10887                                         count++;
10888                         } else {
10889                                 u32 cfg = MF_CFG_RD(bp,
10890                                                     func_ext_config[fid].
10891                                                                       func_cfg);
10892
10893                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
10894                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
10895                                         count++;
10896                         }
10897                 }
10898         } else { /* SF */
10899                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
10900
10901                 for (port = 0; port < port_cnt; port++) {
10902                         u32 lic = SHMEM_RD(bp,
10903                                            drv_lic_key[port].max_fcoe_conn) ^
10904                                   FW_ENCODE_32BIT_PATTERN;
10905                         if (lic)
10906                                 count++;
10907                 }
10908         }
10909
10910         return count;
10911 }
10912
10913 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10914 {
10915         int port = BP_PORT(bp);
10916         int func = BP_ABS_FUNC(bp);
10917         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10918                                 drv_lic_key[port].max_fcoe_conn);
10919         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
10920
10921         if (!CNIC_SUPPORT(bp)) {
10922                 bp->flags |= NO_FCOE_FLAG;
10923                 return;
10924         }
10925
10926         /* Get the number of maximum allowed FCoE connections */
10927         bp->cnic_eth_dev.max_fcoe_conn =
10928                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10929                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10930
10931         /* Calculate the number of maximum allowed FCoE tasks */
10932         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
10933
10934         /* check if FCoE resources must be shared between different functions */
10935         if (num_fcoe_func)
10936                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
10937
10938         /* Read the WWN: */
10939         if (!IS_MF(bp)) {
10940                 /* Port info */
10941                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10942                         SHMEM_RD(bp,
10943                                  dev_info.port_hw_config[port].
10944                                  fcoe_wwn_port_name_upper);
10945                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10946                         SHMEM_RD(bp,
10947                                  dev_info.port_hw_config[port].
10948                                  fcoe_wwn_port_name_lower);
10949
10950                 /* Node info */
10951                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10952                         SHMEM_RD(bp,
10953                                  dev_info.port_hw_config[port].
10954                                  fcoe_wwn_node_name_upper);
10955                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10956                         SHMEM_RD(bp,
10957                                  dev_info.port_hw_config[port].
10958                                  fcoe_wwn_node_name_lower);
10959         } else if (!IS_MF_SD(bp)) {
10960                 /*
10961                  * Read the WWN info only if the FCoE feature is enabled for
10962                  * this function.
10963                  */
10964                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10965                         bnx2x_get_ext_wwn_info(bp, func);
10966
10967         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10968                 bnx2x_get_ext_wwn_info(bp, func);
10969         }
10970
10971         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10972
10973         /*
10974          * If maximum allowed number of connections is zero -
10975          * disable the feature.
10976          */
10977         if (!bp->cnic_eth_dev.max_fcoe_conn)
10978                 bp->flags |= NO_FCOE_FLAG;
10979 }
10980
10981 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10982 {
10983         /*
10984          * iSCSI may be dynamically disabled but reading
10985          * info here we will decrease memory usage by driver
10986          * if the feature is disabled for good
10987          */
10988         bnx2x_get_iscsi_info(bp);
10989         bnx2x_get_fcoe_info(bp);
10990 }
10991
10992 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10993 {
10994         u32 val, val2;
10995         int func = BP_ABS_FUNC(bp);
10996         int port = BP_PORT(bp);
10997         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10998         u8 *fip_mac = bp->fip_mac;
10999
11000         if (IS_MF(bp)) {
11001                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11002                  * FCoE MAC then the appropriate feature should be disabled.
11003                  * In non SD mode features configuration comes from struct
11004                  * func_ext_config.
11005                  */
11006                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11007                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11008                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11009                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11010                                                  iscsi_mac_addr_upper);
11011                                 val = MF_CFG_RD(bp, func_ext_config[func].
11012                                                 iscsi_mac_addr_lower);
11013                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11014                                 BNX2X_DEV_INFO
11015                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11016                         } else {
11017                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11018                         }
11019
11020                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11021                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11022                                                  fcoe_mac_addr_upper);
11023                                 val = MF_CFG_RD(bp, func_ext_config[func].
11024                                                 fcoe_mac_addr_lower);
11025                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11026                                 BNX2X_DEV_INFO
11027                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11028                         } else {
11029                                 bp->flags |= NO_FCOE_FLAG;
11030                         }
11031
11032                         bp->mf_ext_config = cfg;
11033
11034                 } else { /* SD MODE */
11035                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11036                                 /* use primary mac as iscsi mac */
11037                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11038
11039                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11040                                 BNX2X_DEV_INFO
11041                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11042                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11043                                 /* use primary mac as fip mac */
11044                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11045                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11046                                 BNX2X_DEV_INFO
11047                                         ("Read FIP MAC: %pM\n", fip_mac);
11048                         }
11049                 }
11050
11051                 /* If this is a storage-only interface, use SAN mac as
11052                  * primary MAC. Notice that for SD this is already the case,
11053                  * as the SAN mac was copied from the primary MAC.
11054                  */
11055                 if (IS_MF_FCOE_AFEX(bp))
11056                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11057         } else {
11058                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11059                                 iscsi_mac_upper);
11060                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11061                                iscsi_mac_lower);
11062                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11063
11064                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11065                                 fcoe_fip_mac_upper);
11066                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11067                                fcoe_fip_mac_lower);
11068                 bnx2x_set_mac_buf(fip_mac, val, val2);
11069         }
11070
11071         /* Disable iSCSI OOO if MAC configuration is invalid. */
11072         if (!is_valid_ether_addr(iscsi_mac)) {
11073                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11074                 memset(iscsi_mac, 0, ETH_ALEN);
11075         }
11076
11077         /* Disable FCoE if MAC configuration is invalid. */
11078         if (!is_valid_ether_addr(fip_mac)) {
11079                 bp->flags |= NO_FCOE_FLAG;
11080                 memset(bp->fip_mac, 0, ETH_ALEN);
11081         }
11082 }
11083
11084 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11085 {
11086         u32 val, val2;
11087         int func = BP_ABS_FUNC(bp);
11088         int port = BP_PORT(bp);
11089
11090         /* Zero primary MAC configuration */
11091         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11092
11093         if (BP_NOMCP(bp)) {
11094                 BNX2X_ERROR("warning: random MAC workaround active\n");
11095                 eth_hw_addr_random(bp->dev);
11096         } else if (IS_MF(bp)) {
11097                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11098                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11099                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11100                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11101                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11102
11103                 if (CNIC_SUPPORT(bp))
11104                         bnx2x_get_cnic_mac_hwinfo(bp);
11105         } else {
11106                 /* in SF read MACs from port configuration */
11107                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11108                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11109                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11110
11111                 if (CNIC_SUPPORT(bp))
11112                         bnx2x_get_cnic_mac_hwinfo(bp);
11113         }
11114
11115         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11116
11117         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11118                 dev_err(&bp->pdev->dev,
11119                         "bad Ethernet MAC address configuration: %pM\n"
11120                         "change it manually before bringing up the appropriate network interface\n",
11121                         bp->dev->dev_addr);
11122 }
11123
11124 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11125 {
11126         int tmp;
11127         u32 cfg;
11128
11129         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11130                 /* Take function: tmp = func */
11131                 tmp = BP_ABS_FUNC(bp);
11132                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11133                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11134         } else {
11135                 /* Take port: tmp = port */
11136                 tmp = BP_PORT(bp);
11137                 cfg = SHMEM_RD(bp,
11138                                dev_info.port_hw_config[tmp].generic_features);
11139                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11140         }
11141         return cfg;
11142 }
11143
11144 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11145 {
11146         int /*abs*/func = BP_ABS_FUNC(bp);
11147         int vn;
11148         u32 val = 0;
11149         int rc = 0;
11150
11151         bnx2x_get_common_hwinfo(bp);
11152
11153         /*
11154          * initialize IGU parameters
11155          */
11156         if (CHIP_IS_E1x(bp)) {
11157                 bp->common.int_block = INT_BLOCK_HC;
11158
11159                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11160                 bp->igu_base_sb = 0;
11161         } else {
11162                 bp->common.int_block = INT_BLOCK_IGU;
11163
11164                 /* do not allow device reset during IGU info processing */
11165                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11166
11167                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11168
11169                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11170                         int tout = 5000;
11171
11172                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11173
11174                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11175                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11176                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11177
11178                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11179                                 tout--;
11180                                 usleep_range(1000, 2000);
11181                         }
11182
11183                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11184                                 dev_err(&bp->pdev->dev,
11185                                         "FORCING Normal Mode failed!!!\n");
11186                                 bnx2x_release_hw_lock(bp,
11187                                                       HW_LOCK_RESOURCE_RESET);
11188                                 return -EPERM;
11189                         }
11190                 }
11191
11192                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11193                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11194                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11195                 } else
11196                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11197
11198                 rc = bnx2x_get_igu_cam_info(bp);
11199                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11200                 if (rc)
11201                         return rc;
11202         }
11203
11204         /*
11205          * set base FW non-default (fast path) status block id, this value is
11206          * used to initialize the fw_sb_id saved on the fp/queue structure to
11207          * determine the id used by the FW.
11208          */
11209         if (CHIP_IS_E1x(bp))
11210                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11211         else /*
11212               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11213               * the same queue are indicated on the same IGU SB). So we prefer
11214               * FW and IGU SBs to be the same value.
11215               */
11216                 bp->base_fw_ndsb = bp->igu_base_sb;
11217
11218         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11219                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11220                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11221
11222         /*
11223          * Initialize MF configuration
11224          */
11225
11226         bp->mf_ov = 0;
11227         bp->mf_mode = 0;
11228         vn = BP_VN(bp);
11229
11230         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11231                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11232                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11233                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11234
11235                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11236                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11237                 else
11238                         bp->common.mf_cfg_base = bp->common.shmem_base +
11239                                 offsetof(struct shmem_region, func_mb) +
11240                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11241                 /*
11242                  * get mf configuration:
11243                  * 1. Existence of MF configuration
11244                  * 2. MAC address must be legal (check only upper bytes)
11245                  *    for  Switch-Independent mode;
11246                  *    OVLAN must be legal for Switch-Dependent mode
11247                  * 3. SF_MODE configures specific MF mode
11248                  */
11249                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11250                         /* get mf configuration */
11251                         val = SHMEM_RD(bp,
11252                                        dev_info.shared_feature_config.config);
11253                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11254
11255                         switch (val) {
11256                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11257                                 val = MF_CFG_RD(bp, func_mf_config[func].
11258                                                 mac_upper);
11259                                 /* check for legal mac (upper bytes)*/
11260                                 if (val != 0xffff) {
11261                                         bp->mf_mode = MULTI_FUNCTION_SI;
11262                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11263                                                    func_mf_config[func].config);
11264                                 } else
11265                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11266                                 break;
11267                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11268                                 if ((!CHIP_IS_E1x(bp)) &&
11269                                     (MF_CFG_RD(bp, func_mf_config[func].
11270                                                mac_upper) != 0xffff) &&
11271                                     (SHMEM2_HAS(bp,
11272                                                 afex_driver_support))) {
11273                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11274                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11275                                                 func_mf_config[func].config);
11276                                 } else {
11277                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11278                                 }
11279                                 break;
11280                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11281                                 /* get OV configuration */
11282                                 val = MF_CFG_RD(bp,
11283                                         func_mf_config[FUNC_0].e1hov_tag);
11284                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11285
11286                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11287                                         bp->mf_mode = MULTI_FUNCTION_SD;
11288                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11289                                                 func_mf_config[func].config);
11290                                 } else
11291                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11292                                 break;
11293                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11294                                 bp->mf_config[vn] = 0;
11295                                 break;
11296                         default:
11297                                 /* Unknown configuration: reset mf_config */
11298                                 bp->mf_config[vn] = 0;
11299                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11300                         }
11301                 }
11302
11303                 BNX2X_DEV_INFO("%s function mode\n",
11304                                IS_MF(bp) ? "multi" : "single");
11305
11306                 switch (bp->mf_mode) {
11307                 case MULTI_FUNCTION_SD:
11308                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11309                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11310                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11311                                 bp->mf_ov = val;
11312                                 bp->path_has_ovlan = true;
11313
11314                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11315                                                func, bp->mf_ov, bp->mf_ov);
11316                         } else {
11317                                 dev_err(&bp->pdev->dev,
11318                                         "No valid MF OV for func %d, aborting\n",
11319                                         func);
11320                                 return -EPERM;
11321                         }
11322                         break;
11323                 case MULTI_FUNCTION_AFEX:
11324                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11325                         break;
11326                 case MULTI_FUNCTION_SI:
11327                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11328                                        func);
11329                         break;
11330                 default:
11331                         if (vn) {
11332                                 dev_err(&bp->pdev->dev,
11333                                         "VN %d is in a single function mode, aborting\n",
11334                                         vn);
11335                                 return -EPERM;
11336                         }
11337                         break;
11338                 }
11339
11340                 /* check if other port on the path needs ovlan:
11341                  * Since MF configuration is shared between ports
11342                  * Possible mixed modes are only
11343                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11344                  */
11345                 if (CHIP_MODE_IS_4_PORT(bp) &&
11346                     !bp->path_has_ovlan &&
11347                     !IS_MF(bp) &&
11348                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11349                         u8 other_port = !BP_PORT(bp);
11350                         u8 other_func = BP_PATH(bp) + 2*other_port;
11351                         val = MF_CFG_RD(bp,
11352                                         func_mf_config[other_func].e1hov_tag);
11353                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11354                                 bp->path_has_ovlan = true;
11355                 }
11356         }
11357
11358         /* adjust igu_sb_cnt to MF for E1x */
11359         if (CHIP_IS_E1x(bp) && IS_MF(bp))
11360                 bp->igu_sb_cnt /= E1HVN_MAX;
11361
11362         /* port info */
11363         bnx2x_get_port_hwinfo(bp);
11364
11365         /* Get MAC addresses */
11366         bnx2x_get_mac_hwinfo(bp);
11367
11368         bnx2x_get_cnic_info(bp);
11369
11370         return rc;
11371 }
11372
11373 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11374 {
11375         int cnt, i, block_end, rodi;
11376         char vpd_start[BNX2X_VPD_LEN+1];
11377         char str_id_reg[VENDOR_ID_LEN+1];
11378         char str_id_cap[VENDOR_ID_LEN+1];
11379         char *vpd_data;
11380         char *vpd_extended_data = NULL;
11381         u8 len;
11382
11383         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11384         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11385
11386         if (cnt < BNX2X_VPD_LEN)
11387                 goto out_not_found;
11388
11389         /* VPD RO tag should be first tag after identifier string, hence
11390          * we should be able to find it in first BNX2X_VPD_LEN chars
11391          */
11392         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11393                              PCI_VPD_LRDT_RO_DATA);
11394         if (i < 0)
11395                 goto out_not_found;
11396
11397         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11398                     pci_vpd_lrdt_size(&vpd_start[i]);
11399
11400         i += PCI_VPD_LRDT_TAG_SIZE;
11401
11402         if (block_end > BNX2X_VPD_LEN) {
11403                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11404                 if (vpd_extended_data  == NULL)
11405                         goto out_not_found;
11406
11407                 /* read rest of vpd image into vpd_extended_data */
11408                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11409                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11410                                    block_end - BNX2X_VPD_LEN,
11411                                    vpd_extended_data + BNX2X_VPD_LEN);
11412                 if (cnt < (block_end - BNX2X_VPD_LEN))
11413                         goto out_not_found;
11414                 vpd_data = vpd_extended_data;
11415         } else
11416                 vpd_data = vpd_start;
11417
11418         /* now vpd_data holds full vpd content in both cases */
11419
11420         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11421                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11422         if (rodi < 0)
11423                 goto out_not_found;
11424
11425         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11426
11427         if (len != VENDOR_ID_LEN)
11428                 goto out_not_found;
11429
11430         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11431
11432         /* vendor specific info */
11433         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11434         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11435         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11436             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11437
11438                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11439                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11440                 if (rodi >= 0) {
11441                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11442
11443                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11444
11445                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11446                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11447                                 bp->fw_ver[len] = ' ';
11448                         }
11449                 }
11450                 kfree(vpd_extended_data);
11451                 return;
11452         }
11453 out_not_found:
11454         kfree(vpd_extended_data);
11455         return;
11456 }
11457
11458 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11459 {
11460         u32 flags = 0;
11461
11462         if (CHIP_REV_IS_FPGA(bp))
11463                 SET_FLAGS(flags, MODE_FPGA);
11464         else if (CHIP_REV_IS_EMUL(bp))
11465                 SET_FLAGS(flags, MODE_EMUL);
11466         else
11467                 SET_FLAGS(flags, MODE_ASIC);
11468
11469         if (CHIP_MODE_IS_4_PORT(bp))
11470                 SET_FLAGS(flags, MODE_PORT4);
11471         else
11472                 SET_FLAGS(flags, MODE_PORT2);
11473
11474         if (CHIP_IS_E2(bp))
11475                 SET_FLAGS(flags, MODE_E2);
11476         else if (CHIP_IS_E3(bp)) {
11477                 SET_FLAGS(flags, MODE_E3);
11478                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11479                         SET_FLAGS(flags, MODE_E3_A0);
11480                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11481                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11482         }
11483
11484         if (IS_MF(bp)) {
11485                 SET_FLAGS(flags, MODE_MF);
11486                 switch (bp->mf_mode) {
11487                 case MULTI_FUNCTION_SD:
11488                         SET_FLAGS(flags, MODE_MF_SD);
11489                         break;
11490                 case MULTI_FUNCTION_SI:
11491                         SET_FLAGS(flags, MODE_MF_SI);
11492                         break;
11493                 case MULTI_FUNCTION_AFEX:
11494                         SET_FLAGS(flags, MODE_MF_AFEX);
11495                         break;
11496                 }
11497         } else
11498                 SET_FLAGS(flags, MODE_SF);
11499
11500 #if defined(__LITTLE_ENDIAN)
11501         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11502 #else /*(__BIG_ENDIAN)*/
11503         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11504 #endif
11505         INIT_MODE_FLAGS(bp) = flags;
11506 }
11507
11508 static int bnx2x_init_bp(struct bnx2x *bp)
11509 {
11510         int func;
11511         int rc;
11512
11513         mutex_init(&bp->port.phy_mutex);
11514         mutex_init(&bp->fw_mb_mutex);
11515         spin_lock_init(&bp->stats_lock);
11516
11517         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11518         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11519         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11520         if (IS_PF(bp)) {
11521                 rc = bnx2x_get_hwinfo(bp);
11522                 if (rc)
11523                         return rc;
11524         } else {
11525                 eth_zero_addr(bp->dev->dev_addr);
11526         }
11527
11528         bnx2x_set_modes_bitmap(bp);
11529
11530         rc = bnx2x_alloc_mem_bp(bp);
11531         if (rc)
11532                 return rc;
11533
11534         bnx2x_read_fwinfo(bp);
11535
11536         func = BP_FUNC(bp);
11537
11538         /* need to reset chip if undi was active */
11539         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11540                 /* init fw_seq */
11541                 bp->fw_seq =
11542                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11543                                                         DRV_MSG_SEQ_NUMBER_MASK;
11544                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11545
11546                 bnx2x_prev_unload(bp);
11547         }
11548
11549         if (CHIP_REV_IS_FPGA(bp))
11550                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11551
11552         if (BP_NOMCP(bp) && (func == 0))
11553                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11554
11555         bp->disable_tpa = disable_tpa;
11556         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11557
11558         /* Set TPA flags */
11559         if (bp->disable_tpa) {
11560                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11561                 bp->dev->features &= ~NETIF_F_LRO;
11562         } else {
11563                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11564                 bp->dev->features |= NETIF_F_LRO;
11565         }
11566
11567         if (CHIP_IS_E1(bp))
11568                 bp->dropless_fc = 0;
11569         else
11570                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11571
11572         bp->mrrs = mrrs;
11573
11574         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11575         if (IS_VF(bp))
11576                 bp->rx_ring_size = MAX_RX_AVAIL;
11577
11578         /* make sure that the numbers are in the right granularity */
11579         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11580         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11581
11582         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11583
11584         init_timer(&bp->timer);
11585         bp->timer.expires = jiffies + bp->current_interval;
11586         bp->timer.data = (unsigned long) bp;
11587         bp->timer.function = bnx2x_timer;
11588
11589         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11590             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11591             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11592             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11593                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11594                 bnx2x_dcbx_init_params(bp);
11595         } else {
11596                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11597         }
11598
11599         if (CHIP_IS_E1x(bp))
11600                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11601         else
11602                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11603
11604         /* multiple tx priority */
11605         if (IS_VF(bp))
11606                 bp->max_cos = 1;
11607         else if (CHIP_IS_E1x(bp))
11608                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11609         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11610                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11611         else if (CHIP_IS_E3B0(bp))
11612                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11613         else
11614                 BNX2X_ERR("unknown chip %x revision %x\n",
11615                           CHIP_NUM(bp), CHIP_REV(bp));
11616         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11617
11618         /* We need at least one default status block for slow-path events,
11619          * second status block for the L2 queue, and a third status block for
11620          * CNIC if supported.
11621          */
11622         if (CNIC_SUPPORT(bp))
11623                 bp->min_msix_vec_cnt = 3;
11624         else
11625                 bp->min_msix_vec_cnt = 2;
11626         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11627
11628         return rc;
11629 }
11630
11631 /****************************************************************************
11632 * General service functions
11633 ****************************************************************************/
11634
11635 /*
11636  * net_device service functions
11637  */
11638
11639 /* called with rtnl_lock */
11640 static int bnx2x_open(struct net_device *dev)
11641 {
11642         struct bnx2x *bp = netdev_priv(dev);
11643         bool global = false;
11644         int other_engine = BP_PATH(bp) ? 0 : 1;
11645         bool other_load_status, load_status;
11646         int rc;
11647
11648         bp->stats_init = true;
11649
11650         netif_carrier_off(dev);
11651
11652         bnx2x_set_power_state(bp, PCI_D0);
11653
11654         /* If parity had happen during the unload, then attentions
11655          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11656          * want the first function loaded on the current engine to
11657          * complete the recovery.
11658          * Parity recovery is only relevant for PF driver.
11659          */
11660         if (IS_PF(bp)) {
11661                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11662                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11663                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11664                     bnx2x_chk_parity_attn(bp, &global, true)) {
11665                         do {
11666                                 /* If there are attentions and they are in a
11667                                  * global blocks, set the GLOBAL_RESET bit
11668                                  * regardless whether it will be this function
11669                                  * that will complete the recovery or not.
11670                                  */
11671                                 if (global)
11672                                         bnx2x_set_reset_global(bp);
11673
11674                                 /* Only the first function on the current
11675                                  * engine should try to recover in open. In case
11676                                  * of attentions in global blocks only the first
11677                                  * in the chip should try to recover.
11678                                  */
11679                                 if ((!load_status &&
11680                                      (!global || !other_load_status)) &&
11681                                       bnx2x_trylock_leader_lock(bp) &&
11682                                       !bnx2x_leader_reset(bp)) {
11683                                         netdev_info(bp->dev,
11684                                                     "Recovered in open\n");
11685                                         break;
11686                                 }
11687
11688                                 /* recovery has failed... */
11689                                 bnx2x_set_power_state(bp, PCI_D3hot);
11690                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11691
11692                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11693                                           "If you still see this message after a few retries then power cycle is required.\n");
11694
11695                                 return -EAGAIN;
11696                         } while (0);
11697                 }
11698         }
11699
11700         bp->recovery_state = BNX2X_RECOVERY_DONE;
11701         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11702         if (rc)
11703                 return rc;
11704         return bnx2x_open_epilog(bp);
11705 }
11706
11707 /* called with rtnl_lock */
11708 static int bnx2x_close(struct net_device *dev)
11709 {
11710         struct bnx2x *bp = netdev_priv(dev);
11711
11712         /* Unload the driver, release IRQs */
11713         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11714
11715         return 0;
11716 }
11717
11718 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11719                                       struct bnx2x_mcast_ramrod_params *p)
11720 {
11721         int mc_count = netdev_mc_count(bp->dev);
11722         struct bnx2x_mcast_list_elem *mc_mac =
11723                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11724         struct netdev_hw_addr *ha;
11725
11726         if (!mc_mac)
11727                 return -ENOMEM;
11728
11729         INIT_LIST_HEAD(&p->mcast_list);
11730
11731         netdev_for_each_mc_addr(ha, bp->dev) {
11732                 mc_mac->mac = bnx2x_mc_addr(ha);
11733                 list_add_tail(&mc_mac->link, &p->mcast_list);
11734                 mc_mac++;
11735         }
11736
11737         p->mcast_list_len = mc_count;
11738
11739         return 0;
11740 }
11741
11742 static void bnx2x_free_mcast_macs_list(
11743         struct bnx2x_mcast_ramrod_params *p)
11744 {
11745         struct bnx2x_mcast_list_elem *mc_mac =
11746                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11747                                  link);
11748
11749         WARN_ON(!mc_mac);
11750         kfree(mc_mac);
11751 }
11752
11753 /**
11754  * bnx2x_set_uc_list - configure a new unicast MACs list.
11755  *
11756  * @bp: driver handle
11757  *
11758  * We will use zero (0) as a MAC type for these MACs.
11759  */
11760 static int bnx2x_set_uc_list(struct bnx2x *bp)
11761 {
11762         int rc;
11763         struct net_device *dev = bp->dev;
11764         struct netdev_hw_addr *ha;
11765         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11766         unsigned long ramrod_flags = 0;
11767
11768         /* First schedule a cleanup up of old configuration */
11769         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11770         if (rc < 0) {
11771                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11772                 return rc;
11773         }
11774
11775         netdev_for_each_uc_addr(ha, dev) {
11776                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11777                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11778                 if (rc == -EEXIST) {
11779                         DP(BNX2X_MSG_SP,
11780                            "Failed to schedule ADD operations: %d\n", rc);
11781                         /* do not treat adding same MAC as error */
11782                         rc = 0;
11783
11784                 } else if (rc < 0) {
11785
11786                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11787                                   rc);
11788                         return rc;
11789                 }
11790         }
11791
11792         /* Execute the pending commands */
11793         __set_bit(RAMROD_CONT, &ramrod_flags);
11794         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11795                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11796 }
11797
11798 static int bnx2x_set_mc_list(struct bnx2x *bp)
11799 {
11800         struct net_device *dev = bp->dev;
11801         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11802         int rc = 0;
11803
11804         rparam.mcast_obj = &bp->mcast_obj;
11805
11806         /* first, clear all configured multicast MACs */
11807         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11808         if (rc < 0) {
11809                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11810                 return rc;
11811         }
11812
11813         /* then, configure a new MACs list */
11814         if (netdev_mc_count(dev)) {
11815                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11816                 if (rc) {
11817                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11818                                   rc);
11819                         return rc;
11820                 }
11821
11822                 /* Now add the new MACs */
11823                 rc = bnx2x_config_mcast(bp, &rparam,
11824                                         BNX2X_MCAST_CMD_ADD);
11825                 if (rc < 0)
11826                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11827                                   rc);
11828
11829                 bnx2x_free_mcast_macs_list(&rparam);
11830         }
11831
11832         return rc;
11833 }
11834
11835 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11836 void bnx2x_set_rx_mode(struct net_device *dev)
11837 {
11838         struct bnx2x *bp = netdev_priv(dev);
11839         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11840
11841         if (bp->state != BNX2X_STATE_OPEN) {
11842                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11843                 return;
11844         }
11845
11846         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11847
11848         if (dev->flags & IFF_PROMISC)
11849                 rx_mode = BNX2X_RX_MODE_PROMISC;
11850         else if ((dev->flags & IFF_ALLMULTI) ||
11851                  ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11852                   CHIP_IS_E1(bp)))
11853                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11854         else {
11855                 if (IS_PF(bp)) {
11856                         /* some multicasts */
11857                         if (bnx2x_set_mc_list(bp) < 0)
11858                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11859
11860                         if (bnx2x_set_uc_list(bp) < 0)
11861                                 rx_mode = BNX2X_RX_MODE_PROMISC;
11862                 } else {
11863                         /* configuring mcast to a vf involves sleeping (when we
11864                          * wait for the pf's response). Since this function is
11865                          * called from non sleepable context we must schedule
11866                          * a work item for this purpose
11867                          */
11868                         smp_mb__before_clear_bit();
11869                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11870                                 &bp->sp_rtnl_state);
11871                         smp_mb__after_clear_bit();
11872                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11873                 }
11874         }
11875
11876         bp->rx_mode = rx_mode;
11877         /* handle ISCSI SD mode */
11878         if (IS_MF_ISCSI_SD(bp))
11879                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11880
11881         /* Schedule the rx_mode command */
11882         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11883                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11884                 return;
11885         }
11886
11887         if (IS_PF(bp)) {
11888                 bnx2x_set_storm_rx_mode(bp);
11889         } else {
11890                 /* configuring rx mode to storms in a vf involves sleeping (when
11891                  * we wait for the pf's response). Since this function is
11892                  * called from non sleepable context we must schedule
11893                  * a work item for this purpose
11894                  */
11895                 smp_mb__before_clear_bit();
11896                 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11897                         &bp->sp_rtnl_state);
11898                 smp_mb__after_clear_bit();
11899                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11900         }
11901 }
11902
11903 /* called with rtnl_lock */
11904 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11905                            int devad, u16 addr)
11906 {
11907         struct bnx2x *bp = netdev_priv(netdev);
11908         u16 value;
11909         int rc;
11910
11911         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11912            prtad, devad, addr);
11913
11914         /* The HW expects different devad if CL22 is used */
11915         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11916
11917         bnx2x_acquire_phy_lock(bp);
11918         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11919         bnx2x_release_phy_lock(bp);
11920         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11921
11922         if (!rc)
11923                 rc = value;
11924         return rc;
11925 }
11926
11927 /* called with rtnl_lock */
11928 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11929                             u16 addr, u16 value)
11930 {
11931         struct bnx2x *bp = netdev_priv(netdev);
11932         int rc;
11933
11934         DP(NETIF_MSG_LINK,
11935            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11936            prtad, devad, addr, value);
11937
11938         /* The HW expects different devad if CL22 is used */
11939         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11940
11941         bnx2x_acquire_phy_lock(bp);
11942         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11943         bnx2x_release_phy_lock(bp);
11944         return rc;
11945 }
11946
11947 /* called with rtnl_lock */
11948 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11949 {
11950         struct bnx2x *bp = netdev_priv(dev);
11951         struct mii_ioctl_data *mdio = if_mii(ifr);
11952
11953         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11954            mdio->phy_id, mdio->reg_num, mdio->val_in);
11955
11956         if (!netif_running(dev))
11957                 return -EAGAIN;
11958
11959         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11960 }
11961
11962 #ifdef CONFIG_NET_POLL_CONTROLLER
11963 static void poll_bnx2x(struct net_device *dev)
11964 {
11965         struct bnx2x *bp = netdev_priv(dev);
11966         int i;
11967
11968         for_each_eth_queue(bp, i) {
11969                 struct bnx2x_fastpath *fp = &bp->fp[i];
11970                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11971         }
11972 }
11973 #endif
11974
11975 static int bnx2x_validate_addr(struct net_device *dev)
11976 {
11977         struct bnx2x *bp = netdev_priv(dev);
11978
11979         /* query the bulletin board for mac address configured by the PF */
11980         if (IS_VF(bp))
11981                 bnx2x_sample_bulletin(bp);
11982
11983         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11984                 BNX2X_ERR("Non-valid Ethernet address\n");
11985                 return -EADDRNOTAVAIL;
11986         }
11987         return 0;
11988 }
11989
11990 static const struct net_device_ops bnx2x_netdev_ops = {
11991         .ndo_open               = bnx2x_open,
11992         .ndo_stop               = bnx2x_close,
11993         .ndo_start_xmit         = bnx2x_start_xmit,
11994         .ndo_select_queue       = bnx2x_select_queue,
11995         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
11996         .ndo_set_mac_address    = bnx2x_change_mac_addr,
11997         .ndo_validate_addr      = bnx2x_validate_addr,
11998         .ndo_do_ioctl           = bnx2x_ioctl,
11999         .ndo_change_mtu         = bnx2x_change_mtu,
12000         .ndo_fix_features       = bnx2x_fix_features,
12001         .ndo_set_features       = bnx2x_set_features,
12002         .ndo_tx_timeout         = bnx2x_tx_timeout,
12003 #ifdef CONFIG_NET_POLL_CONTROLLER
12004         .ndo_poll_controller    = poll_bnx2x,
12005 #endif
12006         .ndo_setup_tc           = bnx2x_setup_tc,
12007 #ifdef CONFIG_BNX2X_SRIOV
12008         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12009         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12010         .ndo_get_vf_config      = bnx2x_get_vf_config,
12011 #endif
12012 #ifdef NETDEV_FCOE_WWNN
12013         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12014 #endif
12015
12016 #ifdef CONFIG_NET_LL_RX_POLL
12017         .ndo_ll_poll            = bnx2x_low_latency_recv,
12018 #endif
12019 };
12020
12021 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12022 {
12023         struct device *dev = &bp->pdev->dev;
12024
12025         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
12026                 bp->flags |= USING_DAC_FLAG;
12027                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
12028                         dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
12029                         return -EIO;
12030                 }
12031         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
12032                 dev_err(dev, "System does not support DMA, aborting\n");
12033                 return -EIO;
12034         }
12035
12036         return 0;
12037 }
12038
12039 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12040                           struct net_device *dev, unsigned long board_type)
12041 {
12042         int rc;
12043         u32 pci_cfg_dword;
12044         bool chip_is_e1x = (board_type == BCM57710 ||
12045                             board_type == BCM57711 ||
12046                             board_type == BCM57711E);
12047
12048         SET_NETDEV_DEV(dev, &pdev->dev);
12049
12050         bp->dev = dev;
12051         bp->pdev = pdev;
12052
12053         rc = pci_enable_device(pdev);
12054         if (rc) {
12055                 dev_err(&bp->pdev->dev,
12056                         "Cannot enable PCI device, aborting\n");
12057                 goto err_out;
12058         }
12059
12060         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12061                 dev_err(&bp->pdev->dev,
12062                         "Cannot find PCI device base address, aborting\n");
12063                 rc = -ENODEV;
12064                 goto err_out_disable;
12065         }
12066
12067         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12068                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12069                 rc = -ENODEV;
12070                 goto err_out_disable;
12071         }
12072
12073         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12074         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12075             PCICFG_REVESION_ID_ERROR_VAL) {
12076                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12077                 rc = -ENODEV;
12078                 goto err_out_disable;
12079         }
12080
12081         if (atomic_read(&pdev->enable_cnt) == 1) {
12082                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12083                 if (rc) {
12084                         dev_err(&bp->pdev->dev,
12085                                 "Cannot obtain PCI resources, aborting\n");
12086                         goto err_out_disable;
12087                 }
12088
12089                 pci_set_master(pdev);
12090                 pci_save_state(pdev);
12091         }
12092
12093         if (IS_PF(bp)) {
12094                 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
12095                 if (bp->pm_cap == 0) {
12096                         dev_err(&bp->pdev->dev,
12097                                 "Cannot find power management capability, aborting\n");
12098                         rc = -EIO;
12099                         goto err_out_release;
12100                 }
12101         }
12102
12103         if (!pci_is_pcie(pdev)) {
12104                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12105                 rc = -EIO;
12106                 goto err_out_release;
12107         }
12108
12109         rc = bnx2x_set_coherency_mask(bp);
12110         if (rc)
12111                 goto err_out_release;
12112
12113         dev->mem_start = pci_resource_start(pdev, 0);
12114         dev->base_addr = dev->mem_start;
12115         dev->mem_end = pci_resource_end(pdev, 0);
12116
12117         dev->irq = pdev->irq;
12118
12119         bp->regview = pci_ioremap_bar(pdev, 0);
12120         if (!bp->regview) {
12121                 dev_err(&bp->pdev->dev,
12122                         "Cannot map register space, aborting\n");
12123                 rc = -ENOMEM;
12124                 goto err_out_release;
12125         }
12126
12127         /* In E1/E1H use pci device function given by kernel.
12128          * In E2/E3 read physical function from ME register since these chips
12129          * support Physical Device Assignment where kernel BDF maybe arbitrary
12130          * (depending on hypervisor).
12131          */
12132         if (chip_is_e1x) {
12133                 bp->pf_num = PCI_FUNC(pdev->devfn);
12134         } else {
12135                 /* chip is E2/3*/
12136                 pci_read_config_dword(bp->pdev,
12137                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12138                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12139                                   ME_REG_ABS_PF_NUM_SHIFT);
12140         }
12141         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12142
12143         bnx2x_set_power_state(bp, PCI_D0);
12144
12145         /* clean indirect addresses */
12146         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12147                                PCICFG_VENDOR_ID_OFFSET);
12148         /*
12149          * Clean the following indirect addresses for all functions since it
12150          * is not used by the driver.
12151          */
12152         if (IS_PF(bp)) {
12153                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12154                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12155                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12156                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12157
12158                 if (chip_is_e1x) {
12159                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12160                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12161                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12162                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12163                 }
12164
12165                 /* Enable internal target-read (in case we are probed after PF
12166                  * FLR). Must be done prior to any BAR read access. Only for
12167                  * 57712 and up
12168                  */
12169                 if (!chip_is_e1x)
12170                         REG_WR(bp,
12171                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12172         }
12173
12174         dev->watchdog_timeo = TX_TIMEOUT;
12175
12176         dev->netdev_ops = &bnx2x_netdev_ops;
12177         bnx2x_set_ethtool_ops(bp, dev);
12178
12179         dev->priv_flags |= IFF_UNICAST_FLT;
12180
12181         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12182                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12183                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12184                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12185         if (!CHIP_IS_E1x(bp)) {
12186                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12187                 dev->hw_enc_features =
12188                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12189                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12190                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12191         }
12192
12193         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12194                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12195
12196         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12197         if (bp->flags & USING_DAC_FLAG)
12198                 dev->features |= NETIF_F_HIGHDMA;
12199
12200         /* Add Loopback capability to the device */
12201         dev->hw_features |= NETIF_F_LOOPBACK;
12202
12203 #ifdef BCM_DCBNL
12204         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12205 #endif
12206
12207         /* get_port_hwinfo() will set prtad and mmds properly */
12208         bp->mdio.prtad = MDIO_PRTAD_NONE;
12209         bp->mdio.mmds = 0;
12210         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12211         bp->mdio.dev = dev;
12212         bp->mdio.mdio_read = bnx2x_mdio_read;
12213         bp->mdio.mdio_write = bnx2x_mdio_write;
12214
12215         return 0;
12216
12217 err_out_release:
12218         if (atomic_read(&pdev->enable_cnt) == 1)
12219                 pci_release_regions(pdev);
12220
12221 err_out_disable:
12222         pci_disable_device(pdev);
12223         pci_set_drvdata(pdev, NULL);
12224
12225 err_out:
12226         return rc;
12227 }
12228
12229 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width,
12230                                        enum bnx2x_pci_bus_speed *speed)
12231 {
12232         u32 link_speed, val = 0;
12233
12234         pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12235         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12236
12237         link_speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12238
12239         switch (link_speed) {
12240         case 3:
12241                 *speed = BNX2X_PCI_LINK_SPEED_8000;
12242                 break;
12243         case 2:
12244                 *speed = BNX2X_PCI_LINK_SPEED_5000;
12245                 break;
12246         default:
12247                 *speed = BNX2X_PCI_LINK_SPEED_2500;
12248         }
12249 }
12250
12251 static int bnx2x_check_firmware(struct bnx2x *bp)
12252 {
12253         const struct firmware *firmware = bp->firmware;
12254         struct bnx2x_fw_file_hdr *fw_hdr;
12255         struct bnx2x_fw_file_section *sections;
12256         u32 offset, len, num_ops;
12257         __be16 *ops_offsets;
12258         int i;
12259         const u8 *fw_ver;
12260
12261         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12262                 BNX2X_ERR("Wrong FW size\n");
12263                 return -EINVAL;
12264         }
12265
12266         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12267         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12268
12269         /* Make sure none of the offsets and sizes make us read beyond
12270          * the end of the firmware data */
12271         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12272                 offset = be32_to_cpu(sections[i].offset);
12273                 len = be32_to_cpu(sections[i].len);
12274                 if (offset + len > firmware->size) {
12275                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12276                         return -EINVAL;
12277                 }
12278         }
12279
12280         /* Likewise for the init_ops offsets */
12281         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12282         ops_offsets = (__force __be16 *)(firmware->data + offset);
12283         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12284
12285         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12286                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12287                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12288                         return -EINVAL;
12289                 }
12290         }
12291
12292         /* Check FW version */
12293         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12294         fw_ver = firmware->data + offset;
12295         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12296             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12297             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12298             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12299                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12300                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12301                        BCM_5710_FW_MAJOR_VERSION,
12302                        BCM_5710_FW_MINOR_VERSION,
12303                        BCM_5710_FW_REVISION_VERSION,
12304                        BCM_5710_FW_ENGINEERING_VERSION);
12305                 return -EINVAL;
12306         }
12307
12308         return 0;
12309 }
12310
12311 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12312 {
12313         const __be32 *source = (const __be32 *)_source;
12314         u32 *target = (u32 *)_target;
12315         u32 i;
12316
12317         for (i = 0; i < n/4; i++)
12318                 target[i] = be32_to_cpu(source[i]);
12319 }
12320
12321 /*
12322    Ops array is stored in the following format:
12323    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12324  */
12325 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12326 {
12327         const __be32 *source = (const __be32 *)_source;
12328         struct raw_op *target = (struct raw_op *)_target;
12329         u32 i, j, tmp;
12330
12331         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12332                 tmp = be32_to_cpu(source[j]);
12333                 target[i].op = (tmp >> 24) & 0xff;
12334                 target[i].offset = tmp & 0xffffff;
12335                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12336         }
12337 }
12338
12339 /* IRO array is stored in the following format:
12340  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12341  */
12342 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12343 {
12344         const __be32 *source = (const __be32 *)_source;
12345         struct iro *target = (struct iro *)_target;
12346         u32 i, j, tmp;
12347
12348         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12349                 target[i].base = be32_to_cpu(source[j]);
12350                 j++;
12351                 tmp = be32_to_cpu(source[j]);
12352                 target[i].m1 = (tmp >> 16) & 0xffff;
12353                 target[i].m2 = tmp & 0xffff;
12354                 j++;
12355                 tmp = be32_to_cpu(source[j]);
12356                 target[i].m3 = (tmp >> 16) & 0xffff;
12357                 target[i].size = tmp & 0xffff;
12358                 j++;
12359         }
12360 }
12361
12362 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12363 {
12364         const __be16 *source = (const __be16 *)_source;
12365         u16 *target = (u16 *)_target;
12366         u32 i;
12367
12368         for (i = 0; i < n/2; i++)
12369                 target[i] = be16_to_cpu(source[i]);
12370 }
12371
12372 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12373 do {                                                                    \
12374         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12375         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12376         if (!bp->arr)                                                   \
12377                 goto lbl;                                               \
12378         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12379              (u8 *)bp->arr, len);                                       \
12380 } while (0)
12381
12382 static int bnx2x_init_firmware(struct bnx2x *bp)
12383 {
12384         const char *fw_file_name;
12385         struct bnx2x_fw_file_hdr *fw_hdr;
12386         int rc;
12387
12388         if (bp->firmware)
12389                 return 0;
12390
12391         if (CHIP_IS_E1(bp))
12392                 fw_file_name = FW_FILE_NAME_E1;
12393         else if (CHIP_IS_E1H(bp))
12394                 fw_file_name = FW_FILE_NAME_E1H;
12395         else if (!CHIP_IS_E1x(bp))
12396                 fw_file_name = FW_FILE_NAME_E2;
12397         else {
12398                 BNX2X_ERR("Unsupported chip revision\n");
12399                 return -EINVAL;
12400         }
12401         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12402
12403         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12404         if (rc) {
12405                 BNX2X_ERR("Can't load firmware file %s\n",
12406                           fw_file_name);
12407                 goto request_firmware_exit;
12408         }
12409
12410         rc = bnx2x_check_firmware(bp);
12411         if (rc) {
12412                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12413                 goto request_firmware_exit;
12414         }
12415
12416         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12417
12418         /* Initialize the pointers to the init arrays */
12419         /* Blob */
12420         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12421
12422         /* Opcodes */
12423         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12424
12425         /* Offsets */
12426         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12427                             be16_to_cpu_n);
12428
12429         /* STORMs firmware */
12430         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12431                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12432         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12433                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12434         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12435                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12436         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12437                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12438         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12439                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12440         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12441                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12442         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12443                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12444         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12445                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12446         /* IRO */
12447         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12448
12449         return 0;
12450
12451 iro_alloc_err:
12452         kfree(bp->init_ops_offsets);
12453 init_offsets_alloc_err:
12454         kfree(bp->init_ops);
12455 init_ops_alloc_err:
12456         kfree(bp->init_data);
12457 request_firmware_exit:
12458         release_firmware(bp->firmware);
12459         bp->firmware = NULL;
12460
12461         return rc;
12462 }
12463
12464 static void bnx2x_release_firmware(struct bnx2x *bp)
12465 {
12466         kfree(bp->init_ops_offsets);
12467         kfree(bp->init_ops);
12468         kfree(bp->init_data);
12469         release_firmware(bp->firmware);
12470         bp->firmware = NULL;
12471 }
12472
12473 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12474         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12475         .init_hw_cmn      = bnx2x_init_hw_common,
12476         .init_hw_port     = bnx2x_init_hw_port,
12477         .init_hw_func     = bnx2x_init_hw_func,
12478
12479         .reset_hw_cmn     = bnx2x_reset_common,
12480         .reset_hw_port    = bnx2x_reset_port,
12481         .reset_hw_func    = bnx2x_reset_func,
12482
12483         .gunzip_init      = bnx2x_gunzip_init,
12484         .gunzip_end       = bnx2x_gunzip_end,
12485
12486         .init_fw          = bnx2x_init_firmware,
12487         .release_fw       = bnx2x_release_firmware,
12488 };
12489
12490 void bnx2x__init_func_obj(struct bnx2x *bp)
12491 {
12492         /* Prepare DMAE related driver resources */
12493         bnx2x_setup_dmae(bp);
12494
12495         bnx2x_init_func_obj(bp, &bp->func_obj,
12496                             bnx2x_sp(bp, func_rdata),
12497                             bnx2x_sp_mapping(bp, func_rdata),
12498                             bnx2x_sp(bp, func_afex_rdata),
12499                             bnx2x_sp_mapping(bp, func_afex_rdata),
12500                             &bnx2x_func_sp_drv);
12501 }
12502
12503 /* must be called after sriov-enable */
12504 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12505 {
12506         int cid_count = BNX2X_L2_MAX_CID(bp);
12507
12508         if (IS_SRIOV(bp))
12509                 cid_count += BNX2X_VF_CIDS;
12510
12511         if (CNIC_SUPPORT(bp))
12512                 cid_count += CNIC_CID_MAX;
12513
12514         return roundup(cid_count, QM_CID_ROUND);
12515 }
12516
12517 /**
12518  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12519  *
12520  * @dev:        pci device
12521  *
12522  */
12523 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12524                                      int cnic_cnt, bool is_vf)
12525 {
12526         int pos, index;
12527         u16 control = 0;
12528
12529         pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12530
12531         /*
12532          * If MSI-X is not supported - return number of SBs needed to support
12533          * one fast path queue: one FP queue + SB for CNIC
12534          */
12535         if (!pos) {
12536                 dev_info(&pdev->dev, "no msix capability found\n");
12537                 return 1 + cnic_cnt;
12538         }
12539         dev_info(&pdev->dev, "msix capability found\n");
12540
12541         /*
12542          * The value in the PCI configuration space is the index of the last
12543          * entry, namely one less than the actual size of the table, which is
12544          * exactly what we want to return from this function: number of all SBs
12545          * without the default SB.
12546          * For VFs there is no default SB, then we return (index+1).
12547          */
12548         pci_read_config_word(pdev, pos  + PCI_MSI_FLAGS, &control);
12549
12550         index = control & PCI_MSIX_FLAGS_QSIZE;
12551
12552         return is_vf ? index + 1 : index;
12553 }
12554
12555 static int set_max_cos_est(int chip_id)
12556 {
12557         switch (chip_id) {
12558         case BCM57710:
12559         case BCM57711:
12560         case BCM57711E:
12561                 return BNX2X_MULTI_TX_COS_E1X;
12562         case BCM57712:
12563         case BCM57712_MF:
12564         case BCM57712_VF:
12565                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12566         case BCM57800:
12567         case BCM57800_MF:
12568         case BCM57800_VF:
12569         case BCM57810:
12570         case BCM57810_MF:
12571         case BCM57840_4_10:
12572         case BCM57840_2_20:
12573         case BCM57840_O:
12574         case BCM57840_MFO:
12575         case BCM57810_VF:
12576         case BCM57840_MF:
12577         case BCM57840_VF:
12578         case BCM57811:
12579         case BCM57811_MF:
12580         case BCM57811_VF:
12581                 return BNX2X_MULTI_TX_COS_E3B0;
12582                 return 1;
12583         default:
12584                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12585                 return -ENODEV;
12586         }
12587 }
12588
12589 static int set_is_vf(int chip_id)
12590 {
12591         switch (chip_id) {
12592         case BCM57712_VF:
12593         case BCM57800_VF:
12594         case BCM57810_VF:
12595         case BCM57840_VF:
12596         case BCM57811_VF:
12597                 return true;
12598         default:
12599                 return false;
12600         }
12601 }
12602
12603 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12604
12605 static int bnx2x_init_one(struct pci_dev *pdev,
12606                                     const struct pci_device_id *ent)
12607 {
12608         struct net_device *dev = NULL;
12609         struct bnx2x *bp;
12610         int pcie_width;
12611         enum bnx2x_pci_bus_speed pcie_speed;
12612         int rc, max_non_def_sbs;
12613         int rx_count, tx_count, rss_count, doorbell_size;
12614         int max_cos_est;
12615         bool is_vf;
12616         int cnic_cnt;
12617
12618         /* An estimated maximum supported CoS number according to the chip
12619          * version.
12620          * We will try to roughly estimate the maximum number of CoSes this chip
12621          * may support in order to minimize the memory allocated for Tx
12622          * netdev_queue's. This number will be accurately calculated during the
12623          * initialization of bp->max_cos based on the chip versions AND chip
12624          * revision in the bnx2x_init_bp().
12625          */
12626         max_cos_est = set_max_cos_est(ent->driver_data);
12627         if (max_cos_est < 0)
12628                 return max_cos_est;
12629         is_vf = set_is_vf(ent->driver_data);
12630         cnic_cnt = is_vf ? 0 : 1;
12631
12632         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12633
12634         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12635         rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12636
12637         if (rss_count < 1)
12638                 return -EINVAL;
12639
12640         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12641         rx_count = rss_count + cnic_cnt;
12642
12643         /* Maximum number of netdev Tx queues:
12644          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12645          */
12646         tx_count = rss_count * max_cos_est + cnic_cnt;
12647
12648         /* dev zeroed in init_etherdev */
12649         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12650         if (!dev)
12651                 return -ENOMEM;
12652
12653         bp = netdev_priv(dev);
12654
12655         bp->flags = 0;
12656         if (is_vf)
12657                 bp->flags |= IS_VF_FLAG;
12658
12659         bp->igu_sb_cnt = max_non_def_sbs;
12660         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12661         bp->msg_enable = debug;
12662         bp->cnic_support = cnic_cnt;
12663         bp->cnic_probe = bnx2x_cnic_probe;
12664
12665         pci_set_drvdata(pdev, dev);
12666
12667         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12668         if (rc < 0) {
12669                 free_netdev(dev);
12670                 return rc;
12671         }
12672
12673         BNX2X_DEV_INFO("This is a %s function\n",
12674                        IS_PF(bp) ? "physical" : "virtual");
12675         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12676         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12677         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12678                        tx_count, rx_count);
12679
12680         rc = bnx2x_init_bp(bp);
12681         if (rc)
12682                 goto init_one_exit;
12683
12684         /* Map doorbells here as we need the real value of bp->max_cos which
12685          * is initialized in bnx2x_init_bp() to determine the number of
12686          * l2 connections.
12687          */
12688         if (IS_VF(bp)) {
12689                 bp->doorbells = bnx2x_vf_doorbells(bp);
12690                 rc = bnx2x_vf_pci_alloc(bp);
12691                 if (rc)
12692                         goto init_one_exit;
12693         } else {
12694                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12695                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12696                         dev_err(&bp->pdev->dev,
12697                                 "Cannot map doorbells, bar size too small, aborting\n");
12698                         rc = -ENOMEM;
12699                         goto init_one_exit;
12700                 }
12701                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12702                                                 doorbell_size);
12703         }
12704         if (!bp->doorbells) {
12705                 dev_err(&bp->pdev->dev,
12706                         "Cannot map doorbell space, aborting\n");
12707                 rc = -ENOMEM;
12708                 goto init_one_exit;
12709         }
12710
12711         if (IS_VF(bp)) {
12712                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12713                 if (rc)
12714                         goto init_one_exit;
12715         }
12716
12717         /* Enable SRIOV if capability found in configuration space */
12718         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12719         if (rc)
12720                 goto init_one_exit;
12721
12722         /* calc qm_cid_count */
12723         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12724         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12725
12726         /* disable FCOE L2 queue for E1x*/
12727         if (CHIP_IS_E1x(bp))
12728                 bp->flags |= NO_FCOE_FLAG;
12729
12730         /* Set bp->num_queues for MSI-X mode*/
12731         bnx2x_set_num_queues(bp);
12732
12733         /* Configure interrupt mode: try to enable MSI-X/MSI if
12734          * needed.
12735          */
12736         rc = bnx2x_set_int_mode(bp);
12737         if (rc) {
12738                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12739                 goto init_one_exit;
12740         }
12741         BNX2X_DEV_INFO("set interrupts successfully\n");
12742
12743         /* register the net device */
12744         rc = register_netdev(dev);
12745         if (rc) {
12746                 dev_err(&pdev->dev, "Cannot register net device\n");
12747                 goto init_one_exit;
12748         }
12749         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12750
12751         if (!NO_FCOE(bp)) {
12752                 /* Add storage MAC address */
12753                 rtnl_lock();
12754                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12755                 rtnl_unlock();
12756         }
12757
12758         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12759         BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12760                        pcie_width, pcie_speed);
12761
12762         BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12763                        board_info[ent->driver_data].name,
12764                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12765                        pcie_width,
12766                        pcie_speed == BNX2X_PCI_LINK_SPEED_2500 ? "2.5GHz" :
12767                        pcie_speed == BNX2X_PCI_LINK_SPEED_5000 ? "5.0GHz" :
12768                        pcie_speed == BNX2X_PCI_LINK_SPEED_8000 ? "8.0GHz" :
12769                        "Unknown",
12770                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
12771
12772         return 0;
12773
12774 init_one_exit:
12775         if (bp->regview)
12776                 iounmap(bp->regview);
12777
12778         if (IS_PF(bp) && bp->doorbells)
12779                 iounmap(bp->doorbells);
12780
12781         free_netdev(dev);
12782
12783         if (atomic_read(&pdev->enable_cnt) == 1)
12784                 pci_release_regions(pdev);
12785
12786         pci_disable_device(pdev);
12787         pci_set_drvdata(pdev, NULL);
12788
12789         return rc;
12790 }
12791
12792 static void __bnx2x_remove(struct pci_dev *pdev,
12793                            struct net_device *dev,
12794                            struct bnx2x *bp,
12795                            bool remove_netdev)
12796 {
12797         /* Delete storage MAC address */
12798         if (!NO_FCOE(bp)) {
12799                 rtnl_lock();
12800                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12801                 rtnl_unlock();
12802         }
12803
12804 #ifdef BCM_DCBNL
12805         /* Delete app tlvs from dcbnl */
12806         bnx2x_dcbnl_update_applist(bp, true);
12807 #endif
12808
12809         /* Close the interface - either directly or implicitly */
12810         if (remove_netdev) {
12811                 unregister_netdev(dev);
12812         } else {
12813                 rtnl_lock();
12814                 if (netif_running(dev))
12815                         bnx2x_close(dev);
12816                 rtnl_unlock();
12817         }
12818
12819         /* Power on: we can't let PCI layer write to us while we are in D3 */
12820         if (IS_PF(bp))
12821                 bnx2x_set_power_state(bp, PCI_D0);
12822
12823         /* Disable MSI/MSI-X */
12824         bnx2x_disable_msi(bp);
12825
12826         /* Power off */
12827         if (IS_PF(bp))
12828                 bnx2x_set_power_state(bp, PCI_D3hot);
12829
12830         /* Make sure RESET task is not scheduled before continuing */
12831         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12832
12833         bnx2x_iov_remove_one(bp);
12834
12835         /* send message via vfpf channel to release the resources of this vf */
12836         if (IS_VF(bp))
12837                 bnx2x_vfpf_release(bp);
12838
12839         /* Assumes no further PCIe PM changes will occur */
12840         if (system_state == SYSTEM_POWER_OFF) {
12841                 pci_wake_from_d3(pdev, bp->wol);
12842                 pci_set_power_state(pdev, PCI_D3hot);
12843         }
12844
12845         if (bp->regview)
12846                 iounmap(bp->regview);
12847
12848         /* for vf doorbells are part of the regview and were unmapped along with
12849          * it. FW is only loaded by PF.
12850          */
12851         if (IS_PF(bp)) {
12852                 if (bp->doorbells)
12853                         iounmap(bp->doorbells);
12854
12855                 bnx2x_release_firmware(bp);
12856         }
12857         bnx2x_free_mem_bp(bp);
12858
12859         if (remove_netdev)
12860                 free_netdev(dev);
12861
12862         if (atomic_read(&pdev->enable_cnt) == 1)
12863                 pci_release_regions(pdev);
12864
12865         pci_disable_device(pdev);
12866         pci_set_drvdata(pdev, NULL);
12867 }
12868
12869 static void bnx2x_remove_one(struct pci_dev *pdev)
12870 {
12871         struct net_device *dev = pci_get_drvdata(pdev);
12872         struct bnx2x *bp;
12873
12874         if (!dev) {
12875                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12876                 return;
12877         }
12878         bp = netdev_priv(dev);
12879
12880         __bnx2x_remove(pdev, dev, bp, true);
12881 }
12882
12883 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12884 {
12885         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12886
12887         bp->rx_mode = BNX2X_RX_MODE_NONE;
12888
12889         if (CNIC_LOADED(bp))
12890                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12891
12892         /* Stop Tx */
12893         bnx2x_tx_disable(bp);
12894         /* Delete all NAPI objects */
12895         bnx2x_del_all_napi(bp);
12896         if (CNIC_LOADED(bp))
12897                 bnx2x_del_all_napi_cnic(bp);
12898         netdev_reset_tc(bp->dev);
12899
12900         del_timer_sync(&bp->timer);
12901         cancel_delayed_work(&bp->sp_task);
12902         cancel_delayed_work(&bp->period_task);
12903
12904         spin_lock_bh(&bp->stats_lock);
12905         bp->stats_state = STATS_STATE_DISABLED;
12906         spin_unlock_bh(&bp->stats_lock);
12907
12908         bnx2x_save_statistics(bp);
12909
12910         netif_carrier_off(bp->dev);
12911
12912         return 0;
12913 }
12914
12915 /**
12916  * bnx2x_io_error_detected - called when PCI error is detected
12917  * @pdev: Pointer to PCI device
12918  * @state: The current pci connection state
12919  *
12920  * This function is called after a PCI bus error affecting
12921  * this device has been detected.
12922  */
12923 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12924                                                 pci_channel_state_t state)
12925 {
12926         struct net_device *dev = pci_get_drvdata(pdev);
12927         struct bnx2x *bp = netdev_priv(dev);
12928
12929         rtnl_lock();
12930
12931         BNX2X_ERR("IO error detected\n");
12932
12933         netif_device_detach(dev);
12934
12935         if (state == pci_channel_io_perm_failure) {
12936                 rtnl_unlock();
12937                 return PCI_ERS_RESULT_DISCONNECT;
12938         }
12939
12940         if (netif_running(dev))
12941                 bnx2x_eeh_nic_unload(bp);
12942
12943         bnx2x_prev_path_mark_eeh(bp);
12944
12945         pci_disable_device(pdev);
12946
12947         rtnl_unlock();
12948
12949         /* Request a slot reset */
12950         return PCI_ERS_RESULT_NEED_RESET;
12951 }
12952
12953 /**
12954  * bnx2x_io_slot_reset - called after the PCI bus has been reset
12955  * @pdev: Pointer to PCI device
12956  *
12957  * Restart the card from scratch, as if from a cold-boot.
12958  */
12959 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12960 {
12961         struct net_device *dev = pci_get_drvdata(pdev);
12962         struct bnx2x *bp = netdev_priv(dev);
12963         int i;
12964
12965         rtnl_lock();
12966         BNX2X_ERR("IO slot reset initializing...\n");
12967         if (pci_enable_device(pdev)) {
12968                 dev_err(&pdev->dev,
12969                         "Cannot re-enable PCI device after reset\n");
12970                 rtnl_unlock();
12971                 return PCI_ERS_RESULT_DISCONNECT;
12972         }
12973
12974         pci_set_master(pdev);
12975         pci_restore_state(pdev);
12976         pci_save_state(pdev);
12977
12978         if (netif_running(dev))
12979                 bnx2x_set_power_state(bp, PCI_D0);
12980
12981         if (netif_running(dev)) {
12982                 BNX2X_ERR("IO slot reset --> driver unload\n");
12983
12984                 /* MCP should have been reset; Need to wait for validity */
12985                 bnx2x_init_shmem(bp);
12986
12987                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
12988                         u32 v;
12989
12990                         v = SHMEM2_RD(bp,
12991                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
12992                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
12993                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
12994                 }
12995                 bnx2x_drain_tx_queues(bp);
12996                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
12997                 bnx2x_netif_stop(bp, 1);
12998                 bnx2x_free_irq(bp);
12999
13000                 /* Report UNLOAD_DONE to MCP */
13001                 bnx2x_send_unload_done(bp, true);
13002
13003                 bp->sp_state = 0;
13004                 bp->port.pmf = 0;
13005
13006                 bnx2x_prev_unload(bp);
13007
13008                 /* We should have reseted the engine, so It's fair to
13009                  * assume the FW will no longer write to the bnx2x driver.
13010                  */
13011                 bnx2x_squeeze_objects(bp);
13012                 bnx2x_free_skbs(bp);
13013                 for_each_rx_queue(bp, i)
13014                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13015                 bnx2x_free_fp_mem(bp);
13016                 bnx2x_free_mem(bp);
13017
13018                 bp->state = BNX2X_STATE_CLOSED;
13019         }
13020
13021         rtnl_unlock();
13022
13023         return PCI_ERS_RESULT_RECOVERED;
13024 }
13025
13026 /**
13027  * bnx2x_io_resume - called when traffic can start flowing again
13028  * @pdev: Pointer to PCI device
13029  *
13030  * This callback is called when the error recovery driver tells us that
13031  * its OK to resume normal operation.
13032  */
13033 static void bnx2x_io_resume(struct pci_dev *pdev)
13034 {
13035         struct net_device *dev = pci_get_drvdata(pdev);
13036         struct bnx2x *bp = netdev_priv(dev);
13037
13038         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13039                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13040                 return;
13041         }
13042
13043         rtnl_lock();
13044
13045         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13046                                                         DRV_MSG_SEQ_NUMBER_MASK;
13047
13048         if (netif_running(dev))
13049                 bnx2x_nic_load(bp, LOAD_NORMAL);
13050
13051         netif_device_attach(dev);
13052
13053         rtnl_unlock();
13054 }
13055
13056 static const struct pci_error_handlers bnx2x_err_handler = {
13057         .error_detected = bnx2x_io_error_detected,
13058         .slot_reset     = bnx2x_io_slot_reset,
13059         .resume         = bnx2x_io_resume,
13060 };
13061
13062 static void bnx2x_shutdown(struct pci_dev *pdev)
13063 {
13064         struct net_device *dev = pci_get_drvdata(pdev);
13065         struct bnx2x *bp;
13066
13067         if (!dev)
13068                 return;
13069
13070         bp = netdev_priv(dev);
13071         if (!bp)
13072                 return;
13073
13074         rtnl_lock();
13075         netif_device_detach(dev);
13076         rtnl_unlock();
13077
13078         /* Don't remove the netdevice, as there are scenarios which will cause
13079          * the kernel to hang, e.g., when trying to remove bnx2i while the
13080          * rootfs is mounted from SAN.
13081          */
13082         __bnx2x_remove(pdev, dev, bp, false);
13083 }
13084
13085 static struct pci_driver bnx2x_pci_driver = {
13086         .name        = DRV_MODULE_NAME,
13087         .id_table    = bnx2x_pci_tbl,
13088         .probe       = bnx2x_init_one,
13089         .remove      = bnx2x_remove_one,
13090         .suspend     = bnx2x_suspend,
13091         .resume      = bnx2x_resume,
13092         .err_handler = &bnx2x_err_handler,
13093 #ifdef CONFIG_BNX2X_SRIOV
13094         .sriov_configure = bnx2x_sriov_configure,
13095 #endif
13096         .shutdown    = bnx2x_shutdown,
13097 };
13098
13099 static int __init bnx2x_init(void)
13100 {
13101         int ret;
13102
13103         pr_info("%s", version);
13104
13105         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13106         if (bnx2x_wq == NULL) {
13107                 pr_err("Cannot create workqueue\n");
13108                 return -ENOMEM;
13109         }
13110
13111         ret = pci_register_driver(&bnx2x_pci_driver);
13112         if (ret) {
13113                 pr_err("Cannot register driver\n");
13114                 destroy_workqueue(bnx2x_wq);
13115         }
13116         return ret;
13117 }
13118
13119 static void __exit bnx2x_cleanup(void)
13120 {
13121         struct list_head *pos, *q;
13122
13123         pci_unregister_driver(&bnx2x_pci_driver);
13124
13125         destroy_workqueue(bnx2x_wq);
13126
13127         /* Free globally allocated resources */
13128         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13129                 struct bnx2x_prev_path_list *tmp =
13130                         list_entry(pos, struct bnx2x_prev_path_list, list);
13131                 list_del(pos);
13132                 kfree(tmp);
13133         }
13134 }
13135
13136 void bnx2x_notify_link_changed(struct bnx2x *bp)
13137 {
13138         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13139 }
13140
13141 module_init(bnx2x_init);
13142 module_exit(bnx2x_cleanup);
13143
13144 /**
13145  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13146  *
13147  * @bp:         driver handle
13148  * @set:        set or clear the CAM entry
13149  *
13150  * This function will wait until the ramrod completion returns.
13151  * Return 0 if success, -ENODEV if ramrod doesn't return.
13152  */
13153 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13154 {
13155         unsigned long ramrod_flags = 0;
13156
13157         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13158         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13159                                  &bp->iscsi_l2_mac_obj, true,
13160                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13161 }
13162
13163 /* count denotes the number of new completions we have seen */
13164 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13165 {
13166         struct eth_spe *spe;
13167         int cxt_index, cxt_offset;
13168
13169 #ifdef BNX2X_STOP_ON_ERROR
13170         if (unlikely(bp->panic))
13171                 return;
13172 #endif
13173
13174         spin_lock_bh(&bp->spq_lock);
13175         BUG_ON(bp->cnic_spq_pending < count);
13176         bp->cnic_spq_pending -= count;
13177
13178         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13179                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13180                                 & SPE_HDR_CONN_TYPE) >>
13181                                 SPE_HDR_CONN_TYPE_SHIFT;
13182                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13183                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13184
13185                 /* Set validation for iSCSI L2 client before sending SETUP
13186                  *  ramrod
13187                  */
13188                 if (type == ETH_CONNECTION_TYPE) {
13189                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13190                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13191                                         ILT_PAGE_CIDS;
13192                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13193                                         (cxt_index * ILT_PAGE_CIDS);
13194                                 bnx2x_set_ctx_validation(bp,
13195                                         &bp->context[cxt_index].
13196                                                          vcxt[cxt_offset].eth,
13197                                         BNX2X_ISCSI_ETH_CID(bp));
13198                         }
13199                 }
13200
13201                 /*
13202                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13203                  * and in the air. We also check that number of outstanding
13204                  * COMMON ramrods is not more than the EQ and SPQ can
13205                  * accommodate.
13206                  */
13207                 if (type == ETH_CONNECTION_TYPE) {
13208                         if (!atomic_read(&bp->cq_spq_left))
13209                                 break;
13210                         else
13211                                 atomic_dec(&bp->cq_spq_left);
13212                 } else if (type == NONE_CONNECTION_TYPE) {
13213                         if (!atomic_read(&bp->eq_spq_left))
13214                                 break;
13215                         else
13216                                 atomic_dec(&bp->eq_spq_left);
13217                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13218                            (type == FCOE_CONNECTION_TYPE)) {
13219                         if (bp->cnic_spq_pending >=
13220                             bp->cnic_eth_dev.max_kwqe_pending)
13221                                 break;
13222                         else
13223                                 bp->cnic_spq_pending++;
13224                 } else {
13225                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13226                         bnx2x_panic();
13227                         break;
13228                 }
13229
13230                 spe = bnx2x_sp_get_next(bp);
13231                 *spe = *bp->cnic_kwq_cons;
13232
13233                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13234                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13235
13236                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13237                         bp->cnic_kwq_cons = bp->cnic_kwq;
13238                 else
13239                         bp->cnic_kwq_cons++;
13240         }
13241         bnx2x_sp_prod_update(bp);
13242         spin_unlock_bh(&bp->spq_lock);
13243 }
13244
13245 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13246                                struct kwqe_16 *kwqes[], u32 count)
13247 {
13248         struct bnx2x *bp = netdev_priv(dev);
13249         int i;
13250
13251 #ifdef BNX2X_STOP_ON_ERROR
13252         if (unlikely(bp->panic)) {
13253                 BNX2X_ERR("Can't post to SP queue while panic\n");
13254                 return -EIO;
13255         }
13256 #endif
13257
13258         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13259             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13260                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13261                 return -EAGAIN;
13262         }
13263
13264         spin_lock_bh(&bp->spq_lock);
13265
13266         for (i = 0; i < count; i++) {
13267                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13268
13269                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13270                         break;
13271
13272                 *bp->cnic_kwq_prod = *spe;
13273
13274                 bp->cnic_kwq_pending++;
13275
13276                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13277                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13278                    spe->data.update_data_addr.hi,
13279                    spe->data.update_data_addr.lo,
13280                    bp->cnic_kwq_pending);
13281
13282                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13283                         bp->cnic_kwq_prod = bp->cnic_kwq;
13284                 else
13285                         bp->cnic_kwq_prod++;
13286         }
13287
13288         spin_unlock_bh(&bp->spq_lock);
13289
13290         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13291                 bnx2x_cnic_sp_post(bp, 0);
13292
13293         return i;
13294 }
13295
13296 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13297 {
13298         struct cnic_ops *c_ops;
13299         int rc = 0;
13300
13301         mutex_lock(&bp->cnic_mutex);
13302         c_ops = rcu_dereference_protected(bp->cnic_ops,
13303                                           lockdep_is_held(&bp->cnic_mutex));
13304         if (c_ops)
13305                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13306         mutex_unlock(&bp->cnic_mutex);
13307
13308         return rc;
13309 }
13310
13311 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13312 {
13313         struct cnic_ops *c_ops;
13314         int rc = 0;
13315
13316         rcu_read_lock();
13317         c_ops = rcu_dereference(bp->cnic_ops);
13318         if (c_ops)
13319                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13320         rcu_read_unlock();
13321
13322         return rc;
13323 }
13324
13325 /*
13326  * for commands that have no data
13327  */
13328 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13329 {
13330         struct cnic_ctl_info ctl = {0};
13331
13332         ctl.cmd = cmd;
13333
13334         return bnx2x_cnic_ctl_send(bp, &ctl);
13335 }
13336
13337 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13338 {
13339         struct cnic_ctl_info ctl = {0};
13340
13341         /* first we tell CNIC and only then we count this as a completion */
13342         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13343         ctl.data.comp.cid = cid;
13344         ctl.data.comp.error = err;
13345
13346         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13347         bnx2x_cnic_sp_post(bp, 0);
13348 }
13349
13350 /* Called with netif_addr_lock_bh() taken.
13351  * Sets an rx_mode config for an iSCSI ETH client.
13352  * Doesn't block.
13353  * Completion should be checked outside.
13354  */
13355 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13356 {
13357         unsigned long accept_flags = 0, ramrod_flags = 0;
13358         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13359         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13360
13361         if (start) {
13362                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13363                  * because it's the only way for UIO Queue to accept
13364                  * multicasts (in non-promiscuous mode only one Queue per
13365                  * function will receive multicast packets (leading in our
13366                  * case).
13367                  */
13368                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13369                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13370                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13371                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13372
13373                 /* Clear STOP_PENDING bit if START is requested */
13374                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13375
13376                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13377         } else
13378                 /* Clear START_PENDING bit if STOP is requested */
13379                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13380
13381         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13382                 set_bit(sched_state, &bp->sp_state);
13383         else {
13384                 __set_bit(RAMROD_RX, &ramrod_flags);
13385                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13386                                     ramrod_flags);
13387         }
13388 }
13389
13390 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13391 {
13392         struct bnx2x *bp = netdev_priv(dev);
13393         int rc = 0;
13394
13395         switch (ctl->cmd) {
13396         case DRV_CTL_CTXTBL_WR_CMD: {
13397                 u32 index = ctl->data.io.offset;
13398                 dma_addr_t addr = ctl->data.io.dma_addr;
13399
13400                 bnx2x_ilt_wr(bp, index, addr);
13401                 break;
13402         }
13403
13404         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13405                 int count = ctl->data.credit.credit_count;
13406
13407                 bnx2x_cnic_sp_post(bp, count);
13408                 break;
13409         }
13410
13411         /* rtnl_lock is held.  */
13412         case DRV_CTL_START_L2_CMD: {
13413                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13414                 unsigned long sp_bits = 0;
13415
13416                 /* Configure the iSCSI classification object */
13417                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13418                                    cp->iscsi_l2_client_id,
13419                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13420                                    bnx2x_sp(bp, mac_rdata),
13421                                    bnx2x_sp_mapping(bp, mac_rdata),
13422                                    BNX2X_FILTER_MAC_PENDING,
13423                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13424                                    &bp->macs_pool);
13425
13426                 /* Set iSCSI MAC address */
13427                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13428                 if (rc)
13429                         break;
13430
13431                 mmiowb();
13432                 barrier();
13433
13434                 /* Start accepting on iSCSI L2 ring */
13435
13436                 netif_addr_lock_bh(dev);
13437                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13438                 netif_addr_unlock_bh(dev);
13439
13440                 /* bits to wait on */
13441                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13442                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13443
13444                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13445                         BNX2X_ERR("rx_mode completion timed out!\n");
13446
13447                 break;
13448         }
13449
13450         /* rtnl_lock is held.  */
13451         case DRV_CTL_STOP_L2_CMD: {
13452                 unsigned long sp_bits = 0;
13453
13454                 /* Stop accepting on iSCSI L2 ring */
13455                 netif_addr_lock_bh(dev);
13456                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13457                 netif_addr_unlock_bh(dev);
13458
13459                 /* bits to wait on */
13460                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13461                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13462
13463                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13464                         BNX2X_ERR("rx_mode completion timed out!\n");
13465
13466                 mmiowb();
13467                 barrier();
13468
13469                 /* Unset iSCSI L2 MAC */
13470                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13471                                         BNX2X_ISCSI_ETH_MAC, true);
13472                 break;
13473         }
13474         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13475                 int count = ctl->data.credit.credit_count;
13476
13477                 smp_mb__before_atomic_inc();
13478                 atomic_add(count, &bp->cq_spq_left);
13479                 smp_mb__after_atomic_inc();
13480                 break;
13481         }
13482         case DRV_CTL_ULP_REGISTER_CMD: {
13483                 int ulp_type = ctl->data.register_data.ulp_type;
13484
13485                 if (CHIP_IS_E3(bp)) {
13486                         int idx = BP_FW_MB_IDX(bp);
13487                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13488                         int path = BP_PATH(bp);
13489                         int port = BP_PORT(bp);
13490                         int i;
13491                         u32 scratch_offset;
13492                         u32 *host_addr;
13493
13494                         /* first write capability to shmem2 */
13495                         if (ulp_type == CNIC_ULP_ISCSI)
13496                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13497                         else if (ulp_type == CNIC_ULP_FCOE)
13498                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13499                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13500
13501                         if ((ulp_type != CNIC_ULP_FCOE) ||
13502                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13503                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13504                                 break;
13505
13506                         /* if reached here - should write fcoe capabilities */
13507                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13508                         if (!scratch_offset)
13509                                 break;
13510                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13511                                                    fcoe_features[path][port]);
13512                         host_addr = (u32 *) &(ctl->data.register_data.
13513                                               fcoe_features);
13514                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13515                              i += 4)
13516                                 REG_WR(bp, scratch_offset + i,
13517                                        *(host_addr + i/4));
13518                 }
13519                 break;
13520         }
13521
13522         case DRV_CTL_ULP_UNREGISTER_CMD: {
13523                 int ulp_type = ctl->data.ulp_type;
13524
13525                 if (CHIP_IS_E3(bp)) {
13526                         int idx = BP_FW_MB_IDX(bp);
13527                         u32 cap;
13528
13529                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13530                         if (ulp_type == CNIC_ULP_ISCSI)
13531                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13532                         else if (ulp_type == CNIC_ULP_FCOE)
13533                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13534                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13535                 }
13536                 break;
13537         }
13538
13539         default:
13540                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13541                 rc = -EINVAL;
13542         }
13543
13544         return rc;
13545 }
13546
13547 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13548 {
13549         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13550
13551         if (bp->flags & USING_MSIX_FLAG) {
13552                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13553                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13554                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13555         } else {
13556                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13557                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13558         }
13559         if (!CHIP_IS_E1x(bp))
13560                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13561         else
13562                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13563
13564         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13565         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13566         cp->irq_arr[1].status_blk = bp->def_status_blk;
13567         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13568         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13569
13570         cp->num_irq = 2;
13571 }
13572
13573 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13574 {
13575         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13576
13577         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13578                              bnx2x_cid_ilt_lines(bp);
13579         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13580         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13581         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13582
13583         if (NO_ISCSI_OOO(bp))
13584                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13585 }
13586
13587 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13588                                void *data)
13589 {
13590         struct bnx2x *bp = netdev_priv(dev);
13591         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13592         int rc;
13593
13594         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13595
13596         if (ops == NULL) {
13597                 BNX2X_ERR("NULL ops received\n");
13598                 return -EINVAL;
13599         }
13600
13601         if (!CNIC_SUPPORT(bp)) {
13602                 BNX2X_ERR("Can't register CNIC when not supported\n");
13603                 return -EOPNOTSUPP;
13604         }
13605
13606         if (!CNIC_LOADED(bp)) {
13607                 rc = bnx2x_load_cnic(bp);
13608                 if (rc) {
13609                         BNX2X_ERR("CNIC-related load failed\n");
13610                         return rc;
13611                 }
13612         }
13613
13614         bp->cnic_enabled = true;
13615
13616         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13617         if (!bp->cnic_kwq)
13618                 return -ENOMEM;
13619
13620         bp->cnic_kwq_cons = bp->cnic_kwq;
13621         bp->cnic_kwq_prod = bp->cnic_kwq;
13622         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13623
13624         bp->cnic_spq_pending = 0;
13625         bp->cnic_kwq_pending = 0;
13626
13627         bp->cnic_data = data;
13628
13629         cp->num_irq = 0;
13630         cp->drv_state |= CNIC_DRV_STATE_REGD;
13631         cp->iro_arr = bp->iro_arr;
13632
13633         bnx2x_setup_cnic_irq_info(bp);
13634
13635         rcu_assign_pointer(bp->cnic_ops, ops);
13636
13637         return 0;
13638 }
13639
13640 static int bnx2x_unregister_cnic(struct net_device *dev)
13641 {
13642         struct bnx2x *bp = netdev_priv(dev);
13643         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13644
13645         mutex_lock(&bp->cnic_mutex);
13646         cp->drv_state = 0;
13647         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13648         mutex_unlock(&bp->cnic_mutex);
13649         synchronize_rcu();
13650         bp->cnic_enabled = false;
13651         kfree(bp->cnic_kwq);
13652         bp->cnic_kwq = NULL;
13653
13654         return 0;
13655 }
13656
13657 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13658 {
13659         struct bnx2x *bp = netdev_priv(dev);
13660         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13661
13662         /* If both iSCSI and FCoE are disabled - return NULL in
13663          * order to indicate CNIC that it should not try to work
13664          * with this device.
13665          */
13666         if (NO_ISCSI(bp) && NO_FCOE(bp))
13667                 return NULL;
13668
13669         cp->drv_owner = THIS_MODULE;
13670         cp->chip_id = CHIP_ID(bp);
13671         cp->pdev = bp->pdev;
13672         cp->io_base = bp->regview;
13673         cp->io_base2 = bp->doorbells;
13674         cp->max_kwqe_pending = 8;
13675         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13676         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13677                              bnx2x_cid_ilt_lines(bp);
13678         cp->ctx_tbl_len = CNIC_ILT_LINES;
13679         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13680         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13681         cp->drv_ctl = bnx2x_drv_ctl;
13682         cp->drv_register_cnic = bnx2x_register_cnic;
13683         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13684         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13685         cp->iscsi_l2_client_id =
13686                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13687         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13688
13689         if (NO_ISCSI_OOO(bp))
13690                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13691
13692         if (NO_ISCSI(bp))
13693                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13694
13695         if (NO_FCOE(bp))
13696                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13697
13698         BNX2X_DEV_INFO(
13699                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13700            cp->ctx_blk_size,
13701            cp->ctx_tbl_offset,
13702            cp->ctx_tbl_len,
13703            cp->starting_cid);
13704         return cp;
13705 }
13706
13707 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13708 {
13709         struct bnx2x *bp = fp->bp;
13710         u32 offset = BAR_USTRORM_INTMEM;
13711
13712         if (IS_VF(bp))
13713                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13714         else if (!CHIP_IS_E1x(bp))
13715                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13716         else
13717                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13718
13719         return offset;
13720 }
13721
13722 /* called only on E1H or E2.
13723  * When pretending to be PF, the pretend value is the function number 0...7
13724  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13725  * combination
13726  */
13727 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13728 {
13729         u32 pretend_reg;
13730
13731         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13732                 return -1;
13733
13734         /* get my own pretend register */
13735         pretend_reg = bnx2x_get_pretend_reg(bp);
13736         REG_WR(bp, pretend_reg, pretend_func_val);
13737         REG_RD(bp, pretend_reg);
13738         return 0;
13739 }