Pileus Git - ~andy/linux/blob - drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/aer.h>
  31 #include <linux/init.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/bitops.h>
  37 #include <linux/irq.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/time.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/if_vlan.h>
  44 #include <net/ip.h>
  45 #include <net/ipv6.h>
  46 #include <net/tcp.h>
  47 #include <net/checksum.h>
  48 #include <net/ip6_checksum.h>
  49 #include <linux/workqueue.h>
  50 #include <linux/crc32.h>
  51 #include <linux/crc32c.h>
  52 #include <linux/prefetch.h>
  53 #include <linux/zlib.h>
  54 #include <linux/io.h>
  55 #include <linux/semaphore.h>
  56 #include <linux/stringify.h>
  57 #include <linux/vmalloc.h>
  58
  59 #include "bnx2x.h"
  60 #include "bnx2x_init.h"
  61 #include "bnx2x_init_ops.h"
  62 #include "bnx2x_cmn.h"
  63 #include "bnx2x_vfpf.h"
  64 #include "bnx2x_dcb.h"
  65 #include "bnx2x_sp.h"
  66
  67 #include <linux/firmware.h>
  68 #include "bnx2x_fw_file_hdr.h"
  69 /* FW files */
  70 #define FW_FILE_VERSION                                 \
  71         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  73         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  74         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  75 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  77 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  78
  79 /* Time in jiffies before concluding the transmitter is hung */
  80 #define TX_TIMEOUT              (5*HZ)
  81
  82 static char version[] =
  83         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  84         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  85
  86 MODULE_AUTHOR("Eliezer Tamir");
  87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  88                    "BCM57710/57711/57711E/"
  89                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  90                    "57840/57840_MF Driver");
  91 MODULE_LICENSE("GPL");
  92 MODULE_VERSION(DRV_MODULE_VERSION);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  96
  97 int num_queues;
  98 module_param(num_queues, int, 0);
  99 MODULE_PARM_DESC(num_queues,
 100                  " Set number of queues (default is as a number of CPUs)");
 101
 102 static int disable_tpa;
 103 module_param(disable_tpa, int, 0);
 104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 105
 106 int int_mode;
 107 module_param(int_mode, int, 0);
 108 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 109                                 "(1 INT#x; 2 MSI)");
 110
 111 static int dropless_fc;
 112 module_param(dropless_fc, int, 0);
 113 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 114
 115 static int mrrs = -1;
 116 module_param(mrrs, int, 0);
 117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 118
 119 static int debug;
 120 module_param(debug, int, 0);
 121 MODULE_PARM_DESC(debug, " Default debug msglevel");
 122
 123 struct workqueue_struct *bnx2x_wq;
 124
 125 struct bnx2x_mac_vals {
 126         u32 xmac_addr;
 127         u32 xmac_val;
 128         u32 emac_addr;
 129         u32 emac_val;
 130         u32 umac_addr;
 131         u32 umac_val;
 132         u32 bmac_addr;
 133         u32 bmac_val[2];
 134 };
 135
 136 enum bnx2x_board_type {
 137         BCM57710 = 0,
 138         BCM57711,
 139         BCM57711E,
 140         BCM57712,
 141         BCM57712_MF,
 142         BCM57712_VF,
 143         BCM57800,
 144         BCM57800_MF,
 145         BCM57800_VF,
 146         BCM57810,
 147         BCM57810_MF,
 148         BCM57810_VF,
 149         BCM57840_4_10,
 150         BCM57840_2_20,
 151         BCM57840_MF,
 152         BCM57840_VF,
 153         BCM57811,
 154         BCM57811_MF,
 155         BCM57840_O,
 156         BCM57840_MFO,
 157         BCM57811_VF
 158 };
 159
 160 /* indexed by board_type, above */
 161 static struct {
 162         char *name;
 163 } board_info[] = {
 164         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 165         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 166         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 167         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 168         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 169         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 170         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 171         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 172         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 173         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 174         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 175         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 176         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 177         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 178         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 179         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 180         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 181         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 182         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 183         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 184         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 185 };
 186
 187 #ifndef PCI_DEVICE_ID_NX2_57710
 188 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 189 #endif
 190 #ifndef PCI_DEVICE_ID_NX2_57711
 191 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 192 #endif
 193 #ifndef PCI_DEVICE_ID_NX2_57711E
 194 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 195 #endif
 196 #ifndef PCI_DEVICE_ID_NX2_57712
 197 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 198 #endif
 199 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 200 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 201 #endif
 202 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 203 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 204 #endif
 205 #ifndef PCI_DEVICE_ID_NX2_57800
 206 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 207 #endif
 208 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 209 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 210 #endif
 211 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 212 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 213 #endif
 214 #ifndef PCI_DEVICE_ID_NX2_57810
 215 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 216 #endif
 217 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 218 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 219 #endif
 220 #ifndef PCI_DEVICE_ID_NX2_57840_O
 221 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 222 #endif
 223 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 224 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 225 #endif
 226 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 227 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 228 #endif
 229 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 230 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 231 #endif
 232 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 233 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 234 #endif
 235 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 236 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 237 #endif
 238 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 239 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 240 #endif
 241 #ifndef PCI_DEVICE_ID_NX2_57811
 242 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 243 #endif
 244 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 245 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 246 #endif
 247 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 248 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 249 #endif
 250
 251 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 273         { 0 }
 274 };
 275
 276 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 277
 278 /* Global resources for unloading a previously loaded device */
 279 #define BNX2X_PREV_WAIT_NEEDED 1
 280 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 281 static LIST_HEAD(bnx2x_prev_list);
 282 /****************************************************************************
 283 * General service functions
 284 ****************************************************************************/
 285
 286 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 287                                        u32 addr, dma_addr_t mapping)
 288 {
 289         REG_WR(bp,  addr, U64_LO(mapping));
 290         REG_WR(bp,  addr + 4, U64_HI(mapping));
 291 }
 292
 293 static void storm_memset_spq_addr(struct bnx2x *bp,
 294                                   dma_addr_t mapping, u16 abs_fid)
 295 {
 296         u32 addr = XSEM_REG_FAST_MEMORY +
 297                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 298
 299         __storm_memset_dma_mapping(bp, addr, mapping);
 300 }
 301
 302 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 303                                   u16 pf_id)
 304 {
 305         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 306                 pf_id);
 307         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 308                 pf_id);
 309         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 310                 pf_id);
 311         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 312                 pf_id);
 313 }
 314
 315 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 316                                  u8 enable)
 317 {
 318         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 319                 enable);
 320         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 321                 enable);
 322         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 323                 enable);
 324         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 325                 enable);
 326 }
 327
 328 static void storm_memset_eq_data(struct bnx2x *bp,
 329                                  struct event_ring_data *eq_data,
 330                                 u16 pfid)
 331 {
 332         size_t size = sizeof(struct event_ring_data);
 333
 334         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 335
 336         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 337 }
 338
 339 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 340                                  u16 pfid)
 341 {
 342         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 343         REG_WR16(bp, addr, eq_prod);
 344 }
 345
 346 /* used only at init
 347  * locking is done by mcp
 348  */
 349 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 350 {
 351         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 352         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 353         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 354                                PCICFG_VENDOR_ID_OFFSET);
 355 }
 356
 357 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 358 {
 359         u32 val;
 360
 361         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 362         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 364                                PCICFG_VENDOR_ID_OFFSET);
 365
 366         return val;
 367 }
 368
 369 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 370 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 371 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 372 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 373 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 374
 375 static void bnx2x_dp_dmae(struct bnx2x *bp,
 376                           struct dmae_command *dmae, int msglvl)
 377 {
 378         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 379         int i;
 380
 381         switch (dmae->opcode & DMAE_COMMAND_DST) {
 382         case DMAE_CMD_DST_PCI:
 383                 if (src_type == DMAE_CMD_SRC_PCI)
 384                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 385                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 386                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 387                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 388                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 389                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 390                            dmae->comp_val);
 391                 else
 392                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 393                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 394                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 395                            dmae->opcode, dmae->src_addr_lo >> 2,
 396                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 397                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 398                            dmae->comp_val);
 399                 break;
 400         case DMAE_CMD_DST_GRC:
 401                 if (src_type == DMAE_CMD_SRC_PCI)
 402                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 403                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 404                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 405                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 406                            dmae->len, dmae->dst_addr_lo >> 2,
 407                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 408                            dmae->comp_val);
 409                 else
 410                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 411                            "src [%08x], len [%d*4], dst [%08x]\n"
 412                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 413                            dmae->opcode, dmae->src_addr_lo >> 2,
 414                            dmae->len, dmae->dst_addr_lo >> 2,
 415                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 416                            dmae->comp_val);
 417                 break;
 418         default:
 419                 if (src_type == DMAE_CMD_SRC_PCI)
 420                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 421                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 422                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 423                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 424                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 425                            dmae->comp_val);
 426                 else
 427                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 428                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 429                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 430                            dmae->opcode, dmae->src_addr_lo >> 2,
 431                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 432                            dmae->comp_val);
 433                 break;
 434         }
 435
 436         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 437                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 438                    i, *(((u32 *)dmae) + i));
 439 }
 440
 441 /* copy command into DMAE command memory and set DMAE command go */
 442 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 443 {
 444         u32 cmd_offset;
 445         int i;
 446
 447         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 448         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 449                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 450         }
 451         REG_WR(bp, dmae_reg_go_c[idx], 1);
 452 }
 453
 454 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 455 {
 456         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 457                            DMAE_CMD_C_ENABLE);
 458 }
 459
 460 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 461 {
 462         return opcode & ~DMAE_CMD_SRC_RESET;
 463 }
 464
 465 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 466                              bool with_comp, u8 comp_type)
 467 {
 468         u32 opcode = 0;
 469
 470         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 471                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 472
 473         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 474
 475         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 476         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 477                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 478         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 479
 480 #ifdef __BIG_ENDIAN
 481         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 482 #else
 483         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 484 #endif
 485         if (with_comp)
 486                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 487         return opcode;
 488 }
 489
 490 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 491                                       struct dmae_command *dmae,
 492                                       u8 src_type, u8 dst_type)
 493 {
 494         memset(dmae, 0, sizeof(struct dmae_command));
 495
 496         /* set the opcode */
 497         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 498                                          true, DMAE_COMP_PCI);
 499
 500         /* fill in the completion parameters */
 501         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 502         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 503         dmae->comp_val = DMAE_COMP_VAL;
 504 }
 505
 506 /* issue a dmae command over the init-channel and wait for completion */
 507 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 508                                u32 *comp)
 509 {
 510         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 511         int rc = 0;
 512
 513         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 514
 515         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 516          * as long as this code is called both from syscall context and
 517          * from ndo_set_rx_mode() flow that may be called from BH.
 518          */
 519         spin_lock_bh(&bp->dmae_lock);
 520
 521         /* reset completion */
 522         *comp = 0;
 523
 524         /* post the command on the channel used for initializations */
 525         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 526
 527         /* wait for completion */
 528         udelay(5);
 529         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 530
 531                 if (!cnt ||
 532                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 533                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 534                         BNX2X_ERR("DMAE timeout!\n");
 535                         rc = DMAE_TIMEOUT;
 536                         goto unlock;
 537                 }
 538                 cnt--;
 539                 udelay(50);
 540         }
 541         if (*comp & DMAE_PCI_ERR_FLAG) {
 542                 BNX2X_ERR("DMAE PCI error!\n");
 543                 rc = DMAE_PCI_ERROR;
 544         }
 545
 546 unlock:
 547         spin_unlock_bh(&bp->dmae_lock);
 548         return rc;
 549 }
 550
 551 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 552                       u32 len32)
 553 {
 554         int rc;
 555         struct dmae_command dmae;
 556
 557         if (!bp->dmae_ready) {
 558                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 559
 560                 if (CHIP_IS_E1(bp))
 561                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 562                 else
 563                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 564                 return;
 565         }
 566
 567         /* set opcode and fixed command fields */
 568         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 569
 570         /* fill in addresses and len */
 571         dmae.src_addr_lo = U64_LO(dma_addr);
 572         dmae.src_addr_hi = U64_HI(dma_addr);
 573         dmae.dst_addr_lo = dst_addr >> 2;
 574         dmae.dst_addr_hi = 0;
 575         dmae.len = len32;
 576
 577         /* issue the command and wait for completion */
 578         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 579         if (rc) {
 580                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 581 #ifdef BNX2X_STOP_ON_ERROR
 582                 bnx2x_panic();
 583 #endif
 584         }
 585 }
 586
 587 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 588 {
 589         int rc;
 590         struct dmae_command dmae;
 591
 592         if (!bp->dmae_ready) {
 593                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 594                 int i;
 595
 596                 if (CHIP_IS_E1(bp))
 597                         for (i = 0; i < len32; i++)
 598                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 599                 else
 600                         for (i = 0; i < len32; i++)
 601                                 data[i] = REG_RD(bp, src_addr + i*4);
 602
 603                 return;
 604         }
 605
 606         /* set opcode and fixed command fields */
 607         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 608
 609         /* fill in addresses and len */
 610         dmae.src_addr_lo = src_addr >> 2;
 611         dmae.src_addr_hi = 0;
 612         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 613         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 614         dmae.len = len32;
 615
 616         /* issue the command and wait for completion */
 617         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 618         if (rc) {
 619                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 620 #ifdef BNX2X_STOP_ON_ERROR
 621                 bnx2x_panic();
 622 #endif
 623         }
 624 }
 625
 626 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 627                                       u32 addr, u32 len)
 628 {
 629         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 630         int offset = 0;
 631
 632         while (len > dmae_wr_max) {
 633                 bnx2x_write_dmae(bp, phys_addr + offset,
 634                                  addr + offset, dmae_wr_max);
 635                 offset += dmae_wr_max * 4;
 636                 len -= dmae_wr_max;
 637         }
 638
 639         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 640 }
 641
 642 static int bnx2x_mc_assert(struct bnx2x *bp)
 643 {
 644         char last_idx;
 645         int i, rc = 0;
 646         u32 row0, row1, row2, row3;
 647
 648         /* XSTORM */
 649         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 650                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 651         if (last_idx)
 652                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 653
 654         /* print the asserts */
 655         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 656
 657                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 658                               XSTORM_ASSERT_LIST_OFFSET(i));
 659                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 660                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 661                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 662                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 663                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 664                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 665
 666                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 667                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 668                                   i, row3, row2, row1, row0);
 669                         rc++;
 670                 } else {
 671                         break;
 672                 }
 673         }
 674
 675         /* TSTORM */
 676         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 677                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 678         if (last_idx)
 679                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 680
 681         /* print the asserts */
 682         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 683
 684                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 685                               TSTORM_ASSERT_LIST_OFFSET(i));
 686                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 687                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 688                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 689                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 690                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 691                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 692
 693                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 694                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 695                                   i, row3, row2, row1, row0);
 696                         rc++;
 697                 } else {
 698                         break;
 699                 }
 700         }
 701
 702         /* CSTORM */
 703         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 704                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 705         if (last_idx)
 706                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 707
 708         /* print the asserts */
 709         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 710
 711                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 712                               CSTORM_ASSERT_LIST_OFFSET(i));
 713                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 714                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 715                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 716                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 717                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 718                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 719
 720                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 721                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 722                                   i, row3, row2, row1, row0);
 723                         rc++;
 724                 } else {
 725                         break;
 726                 }
 727         }
 728
 729         /* USTORM */
 730         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 731                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 732         if (last_idx)
 733                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 734
 735         /* print the asserts */
 736         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 737
 738                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 739                               USTORM_ASSERT_LIST_OFFSET(i));
 740                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 741                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 742                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 743                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 744                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 745                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 746
 747                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 748                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 749                                   i, row3, row2, row1, row0);
 750                         rc++;
 751                 } else {
 752                         break;
 753                 }
 754         }
 755
 756         return rc;
 757 }
 758
 759 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 760 #define SCRATCH_BUFFER_SIZE(bp) \
 761         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 762
 763 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 764 {
 765         u32 addr, val;
 766         u32 mark, offset;
 767         __be32 data[9];
 768         int word;
 769         u32 trace_shmem_base;
 770         if (BP_NOMCP(bp)) {
 771                 BNX2X_ERR("NO MCP - can not dump\n");
 772                 return;
 773         }
 774         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 775                 (bp->common.bc_ver & 0xff0000) >> 16,
 776                 (bp->common.bc_ver & 0xff00) >> 8,
 777                 (bp->common.bc_ver & 0xff));
 778
 779         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 780         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 781                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 782
 783         if (BP_PATH(bp) == 0)
 784                 trace_shmem_base = bp->common.shmem_base;
 785         else
 786                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 787
 788         /* sanity */
 789         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 790             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 791                                 SCRATCH_BUFFER_SIZE(bp)) {
 792                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 793                           trace_shmem_base);
 794                 return;
 795         }
 796
 797         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 798
 799         /* validate TRCB signature */
 800         mark = REG_RD(bp, addr);
 801         if (mark != MFW_TRACE_SIGNATURE) {
 802                 BNX2X_ERR("Trace buffer signature is missing.");
 803                 return ;
 804         }
 805
 806         /* read cyclic buffer pointer */
 807         addr += 4;
 808         mark = REG_RD(bp, addr);
 809         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 810         if (mark >= trace_shmem_base || mark < addr + 4) {
 811                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 812                 return;
 813         }
 814         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 815
 816         printk("%s", lvl);
 817
 818         /* dump buffer after the mark */
 819         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 820                 for (word = 0; word < 8; word++)
 821                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 822                 data[8] = 0x0;
 823                 pr_cont("%s", (char *)data);
 824         }
 825
 826         /* dump buffer before the mark */
 827         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 828                 for (word = 0; word < 8; word++)
 829                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 830                 data[8] = 0x0;
 831                 pr_cont("%s", (char *)data);
 832         }
 833         printk("%s" "end of fw dump\n", lvl);
 834 }
 835
 836 static void bnx2x_fw_dump(struct bnx2x *bp)
 837 {
 838         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 839 }
 840
 841 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 842 {
 843         int port = BP_PORT(bp);
 844         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 845         u32 val = REG_RD(bp, addr);
 846
 847         /* in E1 we must use only PCI configuration space to disable
 848          * MSI/MSIX capability
 849          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 850          */
 851         if (CHIP_IS_E1(bp)) {
 852                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 853                  * Use mask register to prevent from HC sending interrupts
 854                  * after we exit the function
 855                  */
 856                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 857
 858                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 859                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 860                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 861         } else
 862                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 863                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 864                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 865                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 866
 867         DP(NETIF_MSG_IFDOWN,
 868            "write %x to HC %d (addr 0x%x)\n",
 869            val, port, addr);
 870
 871         /* flush all outstanding writes */
 872         mmiowb();
 873
 874         REG_WR(bp, addr, val);
 875         if (REG_RD(bp, addr) != val)
 876                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 877 }
 878
 879 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 880 {
 881         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 882
 883         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 884                  IGU_PF_CONF_INT_LINE_EN |
 885                  IGU_PF_CONF_ATTN_BIT_EN);
 886
 887         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 888
 889         /* flush all outstanding writes */
 890         mmiowb();
 891
 892         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 893         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 894                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 895 }
 896
 897 static void bnx2x_int_disable(struct bnx2x *bp)
 898 {
 899         if (bp->common.int_block == INT_BLOCK_HC)
 900                 bnx2x_hc_int_disable(bp);
 901         else
 902                 bnx2x_igu_int_disable(bp);
 903 }
 904
 905 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 906 {
 907         int i;
 908         u16 j;
 909         struct hc_sp_status_block_data sp_sb_data;
 910         int func = BP_FUNC(bp);
 911 #ifdef BNX2X_STOP_ON_ERROR
 912         u16 start = 0, end = 0;
 913         u8 cos;
 914 #endif
 915         if (disable_int)
 916                 bnx2x_int_disable(bp);
 917
 918         bp->stats_state = STATS_STATE_DISABLED;
 919         bp->eth_stats.unrecoverable_error++;
 920         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 921
 922         BNX2X_ERR("begin crash dump -----------------\n");
 923
 924         /* Indices */
 925         /* Common */
 926         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 927                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 928                   bp->spq_prod_idx, bp->stats_counter);
 929         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 930                   bp->def_status_blk->atten_status_block.attn_bits,
 931                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 932                   bp->def_status_blk->atten_status_block.status_block_id,
 933                   bp->def_status_blk->atten_status_block.attn_bits_index);
 934         BNX2X_ERR("     def (");
 935         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 936                 pr_cont("0x%x%s",
 937                         bp->def_status_blk->sp_sb.index_values[i],
 938                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 939
 940         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 941                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 942                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 943                         i*sizeof(u32));
 944
 945         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 946                sp_sb_data.igu_sb_id,
 947                sp_sb_data.igu_seg_id,
 948                sp_sb_data.p_func.pf_id,
 949                sp_sb_data.p_func.vnic_id,
 950                sp_sb_data.p_func.vf_id,
 951                sp_sb_data.p_func.vf_valid,
 952                sp_sb_data.state);
 953
 954         for_each_eth_queue(bp, i) {
 955                 struct bnx2x_fastpath *fp = &bp->fp[i];
 956                 int loop;
 957                 struct hc_status_block_data_e2 sb_data_e2;
 958                 struct hc_status_block_data_e1x sb_data_e1x;
 959                 struct hc_status_block_sm  *hc_sm_p =
 960                         CHIP_IS_E1x(bp) ?
 961                         sb_data_e1x.common.state_machine :
 962                         sb_data_e2.common.state_machine;
 963                 struct hc_index_data *hc_index_p =
 964                         CHIP_IS_E1x(bp) ?
 965                         sb_data_e1x.index_data :
 966                         sb_data_e2.index_data;
 967                 u8 data_size, cos;
 968                 u32 *sb_data_p;
 969                 struct bnx2x_fp_txdata txdata;
 970
 971                 /* Rx */
 972                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 973                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 974                           fp->rx_comp_prod,
 975                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 976                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 977                           fp->rx_sge_prod, fp->last_max_sge,
 978                           le16_to_cpu(fp->fp_hc_idx));
 979
 980                 /* Tx */
 981                 for_each_cos_in_tx_queue(fp, cos)
 982                 {
 983                         txdata = *fp->txdata_ptr[cos];
 984                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 985                                   i, txdata.tx_pkt_prod,
 986                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 987                                   txdata.tx_bd_cons,
 988                                   le16_to_cpu(*txdata.tx_cons_sb));
 989                 }
 990
 991                 loop = CHIP_IS_E1x(bp) ?
 992                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 993
 994                 /* host sb data */
 995
 996                 if (IS_FCOE_FP(fp))
 997                         continue;
 998
 999                 BNX2X_ERR("     run indexes (");
1000                 for (j = 0; j < HC_SB_MAX_SM; j++)
1001                         pr_cont("0x%x%s",
1002                                fp->sb_running_index[j],
1003                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1004
1005                 BNX2X_ERR("     indexes (");
1006                 for (j = 0; j < loop; j++)
1007                         pr_cont("0x%x%s",
1008                                fp->sb_index_values[j],
1009                                (j == loop - 1) ? ")" : " ");
1010                 /* fw sb data */
1011                 data_size = CHIP_IS_E1x(bp) ?
1012                         sizeof(struct hc_status_block_data_e1x) :
1013                         sizeof(struct hc_status_block_data_e2);
1014                 data_size /= sizeof(u32);
1015                 sb_data_p = CHIP_IS_E1x(bp) ?
1016                         (u32 *)&sb_data_e1x :
1017                         (u32 *)&sb_data_e2;
1018                 /* copy sb data in here */
1019                 for (j = 0; j < data_size; j++)
1020                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1021                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1022                                 j * sizeof(u32));
1023
1024                 if (!CHIP_IS_E1x(bp)) {
1025                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1026                                 sb_data_e2.common.p_func.pf_id,
1027                                 sb_data_e2.common.p_func.vf_id,
1028                                 sb_data_e2.common.p_func.vf_valid,
1029                                 sb_data_e2.common.p_func.vnic_id,
1030                                 sb_data_e2.common.same_igu_sb_1b,
1031                                 sb_data_e2.common.state);
1032                 } else {
1033                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1034                                 sb_data_e1x.common.p_func.pf_id,
1035                                 sb_data_e1x.common.p_func.vf_id,
1036                                 sb_data_e1x.common.p_func.vf_valid,
1037                                 sb_data_e1x.common.p_func.vnic_id,
1038                                 sb_data_e1x.common.same_igu_sb_1b,
1039                                 sb_data_e1x.common.state);
1040                 }
1041
1042                 /* SB_SMs data */
1043                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1044                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1045                                 j, hc_sm_p[j].__flags,
1046                                 hc_sm_p[j].igu_sb_id,
1047                                 hc_sm_p[j].igu_seg_id,
1048                                 hc_sm_p[j].time_to_expire,
1049                                 hc_sm_p[j].timer_value);
1050                 }
1051
1052                 /* Indices data */
1053                 for (j = 0; j < loop; j++) {
1054                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1055                                hc_index_p[j].flags,
1056                                hc_index_p[j].timeout);
1057                 }
1058         }
1059
1060 #ifdef BNX2X_STOP_ON_ERROR
1061
1062         /* event queue */
1063         BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1064         for (i = 0; i < NUM_EQ_DESC; i++) {
1065                 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1066
1067                 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1068                           i, bp->eq_ring[i].message.opcode,
1069                           bp->eq_ring[i].message.error);
1070                 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1071         }
1072
1073         /* Rings */
1074         /* Rx */
1075         for_each_valid_rx_queue(bp, i) {
1076                 struct bnx2x_fastpath *fp = &bp->fp[i];
1077
1078                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1079                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1080                 for (j = start; j != end; j = RX_BD(j + 1)) {
1081                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1082                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1083
1084                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1085                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1086                 }
1087
1088                 start = RX_SGE(fp->rx_sge_prod);
1089                 end = RX_SGE(fp->last_max_sge);
1090                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1091                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1092                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1093
1094                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1095                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1096                 }
1097
1098                 start = RCQ_BD(fp->rx_comp_cons - 10);
1099                 end = RCQ_BD(fp->rx_comp_cons + 503);
1100                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1101                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1102
1103                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1104                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1105                 }
1106         }
1107
1108         /* Tx */
1109         for_each_valid_tx_queue(bp, i) {
1110                 struct bnx2x_fastpath *fp = &bp->fp[i];
1111                 for_each_cos_in_tx_queue(fp, cos) {
1112                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1113
1114                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1115                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1116                         for (j = start; j != end; j = TX_BD(j + 1)) {
1117                                 struct sw_tx_bd *sw_bd =
1118                                         &txdata->tx_buf_ring[j];
1119
1120                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1121                                           i, cos, j, sw_bd->skb,
1122                                           sw_bd->first_bd);
1123                         }
1124
1125                         start = TX_BD(txdata->tx_bd_cons - 10);
1126                         end = TX_BD(txdata->tx_bd_cons + 254);
1127                         for (j = start; j != end; j = TX_BD(j + 1)) {
1128                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1129
1130                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1131                                           i, cos, j, tx_bd[0], tx_bd[1],
1132                                           tx_bd[2], tx_bd[3]);
1133                         }
1134                 }
1135         }
1136 #endif
1137         bnx2x_fw_dump(bp);
1138         bnx2x_mc_assert(bp);
1139         BNX2X_ERR("end crash dump -----------------\n");
1140 }
1141
1142 /*
1143  * FLR Support for E2
1144  *
1145  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1146  * initialization.
1147  */
1148 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1149 #define FLR_WAIT_INTERVAL       50      /* usec */
1150 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1151
1152 struct pbf_pN_buf_regs {
1153         int pN;
1154         u32 init_crd;
1155         u32 crd;
1156         u32 crd_freed;
1157 };
1158
1159 struct pbf_pN_cmd_regs {
1160         int pN;
1161         u32 lines_occup;
1162         u32 lines_freed;
1163 };
1164
1165 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1166                                      struct pbf_pN_buf_regs *regs,
1167                                      u32 poll_count)
1168 {
1169         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1170         u32 cur_cnt = poll_count;
1171
1172         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1173         crd = crd_start = REG_RD(bp, regs->crd);
1174         init_crd = REG_RD(bp, regs->init_crd);
1175
1176         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1177         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1178         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1179
1180         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1181                (init_crd - crd_start))) {
1182                 if (cur_cnt--) {
1183                         udelay(FLR_WAIT_INTERVAL);
1184                         crd = REG_RD(bp, regs->crd);
1185                         crd_freed = REG_RD(bp, regs->crd_freed);
1186                 } else {
1187                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1188                            regs->pN);
1189                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1190                            regs->pN, crd);
1191                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1192                            regs->pN, crd_freed);
1193                         break;
1194                 }
1195         }
1196         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1197            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1198 }
1199
1200 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1201                                      struct pbf_pN_cmd_regs *regs,
1202                                      u32 poll_count)
1203 {
1204         u32 occup, to_free, freed, freed_start;
1205         u32 cur_cnt = poll_count;
1206
1207         occup = to_free = REG_RD(bp, regs->lines_occup);
1208         freed = freed_start = REG_RD(bp, regs->lines_freed);
1209
1210         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1211         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1212
1213         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1214                 if (cur_cnt--) {
1215                         udelay(FLR_WAIT_INTERVAL);
1216                         occup = REG_RD(bp, regs->lines_occup);
1217                         freed = REG_RD(bp, regs->lines_freed);
1218                 } else {
1219                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1220                            regs->pN);
1221                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1222                            regs->pN, occup);
1223                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1224                            regs->pN, freed);
1225                         break;
1226                 }
1227         }
1228         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1229            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1230 }
1231
1232 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1233                                     u32 expected, u32 poll_count)
1234 {
1235         u32 cur_cnt = poll_count;
1236         u32 val;
1237
1238         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1239                 udelay(FLR_WAIT_INTERVAL);
1240
1241         return val;
1242 }
1243
1244 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1245                                     char *msg, u32 poll_cnt)
1246 {
1247         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1248         if (val != 0) {
1249                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1250                 return 1;
1251         }
1252         return 0;
1253 }
1254
1255 /* Common routines with VF FLR cleanup */
1256 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1257 {
1258         /* adjust polling timeout */
1259         if (CHIP_REV_IS_EMUL(bp))
1260                 return FLR_POLL_CNT * 2000;
1261
1262         if (CHIP_REV_IS_FPGA(bp))
1263                 return FLR_POLL_CNT * 120;
1264
1265         return FLR_POLL_CNT;
1266 }
1267
1268 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1269 {
1270         struct pbf_pN_cmd_regs cmd_regs[] = {
1271                 {0, (CHIP_IS_E3B0(bp)) ?
1272                         PBF_REG_TQ_OCCUPANCY_Q0 :
1273                         PBF_REG_P0_TQ_OCCUPANCY,
1274                     (CHIP_IS_E3B0(bp)) ?
1275                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1276                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1277                 {1, (CHIP_IS_E3B0(bp)) ?
1278                         PBF_REG_TQ_OCCUPANCY_Q1 :
1279                         PBF_REG_P1_TQ_OCCUPANCY,
1280                     (CHIP_IS_E3B0(bp)) ?
1281                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1282                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1283                 {4, (CHIP_IS_E3B0(bp)) ?
1284                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1285                         PBF_REG_P4_TQ_OCCUPANCY,
1286                     (CHIP_IS_E3B0(bp)) ?
1287                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1288                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1289         };
1290
1291         struct pbf_pN_buf_regs buf_regs[] = {
1292                 {0, (CHIP_IS_E3B0(bp)) ?
1293                         PBF_REG_INIT_CRD_Q0 :
1294                         PBF_REG_P0_INIT_CRD ,
1295                     (CHIP_IS_E3B0(bp)) ?
1296                         PBF_REG_CREDIT_Q0 :
1297                         PBF_REG_P0_CREDIT,
1298                     (CHIP_IS_E3B0(bp)) ?
1299                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1300                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1301                 {1, (CHIP_IS_E3B0(bp)) ?
1302                         PBF_REG_INIT_CRD_Q1 :
1303                         PBF_REG_P1_INIT_CRD,
1304                     (CHIP_IS_E3B0(bp)) ?
1305                         PBF_REG_CREDIT_Q1 :
1306                         PBF_REG_P1_CREDIT,
1307                     (CHIP_IS_E3B0(bp)) ?
1308                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1309                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1310                 {4, (CHIP_IS_E3B0(bp)) ?
1311                         PBF_REG_INIT_CRD_LB_Q :
1312                         PBF_REG_P4_INIT_CRD,
1313                     (CHIP_IS_E3B0(bp)) ?
1314                         PBF_REG_CREDIT_LB_Q :
1315                         PBF_REG_P4_CREDIT,
1316                     (CHIP_IS_E3B0(bp)) ?
1317                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1318                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1319         };
1320
1321         int i;
1322
1323         /* Verify the command queues are flushed P0, P1, P4 */
1324         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1325                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1326
1327         /* Verify the transmission buffers are flushed P0, P1, P4 */
1328         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1329                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1330 }
1331
1332 #define OP_GEN_PARAM(param) \
1333         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1334
1335 #define OP_GEN_TYPE(type) \
1336         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1337
1338 #define OP_GEN_AGG_VECT(index) \
1339         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1340
1341 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1342 {
1343         u32 op_gen_command = 0;
1344         u32 comp_addr = BAR_CSTRORM_INTMEM +
1345                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1346         int ret = 0;
1347
1348         if (REG_RD(bp, comp_addr)) {
1349                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1350                 return 1;
1351         }
1352
1353         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1354         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1355         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1356         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1357
1358         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1359         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1360
1361         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1362                 BNX2X_ERR("FW final cleanup did not succeed\n");
1363                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1364                    (REG_RD(bp, comp_addr)));
1365                 bnx2x_panic();
1366                 return 1;
1367         }
1368         /* Zero completion for next FLR */
1369         REG_WR(bp, comp_addr, 0);
1370
1371         return ret;
1372 }
1373
1374 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1375 {
1376         u16 status;
1377
1378         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1379         return status & PCI_EXP_DEVSTA_TRPND;
1380 }
1381
1382 /* PF FLR specific routines
1383 */
1384 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1385 {
1386         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1387         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1388                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1389                         "CFC PF usage counter timed out",
1390                         poll_cnt))
1391                 return 1;
1392
1393         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1394         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1395                         DORQ_REG_PF_USAGE_CNT,
1396                         "DQ PF usage counter timed out",
1397                         poll_cnt))
1398                 return 1;
1399
1400         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1401         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1402                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1403                         "QM PF usage counter timed out",
1404                         poll_cnt))
1405                 return 1;
1406
1407         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1408         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1409                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1410                         "Timers VNIC usage counter timed out",
1411                         poll_cnt))
1412                 return 1;
1413         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1414                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1415                         "Timers NUM_SCANS usage counter timed out",
1416                         poll_cnt))
1417                 return 1;
1418
1419         /* Wait DMAE PF usage counter to zero */
1420         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1421                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1422                         "DMAE command register timed out",
1423                         poll_cnt))
1424                 return 1;
1425
1426         return 0;
1427 }
1428
1429 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1430 {
1431         u32 val;
1432
1433         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1434         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1435
1436         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1437         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1438
1439         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1440         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1441
1442         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1443         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1444
1445         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1446         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1447
1448         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1449         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1450
1451         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1452         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1453
1454         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1455         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1456            val);
1457 }
1458
1459 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1460 {
1461         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1462
1463         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1464
1465         /* Re-enable PF target read access */
1466         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1467
1468         /* Poll HW usage counters */
1469         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1470         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1471                 return -EBUSY;
1472
1473         /* Zero the igu 'trailing edge' and 'leading edge' */
1474
1475         /* Send the FW cleanup command */
1476         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1477                 return -EBUSY;
1478
1479         /* ATC cleanup */
1480
1481         /* Verify TX hw is flushed */
1482         bnx2x_tx_hw_flushed(bp, poll_cnt);
1483
1484         /* Wait 100ms (not adjusted according to platform) */
1485         msleep(100);
1486
1487         /* Verify no pending pci transactions */
1488         if (bnx2x_is_pcie_pending(bp->pdev))
1489                 BNX2X_ERR("PCIE Transactions still pending\n");
1490
1491         /* Debug */
1492         bnx2x_hw_enable_status(bp);
1493
1494         /*
1495          * Master enable - Due to WB DMAE writes performed before this
1496          * register is re-initialized as part of the regular function init
1497          */
1498         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1499
1500         return 0;
1501 }
1502
1503 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1504 {
1505         int port = BP_PORT(bp);
1506         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1507         u32 val = REG_RD(bp, addr);
1508         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1509         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1510         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1511
1512         if (msix) {
1513                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1514                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1515                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1516                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1517                 if (single_msix)
1518                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1519         } else if (msi) {
1520                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1521                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1522                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1523                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1524         } else {
1525                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1526                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1527                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1528                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1529
1530                 if (!CHIP_IS_E1(bp)) {
1531                         DP(NETIF_MSG_IFUP,
1532                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1533
1534                         REG_WR(bp, addr, val);
1535
1536                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1537                 }
1538         }
1539
1540         if (CHIP_IS_E1(bp))
1541                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1542
1543         DP(NETIF_MSG_IFUP,
1544            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1545            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1546
1547         REG_WR(bp, addr, val);
1548         /*
1549          * Ensure that HC_CONFIG is written before leading/trailing edge config
1550          */
1551         mmiowb();
1552         barrier();
1553
1554         if (!CHIP_IS_E1(bp)) {
1555                 /* init leading/trailing edge */
1556                 if (IS_MF(bp)) {
1557                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1558                         if (bp->port.pmf)
1559                                 /* enable nig and gpio3 attention */
1560                                 val |= 0x1100;
1561                 } else
1562                         val = 0xffff;
1563
1564                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1565                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1566         }
1567
1568         /* Make sure that interrupts are indeed enabled from here on */
1569         mmiowb();
1570 }
1571
1572 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1573 {
1574         u32 val;
1575         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1576         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1577         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1578
1579         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1580
1581         if (msix) {
1582                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1583                          IGU_PF_CONF_SINGLE_ISR_EN);
1584                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1585                         IGU_PF_CONF_ATTN_BIT_EN);
1586
1587                 if (single_msix)
1588                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1589         } else if (msi) {
1590                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1591                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1592                         IGU_PF_CONF_ATTN_BIT_EN |
1593                         IGU_PF_CONF_SINGLE_ISR_EN);
1594         } else {
1595                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1596                 val |= (IGU_PF_CONF_INT_LINE_EN |
1597                         IGU_PF_CONF_ATTN_BIT_EN |
1598                         IGU_PF_CONF_SINGLE_ISR_EN);
1599         }
1600
1601         /* Clean previous status - need to configure igu prior to ack*/
1602         if ((!msix) || single_msix) {
1603                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1604                 bnx2x_ack_int(bp);
1605         }
1606
1607         val |= IGU_PF_CONF_FUNC_EN;
1608
1609         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1610            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1611
1612         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1613
1614         if (val & IGU_PF_CONF_INT_LINE_EN)
1615                 pci_intx(bp->pdev, true);
1616
1617         barrier();
1618
1619         /* init leading/trailing edge */
1620         if (IS_MF(bp)) {
1621                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1622                 if (bp->port.pmf)
1623                         /* enable nig and gpio3 attention */
1624                         val |= 0x1100;
1625         } else
1626                 val = 0xffff;
1627
1628         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1629         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1630
1631         /* Make sure that interrupts are indeed enabled from here on */
1632         mmiowb();
1633 }
1634
1635 void bnx2x_int_enable(struct bnx2x *bp)
1636 {
1637         if (bp->common.int_block == INT_BLOCK_HC)
1638                 bnx2x_hc_int_enable(bp);
1639         else
1640                 bnx2x_igu_int_enable(bp);
1641 }
1642
1643 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1644 {
1645         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1646         int i, offset;
1647
1648         if (disable_hw)
1649                 /* prevent the HW from sending interrupts */
1650                 bnx2x_int_disable(bp);
1651
1652         /* make sure all ISRs are done */
1653         if (msix) {
1654                 synchronize_irq(bp->msix_table[0].vector);
1655                 offset = 1;
1656                 if (CNIC_SUPPORT(bp))
1657                         offset++;
1658                 for_each_eth_queue(bp, i)
1659                         synchronize_irq(bp->msix_table[offset++].vector);
1660         } else
1661                 synchronize_irq(bp->pdev->irq);
1662
1663         /* make sure sp_task is not running */
1664         cancel_delayed_work(&bp->sp_task);
1665         cancel_delayed_work(&bp->period_task);
1666         flush_workqueue(bnx2x_wq);
1667 }
1668
1669 /* fast path */
1670
1671 /*
1672  * General service functions
1673  */
1674
1675 /* Return true if succeeded to acquire the lock */
1676 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1677 {
1678         u32 lock_status;
1679         u32 resource_bit = (1 << resource);
1680         int func = BP_FUNC(bp);
1681         u32 hw_lock_control_reg;
1682
1683         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1684            "Trying to take a lock on resource %d\n", resource);
1685
1686         /* Validating that the resource is within range */
1687         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1688                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1689                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1690                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1691                 return false;
1692         }
1693
1694         if (func <= 5)
1695                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1696         else
1697                 hw_lock_control_reg =
1698                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1699
1700         /* Try to acquire the lock */
1701         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1702         lock_status = REG_RD(bp, hw_lock_control_reg);
1703         if (lock_status & resource_bit)
1704                 return true;
1705
1706         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1707            "Failed to get a lock on resource %d\n", resource);
1708         return false;
1709 }
1710
1711 /**
1712  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1713  *
1714  * @bp: driver handle
1715  *
1716  * Returns the recovery leader resource id according to the engine this function
1717  * belongs to. Currently only only 2 engines is supported.
1718  */
1719 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1720 {
1721         if (BP_PATH(bp))
1722                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1723         else
1724                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1725 }
1726
1727 /**
1728  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1729  *
1730  * @bp: driver handle
1731  *
1732  * Tries to acquire a leader lock for current engine.
1733  */
1734 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1735 {
1736         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1737 }
1738
1739 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1740
1741 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1742 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1743 {
1744         /* Set the interrupt occurred bit for the sp-task to recognize it
1745          * must ack the interrupt and transition according to the IGU
1746          * state machine.
1747          */
1748         atomic_set(&bp->interrupt_occurred, 1);
1749
1750         /* The sp_task must execute only after this bit
1751          * is set, otherwise we will get out of sync and miss all
1752          * further interrupts. Hence, the barrier.
1753          */
1754         smp_wmb();
1755
1756         /* schedule sp_task to workqueue */
1757         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1758 }
1759
1760 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1761 {
1762         struct bnx2x *bp = fp->bp;
1763         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1764         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1765         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1766         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1767
1768         DP(BNX2X_MSG_SP,
1769            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1770            fp->index, cid, command, bp->state,
1771            rr_cqe->ramrod_cqe.ramrod_type);
1772
1773         /* If cid is within VF range, replace the slowpath object with the
1774          * one corresponding to this VF
1775          */
1776         if (cid >= BNX2X_FIRST_VF_CID  &&
1777             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1778                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1779
1780         switch (command) {
1781         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1782                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1783                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1784                 break;
1785
1786         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1787                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1788                 drv_cmd = BNX2X_Q_CMD_SETUP;
1789                 break;
1790
1791         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1792                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1793                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1794                 break;
1795
1796         case (RAMROD_CMD_ID_ETH_HALT):
1797                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1798                 drv_cmd = BNX2X_Q_CMD_HALT;
1799                 break;
1800
1801         case (RAMROD_CMD_ID_ETH_TERMINATE):
1802                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1803                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1804                 break;
1805
1806         case (RAMROD_CMD_ID_ETH_EMPTY):
1807                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1808                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1809                 break;
1810
1811         default:
1812                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1813                           command, fp->index);
1814                 return;
1815         }
1816
1817         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1818             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1819                 /* q_obj->complete_cmd() failure means that this was
1820                  * an unexpected completion.
1821                  *
1822                  * In this case we don't want to increase the bp->spq_left
1823                  * because apparently we haven't sent this command the first
1824                  * place.
1825                  */
1826 #ifdef BNX2X_STOP_ON_ERROR
1827                 bnx2x_panic();
1828 #else
1829                 return;
1830 #endif
1831         /* SRIOV: reschedule any 'in_progress' operations */
1832         bnx2x_iov_sp_event(bp, cid, true);
1833
1834         smp_mb__before_atomic_inc();
1835         atomic_inc(&bp->cq_spq_left);
1836         /* push the change in bp->spq_left and towards the memory */
1837         smp_mb__after_atomic_inc();
1838
1839         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1840
1841         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1842             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1843                 /* if Q update ramrod is completed for last Q in AFEX vif set
1844                  * flow, then ACK MCP at the end
1845                  *
1846                  * mark pending ACK to MCP bit.
1847                  * prevent case that both bits are cleared.
1848                  * At the end of load/unload driver checks that
1849                  * sp_state is cleared, and this order prevents
1850                  * races
1851                  */
1852                 smp_mb__before_clear_bit();
1853                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1854                 wmb();
1855                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1856                 smp_mb__after_clear_bit();
1857
1858                 /* schedule the sp task as mcp ack is required */
1859                 bnx2x_schedule_sp_task(bp);
1860         }
1861
1862         return;
1863 }
1864
1865 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1866 {
1867         struct bnx2x *bp = netdev_priv(dev_instance);
1868         u16 status = bnx2x_ack_int(bp);
1869         u16 mask;
1870         int i;
1871         u8 cos;
1872
1873         /* Return here if interrupt is shared and it's not for us */
1874         if (unlikely(status == 0)) {
1875                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1876                 return IRQ_NONE;
1877         }
1878         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1879
1880 #ifdef BNX2X_STOP_ON_ERROR
1881         if (unlikely(bp->panic))
1882                 return IRQ_HANDLED;
1883 #endif
1884
1885         for_each_eth_queue(bp, i) {
1886                 struct bnx2x_fastpath *fp = &bp->fp[i];
1887
1888                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1889                 if (status & mask) {
1890                         /* Handle Rx or Tx according to SB id */
1891                         for_each_cos_in_tx_queue(fp, cos)
1892                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1893                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1894                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1895                         status &= ~mask;
1896                 }
1897         }
1898
1899         if (CNIC_SUPPORT(bp)) {
1900                 mask = 0x2;
1901                 if (status & (mask | 0x1)) {
1902                         struct cnic_ops *c_ops = NULL;
1903
1904                         rcu_read_lock();
1905                         c_ops = rcu_dereference(bp->cnic_ops);
1906                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1907                                       CNIC_DRV_STATE_HANDLES_IRQ))
1908                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1909                         rcu_read_unlock();
1910
1911                         status &= ~mask;
1912                 }
1913         }
1914
1915         if (unlikely(status & 0x1)) {
1916
1917                 /* schedule sp task to perform default status block work, ack
1918                  * attentions and enable interrupts.
1919                  */
1920                 bnx2x_schedule_sp_task(bp);
1921
1922                 status &= ~0x1;
1923                 if (!status)
1924                         return IRQ_HANDLED;
1925         }
1926
1927         if (unlikely(status))
1928                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1929                    status);
1930
1931         return IRQ_HANDLED;
1932 }
1933
1934 /* Link */
1935
1936 /*
1937  * General service functions
1938  */
1939
1940 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1941 {
1942         u32 lock_status;
1943         u32 resource_bit = (1 << resource);
1944         int func = BP_FUNC(bp);
1945         u32 hw_lock_control_reg;
1946         int cnt;
1947
1948         /* Validating that the resource is within range */
1949         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1950                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1951                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1952                 return -EINVAL;
1953         }
1954
1955         if (func <= 5) {
1956                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1957         } else {
1958                 hw_lock_control_reg =
1959                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1960         }
1961
1962         /* Validating that the resource is not already taken */
1963         lock_status = REG_RD(bp, hw_lock_control_reg);
1964         if (lock_status & resource_bit) {
1965                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1966                    lock_status, resource_bit);
1967                 return -EEXIST;
1968         }
1969
1970         /* Try for 5 second every 5ms */
1971         for (cnt = 0; cnt < 1000; cnt++) {
1972                 /* Try to acquire the lock */
1973                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1974                 lock_status = REG_RD(bp, hw_lock_control_reg);
1975                 if (lock_status & resource_bit)
1976                         return 0;
1977
1978                 usleep_range(5000, 10000);
1979         }
1980         BNX2X_ERR("Timeout\n");
1981         return -EAGAIN;
1982 }
1983
1984 int bnx2x_release_leader_lock(struct bnx2x *bp)
1985 {
1986         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1987 }
1988
1989 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1990 {
1991         u32 lock_status;
1992         u32 resource_bit = (1 << resource);
1993         int func = BP_FUNC(bp);
1994         u32 hw_lock_control_reg;
1995
1996         /* Validating that the resource is within range */
1997         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1998                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1999                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2000                 return -EINVAL;
2001         }
2002
2003         if (func <= 5) {
2004                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2005         } else {
2006                 hw_lock_control_reg =
2007                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2008         }
2009
2010         /* Validating that the resource is currently taken */
2011         lock_status = REG_RD(bp, hw_lock_control_reg);
2012         if (!(lock_status & resource_bit)) {
2013                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2014                           lock_status, resource_bit);
2015                 return -EFAULT;
2016         }
2017
2018         REG_WR(bp, hw_lock_control_reg, resource_bit);
2019         return 0;
2020 }
2021
2022 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2023 {
2024         /* The GPIO should be swapped if swap register is set and active */
2025         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2026                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2027         int gpio_shift = gpio_num +
2028                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2029         u32 gpio_mask = (1 << gpio_shift);
2030         u32 gpio_reg;
2031         int value;
2032
2033         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2034                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2035                 return -EINVAL;
2036         }
2037
2038         /* read GPIO value */
2039         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2040
2041         /* get the requested pin value */
2042         if ((gpio_reg & gpio_mask) == gpio_mask)
2043                 value = 1;
2044         else
2045                 value = 0;
2046
2047         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2048
2049         return value;
2050 }
2051
2052 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2053 {
2054         /* The GPIO should be swapped if swap register is set and active */
2055         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2056                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2057         int gpio_shift = gpio_num +
2058                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2059         u32 gpio_mask = (1 << gpio_shift);
2060         u32 gpio_reg;
2061
2062         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2063                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2064                 return -EINVAL;
2065         }
2066
2067         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2068         /* read GPIO and mask except the float bits */
2069         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2070
2071         switch (mode) {
2072         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2073                 DP(NETIF_MSG_LINK,
2074                    "Set GPIO %d (shift %d) -> output low\n",
2075                    gpio_num, gpio_shift);
2076                 /* clear FLOAT and set CLR */
2077                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2078                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2079                 break;
2080
2081         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2082                 DP(NETIF_MSG_LINK,
2083                    "Set GPIO %d (shift %d) -> output high\n",
2084                    gpio_num, gpio_shift);
2085                 /* clear FLOAT and set SET */
2086                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2087                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2088                 break;
2089
2090         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2091                 DP(NETIF_MSG_LINK,
2092                    "Set GPIO %d (shift %d) -> input\n",
2093                    gpio_num, gpio_shift);
2094                 /* set FLOAT */
2095                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2096                 break;
2097
2098         default:
2099                 break;
2100         }
2101
2102         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2103         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2104
2105         return 0;
2106 }
2107
2108 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2109 {
2110         u32 gpio_reg = 0;
2111         int rc = 0;
2112
2113         /* Any port swapping should be handled by caller. */
2114
2115         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2116         /* read GPIO and mask except the float bits */
2117         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2118         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2119         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2120         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2121
2122         switch (mode) {
2123         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2124                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2125                 /* set CLR */
2126                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2127                 break;
2128
2129         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2130                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2131                 /* set SET */
2132                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2133                 break;
2134
2135         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2136                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2137                 /* set FLOAT */
2138                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2139                 break;
2140
2141         default:
2142                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2143                 rc = -EINVAL;
2144                 break;
2145         }
2146
2147         if (rc == 0)
2148                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2149
2150         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2151
2152         return rc;
2153 }
2154
2155 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2156 {
2157         /* The GPIO should be swapped if swap register is set and active */
2158         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2159                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2160         int gpio_shift = gpio_num +
2161                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2162         u32 gpio_mask = (1 << gpio_shift);
2163         u32 gpio_reg;
2164
2165         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2166                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2167                 return -EINVAL;
2168         }
2169
2170         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2171         /* read GPIO int */
2172         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2173
2174         switch (mode) {
2175         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2176                 DP(NETIF_MSG_LINK,
2177                    "Clear GPIO INT %d (shift %d) -> output low\n",
2178                    gpio_num, gpio_shift);
2179                 /* clear SET and set CLR */
2180                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2181                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2182                 break;
2183
2184         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2185                 DP(NETIF_MSG_LINK,
2186                    "Set GPIO INT %d (shift %d) -> output high\n",
2187                    gpio_num, gpio_shift);
2188                 /* clear CLR and set SET */
2189                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2190                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2191                 break;
2192
2193         default:
2194                 break;
2195         }
2196
2197         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2198         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2199
2200         return 0;
2201 }
2202
2203 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2204 {
2205         u32 spio_reg;
2206
2207         /* Only 2 SPIOs are configurable */
2208         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2209                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2210                 return -EINVAL;
2211         }
2212
2213         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2214         /* read SPIO and mask except the float bits */
2215         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2216
2217         switch (mode) {
2218         case MISC_SPIO_OUTPUT_LOW:
2219                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2220                 /* clear FLOAT and set CLR */
2221                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2222                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2223                 break;
2224
2225         case MISC_SPIO_OUTPUT_HIGH:
2226                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2227                 /* clear FLOAT and set SET */
2228                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2229                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2230                 break;
2231
2232         case MISC_SPIO_INPUT_HI_Z:
2233                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2234                 /* set FLOAT */
2235                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2236                 break;
2237
2238         default:
2239                 break;
2240         }
2241
2242         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2243         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2244
2245         return 0;
2246 }
2247
2248 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2249 {
2250         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2251         switch (bp->link_vars.ieee_fc &
2252                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2253         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2254                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2255                                                    ADVERTISED_Pause);
2256                 break;
2257
2258         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2259                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2260                                                   ADVERTISED_Pause);
2261                 break;
2262
2263         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2264                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2265                 break;
2266
2267         default:
2268                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2269                                                    ADVERTISED_Pause);
2270                 break;
2271         }
2272 }
2273
2274 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2275 {
2276         /* Initialize link parameters structure variables
2277          * It is recommended to turn off RX FC for jumbo frames
2278          *  for better performance
2279          */
2280         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2281                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2282         else
2283                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2284 }
2285
2286 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2287 {
2288         u32 pause_enabled = 0;
2289
2290         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2291                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2292                         pause_enabled = 1;
2293
2294                 REG_WR(bp, BAR_USTRORM_INTMEM +
2295                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2296                        pause_enabled);
2297         }
2298
2299         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2300            pause_enabled ? "enabled" : "disabled");
2301 }
2302
2303 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2304 {
2305         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2306         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2307
2308         if (!BP_NOMCP(bp)) {
2309                 bnx2x_set_requested_fc(bp);
2310                 bnx2x_acquire_phy_lock(bp);
2311
2312                 if (load_mode == LOAD_DIAG) {
2313                         struct link_params *lp = &bp->link_params;
2314                         lp->loopback_mode = LOOPBACK_XGXS;
2315                         /* do PHY loopback at 10G speed, if possible */
2316                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2317                                 if (lp->speed_cap_mask[cfx_idx] &
2318                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2319                                         lp->req_line_speed[cfx_idx] =
2320                                         SPEED_10000;
2321                                 else
2322                                         lp->req_line_speed[cfx_idx] =
2323                                         SPEED_1000;
2324                         }
2325                 }
2326
2327                 if (load_mode == LOAD_LOOPBACK_EXT) {
2328                         struct link_params *lp = &bp->link_params;
2329                         lp->loopback_mode = LOOPBACK_EXT;
2330                 }
2331
2332                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2333
2334                 bnx2x_release_phy_lock(bp);
2335
2336                 bnx2x_init_dropless_fc(bp);
2337
2338                 bnx2x_calc_fc_adv(bp);
2339
2340                 if (bp->link_vars.link_up) {
2341                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2342                         bnx2x_link_report(bp);
2343                 }
2344                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2345                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2346                 return rc;
2347         }
2348         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2349         return -EINVAL;
2350 }
2351
2352 void bnx2x_link_set(struct bnx2x *bp)
2353 {
2354         if (!BP_NOMCP(bp)) {
2355                 bnx2x_acquire_phy_lock(bp);
2356                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2357                 bnx2x_release_phy_lock(bp);
2358
2359                 bnx2x_init_dropless_fc(bp);
2360
2361                 bnx2x_calc_fc_adv(bp);
2362         } else
2363                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2364 }
2365
2366 static void bnx2x__link_reset(struct bnx2x *bp)
2367 {
2368         if (!BP_NOMCP(bp)) {
2369                 bnx2x_acquire_phy_lock(bp);
2370                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2371                 bnx2x_release_phy_lock(bp);
2372         } else
2373                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2374 }
2375
2376 void bnx2x_force_link_reset(struct bnx2x *bp)
2377 {
2378         bnx2x_acquire_phy_lock(bp);
2379         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2380         bnx2x_release_phy_lock(bp);
2381 }
2382
2383 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2384 {
2385         u8 rc = 0;
2386
2387         if (!BP_NOMCP(bp)) {
2388                 bnx2x_acquire_phy_lock(bp);
2389                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2390                                      is_serdes);
2391                 bnx2x_release_phy_lock(bp);
2392         } else
2393                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2394
2395         return rc;
2396 }
2397
2398 /* Calculates the sum of vn_min_rates.
2399    It's needed for further normalizing of the min_rates.
2400    Returns:
2401      sum of vn_min_rates.
2402        or
2403      0 - if all the min_rates are 0.
2404      In the later case fairness algorithm should be deactivated.
2405      If not all min_rates are zero then those that are zeroes will be set to 1.
2406  */
2407 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2408                                       struct cmng_init_input *input)
2409 {
2410         int all_zero = 1;
2411         int vn;
2412
2413         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2414                 u32 vn_cfg = bp->mf_config[vn];
2415                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2416                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2417
2418                 /* Skip hidden vns */
2419                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2420                         vn_min_rate = 0;
2421                 /* If min rate is zero - set it to 1 */
2422                 else if (!vn_min_rate)
2423                         vn_min_rate = DEF_MIN_RATE;
2424                 else
2425                         all_zero = 0;
2426
2427                 input->vnic_min_rate[vn] = vn_min_rate;
2428         }
2429
2430         /* if ETS or all min rates are zeros - disable fairness */
2431         if (BNX2X_IS_ETS_ENABLED(bp)) {
2432                 input->flags.cmng_enables &=
2433                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2434                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2435         } else if (all_zero) {
2436                 input->flags.cmng_enables &=
2437                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2438                 DP(NETIF_MSG_IFUP,
2439                    "All MIN values are zeroes fairness will be disabled\n");
2440         } else
2441                 input->flags.cmng_enables |=
2442                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2443 }
2444
2445 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2446                                     struct cmng_init_input *input)
2447 {
2448         u16 vn_max_rate;
2449         u32 vn_cfg = bp->mf_config[vn];
2450
2451         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2452                 vn_max_rate = 0;
2453         else {
2454                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2455
2456                 if (IS_MF_SI(bp)) {
2457                         /* maxCfg in percents of linkspeed */
2458                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2459                 } else /* SD modes */
2460                         /* maxCfg is absolute in 100Mb units */
2461                         vn_max_rate = maxCfg * 100;
2462         }
2463
2464         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2465
2466         input->vnic_max_rate[vn] = vn_max_rate;
2467 }
2468
2469 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2470 {
2471         if (CHIP_REV_IS_SLOW(bp))
2472                 return CMNG_FNS_NONE;
2473         if (IS_MF(bp))
2474                 return CMNG_FNS_MINMAX;
2475
2476         return CMNG_FNS_NONE;
2477 }
2478
2479 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2480 {
2481         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2482
2483         if (BP_NOMCP(bp))
2484                 return; /* what should be the default value in this case */
2485
2486         /* For 2 port configuration the absolute function number formula
2487          * is:
2488          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2489          *
2490          *      and there are 4 functions per port
2491          *
2492          * For 4 port configuration it is
2493          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2494          *
2495          *      and there are 2 functions per port
2496          */
2497         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2498                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2499
2500                 if (func >= E1H_FUNC_MAX)
2501                         break;
2502
2503                 bp->mf_config[vn] =
2504                         MF_CFG_RD(bp, func_mf_config[func].config);
2505         }
2506         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2507                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2508                 bp->flags |= MF_FUNC_DIS;
2509         } else {
2510                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2511                 bp->flags &= ~MF_FUNC_DIS;
2512         }
2513 }
2514
2515 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2516 {
2517         struct cmng_init_input input;
2518         memset(&input, 0, sizeof(struct cmng_init_input));
2519
2520         input.port_rate = bp->link_vars.line_speed;
2521
2522         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2523                 int vn;
2524
2525                 /* read mf conf from shmem */
2526                 if (read_cfg)
2527                         bnx2x_read_mf_cfg(bp);
2528
2529                 /* vn_weight_sum and enable fairness if not 0 */
2530                 bnx2x_calc_vn_min(bp, &input);
2531
2532                 /* calculate and set min-max rate for each vn */
2533                 if (bp->port.pmf)
2534                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2535                                 bnx2x_calc_vn_max(bp, vn, &input);
2536
2537                 /* always enable rate shaping and fairness */
2538                 input.flags.cmng_enables |=
2539                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2540
2541                 bnx2x_init_cmng(&input, &bp->cmng);
2542                 return;
2543         }
2544
2545         /* rate shaping and fairness are disabled */
2546         DP(NETIF_MSG_IFUP,
2547            "rate shaping and fairness are disabled\n");
2548 }
2549
2550 static void storm_memset_cmng(struct bnx2x *bp,
2551                               struct cmng_init *cmng,
2552                               u8 port)
2553 {
2554         int vn;
2555         size_t size = sizeof(struct cmng_struct_per_port);
2556
2557         u32 addr = BAR_XSTRORM_INTMEM +
2558                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2559
2560         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2561
2562         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2563                 int func = func_by_vn(bp, vn);
2564
2565                 addr = BAR_XSTRORM_INTMEM +
2566                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2567                 size = sizeof(struct rate_shaping_vars_per_vn);
2568                 __storm_memset_struct(bp, addr, size,
2569                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2570
2571                 addr = BAR_XSTRORM_INTMEM +
2572                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2573                 size = sizeof(struct fairness_vars_per_vn);
2574                 __storm_memset_struct(bp, addr, size,
2575                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2576         }
2577 }
2578
2579 /* init cmng mode in HW according to local configuration */
2580 void bnx2x_set_local_cmng(struct bnx2x *bp)
2581 {
2582         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2583
2584         if (cmng_fns != CMNG_FNS_NONE) {
2585                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2586                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2587         } else {
2588                 /* rate shaping and fairness are disabled */
2589                 DP(NETIF_MSG_IFUP,
2590                    "single function mode without fairness\n");
2591         }
2592 }
2593
2594 /* This function is called upon link interrupt */
2595 static void bnx2x_link_attn(struct bnx2x *bp)
2596 {
2597         /* Make sure that we are synced with the current statistics */
2598         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2599
2600         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2601
2602         bnx2x_init_dropless_fc(bp);
2603
2604         if (bp->link_vars.link_up) {
2605
2606                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2607                         struct host_port_stats *pstats;
2608
2609                         pstats = bnx2x_sp(bp, port_stats);
2610                         /* reset old mac stats */
2611                         memset(&(pstats->mac_stx[0]), 0,
2612                                sizeof(struct mac_stx));
2613                 }
2614                 if (bp->state == BNX2X_STATE_OPEN)
2615                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2616         }
2617
2618         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2619                 bnx2x_set_local_cmng(bp);
2620
2621         __bnx2x_link_report(bp);
2622
2623         if (IS_MF(bp))
2624                 bnx2x_link_sync_notify(bp);
2625 }
2626
2627 void bnx2x__link_status_update(struct bnx2x *bp)
2628 {
2629         if (bp->state != BNX2X_STATE_OPEN)
2630                 return;
2631
2632         /* read updated dcb configuration */
2633         if (IS_PF(bp)) {
2634                 bnx2x_dcbx_pmf_update(bp);
2635                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2636                 if (bp->link_vars.link_up)
2637                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2638                 else
2639                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2640                         /* indicate link status */
2641                 bnx2x_link_report(bp);
2642
2643         } else { /* VF */
2644                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2645                                           SUPPORTED_10baseT_Full |
2646                                           SUPPORTED_100baseT_Half |
2647                                           SUPPORTED_100baseT_Full |
2648                                           SUPPORTED_1000baseT_Full |
2649                                           SUPPORTED_2500baseX_Full |
2650                                           SUPPORTED_10000baseT_Full |
2651                                           SUPPORTED_TP |
2652                                           SUPPORTED_FIBRE |
2653                                           SUPPORTED_Autoneg |
2654                                           SUPPORTED_Pause |
2655                                           SUPPORTED_Asym_Pause);
2656                 bp->port.advertising[0] = bp->port.supported[0];
2657
2658                 bp->link_params.bp = bp;
2659                 bp->link_params.port = BP_PORT(bp);
2660                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2661                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2662                 bp->link_params.req_line_speed[0] = SPEED_10000;
2663                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2664                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2665                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2666                 bp->link_vars.line_speed = SPEED_10000;
2667                 bp->link_vars.link_status =
2668                         (LINK_STATUS_LINK_UP |
2669                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2670                 bp->link_vars.link_up = 1;
2671                 bp->link_vars.duplex = DUPLEX_FULL;
2672                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2673                 __bnx2x_link_report(bp);
2674                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2675         }
2676 }
2677
2678 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2679                                   u16 vlan_val, u8 allowed_prio)
2680 {
2681         struct bnx2x_func_state_params func_params = {NULL};
2682         struct bnx2x_func_afex_update_params *f_update_params =
2683                 &func_params.params.afex_update;
2684
2685         func_params.f_obj = &bp->func_obj;
2686         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2687
2688         /* no need to wait for RAMROD completion, so don't
2689          * set RAMROD_COMP_WAIT flag
2690          */
2691
2692         f_update_params->vif_id = vifid;
2693         f_update_params->afex_default_vlan = vlan_val;
2694         f_update_params->allowed_priorities = allowed_prio;
2695
2696         /* if ramrod can not be sent, response to MCP immediately */
2697         if (bnx2x_func_state_change(bp, &func_params) < 0)
2698                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2699
2700         return 0;
2701 }
2702
2703 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2704                                           u16 vif_index, u8 func_bit_map)
2705 {
2706         struct bnx2x_func_state_params func_params = {NULL};
2707         struct bnx2x_func_afex_viflists_params *update_params =
2708                 &func_params.params.afex_viflists;
2709         int rc;
2710         u32 drv_msg_code;
2711
2712         /* validate only LIST_SET and LIST_GET are received from switch */
2713         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2714                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2715                           cmd_type);
2716
2717         func_params.f_obj = &bp->func_obj;
2718         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2719
2720         /* set parameters according to cmd_type */
2721         update_params->afex_vif_list_command = cmd_type;
2722         update_params->vif_list_index = vif_index;
2723         update_params->func_bit_map =
2724                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2725         update_params->func_to_clear = 0;
2726         drv_msg_code =
2727                 (cmd_type == VIF_LIST_RULE_GET) ?
2728                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2729                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2730
2731         /* if ramrod can not be sent, respond to MCP immediately for
2732          * SET and GET requests (other are not triggered from MCP)
2733          */
2734         rc = bnx2x_func_state_change(bp, &func_params);
2735         if (rc < 0)
2736                 bnx2x_fw_command(bp, drv_msg_code, 0);
2737
2738         return 0;
2739 }
2740
2741 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2742 {
2743         struct afex_stats afex_stats;
2744         u32 func = BP_ABS_FUNC(bp);
2745         u32 mf_config;
2746         u16 vlan_val;
2747         u32 vlan_prio;
2748         u16 vif_id;
2749         u8 allowed_prio;
2750         u8 vlan_mode;
2751         u32 addr_to_write, vifid, addrs, stats_type, i;
2752
2753         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2754                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2755                 DP(BNX2X_MSG_MCP,
2756                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2757                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2758         }
2759
2760         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2761                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2762                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2763                 DP(BNX2X_MSG_MCP,
2764                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2765                    vifid, addrs);
2766                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2767                                                addrs);
2768         }
2769
2770         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2771                 addr_to_write = SHMEM2_RD(bp,
2772                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2773                 stats_type = SHMEM2_RD(bp,
2774                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2775
2776                 DP(BNX2X_MSG_MCP,
2777                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2778                    addr_to_write);
2779
2780                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2781
2782                 /* write response to scratchpad, for MCP */
2783                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2784                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2785                                *(((u32 *)(&afex_stats))+i));
2786
2787                 /* send ack message to MCP */
2788                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2789         }
2790
2791         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2792                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2793                 bp->mf_config[BP_VN(bp)] = mf_config;
2794                 DP(BNX2X_MSG_MCP,
2795                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2796                    mf_config);
2797
2798                 /* if VIF_SET is "enabled" */
2799                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2800                         /* set rate limit directly to internal RAM */
2801                         struct cmng_init_input cmng_input;
2802                         struct rate_shaping_vars_per_vn m_rs_vn;
2803                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2804                         u32 addr = BAR_XSTRORM_INTMEM +
2805                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2806
2807                         bp->mf_config[BP_VN(bp)] = mf_config;
2808
2809                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2810                         m_rs_vn.vn_counter.rate =
2811                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2812                         m_rs_vn.vn_counter.quota =
2813                                 (m_rs_vn.vn_counter.rate *
2814                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2815
2816                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2817
2818                         /* read relevant values from mf_cfg struct in shmem */
2819                         vif_id =
2820                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2821                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2822                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2823                         vlan_val =
2824                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2825                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2826                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2827                         vlan_prio = (mf_config &
2828                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2829                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2830                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2831                         vlan_mode =
2832                                 (MF_CFG_RD(bp,
2833                                            func_mf_config[func].afex_config) &
2834                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2835                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2836                         allowed_prio =
2837                                 (MF_CFG_RD(bp,
2838                                            func_mf_config[func].afex_config) &
2839                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2840                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2841
2842                         /* send ramrod to FW, return in case of failure */
2843                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2844                                                    allowed_prio))
2845                                 return;
2846
2847                         bp->afex_def_vlan_tag = vlan_val;
2848                         bp->afex_vlan_mode = vlan_mode;
2849                 } else {
2850                         /* notify link down because BP->flags is disabled */
2851                         bnx2x_link_report(bp);
2852
2853                         /* send INVALID VIF ramrod to FW */
2854                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2855
2856                         /* Reset the default afex VLAN */
2857                         bp->afex_def_vlan_tag = -1;
2858                 }
2859         }
2860 }
2861
2862 static void bnx2x_pmf_update(struct bnx2x *bp)
2863 {
2864         int port = BP_PORT(bp);
2865         u32 val;
2866
2867         bp->port.pmf = 1;
2868         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2869
2870         /*
2871          * We need the mb() to ensure the ordering between the writing to
2872          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2873          */
2874         smp_mb();
2875
2876         /* queue a periodic task */
2877         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2878
2879         bnx2x_dcbx_pmf_update(bp);
2880
2881         /* enable nig attention */
2882         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2883         if (bp->common.int_block == INT_BLOCK_HC) {
2884                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2885                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2886         } else if (!CHIP_IS_E1x(bp)) {
2887                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2888                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2889         }
2890
2891         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2892 }
2893
2894 /* end of Link */
2895
2896 /* slow path */
2897
2898 /*
2899  * General service functions
2900  */
2901
2902 /* send the MCP a request, block until there is a reply */
2903 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2904 {
2905         int mb_idx = BP_FW_MB_IDX(bp);
2906         u32 seq;
2907         u32 rc = 0;
2908         u32 cnt = 1;
2909         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2910
2911         mutex_lock(&bp->fw_mb_mutex);
2912         seq = ++bp->fw_seq;
2913         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2914         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2915
2916         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2917                         (command | seq), param);
2918
2919         do {
2920                 /* let the FW do it's magic ... */
2921                 msleep(delay);
2922
2923                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2924
2925                 /* Give the FW up to 5 second (500*10ms) */
2926         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2927
2928         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2929            cnt*delay, rc, seq);
2930
2931         /* is this a reply to our command? */
2932         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2933                 rc &= FW_MSG_CODE_MASK;
2934         else {
2935                 /* FW BUG! */
2936                 BNX2X_ERR("FW failed to respond!\n");
2937                 bnx2x_fw_dump(bp);
2938                 rc = 0;
2939         }
2940         mutex_unlock(&bp->fw_mb_mutex);
2941
2942         return rc;
2943 }
2944
2945 static void storm_memset_func_cfg(struct bnx2x *bp,
2946                                  struct tstorm_eth_function_common_config *tcfg,
2947                                  u16 abs_fid)
2948 {
2949         size_t size = sizeof(struct tstorm_eth_function_common_config);
2950
2951         u32 addr = BAR_TSTRORM_INTMEM +
2952                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2953
2954         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2955 }
2956
2957 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2958 {
2959         if (CHIP_IS_E1x(bp)) {
2960                 struct tstorm_eth_function_common_config tcfg = {0};
2961
2962                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2963         }
2964
2965         /* Enable the function in the FW */
2966         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2967         storm_memset_func_en(bp, p->func_id, 1);
2968
2969         /* spq */
2970         if (p->func_flgs & FUNC_FLG_SPQ) {
2971                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2972                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2973                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2974         }
2975 }
2976
2977 /**
2978  * bnx2x_get_common_flags - Return common flags
2979  *
2980  * @bp          device handle
2981  * @fp          queue handle
2982  * @zero_stats  TRUE if statistics zeroing is needed
2983  *
2984  * Return the flags that are common for the Tx-only and not normal connections.
2985  */
2986 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2987                                             struct bnx2x_fastpath *fp,
2988                                             bool zero_stats)
2989 {
2990         unsigned long flags = 0;
2991
2992         /* PF driver will always initialize the Queue to an ACTIVE state */
2993         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2994
2995         /* tx only connections collect statistics (on the same index as the
2996          * parent connection). The statistics are zeroed when the parent
2997          * connection is initialized.
2998          */
2999
3000         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3001         if (zero_stats)
3002                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3003
3004         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3005         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3006
3007 #ifdef BNX2X_STOP_ON_ERROR
3008         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3009 #endif
3010
3011         return flags;
3012 }
3013
3014 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3015                                        struct bnx2x_fastpath *fp,
3016                                        bool leading)
3017 {
3018         unsigned long flags = 0;
3019
3020         /* calculate other queue flags */
3021         if (IS_MF_SD(bp))
3022                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3023
3024         if (IS_FCOE_FP(fp)) {
3025                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3026                 /* For FCoE - force usage of default priority (for afex) */
3027                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3028         }
3029
3030         if (!fp->disable_tpa) {
3031                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3032                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3033                 if (fp->mode == TPA_MODE_GRO)
3034                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3035         }
3036
3037         if (leading) {
3038                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3039                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3040         }
3041
3042         /* Always set HW VLAN stripping */
3043         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3044
3045         /* configure silent vlan removal */
3046         if (IS_MF_AFEX(bp))
3047                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3048
3049         return flags | bnx2x_get_common_flags(bp, fp, true);
3050 }
3051
3052 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3053         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3054         u8 cos)
3055 {
3056         gen_init->stat_id = bnx2x_stats_id(fp);
3057         gen_init->spcl_id = fp->cl_id;
3058
3059         /* Always use mini-jumbo MTU for FCoE L2 ring */
3060         if (IS_FCOE_FP(fp))
3061                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3062         else
3063                 gen_init->mtu = bp->dev->mtu;
3064
3065         gen_init->cos = cos;
3066 }
3067
3068 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3069         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3070         struct bnx2x_rxq_setup_params *rxq_init)
3071 {
3072         u8 max_sge = 0;
3073         u16 sge_sz = 0;
3074         u16 tpa_agg_size = 0;
3075
3076         if (!fp->disable_tpa) {
3077                 pause->sge_th_lo = SGE_TH_LO(bp);
3078                 pause->sge_th_hi = SGE_TH_HI(bp);
3079
3080                 /* validate SGE ring has enough to cross high threshold */
3081                 WARN_ON(bp->dropless_fc &&
3082                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3083                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3084
3085                 tpa_agg_size = TPA_AGG_SIZE;
3086                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3087                         SGE_PAGE_SHIFT;
3088                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3089                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3090                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3091         }
3092
3093         /* pause - not for e1 */
3094         if (!CHIP_IS_E1(bp)) {
3095                 pause->bd_th_lo = BD_TH_LO(bp);
3096                 pause->bd_th_hi = BD_TH_HI(bp);
3097
3098                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3099                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3100                 /*
3101                  * validate that rings have enough entries to cross
3102                  * high thresholds
3103                  */
3104                 WARN_ON(bp->dropless_fc &&
3105                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3106                                 bp->rx_ring_size);
3107                 WARN_ON(bp->dropless_fc &&
3108                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3109                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3110
3111                 pause->pri_map = 1;
3112         }
3113
3114         /* rxq setup */
3115         rxq_init->dscr_map = fp->rx_desc_mapping;
3116         rxq_init->sge_map = fp->rx_sge_mapping;
3117         rxq_init->rcq_map = fp->rx_comp_mapping;
3118         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3119
3120         /* This should be a maximum number of data bytes that may be
3121          * placed on the BD (not including paddings).
3122          */
3123         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3124                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3125
3126         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3127         rxq_init->tpa_agg_sz = tpa_agg_size;
3128         rxq_init->sge_buf_sz = sge_sz;
3129         rxq_init->max_sges_pkt = max_sge;
3130         rxq_init->rss_engine_id = BP_FUNC(bp);
3131         rxq_init->mcast_engine_id = BP_FUNC(bp);
3132
3133         /* Maximum number or simultaneous TPA aggregation for this Queue.
3134          *
3135          * For PF Clients it should be the maximum available number.
3136          * VF driver(s) may want to define it to a smaller value.
3137          */
3138         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3139
3140         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3141         rxq_init->fw_sb_id = fp->fw_sb_id;
3142
3143         if (IS_FCOE_FP(fp))
3144                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3145         else
3146                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3147         /* configure silent vlan removal
3148          * if multi function mode is afex, then mask default vlan
3149          */
3150         if (IS_MF_AFEX(bp)) {
3151                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3152                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3153         }
3154 }
3155
3156 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3157         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3158         u8 cos)
3159 {
3160         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3161         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3162         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3163         txq_init->fw_sb_id = fp->fw_sb_id;
3164
3165         /*
3166          * set the tss leading client id for TX classification ==
3167          * leading RSS client id
3168          */
3169         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3170
3171         if (IS_FCOE_FP(fp)) {
3172                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3173                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3174         }
3175 }
3176
3177 static void bnx2x_pf_init(struct bnx2x *bp)
3178 {
3179         struct bnx2x_func_init_params func_init = {0};
3180         struct event_ring_data eq_data = { {0} };
3181         u16 flags;
3182
3183         if (!CHIP_IS_E1x(bp)) {
3184                 /* reset IGU PF statistics: MSIX + ATTN */
3185                 /* PF */
3186                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3187                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3188                            (CHIP_MODE_IS_4_PORT(bp) ?
3189                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3190                 /* ATTN */
3191                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3192                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3193                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3194                            (CHIP_MODE_IS_4_PORT(bp) ?
3195                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3196         }
3197
3198         /* function setup flags */
3199         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3200
3201         /* This flag is relevant for E1x only.
3202          * E2 doesn't have a TPA configuration in a function level.
3203          */
3204         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3205
3206         func_init.func_flgs = flags;
3207         func_init.pf_id = BP_FUNC(bp);
3208         func_init.func_id = BP_FUNC(bp);
3209         func_init.spq_map = bp->spq_mapping;
3210         func_init.spq_prod = bp->spq_prod_idx;
3211
3212         bnx2x_func_init(bp, &func_init);
3213
3214         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3215
3216         /*
3217          * Congestion management values depend on the link rate
3218          * There is no active link so initial link rate is set to 10 Gbps.
3219          * When the link comes up The congestion management values are
3220          * re-calculated according to the actual link rate.
3221          */
3222         bp->link_vars.line_speed = SPEED_10000;
3223         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3224
3225         /* Only the PMF sets the HW */
3226         if (bp->port.pmf)
3227                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3228
3229         /* init Event Queue - PCI bus guarantees correct endianity*/
3230         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3231         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3232         eq_data.producer = bp->eq_prod;
3233         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3234         eq_data.sb_id = DEF_SB_ID;
3235         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3236 }
3237
3238 static void bnx2x_e1h_disable(struct bnx2x *bp)
3239 {
3240         int port = BP_PORT(bp);
3241
3242         bnx2x_tx_disable(bp);
3243
3244         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3245 }
3246
3247 static void bnx2x_e1h_enable(struct bnx2x *bp)
3248 {
3249         int port = BP_PORT(bp);
3250
3251         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3252
3253         /* Tx queue should be only re-enabled */
3254         netif_tx_wake_all_queues(bp->dev);
3255
3256         /*
3257          * Should not call netif_carrier_on since it will be called if the link
3258          * is up when checking for link state
3259          */
3260 }
3261
3262 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3263
3264 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3265 {
3266         struct eth_stats_info *ether_stat =
3267                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3268         struct bnx2x_vlan_mac_obj *mac_obj =
3269                 &bp->sp_objs->mac_obj;
3270         int i;
3271
3272         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3273                 ETH_STAT_INFO_VERSION_LEN);
3274
3275         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3276          * mac_local field in ether_stat struct. The base address is offset by 2
3277          * bytes to account for the field being 8 bytes but a mac address is
3278          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3279          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3280          * allocated by the ether_stat struct, so the macs will land in their
3281          * proper positions.
3282          */
3283         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3284                 memset(ether_stat->mac_local + i, 0,
3285                        sizeof(ether_stat->mac_local[0]));
3286         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3287                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3288                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3289                                 ETH_ALEN);
3290         ether_stat->mtu_size = bp->dev->mtu;
3291         if (bp->dev->features & NETIF_F_RXCSUM)
3292                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3293         if (bp->dev->features & NETIF_F_TSO)
3294                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3295         ether_stat->feature_flags |= bp->common.boot_mode;
3296
3297         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3298
3299         ether_stat->txq_size = bp->tx_ring_size;
3300         ether_stat->rxq_size = bp->rx_ring_size;
3301
3302 #ifdef CONFIG_BNX2X_SRIOV
3303         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3304 #endif
3305 }
3306
3307 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3308 {
3309         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3310         struct fcoe_stats_info *fcoe_stat =
3311                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3312
3313         if (!CNIC_LOADED(bp))
3314                 return;
3315
3316         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3317
3318         fcoe_stat->qos_priority =
3319                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3320
3321         /* insert FCoE stats from ramrod response */
3322         if (!NO_FCOE(bp)) {
3323                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3324                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3325                         tstorm_queue_statistics;
3326
3327                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3328                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3329                         xstorm_queue_statistics;
3330
3331                 struct fcoe_statistics_params *fw_fcoe_stat =
3332                         &bp->fw_stats_data->fcoe;
3333
3334                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3335                           fcoe_stat->rx_bytes_lo,
3336                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3337
3338                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3339                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3340                           fcoe_stat->rx_bytes_lo,
3341                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3342
3343                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3344                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3345                           fcoe_stat->rx_bytes_lo,
3346                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3347
3348                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3349                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3350                           fcoe_stat->rx_bytes_lo,
3351                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3352
3353                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3354                           fcoe_stat->rx_frames_lo,
3355                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3356
3357                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3358                           fcoe_stat->rx_frames_lo,
3359                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3360
3361                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3362                           fcoe_stat->rx_frames_lo,
3363                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3364
3365                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3366                           fcoe_stat->rx_frames_lo,
3367                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3368
3369                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3370                           fcoe_stat->tx_bytes_lo,
3371                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3372
3373                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3374                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3375                           fcoe_stat->tx_bytes_lo,
3376                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3377
3378                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3379                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3380                           fcoe_stat->tx_bytes_lo,
3381                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3382
3383                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3384                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3385                           fcoe_stat->tx_bytes_lo,
3386                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3387
3388                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3389                           fcoe_stat->tx_frames_lo,
3390                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3391
3392                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3393                           fcoe_stat->tx_frames_lo,
3394                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3395
3396                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3397                           fcoe_stat->tx_frames_lo,
3398                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3399
3400                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3401                           fcoe_stat->tx_frames_lo,
3402                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3403         }
3404
3405         /* ask L5 driver to add data to the struct */
3406         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3407 }
3408
3409 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3410 {
3411         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3412         struct iscsi_stats_info *iscsi_stat =
3413                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3414
3415         if (!CNIC_LOADED(bp))
3416                 return;
3417
3418         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3419                ETH_ALEN);
3420
3421         iscsi_stat->qos_priority =
3422                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3423
3424         /* ask L5 driver to add data to the struct */
3425         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3426 }
3427
3428 /* called due to MCP event (on pmf):
3429  *      reread new bandwidth configuration
3430  *      configure FW
3431  *      notify others function about the change
3432  */
3433 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3434 {
3435         if (bp->link_vars.link_up) {
3436                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3437                 bnx2x_link_sync_notify(bp);
3438         }
3439         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3440 }
3441
3442 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3443 {
3444         bnx2x_config_mf_bw(bp);
3445         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3446 }
3447
3448 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3449 {
3450         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3451         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3452 }
3453
3454 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3455 {
3456         enum drv_info_opcode op_code;
3457         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3458
3459         /* if drv_info version supported by MFW doesn't match - send NACK */
3460         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3461                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3462                 return;
3463         }
3464
3465         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3466                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3467
3468         memset(&bp->slowpath->drv_info_to_mcp, 0,
3469                sizeof(union drv_info_to_mcp));
3470
3471         switch (op_code) {
3472         case ETH_STATS_OPCODE:
3473                 bnx2x_drv_info_ether_stat(bp);
3474                 break;
3475         case FCOE_STATS_OPCODE:
3476                 bnx2x_drv_info_fcoe_stat(bp);
3477                 break;
3478         case ISCSI_STATS_OPCODE:
3479                 bnx2x_drv_info_iscsi_stat(bp);
3480                 break;
3481         default:
3482                 /* if op code isn't supported - send NACK */
3483                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3484                 return;
3485         }
3486
3487         /* if we got drv_info attn from MFW then these fields are defined in
3488          * shmem2 for sure
3489          */
3490         SHMEM2_WR(bp, drv_info_host_addr_lo,
3491                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3492         SHMEM2_WR(bp, drv_info_host_addr_hi,
3493                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3494
3495         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3496 }
3497
3498 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3499 {
3500         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3501
3502         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3503
3504                 /*
3505                  * This is the only place besides the function initialization
3506                  * where the bp->flags can change so it is done without any
3507                  * locks
3508                  */
3509                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3510                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3511                         bp->flags |= MF_FUNC_DIS;
3512
3513                         bnx2x_e1h_disable(bp);
3514                 } else {
3515                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3516                         bp->flags &= ~MF_FUNC_DIS;
3517
3518                         bnx2x_e1h_enable(bp);
3519                 }
3520                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3521         }
3522         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3523                 bnx2x_config_mf_bw(bp);
3524                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3525         }
3526
3527         /* Report results to MCP */
3528         if (dcc_event)
3529                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3530         else
3531                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3532 }
3533
3534 /* must be called under the spq lock */
3535 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3536 {
3537         struct eth_spe *next_spe = bp->spq_prod_bd;
3538
3539         if (bp->spq_prod_bd == bp->spq_last_bd) {
3540                 bp->spq_prod_bd = bp->spq;
3541                 bp->spq_prod_idx = 0;
3542                 DP(BNX2X_MSG_SP, "end of spq\n");
3543         } else {
3544                 bp->spq_prod_bd++;
3545                 bp->spq_prod_idx++;
3546         }
3547         return next_spe;
3548 }
3549
3550 /* must be called under the spq lock */
3551 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3552 {
3553         int func = BP_FUNC(bp);
3554
3555         /*
3556          * Make sure that BD data is updated before writing the producer:
3557          * BD data is written to the memory, the producer is read from the
3558          * memory, thus we need a full memory barrier to ensure the ordering.
3559          */
3560         mb();
3561
3562         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3563                  bp->spq_prod_idx);
3564         mmiowb();
3565 }
3566
3567 /**
3568  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3569  *
3570  * @cmd:        command to check
3571  * @cmd_type:   command type
3572  */
3573 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3574 {
3575         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3576             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3577             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3578             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3579             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3580             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3581             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3582                 return true;
3583         else
3584                 return false;
3585 }
3586
3587 /**
3588  * bnx2x_sp_post - place a single command on an SP ring
3589  *
3590  * @bp:         driver handle
3591  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3592  * @cid:        SW CID the command is related to
3593  * @data_hi:    command private data address (high 32 bits)
3594  * @data_lo:    command private data address (low 32 bits)
3595  * @cmd_type:   command type (e.g. NONE, ETH)
3596  *
3597  * SP data is handled as if it's always an address pair, thus data fields are
3598  * not swapped to little endian in upper functions. Instead this function swaps
3599  * data as if it's two u32 fields.
3600  */
3601 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3602                   u32 data_hi, u32 data_lo, int cmd_type)
3603 {
3604         struct eth_spe *spe;
3605         u16 type;
3606         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3607
3608 #ifdef BNX2X_STOP_ON_ERROR
3609         if (unlikely(bp->panic)) {
3610                 BNX2X_ERR("Can't post SP when there is panic\n");
3611                 return -EIO;
3612         }
3613 #endif
3614
3615         spin_lock_bh(&bp->spq_lock);
3616
3617         if (common) {
3618                 if (!atomic_read(&bp->eq_spq_left)) {
3619                         BNX2X_ERR("BUG! EQ ring full!\n");
3620                         spin_unlock_bh(&bp->spq_lock);
3621                         bnx2x_panic();
3622                         return -EBUSY;
3623                 }
3624         } else if (!atomic_read(&bp->cq_spq_left)) {
3625                         BNX2X_ERR("BUG! SPQ ring full!\n");
3626                         spin_unlock_bh(&bp->spq_lock);
3627                         bnx2x_panic();
3628                         return -EBUSY;
3629         }
3630
3631         spe = bnx2x_sp_get_next(bp);
3632
3633         /* CID needs port number to be encoded int it */
3634         spe->hdr.conn_and_cmd_data =
3635                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3636                                     HW_CID(bp, cid));
3637
3638         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3639
3640         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3641                  SPE_HDR_FUNCTION_ID);
3642
3643         spe->hdr.type = cpu_to_le16(type);
3644
3645         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3646         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3647
3648         /*
3649          * It's ok if the actual decrement is issued towards the memory
3650          * somewhere between the spin_lock and spin_unlock. Thus no
3651          * more explicit memory barrier is needed.
3652          */
3653         if (common)
3654                 atomic_dec(&bp->eq_spq_left);
3655         else
3656                 atomic_dec(&bp->cq_spq_left);
3657
3658         DP(BNX2X_MSG_SP,
3659            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3660            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3661            (u32)(U64_LO(bp->spq_mapping) +
3662            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3663            HW_CID(bp, cid), data_hi, data_lo, type,
3664            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3665
3666         bnx2x_sp_prod_update(bp);
3667         spin_unlock_bh(&bp->spq_lock);
3668         return 0;
3669 }
3670
3671 /* acquire split MCP access lock register */
3672 static int bnx2x_acquire_alr(struct bnx2x *bp)
3673 {
3674         u32 j, val;
3675         int rc = 0;
3676
3677         might_sleep();
3678         for (j = 0; j < 1000; j++) {
3679                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3680                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3681                 if (val & MCPR_ACCESS_LOCK_LOCK)
3682                         break;
3683
3684                 usleep_range(5000, 10000);
3685         }
3686         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3687                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3688                 rc = -EBUSY;
3689         }
3690
3691         return rc;
3692 }
3693
3694 /* release split MCP access lock register */
3695 static void bnx2x_release_alr(struct bnx2x *bp)
3696 {
3697         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3698 }
3699
3700 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3701 #define BNX2X_DEF_SB_IDX        0x0002
3702
3703 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3704 {
3705         struct host_sp_status_block *def_sb = bp->def_status_blk;
3706         u16 rc = 0;
3707
3708         barrier(); /* status block is written to by the chip */
3709         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3710                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3711                 rc |= BNX2X_DEF_SB_ATT_IDX;
3712         }
3713
3714         if (bp->def_idx != def_sb->sp_sb.running_index) {
3715                 bp->def_idx = def_sb->sp_sb.running_index;
3716                 rc |= BNX2X_DEF_SB_IDX;
3717         }
3718
3719         /* Do not reorder: indices reading should complete before handling */
3720         barrier();
3721         return rc;
3722 }
3723
3724 /*
3725  * slow path service functions
3726  */
3727
3728 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3729 {
3730         int port = BP_PORT(bp);
3731         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3732                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3733         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3734                                        NIG_REG_MASK_INTERRUPT_PORT0;
3735         u32 aeu_mask;
3736         u32 nig_mask = 0;
3737         u32 reg_addr;
3738
3739         if (bp->attn_state & asserted)
3740                 BNX2X_ERR("IGU ERROR\n");
3741
3742         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3743         aeu_mask = REG_RD(bp, aeu_addr);
3744
3745         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3746            aeu_mask, asserted);
3747         aeu_mask &= ~(asserted & 0x3ff);
3748         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3749
3750         REG_WR(bp, aeu_addr, aeu_mask);
3751         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3752
3753         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3754         bp->attn_state |= asserted;
3755         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3756
3757         if (asserted & ATTN_HARD_WIRED_MASK) {
3758                 if (asserted & ATTN_NIG_FOR_FUNC) {
3759
3760                         bnx2x_acquire_phy_lock(bp);
3761
3762                         /* save nig interrupt mask */
3763                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3764
3765                         /* If nig_mask is not set, no need to call the update
3766                          * function.
3767                          */
3768                         if (nig_mask) {
3769                                 REG_WR(bp, nig_int_mask_addr, 0);
3770
3771                                 bnx2x_link_attn(bp);
3772                         }
3773
3774                         /* handle unicore attn? */
3775                 }
3776                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3777                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3778
3779                 if (asserted & GPIO_2_FUNC)
3780                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3781
3782                 if (asserted & GPIO_3_FUNC)
3783                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3784
3785                 if (asserted & GPIO_4_FUNC)
3786                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3787
3788                 if (port == 0) {
3789                         if (asserted & ATTN_GENERAL_ATTN_1) {
3790                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3791                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3792                         }
3793                         if (asserted & ATTN_GENERAL_ATTN_2) {
3794                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3795                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3796                         }
3797                         if (asserted & ATTN_GENERAL_ATTN_3) {
3798                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3799                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3800                         }
3801                 } else {
3802                         if (asserted & ATTN_GENERAL_ATTN_4) {
3803                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3804                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3805                         }
3806                         if (asserted & ATTN_GENERAL_ATTN_5) {
3807                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3808                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3809                         }
3810                         if (asserted & ATTN_GENERAL_ATTN_6) {
3811                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3812                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3813                         }
3814                 }
3815
3816         } /* if hardwired */
3817
3818         if (bp->common.int_block == INT_BLOCK_HC)
3819                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3820                             COMMAND_REG_ATTN_BITS_SET);
3821         else
3822                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3823
3824         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3825            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3826         REG_WR(bp, reg_addr, asserted);
3827
3828         /* now set back the mask */
3829         if (asserted & ATTN_NIG_FOR_FUNC) {
3830                 /* Verify that IGU ack through BAR was written before restoring
3831                  * NIG mask. This loop should exit after 2-3 iterations max.
3832                  */
3833                 if (bp->common.int_block != INT_BLOCK_HC) {
3834                         u32 cnt = 0, igu_acked;
3835                         do {
3836                                 igu_acked = REG_RD(bp,
3837                                                    IGU_REG_ATTENTION_ACK_BITS);
3838                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3839                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3840                         if (!igu_acked)
3841                                 DP(NETIF_MSG_HW,
3842                                    "Failed to verify IGU ack on time\n");
3843                         barrier();
3844                 }
3845                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3846                 bnx2x_release_phy_lock(bp);
3847         }
3848 }
3849
3850 static void bnx2x_fan_failure(struct bnx2x *bp)
3851 {
3852         int port = BP_PORT(bp);
3853         u32 ext_phy_config;
3854         /* mark the failure */
3855         ext_phy_config =
3856                 SHMEM_RD(bp,
3857                          dev_info.port_hw_config[port].external_phy_config);
3858
3859         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3860         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3861         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3862                  ext_phy_config);
3863
3864         /* log the failure */
3865         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3866                             "Please contact OEM Support for assistance\n");
3867
3868         /* Schedule device reset (unload)
3869          * This is due to some boards consuming sufficient power when driver is
3870          * up to overheat if fan fails.
3871          */
3872         smp_mb__before_clear_bit();
3873         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3874         smp_mb__after_clear_bit();
3875         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3876 }
3877
3878 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3879 {
3880         int port = BP_PORT(bp);
3881         int reg_offset;
3882         u32 val;
3883
3884         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3885                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3886
3887         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3888
3889                 val = REG_RD(bp, reg_offset);
3890                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3891                 REG_WR(bp, reg_offset, val);
3892
3893                 BNX2X_ERR("SPIO5 hw attention\n");
3894
3895                 /* Fan failure attention */
3896                 bnx2x_hw_reset_phy(&bp->link_params);
3897                 bnx2x_fan_failure(bp);
3898         }
3899
3900         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3901                 bnx2x_acquire_phy_lock(bp);
3902                 bnx2x_handle_module_detect_int(&bp->link_params);
3903                 bnx2x_release_phy_lock(bp);
3904         }
3905
3906         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3907
3908                 val = REG_RD(bp, reg_offset);
3909                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3910                 REG_WR(bp, reg_offset, val);
3911
3912                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3913                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3914                 bnx2x_panic();
3915         }
3916 }
3917
3918 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3919 {
3920         u32 val;
3921
3922         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3923
3924                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3925                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3926                 /* DORQ discard attention */
3927                 if (val & 0x2)
3928                         BNX2X_ERR("FATAL error from DORQ\n");
3929         }
3930
3931         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3932
3933                 int port = BP_PORT(bp);
3934                 int reg_offset;
3935
3936                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3937                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3938
3939                 val = REG_RD(bp, reg_offset);
3940                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3941                 REG_WR(bp, reg_offset, val);
3942
3943                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3944                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3945                 bnx2x_panic();
3946         }
3947 }
3948
3949 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3950 {
3951         u32 val;
3952
3953         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3954
3955                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3956                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3957                 /* CFC error attention */
3958                 if (val & 0x2)
3959                         BNX2X_ERR("FATAL error from CFC\n");
3960         }
3961
3962         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3963                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3964                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3965                 /* RQ_USDMDP_FIFO_OVERFLOW */
3966                 if (val & 0x18000)
3967                         BNX2X_ERR("FATAL error from PXP\n");
3968
3969                 if (!CHIP_IS_E1x(bp)) {
3970                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3971                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3972                 }
3973         }
3974
3975         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3976
3977                 int port = BP_PORT(bp);
3978                 int reg_offset;
3979
3980                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3981                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3982
3983                 val = REG_RD(bp, reg_offset);
3984                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3985                 REG_WR(bp, reg_offset, val);
3986
3987                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3988                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3989                 bnx2x_panic();
3990         }
3991 }
3992
3993 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3994 {
3995         u32 val;
3996
3997         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3998
3999                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4000                         int func = BP_FUNC(bp);
4001
4002                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4003                         bnx2x_read_mf_cfg(bp);
4004                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4005                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4006                         val = SHMEM_RD(bp,
4007                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4008                         if (val & DRV_STATUS_DCC_EVENT_MASK)
4009                                 bnx2x_dcc_event(bp,
4010                                             (val & DRV_STATUS_DCC_EVENT_MASK));
4011
4012                         if (val & DRV_STATUS_SET_MF_BW)
4013                                 bnx2x_set_mf_bw(bp);
4014
4015                         if (val & DRV_STATUS_DRV_INFO_REQ)
4016                                 bnx2x_handle_drv_info_req(bp);
4017
4018                         if (val & DRV_STATUS_VF_DISABLED)
4019                                 bnx2x_vf_handle_flr_event(bp);
4020
4021                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4022                                 bnx2x_pmf_update(bp);
4023
4024                         if (bp->port.pmf &&
4025                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4026                                 bp->dcbx_enabled > 0)
4027                                 /* start dcbx state machine */
4028                                 bnx2x_dcbx_set_params(bp,
4029                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4030                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4031                                 bnx2x_handle_afex_cmd(bp,
4032                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4033                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4034                                 bnx2x_handle_eee_event(bp);
4035                         if (bp->link_vars.periodic_flags &
4036                             PERIODIC_FLAGS_LINK_EVENT) {
4037                                 /*  sync with link */
4038                                 bnx2x_acquire_phy_lock(bp);
4039                                 bp->link_vars.periodic_flags &=
4040                                         ~PERIODIC_FLAGS_LINK_EVENT;
4041                                 bnx2x_release_phy_lock(bp);
4042                                 if (IS_MF(bp))
4043                                         bnx2x_link_sync_notify(bp);
4044                                 bnx2x_link_report(bp);
4045                         }
4046                         /* Always call it here: bnx2x_link_report() will
4047                          * prevent the link indication duplication.
4048                          */
4049                         bnx2x__link_status_update(bp);
4050                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4051
4052                         BNX2X_ERR("MC assert!\n");
4053                         bnx2x_mc_assert(bp);
4054                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4055                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4056                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4057                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4058                         bnx2x_panic();
4059
4060                 } else if (attn & BNX2X_MCP_ASSERT) {
4061
4062                         BNX2X_ERR("MCP assert!\n");
4063                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4064                         bnx2x_fw_dump(bp);
4065
4066                 } else
4067                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4068         }
4069
4070         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4071                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4072                 if (attn & BNX2X_GRC_TIMEOUT) {
4073                         val = CHIP_IS_E1(bp) ? 0 :
4074                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4075                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4076                 }
4077                 if (attn & BNX2X_GRC_RSV) {
4078                         val = CHIP_IS_E1(bp) ? 0 :
4079                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4080                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4081                 }
4082                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4083         }
4084 }
4085
4086 /*
4087  * Bits map:
4088  * 0-7   - Engine0 load counter.
4089  * 8-15  - Engine1 load counter.
4090  * 16    - Engine0 RESET_IN_PROGRESS bit.
4091  * 17    - Engine1 RESET_IN_PROGRESS bit.
4092  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4093  *         on the engine
4094  * 19    - Engine1 ONE_IS_LOADED.
4095  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4096  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4097  *         just the one belonging to its engine).
4098  *
4099  */
4100 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4101
4102 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4103 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4104 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4105 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4106 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4107 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4108 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4109
4110 /*
4111  * Set the GLOBAL_RESET bit.
4112  *
4113  * Should be run under rtnl lock
4114  */
4115 void bnx2x_set_reset_global(struct bnx2x *bp)
4116 {
4117         u32 val;
4118         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4119         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4120         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4121         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4122 }
4123
4124 /*
4125  * Clear the GLOBAL_RESET bit.
4126  *
4127  * Should be run under rtnl lock
4128  */
4129 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4130 {
4131         u32 val;
4132         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4133         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4134         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4135         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4136 }
4137
4138 /*
4139  * Checks the GLOBAL_RESET bit.
4140  *
4141  * should be run under rtnl lock
4142  */
4143 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4144 {
4145         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4146
4147         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4148         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4149 }
4150
4151 /*
4152  * Clear RESET_IN_PROGRESS bit for the current engine.
4153  *
4154  * Should be run under rtnl lock
4155  */
4156 static void bnx2x_set_reset_done(struct bnx2x *bp)
4157 {
4158         u32 val;
4159         u32 bit = BP_PATH(bp) ?
4160                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4161         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4162         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4163
4164         /* Clear the bit */
4165         val &= ~bit;
4166         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4167
4168         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4169 }
4170
4171 /*
4172  * Set RESET_IN_PROGRESS for the current engine.
4173  *
4174  * should be run under rtnl lock
4175  */
4176 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4177 {
4178         u32 val;
4179         u32 bit = BP_PATH(bp) ?
4180                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4181         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4182         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4183
4184         /* Set the bit */
4185         val |= bit;
4186         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4187         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4188 }
4189
4190 /*
4191  * Checks the RESET_IN_PROGRESS bit for the given engine.
4192  * should be run under rtnl lock
4193  */
4194 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4195 {
4196         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4197         u32 bit = engine ?
4198                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4199
4200         /* return false if bit is set */
4201         return (val & bit) ? false : true;
4202 }
4203
4204 /*
4205  * set pf load for the current pf.
4206  *
4207  * should be run under rtnl lock
4208  */
4209 void bnx2x_set_pf_load(struct bnx2x *bp)
4210 {
4211         u32 val1, val;
4212         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4213                              BNX2X_PATH0_LOAD_CNT_MASK;
4214         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4215                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4216
4217         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4218         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4219
4220         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4221
4222         /* get the current counter value */
4223         val1 = (val & mask) >> shift;
4224
4225         /* set bit of that PF */
4226         val1 |= (1 << bp->pf_num);
4227
4228         /* clear the old value */
4229         val &= ~mask;
4230
4231         /* set the new one */
4232         val |= ((val1 << shift) & mask);
4233
4234         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4235         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4236 }
4237
4238 /**
4239  * bnx2x_clear_pf_load - clear pf load mark
4240  *
4241  * @bp:         driver handle
4242  *
4243  * Should be run under rtnl lock.
4244  * Decrements the load counter for the current engine. Returns
4245  * whether other functions are still loaded
4246  */
4247 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4248 {
4249         u32 val1, val;
4250         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4251                              BNX2X_PATH0_LOAD_CNT_MASK;
4252         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4253                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4254
4255         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4256         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4257         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4258
4259         /* get the current counter value */
4260         val1 = (val & mask) >> shift;
4261
4262         /* clear bit of that PF */
4263         val1 &= ~(1 << bp->pf_num);
4264
4265         /* clear the old value */
4266         val &= ~mask;
4267
4268         /* set the new one */
4269         val |= ((val1 << shift) & mask);
4270
4271         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4272         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4273         return val1 != 0;
4274 }
4275
4276 /*
4277  * Read the load status for the current engine.
4278  *
4279  * should be run under rtnl lock
4280  */
4281 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4282 {
4283         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4284                              BNX2X_PATH0_LOAD_CNT_MASK);
4285         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4286                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4287         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4288
4289         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4290
4291         val = (val & mask) >> shift;
4292
4293         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4294            engine, val);
4295
4296         return val != 0;
4297 }
4298
4299 static void _print_parity(struct bnx2x *bp, u32 reg)
4300 {
4301         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4302 }
4303
4304 static void _print_next_block(int idx, const char *blk)
4305 {
4306         pr_cont("%s%s", idx ? ", " : "", blk);
4307 }
4308
4309 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4310                                             int *par_num, bool print)
4311 {
4312         u32 cur_bit;
4313         bool res;
4314         int i;
4315
4316         res = false;
4317
4318         for (i = 0; sig; i++) {
4319                 cur_bit = (0x1UL << i);
4320                 if (sig & cur_bit) {
4321                         res |= true; /* Each bit is real error! */
4322
4323                         if (print) {
4324                                 switch (cur_bit) {
4325                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4326                                         _print_next_block((*par_num)++, "BRB");
4327                                         _print_parity(bp,
4328                                                       BRB1_REG_BRB1_PRTY_STS);
4329                                         break;
4330                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4331                                         _print_next_block((*par_num)++,
4332                                                           "PARSER");
4333                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4334                                         break;
4335                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4336                                         _print_next_block((*par_num)++, "TSDM");
4337                                         _print_parity(bp,
4338                                                       TSDM_REG_TSDM_PRTY_STS);
4339                                         break;
4340                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4341                                         _print_next_block((*par_num)++,
4342                                                           "SEARCHER");
4343                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4344                                         break;
4345                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4346                                         _print_next_block((*par_num)++, "TCM");
4347                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4348                                         break;
4349                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4350                                         _print_next_block((*par_num)++,
4351                                                           "TSEMI");
4352                                         _print_parity(bp,
4353                                                       TSEM_REG_TSEM_PRTY_STS_0);
4354                                         _print_parity(bp,
4355                                                       TSEM_REG_TSEM_PRTY_STS_1);
4356                                         break;
4357                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4358                                         _print_next_block((*par_num)++, "XPB");
4359                                         _print_parity(bp, GRCBASE_XPB +
4360                                                           PB_REG_PB_PRTY_STS);
4361                                         break;
4362                                 }
4363                         }
4364
4365                         /* Clear the bit */
4366                         sig &= ~cur_bit;
4367                 }
4368         }
4369
4370         return res;
4371 }
4372
4373 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4374                                             int *par_num, bool *global,
4375                                             bool print)
4376 {
4377         u32 cur_bit;
4378         bool res;
4379         int i;
4380
4381         res = false;
4382
4383         for (i = 0; sig; i++) {
4384                 cur_bit = (0x1UL << i);
4385                 if (sig & cur_bit) {
4386                         res |= true; /* Each bit is real error! */
4387                         switch (cur_bit) {
4388                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4389                                 if (print) {
4390                                         _print_next_block((*par_num)++, "PBF");
4391                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4392                                 }
4393                                 break;
4394                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4395                                 if (print) {
4396                                         _print_next_block((*par_num)++, "QM");
4397                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4398                                 }
4399                                 break;
4400                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4401                                 if (print) {
4402                                         _print_next_block((*par_num)++, "TM");
4403                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4404                                 }
4405                                 break;
4406                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4407                                 if (print) {
4408                                         _print_next_block((*par_num)++, "XSDM");
4409                                         _print_parity(bp,
4410                                                       XSDM_REG_XSDM_PRTY_STS);
4411                                 }
4412                                 break;
4413                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4414                                 if (print) {
4415                                         _print_next_block((*par_num)++, "XCM");
4416                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4417                                 }
4418                                 break;
4419                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4420                                 if (print) {
4421                                         _print_next_block((*par_num)++,
4422                                                           "XSEMI");
4423                                         _print_parity(bp,
4424                                                       XSEM_REG_XSEM_PRTY_STS_0);
4425                                         _print_parity(bp,
4426                                                       XSEM_REG_XSEM_PRTY_STS_1);
4427                                 }
4428                                 break;
4429                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4430                                 if (print) {
4431                                         _print_next_block((*par_num)++,
4432                                                           "DOORBELLQ");
4433                                         _print_parity(bp,
4434                                                       DORQ_REG_DORQ_PRTY_STS);
4435                                 }
4436                                 break;
4437                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4438                                 if (print) {
4439                                         _print_next_block((*par_num)++, "NIG");
4440                                         if (CHIP_IS_E1x(bp)) {
4441                                                 _print_parity(bp,
4442                                                         NIG_REG_NIG_PRTY_STS);
4443                                         } else {
4444                                                 _print_parity(bp,
4445                                                         NIG_REG_NIG_PRTY_STS_0);
4446                                                 _print_parity(bp,
4447                                                         NIG_REG_NIG_PRTY_STS_1);
4448                                         }
4449                                 }
4450                                 break;
4451                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4452                                 if (print)
4453                                         _print_next_block((*par_num)++,
4454                                                           "VAUX PCI CORE");
4455                                 *global = true;
4456                                 break;
4457                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4458                                 if (print) {
4459                                         _print_next_block((*par_num)++,
4460                                                           "DEBUG");
4461                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4462                                 }
4463                                 break;
4464                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4465                                 if (print) {
4466                                         _print_next_block((*par_num)++, "USDM");
4467                                         _print_parity(bp,
4468                                                       USDM_REG_USDM_PRTY_STS);
4469                                 }
4470                                 break;
4471                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4472                                 if (print) {
4473                                         _print_next_block((*par_num)++, "UCM");
4474                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4475                                 }
4476                                 break;
4477                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4478                                 if (print) {
4479                                         _print_next_block((*par_num)++,
4480                                                           "USEMI");
4481                                         _print_parity(bp,
4482                                                       USEM_REG_USEM_PRTY_STS_0);
4483                                         _print_parity(bp,
4484                                                       USEM_REG_USEM_PRTY_STS_1);
4485                                 }
4486                                 break;
4487                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4488                                 if (print) {
4489                                         _print_next_block((*par_num)++, "UPB");
4490                                         _print_parity(bp, GRCBASE_UPB +
4491                                                           PB_REG_PB_PRTY_STS);
4492                                 }
4493                                 break;
4494                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4495                                 if (print) {
4496                                         _print_next_block((*par_num)++, "CSDM");
4497                                         _print_parity(bp,
4498                                                       CSDM_REG_CSDM_PRTY_STS);
4499                                 }
4500                                 break;
4501                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4502                                 if (print) {
4503                                         _print_next_block((*par_num)++, "CCM");
4504                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4505                                 }
4506                                 break;
4507                         }
4508
4509                         /* Clear the bit */
4510                         sig &= ~cur_bit;
4511                 }
4512         }
4513
4514         return res;
4515 }
4516
4517 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4518                                             int *par_num, bool print)
4519 {
4520         u32 cur_bit;
4521         bool res;
4522         int i;
4523
4524         res = false;
4525
4526         for (i = 0; sig; i++) {
4527                 cur_bit = (0x1UL << i);
4528                 if (sig & cur_bit) {
4529                         res |= true; /* Each bit is real error! */
4530                         if (print) {
4531                                 switch (cur_bit) {
4532                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4533                                         _print_next_block((*par_num)++,
4534                                                           "CSEMI");
4535                                         _print_parity(bp,
4536                                                       CSEM_REG_CSEM_PRTY_STS_0);
4537                                         _print_parity(bp,
4538                                                       CSEM_REG_CSEM_PRTY_STS_1);
4539                                         break;
4540                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4541                                         _print_next_block((*par_num)++, "PXP");
4542                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4543                                         _print_parity(bp,
4544                                                       PXP2_REG_PXP2_PRTY_STS_0);
4545                                         _print_parity(bp,
4546                                                       PXP2_REG_PXP2_PRTY_STS_1);
4547                                         break;
4548                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4549                                         _print_next_block((*par_num)++,
4550                                                           "PXPPCICLOCKCLIENT");
4551                                         break;
4552                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4553                                         _print_next_block((*par_num)++, "CFC");
4554                                         _print_parity(bp,
4555                                                       CFC_REG_CFC_PRTY_STS);
4556                                         break;
4557                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4558                                         _print_next_block((*par_num)++, "CDU");
4559                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4560                                         break;
4561                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4562                                         _print_next_block((*par_num)++, "DMAE");
4563                                         _print_parity(bp,
4564                                                       DMAE_REG_DMAE_PRTY_STS);
4565                                         break;
4566                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4567                                         _print_next_block((*par_num)++, "IGU");
4568                                         if (CHIP_IS_E1x(bp))
4569                                                 _print_parity(bp,
4570                                                         HC_REG_HC_PRTY_STS);
4571                                         else
4572                                                 _print_parity(bp,
4573                                                         IGU_REG_IGU_PRTY_STS);
4574                                         break;
4575                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4576                                         _print_next_block((*par_num)++, "MISC");
4577                                         _print_parity(bp,
4578                                                       MISC_REG_MISC_PRTY_STS);
4579                                         break;
4580                                 }
4581                         }
4582
4583                         /* Clear the bit */
4584                         sig &= ~cur_bit;
4585                 }
4586         }
4587
4588         return res;
4589 }
4590
4591 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4592                                             int *par_num, bool *global,
4593                                             bool print)
4594 {
4595         bool res = false;
4596         u32 cur_bit;
4597         int i;
4598
4599         for (i = 0; sig; i++) {
4600                 cur_bit = (0x1UL << i);
4601                 if (sig & cur_bit) {
4602                         switch (cur_bit) {
4603                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4604                                 if (print)
4605                                         _print_next_block((*par_num)++,
4606                                                           "MCP ROM");
4607                                 *global = true;
4608                                 res |= true;
4609                                 break;
4610                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4611                                 if (print)
4612                                         _print_next_block((*par_num)++,
4613                                                           "MCP UMP RX");
4614                                 *global = true;
4615                                 res |= true;
4616                                 break;
4617                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4618                                 if (print)
4619                                         _print_next_block((*par_num)++,
4620                                                           "MCP UMP TX");
4621                                 *global = true;
4622                                 res |= true;
4623                                 break;
4624                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4625                                 if (print)
4626                                         _print_next_block((*par_num)++,
4627                                                           "MCP SCPAD");
4628                                 /* clear latched SCPAD PATIRY from MCP */
4629                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4630                                        1UL << 10);
4631                                 break;
4632                         }
4633
4634                         /* Clear the bit */
4635                         sig &= ~cur_bit;
4636                 }
4637         }
4638
4639         return res;
4640 }
4641
4642 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4643                                             int *par_num, bool print)
4644 {
4645         u32 cur_bit;
4646         bool res;
4647         int i;
4648
4649         res = false;
4650
4651         for (i = 0; sig; i++) {
4652                 cur_bit = (0x1UL << i);
4653                 if (sig & cur_bit) {
4654                         res |= true; /* Each bit is real error! */
4655                         if (print) {
4656                                 switch (cur_bit) {
4657                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4658                                         _print_next_block((*par_num)++,
4659                                                           "PGLUE_B");
4660                                         _print_parity(bp,
4661                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4662                                         break;
4663                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4664                                         _print_next_block((*par_num)++, "ATC");
4665                                         _print_parity(bp,
4666                                                       ATC_REG_ATC_PRTY_STS);
4667                                         break;
4668                                 }
4669                         }
4670                         /* Clear the bit */
4671                         sig &= ~cur_bit;
4672                 }
4673         }
4674
4675         return res;
4676 }
4677
4678 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4679                               u32 *sig)
4680 {
4681         bool res = false;
4682
4683         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4684             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4685             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4686             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4687             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4688                 int par_num = 0;
4689                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4690                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4691                           sig[0] & HW_PRTY_ASSERT_SET_0,
4692                           sig[1] & HW_PRTY_ASSERT_SET_1,
4693                           sig[2] & HW_PRTY_ASSERT_SET_2,
4694                           sig[3] & HW_PRTY_ASSERT_SET_3,
4695                           sig[4] & HW_PRTY_ASSERT_SET_4);
4696                 if (print)
4697                         netdev_err(bp->dev,
4698                                    "Parity errors detected in blocks: ");
4699                 res |= bnx2x_check_blocks_with_parity0(bp,
4700                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4701                 res |= bnx2x_check_blocks_with_parity1(bp,
4702                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4703                 res |= bnx2x_check_blocks_with_parity2(bp,
4704                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4705                 res |= bnx2x_check_blocks_with_parity3(bp,
4706                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4707                 res |= bnx2x_check_blocks_with_parity4(bp,
4708                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4709
4710                 if (print)
4711                         pr_cont("\n");
4712         }
4713
4714         return res;
4715 }
4716
4717 /**
4718  * bnx2x_chk_parity_attn - checks for parity attentions.
4719  *
4720  * @bp:         driver handle
4721  * @global:     true if there was a global attention
4722  * @print:      show parity attention in syslog
4723  */
4724 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4725 {
4726         struct attn_route attn = { {0} };
4727         int port = BP_PORT(bp);
4728
4729         attn.sig[0] = REG_RD(bp,
4730                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4731                              port*4);
4732         attn.sig[1] = REG_RD(bp,
4733                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4734                              port*4);
4735         attn.sig[2] = REG_RD(bp,
4736                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4737                              port*4);
4738         attn.sig[3] = REG_RD(bp,
4739                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4740                              port*4);
4741         /* Since MCP attentions can't be disabled inside the block, we need to
4742          * read AEU registers to see whether they're currently disabled
4743          */
4744         attn.sig[3] &= ((REG_RD(bp,
4745                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4746                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4747                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4748                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4749
4750         if (!CHIP_IS_E1x(bp))
4751                 attn.sig[4] = REG_RD(bp,
4752                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4753                                      port*4);
4754
4755         return bnx2x_parity_attn(bp, global, print, attn.sig);
4756 }
4757
4758 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4759 {
4760         u32 val;
4761         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4762
4763                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4764                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4765                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4766                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4767                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4768                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4769                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4770                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4771                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4772                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4773                 if (val &
4774                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4775                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4776                 if (val &
4777                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4778                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4779                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4780                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4781                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4782                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4783                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4784                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4785         }
4786         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4787                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4788                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4789                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4790                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4791                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4792                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4793                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4794                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4795                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4796                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4797                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4798                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4799                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4800                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4801         }
4802
4803         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4804                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4805                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4806                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4807                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4808         }
4809 }
4810
4811 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4812 {
4813         struct attn_route attn, *group_mask;
4814         int port = BP_PORT(bp);
4815         int index;
4816         u32 reg_addr;
4817         u32 val;
4818         u32 aeu_mask;
4819         bool global = false;
4820
4821         /* need to take HW lock because MCP or other port might also
4822            try to handle this event */
4823         bnx2x_acquire_alr(bp);
4824
4825         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4826 #ifndef BNX2X_STOP_ON_ERROR
4827                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4828                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4829                 /* Disable HW interrupts */
4830                 bnx2x_int_disable(bp);
4831                 /* In case of parity errors don't handle attentions so that
4832                  * other function would "see" parity errors.
4833                  */
4834 #else
4835                 bnx2x_panic();
4836 #endif
4837                 bnx2x_release_alr(bp);
4838                 return;
4839         }
4840
4841         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4842         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4843         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4844         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4845         if (!CHIP_IS_E1x(bp))
4846                 attn.sig[4] =
4847                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4848         else
4849                 attn.sig[4] = 0;
4850
4851         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4852            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4853
4854         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4855                 if (deasserted & (1 << index)) {
4856                         group_mask = &bp->attn_group[index];
4857
4858                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4859                            index,
4860                            group_mask->sig[0], group_mask->sig[1],
4861                            group_mask->sig[2], group_mask->sig[3],
4862                            group_mask->sig[4]);
4863
4864                         bnx2x_attn_int_deasserted4(bp,
4865                                         attn.sig[4] & group_mask->sig[4]);
4866                         bnx2x_attn_int_deasserted3(bp,
4867                                         attn.sig[3] & group_mask->sig[3]);
4868                         bnx2x_attn_int_deasserted1(bp,
4869                                         attn.sig[1] & group_mask->sig[1]);
4870                         bnx2x_attn_int_deasserted2(bp,
4871                                         attn.sig[2] & group_mask->sig[2]);
4872                         bnx2x_attn_int_deasserted0(bp,
4873                                         attn.sig[0] & group_mask->sig[0]);
4874                 }
4875         }
4876
4877         bnx2x_release_alr(bp);
4878
4879         if (bp->common.int_block == INT_BLOCK_HC)
4880                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4881                             COMMAND_REG_ATTN_BITS_CLR);
4882         else
4883                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4884
4885         val = ~deasserted;
4886         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4887            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4888         REG_WR(bp, reg_addr, val);
4889
4890         if (~bp->attn_state & deasserted)
4891                 BNX2X_ERR("IGU ERROR\n");
4892
4893         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4894                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4895
4896         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4897         aeu_mask = REG_RD(bp, reg_addr);
4898
4899         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4900            aeu_mask, deasserted);
4901         aeu_mask |= (deasserted & 0x3ff);
4902         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4903
4904         REG_WR(bp, reg_addr, aeu_mask);
4905         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4906
4907         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4908         bp->attn_state &= ~deasserted;
4909         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4910 }
4911
4912 static void bnx2x_attn_int(struct bnx2x *bp)
4913 {
4914         /* read local copy of bits */
4915         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4916                                                                 attn_bits);
4917         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4918                                                                 attn_bits_ack);
4919         u32 attn_state = bp->attn_state;
4920
4921         /* look for changed bits */
4922         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4923         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4924
4925         DP(NETIF_MSG_HW,
4926            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4927            attn_bits, attn_ack, asserted, deasserted);
4928
4929         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4930                 BNX2X_ERR("BAD attention state\n");
4931
4932         /* handle bits that were raised */
4933         if (asserted)
4934                 bnx2x_attn_int_asserted(bp, asserted);
4935
4936         if (deasserted)
4937                 bnx2x_attn_int_deasserted(bp, deasserted);
4938 }
4939
4940 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4941                       u16 index, u8 op, u8 update)
4942 {
4943         u32 igu_addr = bp->igu_base_addr;
4944         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4945         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4946                              igu_addr);
4947 }
4948
4949 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4950 {
4951         /* No memory barriers */
4952         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4953         mmiowb(); /* keep prod updates ordered */
4954 }
4955
4956 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4957                                       union event_ring_elem *elem)
4958 {
4959         u8 err = elem->message.error;
4960
4961         if (!bp->cnic_eth_dev.starting_cid  ||
4962             (cid < bp->cnic_eth_dev.starting_cid &&
4963             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4964                 return 1;
4965
4966         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4967
4968         if (unlikely(err)) {
4969
4970                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4971                           cid);
4972                 bnx2x_panic_dump(bp, false);
4973         }
4974         bnx2x_cnic_cfc_comp(bp, cid, err);
4975         return 0;
4976 }
4977
4978 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4979 {
4980         struct bnx2x_mcast_ramrod_params rparam;
4981         int rc;
4982
4983         memset(&rparam, 0, sizeof(rparam));
4984
4985         rparam.mcast_obj = &bp->mcast_obj;
4986
4987         netif_addr_lock_bh(bp->dev);
4988
4989         /* Clear pending state for the last command */
4990         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4991
4992         /* If there are pending mcast commands - send them */
4993         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4994                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4995                 if (rc < 0)
4996                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4997                                   rc);
4998         }
4999
5000         netif_addr_unlock_bh(bp->dev);
5001 }
5002
5003 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5004                                             union event_ring_elem *elem)
5005 {
5006         unsigned long ramrod_flags = 0;
5007         int rc = 0;
5008         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5009         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5010
5011         /* Always push next commands out, don't wait here */
5012         __set_bit(RAMROD_CONT, &ramrod_flags);
5013
5014         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5015                             >> BNX2X_SWCID_SHIFT) {
5016         case BNX2X_FILTER_MAC_PENDING:
5017                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5018                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5019                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5020                 else
5021                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5022
5023                 break;
5024         case BNX2X_FILTER_MCAST_PENDING:
5025                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5026                 /* This is only relevant for 57710 where multicast MACs are
5027                  * configured as unicast MACs using the same ramrod.
5028                  */
5029                 bnx2x_handle_mcast_eqe(bp);
5030                 return;
5031         default:
5032                 BNX2X_ERR("Unsupported classification command: %d\n",
5033                           elem->message.data.eth_event.echo);
5034                 return;
5035         }
5036
5037         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5038
5039         if (rc < 0)
5040                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5041         else if (rc > 0)
5042                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5043 }
5044
5045 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5046
5047 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5048 {
5049         netif_addr_lock_bh(bp->dev);
5050
5051         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5052
5053         /* Send rx_mode command again if was requested */
5054         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5055                 bnx2x_set_storm_rx_mode(bp);
5056         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5057                                     &bp->sp_state))
5058                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5059         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5060                                     &bp->sp_state))
5061                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5062
5063         netif_addr_unlock_bh(bp->dev);
5064 }
5065
5066 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5067                                               union event_ring_elem *elem)
5068 {
5069         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5070                 DP(BNX2X_MSG_SP,
5071                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5072                    elem->message.data.vif_list_event.func_bit_map);
5073                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5074                         elem->message.data.vif_list_event.func_bit_map);
5075         } else if (elem->message.data.vif_list_event.echo ==
5076                    VIF_LIST_RULE_SET) {
5077                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5078                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5079         }
5080 }
5081
5082 /* called with rtnl_lock */
5083 static void bnx2x_after_function_update(struct bnx2x *bp)
5084 {
5085         int q, rc;
5086         struct bnx2x_fastpath *fp;
5087         struct bnx2x_queue_state_params queue_params = {NULL};
5088         struct bnx2x_queue_update_params *q_update_params =
5089                 &queue_params.params.update;
5090
5091         /* Send Q update command with afex vlan removal values for all Qs */
5092         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5093
5094         /* set silent vlan removal values according to vlan mode */
5095         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5096                   &q_update_params->update_flags);
5097         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5098                   &q_update_params->update_flags);
5099         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5100
5101         /* in access mode mark mask and value are 0 to strip all vlans */
5102         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5103                 q_update_params->silent_removal_value = 0;
5104                 q_update_params->silent_removal_mask = 0;
5105         } else {
5106                 q_update_params->silent_removal_value =
5107                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5108                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5109         }
5110
5111         for_each_eth_queue(bp, q) {
5112                 /* Set the appropriate Queue object */
5113                 fp = &bp->fp[q];
5114                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5115
5116                 /* send the ramrod */
5117                 rc = bnx2x_queue_state_change(bp, &queue_params);
5118                 if (rc < 0)
5119                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5120                                   q);
5121         }
5122
5123         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5124                 fp = &bp->fp[FCOE_IDX(bp)];
5125                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5126
5127                 /* clear pending completion bit */
5128                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5129
5130                 /* mark latest Q bit */
5131                 smp_mb__before_clear_bit();
5132                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5133                 smp_mb__after_clear_bit();
5134
5135                 /* send Q update ramrod for FCoE Q */
5136                 rc = bnx2x_queue_state_change(bp, &queue_params);
5137                 if (rc < 0)
5138                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5139                                   q);
5140         } else {
5141                 /* If no FCoE ring - ACK MCP now */
5142                 bnx2x_link_report(bp);
5143                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5144         }
5145 }
5146
5147 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5148         struct bnx2x *bp, u32 cid)
5149 {
5150         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5151
5152         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5153                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5154         else
5155                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5156 }
5157
5158 static void bnx2x_eq_int(struct bnx2x *bp)
5159 {
5160         u16 hw_cons, sw_cons, sw_prod;
5161         union event_ring_elem *elem;
5162         u8 echo;
5163         u32 cid;
5164         u8 opcode;
5165         int rc, spqe_cnt = 0;
5166         struct bnx2x_queue_sp_obj *q_obj;
5167         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5168         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5169
5170         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5171
5172         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5173          * when we get the next-page we need to adjust so the loop
5174          * condition below will be met. The next element is the size of a
5175          * regular element and hence incrementing by 1
5176          */
5177         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5178                 hw_cons++;
5179
5180         /* This function may never run in parallel with itself for a
5181          * specific bp, thus there is no need in "paired" read memory
5182          * barrier here.
5183          */
5184         sw_cons = bp->eq_cons;
5185         sw_prod = bp->eq_prod;
5186
5187         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5188                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5189
5190         for (; sw_cons != hw_cons;
5191               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5192
5193                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5194
5195                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5196                 if (!rc) {
5197                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5198                            rc);
5199                         goto next_spqe;
5200                 }
5201
5202                 /* elem CID originates from FW; actually LE */
5203                 cid = SW_CID((__force __le32)
5204                              elem->message.data.cfc_del_event.cid);
5205                 opcode = elem->message.opcode;
5206
5207                 /* handle eq element */
5208                 switch (opcode) {
5209                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5210                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5211                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5212                         continue;
5213
5214                 case EVENT_RING_OPCODE_STAT_QUERY:
5215                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5216                            "got statistics comp event %d\n",
5217                            bp->stats_comp++);
5218                         /* nothing to do with stats comp */
5219                         goto next_spqe;
5220
5221                 case EVENT_RING_OPCODE_CFC_DEL:
5222                         /* handle according to cid range */
5223                         /*
5224                          * we may want to verify here that the bp state is
5225                          * HALTING
5226                          */
5227                         DP(BNX2X_MSG_SP,
5228                            "got delete ramrod for MULTI[%d]\n", cid);
5229
5230                         if (CNIC_LOADED(bp) &&
5231                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5232                                 goto next_spqe;
5233
5234                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5235
5236                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5237                                 break;
5238
5239                         goto next_spqe;
5240
5241                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5242                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5243                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5244                         if (f_obj->complete_cmd(bp, f_obj,
5245                                                 BNX2X_F_CMD_TX_STOP))
5246                                 break;
5247                         goto next_spqe;
5248
5249                 case EVENT_RING_OPCODE_START_TRAFFIC:
5250                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5251                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5252                         if (f_obj->complete_cmd(bp, f_obj,
5253                                                 BNX2X_F_CMD_TX_START))
5254                                 break;
5255                         goto next_spqe;
5256
5257                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5258                         echo = elem->message.data.function_update_event.echo;
5259                         if (echo == SWITCH_UPDATE) {
5260                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5261                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5262                                 if (f_obj->complete_cmd(
5263                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5264                                         break;
5265
5266                         } else {
5267                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5268                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5269                                 f_obj->complete_cmd(bp, f_obj,
5270                                                     BNX2X_F_CMD_AFEX_UPDATE);
5271
5272                                 /* We will perform the Queues update from
5273                                  * sp_rtnl task as all Queue SP operations
5274                                  * should run under rtnl_lock.
5275                                  */
5276                                 smp_mb__before_clear_bit();
5277                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5278                                         &bp->sp_rtnl_state);
5279                                 smp_mb__after_clear_bit();
5280
5281                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5282                         }
5283
5284                         goto next_spqe;
5285
5286                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5287                         f_obj->complete_cmd(bp, f_obj,
5288                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5289                         bnx2x_after_afex_vif_lists(bp, elem);
5290                         goto next_spqe;
5291                 case EVENT_RING_OPCODE_FUNCTION_START:
5292                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5293                            "got FUNC_START ramrod\n");
5294                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5295                                 break;
5296
5297                         goto next_spqe;
5298
5299                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5300                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5301                            "got FUNC_STOP ramrod\n");
5302                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5303                                 break;
5304
5305                         goto next_spqe;
5306                 }
5307
5308                 switch (opcode | bp->state) {
5309                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5310                       BNX2X_STATE_OPEN):
5311                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5312                       BNX2X_STATE_OPENING_WAIT4_PORT):
5313                         cid = elem->message.data.eth_event.echo &
5314                                 BNX2X_SWCID_MASK;
5315                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5316                            cid);
5317                         rss_raw->clear_pending(rss_raw);
5318                         break;
5319
5320                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5321                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5322                 case (EVENT_RING_OPCODE_SET_MAC |
5323                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5324                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5325                       BNX2X_STATE_OPEN):
5326                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5327                       BNX2X_STATE_DIAG):
5328                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5329                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5330                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5331                         bnx2x_handle_classification_eqe(bp, elem);
5332                         break;
5333
5334                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5335                       BNX2X_STATE_OPEN):
5336                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5337                       BNX2X_STATE_DIAG):
5338                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5339                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5340                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5341                         bnx2x_handle_mcast_eqe(bp);
5342                         break;
5343
5344                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5345                       BNX2X_STATE_OPEN):
5346                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5347                       BNX2X_STATE_DIAG):
5348                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5349                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5350                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5351                         bnx2x_handle_rx_mode_eqe(bp);
5352                         break;
5353                 default:
5354                         /* unknown event log error and continue */
5355                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5356                                   elem->message.opcode, bp->state);
5357                 }
5358 next_spqe:
5359                 spqe_cnt++;
5360         } /* for */
5361
5362         smp_mb__before_atomic_inc();
5363         atomic_add(spqe_cnt, &bp->eq_spq_left);
5364
5365         bp->eq_cons = sw_cons;
5366         bp->eq_prod = sw_prod;
5367         /* Make sure that above mem writes were issued towards the memory */
5368         smp_wmb();
5369
5370         /* update producer */
5371         bnx2x_update_eq_prod(bp, bp->eq_prod);
5372 }
5373
5374 static void bnx2x_sp_task(struct work_struct *work)
5375 {
5376         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5377
5378         DP(BNX2X_MSG_SP, "sp task invoked\n");
5379
5380         /* make sure the atomic interrupt_occurred has been written */
5381         smp_rmb();
5382         if (atomic_read(&bp->interrupt_occurred)) {
5383
5384                 /* what work needs to be performed? */
5385                 u16 status = bnx2x_update_dsb_idx(bp);
5386
5387                 DP(BNX2X_MSG_SP, "status %x\n", status);
5388                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5389                 atomic_set(&bp->interrupt_occurred, 0);
5390
5391                 /* HW attentions */
5392                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5393                         bnx2x_attn_int(bp);
5394                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5395                 }
5396
5397                 /* SP events: STAT_QUERY and others */
5398                 if (status & BNX2X_DEF_SB_IDX) {
5399                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5400
5401                 if (FCOE_INIT(bp) &&
5402                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5403                                 /* Prevent local bottom-halves from running as
5404                                  * we are going to change the local NAPI list.
5405                                  */
5406                                 local_bh_disable();
5407                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5408                                 local_bh_enable();
5409                         }
5410
5411                         /* Handle EQ completions */
5412                         bnx2x_eq_int(bp);
5413                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5414                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5415
5416                         status &= ~BNX2X_DEF_SB_IDX;
5417                 }
5418
5419                 /* if status is non zero then perhaps something went wrong */
5420                 if (unlikely(status))
5421                         DP(BNX2X_MSG_SP,
5422                            "got an unknown interrupt! (status 0x%x)\n", status);
5423
5424                 /* ack status block only if something was actually handled */
5425                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5426                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5427         }
5428
5429         /* must be called after the EQ processing (since eq leads to sriov
5430          * ramrod completion flows).
5431          * This flow may have been scheduled by the arrival of a ramrod
5432          * completion, or by the sriov code rescheduling itself.
5433          */
5434         bnx2x_iov_sp_task(bp);
5435
5436         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5437         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5438                                &bp->sp_state)) {
5439                 bnx2x_link_report(bp);
5440                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5441         }
5442 }
5443
5444 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5445 {
5446         struct net_device *dev = dev_instance;
5447         struct bnx2x *bp = netdev_priv(dev);
5448
5449         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5450                      IGU_INT_DISABLE, 0);
5451
5452 #ifdef BNX2X_STOP_ON_ERROR
5453         if (unlikely(bp->panic))
5454                 return IRQ_HANDLED;
5455 #endif
5456
5457         if (CNIC_LOADED(bp)) {
5458                 struct cnic_ops *c_ops;
5459
5460                 rcu_read_lock();
5461                 c_ops = rcu_dereference(bp->cnic_ops);
5462                 if (c_ops)
5463                         c_ops->cnic_handler(bp->cnic_data, NULL);
5464                 rcu_read_unlock();
5465         }
5466
5467         /* schedule sp task to perform default status block work, ack
5468          * attentions and enable interrupts.
5469          */
5470         bnx2x_schedule_sp_task(bp);
5471
5472         return IRQ_HANDLED;
5473 }
5474
5475 /* end of slow path */
5476
5477 void bnx2x_drv_pulse(struct bnx2x *bp)
5478 {
5479         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5480                  bp->fw_drv_pulse_wr_seq);
5481 }
5482
5483 static void bnx2x_timer(unsigned long data)
5484 {
5485         struct bnx2x *bp = (struct bnx2x *) data;
5486
5487         if (!netif_running(bp->dev))
5488                 return;
5489
5490         if (IS_PF(bp) &&
5491             !BP_NOMCP(bp)) {
5492                 int mb_idx = BP_FW_MB_IDX(bp);
5493                 u16 drv_pulse;
5494                 u16 mcp_pulse;
5495
5496                 ++bp->fw_drv_pulse_wr_seq;
5497                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5498                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5499                 bnx2x_drv_pulse(bp);
5500
5501                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5502                              MCP_PULSE_SEQ_MASK);
5503                 /* The delta between driver pulse and mcp response
5504                  * should not get too big. If the MFW is more than 5 pulses
5505                  * behind, we should worry about it enough to generate an error
5506                  * log.
5507                  */
5508                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5509                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5510                                   drv_pulse, mcp_pulse);
5511         }
5512
5513         if (bp->state == BNX2X_STATE_OPEN)
5514                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5515
5516         /* sample pf vf bulletin board for new posts from pf */
5517         if (IS_VF(bp))
5518                 bnx2x_timer_sriov(bp);
5519
5520         mod_timer(&bp->timer, jiffies + bp->current_interval);
5521 }
5522
5523 /* end of Statistics */
5524
5525 /* nic init */
5526
5527 /*
5528  * nic init service functions
5529  */
5530
5531 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5532 {
5533         u32 i;
5534         if (!(len%4) && !(addr%4))
5535                 for (i = 0; i < len; i += 4)
5536                         REG_WR(bp, addr + i, fill);
5537         else
5538                 for (i = 0; i < len; i++)
5539                         REG_WR8(bp, addr + i, fill);
5540 }
5541
5542 /* helper: writes FP SP data to FW - data_size in dwords */
5543 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5544                                 int fw_sb_id,
5545                                 u32 *sb_data_p,
5546                                 u32 data_size)
5547 {
5548         int index;
5549         for (index = 0; index < data_size; index++)
5550                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5551                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5552                         sizeof(u32)*index,
5553                         *(sb_data_p + index));
5554 }
5555
5556 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5557 {
5558         u32 *sb_data_p;
5559         u32 data_size = 0;
5560         struct hc_status_block_data_e2 sb_data_e2;
5561         struct hc_status_block_data_e1x sb_data_e1x;
5562
5563         /* disable the function first */
5564         if (!CHIP_IS_E1x(bp)) {
5565                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5566                 sb_data_e2.common.state = SB_DISABLED;
5567                 sb_data_e2.common.p_func.vf_valid = false;
5568                 sb_data_p = (u32 *)&sb_data_e2;
5569                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5570         } else {
5571                 memset(&sb_data_e1x, 0,
5572                        sizeof(struct hc_status_block_data_e1x));
5573                 sb_data_e1x.common.state = SB_DISABLED;
5574                 sb_data_e1x.common.p_func.vf_valid = false;
5575                 sb_data_p = (u32 *)&sb_data_e1x;
5576                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5577         }
5578         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5579
5580         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5581                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5582                         CSTORM_STATUS_BLOCK_SIZE);
5583         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5584                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5585                         CSTORM_SYNC_BLOCK_SIZE);
5586 }
5587
5588 /* helper:  writes SP SB data to FW */
5589 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5590                 struct hc_sp_status_block_data *sp_sb_data)
5591 {
5592         int func = BP_FUNC(bp);
5593         int i;
5594         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5595                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5596                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5597                         i*sizeof(u32),
5598                         *((u32 *)sp_sb_data + i));
5599 }
5600
5601 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5602 {
5603         int func = BP_FUNC(bp);
5604         struct hc_sp_status_block_data sp_sb_data;
5605         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5606
5607         sp_sb_data.state = SB_DISABLED;
5608         sp_sb_data.p_func.vf_valid = false;
5609
5610         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5611
5612         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5613                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5614                         CSTORM_SP_STATUS_BLOCK_SIZE);
5615         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5616                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5617                         CSTORM_SP_SYNC_BLOCK_SIZE);
5618 }
5619
5620 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5621                                            int igu_sb_id, int igu_seg_id)
5622 {
5623         hc_sm->igu_sb_id = igu_sb_id;
5624         hc_sm->igu_seg_id = igu_seg_id;
5625         hc_sm->timer_value = 0xFF;
5626         hc_sm->time_to_expire = 0xFFFFFFFF;
5627 }
5628
5629 /* allocates state machine ids. */
5630 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5631 {
5632         /* zero out state machine indices */
5633         /* rx indices */
5634         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5635
5636         /* tx indices */
5637         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5638         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5639         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5640         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5641
5642         /* map indices */
5643         /* rx indices */
5644         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5645                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5646
5647         /* tx indices */
5648         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5649                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5650         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5651                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5652         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5653                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5654         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5655                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5656 }
5657
5658 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5659                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5660 {
5661         int igu_seg_id;
5662
5663         struct hc_status_block_data_e2 sb_data_e2;
5664         struct hc_status_block_data_e1x sb_data_e1x;
5665         struct hc_status_block_sm  *hc_sm_p;
5666         int data_size;
5667         u32 *sb_data_p;
5668
5669         if (CHIP_INT_MODE_IS_BC(bp))
5670                 igu_seg_id = HC_SEG_ACCESS_NORM;
5671         else
5672                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5673
5674         bnx2x_zero_fp_sb(bp, fw_sb_id);
5675
5676         if (!CHIP_IS_E1x(bp)) {
5677                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5678                 sb_data_e2.common.state = SB_ENABLED;
5679                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5680                 sb_data_e2.common.p_func.vf_id = vfid;
5681                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5682                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5683                 sb_data_e2.common.same_igu_sb_1b = true;
5684                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5685                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5686                 hc_sm_p = sb_data_e2.common.state_machine;
5687                 sb_data_p = (u32 *)&sb_data_e2;
5688                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5689                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5690         } else {
5691                 memset(&sb_data_e1x, 0,
5692                        sizeof(struct hc_status_block_data_e1x));
5693                 sb_data_e1x.common.state = SB_ENABLED;
5694                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5695                 sb_data_e1x.common.p_func.vf_id = 0xff;
5696                 sb_data_e1x.common.p_func.vf_valid = false;
5697                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5698                 sb_data_e1x.common.same_igu_sb_1b = true;
5699                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5700                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5701                 hc_sm_p = sb_data_e1x.common.state_machine;
5702                 sb_data_p = (u32 *)&sb_data_e1x;
5703                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5704                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5705         }
5706
5707         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5708                                        igu_sb_id, igu_seg_id);
5709         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5710                                        igu_sb_id, igu_seg_id);
5711
5712         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5713
5714         /* write indices to HW - PCI guarantees endianity of regpairs */
5715         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5716 }
5717
5718 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5719                                      u16 tx_usec, u16 rx_usec)
5720 {
5721         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5722                                     false, rx_usec);
5723         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5724                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5725                                        tx_usec);
5726         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5727                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5728                                        tx_usec);
5729         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5730                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5731                                        tx_usec);
5732 }
5733
5734 static void bnx2x_init_def_sb(struct bnx2x *bp)
5735 {
5736         struct host_sp_status_block *def_sb = bp->def_status_blk;
5737         dma_addr_t mapping = bp->def_status_blk_mapping;
5738         int igu_sp_sb_index;
5739         int igu_seg_id;
5740         int port = BP_PORT(bp);
5741         int func = BP_FUNC(bp);
5742         int reg_offset, reg_offset_en5;
5743         u64 section;
5744         int index;
5745         struct hc_sp_status_block_data sp_sb_data;
5746         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5747
5748         if (CHIP_INT_MODE_IS_BC(bp)) {
5749                 igu_sp_sb_index = DEF_SB_IGU_ID;
5750                 igu_seg_id = HC_SEG_ACCESS_DEF;
5751         } else {
5752                 igu_sp_sb_index = bp->igu_dsb_id;
5753                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5754         }
5755
5756         /* ATTN */
5757         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5758                                             atten_status_block);
5759         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5760
5761         bp->attn_state = 0;
5762
5763         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5764                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5765         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5766                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5767         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5768                 int sindex;
5769                 /* take care of sig[0]..sig[4] */
5770                 for (sindex = 0; sindex < 4; sindex++)
5771                         bp->attn_group[index].sig[sindex] =
5772                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5773
5774                 if (!CHIP_IS_E1x(bp))
5775                         /*
5776                          * enable5 is separate from the rest of the registers,
5777                          * and therefore the address skip is 4
5778                          * and not 16 between the different groups
5779                          */
5780                         bp->attn_group[index].sig[4] = REG_RD(bp,
5781                                         reg_offset_en5 + 0x4*index);
5782                 else
5783                         bp->attn_group[index].sig[4] = 0;
5784         }
5785
5786         if (bp->common.int_block == INT_BLOCK_HC) {
5787                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5788                                      HC_REG_ATTN_MSG0_ADDR_L);
5789
5790                 REG_WR(bp, reg_offset, U64_LO(section));
5791                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5792         } else if (!CHIP_IS_E1x(bp)) {
5793                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5794                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5795         }
5796
5797         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5798                                             sp_sb);
5799
5800         bnx2x_zero_sp_sb(bp);
5801
5802         /* PCI guarantees endianity of regpairs */
5803         sp_sb_data.state                = SB_ENABLED;
5804         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5805         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5806         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5807         sp_sb_data.igu_seg_id           = igu_seg_id;
5808         sp_sb_data.p_func.pf_id         = func;
5809         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5810         sp_sb_data.p_func.vf_id         = 0xff;
5811
5812         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5813
5814         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5815 }
5816
5817 void bnx2x_update_coalesce(struct bnx2x *bp)
5818 {
5819         int i;
5820
5821         for_each_eth_queue(bp, i)
5822                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5823                                          bp->tx_ticks, bp->rx_ticks);
5824 }
5825
5826 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5827 {
5828         spin_lock_init(&bp->spq_lock);
5829         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5830
5831         bp->spq_prod_idx = 0;
5832         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5833         bp->spq_prod_bd = bp->spq;
5834         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5835 }
5836
5837 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5838 {
5839         int i;
5840         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5841                 union event_ring_elem *elem =
5842                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5843
5844                 elem->next_page.addr.hi =
5845                         cpu_to_le32(U64_HI(bp->eq_mapping +
5846                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5847                 elem->next_page.addr.lo =
5848                         cpu_to_le32(U64_LO(bp->eq_mapping +
5849                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5850         }
5851         bp->eq_cons = 0;
5852         bp->eq_prod = NUM_EQ_DESC;
5853         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5854         /* we want a warning message before it gets wrought... */
5855         atomic_set(&bp->eq_spq_left,
5856                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5857 }
5858
5859 /* called with netif_addr_lock_bh() */
5860 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5861                         unsigned long rx_mode_flags,
5862                         unsigned long rx_accept_flags,
5863                         unsigned long tx_accept_flags,
5864                         unsigned long ramrod_flags)
5865 {
5866         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5867         int rc;
5868
5869         memset(&ramrod_param, 0, sizeof(ramrod_param));
5870
5871         /* Prepare ramrod parameters */
5872         ramrod_param.cid = 0;
5873         ramrod_param.cl_id = cl_id;
5874         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5875         ramrod_param.func_id = BP_FUNC(bp);
5876
5877         ramrod_param.pstate = &bp->sp_state;
5878         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5879
5880         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5881         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5882
5883         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5884
5885         ramrod_param.ramrod_flags = ramrod_flags;
5886         ramrod_param.rx_mode_flags = rx_mode_flags;
5887
5888         ramrod_param.rx_accept_flags = rx_accept_flags;
5889         ramrod_param.tx_accept_flags = tx_accept_flags;
5890
5891         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5892         if (rc < 0) {
5893                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5894                 return rc;
5895         }
5896
5897         return 0;
5898 }
5899
5900 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5901                                    unsigned long *rx_accept_flags,
5902                                    unsigned long *tx_accept_flags)
5903 {
5904         /* Clear the flags first */
5905         *rx_accept_flags = 0;
5906         *tx_accept_flags = 0;
5907
5908         switch (rx_mode) {
5909         case BNX2X_RX_MODE_NONE:
5910                 /*
5911                  * 'drop all' supersedes any accept flags that may have been
5912                  * passed to the function.
5913                  */
5914                 break;
5915         case BNX2X_RX_MODE_NORMAL:
5916                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5917                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5918                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5919
5920                 /* internal switching mode */
5921                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5922                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5923                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5924
5925                 break;
5926         case BNX2X_RX_MODE_ALLMULTI:
5927                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5928                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5929                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5930
5931                 /* internal switching mode */
5932                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5933                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5934                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5935
5936                 break;
5937         case BNX2X_RX_MODE_PROMISC:
5938                 /* According to definition of SI mode, iface in promisc mode
5939                  * should receive matched and unmatched (in resolution of port)
5940                  * unicast packets.
5941                  */
5942                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5943                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5944                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5945                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5946
5947                 /* internal switching mode */
5948                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5949                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5950
5951                 if (IS_MF_SI(bp))
5952                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5953                 else
5954                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5955
5956                 break;
5957         default:
5958                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5959                 return -EINVAL;
5960         }
5961
5962         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5963         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5964                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5965                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5966         }
5967
5968         return 0;
5969 }
5970
5971 /* called with netif_addr_lock_bh() */
5972 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5973 {
5974         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5975         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5976         int rc;
5977
5978         if (!NO_FCOE(bp))
5979                 /* Configure rx_mode of FCoE Queue */
5980                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5981
5982         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5983                                      &tx_accept_flags);
5984         if (rc)
5985                 return rc;
5986
5987         __set_bit(RAMROD_RX, &ramrod_flags);
5988         __set_bit(RAMROD_TX, &ramrod_flags);
5989
5990         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5991                                    rx_accept_flags, tx_accept_flags,
5992                                    ramrod_flags);
5993 }
5994
5995 static void bnx2x_init_internal_common(struct bnx2x *bp)
5996 {
5997         int i;
5998
5999         if (IS_MF_SI(bp))
6000                 /*
6001                  * In switch independent mode, the TSTORM needs to accept
6002                  * packets that failed classification, since approximate match
6003                  * mac addresses aren't written to NIG LLH
6004                  */
6005                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6006                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
6007         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
6008                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6009                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
6010
6011         /* Zero this manually as its initialization is
6012            currently missing in the initTool */
6013         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6014                 REG_WR(bp, BAR_USTRORM_INTMEM +
6015                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6016         if (!CHIP_IS_E1x(bp)) {
6017                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6018                         CHIP_INT_MODE_IS_BC(bp) ?
6019                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6020         }
6021 }
6022
6023 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6024 {
6025         switch (load_code) {
6026         case FW_MSG_CODE_DRV_LOAD_COMMON:
6027         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6028                 bnx2x_init_internal_common(bp);
6029                 /* no break */
6030
6031         case FW_MSG_CODE_DRV_LOAD_PORT:
6032                 /* nothing to do */
6033                 /* no break */
6034
6035         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6036                 /* internal memory per function is
6037                    initialized inside bnx2x_pf_init */
6038                 break;
6039
6040         default:
6041                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6042                 break;
6043         }
6044 }
6045
6046 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6047 {
6048         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6049 }
6050
6051 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6052 {
6053         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6054 }
6055
6056 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6057 {
6058         if (CHIP_IS_E1x(fp->bp))
6059                 return BP_L_ID(fp->bp) + fp->index;
6060         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6061                 return bnx2x_fp_igu_sb_id(fp);
6062 }
6063
6064 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6065 {
6066         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6067         u8 cos;
6068         unsigned long q_type = 0;
6069         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6070         fp->rx_queue = fp_idx;
6071         fp->cid = fp_idx;
6072         fp->cl_id = bnx2x_fp_cl_id(fp);
6073         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6074         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6075         /* qZone id equals to FW (per path) client id */
6076         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6077
6078         /* init shortcut */
6079         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6080
6081         /* Setup SB indices */
6082         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6083
6084         /* Configure Queue State object */
6085         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6086         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6087
6088         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6089
6090         /* init tx data */
6091         for_each_cos_in_tx_queue(fp, cos) {
6092                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6093                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6094                                   FP_COS_TO_TXQ(fp, cos, bp),
6095                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6096                 cids[cos] = fp->txdata_ptr[cos]->cid;
6097         }
6098
6099         /* nothing more for vf to do here */
6100         if (IS_VF(bp))
6101                 return;
6102
6103         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6104                       fp->fw_sb_id, fp->igu_sb_id);
6105         bnx2x_update_fpsb_idx(fp);
6106         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6107                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6108                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6109
6110         /**
6111          * Configure classification DBs: Always enable Tx switching
6112          */
6113         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6114
6115         DP(NETIF_MSG_IFUP,
6116            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6117            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6118            fp->igu_sb_id);
6119 }
6120
6121 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6122 {
6123         int i;
6124
6125         for (i = 1; i <= NUM_TX_RINGS; i++) {
6126                 struct eth_tx_next_bd *tx_next_bd =
6127                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6128
6129                 tx_next_bd->addr_hi =
6130                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6131                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6132                 tx_next_bd->addr_lo =
6133                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6134                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6135         }
6136
6137         *txdata->tx_cons_sb = cpu_to_le16(0);
6138
6139         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6140         txdata->tx_db.data.zero_fill1 = 0;
6141         txdata->tx_db.data.prod = 0;
6142
6143         txdata->tx_pkt_prod = 0;
6144         txdata->tx_pkt_cons = 0;
6145         txdata->tx_bd_prod = 0;
6146         txdata->tx_bd_cons = 0;
6147         txdata->tx_pkt = 0;
6148 }
6149
6150 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6151 {
6152         int i;
6153
6154         for_each_tx_queue_cnic(bp, i)
6155                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6156 }
6157
6158 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6159 {
6160         int i;
6161         u8 cos;
6162
6163         for_each_eth_queue(bp, i)
6164                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6165                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6166 }
6167
6168 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6169 {
6170         if (!NO_FCOE(bp))
6171                 bnx2x_init_fcoe_fp(bp);
6172
6173         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6174                       BNX2X_VF_ID_INVALID, false,
6175                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6176
6177         /* ensure status block indices were read */
6178         rmb();
6179         bnx2x_init_rx_rings_cnic(bp);
6180         bnx2x_init_tx_rings_cnic(bp);
6181
6182         /* flush all */
6183         mb();
6184         mmiowb();
6185 }
6186
6187 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6188 {
6189         int i;
6190
6191         /* Setup NIC internals and enable interrupts */
6192         for_each_eth_queue(bp, i)
6193                 bnx2x_init_eth_fp(bp, i);
6194
6195         /* ensure status block indices were read */
6196         rmb();
6197         bnx2x_init_rx_rings(bp);
6198         bnx2x_init_tx_rings(bp);
6199
6200         if (IS_PF(bp)) {
6201                 /* Initialize MOD_ABS interrupts */
6202                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6203                                        bp->common.shmem_base,
6204                                        bp->common.shmem2_base, BP_PORT(bp));
6205
6206                 /* initialize the default status block and sp ring */
6207                 bnx2x_init_def_sb(bp);
6208                 bnx2x_update_dsb_idx(bp);
6209                 bnx2x_init_sp_ring(bp);
6210         } else {
6211                 bnx2x_memset_stats(bp);
6212         }
6213 }
6214
6215 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6216 {
6217         bnx2x_init_eq_ring(bp);
6218         bnx2x_init_internal(bp, load_code);
6219         bnx2x_pf_init(bp);
6220         bnx2x_stats_init(bp);
6221
6222         /* flush all before enabling interrupts */
6223         mb();
6224         mmiowb();
6225
6226         bnx2x_int_enable(bp);
6227
6228         /* Check for SPIO5 */
6229         bnx2x_attn_int_deasserted0(bp,
6230                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6231                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6232 }
6233
6234 /* gzip service functions */
6235 static int bnx2x_gunzip_init(struct bnx2x *bp)
6236 {
6237         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6238                                             &bp->gunzip_mapping, GFP_KERNEL);
6239         if (bp->gunzip_buf  == NULL)
6240                 goto gunzip_nomem1;
6241
6242         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6243         if (bp->strm  == NULL)
6244                 goto gunzip_nomem2;
6245
6246         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6247         if (bp->strm->workspace == NULL)
6248                 goto gunzip_nomem3;
6249
6250         return 0;
6251
6252 gunzip_nomem3:
6253         kfree(bp->strm);
6254         bp->strm = NULL;
6255
6256 gunzip_nomem2:
6257         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6258                           bp->gunzip_mapping);
6259         bp->gunzip_buf = NULL;
6260
6261 gunzip_nomem1:
6262         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6263         return -ENOMEM;
6264 }
6265
6266 static void bnx2x_gunzip_end(struct bnx2x *bp)
6267 {
6268         if (bp->strm) {
6269                 vfree(bp->strm->workspace);
6270                 kfree(bp->strm);
6271                 bp->strm = NULL;
6272         }
6273
6274         if (bp->gunzip_buf) {
6275                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6276                                   bp->gunzip_mapping);
6277                 bp->gunzip_buf = NULL;
6278         }
6279 }
6280
6281 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6282 {
6283         int n, rc;
6284
6285         /* check gzip header */
6286         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6287                 BNX2X_ERR("Bad gzip header\n");
6288                 return -EINVAL;
6289         }
6290
6291         n = 10;
6292
6293 #define FNAME                           0x8
6294
6295         if (zbuf[3] & FNAME)
6296                 while ((zbuf[n++] != 0) && (n < len));
6297
6298         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6299         bp->strm->avail_in = len - n;
6300         bp->strm->next_out = bp->gunzip_buf;
6301         bp->strm->avail_out = FW_BUF_SIZE;
6302
6303         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6304         if (rc != Z_OK)
6305                 return rc;
6306
6307         rc = zlib_inflate(bp->strm, Z_FINISH);
6308         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6309                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6310                            bp->strm->msg);
6311
6312         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6313         if (bp->gunzip_outlen & 0x3)
6314                 netdev_err(bp->dev,
6315                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6316                                 bp->gunzip_outlen);
6317         bp->gunzip_outlen >>= 2;
6318
6319         zlib_inflateEnd(bp->strm);
6320
6321         if (rc == Z_STREAM_END)
6322                 return 0;
6323
6324         return rc;
6325 }
6326
6327 /* nic load/unload */
6328
6329 /*
6330  * General service functions
6331  */
6332
6333 /* send a NIG loopback debug packet */
6334 static void bnx2x_lb_pckt(struct bnx2x *bp)
6335 {
6336         u32 wb_write[3];
6337
6338         /* Ethernet source and destination addresses */
6339         wb_write[0] = 0x55555555;
6340         wb_write[1] = 0x55555555;
6341         wb_write[2] = 0x20;             /* SOP */
6342         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6343
6344         /* NON-IP protocol */
6345         wb_write[0] = 0x09000000;
6346         wb_write[1] = 0x55555555;
6347         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6348         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6349 }
6350
6351 /* some of the internal memories
6352  * are not directly readable from the driver
6353  * to test them we send debug packets
6354  */
6355 static int bnx2x_int_mem_test(struct bnx2x *bp)
6356 {
6357         int factor;
6358         int count, i;
6359         u32 val = 0;
6360
6361         if (CHIP_REV_IS_FPGA(bp))
6362                 factor = 120;
6363         else if (CHIP_REV_IS_EMUL(bp))
6364                 factor = 200;
6365         else
6366                 factor = 1;
6367
6368         /* Disable inputs of parser neighbor blocks */
6369         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6370         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6371         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6372         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6373
6374         /*  Write 0 to parser credits for CFC search request */
6375         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6376
6377         /* send Ethernet packet */
6378         bnx2x_lb_pckt(bp);
6379
6380         /* TODO do i reset NIG statistic? */
6381         /* Wait until NIG register shows 1 packet of size 0x10 */
6382         count = 1000 * factor;
6383         while (count) {
6384
6385                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6386                 val = *bnx2x_sp(bp, wb_data[0]);
6387                 if (val == 0x10)
6388                         break;
6389
6390                 usleep_range(10000, 20000);
6391                 count--;
6392         }
6393         if (val != 0x10) {
6394                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6395                 return -1;
6396         }
6397
6398         /* Wait until PRS register shows 1 packet */
6399         count = 1000 * factor;
6400         while (count) {
6401                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6402                 if (val == 1)
6403                         break;
6404
6405                 usleep_range(10000, 20000);
6406                 count--;
6407         }
6408         if (val != 0x1) {
6409                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6410                 return -2;
6411         }
6412
6413         /* Reset and init BRB, PRS */
6414         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6415         msleep(50);
6416         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6417         msleep(50);
6418         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6419         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6420
6421         DP(NETIF_MSG_HW, "part2\n");
6422
6423         /* Disable inputs of parser neighbor blocks */
6424         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6425         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6426         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6427         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6428
6429         /* Write 0 to parser credits for CFC search request */
6430         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6431
6432         /* send 10 Ethernet packets */
6433         for (i = 0; i < 10; i++)
6434                 bnx2x_lb_pckt(bp);
6435
6436         /* Wait until NIG register shows 10 + 1
6437            packets of size 11*0x10 = 0xb0 */
6438         count = 1000 * factor;
6439         while (count) {
6440
6441                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6442                 val = *bnx2x_sp(bp, wb_data[0]);
6443                 if (val == 0xb0)
6444                         break;
6445
6446                 usleep_range(10000, 20000);
6447                 count--;
6448         }
6449         if (val != 0xb0) {
6450                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6451                 return -3;
6452         }
6453
6454         /* Wait until PRS register shows 2 packets */
6455         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6456         if (val != 2)
6457                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6458
6459         /* Write 1 to parser credits for CFC search request */
6460         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6461
6462         /* Wait until PRS register shows 3 packets */
6463         msleep(10 * factor);
6464         /* Wait until NIG register shows 1 packet of size 0x10 */
6465         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6466         if (val != 3)
6467                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6468
6469         /* clear NIG EOP FIFO */
6470         for (i = 0; i < 11; i++)
6471                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6472         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6473         if (val != 1) {
6474                 BNX2X_ERR("clear of NIG failed\n");
6475                 return -4;
6476         }
6477
6478         /* Reset and init BRB, PRS, NIG */
6479         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6480         msleep(50);
6481         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6482         msleep(50);
6483         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6484         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6485         if (!CNIC_SUPPORT(bp))
6486                 /* set NIC mode */
6487                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6488
6489         /* Enable inputs of parser neighbor blocks */
6490         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6491         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6492         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6493         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6494
6495         DP(NETIF_MSG_HW, "done\n");
6496
6497         return 0; /* OK */
6498 }
6499
6500 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6501 {
6502         u32 val;
6503
6504         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6505         if (!CHIP_IS_E1x(bp))
6506                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6507         else
6508                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6509         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6510         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6511         /*
6512          * mask read length error interrupts in brb for parser
6513          * (parsing unit and 'checksum and crc' unit)
6514          * these errors are legal (PU reads fixed length and CAC can cause
6515          * read length error on truncated packets)
6516          */
6517         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6518         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6519         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6520         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6521         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6522         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6523 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6524 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6525         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6526         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6527         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6528 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6529 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6530         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6531         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6532         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6533         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6534 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6535 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6536
6537         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6538                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6539                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6540         if (!CHIP_IS_E1x(bp))
6541                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6542                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6543         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6544
6545         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6546         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6547         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6548 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6549
6550         if (!CHIP_IS_E1x(bp))
6551                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6552                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6553
6554         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6555         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6556 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6557         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6558 }
6559
6560 static void bnx2x_reset_common(struct bnx2x *bp)
6561 {
6562         u32 val = 0x1400;
6563
6564         /* reset_common */
6565         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6566                0xd3ffff7f);
6567
6568         if (CHIP_IS_E3(bp)) {
6569                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6570                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6571         }
6572
6573         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6574 }
6575
6576 static void bnx2x_setup_dmae(struct bnx2x *bp)
6577 {
6578         bp->dmae_ready = 0;
6579         spin_lock_init(&bp->dmae_lock);
6580 }
6581
6582 static void bnx2x_init_pxp(struct bnx2x *bp)
6583 {
6584         u16 devctl;
6585         int r_order, w_order;
6586
6587         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6588         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6589         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6590         if (bp->mrrs == -1)
6591                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6592         else {
6593                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6594                 r_order = bp->mrrs;
6595         }
6596
6597         bnx2x_init_pxp_arb(bp, r_order, w_order);
6598 }
6599
6600 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6601 {
6602         int is_required;
6603         u32 val;
6604         int port;
6605
6606         if (BP_NOMCP(bp))
6607                 return;
6608
6609         is_required = 0;
6610         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6611               SHARED_HW_CFG_FAN_FAILURE_MASK;
6612
6613         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6614                 is_required = 1;
6615
6616         /*
6617          * The fan failure mechanism is usually related to the PHY type since
6618          * the power consumption of the board is affected by the PHY. Currently,
6619          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6620          */
6621         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6622                 for (port = PORT_0; port < PORT_MAX; port++) {
6623                         is_required |=
6624                                 bnx2x_fan_failure_det_req(
6625                                         bp,
6626                                         bp->common.shmem_base,
6627                                         bp->common.shmem2_base,
6628                                         port);
6629                 }
6630
6631         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6632
6633         if (is_required == 0)
6634                 return;
6635
6636         /* Fan failure is indicated by SPIO 5 */
6637         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6638
6639         /* set to active low mode */
6640         val = REG_RD(bp, MISC_REG_SPIO_INT);
6641         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6642         REG_WR(bp, MISC_REG_SPIO_INT, val);
6643
6644         /* enable interrupt to signal the IGU */
6645         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6646         val |= MISC_SPIO_SPIO5;
6647         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6648 }
6649
6650 void bnx2x_pf_disable(struct bnx2x *bp)
6651 {
6652         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6653         val &= ~IGU_PF_CONF_FUNC_EN;
6654
6655         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6656         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6657         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6658 }
6659
6660 static void bnx2x__common_init_phy(struct bnx2x *bp)
6661 {
6662         u32 shmem_base[2], shmem2_base[2];
6663         /* Avoid common init in case MFW supports LFA */
6664         if (SHMEM2_RD(bp, size) >
6665             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6666                 return;
6667         shmem_base[0] =  bp->common.shmem_base;
6668         shmem2_base[0] = bp->common.shmem2_base;
6669         if (!CHIP_IS_E1x(bp)) {
6670                 shmem_base[1] =
6671                         SHMEM2_RD(bp, other_shmem_base_addr);
6672                 shmem2_base[1] =
6673                         SHMEM2_RD(bp, other_shmem2_base_addr);
6674         }
6675         bnx2x_acquire_phy_lock(bp);
6676         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6677                               bp->common.chip_id);
6678         bnx2x_release_phy_lock(bp);
6679 }
6680
6681 /**
6682  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6683  *
6684  * @bp:         driver handle
6685  */
6686 static int bnx2x_init_hw_common(struct bnx2x *bp)
6687 {
6688         u32 val;
6689
6690         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6691
6692         /*
6693          * take the RESET lock to protect undi_unload flow from accessing
6694          * registers while we're resetting the chip
6695          */
6696         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6697
6698         bnx2x_reset_common(bp);
6699         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6700
6701         val = 0xfffc;
6702         if (CHIP_IS_E3(bp)) {
6703                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6704                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6705         }
6706         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6707
6708         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6709
6710         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6711
6712         if (!CHIP_IS_E1x(bp)) {
6713                 u8 abs_func_id;
6714
6715                 /**
6716                  * 4-port mode or 2-port mode we need to turn of master-enable
6717                  * for everyone, after that, turn it back on for self.
6718                  * so, we disregard multi-function or not, and always disable
6719                  * for all functions on the given path, this means 0,2,4,6 for
6720                  * path 0 and 1,3,5,7 for path 1
6721                  */
6722                 for (abs_func_id = BP_PATH(bp);
6723                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6724                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6725                                 REG_WR(bp,
6726                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6727                                     1);
6728                                 continue;
6729                         }
6730
6731                         bnx2x_pretend_func(bp, abs_func_id);
6732                         /* clear pf enable */
6733                         bnx2x_pf_disable(bp);
6734                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6735                 }
6736         }
6737
6738         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6739         if (CHIP_IS_E1(bp)) {
6740                 /* enable HW interrupt from PXP on USDM overflow
6741                    bit 16 on INT_MASK_0 */
6742                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6743         }
6744
6745         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6746         bnx2x_init_pxp(bp);
6747
6748 #ifdef __BIG_ENDIAN
6749         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6750         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6751         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6752         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6753         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6754         /* make sure this value is 0 */
6755         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6756
6757 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6758         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6759         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6760         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6761         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6762 #endif
6763
6764         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6765
6766         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6767                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6768
6769         /* let the HW do it's magic ... */
6770         msleep(100);
6771         /* finish PXP init */
6772         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6773         if (val != 1) {
6774                 BNX2X_ERR("PXP2 CFG failed\n");
6775                 return -EBUSY;
6776         }
6777         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6778         if (val != 1) {
6779                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6780                 return -EBUSY;
6781         }
6782
6783         /* Timers bug workaround E2 only. We need to set the entire ILT to
6784          * have entries with value "0" and valid bit on.
6785          * This needs to be done by the first PF that is loaded in a path
6786          * (i.e. common phase)
6787          */
6788         if (!CHIP_IS_E1x(bp)) {
6789 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6790  * (i.e. vnic3) to start even if it is marked as "scan-off".
6791  * This occurs when a different function (func2,3) is being marked
6792  * as "scan-off". Real-life scenario for example: if a driver is being
6793  * load-unloaded while func6,7 are down. This will cause the timer to access
6794  * the ilt, translate to a logical address and send a request to read/write.
6795  * Since the ilt for the function that is down is not valid, this will cause
6796  * a translation error which is unrecoverable.
6797  * The Workaround is intended to make sure that when this happens nothing fatal
6798  * will occur. The workaround:
6799  *      1.  First PF driver which loads on a path will:
6800  *              a.  After taking the chip out of reset, by using pretend,
6801  *                  it will write "0" to the following registers of
6802  *                  the other vnics.
6803  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6804  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6805  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6806  *                  And for itself it will write '1' to
6807  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6808  *                  dmae-operations (writing to pram for example.)
6809  *                  note: can be done for only function 6,7 but cleaner this
6810  *                        way.
6811  *              b.  Write zero+valid to the entire ILT.
6812  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6813  *                  VNIC3 (of that port). The range allocated will be the
6814  *                  entire ILT. This is needed to prevent  ILT range error.
6815  *      2.  Any PF driver load flow:
6816  *              a.  ILT update with the physical addresses of the allocated
6817  *                  logical pages.
6818  *              b.  Wait 20msec. - note that this timeout is needed to make
6819  *                  sure there are no requests in one of the PXP internal
6820  *                  queues with "old" ILT addresses.
6821  *              c.  PF enable in the PGLC.
6822  *              d.  Clear the was_error of the PF in the PGLC. (could have
6823  *                  occurred while driver was down)
6824  *              e.  PF enable in the CFC (WEAK + STRONG)
6825  *              f.  Timers scan enable
6826  *      3.  PF driver unload flow:
6827  *              a.  Clear the Timers scan_en.
6828  *              b.  Polling for scan_on=0 for that PF.
6829  *              c.  Clear the PF enable bit in the PXP.
6830  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6831  *              e.  Write zero+valid to all ILT entries (The valid bit must
6832  *                  stay set)
6833  *              f.  If this is VNIC 3 of a port then also init
6834  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6835  *                  to the last entry in the ILT.
6836  *
6837  *      Notes:
6838  *      Currently the PF error in the PGLC is non recoverable.
6839  *      In the future the there will be a recovery routine for this error.
6840  *      Currently attention is masked.
6841  *      Having an MCP lock on the load/unload process does not guarantee that
6842  *      there is no Timer disable during Func6/7 enable. This is because the
6843  *      Timers scan is currently being cleared by the MCP on FLR.
6844  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6845  *      there is error before clearing it. But the flow above is simpler and
6846  *      more general.
6847  *      All ILT entries are written by zero+valid and not just PF6/7
6848  *      ILT entries since in the future the ILT entries allocation for
6849  *      PF-s might be dynamic.
6850  */
6851                 struct ilt_client_info ilt_cli;
6852                 struct bnx2x_ilt ilt;
6853                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6854                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6855
6856                 /* initialize dummy TM client */
6857                 ilt_cli.start = 0;
6858                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6859                 ilt_cli.client_num = ILT_CLIENT_TM;
6860
6861                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6862                  * Step 2: set the timers first/last ilt entry to point
6863                  * to the entire range to prevent ILT range error for 3rd/4th
6864                  * vnic (this code assumes existence of the vnic)
6865                  *
6866                  * both steps performed by call to bnx2x_ilt_client_init_op()
6867                  * with dummy TM client
6868                  *
6869                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6870                  * and his brother are split registers
6871                  */
6872                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6873                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6874                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6875
6876                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6877                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6878                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6879         }
6880
6881         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6882         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6883
6884         if (!CHIP_IS_E1x(bp)) {
6885                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6886                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6887                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6888
6889                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6890
6891                 /* let the HW do it's magic ... */
6892                 do {
6893                         msleep(200);
6894                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6895                 } while (factor-- && (val != 1));
6896
6897                 if (val != 1) {
6898                         BNX2X_ERR("ATC_INIT failed\n");
6899                         return -EBUSY;
6900                 }
6901         }
6902
6903         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6904
6905         bnx2x_iov_init_dmae(bp);
6906
6907         /* clean the DMAE memory */
6908         bp->dmae_ready = 1;
6909         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6910
6911         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6912
6913         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6914
6915         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6916
6917         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6918
6919         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6920         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6921         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6922         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6923
6924         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6925
6926         /* QM queues pointers table */
6927         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6928
6929         /* soft reset pulse */
6930         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6931         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6932
6933         if (CNIC_SUPPORT(bp))
6934                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6935
6936         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6937
6938         if (!CHIP_REV_IS_SLOW(bp))
6939                 /* enable hw interrupt from doorbell Q */
6940                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6941
6942         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6943
6944         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6945         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6946
6947         if (!CHIP_IS_E1(bp))
6948                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6949
6950         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6951                 if (IS_MF_AFEX(bp)) {
6952                         /* configure that VNTag and VLAN headers must be
6953                          * received in afex mode
6954                          */
6955                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6956                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6957                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6958                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6959                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6960                 } else {
6961                         /* Bit-map indicating which L2 hdrs may appear
6962                          * after the basic Ethernet header
6963                          */
6964                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6965                                bp->path_has_ovlan ? 7 : 6);
6966                 }
6967         }
6968
6969         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6970         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6971         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6972         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6973
6974         if (!CHIP_IS_E1x(bp)) {
6975                 /* reset VFC memories */
6976                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6977                            VFC_MEMORIES_RST_REG_CAM_RST |
6978                            VFC_MEMORIES_RST_REG_RAM_RST);
6979                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6980                            VFC_MEMORIES_RST_REG_CAM_RST |
6981                            VFC_MEMORIES_RST_REG_RAM_RST);
6982
6983                 msleep(20);
6984         }
6985
6986         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6987         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6988         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6989         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6990
6991         /* sync semi rtc */
6992         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6993                0x80000000);
6994         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6995                0x80000000);
6996
6997         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6998         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6999         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7000
7001         if (!CHIP_IS_E1x(bp)) {
7002                 if (IS_MF_AFEX(bp)) {
7003                         /* configure that VNTag and VLAN headers must be
7004                          * sent in afex mode
7005                          */
7006                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7007                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7008                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7009                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7010                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7011                 } else {
7012                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7013                                bp->path_has_ovlan ? 7 : 6);
7014                 }
7015         }
7016
7017         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7018
7019         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7020
7021         if (CNIC_SUPPORT(bp)) {
7022                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7023                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7024                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7025                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7026                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7027                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7028                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7029                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7030                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7031                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7032         }
7033         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7034
7035         if (sizeof(union cdu_context) != 1024)
7036                 /* we currently assume that a context is 1024 bytes */
7037                 dev_alert(&bp->pdev->dev,
7038                           "please adjust the size of cdu_context(%ld)\n",
7039                           (long)sizeof(union cdu_context));
7040
7041         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7042         val = (4 << 24) + (0 << 12) + 1024;
7043         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7044
7045         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7046         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7047         /* enable context validation interrupt from CFC */
7048         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7049
7050         /* set the thresholds to prevent CFC/CDU race */
7051         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7052
7053         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7054
7055         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7056                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7057
7058         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7059         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7060
7061         /* Reset PCIE errors for debug */
7062         REG_WR(bp, 0x2814, 0xffffffff);
7063         REG_WR(bp, 0x3820, 0xffffffff);
7064
7065         if (!CHIP_IS_E1x(bp)) {
7066                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7067                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7068                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7069                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7070                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7071                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7072                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7073                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7074                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7075                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7076                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7077         }
7078
7079         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7080         if (!CHIP_IS_E1(bp)) {
7081                 /* in E3 this done in per-port section */
7082                 if (!CHIP_IS_E3(bp))
7083                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7084         }
7085         if (CHIP_IS_E1H(bp))
7086                 /* not applicable for E2 (and above ...) */
7087                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7088
7089         if (CHIP_REV_IS_SLOW(bp))
7090                 msleep(200);
7091
7092         /* finish CFC init */
7093         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7094         if (val != 1) {
7095                 BNX2X_ERR("CFC LL_INIT failed\n");
7096                 return -EBUSY;
7097         }
7098         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7099         if (val != 1) {
7100                 BNX2X_ERR("CFC AC_INIT failed\n");
7101                 return -EBUSY;
7102         }
7103         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7104         if (val != 1) {
7105                 BNX2X_ERR("CFC CAM_INIT failed\n");
7106                 return -EBUSY;
7107         }
7108         REG_WR(bp, CFC_REG_DEBUG0, 0);
7109
7110         if (CHIP_IS_E1(bp)) {
7111                 /* read NIG statistic
7112                    to see if this is our first up since powerup */
7113                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7114                 val = *bnx2x_sp(bp, wb_data[0]);
7115
7116                 /* do internal memory self test */
7117                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7118                         BNX2X_ERR("internal mem self test failed\n");
7119                         return -EBUSY;
7120                 }
7121         }
7122
7123         bnx2x_setup_fan_failure_detection(bp);
7124
7125         /* clear PXP2 attentions */
7126         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7127
7128         bnx2x_enable_blocks_attention(bp);
7129         bnx2x_enable_blocks_parity(bp);
7130
7131         if (!BP_NOMCP(bp)) {
7132                 if (CHIP_IS_E1x(bp))
7133                         bnx2x__common_init_phy(bp);
7134         } else
7135                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7136
7137         return 0;
7138 }
7139
7140 /**
7141  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7142  *
7143  * @bp:         driver handle
7144  */
7145 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7146 {
7147         int rc = bnx2x_init_hw_common(bp);
7148
7149         if (rc)
7150                 return rc;
7151
7152         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7153         if (!BP_NOMCP(bp))
7154                 bnx2x__common_init_phy(bp);
7155
7156         return 0;
7157 }
7158
7159 static int bnx2x_init_hw_port(struct bnx2x *bp)
7160 {
7161         int port = BP_PORT(bp);
7162         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7163         u32 low, high;
7164         u32 val, reg;
7165
7166         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7167
7168         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7169
7170         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7171         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7172         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7173
7174         /* Timers bug workaround: disables the pf_master bit in pglue at
7175          * common phase, we need to enable it here before any dmae access are
7176          * attempted. Therefore we manually added the enable-master to the
7177          * port phase (it also happens in the function phase)
7178          */
7179         if (!CHIP_IS_E1x(bp))
7180                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7181
7182         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7183         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7184         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7185         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7186
7187         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7188         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7189         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7190         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7191
7192         /* QM cid (connection) count */
7193         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7194
7195         if (CNIC_SUPPORT(bp)) {
7196                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7197                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7198                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7199         }
7200
7201         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7202
7203         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7204
7205         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7206
7207                 if (IS_MF(bp))
7208                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7209                 else if (bp->dev->mtu > 4096) {
7210                         if (bp->flags & ONE_PORT_FLAG)
7211                                 low = 160;
7212                         else {
7213                                 val = bp->dev->mtu;
7214                                 /* (24*1024 + val*4)/256 */
7215                                 low = 96 + (val/64) +
7216                                                 ((val % 64) ? 1 : 0);
7217                         }
7218                 } else
7219                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7220                 high = low + 56;        /* 14*1024/256 */
7221                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7222                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7223         }
7224
7225         if (CHIP_MODE_IS_4_PORT(bp))
7226                 REG_WR(bp, (BP_PORT(bp) ?
7227                             BRB1_REG_MAC_GUARANTIED_1 :
7228                             BRB1_REG_MAC_GUARANTIED_0), 40);
7229
7230         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7231         if (CHIP_IS_E3B0(bp)) {
7232                 if (IS_MF_AFEX(bp)) {
7233                         /* configure headers for AFEX mode */
7234                         REG_WR(bp, BP_PORT(bp) ?
7235                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7236                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7237                         REG_WR(bp, BP_PORT(bp) ?
7238                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7239                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7240                         REG_WR(bp, BP_PORT(bp) ?
7241                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7242                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7243                 } else {
7244                         /* Ovlan exists only if we are in multi-function +
7245                          * switch-dependent mode, in switch-independent there
7246                          * is no ovlan headers
7247                          */
7248                         REG_WR(bp, BP_PORT(bp) ?
7249                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7250                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7251                                (bp->path_has_ovlan ? 7 : 6));
7252                 }
7253         }
7254
7255         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7256         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7257         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7258         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7259
7260         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7261         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7262         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7263         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7264
7265         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7266         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7267
7268         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7269
7270         if (CHIP_IS_E1x(bp)) {
7271                 /* configure PBF to work without PAUSE mtu 9000 */
7272                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7273
7274                 /* update threshold */
7275                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7276                 /* update init credit */
7277                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7278
7279                 /* probe changes */
7280                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7281                 udelay(50);
7282                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7283         }
7284
7285         if (CNIC_SUPPORT(bp))
7286                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7287
7288         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7289         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7290
7291         if (CHIP_IS_E1(bp)) {
7292                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7293                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7294         }
7295         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7296
7297         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7298
7299         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7300         /* init aeu_mask_attn_func_0/1:
7301          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7302          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7303          *             bits 4-7 are used for "per vn group attention" */
7304         val = IS_MF(bp) ? 0xF7 : 0x7;
7305         /* Enable DCBX attention for all but E1 */
7306         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7307         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7308
7309         /* SCPAD_PARITY should NOT trigger close the gates */
7310         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7311         REG_WR(bp, reg,
7312                REG_RD(bp, reg) &
7313                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7314
7315         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7316         REG_WR(bp, reg,
7317                REG_RD(bp, reg) &
7318                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7319
7320         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7321
7322         if (!CHIP_IS_E1x(bp)) {
7323                 /* Bit-map indicating which L2 hdrs may appear after the
7324                  * basic Ethernet header
7325                  */
7326                 if (IS_MF_AFEX(bp))
7327                         REG_WR(bp, BP_PORT(bp) ?
7328                                NIG_REG_P1_HDRS_AFTER_BASIC :
7329                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7330                 else
7331                         REG_WR(bp, BP_PORT(bp) ?
7332                                NIG_REG_P1_HDRS_AFTER_BASIC :
7333                                NIG_REG_P0_HDRS_AFTER_BASIC,
7334                                IS_MF_SD(bp) ? 7 : 6);
7335
7336                 if (CHIP_IS_E3(bp))
7337                         REG_WR(bp, BP_PORT(bp) ?
7338                                    NIG_REG_LLH1_MF_MODE :
7339                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7340         }
7341         if (!CHIP_IS_E3(bp))
7342                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7343
7344         if (!CHIP_IS_E1(bp)) {
7345                 /* 0x2 disable mf_ov, 0x1 enable */
7346                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7347                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7348
7349                 if (!CHIP_IS_E1x(bp)) {
7350                         val = 0;
7351                         switch (bp->mf_mode) {
7352                         case MULTI_FUNCTION_SD:
7353                                 val = 1;
7354                                 break;
7355                         case MULTI_FUNCTION_SI:
7356                         case MULTI_FUNCTION_AFEX:
7357                                 val = 2;
7358                                 break;
7359                         }
7360
7361                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7362                                                   NIG_REG_LLH0_CLS_TYPE), val);
7363                 }
7364                 {
7365                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7366                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7367                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7368                 }
7369         }
7370
7371         /* If SPIO5 is set to generate interrupts, enable it for this port */
7372         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7373         if (val & MISC_SPIO_SPIO5) {
7374                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7375                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7376                 val = REG_RD(bp, reg_addr);
7377                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7378                 REG_WR(bp, reg_addr, val);
7379         }
7380
7381         return 0;
7382 }
7383
7384 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7385 {
7386         int reg;
7387         u32 wb_write[2];
7388
7389         if (CHIP_IS_E1(bp))
7390                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7391         else
7392                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7393
7394         wb_write[0] = ONCHIP_ADDR1(addr);
7395         wb_write[1] = ONCHIP_ADDR2(addr);
7396         REG_WR_DMAE(bp, reg, wb_write, 2);
7397 }
7398
7399 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7400 {
7401         u32 data, ctl, cnt = 100;
7402         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7403         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7404         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7405         u32 sb_bit =  1 << (idu_sb_id%32);
7406         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7407         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7408
7409         /* Not supported in BC mode */
7410         if (CHIP_INT_MODE_IS_BC(bp))
7411                 return;
7412
7413         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7414                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7415                 IGU_REGULAR_CLEANUP_SET                         |
7416                 IGU_REGULAR_BCLEANUP;
7417
7418         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7419               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7420               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7421
7422         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7423                          data, igu_addr_data);
7424         REG_WR(bp, igu_addr_data, data);
7425         mmiowb();
7426         barrier();
7427         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7428                           ctl, igu_addr_ctl);
7429         REG_WR(bp, igu_addr_ctl, ctl);
7430         mmiowb();
7431         barrier();
7432
7433         /* wait for clean up to finish */
7434         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7435                 msleep(20);
7436
7437         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7438                 DP(NETIF_MSG_HW,
7439                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7440                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7441         }
7442 }
7443
7444 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7445 {
7446         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7447 }
7448
7449 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7450 {
7451         u32 i, base = FUNC_ILT_BASE(func);
7452         for (i = base; i < base + ILT_PER_FUNC; i++)
7453                 bnx2x_ilt_wr(bp, i, 0);
7454 }
7455
7456 static void bnx2x_init_searcher(struct bnx2x *bp)
7457 {
7458         int port = BP_PORT(bp);
7459         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7460         /* T1 hash bits value determines the T1 number of entries */
7461         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7462 }
7463
7464 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7465 {
7466         int rc;
7467         struct bnx2x_func_state_params func_params = {NULL};
7468         struct bnx2x_func_switch_update_params *switch_update_params =
7469                 &func_params.params.switch_update;
7470
7471         /* Prepare parameters for function state transitions */
7472         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7473         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7474
7475         func_params.f_obj = &bp->func_obj;
7476         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7477
7478         /* Function parameters */
7479         switch_update_params->suspend = suspend;
7480
7481         rc = bnx2x_func_state_change(bp, &func_params);
7482
7483         return rc;
7484 }
7485
7486 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7487 {
7488         int rc, i, port = BP_PORT(bp);
7489         int vlan_en = 0, mac_en[NUM_MACS];
7490
7491         /* Close input from network */
7492         if (bp->mf_mode == SINGLE_FUNCTION) {
7493                 bnx2x_set_rx_filter(&bp->link_params, 0);
7494         } else {
7495                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7496                                    NIG_REG_LLH0_FUNC_EN);
7497                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7498                           NIG_REG_LLH0_FUNC_EN, 0);
7499                 for (i = 0; i < NUM_MACS; i++) {
7500                         mac_en[i] = REG_RD(bp, port ?
7501                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7502                                               4 * i) :
7503                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7504                                               4 * i));
7505                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7506                                               4 * i) :
7507                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7508                 }
7509         }
7510
7511         /* Close BMC to host */
7512         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7513                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7514
7515         /* Suspend Tx switching to the PF. Completion of this ramrod
7516          * further guarantees that all the packets of that PF / child
7517          * VFs in BRB were processed by the Parser, so it is safe to
7518          * change the NIC_MODE register.
7519          */
7520         rc = bnx2x_func_switch_update(bp, 1);
7521         if (rc) {
7522                 BNX2X_ERR("Can't suspend tx-switching!\n");
7523                 return rc;
7524         }
7525
7526         /* Change NIC_MODE register */
7527         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7528
7529         /* Open input from network */
7530         if (bp->mf_mode == SINGLE_FUNCTION) {
7531                 bnx2x_set_rx_filter(&bp->link_params, 1);
7532         } else {
7533                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7534                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7535                 for (i = 0; i < NUM_MACS; i++) {
7536                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7537                                               4 * i) :
7538                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7539                                   mac_en[i]);
7540                 }
7541         }
7542
7543         /* Enable BMC to host */
7544         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7545                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7546
7547         /* Resume Tx switching to the PF */
7548         rc = bnx2x_func_switch_update(bp, 0);
7549         if (rc) {
7550                 BNX2X_ERR("Can't resume tx-switching!\n");
7551                 return rc;
7552         }
7553
7554         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7555         return 0;
7556 }
7557
7558 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7559 {
7560         int rc;
7561
7562         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7563
7564         if (CONFIGURE_NIC_MODE(bp)) {
7565                 /* Configure searcher as part of function hw init */
7566                 bnx2x_init_searcher(bp);
7567
7568                 /* Reset NIC mode */
7569                 rc = bnx2x_reset_nic_mode(bp);
7570                 if (rc)
7571                         BNX2X_ERR("Can't change NIC mode!\n");
7572                 return rc;
7573         }
7574
7575         return 0;
7576 }
7577
7578 static int bnx2x_init_hw_func(struct bnx2x *bp)
7579 {
7580         int port = BP_PORT(bp);
7581         int func = BP_FUNC(bp);
7582         int init_phase = PHASE_PF0 + func;
7583         struct bnx2x_ilt *ilt = BP_ILT(bp);
7584         u16 cdu_ilt_start;
7585         u32 addr, val;
7586         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7587         int i, main_mem_width, rc;
7588
7589         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7590
7591         /* FLR cleanup - hmmm */
7592         if (!CHIP_IS_E1x(bp)) {
7593                 rc = bnx2x_pf_flr_clnup(bp);
7594                 if (rc) {
7595                         bnx2x_fw_dump(bp);
7596                         return rc;
7597                 }
7598         }
7599
7600         /* set MSI reconfigure capability */
7601         if (bp->common.int_block == INT_BLOCK_HC) {
7602                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7603                 val = REG_RD(bp, addr);
7604                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7605                 REG_WR(bp, addr, val);
7606         }
7607
7608         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7609         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7610
7611         ilt = BP_ILT(bp);
7612         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7613
7614         if (IS_SRIOV(bp))
7615                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7616         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7617
7618         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7619          * those of the VFs, so start line should be reset
7620          */
7621         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7622         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7623                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7624                 ilt->lines[cdu_ilt_start + i].page_mapping =
7625                         bp->context[i].cxt_mapping;
7626                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7627         }
7628
7629         bnx2x_ilt_init_op(bp, INITOP_SET);
7630
7631         if (!CONFIGURE_NIC_MODE(bp)) {
7632                 bnx2x_init_searcher(bp);
7633                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7634                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7635         } else {
7636                 /* Set NIC mode */
7637                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7638                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7639         }
7640
7641         if (!CHIP_IS_E1x(bp)) {
7642                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7643
7644                 /* Turn on a single ISR mode in IGU if driver is going to use
7645                  * INT#x or MSI
7646                  */
7647                 if (!(bp->flags & USING_MSIX_FLAG))
7648                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7649                 /*
7650                  * Timers workaround bug: function init part.
7651                  * Need to wait 20msec after initializing ILT,
7652                  * needed to make sure there are no requests in
7653                  * one of the PXP internal queues with "old" ILT addresses
7654                  */
7655                 msleep(20);
7656                 /*
7657                  * Master enable - Due to WB DMAE writes performed before this
7658                  * register is re-initialized as part of the regular function
7659                  * init
7660                  */
7661                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7662                 /* Enable the function in IGU */
7663                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7664         }
7665
7666         bp->dmae_ready = 1;
7667
7668         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7669
7670         if (!CHIP_IS_E1x(bp))
7671                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7672
7673         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7674         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7675         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7676         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7677         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7678         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7679         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7680         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7681         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7682         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7683         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7684         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7685         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7686
7687         if (!CHIP_IS_E1x(bp))
7688                 REG_WR(bp, QM_REG_PF_EN, 1);
7689
7690         if (!CHIP_IS_E1x(bp)) {
7691                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7692                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7693                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7694                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7695         }
7696         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7697
7698         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7699         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7700         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7701
7702         bnx2x_iov_init_dq(bp);
7703
7704         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7705         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7706         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7707         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7708         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7709         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7710         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7711         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7712         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7713         if (!CHIP_IS_E1x(bp))
7714                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7715
7716         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7717
7718         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7719
7720         if (!CHIP_IS_E1x(bp))
7721                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7722
7723         if (IS_MF(bp)) {
7724                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7725                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7726         }
7727
7728         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7729
7730         /* HC init per function */
7731         if (bp->common.int_block == INT_BLOCK_HC) {
7732                 if (CHIP_IS_E1H(bp)) {
7733                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7734
7735                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7736                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7737                 }
7738                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7739
7740         } else {
7741                 int num_segs, sb_idx, prod_offset;
7742
7743                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7744
7745                 if (!CHIP_IS_E1x(bp)) {
7746                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7747                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7748                 }
7749
7750                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7751
7752                 if (!CHIP_IS_E1x(bp)) {
7753                         int dsb_idx = 0;
7754                         /**
7755                          * Producer memory:
7756                          * E2 mode: address 0-135 match to the mapping memory;
7757                          * 136 - PF0 default prod; 137 - PF1 default prod;
7758                          * 138 - PF2 default prod; 139 - PF3 default prod;
7759                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7760                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7761                          * 144-147 reserved.
7762                          *
7763                          * E1.5 mode - In backward compatible mode;
7764                          * for non default SB; each even line in the memory
7765                          * holds the U producer and each odd line hold
7766                          * the C producer. The first 128 producers are for
7767                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7768                          * producers are for the DSB for each PF.
7769                          * Each PF has five segments: (the order inside each
7770                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7771                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7772                          * 144-147 attn prods;
7773                          */
7774                         /* non-default-status-blocks */
7775                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7776                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7777                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7778                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7779                                         num_segs;
7780
7781                                 for (i = 0; i < num_segs; i++) {
7782                                         addr = IGU_REG_PROD_CONS_MEMORY +
7783                                                         (prod_offset + i) * 4;
7784                                         REG_WR(bp, addr, 0);
7785                                 }
7786                                 /* send consumer update with value 0 */
7787                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7788                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7789                                 bnx2x_igu_clear_sb(bp,
7790                                                    bp->igu_base_sb + sb_idx);
7791                         }
7792
7793                         /* default-status-blocks */
7794                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7795                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7796
7797                         if (CHIP_MODE_IS_4_PORT(bp))
7798                                 dsb_idx = BP_FUNC(bp);
7799                         else
7800                                 dsb_idx = BP_VN(bp);
7801
7802                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7803                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7804                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7805
7806                         /*
7807                          * igu prods come in chunks of E1HVN_MAX (4) -
7808                          * does not matters what is the current chip mode
7809                          */
7810                         for (i = 0; i < (num_segs * E1HVN_MAX);
7811                              i += E1HVN_MAX) {
7812                                 addr = IGU_REG_PROD_CONS_MEMORY +
7813                                                         (prod_offset + i)*4;
7814                                 REG_WR(bp, addr, 0);
7815                         }
7816                         /* send consumer update with 0 */
7817                         if (CHIP_INT_MODE_IS_BC(bp)) {
7818                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7819                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7820                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7821                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7822                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7823                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7824                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7825                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7826                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7827                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7828                         } else {
7829                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7830                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7831                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7832                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7833                         }
7834                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7835
7836                         /* !!! These should become driver const once
7837                            rf-tool supports split-68 const */
7838                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7839                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7840                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7841                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7842                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7843                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7844                 }
7845         }
7846
7847         /* Reset PCIE errors for debug */
7848         REG_WR(bp, 0x2114, 0xffffffff);
7849         REG_WR(bp, 0x2120, 0xffffffff);
7850
7851         if (CHIP_IS_E1x(bp)) {
7852                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7853                 main_mem_base = HC_REG_MAIN_MEMORY +
7854                                 BP_PORT(bp) * (main_mem_size * 4);
7855                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7856                 main_mem_width = 8;
7857
7858                 val = REG_RD(bp, main_mem_prty_clr);
7859                 if (val)
7860                         DP(NETIF_MSG_HW,
7861                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7862                            val);
7863
7864                 /* Clear "false" parity errors in MSI-X table */
7865                 for (i = main_mem_base;
7866                      i < main_mem_base + main_mem_size * 4;
7867                      i += main_mem_width) {
7868                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7869                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7870                                          i, main_mem_width / 4);
7871                 }
7872                 /* Clear HC parity attention */
7873                 REG_RD(bp, main_mem_prty_clr);
7874         }
7875
7876 #ifdef BNX2X_STOP_ON_ERROR
7877         /* Enable STORMs SP logging */
7878         REG_WR8(bp, BAR_USTRORM_INTMEM +
7879                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7880         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7881                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7882         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7883                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7884         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7885                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7886 #endif
7887
7888         bnx2x_phy_probe(&bp->link_params);
7889
7890         return 0;
7891 }
7892
7893 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7894 {
7895         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7896
7897         if (!CHIP_IS_E1x(bp))
7898                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7899                                sizeof(struct host_hc_status_block_e2));
7900         else
7901                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7902                                sizeof(struct host_hc_status_block_e1x));
7903
7904         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7905 }
7906
7907 void bnx2x_free_mem(struct bnx2x *bp)
7908 {
7909         int i;
7910
7911         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7912                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7913
7914         if (IS_VF(bp))
7915                 return;
7916
7917         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7918                        sizeof(struct host_sp_status_block));
7919
7920         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7921                        sizeof(struct bnx2x_slowpath));
7922
7923         for (i = 0; i < L2_ILT_LINES(bp); i++)
7924                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7925                                bp->context[i].size);
7926         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7927
7928         BNX2X_FREE(bp->ilt->lines);
7929
7930         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7931
7932         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7933                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7934
7935         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7936
7937         bnx2x_iov_free_mem(bp);
7938 }
7939
7940 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7941 {
7942         if (!CHIP_IS_E1x(bp))
7943                 /* size = the status block + ramrod buffers */
7944                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7945                                 sizeof(struct host_hc_status_block_e2));
7946         else
7947                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7948                                 &bp->cnic_sb_mapping,
7949                                 sizeof(struct
7950                                        host_hc_status_block_e1x));
7951
7952         if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
7953                 /* allocate searcher T2 table, as it wasn't allocated before */
7954                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7955
7956         /* write address to which L5 should insert its values */
7957         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7958                 &bp->slowpath->drv_info_to_mcp;
7959
7960         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7961                 goto alloc_mem_err;
7962
7963         return 0;
7964
7965 alloc_mem_err:
7966         bnx2x_free_mem_cnic(bp);
7967         BNX2X_ERR("Can't allocate memory\n");
7968         return -ENOMEM;
7969 }
7970
7971 int bnx2x_alloc_mem(struct bnx2x *bp)
7972 {
7973         int i, allocated, context_size;
7974
7975         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
7976                 /* allocate searcher T2 table */
7977                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7978
7979         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7980                         sizeof(struct host_sp_status_block));
7981
7982         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7983                         sizeof(struct bnx2x_slowpath));
7984
7985         /* Allocate memory for CDU context:
7986          * This memory is allocated separately and not in the generic ILT
7987          * functions because CDU differs in few aspects:
7988          * 1. There are multiple entities allocating memory for context -
7989          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7990          * its own ILT lines.
7991          * 2. Since CDU page-size is not a single 4KB page (which is the case
7992          * for the other ILT clients), to be efficient we want to support
7993          * allocation of sub-page-size in the last entry.
7994          * 3. Context pointers are used by the driver to pass to FW / update
7995          * the context (for the other ILT clients the pointers are used just to
7996          * free the memory during unload).
7997          */
7998         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7999
8000         for (i = 0, allocated = 0; allocated < context_size; i++) {
8001                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8002                                           (context_size - allocated));
8003                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
8004                                 &bp->context[i].cxt_mapping,
8005                                 bp->context[i].size);
8006                 allocated += bp->context[i].size;
8007         }
8008         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
8009
8010         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8011                 goto alloc_mem_err;
8012
8013         if (bnx2x_iov_alloc_mem(bp))
8014                 goto alloc_mem_err;
8015
8016         /* Slow path ring */
8017         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
8018
8019         /* EQ */
8020         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
8021                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
8022
8023         return 0;
8024
8025 alloc_mem_err:
8026         bnx2x_free_mem(bp);
8027         BNX2X_ERR("Can't allocate memory\n");
8028         return -ENOMEM;
8029 }
8030
8031 /*
8032  * Init service functions
8033  */
8034
8035 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8036                       struct bnx2x_vlan_mac_obj *obj, bool set,
8037                       int mac_type, unsigned long *ramrod_flags)
8038 {
8039         int rc;
8040         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8041
8042         memset(&ramrod_param, 0, sizeof(ramrod_param));
8043
8044         /* Fill general parameters */
8045         ramrod_param.vlan_mac_obj = obj;
8046         ramrod_param.ramrod_flags = *ramrod_flags;
8047
8048         /* Fill a user request section if needed */
8049         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8050                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8051
8052                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8053
8054                 /* Set the command: ADD or DEL */
8055                 if (set)
8056                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8057                 else
8058                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8059         }
8060
8061         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8062
8063         if (rc == -EEXIST) {
8064                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8065                 /* do not treat adding same MAC as error */
8066                 rc = 0;
8067         } else if (rc < 0)
8068                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8069
8070         return rc;
8071 }
8072
8073 int bnx2x_del_all_macs(struct bnx2x *bp,
8074                        struct bnx2x_vlan_mac_obj *mac_obj,
8075                        int mac_type, bool wait_for_comp)
8076 {
8077         int rc;
8078         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8079
8080         /* Wait for completion of requested */
8081         if (wait_for_comp)
8082                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8083
8084         /* Set the mac type of addresses we want to clear */
8085         __set_bit(mac_type, &vlan_mac_flags);
8086
8087         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8088         if (rc < 0)
8089                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8090
8091         return rc;
8092 }
8093
8094 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8095 {
8096         if (is_zero_ether_addr(bp->dev->dev_addr) &&
8097             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8098                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8099                    "Ignoring Zero MAC for STORAGE SD mode\n");
8100                 return 0;
8101         }
8102
8103         if (IS_PF(bp)) {
8104                 unsigned long ramrod_flags = 0;
8105
8106                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8107                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8108                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8109                                          &bp->sp_objs->mac_obj, set,
8110                                          BNX2X_ETH_MAC, &ramrod_flags);
8111         } else { /* vf */
8112                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8113                                              bp->fp->index, true);
8114         }
8115 }
8116
8117 int bnx2x_setup_leading(struct bnx2x *bp)
8118 {
8119         if (IS_PF(bp))
8120                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8121         else /* VF */
8122                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8123 }
8124
8125 /**
8126  * bnx2x_set_int_mode - configure interrupt mode
8127  *
8128  * @bp:         driver handle
8129  *
8130  * In case of MSI-X it will also try to enable MSI-X.
8131  */
8132 int bnx2x_set_int_mode(struct bnx2x *bp)
8133 {
8134         int rc = 0;
8135
8136         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8137                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8138                 return -EINVAL;
8139         }
8140
8141         switch (int_mode) {
8142         case BNX2X_INT_MODE_MSIX:
8143                 /* attempt to enable msix */
8144                 rc = bnx2x_enable_msix(bp);
8145
8146                 /* msix attained */
8147                 if (!rc)
8148                         return 0;
8149
8150                 /* vfs use only msix */
8151                 if (rc && IS_VF(bp))
8152                         return rc;
8153
8154                 /* failed to enable multiple MSI-X */
8155                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8156                                bp->num_queues,
8157                                1 + bp->num_cnic_queues);
8158
8159                 /* falling through... */
8160         case BNX2X_INT_MODE_MSI:
8161                 bnx2x_enable_msi(bp);
8162
8163                 /* falling through... */
8164         case BNX2X_INT_MODE_INTX:
8165                 bp->num_ethernet_queues = 1;
8166                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8167                 BNX2X_DEV_INFO("set number of queues to 1\n");
8168                 break;
8169         default:
8170                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8171                 return -EINVAL;
8172         }
8173         return 0;
8174 }
8175
8176 /* must be called prior to any HW initializations */
8177 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8178 {
8179         if (IS_SRIOV(bp))
8180                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8181         return L2_ILT_LINES(bp);
8182 }
8183
8184 void bnx2x_ilt_set_info(struct bnx2x *bp)
8185 {
8186         struct ilt_client_info *ilt_client;
8187         struct bnx2x_ilt *ilt = BP_ILT(bp);
8188         u16 line = 0;
8189
8190         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8191         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8192
8193         /* CDU */
8194         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8195         ilt_client->client_num = ILT_CLIENT_CDU;
8196         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8197         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8198         ilt_client->start = line;
8199         line += bnx2x_cid_ilt_lines(bp);
8200
8201         if (CNIC_SUPPORT(bp))
8202                 line += CNIC_ILT_LINES;
8203         ilt_client->end = line - 1;
8204
8205         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8206            ilt_client->start,
8207            ilt_client->end,
8208            ilt_client->page_size,
8209            ilt_client->flags,
8210            ilog2(ilt_client->page_size >> 12));
8211
8212         /* QM */
8213         if (QM_INIT(bp->qm_cid_count)) {
8214                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8215                 ilt_client->client_num = ILT_CLIENT_QM;
8216                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8217                 ilt_client->flags = 0;
8218                 ilt_client->start = line;
8219
8220                 /* 4 bytes for each cid */
8221                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8222                                                          QM_ILT_PAGE_SZ);
8223
8224                 ilt_client->end = line - 1;
8225
8226                 DP(NETIF_MSG_IFUP,
8227                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8228                    ilt_client->start,
8229                    ilt_client->end,
8230                    ilt_client->page_size,
8231                    ilt_client->flags,
8232                    ilog2(ilt_client->page_size >> 12));
8233         }
8234
8235         if (CNIC_SUPPORT(bp)) {
8236                 /* SRC */
8237                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8238                 ilt_client->client_num = ILT_CLIENT_SRC;
8239                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8240                 ilt_client->flags = 0;
8241                 ilt_client->start = line;
8242                 line += SRC_ILT_LINES;
8243                 ilt_client->end = line - 1;
8244
8245                 DP(NETIF_MSG_IFUP,
8246                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8247                    ilt_client->start,
8248                    ilt_client->end,
8249                    ilt_client->page_size,
8250                    ilt_client->flags,
8251                    ilog2(ilt_client->page_size >> 12));
8252
8253                 /* TM */
8254                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8255                 ilt_client->client_num = ILT_CLIENT_TM;
8256                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8257                 ilt_client->flags = 0;
8258                 ilt_client->start = line;
8259                 line += TM_ILT_LINES;
8260                 ilt_client->end = line - 1;
8261
8262                 DP(NETIF_MSG_IFUP,
8263                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8264                    ilt_client->start,
8265                    ilt_client->end,
8266                    ilt_client->page_size,
8267                    ilt_client->flags,
8268                    ilog2(ilt_client->page_size >> 12));
8269         }
8270
8271         BUG_ON(line > ILT_MAX_LINES);
8272 }
8273
8274 /**
8275  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8276  *
8277  * @bp:                 driver handle
8278  * @fp:                 pointer to fastpath
8279  * @init_params:        pointer to parameters structure
8280  *
8281  * parameters configured:
8282  *      - HC configuration
8283  *      - Queue's CDU context
8284  */
8285 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8286         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8287 {
8288         u8 cos;
8289         int cxt_index, cxt_offset;
8290
8291         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8292         if (!IS_FCOE_FP(fp)) {
8293                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8294                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8295
8296                 /* If HC is supported, enable host coalescing in the transition
8297                  * to INIT state.
8298                  */
8299                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8300                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8301
8302                 /* HC rate */
8303                 init_params->rx.hc_rate = bp->rx_ticks ?
8304                         (1000000 / bp->rx_ticks) : 0;
8305                 init_params->tx.hc_rate = bp->tx_ticks ?
8306                         (1000000 / bp->tx_ticks) : 0;
8307
8308                 /* FW SB ID */
8309                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8310                         fp->fw_sb_id;
8311
8312                 /*
8313                  * CQ index among the SB indices: FCoE clients uses the default
8314                  * SB, therefore it's different.
8315                  */
8316                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8317                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8318         }
8319
8320         /* set maximum number of COSs supported by this queue */
8321         init_params->max_cos = fp->max_cos;
8322
8323         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8324             fp->index, init_params->max_cos);
8325
8326         /* set the context pointers queue object */
8327         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8328                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8329                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8330                                 ILT_PAGE_CIDS);
8331                 init_params->cxts[cos] =
8332                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8333         }
8334 }
8335
8336 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8337                         struct bnx2x_queue_state_params *q_params,
8338                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8339                         int tx_index, bool leading)
8340 {
8341         memset(tx_only_params, 0, sizeof(*tx_only_params));
8342
8343         /* Set the command */
8344         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8345
8346         /* Set tx-only QUEUE flags: don't zero statistics */
8347         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8348
8349         /* choose the index of the cid to send the slow path on */
8350         tx_only_params->cid_index = tx_index;
8351
8352         /* Set general TX_ONLY_SETUP parameters */
8353         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8354
8355         /* Set Tx TX_ONLY_SETUP parameters */
8356         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8357
8358         DP(NETIF_MSG_IFUP,
8359            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8360            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8361            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8362            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8363
8364         /* send the ramrod */
8365         return bnx2x_queue_state_change(bp, q_params);
8366 }
8367
8368 /**
8369  * bnx2x_setup_queue - setup queue
8370  *
8371  * @bp:         driver handle
8372  * @fp:         pointer to fastpath
8373  * @leading:    is leading
8374  *
8375  * This function performs 2 steps in a Queue state machine
8376  *      actually: 1) RESET->INIT 2) INIT->SETUP
8377  */
8378
8379 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8380                        bool leading)
8381 {
8382         struct bnx2x_queue_state_params q_params = {NULL};
8383         struct bnx2x_queue_setup_params *setup_params =
8384                                                 &q_params.params.setup;
8385         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8386                                                 &q_params.params.tx_only;
8387         int rc;
8388         u8 tx_index;
8389
8390         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8391
8392         /* reset IGU state skip FCoE L2 queue */
8393         if (!IS_FCOE_FP(fp))
8394                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8395                              IGU_INT_ENABLE, 0);
8396
8397         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8398         /* We want to wait for completion in this context */
8399         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8400
8401         /* Prepare the INIT parameters */
8402         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8403
8404         /* Set the command */
8405         q_params.cmd = BNX2X_Q_CMD_INIT;
8406
8407         /* Change the state to INIT */
8408         rc = bnx2x_queue_state_change(bp, &q_params);
8409         if (rc) {
8410                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8411                 return rc;
8412         }
8413
8414         DP(NETIF_MSG_IFUP, "init complete\n");
8415
8416         /* Now move the Queue to the SETUP state... */
8417         memset(setup_params, 0, sizeof(*setup_params));
8418
8419         /* Set QUEUE flags */
8420         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8421
8422         /* Set general SETUP parameters */
8423         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8424                                 FIRST_TX_COS_INDEX);
8425
8426         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8427                             &setup_params->rxq_params);
8428
8429         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8430                            FIRST_TX_COS_INDEX);
8431
8432         /* Set the command */
8433         q_params.cmd = BNX2X_Q_CMD_SETUP;
8434
8435         if (IS_FCOE_FP(fp))
8436                 bp->fcoe_init = true;
8437
8438         /* Change the state to SETUP */
8439         rc = bnx2x_queue_state_change(bp, &q_params);
8440         if (rc) {
8441                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8442                 return rc;
8443         }
8444
8445         /* loop through the relevant tx-only indices */
8446         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8447               tx_index < fp->max_cos;
8448               tx_index++) {
8449
8450                 /* prepare and send tx-only ramrod*/
8451                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8452                                           tx_only_params, tx_index, leading);
8453                 if (rc) {
8454                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8455                                   fp->index, tx_index);
8456                         return rc;
8457                 }
8458         }
8459
8460         return rc;
8461 }
8462
8463 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8464 {
8465         struct bnx2x_fastpath *fp = &bp->fp[index];
8466         struct bnx2x_fp_txdata *txdata;
8467         struct bnx2x_queue_state_params q_params = {NULL};
8468         int rc, tx_index;
8469
8470         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8471
8472         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8473         /* We want to wait for completion in this context */
8474         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8475
8476         /* close tx-only connections */
8477         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8478              tx_index < fp->max_cos;
8479              tx_index++){
8480
8481                 /* ascertain this is a normal queue*/
8482                 txdata = fp->txdata_ptr[tx_index];
8483
8484                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8485                                                         txdata->txq_index);
8486
8487                 /* send halt terminate on tx-only connection */
8488                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8489                 memset(&q_params.params.terminate, 0,
8490                        sizeof(q_params.params.terminate));
8491                 q_params.params.terminate.cid_index = tx_index;
8492
8493                 rc = bnx2x_queue_state_change(bp, &q_params);
8494                 if (rc)
8495                         return rc;
8496
8497                 /* send halt terminate on tx-only connection */
8498                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8499                 memset(&q_params.params.cfc_del, 0,
8500                        sizeof(q_params.params.cfc_del));
8501                 q_params.params.cfc_del.cid_index = tx_index;
8502                 rc = bnx2x_queue_state_change(bp, &q_params);
8503                 if (rc)
8504                         return rc;
8505         }
8506         /* Stop the primary connection: */
8507         /* ...halt the connection */
8508         q_params.cmd = BNX2X_Q_CMD_HALT;
8509         rc = bnx2x_queue_state_change(bp, &q_params);
8510         if (rc)
8511                 return rc;
8512
8513         /* ...terminate the connection */
8514         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8515         memset(&q_params.params.terminate, 0,
8516                sizeof(q_params.params.terminate));
8517         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8518         rc = bnx2x_queue_state_change(bp, &q_params);
8519         if (rc)
8520                 return rc;
8521         /* ...delete cfc entry */
8522         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8523         memset(&q_params.params.cfc_del, 0,
8524                sizeof(q_params.params.cfc_del));
8525         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8526         return bnx2x_queue_state_change(bp, &q_params);
8527 }
8528
8529 static void bnx2x_reset_func(struct bnx2x *bp)
8530 {
8531         int port = BP_PORT(bp);
8532         int func = BP_FUNC(bp);
8533         int i;
8534
8535         /* Disable the function in the FW */
8536         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8537         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8538         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8539         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8540
8541         /* FP SBs */
8542         for_each_eth_queue(bp, i) {
8543                 struct bnx2x_fastpath *fp = &bp->fp[i];
8544                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8545                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8546                            SB_DISABLED);
8547         }
8548
8549         if (CNIC_LOADED(bp))
8550                 /* CNIC SB */
8551                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8552                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8553                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8554
8555         /* SP SB */
8556         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8557                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8558                 SB_DISABLED);
8559
8560         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8561                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8562                        0);
8563
8564         /* Configure IGU */
8565         if (bp->common.int_block == INT_BLOCK_HC) {
8566                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8567                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8568         } else {
8569                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8570                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8571         }
8572
8573         if (CNIC_LOADED(bp)) {
8574                 /* Disable Timer scan */
8575                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8576                 /*
8577                  * Wait for at least 10ms and up to 2 second for the timers
8578                  * scan to complete
8579                  */
8580                 for (i = 0; i < 200; i++) {
8581                         usleep_range(10000, 20000);
8582                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8583                                 break;
8584                 }
8585         }
8586         /* Clear ILT */
8587         bnx2x_clear_func_ilt(bp, func);
8588
8589         /* Timers workaround bug for E2: if this is vnic-3,
8590          * we need to set the entire ilt range for this timers.
8591          */
8592         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8593                 struct ilt_client_info ilt_cli;
8594                 /* use dummy TM client */
8595                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8596                 ilt_cli.start = 0;
8597                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8598                 ilt_cli.client_num = ILT_CLIENT_TM;
8599
8600                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8601         }
8602
8603         /* this assumes that reset_port() called before reset_func()*/
8604         if (!CHIP_IS_E1x(bp))
8605                 bnx2x_pf_disable(bp);
8606
8607         bp->dmae_ready = 0;
8608 }
8609
8610 static void bnx2x_reset_port(struct bnx2x *bp)
8611 {
8612         int port = BP_PORT(bp);
8613         u32 val;
8614
8615         /* Reset physical Link */
8616         bnx2x__link_reset(bp);
8617
8618         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8619
8620         /* Do not rcv packets to BRB */
8621         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8622         /* Do not direct rcv packets that are not for MCP to the BRB */
8623         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8624                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8625
8626         /* Configure AEU */
8627         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8628
8629         msleep(100);
8630         /* Check for BRB port occupancy */
8631         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8632         if (val)
8633                 DP(NETIF_MSG_IFDOWN,
8634                    "BRB1 is not empty  %d blocks are occupied\n", val);
8635
8636         /* TODO: Close Doorbell port? */
8637 }
8638
8639 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8640 {
8641         struct bnx2x_func_state_params func_params = {NULL};
8642
8643         /* Prepare parameters for function state transitions */
8644         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8645
8646         func_params.f_obj = &bp->func_obj;
8647         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8648
8649         func_params.params.hw_init.load_phase = load_code;
8650
8651         return bnx2x_func_state_change(bp, &func_params);
8652 }
8653
8654 static int bnx2x_func_stop(struct bnx2x *bp)
8655 {
8656         struct bnx2x_func_state_params func_params = {NULL};
8657         int rc;
8658
8659         /* Prepare parameters for function state transitions */
8660         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8661         func_params.f_obj = &bp->func_obj;
8662         func_params.cmd = BNX2X_F_CMD_STOP;
8663
8664         /*
8665          * Try to stop the function the 'good way'. If fails (in case
8666          * of a parity error during bnx2x_chip_cleanup()) and we are
8667          * not in a debug mode, perform a state transaction in order to
8668          * enable further HW_RESET transaction.
8669          */
8670         rc = bnx2x_func_state_change(bp, &func_params);
8671         if (rc) {
8672 #ifdef BNX2X_STOP_ON_ERROR
8673                 return rc;
8674 #else
8675                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8676                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8677                 return bnx2x_func_state_change(bp, &func_params);
8678 #endif
8679         }
8680
8681         return 0;
8682 }
8683
8684 /**
8685  * bnx2x_send_unload_req - request unload mode from the MCP.
8686  *
8687  * @bp:                 driver handle
8688  * @unload_mode:        requested function's unload mode
8689  *
8690  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8691  */
8692 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8693 {
8694         u32 reset_code = 0;
8695         int port = BP_PORT(bp);
8696
8697         /* Select the UNLOAD request mode */
8698         if (unload_mode == UNLOAD_NORMAL)
8699                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8700
8701         else if (bp->flags & NO_WOL_FLAG)
8702                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8703
8704         else if (bp->wol) {
8705                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8706                 u8 *mac_addr = bp->dev->dev_addr;
8707                 struct pci_dev *pdev = bp->pdev;
8708                 u32 val;
8709                 u16 pmc;
8710
8711                 /* The mac address is written to entries 1-4 to
8712                  * preserve entry 0 which is used by the PMF
8713                  */
8714                 u8 entry = (BP_VN(bp) + 1)*8;
8715
8716                 val = (mac_addr[0] << 8) | mac_addr[1];
8717                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8718
8719                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8720                       (mac_addr[4] << 8) | mac_addr[5];
8721                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8722
8723                 /* Enable the PME and clear the status */
8724                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
8725                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8726                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
8727
8728                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8729
8730         } else
8731                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8732
8733         /* Send the request to the MCP */
8734         if (!BP_NOMCP(bp))
8735                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8736         else {
8737                 int path = BP_PATH(bp);
8738
8739                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8740                    path, load_count[path][0], load_count[path][1],
8741                    load_count[path][2]);
8742                 load_count[path][0]--;
8743                 load_count[path][1 + port]--;
8744                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8745                    path, load_count[path][0], load_count[path][1],
8746                    load_count[path][2]);
8747                 if (load_count[path][0] == 0)
8748                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8749                 else if (load_count[path][1 + port] == 0)
8750                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8751                 else
8752                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8753         }
8754
8755         return reset_code;
8756 }
8757
8758 /**
8759  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8760  *
8761  * @bp:         driver handle
8762  * @keep_link:          true iff link should be kept up
8763  */
8764 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8765 {
8766         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8767
8768         /* Report UNLOAD_DONE to MCP */
8769         if (!BP_NOMCP(bp))
8770                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8771 }
8772
8773 static int bnx2x_func_wait_started(struct bnx2x *bp)
8774 {
8775         int tout = 50;
8776         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8777
8778         if (!bp->port.pmf)
8779                 return 0;
8780
8781         /*
8782          * (assumption: No Attention from MCP at this stage)
8783          * PMF probably in the middle of TX disable/enable transaction
8784          * 1. Sync IRS for default SB
8785          * 2. Sync SP queue - this guarantees us that attention handling started
8786          * 3. Wait, that TX disable/enable transaction completes
8787          *
8788          * 1+2 guarantee that if DCBx attention was scheduled it already changed
8789          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8790          * received completion for the transaction the state is TX_STOPPED.
8791          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8792          * transaction.
8793          */
8794
8795         /* make sure default SB ISR is done */
8796         if (msix)
8797                 synchronize_irq(bp->msix_table[0].vector);
8798         else
8799                 synchronize_irq(bp->pdev->irq);
8800
8801         flush_workqueue(bnx2x_wq);
8802
8803         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8804                                 BNX2X_F_STATE_STARTED && tout--)
8805                 msleep(20);
8806
8807         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8808                                                 BNX2X_F_STATE_STARTED) {
8809 #ifdef BNX2X_STOP_ON_ERROR
8810                 BNX2X_ERR("Wrong function state\n");
8811                 return -EBUSY;
8812 #else
8813                 /*
8814                  * Failed to complete the transaction in a "good way"
8815                  * Force both transactions with CLR bit
8816                  */
8817                 struct bnx2x_func_state_params func_params = {NULL};
8818
8819                 DP(NETIF_MSG_IFDOWN,
8820                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8821
8822                 func_params.f_obj = &bp->func_obj;
8823                 __set_bit(RAMROD_DRV_CLR_ONLY,
8824                                         &func_params.ramrod_flags);
8825
8826                 /* STARTED-->TX_ST0PPED */
8827                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8828                 bnx2x_func_state_change(bp, &func_params);
8829
8830                 /* TX_ST0PPED-->STARTED */
8831                 func_params.cmd = BNX2X_F_CMD_TX_START;
8832                 return bnx2x_func_state_change(bp, &func_params);
8833 #endif
8834         }
8835
8836         return 0;
8837 }
8838
8839 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8840 {
8841         int port = BP_PORT(bp);
8842         int i, rc = 0;
8843         u8 cos;
8844         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8845         u32 reset_code;
8846
8847         /* Wait until tx fastpath tasks complete */
8848         for_each_tx_queue(bp, i) {
8849                 struct bnx2x_fastpath *fp = &bp->fp[i];
8850
8851                 for_each_cos_in_tx_queue(fp, cos)
8852                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8853 #ifdef BNX2X_STOP_ON_ERROR
8854                 if (rc)
8855                         return;
8856 #endif
8857         }
8858
8859         /* Give HW time to discard old tx messages */
8860         usleep_range(1000, 2000);
8861
8862         /* Clean all ETH MACs */
8863         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8864                                 false);
8865         if (rc < 0)
8866                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8867
8868         /* Clean up UC list  */
8869         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8870                                 true);
8871         if (rc < 0)
8872                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8873                           rc);
8874
8875         /* Disable LLH */
8876         if (!CHIP_IS_E1(bp))
8877                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8878
8879         /* Set "drop all" (stop Rx).
8880          * We need to take a netif_addr_lock() here in order to prevent
8881          * a race between the completion code and this code.
8882          */
8883         netif_addr_lock_bh(bp->dev);
8884         /* Schedule the rx_mode command */
8885         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8886                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8887         else
8888                 bnx2x_set_storm_rx_mode(bp);
8889
8890         /* Cleanup multicast configuration */
8891         rparam.mcast_obj = &bp->mcast_obj;
8892         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8893         if (rc < 0)
8894                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8895
8896         netif_addr_unlock_bh(bp->dev);
8897
8898         bnx2x_iov_chip_cleanup(bp);
8899
8900         /*
8901          * Send the UNLOAD_REQUEST to the MCP. This will return if
8902          * this function should perform FUNC, PORT or COMMON HW
8903          * reset.
8904          */
8905         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8906
8907         /*
8908          * (assumption: No Attention from MCP at this stage)
8909          * PMF probably in the middle of TX disable/enable transaction
8910          */
8911         rc = bnx2x_func_wait_started(bp);
8912         if (rc) {
8913                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8914 #ifdef BNX2X_STOP_ON_ERROR
8915                 return;
8916 #endif
8917         }
8918
8919         /* Close multi and leading connections
8920          * Completions for ramrods are collected in a synchronous way
8921          */
8922         for_each_eth_queue(bp, i)
8923                 if (bnx2x_stop_queue(bp, i))
8924 #ifdef BNX2X_STOP_ON_ERROR
8925                         return;
8926 #else
8927                         goto unload_error;
8928 #endif
8929
8930         if (CNIC_LOADED(bp)) {
8931                 for_each_cnic_queue(bp, i)
8932                         if (bnx2x_stop_queue(bp, i))
8933 #ifdef BNX2X_STOP_ON_ERROR
8934                                 return;
8935 #else
8936                                 goto unload_error;
8937 #endif
8938         }
8939
8940         /* If SP settings didn't get completed so far - something
8941          * very wrong has happen.
8942          */
8943         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8944                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8945
8946 #ifndef BNX2X_STOP_ON_ERROR
8947 unload_error:
8948 #endif
8949         rc = bnx2x_func_stop(bp);
8950         if (rc) {
8951                 BNX2X_ERR("Function stop failed!\n");
8952 #ifdef BNX2X_STOP_ON_ERROR
8953                 return;
8954 #endif
8955         }
8956
8957         /* Disable HW interrupts, NAPI */
8958         bnx2x_netif_stop(bp, 1);
8959         /* Delete all NAPI objects */
8960         bnx2x_del_all_napi(bp);
8961         if (CNIC_LOADED(bp))
8962                 bnx2x_del_all_napi_cnic(bp);
8963
8964         /* Release IRQs */
8965         bnx2x_free_irq(bp);
8966
8967         /* Reset the chip */
8968         rc = bnx2x_reset_hw(bp, reset_code);
8969         if (rc)
8970                 BNX2X_ERR("HW_RESET failed\n");
8971
8972         /* Report UNLOAD_DONE to MCP */
8973         bnx2x_send_unload_done(bp, keep_link);
8974 }
8975
8976 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8977 {
8978         u32 val;
8979
8980         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8981
8982         if (CHIP_IS_E1(bp)) {
8983                 int port = BP_PORT(bp);
8984                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8985                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8986
8987                 val = REG_RD(bp, addr);
8988                 val &= ~(0x300);
8989                 REG_WR(bp, addr, val);
8990         } else {
8991                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8992                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8993                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8994                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8995         }
8996 }
8997
8998 /* Close gates #2, #3 and #4: */
8999 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9000 {
9001         u32 val;
9002
9003         /* Gates #2 and #4a are closed/opened for "not E1" only */
9004         if (!CHIP_IS_E1(bp)) {
9005                 /* #4 */
9006                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9007                 /* #2 */
9008                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9009         }
9010
9011         /* #3 */
9012         if (CHIP_IS_E1x(bp)) {
9013                 /* Prevent interrupts from HC on both ports */
9014                 val = REG_RD(bp, HC_REG_CONFIG_1);
9015                 REG_WR(bp, HC_REG_CONFIG_1,
9016                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9017                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9018
9019                 val = REG_RD(bp, HC_REG_CONFIG_0);
9020                 REG_WR(bp, HC_REG_CONFIG_0,
9021                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9022                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9023         } else {
9024                 /* Prevent incoming interrupts in IGU */
9025                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9026
9027                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9028                        (!close) ?
9029                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9030                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9031         }
9032
9033         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9034                 close ? "closing" : "opening");
9035         mmiowb();
9036 }
9037
9038 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9039
9040 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9041 {
9042         /* Do some magic... */
9043         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9044         *magic_val = val & SHARED_MF_CLP_MAGIC;
9045         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9046 }
9047
9048 /**
9049  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9050  *
9051  * @bp:         driver handle
9052  * @magic_val:  old value of the `magic' bit.
9053  */
9054 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9055 {
9056         /* Restore the `magic' bit value... */
9057         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9058         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9059                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9060 }
9061
9062 /**
9063  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9064  *
9065  * @bp:         driver handle
9066  * @magic_val:  old value of 'magic' bit.
9067  *
9068  * Takes care of CLP configurations.
9069  */
9070 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9071 {
9072         u32 shmem;
9073         u32 validity_offset;
9074
9075         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9076
9077         /* Set `magic' bit in order to save MF config */
9078         if (!CHIP_IS_E1(bp))
9079                 bnx2x_clp_reset_prep(bp, magic_val);
9080
9081         /* Get shmem offset */
9082         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9083         validity_offset =
9084                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9085
9086         /* Clear validity map flags */
9087         if (shmem > 0)
9088                 REG_WR(bp, shmem + validity_offset, 0);
9089 }
9090
9091 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9092 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9093
9094 /**
9095  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9096  *
9097  * @bp: driver handle
9098  */
9099 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9100 {
9101         /* special handling for emulation and FPGA,
9102            wait 10 times longer */
9103         if (CHIP_REV_IS_SLOW(bp))
9104                 msleep(MCP_ONE_TIMEOUT*10);
9105         else
9106                 msleep(MCP_ONE_TIMEOUT);
9107 }
9108
9109 /*
9110  * initializes bp->common.shmem_base and waits for validity signature to appear
9111  */
9112 static int bnx2x_init_shmem(struct bnx2x *bp)
9113 {
9114         int cnt = 0;
9115         u32 val = 0;
9116
9117         do {
9118                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9119                 if (bp->common.shmem_base) {
9120                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9121                         if (val & SHR_MEM_VALIDITY_MB)
9122                                 return 0;
9123                 }
9124
9125                 bnx2x_mcp_wait_one(bp);
9126
9127         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9128
9129         BNX2X_ERR("BAD MCP validity signature\n");
9130
9131         return -ENODEV;
9132 }
9133
9134 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9135 {
9136         int rc = bnx2x_init_shmem(bp);
9137
9138         /* Restore the `magic' bit value */
9139         if (!CHIP_IS_E1(bp))
9140                 bnx2x_clp_reset_done(bp, magic_val);
9141
9142         return rc;
9143 }
9144
9145 static void bnx2x_pxp_prep(struct bnx2x *bp)
9146 {
9147         if (!CHIP_IS_E1(bp)) {
9148                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9149                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9150                 mmiowb();
9151         }
9152 }
9153
9154 /*
9155  * Reset the whole chip except for:
9156  *      - PCIE core
9157  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9158  *              one reset bit)
9159  *      - IGU
9160  *      - MISC (including AEU)
9161  *      - GRC
9162  *      - RBCN, RBCP
9163  */
9164 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9165 {
9166         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9167         u32 global_bits2, stay_reset2;
9168
9169         /*
9170          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9171          * (per chip) blocks.
9172          */
9173         global_bits2 =
9174                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9175                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9176
9177         /* Don't reset the following blocks.
9178          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9179          *            reset, as in 4 port device they might still be owned
9180          *            by the MCP (there is only one leader per path).
9181          */
9182         not_reset_mask1 =
9183                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9184                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9185                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9186
9187         not_reset_mask2 =
9188                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9189                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9190                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9191                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9192                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9193                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9194                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9195                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9196                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9197                 MISC_REGISTERS_RESET_REG_2_PGLC |
9198                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9199                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9200                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9201                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9202                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9203                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9204
9205         /*
9206          * Keep the following blocks in reset:
9207          *  - all xxMACs are handled by the bnx2x_link code.
9208          */
9209         stay_reset2 =
9210                 MISC_REGISTERS_RESET_REG_2_XMAC |
9211                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9212
9213         /* Full reset masks according to the chip */
9214         reset_mask1 = 0xffffffff;
9215
9216         if (CHIP_IS_E1(bp))
9217                 reset_mask2 = 0xffff;
9218         else if (CHIP_IS_E1H(bp))
9219                 reset_mask2 = 0x1ffff;
9220         else if (CHIP_IS_E2(bp))
9221                 reset_mask2 = 0xfffff;
9222         else /* CHIP_IS_E3 */
9223                 reset_mask2 = 0x3ffffff;
9224
9225         /* Don't reset global blocks unless we need to */
9226         if (!global)
9227                 reset_mask2 &= ~global_bits2;
9228
9229         /*
9230          * In case of attention in the QM, we need to reset PXP
9231          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9232          * because otherwise QM reset would release 'close the gates' shortly
9233          * before resetting the PXP, then the PSWRQ would send a write
9234          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9235          * read the payload data from PSWWR, but PSWWR would not
9236          * respond. The write queue in PGLUE would stuck, dmae commands
9237          * would not return. Therefore it's important to reset the second
9238          * reset register (containing the
9239          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9240          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9241          * bit).
9242          */
9243         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9244                reset_mask2 & (~not_reset_mask2));
9245
9246         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9247                reset_mask1 & (~not_reset_mask1));
9248
9249         barrier();
9250         mmiowb();
9251
9252         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9253                reset_mask2 & (~stay_reset2));
9254
9255         barrier();
9256         mmiowb();
9257
9258         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9259         mmiowb();
9260 }
9261
9262 /**
9263  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9264  * It should get cleared in no more than 1s.
9265  *
9266  * @bp: driver handle
9267  *
9268  * It should get cleared in no more than 1s. Returns 0 if
9269  * pending writes bit gets cleared.
9270  */
9271 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9272 {
9273         u32 cnt = 1000;
9274         u32 pend_bits = 0;
9275
9276         do {
9277                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9278
9279                 if (pend_bits == 0)
9280                         break;
9281
9282                 usleep_range(1000, 2000);
9283         } while (cnt-- > 0);
9284
9285         if (cnt <= 0) {
9286                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9287                           pend_bits);
9288                 return -EBUSY;
9289         }
9290
9291         return 0;
9292 }
9293
9294 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9295 {
9296         int cnt = 1000;
9297         u32 val = 0;
9298         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9299         u32 tags_63_32 = 0;
9300
9301         /* Empty the Tetris buffer, wait for 1s */
9302         do {
9303                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9304                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9305                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9306                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9307                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9308                 if (CHIP_IS_E3(bp))
9309                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9310
9311                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9312                     ((port_is_idle_0 & 0x1) == 0x1) &&
9313                     ((port_is_idle_1 & 0x1) == 0x1) &&
9314                     (pgl_exp_rom2 == 0xffffffff) &&
9315                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9316                         break;
9317                 usleep_range(1000, 2000);
9318         } while (cnt-- > 0);
9319
9320         if (cnt <= 0) {
9321                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9322                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9323                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9324                           pgl_exp_rom2);
9325                 return -EAGAIN;
9326         }
9327
9328         barrier();
9329
9330         /* Close gates #2, #3 and #4 */
9331         bnx2x_set_234_gates(bp, true);
9332
9333         /* Poll for IGU VQs for 57712 and newer chips */
9334         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9335                 return -EAGAIN;
9336
9337         /* TBD: Indicate that "process kill" is in progress to MCP */
9338
9339         /* Clear "unprepared" bit */
9340         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9341         barrier();
9342
9343         /* Make sure all is written to the chip before the reset */
9344         mmiowb();
9345
9346         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9347          * PSWHST, GRC and PSWRD Tetris buffer.
9348          */
9349         usleep_range(1000, 2000);
9350
9351         /* Prepare to chip reset: */
9352         /* MCP */
9353         if (global)
9354                 bnx2x_reset_mcp_prep(bp, &val);
9355
9356         /* PXP */
9357         bnx2x_pxp_prep(bp);
9358         barrier();
9359
9360         /* reset the chip */
9361         bnx2x_process_kill_chip_reset(bp, global);
9362         barrier();
9363
9364         /* clear errors in PGB */
9365         if (!CHIP_IS_E1x(bp))
9366                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9367
9368         /* Recover after reset: */
9369         /* MCP */
9370         if (global && bnx2x_reset_mcp_comp(bp, val))
9371                 return -EAGAIN;
9372
9373         /* TBD: Add resetting the NO_MCP mode DB here */
9374
9375         /* Open the gates #2, #3 and #4 */
9376         bnx2x_set_234_gates(bp, false);
9377
9378         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9379          * reset state, re-enable attentions. */
9380
9381         return 0;
9382 }
9383
9384 static int bnx2x_leader_reset(struct bnx2x *bp)
9385 {
9386         int rc = 0;
9387         bool global = bnx2x_reset_is_global(bp);
9388         u32 load_code;
9389
9390         /* if not going to reset MCP - load "fake" driver to reset HW while
9391          * driver is owner of the HW
9392          */
9393         if (!global && !BP_NOMCP(bp)) {
9394                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9395                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9396                 if (!load_code) {
9397                         BNX2X_ERR("MCP response failure, aborting\n");
9398                         rc = -EAGAIN;
9399                         goto exit_leader_reset;
9400                 }
9401                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9402                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9403                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9404                         rc = -EAGAIN;
9405                         goto exit_leader_reset2;
9406                 }
9407                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9408                 if (!load_code) {
9409                         BNX2X_ERR("MCP response failure, aborting\n");
9410                         rc = -EAGAIN;
9411                         goto exit_leader_reset2;
9412                 }
9413         }
9414
9415         /* Try to recover after the failure */
9416         if (bnx2x_process_kill(bp, global)) {
9417                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9418                           BP_PATH(bp));
9419                 rc = -EAGAIN;
9420                 goto exit_leader_reset2;
9421         }
9422
9423         /*
9424          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9425          * state.
9426          */
9427         bnx2x_set_reset_done(bp);
9428         if (global)
9429                 bnx2x_clear_reset_global(bp);
9430
9431 exit_leader_reset2:
9432         /* unload "fake driver" if it was loaded */
9433         if (!global && !BP_NOMCP(bp)) {
9434                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9435                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9436         }
9437 exit_leader_reset:
9438         bp->is_leader = 0;
9439         bnx2x_release_leader_lock(bp);
9440         smp_mb();
9441         return rc;
9442 }
9443
9444 static void bnx2x_recovery_failed(struct bnx2x *bp)
9445 {
9446         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9447
9448         /* Disconnect this device */
9449         netif_device_detach(bp->dev);
9450
9451         /*
9452          * Block ifup for all function on this engine until "process kill"
9453          * or power cycle.
9454          */
9455         bnx2x_set_reset_in_progress(bp);
9456
9457         /* Shut down the power */
9458         bnx2x_set_power_state(bp, PCI_D3hot);
9459
9460         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9461
9462         smp_mb();
9463 }
9464
9465 /*
9466  * Assumption: runs under rtnl lock. This together with the fact
9467  * that it's called only from bnx2x_sp_rtnl() ensure that it
9468  * will never be called when netif_running(bp->dev) is false.
9469  */
9470 static void bnx2x_parity_recover(struct bnx2x *bp)
9471 {
9472         bool global = false;
9473         u32 error_recovered, error_unrecovered;
9474         bool is_parity;
9475
9476         DP(NETIF_MSG_HW, "Handling parity\n");
9477         while (1) {
9478                 switch (bp->recovery_state) {
9479                 case BNX2X_RECOVERY_INIT:
9480                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9481                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9482                         WARN_ON(!is_parity);
9483
9484                         /* Try to get a LEADER_LOCK HW lock */
9485                         if (bnx2x_trylock_leader_lock(bp)) {
9486                                 bnx2x_set_reset_in_progress(bp);
9487                                 /*
9488                                  * Check if there is a global attention and if
9489                                  * there was a global attention, set the global
9490                                  * reset bit.
9491                                  */
9492
9493                                 if (global)
9494                                         bnx2x_set_reset_global(bp);
9495
9496                                 bp->is_leader = 1;
9497                         }
9498
9499                         /* Stop the driver */
9500                         /* If interface has been removed - break */
9501                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9502                                 return;
9503
9504                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9505
9506                         /* Ensure "is_leader", MCP command sequence and
9507                          * "recovery_state" update values are seen on other
9508                          * CPUs.
9509                          */
9510                         smp_mb();
9511                         break;
9512
9513                 case BNX2X_RECOVERY_WAIT:
9514                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9515                         if (bp->is_leader) {
9516                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9517                                 bool other_load_status =
9518                                         bnx2x_get_load_status(bp, other_engine);
9519                                 bool load_status =
9520                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9521                                 global = bnx2x_reset_is_global(bp);
9522
9523                                 /*
9524                                  * In case of a parity in a global block, let
9525                                  * the first leader that performs a
9526                                  * leader_reset() reset the global blocks in
9527                                  * order to clear global attentions. Otherwise
9528                                  * the gates will remain closed for that
9529                                  * engine.
9530                                  */
9531                                 if (load_status ||
9532                                     (global && other_load_status)) {
9533                                         /* Wait until all other functions get
9534                                          * down.
9535                                          */
9536                                         schedule_delayed_work(&bp->sp_rtnl_task,
9537                                                                 HZ/10);
9538                                         return;
9539                                 } else {
9540                                         /* If all other functions got down -
9541                                          * try to bring the chip back to
9542                                          * normal. In any case it's an exit
9543                                          * point for a leader.
9544                                          */
9545                                         if (bnx2x_leader_reset(bp)) {
9546                                                 bnx2x_recovery_failed(bp);
9547                                                 return;
9548                                         }
9549
9550                                         /* If we are here, means that the
9551                                          * leader has succeeded and doesn't
9552                                          * want to be a leader any more. Try
9553                                          * to continue as a none-leader.
9554                                          */
9555                                         break;
9556                                 }
9557                         } else { /* non-leader */
9558                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9559                                         /* Try to get a LEADER_LOCK HW lock as
9560                                          * long as a former leader may have
9561                                          * been unloaded by the user or
9562                                          * released a leadership by another
9563                                          * reason.
9564                                          */
9565                                         if (bnx2x_trylock_leader_lock(bp)) {
9566                                                 /* I'm a leader now! Restart a
9567                                                  * switch case.
9568                                                  */
9569                                                 bp->is_leader = 1;
9570                                                 break;
9571                                         }
9572
9573                                         schedule_delayed_work(&bp->sp_rtnl_task,
9574                                                                 HZ/10);
9575                                         return;
9576
9577                                 } else {
9578                                         /*
9579                                          * If there was a global attention, wait
9580                                          * for it to be cleared.
9581                                          */
9582                                         if (bnx2x_reset_is_global(bp)) {
9583                                                 schedule_delayed_work(
9584                                                         &bp->sp_rtnl_task,
9585                                                         HZ/10);
9586                                                 return;
9587                                         }
9588
9589                                         error_recovered =
9590                                           bp->eth_stats.recoverable_error;
9591                                         error_unrecovered =
9592                                           bp->eth_stats.unrecoverable_error;
9593                                         bp->recovery_state =
9594                                                 BNX2X_RECOVERY_NIC_LOADING;
9595                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9596                                                 error_unrecovered++;
9597                                                 netdev_err(bp->dev,
9598                                                            "Recovery failed. Power cycle needed\n");
9599                                                 /* Disconnect this device */
9600                                                 netif_device_detach(bp->dev);
9601                                                 /* Shut down the power */
9602                                                 bnx2x_set_power_state(
9603                                                         bp, PCI_D3hot);
9604                                                 smp_mb();
9605                                         } else {
9606                                                 bp->recovery_state =
9607                                                         BNX2X_RECOVERY_DONE;
9608                                                 error_recovered++;
9609                                                 smp_mb();
9610                                         }
9611                                         bp->eth_stats.recoverable_error =
9612                                                 error_recovered;
9613                                         bp->eth_stats.unrecoverable_error =
9614                                                 error_unrecovered;
9615
9616                                         return;
9617                                 }
9618                         }
9619                 default:
9620                         return;
9621                 }
9622         }
9623 }
9624
9625 static int bnx2x_close(struct net_device *dev);
9626
9627 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9628  * scheduled on a general queue in order to prevent a dead lock.
9629  */
9630 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9631 {
9632         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9633
9634         rtnl_lock();
9635
9636         if (!netif_running(bp->dev)) {
9637                 rtnl_unlock();
9638                 return;
9639         }
9640
9641         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9642 #ifdef BNX2X_STOP_ON_ERROR
9643                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9644                           "you will need to reboot when done\n");
9645                 goto sp_rtnl_not_reset;
9646 #endif
9647                 /*
9648                  * Clear all pending SP commands as we are going to reset the
9649                  * function anyway.
9650                  */
9651                 bp->sp_rtnl_state = 0;
9652                 smp_mb();
9653
9654                 bnx2x_parity_recover(bp);
9655
9656                 rtnl_unlock();
9657                 return;
9658         }
9659
9660         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9661 #ifdef BNX2X_STOP_ON_ERROR
9662                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9663                           "you will need to reboot when done\n");
9664                 goto sp_rtnl_not_reset;
9665 #endif
9666
9667                 /*
9668                  * Clear all pending SP commands as we are going to reset the
9669                  * function anyway.
9670                  */
9671                 bp->sp_rtnl_state = 0;
9672                 smp_mb();
9673
9674                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9675                 bnx2x_nic_load(bp, LOAD_NORMAL);
9676
9677                 rtnl_unlock();
9678                 return;
9679         }
9680 #ifdef BNX2X_STOP_ON_ERROR
9681 sp_rtnl_not_reset:
9682 #endif
9683         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9684                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9685         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9686                 bnx2x_after_function_update(bp);
9687         /*
9688          * in case of fan failure we need to reset id if the "stop on error"
9689          * debug flag is set, since we trying to prevent permanent overheating
9690          * damage
9691          */
9692         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9693                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9694                 netif_device_detach(bp->dev);
9695                 bnx2x_close(bp->dev);
9696                 rtnl_unlock();
9697                 return;
9698         }
9699
9700         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9701                 DP(BNX2X_MSG_SP,
9702                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9703                 bnx2x_vfpf_set_mcast(bp->dev);
9704         }
9705         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9706                                &bp->sp_rtnl_state)){
9707                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9708                         bnx2x_tx_disable(bp);
9709                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9710                 }
9711         }
9712
9713         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9714                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9715                 bnx2x_set_rx_mode_inner(bp);
9716         }
9717
9718         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9719                                &bp->sp_rtnl_state))
9720                 bnx2x_pf_set_vfs_vlan(bp);
9721
9722         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
9723                 bnx2x_dcbx_stop_hw_tx(bp);
9724                 bnx2x_dcbx_resume_hw_tx(bp);
9725         }
9726
9727         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9728          * can be called from other contexts as well)
9729          */
9730         rtnl_unlock();
9731
9732         /* enable SR-IOV if applicable */
9733         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9734                                                &bp->sp_rtnl_state)) {
9735                 bnx2x_disable_sriov(bp);
9736                 bnx2x_enable_sriov(bp);
9737         }
9738 }
9739
9740 static void bnx2x_period_task(struct work_struct *work)
9741 {
9742         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9743
9744         if (!netif_running(bp->dev))
9745                 goto period_task_exit;
9746
9747         if (CHIP_REV_IS_SLOW(bp)) {
9748                 BNX2X_ERR("period task called on emulation, ignoring\n");
9749                 goto period_task_exit;
9750         }
9751
9752         bnx2x_acquire_phy_lock(bp);
9753         /*
9754          * The barrier is needed to ensure the ordering between the writing to
9755          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9756          * the reading here.
9757          */
9758         smp_mb();
9759         if (bp->port.pmf) {
9760                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9761
9762                 /* Re-queue task in 1 sec */
9763                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9764         }
9765
9766         bnx2x_release_phy_lock(bp);
9767 period_task_exit:
9768         return;
9769 }
9770
9771 /*
9772  * Init service functions
9773  */
9774
9775 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9776 {
9777         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9778         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9779         return base + (BP_ABS_FUNC(bp)) * stride;
9780 }
9781
9782 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9783                                         struct bnx2x_mac_vals *vals)
9784 {
9785         u32 val, base_addr, offset, mask, reset_reg;
9786         bool mac_stopped = false;
9787         u8 port = BP_PORT(bp);
9788
9789         /* reset addresses as they also mark which values were changed */
9790         vals->bmac_addr = 0;
9791         vals->umac_addr = 0;
9792         vals->xmac_addr = 0;
9793         vals->emac_addr = 0;
9794
9795         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9796
9797         if (!CHIP_IS_E3(bp)) {
9798                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9799                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9800                 if ((mask & reset_reg) && val) {
9801                         u32 wb_data[2];
9802                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9803                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9804                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9805                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9806                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9807
9808                         /*
9809                          * use rd/wr since we cannot use dmae. This is safe
9810                          * since MCP won't access the bus due to the request
9811                          * to unload, and no function on the path can be
9812                          * loaded at this time.
9813                          */
9814                         wb_data[0] = REG_RD(bp, base_addr + offset);
9815                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9816                         vals->bmac_addr = base_addr + offset;
9817                         vals->bmac_val[0] = wb_data[0];
9818                         vals->bmac_val[1] = wb_data[1];
9819                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9820                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
9821                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9822                 }
9823                 BNX2X_DEV_INFO("Disable emac Rx\n");
9824                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9825                 vals->emac_val = REG_RD(bp, vals->emac_addr);
9826                 REG_WR(bp, vals->emac_addr, 0);
9827                 mac_stopped = true;
9828         } else {
9829                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9830                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9831                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9832                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9833                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9834                                val & ~(1 << 1));
9835                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9836                                val | (1 << 1));
9837                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9838                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9839                         REG_WR(bp, vals->xmac_addr, 0);
9840                         mac_stopped = true;
9841                 }
9842                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9843                 if (mask & reset_reg) {
9844                         BNX2X_DEV_INFO("Disable umac Rx\n");
9845                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9846                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9847                         vals->umac_val = REG_RD(bp, vals->umac_addr);
9848                         REG_WR(bp, vals->umac_addr, 0);
9849                         mac_stopped = true;
9850                 }
9851         }
9852
9853         if (mac_stopped)
9854                 msleep(20);
9855 }
9856
9857 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9858 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9859 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9860 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9861
9862 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
9863 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
9864 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
9865 #define BNX2X_PREV_UNDI_MF_PORT(p)      (0x1a150c + ((p) << 4))
9866 #define BNX2X_PREV_UNDI_MF_FUNC(f)      (0x1a184c + ((f) << 4))
9867 static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
9868 {
9869         u8 major, minor, version;
9870         u32 fw;
9871
9872         /* Must check that FW is loaded */
9873         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
9874              MISC_REGISTERS_RESET_REG_1_RST_XSEM)) {
9875                 BNX2X_DEV_INFO("XSEM is reset - UNDI MF FW is not loaded\n");
9876                 return false;
9877         }
9878
9879         /* Read Currently loaded FW version */
9880         fw = REG_RD(bp, XSEM_REG_PRAM);
9881         major = fw & 0xff;
9882         minor = (fw >> 0x8) & 0xff;
9883         version = (fw >> 0x10) & 0xff;
9884         BNX2X_DEV_INFO("Loaded FW: 0x%08x: Major 0x%02x Minor 0x%02x Version 0x%02x\n",
9885                        fw, major, minor, version);
9886
9887         if (major > BCM_5710_UNDI_FW_MF_MAJOR)
9888                 return true;
9889
9890         if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
9891             (minor > BCM_5710_UNDI_FW_MF_MINOR))
9892                 return true;
9893
9894         if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
9895             (minor == BCM_5710_UNDI_FW_MF_MINOR) &&
9896             (version >= BCM_5710_UNDI_FW_MF_VERS))
9897                 return true;
9898
9899         return false;
9900 }
9901
9902 static void bnx2x_prev_unload_undi_mf(struct bnx2x *bp)
9903 {
9904         int i;
9905
9906         /* Due to legacy (FW) code, the first function on each engine has a
9907          * different offset macro from the rest of the functions.
9908          * Setting this for all 8 functions is harmless regardless of whether
9909          * this is actually a multi-function device.
9910          */
9911         for (i = 0; i < 2; i++)
9912                 REG_WR(bp, BNX2X_PREV_UNDI_MF_PORT(i), 1);
9913
9914         for (i = 2; i < 8; i++)
9915                 REG_WR(bp, BNX2X_PREV_UNDI_MF_FUNC(i - 2), 1);
9916
9917         BNX2X_DEV_INFO("UNDI FW (MF) set to discard\n");
9918 }
9919
9920 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9921 {
9922         u16 rcq, bd;
9923         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9924
9925         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9926         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9927
9928         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9929         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9930
9931         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9932                        port, bd, rcq);
9933 }
9934
9935 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9936 {
9937         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9938                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9939         if (!rc) {
9940                 BNX2X_ERR("MCP response failure, aborting\n");
9941                 return -EBUSY;
9942         }
9943
9944         return 0;
9945 }
9946
9947 static struct bnx2x_prev_path_list *
9948                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9949 {
9950         struct bnx2x_prev_path_list *tmp_list;
9951
9952         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9953                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9954                     bp->pdev->bus->number == tmp_list->bus &&
9955                     BP_PATH(bp) == tmp_list->path)
9956                         return tmp_list;
9957
9958         return NULL;
9959 }
9960
9961 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9962 {
9963         struct bnx2x_prev_path_list *tmp_list;
9964         int rc;
9965
9966         rc = down_interruptible(&bnx2x_prev_sem);
9967         if (rc) {
9968                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9969                 return rc;
9970         }
9971
9972         tmp_list = bnx2x_prev_path_get_entry(bp);
9973         if (tmp_list) {
9974                 tmp_list->aer = 1;
9975                 rc = 0;
9976         } else {
9977                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9978                           BP_PATH(bp));
9979         }
9980
9981         up(&bnx2x_prev_sem);
9982
9983         return rc;
9984 }
9985
9986 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9987 {
9988         struct bnx2x_prev_path_list *tmp_list;
9989         bool rc = false;
9990
9991         if (down_trylock(&bnx2x_prev_sem))
9992                 return false;
9993
9994         tmp_list = bnx2x_prev_path_get_entry(bp);
9995         if (tmp_list) {
9996                 if (tmp_list->aer) {
9997                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9998                            BP_PATH(bp));
9999                 } else {
10000                         rc = true;
10001                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10002                                        BP_PATH(bp));
10003                 }
10004         }
10005
10006         up(&bnx2x_prev_sem);
10007
10008         return rc;
10009 }
10010
10011 bool bnx2x_port_after_undi(struct bnx2x *bp)
10012 {
10013         struct bnx2x_prev_path_list *entry;
10014         bool val;
10015
10016         down(&bnx2x_prev_sem);
10017
10018         entry = bnx2x_prev_path_get_entry(bp);
10019         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10020
10021         up(&bnx2x_prev_sem);
10022
10023         return val;
10024 }
10025
10026 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10027 {
10028         struct bnx2x_prev_path_list *tmp_list;
10029         int rc;
10030
10031         rc = down_interruptible(&bnx2x_prev_sem);
10032         if (rc) {
10033                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10034                 return rc;
10035         }
10036
10037         /* Check whether the entry for this path already exists */
10038         tmp_list = bnx2x_prev_path_get_entry(bp);
10039         if (tmp_list) {
10040                 if (!tmp_list->aer) {
10041                         BNX2X_ERR("Re-Marking the path.\n");
10042                 } else {
10043                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10044                            BP_PATH(bp));
10045                         tmp_list->aer = 0;
10046                 }
10047                 up(&bnx2x_prev_sem);
10048                 return 0;
10049         }
10050         up(&bnx2x_prev_sem);
10051
10052         /* Create an entry for this path and add it */
10053         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10054         if (!tmp_list) {
10055                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10056                 return -ENOMEM;
10057         }
10058
10059         tmp_list->bus = bp->pdev->bus->number;
10060         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10061         tmp_list->path = BP_PATH(bp);
10062         tmp_list->aer = 0;
10063         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10064
10065         rc = down_interruptible(&bnx2x_prev_sem);
10066         if (rc) {
10067                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10068                 kfree(tmp_list);
10069         } else {
10070                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10071                    BP_PATH(bp));
10072                 list_add(&tmp_list->list, &bnx2x_prev_list);
10073                 up(&bnx2x_prev_sem);
10074         }
10075
10076         return rc;
10077 }
10078
10079 static int bnx2x_do_flr(struct bnx2x *bp)
10080 {
10081         struct pci_dev *dev = bp->pdev;
10082
10083         if (CHIP_IS_E1x(bp)) {
10084                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10085                 return -EINVAL;
10086         }
10087
10088         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10089         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10090                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10091                           bp->common.bc_ver);
10092                 return -EINVAL;
10093         }
10094
10095         if (!pci_wait_for_pending_transaction(dev))
10096                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10097
10098         BNX2X_DEV_INFO("Initiating FLR\n");
10099         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10100
10101         return 0;
10102 }
10103
10104 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10105 {
10106         int rc;
10107
10108         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10109
10110         /* Test if previous unload process was already finished for this path */
10111         if (bnx2x_prev_is_path_marked(bp))
10112                 return bnx2x_prev_mcp_done(bp);
10113
10114         BNX2X_DEV_INFO("Path is unmarked\n");
10115
10116         /* If function has FLR capabilities, and existing FW version matches
10117          * the one required, then FLR will be sufficient to clean any residue
10118          * left by previous driver
10119          */
10120         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10121
10122         if (!rc) {
10123                 /* fw version is good */
10124                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10125                 rc = bnx2x_do_flr(bp);
10126         }
10127
10128         if (!rc) {
10129                 /* FLR was performed */
10130                 BNX2X_DEV_INFO("FLR successful\n");
10131                 return 0;
10132         }
10133
10134         BNX2X_DEV_INFO("Could not FLR\n");
10135
10136         /* Close the MCP request, return failure*/
10137         rc = bnx2x_prev_mcp_done(bp);
10138         if (!rc)
10139                 rc = BNX2X_PREV_WAIT_NEEDED;
10140
10141         return rc;
10142 }
10143
10144 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10145 {
10146         u32 reset_reg, tmp_reg = 0, rc;
10147         bool prev_undi = false;
10148         struct bnx2x_mac_vals mac_vals;
10149
10150         /* It is possible a previous function received 'common' answer,
10151          * but hasn't loaded yet, therefore creating a scenario of
10152          * multiple functions receiving 'common' on the same path.
10153          */
10154         BNX2X_DEV_INFO("Common unload Flow\n");
10155
10156         memset(&mac_vals, 0, sizeof(mac_vals));
10157
10158         if (bnx2x_prev_is_path_marked(bp))
10159                 return bnx2x_prev_mcp_done(bp);
10160
10161         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10162
10163         /* Reset should be performed after BRB is emptied */
10164         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10165                 u32 timer_count = 1000;
10166
10167                 /* Close the MAC Rx to prevent BRB from filling up */
10168                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10169
10170                 /* close LLH filters towards the BRB */
10171                 bnx2x_set_rx_filter(&bp->link_params, 0);
10172
10173                 /* Check if the UNDI driver was previously loaded
10174                  * UNDI driver initializes CID offset for normal bell to 0x7
10175                  */
10176                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10177                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10178                         if (tmp_reg == 0x7) {
10179                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10180                                 prev_undi = true;
10181                                 /* clear the UNDI indication */
10182                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10183                                 /* clear possible idle check errors */
10184                                 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10185                         }
10186                 }
10187                 if (!CHIP_IS_E1x(bp))
10188                         /* block FW from writing to host */
10189                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10190
10191                 /* wait until BRB is empty */
10192                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10193                 while (timer_count) {
10194                         u32 prev_brb = tmp_reg;
10195
10196                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10197                         if (!tmp_reg)
10198                                 break;
10199
10200                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10201
10202                         /* reset timer as long as BRB actually gets emptied */
10203                         if (prev_brb > tmp_reg)
10204                                 timer_count = 1000;
10205                         else
10206                                 timer_count--;
10207
10208                         /* New UNDI FW supports MF and contains better
10209                          * cleaning methods - might be redundant but harmless.
10210                          */
10211                         if (bnx2x_prev_unload_undi_fw_supports_mf(bp)) {
10212                                 bnx2x_prev_unload_undi_mf(bp);
10213                         } else if (prev_undi) {
10214                                 /* If UNDI resides in memory,
10215                                  * manually increment it
10216                                  */
10217                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10218                         }
10219                         udelay(10);
10220                 }
10221
10222                 if (!timer_count)
10223                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10224         }
10225
10226         /* No packets are in the pipeline, path is ready for reset */
10227         bnx2x_reset_common(bp);
10228
10229         if (mac_vals.xmac_addr)
10230                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10231         if (mac_vals.umac_addr)
10232                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10233         if (mac_vals.emac_addr)
10234                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10235         if (mac_vals.bmac_addr) {
10236                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10237                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10238         }
10239
10240         rc = bnx2x_prev_mark_path(bp, prev_undi);
10241         if (rc) {
10242                 bnx2x_prev_mcp_done(bp);
10243                 return rc;
10244         }
10245
10246         return bnx2x_prev_mcp_done(bp);
10247 }
10248
10249 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10250  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10251  * the addresses of the transaction, resulting in was-error bit set in the pci
10252  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10253  * to clear the interrupt which detected this from the pglueb and the was done
10254  * bit
10255  */
10256 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10257 {
10258         if (!CHIP_IS_E1x(bp)) {
10259                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10260                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10261                         DP(BNX2X_MSG_SP,
10262                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10263                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10264                                1 << BP_FUNC(bp));
10265                 }
10266         }
10267 }
10268
10269 static int bnx2x_prev_unload(struct bnx2x *bp)
10270 {
10271         int time_counter = 10;
10272         u32 rc, fw, hw_lock_reg, hw_lock_val;
10273         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10274
10275         /* clear hw from errors which may have resulted from an interrupted
10276          * dmae transaction.
10277          */
10278         bnx2x_prev_interrupted_dmae(bp);
10279
10280         /* Release previously held locks */
10281         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10282                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10283                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10284
10285         hw_lock_val = REG_RD(bp, hw_lock_reg);
10286         if (hw_lock_val) {
10287                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10288                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10289                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10290                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10291                 }
10292
10293                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10294                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10295         } else
10296                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10297
10298         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10299                 BNX2X_DEV_INFO("Release previously held alr\n");
10300                 bnx2x_release_alr(bp);
10301         }
10302
10303         do {
10304                 int aer = 0;
10305                 /* Lock MCP using an unload request */
10306                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10307                 if (!fw) {
10308                         BNX2X_ERR("MCP response failure, aborting\n");
10309                         rc = -EBUSY;
10310                         break;
10311                 }
10312
10313                 rc = down_interruptible(&bnx2x_prev_sem);
10314                 if (rc) {
10315                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10316                                   rc);
10317                 } else {
10318                         /* If Path is marked by EEH, ignore unload status */
10319                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10320                                  bnx2x_prev_path_get_entry(bp)->aer);
10321                         up(&bnx2x_prev_sem);
10322                 }
10323
10324                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10325                         rc = bnx2x_prev_unload_common(bp);
10326                         break;
10327                 }
10328
10329                 /* non-common reply from MCP might require looping */
10330                 rc = bnx2x_prev_unload_uncommon(bp);
10331                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10332                         break;
10333
10334                 msleep(20);
10335         } while (--time_counter);
10336
10337         if (!time_counter || rc) {
10338                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10339                 rc = -EPROBE_DEFER;
10340         }
10341
10342         /* Mark function if its port was used to boot from SAN */
10343         if (bnx2x_port_after_undi(bp))
10344                 bp->link_params.feature_config_flags |=
10345                         FEATURE_CONFIG_BOOT_FROM_SAN;
10346
10347         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10348
10349         return rc;
10350 }
10351
10352 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10353 {
10354         u32 val, val2, val3, val4, id, boot_mode;
10355         u16 pmc;
10356
10357         /* Get the chip revision id and number. */
10358         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10359         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10360         id = ((val & 0xffff) << 16);
10361         val = REG_RD(bp, MISC_REG_CHIP_REV);
10362         id |= ((val & 0xf) << 12);
10363
10364         /* Metal is read from PCI regs, but we can't access >=0x400 from
10365          * the configuration space (so we need to reg_rd)
10366          */
10367         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10368         id |= (((val >> 24) & 0xf) << 4);
10369         val = REG_RD(bp, MISC_REG_BOND_ID);
10370         id |= (val & 0xf);
10371         bp->common.chip_id = id;
10372
10373         /* force 57811 according to MISC register */
10374         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10375                 if (CHIP_IS_57810(bp))
10376                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10377                                 (bp->common.chip_id & 0x0000FFFF);
10378                 else if (CHIP_IS_57810_MF(bp))
10379                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10380                                 (bp->common.chip_id & 0x0000FFFF);
10381                 bp->common.chip_id |= 0x1;
10382         }
10383
10384         /* Set doorbell size */
10385         bp->db_size = (1 << BNX2X_DB_SHIFT);
10386
10387         if (!CHIP_IS_E1x(bp)) {
10388                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10389                 if ((val & 1) == 0)
10390                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10391                 else
10392                         val = (val >> 1) & 1;
10393                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10394                                                        "2_PORT_MODE");
10395                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10396                                                  CHIP_2_PORT_MODE;
10397
10398                 if (CHIP_MODE_IS_4_PORT(bp))
10399                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10400                 else
10401                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10402         } else {
10403                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10404                 bp->pfid = bp->pf_num;                  /* 0..7 */
10405         }
10406
10407         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10408
10409         bp->link_params.chip_id = bp->common.chip_id;
10410         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10411
10412         val = (REG_RD(bp, 0x2874) & 0x55);
10413         if ((bp->common.chip_id & 0x1) ||
10414             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10415                 bp->flags |= ONE_PORT_FLAG;
10416                 BNX2X_DEV_INFO("single port device\n");
10417         }
10418
10419         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10420         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10421                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10422         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10423                        bp->common.flash_size, bp->common.flash_size);
10424
10425         bnx2x_init_shmem(bp);
10426
10427         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10428                                         MISC_REG_GENERIC_CR_1 :
10429                                         MISC_REG_GENERIC_CR_0));
10430
10431         bp->link_params.shmem_base = bp->common.shmem_base;
10432         bp->link_params.shmem2_base = bp->common.shmem2_base;
10433         if (SHMEM2_RD(bp, size) >
10434             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10435                 bp->link_params.lfa_base =
10436                 REG_RD(bp, bp->common.shmem2_base +
10437                        (u32)offsetof(struct shmem2_region,
10438                                      lfa_host_addr[BP_PORT(bp)]));
10439         else
10440                 bp->link_params.lfa_base = 0;
10441         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10442                        bp->common.shmem_base, bp->common.shmem2_base);
10443
10444         if (!bp->common.shmem_base) {
10445                 BNX2X_DEV_INFO("MCP not active\n");
10446                 bp->flags |= NO_MCP_FLAG;
10447                 return;
10448         }
10449
10450         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10451         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10452
10453         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10454                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10455                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10456
10457         bp->link_params.feature_config_flags = 0;
10458         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10459         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10460                 bp->link_params.feature_config_flags |=
10461                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10462         else
10463                 bp->link_params.feature_config_flags &=
10464                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10465
10466         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10467         bp->common.bc_ver = val;
10468         BNX2X_DEV_INFO("bc_ver %X\n", val);
10469         if (val < BNX2X_BC_VER) {
10470                 /* for now only warn
10471                  * later we might need to enforce this */
10472                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10473                           BNX2X_BC_VER, val);
10474         }
10475         bp->link_params.feature_config_flags |=
10476                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10477                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10478
10479         bp->link_params.feature_config_flags |=
10480                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10481                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10482         bp->link_params.feature_config_flags |=
10483                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10484                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10485         bp->link_params.feature_config_flags |=
10486                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10487                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10488
10489         bp->link_params.feature_config_flags |=
10490                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10491                 FEATURE_CONFIG_MT_SUPPORT : 0;
10492
10493         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10494                         BC_SUPPORTS_PFC_STATS : 0;
10495
10496         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10497                         BC_SUPPORTS_FCOE_FEATURES : 0;
10498
10499         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10500                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10501
10502         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10503                         BC_SUPPORTS_RMMOD_CMD : 0;
10504
10505         boot_mode = SHMEM_RD(bp,
10506                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10507                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10508         switch (boot_mode) {
10509         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10510                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10511                 break;
10512         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10513                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10514                 break;
10515         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10516                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10517                 break;
10518         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10519                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10520                 break;
10521         }
10522
10523         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10524         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10525
10526         BNX2X_DEV_INFO("%sWoL capable\n",
10527                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10528
10529         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10530         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10531         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10532         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10533
10534         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10535                  val, val2, val3, val4);
10536 }
10537
10538 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10539 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10540
10541 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10542 {
10543         int pfid = BP_FUNC(bp);
10544         int igu_sb_id;
10545         u32 val;
10546         u8 fid, igu_sb_cnt = 0;
10547
10548         bp->igu_base_sb = 0xff;
10549         if (CHIP_INT_MODE_IS_BC(bp)) {
10550                 int vn = BP_VN(bp);
10551                 igu_sb_cnt = bp->igu_sb_cnt;
10552                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10553                         FP_SB_MAX_E1x;
10554
10555                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10556                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10557
10558                 return 0;
10559         }
10560
10561         /* IGU in normal mode - read CAM */
10562         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10563              igu_sb_id++) {
10564                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10565                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10566                         continue;
10567                 fid = IGU_FID(val);
10568                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10569                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10570                                 continue;
10571                         if (IGU_VEC(val) == 0)
10572                                 /* default status block */
10573                                 bp->igu_dsb_id = igu_sb_id;
10574                         else {
10575                                 if (bp->igu_base_sb == 0xff)
10576                                         bp->igu_base_sb = igu_sb_id;
10577                                 igu_sb_cnt++;
10578                         }
10579                 }
10580         }
10581
10582 #ifdef CONFIG_PCI_MSI
10583         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10584          * optional that number of CAM entries will not be equal to the value
10585          * advertised in PCI.
10586          * Driver should use the minimal value of both as the actual status
10587          * block count
10588          */
10589         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10590 #endif
10591
10592         if (igu_sb_cnt == 0) {
10593                 BNX2X_ERR("CAM configuration error\n");
10594                 return -EINVAL;
10595         }
10596
10597         return 0;
10598 }
10599
10600 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10601 {
10602         int cfg_size = 0, idx, port = BP_PORT(bp);
10603
10604         /* Aggregation of supported attributes of all external phys */
10605         bp->port.supported[0] = 0;
10606         bp->port.supported[1] = 0;
10607         switch (bp->link_params.num_phys) {
10608         case 1:
10609                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10610                 cfg_size = 1;
10611                 break;
10612         case 2:
10613                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10614                 cfg_size = 1;
10615                 break;
10616         case 3:
10617                 if (bp->link_params.multi_phy_config &
10618                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10619                         bp->port.supported[1] =
10620                                 bp->link_params.phy[EXT_PHY1].supported;
10621                         bp->port.supported[0] =
10622                                 bp->link_params.phy[EXT_PHY2].supported;
10623                 } else {
10624                         bp->port.supported[0] =
10625                                 bp->link_params.phy[EXT_PHY1].supported;
10626                         bp->port.supported[1] =
10627                                 bp->link_params.phy[EXT_PHY2].supported;
10628                 }
10629                 cfg_size = 2;
10630                 break;
10631         }
10632
10633         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10634                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10635                            SHMEM_RD(bp,
10636                            dev_info.port_hw_config[port].external_phy_config),
10637                            SHMEM_RD(bp,
10638                            dev_info.port_hw_config[port].external_phy_config2));
10639                         return;
10640         }
10641
10642         if (CHIP_IS_E3(bp))
10643                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10644         else {
10645                 switch (switch_cfg) {
10646                 case SWITCH_CFG_1G:
10647                         bp->port.phy_addr = REG_RD(
10648                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10649                         break;
10650                 case SWITCH_CFG_10G:
10651                         bp->port.phy_addr = REG_RD(
10652                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10653                         break;
10654                 default:
10655                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10656                                   bp->port.link_config[0]);
10657                         return;
10658                 }
10659         }
10660         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10661         /* mask what we support according to speed_cap_mask per configuration */
10662         for (idx = 0; idx < cfg_size; idx++) {
10663                 if (!(bp->link_params.speed_cap_mask[idx] &
10664                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10665                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10666
10667                 if (!(bp->link_params.speed_cap_mask[idx] &
10668                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10669                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10670
10671                 if (!(bp->link_params.speed_cap_mask[idx] &
10672                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10673                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10674
10675                 if (!(bp->link_params.speed_cap_mask[idx] &
10676                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10677                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10678
10679                 if (!(bp->link_params.speed_cap_mask[idx] &
10680                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10681                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10682                                                      SUPPORTED_1000baseT_Full);
10683
10684                 if (!(bp->link_params.speed_cap_mask[idx] &
10685                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10686                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10687
10688                 if (!(bp->link_params.speed_cap_mask[idx] &
10689                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10690                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10691
10692                 if (!(bp->link_params.speed_cap_mask[idx] &
10693                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10694                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10695         }
10696
10697         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10698                        bp->port.supported[1]);
10699 }
10700
10701 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10702 {
10703         u32 link_config, idx, cfg_size = 0;
10704         bp->port.advertising[0] = 0;
10705         bp->port.advertising[1] = 0;
10706         switch (bp->link_params.num_phys) {
10707         case 1:
10708         case 2:
10709                 cfg_size = 1;
10710                 break;
10711         case 3:
10712                 cfg_size = 2;
10713                 break;
10714         }
10715         for (idx = 0; idx < cfg_size; idx++) {
10716                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10717                 link_config = bp->port.link_config[idx];
10718                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10719                 case PORT_FEATURE_LINK_SPEED_AUTO:
10720                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10721                                 bp->link_params.req_line_speed[idx] =
10722                                         SPEED_AUTO_NEG;
10723                                 bp->port.advertising[idx] |=
10724                                         bp->port.supported[idx];
10725                                 if (bp->link_params.phy[EXT_PHY1].type ==
10726                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10727                                         bp->port.advertising[idx] |=
10728                                         (SUPPORTED_100baseT_Half |
10729                                          SUPPORTED_100baseT_Full);
10730                         } else {
10731                                 /* force 10G, no AN */
10732                                 bp->link_params.req_line_speed[idx] =
10733                                         SPEED_10000;
10734                                 bp->port.advertising[idx] |=
10735                                         (ADVERTISED_10000baseT_Full |
10736                                          ADVERTISED_FIBRE);
10737                                 continue;
10738                         }
10739                         break;
10740
10741                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10742                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10743                                 bp->link_params.req_line_speed[idx] =
10744                                         SPEED_10;
10745                                 bp->port.advertising[idx] |=
10746                                         (ADVERTISED_10baseT_Full |
10747                                          ADVERTISED_TP);
10748                         } else {
10749                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10750                                             link_config,
10751                                     bp->link_params.speed_cap_mask[idx]);
10752                                 return;
10753                         }
10754                         break;
10755
10756                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10757                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10758                                 bp->link_params.req_line_speed[idx] =
10759                                         SPEED_10;
10760                                 bp->link_params.req_duplex[idx] =
10761                                         DUPLEX_HALF;
10762                                 bp->port.advertising[idx] |=
10763                                         (ADVERTISED_10baseT_Half |
10764                                          ADVERTISED_TP);
10765                         } else {
10766                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10767                                             link_config,
10768                                           bp->link_params.speed_cap_mask[idx]);
10769                                 return;
10770                         }
10771                         break;
10772
10773                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10774                         if (bp->port.supported[idx] &
10775                             SUPPORTED_100baseT_Full) {
10776                                 bp->link_params.req_line_speed[idx] =
10777                                         SPEED_100;
10778                                 bp->port.advertising[idx] |=
10779                                         (ADVERTISED_100baseT_Full |
10780                                          ADVERTISED_TP);
10781                         } else {
10782                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10783                                             link_config,
10784                                           bp->link_params.speed_cap_mask[idx]);
10785                                 return;
10786                         }
10787                         break;
10788
10789                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10790                         if (bp->port.supported[idx] &
10791                             SUPPORTED_100baseT_Half) {
10792                                 bp->link_params.req_line_speed[idx] =
10793                                                                 SPEED_100;
10794                                 bp->link_params.req_duplex[idx] =
10795                                                                 DUPLEX_HALF;
10796                                 bp->port.advertising[idx] |=
10797                                         (ADVERTISED_100baseT_Half |
10798                                          ADVERTISED_TP);
10799                         } else {
10800                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10801                                     link_config,
10802                                     bp->link_params.speed_cap_mask[idx]);
10803                                 return;
10804                         }
10805                         break;
10806
10807                 case PORT_FEATURE_LINK_SPEED_1G:
10808                         if (bp->port.supported[idx] &
10809                             SUPPORTED_1000baseT_Full) {
10810                                 bp->link_params.req_line_speed[idx] =
10811                                         SPEED_1000;
10812                                 bp->port.advertising[idx] |=
10813                                         (ADVERTISED_1000baseT_Full |
10814                                          ADVERTISED_TP);
10815                         } else {
10816                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10817                                     link_config,
10818                                     bp->link_params.speed_cap_mask[idx]);
10819                                 return;
10820                         }
10821                         break;
10822
10823                 case PORT_FEATURE_LINK_SPEED_2_5G:
10824                         if (bp->port.supported[idx] &
10825                             SUPPORTED_2500baseX_Full) {
10826                                 bp->link_params.req_line_speed[idx] =
10827                                         SPEED_2500;
10828                                 bp->port.advertising[idx] |=
10829                                         (ADVERTISED_2500baseX_Full |
10830                                                 ADVERTISED_TP);
10831                         } else {
10832                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10833                                     link_config,
10834                                     bp->link_params.speed_cap_mask[idx]);
10835                                 return;
10836                         }
10837                         break;
10838
10839                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10840                         if (bp->port.supported[idx] &
10841                             SUPPORTED_10000baseT_Full) {
10842                                 bp->link_params.req_line_speed[idx] =
10843                                         SPEED_10000;
10844                                 bp->port.advertising[idx] |=
10845                                         (ADVERTISED_10000baseT_Full |
10846                                                 ADVERTISED_FIBRE);
10847                         } else {
10848                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10849                                     link_config,
10850                                     bp->link_params.speed_cap_mask[idx]);
10851                                 return;
10852                         }
10853                         break;
10854                 case PORT_FEATURE_LINK_SPEED_20G:
10855                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10856
10857                         break;
10858                 default:
10859                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10860                                   link_config);
10861                                 bp->link_params.req_line_speed[idx] =
10862                                                         SPEED_AUTO_NEG;
10863                                 bp->port.advertising[idx] =
10864                                                 bp->port.supported[idx];
10865                         break;
10866                 }
10867
10868                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10869                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10870                 if (bp->link_params.req_flow_ctrl[idx] ==
10871                     BNX2X_FLOW_CTRL_AUTO) {
10872                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10873                                 bp->link_params.req_flow_ctrl[idx] =
10874                                                         BNX2X_FLOW_CTRL_NONE;
10875                         else
10876                                 bnx2x_set_requested_fc(bp);
10877                 }
10878
10879                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10880                                bp->link_params.req_line_speed[idx],
10881                                bp->link_params.req_duplex[idx],
10882                                bp->link_params.req_flow_ctrl[idx],
10883                                bp->port.advertising[idx]);
10884         }
10885 }
10886
10887 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10888 {
10889         __be16 mac_hi_be = cpu_to_be16(mac_hi);
10890         __be32 mac_lo_be = cpu_to_be32(mac_lo);
10891         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10892         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10893 }
10894
10895 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10896 {
10897         int port = BP_PORT(bp);
10898         u32 config;
10899         u32 ext_phy_type, ext_phy_config, eee_mode;
10900
10901         bp->link_params.bp = bp;
10902         bp->link_params.port = port;
10903
10904         bp->link_params.lane_config =
10905                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10906
10907         bp->link_params.speed_cap_mask[0] =
10908                 SHMEM_RD(bp,
10909                          dev_info.port_hw_config[port].speed_capability_mask) &
10910                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10911         bp->link_params.speed_cap_mask[1] =
10912                 SHMEM_RD(bp,
10913                          dev_info.port_hw_config[port].speed_capability_mask2) &
10914                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10915         bp->port.link_config[0] =
10916                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10917
10918         bp->port.link_config[1] =
10919                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10920
10921         bp->link_params.multi_phy_config =
10922                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10923         /* If the device is capable of WoL, set the default state according
10924          * to the HW
10925          */
10926         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10927         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10928                    (config & PORT_FEATURE_WOL_ENABLED));
10929
10930         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10931             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10932                 bp->flags |= NO_ISCSI_FLAG;
10933         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10934             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10935                 bp->flags |= NO_FCOE_FLAG;
10936
10937         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10938                        bp->link_params.lane_config,
10939                        bp->link_params.speed_cap_mask[0],
10940                        bp->port.link_config[0]);
10941
10942         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10943                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10944         bnx2x_phy_probe(&bp->link_params);
10945         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10946
10947         bnx2x_link_settings_requested(bp);
10948
10949         /*
10950          * If connected directly, work with the internal PHY, otherwise, work
10951          * with the external PHY
10952          */
10953         ext_phy_config =
10954                 SHMEM_RD(bp,
10955                          dev_info.port_hw_config[port].external_phy_config);
10956         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10957         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10958                 bp->mdio.prtad = bp->port.phy_addr;
10959
10960         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10961                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10962                 bp->mdio.prtad =
10963                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10964
10965         /* Configure link feature according to nvram value */
10966         eee_mode = (((SHMEM_RD(bp, dev_info.
10967                       port_feature_config[port].eee_power_mode)) &
10968                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10969                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10970         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10971                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10972                                            EEE_MODE_ENABLE_LPI |
10973                                            EEE_MODE_OUTPUT_TIME;
10974         } else {
10975                 bp->link_params.eee_mode = 0;
10976         }
10977 }
10978
10979 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10980 {
10981         u32 no_flags = NO_ISCSI_FLAG;
10982         int port = BP_PORT(bp);
10983         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10984                                 drv_lic_key[port].max_iscsi_conn);
10985
10986         if (!CNIC_SUPPORT(bp)) {
10987                 bp->flags |= no_flags;
10988                 return;
10989         }
10990
10991         /* Get the number of maximum allowed iSCSI connections */
10992         bp->cnic_eth_dev.max_iscsi_conn =
10993                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10994                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10995
10996         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10997                        bp->cnic_eth_dev.max_iscsi_conn);
10998
10999         /*
11000          * If maximum allowed number of connections is zero -
11001          * disable the feature.
11002          */
11003         if (!bp->cnic_eth_dev.max_iscsi_conn)
11004                 bp->flags |= no_flags;
11005 }
11006
11007 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11008 {
11009         /* Port info */
11010         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11011                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11012         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11013                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11014
11015         /* Node info */
11016         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11017                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11018         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11019                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11020 }
11021
11022 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11023 {
11024         u8 count = 0;
11025
11026         if (IS_MF(bp)) {
11027                 u8 fid;
11028
11029                 /* iterate over absolute function ids for this path: */
11030                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11031                         if (IS_MF_SD(bp)) {
11032                                 u32 cfg = MF_CFG_RD(bp,
11033                                                     func_mf_config[fid].config);
11034
11035                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11036                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11037                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11038                                         count++;
11039                         } else {
11040                                 u32 cfg = MF_CFG_RD(bp,
11041                                                     func_ext_config[fid].
11042                                                                       func_cfg);
11043
11044                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11045                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11046                                         count++;
11047                         }
11048                 }
11049         } else { /* SF */
11050                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11051
11052                 for (port = 0; port < port_cnt; port++) {
11053                         u32 lic = SHMEM_RD(bp,
11054                                            drv_lic_key[port].max_fcoe_conn) ^
11055                                   FW_ENCODE_32BIT_PATTERN;
11056                         if (lic)
11057                                 count++;
11058                 }
11059         }
11060
11061         return count;
11062 }
11063
11064 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11065 {
11066         int port = BP_PORT(bp);
11067         int func = BP_ABS_FUNC(bp);
11068         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11069                                 drv_lic_key[port].max_fcoe_conn);
11070         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11071
11072         if (!CNIC_SUPPORT(bp)) {
11073                 bp->flags |= NO_FCOE_FLAG;
11074                 return;
11075         }
11076
11077         /* Get the number of maximum allowed FCoE connections */
11078         bp->cnic_eth_dev.max_fcoe_conn =
11079                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11080                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11081
11082         /* Calculate the number of maximum allowed FCoE tasks */
11083         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11084
11085         /* check if FCoE resources must be shared between different functions */
11086         if (num_fcoe_func)
11087                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11088
11089         /* Read the WWN: */
11090         if (!IS_MF(bp)) {
11091                 /* Port info */
11092                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11093                         SHMEM_RD(bp,
11094                                  dev_info.port_hw_config[port].
11095                                  fcoe_wwn_port_name_upper);
11096                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11097                         SHMEM_RD(bp,
11098                                  dev_info.port_hw_config[port].
11099                                  fcoe_wwn_port_name_lower);
11100
11101                 /* Node info */
11102                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11103                         SHMEM_RD(bp,
11104                                  dev_info.port_hw_config[port].
11105                                  fcoe_wwn_node_name_upper);
11106                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11107                         SHMEM_RD(bp,
11108                                  dev_info.port_hw_config[port].
11109                                  fcoe_wwn_node_name_lower);
11110         } else if (!IS_MF_SD(bp)) {
11111                 /*
11112                  * Read the WWN info only if the FCoE feature is enabled for
11113                  * this function.
11114                  */
11115                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11116                         bnx2x_get_ext_wwn_info(bp, func);
11117
11118         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
11119                 bnx2x_get_ext_wwn_info(bp, func);
11120         }
11121
11122         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11123
11124         /*
11125          * If maximum allowed number of connections is zero -
11126          * disable the feature.
11127          */
11128         if (!bp->cnic_eth_dev.max_fcoe_conn)
11129                 bp->flags |= NO_FCOE_FLAG;
11130 }
11131
11132 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11133 {
11134         /*
11135          * iSCSI may be dynamically disabled but reading
11136          * info here we will decrease memory usage by driver
11137          * if the feature is disabled for good
11138          */
11139         bnx2x_get_iscsi_info(bp);
11140         bnx2x_get_fcoe_info(bp);
11141 }
11142
11143 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11144 {
11145         u32 val, val2;
11146         int func = BP_ABS_FUNC(bp);
11147         int port = BP_PORT(bp);
11148         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11149         u8 *fip_mac = bp->fip_mac;
11150
11151         if (IS_MF(bp)) {
11152                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11153                  * FCoE MAC then the appropriate feature should be disabled.
11154                  * In non SD mode features configuration comes from struct
11155                  * func_ext_config.
11156                  */
11157                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11158                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11159                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11160                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11161                                                  iscsi_mac_addr_upper);
11162                                 val = MF_CFG_RD(bp, func_ext_config[func].
11163                                                 iscsi_mac_addr_lower);
11164                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11165                                 BNX2X_DEV_INFO
11166                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11167                         } else {
11168                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11169                         }
11170
11171                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11172                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11173                                                  fcoe_mac_addr_upper);
11174                                 val = MF_CFG_RD(bp, func_ext_config[func].
11175                                                 fcoe_mac_addr_lower);
11176                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11177                                 BNX2X_DEV_INFO
11178                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11179                         } else {
11180                                 bp->flags |= NO_FCOE_FLAG;
11181                         }
11182
11183                         bp->mf_ext_config = cfg;
11184
11185                 } else { /* SD MODE */
11186                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11187                                 /* use primary mac as iscsi mac */
11188                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11189
11190                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11191                                 BNX2X_DEV_INFO
11192                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11193                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11194                                 /* use primary mac as fip mac */
11195                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11196                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11197                                 BNX2X_DEV_INFO
11198                                         ("Read FIP MAC: %pM\n", fip_mac);
11199                         }
11200                 }
11201
11202                 /* If this is a storage-only interface, use SAN mac as
11203                  * primary MAC. Notice that for SD this is already the case,
11204                  * as the SAN mac was copied from the primary MAC.
11205                  */
11206                 if (IS_MF_FCOE_AFEX(bp))
11207                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11208         } else {
11209                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11210                                 iscsi_mac_upper);
11211                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11212                                iscsi_mac_lower);
11213                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11214
11215                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11216                                 fcoe_fip_mac_upper);
11217                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11218                                fcoe_fip_mac_lower);
11219                 bnx2x_set_mac_buf(fip_mac, val, val2);
11220         }
11221
11222         /* Disable iSCSI OOO if MAC configuration is invalid. */
11223         if (!is_valid_ether_addr(iscsi_mac)) {
11224                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11225                 memset(iscsi_mac, 0, ETH_ALEN);
11226         }
11227
11228         /* Disable FCoE if MAC configuration is invalid. */
11229         if (!is_valid_ether_addr(fip_mac)) {
11230                 bp->flags |= NO_FCOE_FLAG;
11231                 memset(bp->fip_mac, 0, ETH_ALEN);
11232         }
11233 }
11234
11235 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11236 {
11237         u32 val, val2;
11238         int func = BP_ABS_FUNC(bp);
11239         int port = BP_PORT(bp);
11240
11241         /* Zero primary MAC configuration */
11242         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11243
11244         if (BP_NOMCP(bp)) {
11245                 BNX2X_ERROR("warning: random MAC workaround active\n");
11246                 eth_hw_addr_random(bp->dev);
11247         } else if (IS_MF(bp)) {
11248                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11249                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11250                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11251                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11252                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11253
11254                 if (CNIC_SUPPORT(bp))
11255                         bnx2x_get_cnic_mac_hwinfo(bp);
11256         } else {
11257                 /* in SF read MACs from port configuration */
11258                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11259                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11260                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11261
11262                 if (CNIC_SUPPORT(bp))
11263                         bnx2x_get_cnic_mac_hwinfo(bp);
11264         }
11265
11266         if (!BP_NOMCP(bp)) {
11267                 /* Read physical port identifier from shmem */
11268                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11269                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11270                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11271                 bp->flags |= HAS_PHYS_PORT_ID;
11272         }
11273
11274         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11275
11276         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11277                 dev_err(&bp->pdev->dev,
11278                         "bad Ethernet MAC address configuration: %pM\n"
11279                         "change it manually before bringing up the appropriate network interface\n",
11280                         bp->dev->dev_addr);
11281 }
11282
11283 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11284 {
11285         int tmp;
11286         u32 cfg;
11287
11288         if (IS_VF(bp))
11289                 return 0;
11290
11291         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11292                 /* Take function: tmp = func */
11293                 tmp = BP_ABS_FUNC(bp);
11294                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11295                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11296         } else {
11297                 /* Take port: tmp = port */
11298                 tmp = BP_PORT(bp);
11299                 cfg = SHMEM_RD(bp,
11300                                dev_info.port_hw_config[tmp].generic_features);
11301                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11302         }
11303         return cfg;
11304 }
11305
11306 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11307 {
11308         int /*abs*/func = BP_ABS_FUNC(bp);
11309         int vn;
11310         u32 val = 0;
11311         int rc = 0;
11312
11313         bnx2x_get_common_hwinfo(bp);
11314
11315         /*
11316          * initialize IGU parameters
11317          */
11318         if (CHIP_IS_E1x(bp)) {
11319                 bp->common.int_block = INT_BLOCK_HC;
11320
11321                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11322                 bp->igu_base_sb = 0;
11323         } else {
11324                 bp->common.int_block = INT_BLOCK_IGU;
11325
11326                 /* do not allow device reset during IGU info processing */
11327                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11328
11329                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11330
11331                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11332                         int tout = 5000;
11333
11334                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11335
11336                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11337                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11338                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11339
11340                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11341                                 tout--;
11342                                 usleep_range(1000, 2000);
11343                         }
11344
11345                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11346                                 dev_err(&bp->pdev->dev,
11347                                         "FORCING Normal Mode failed!!!\n");
11348                                 bnx2x_release_hw_lock(bp,
11349                                                       HW_LOCK_RESOURCE_RESET);
11350                                 return -EPERM;
11351                         }
11352                 }
11353
11354                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11355                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11356                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11357                 } else
11358                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11359
11360                 rc = bnx2x_get_igu_cam_info(bp);
11361                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11362                 if (rc)
11363                         return rc;
11364         }
11365
11366         /*
11367          * set base FW non-default (fast path) status block id, this value is
11368          * used to initialize the fw_sb_id saved on the fp/queue structure to
11369          * determine the id used by the FW.
11370          */
11371         if (CHIP_IS_E1x(bp))
11372                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11373         else /*
11374               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11375               * the same queue are indicated on the same IGU SB). So we prefer
11376               * FW and IGU SBs to be the same value.
11377               */
11378                 bp->base_fw_ndsb = bp->igu_base_sb;
11379
11380         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11381                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11382                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11383
11384         /*
11385          * Initialize MF configuration
11386          */
11387
11388         bp->mf_ov = 0;
11389         bp->mf_mode = 0;
11390         vn = BP_VN(bp);
11391
11392         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11393                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11394                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11395                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11396
11397                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11398                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11399                 else
11400                         bp->common.mf_cfg_base = bp->common.shmem_base +
11401                                 offsetof(struct shmem_region, func_mb) +
11402                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11403                 /*
11404                  * get mf configuration:
11405                  * 1. Existence of MF configuration
11406                  * 2. MAC address must be legal (check only upper bytes)
11407                  *    for  Switch-Independent mode;
11408                  *    OVLAN must be legal for Switch-Dependent mode
11409                  * 3. SF_MODE configures specific MF mode
11410                  */
11411                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11412                         /* get mf configuration */
11413                         val = SHMEM_RD(bp,
11414                                        dev_info.shared_feature_config.config);
11415                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11416
11417                         switch (val) {
11418                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11419                                 val = MF_CFG_RD(bp, func_mf_config[func].
11420                                                 mac_upper);
11421                                 /* check for legal mac (upper bytes)*/
11422                                 if (val != 0xffff) {
11423                                         bp->mf_mode = MULTI_FUNCTION_SI;
11424                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11425                                                    func_mf_config[func].config);
11426                                 } else
11427                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11428                                 break;
11429                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11430                                 if ((!CHIP_IS_E1x(bp)) &&
11431                                     (MF_CFG_RD(bp, func_mf_config[func].
11432                                                mac_upper) != 0xffff) &&
11433                                     (SHMEM2_HAS(bp,
11434                                                 afex_driver_support))) {
11435                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11436                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11437                                                 func_mf_config[func].config);
11438                                 } else {
11439                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11440                                 }
11441                                 break;
11442                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11443                                 /* get OV configuration */
11444                                 val = MF_CFG_RD(bp,
11445                                         func_mf_config[FUNC_0].e1hov_tag);
11446                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11447
11448                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11449                                         bp->mf_mode = MULTI_FUNCTION_SD;
11450                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11451                                                 func_mf_config[func].config);
11452                                 } else
11453                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11454                                 break;
11455                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11456                                 bp->mf_config[vn] = 0;
11457                                 break;
11458                         default:
11459                                 /* Unknown configuration: reset mf_config */
11460                                 bp->mf_config[vn] = 0;
11461                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11462                         }
11463                 }
11464
11465                 BNX2X_DEV_INFO("%s function mode\n",
11466                                IS_MF(bp) ? "multi" : "single");
11467
11468                 switch (bp->mf_mode) {
11469                 case MULTI_FUNCTION_SD:
11470                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11471                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11472                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11473                                 bp->mf_ov = val;
11474                                 bp->path_has_ovlan = true;
11475
11476                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11477                                                func, bp->mf_ov, bp->mf_ov);
11478                         } else {
11479                                 dev_err(&bp->pdev->dev,
11480                                         "No valid MF OV for func %d, aborting\n",
11481                                         func);
11482                                 return -EPERM;
11483                         }
11484                         break;
11485                 case MULTI_FUNCTION_AFEX:
11486                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11487                         break;
11488                 case MULTI_FUNCTION_SI:
11489                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11490                                        func);
11491                         break;
11492                 default:
11493                         if (vn) {
11494                                 dev_err(&bp->pdev->dev,
11495                                         "VN %d is in a single function mode, aborting\n",
11496                                         vn);
11497                                 return -EPERM;
11498                         }
11499                         break;
11500                 }
11501
11502                 /* check if other port on the path needs ovlan:
11503                  * Since MF configuration is shared between ports
11504                  * Possible mixed modes are only
11505                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11506                  */
11507                 if (CHIP_MODE_IS_4_PORT(bp) &&
11508                     !bp->path_has_ovlan &&
11509                     !IS_MF(bp) &&
11510                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11511                         u8 other_port = !BP_PORT(bp);
11512                         u8 other_func = BP_PATH(bp) + 2*other_port;
11513                         val = MF_CFG_RD(bp,
11514                                         func_mf_config[other_func].e1hov_tag);
11515                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11516                                 bp->path_has_ovlan = true;
11517                 }
11518         }
11519
11520         /* adjust igu_sb_cnt to MF for E1H */
11521         if (CHIP_IS_E1H(bp) && IS_MF(bp))
11522                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11523
11524         /* port info */
11525         bnx2x_get_port_hwinfo(bp);
11526
11527         /* Get MAC addresses */
11528         bnx2x_get_mac_hwinfo(bp);
11529
11530         bnx2x_get_cnic_info(bp);
11531
11532         return rc;
11533 }
11534
11535 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11536 {
11537         int cnt, i, block_end, rodi;
11538         char vpd_start[BNX2X_VPD_LEN+1];
11539         char str_id_reg[VENDOR_ID_LEN+1];
11540         char str_id_cap[VENDOR_ID_LEN+1];
11541         char *vpd_data;
11542         char *vpd_extended_data = NULL;
11543         u8 len;
11544
11545         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11546         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11547
11548         if (cnt < BNX2X_VPD_LEN)
11549                 goto out_not_found;
11550
11551         /* VPD RO tag should be first tag after identifier string, hence
11552          * we should be able to find it in first BNX2X_VPD_LEN chars
11553          */
11554         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11555                              PCI_VPD_LRDT_RO_DATA);
11556         if (i < 0)
11557                 goto out_not_found;
11558
11559         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11560                     pci_vpd_lrdt_size(&vpd_start[i]);
11561
11562         i += PCI_VPD_LRDT_TAG_SIZE;
11563
11564         if (block_end > BNX2X_VPD_LEN) {
11565                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11566                 if (vpd_extended_data  == NULL)
11567                         goto out_not_found;
11568
11569                 /* read rest of vpd image into vpd_extended_data */
11570                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11571                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11572                                    block_end - BNX2X_VPD_LEN,
11573                                    vpd_extended_data + BNX2X_VPD_LEN);
11574                 if (cnt < (block_end - BNX2X_VPD_LEN))
11575                         goto out_not_found;
11576                 vpd_data = vpd_extended_data;
11577         } else
11578                 vpd_data = vpd_start;
11579
11580         /* now vpd_data holds full vpd content in both cases */
11581
11582         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11583                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11584         if (rodi < 0)
11585                 goto out_not_found;
11586
11587         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11588
11589         if (len != VENDOR_ID_LEN)
11590                 goto out_not_found;
11591
11592         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11593
11594         /* vendor specific info */
11595         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11596         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11597         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11598             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11599
11600                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11601                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11602                 if (rodi >= 0) {
11603                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11604
11605                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11606
11607                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11608                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11609                                 bp->fw_ver[len] = ' ';
11610                         }
11611                 }
11612                 kfree(vpd_extended_data);
11613                 return;
11614         }
11615 out_not_found:
11616         kfree(vpd_extended_data);
11617         return;
11618 }
11619
11620 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11621 {
11622         u32 flags = 0;
11623
11624         if (CHIP_REV_IS_FPGA(bp))
11625                 SET_FLAGS(flags, MODE_FPGA);
11626         else if (CHIP_REV_IS_EMUL(bp))
11627                 SET_FLAGS(flags, MODE_EMUL);
11628         else
11629                 SET_FLAGS(flags, MODE_ASIC);
11630
11631         if (CHIP_MODE_IS_4_PORT(bp))
11632                 SET_FLAGS(flags, MODE_PORT4);
11633         else
11634                 SET_FLAGS(flags, MODE_PORT2);
11635
11636         if (CHIP_IS_E2(bp))
11637                 SET_FLAGS(flags, MODE_E2);
11638         else if (CHIP_IS_E3(bp)) {
11639                 SET_FLAGS(flags, MODE_E3);
11640                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11641                         SET_FLAGS(flags, MODE_E3_A0);
11642                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11643                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11644         }
11645
11646         if (IS_MF(bp)) {
11647                 SET_FLAGS(flags, MODE_MF);
11648                 switch (bp->mf_mode) {
11649                 case MULTI_FUNCTION_SD:
11650                         SET_FLAGS(flags, MODE_MF_SD);
11651                         break;
11652                 case MULTI_FUNCTION_SI:
11653                         SET_FLAGS(flags, MODE_MF_SI);
11654                         break;
11655                 case MULTI_FUNCTION_AFEX:
11656                         SET_FLAGS(flags, MODE_MF_AFEX);
11657                         break;
11658                 }
11659         } else
11660                 SET_FLAGS(flags, MODE_SF);
11661
11662 #if defined(__LITTLE_ENDIAN)
11663         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11664 #else /*(__BIG_ENDIAN)*/
11665         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11666 #endif
11667         INIT_MODE_FLAGS(bp) = flags;
11668 }
11669
11670 static int bnx2x_init_bp(struct bnx2x *bp)
11671 {
11672         int func;
11673         int rc;
11674
11675         mutex_init(&bp->port.phy_mutex);
11676         mutex_init(&bp->fw_mb_mutex);
11677         spin_lock_init(&bp->stats_lock);
11678         sema_init(&bp->stats_sema, 1);
11679
11680         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11681         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11682         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11683         if (IS_PF(bp)) {
11684                 rc = bnx2x_get_hwinfo(bp);
11685                 if (rc)
11686                         return rc;
11687         } else {
11688                 eth_zero_addr(bp->dev->dev_addr);
11689         }
11690
11691         bnx2x_set_modes_bitmap(bp);
11692
11693         rc = bnx2x_alloc_mem_bp(bp);
11694         if (rc)
11695                 return rc;
11696
11697         bnx2x_read_fwinfo(bp);
11698
11699         func = BP_FUNC(bp);
11700
11701         /* need to reset chip if undi was active */
11702         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11703                 /* init fw_seq */
11704                 bp->fw_seq =
11705                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11706                                                         DRV_MSG_SEQ_NUMBER_MASK;
11707                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11708
11709                 rc = bnx2x_prev_unload(bp);
11710                 if (rc) {
11711                         bnx2x_free_mem_bp(bp);
11712                         return rc;
11713                 }
11714         }
11715
11716         if (CHIP_REV_IS_FPGA(bp))
11717                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11718
11719         if (BP_NOMCP(bp) && (func == 0))
11720                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11721
11722         bp->disable_tpa = disable_tpa;
11723         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11724
11725         /* Set TPA flags */
11726         if (bp->disable_tpa) {
11727                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11728                 bp->dev->features &= ~NETIF_F_LRO;
11729         } else {
11730                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11731                 bp->dev->features |= NETIF_F_LRO;
11732         }
11733
11734         if (CHIP_IS_E1(bp))
11735                 bp->dropless_fc = 0;
11736         else
11737                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11738
11739         bp->mrrs = mrrs;
11740
11741         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11742         if (IS_VF(bp))
11743                 bp->rx_ring_size = MAX_RX_AVAIL;
11744
11745         /* make sure that the numbers are in the right granularity */
11746         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11747         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11748
11749         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11750
11751         init_timer(&bp->timer);
11752         bp->timer.expires = jiffies + bp->current_interval;
11753         bp->timer.data = (unsigned long) bp;
11754         bp->timer.function = bnx2x_timer;
11755
11756         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11757             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11758             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11759             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11760                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11761                 bnx2x_dcbx_init_params(bp);
11762         } else {
11763                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11764         }
11765
11766         if (CHIP_IS_E1x(bp))
11767                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11768         else
11769                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11770
11771         /* multiple tx priority */
11772         if (IS_VF(bp))
11773                 bp->max_cos = 1;
11774         else if (CHIP_IS_E1x(bp))
11775                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11776         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11777                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11778         else if (CHIP_IS_E3B0(bp))
11779                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11780         else
11781                 BNX2X_ERR("unknown chip %x revision %x\n",
11782                           CHIP_NUM(bp), CHIP_REV(bp));
11783         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11784
11785         /* We need at least one default status block for slow-path events,
11786          * second status block for the L2 queue, and a third status block for
11787          * CNIC if supported.
11788          */
11789         if (IS_VF(bp))
11790                 bp->min_msix_vec_cnt = 1;
11791         else if (CNIC_SUPPORT(bp))
11792                 bp->min_msix_vec_cnt = 3;
11793         else /* PF w/o cnic */
11794                 bp->min_msix_vec_cnt = 2;
11795         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11796
11797         bp->dump_preset_idx = 1;
11798
11799         return rc;
11800 }
11801
11802 /****************************************************************************
11803 * General service functions
11804 ****************************************************************************/
11805
11806 /*
11807  * net_device service functions
11808  */
11809
11810 /* called with rtnl_lock */
11811 static int bnx2x_open(struct net_device *dev)
11812 {
11813         struct bnx2x *bp = netdev_priv(dev);
11814         int rc;
11815
11816         bp->stats_init = true;
11817
11818         netif_carrier_off(dev);
11819
11820         bnx2x_set_power_state(bp, PCI_D0);
11821
11822         /* If parity had happen during the unload, then attentions
11823          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11824          * want the first function loaded on the current engine to
11825          * complete the recovery.
11826          * Parity recovery is only relevant for PF driver.
11827          */
11828         if (IS_PF(bp)) {
11829                 int other_engine = BP_PATH(bp) ? 0 : 1;
11830                 bool other_load_status, load_status;
11831                 bool global = false;
11832
11833                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11834                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11835                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11836                     bnx2x_chk_parity_attn(bp, &global, true)) {
11837                         do {
11838                                 /* If there are attentions and they are in a
11839                                  * global blocks, set the GLOBAL_RESET bit
11840                                  * regardless whether it will be this function
11841                                  * that will complete the recovery or not.
11842                                  */
11843                                 if (global)
11844                                         bnx2x_set_reset_global(bp);
11845
11846                                 /* Only the first function on the current
11847                                  * engine should try to recover in open. In case
11848                                  * of attentions in global blocks only the first
11849                                  * in the chip should try to recover.
11850                                  */
11851                                 if ((!load_status &&
11852                                      (!global || !other_load_status)) &&
11853                                       bnx2x_trylock_leader_lock(bp) &&
11854                                       !bnx2x_leader_reset(bp)) {
11855                                         netdev_info(bp->dev,
11856                                                     "Recovered in open\n");
11857                                         break;
11858                                 }
11859
11860                                 /* recovery has failed... */
11861                                 bnx2x_set_power_state(bp, PCI_D3hot);
11862                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11863
11864                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11865                                           "If you still see this message after a few retries then power cycle is required.\n");
11866
11867                                 return -EAGAIN;
11868                         } while (0);
11869                 }
11870         }
11871
11872         bp->recovery_state = BNX2X_RECOVERY_DONE;
11873         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11874         if (rc)
11875                 return rc;
11876         return 0;
11877 }
11878
11879 /* called with rtnl_lock */
11880 static int bnx2x_close(struct net_device *dev)
11881 {
11882         struct bnx2x *bp = netdev_priv(dev);
11883
11884         /* Unload the driver, release IRQs */
11885         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11886
11887         return 0;
11888 }
11889
11890 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11891                                       struct bnx2x_mcast_ramrod_params *p)
11892 {
11893         int mc_count = netdev_mc_count(bp->dev);
11894         struct bnx2x_mcast_list_elem *mc_mac =
11895                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11896         struct netdev_hw_addr *ha;
11897
11898         if (!mc_mac)
11899                 return -ENOMEM;
11900
11901         INIT_LIST_HEAD(&p->mcast_list);
11902
11903         netdev_for_each_mc_addr(ha, bp->dev) {
11904                 mc_mac->mac = bnx2x_mc_addr(ha);
11905                 list_add_tail(&mc_mac->link, &p->mcast_list);
11906                 mc_mac++;
11907         }
11908
11909         p->mcast_list_len = mc_count;
11910
11911         return 0;
11912 }
11913
11914 static void bnx2x_free_mcast_macs_list(
11915         struct bnx2x_mcast_ramrod_params *p)
11916 {
11917         struct bnx2x_mcast_list_elem *mc_mac =
11918                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11919                                  link);
11920
11921         WARN_ON(!mc_mac);
11922         kfree(mc_mac);
11923 }
11924
11925 /**
11926  * bnx2x_set_uc_list - configure a new unicast MACs list.
11927  *
11928  * @bp: driver handle
11929  *
11930  * We will use zero (0) as a MAC type for these MACs.
11931  */
11932 static int bnx2x_set_uc_list(struct bnx2x *bp)
11933 {
11934         int rc;
11935         struct net_device *dev = bp->dev;
11936         struct netdev_hw_addr *ha;
11937         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11938         unsigned long ramrod_flags = 0;
11939
11940         /* First schedule a cleanup up of old configuration */
11941         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11942         if (rc < 0) {
11943                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11944                 return rc;
11945         }
11946
11947         netdev_for_each_uc_addr(ha, dev) {
11948                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11949                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11950                 if (rc == -EEXIST) {
11951                         DP(BNX2X_MSG_SP,
11952                            "Failed to schedule ADD operations: %d\n", rc);
11953                         /* do not treat adding same MAC as error */
11954                         rc = 0;
11955
11956                 } else if (rc < 0) {
11957
11958                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11959                                   rc);
11960                         return rc;
11961                 }
11962         }
11963
11964         /* Execute the pending commands */
11965         __set_bit(RAMROD_CONT, &ramrod_flags);
11966         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11967                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11968 }
11969
11970 static int bnx2x_set_mc_list(struct bnx2x *bp)
11971 {
11972         struct net_device *dev = bp->dev;
11973         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11974         int rc = 0;
11975
11976         rparam.mcast_obj = &bp->mcast_obj;
11977
11978         /* first, clear all configured multicast MACs */
11979         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11980         if (rc < 0) {
11981                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11982                 return rc;
11983         }
11984
11985         /* then, configure a new MACs list */
11986         if (netdev_mc_count(dev)) {
11987                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11988                 if (rc) {
11989                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11990                                   rc);
11991                         return rc;
11992                 }
11993
11994                 /* Now add the new MACs */
11995                 rc = bnx2x_config_mcast(bp, &rparam,
11996                                         BNX2X_MCAST_CMD_ADD);
11997                 if (rc < 0)
11998                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11999                                   rc);
12000
12001                 bnx2x_free_mcast_macs_list(&rparam);
12002         }
12003
12004         return rc;
12005 }
12006
12007 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12008 void bnx2x_set_rx_mode(struct net_device *dev)
12009 {
12010         struct bnx2x *bp = netdev_priv(dev);
12011
12012         if (bp->state != BNX2X_STATE_OPEN) {
12013                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12014                 return;
12015         } else {
12016                 /* Schedule an SP task to handle rest of change */
12017                 DP(NETIF_MSG_IFUP, "Scheduling an Rx mode change\n");
12018                 smp_mb__before_clear_bit();
12019                 set_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state);
12020                 smp_mb__after_clear_bit();
12021                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
12022         }
12023 }
12024
12025 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12026 {
12027         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12028
12029         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12030
12031         netif_addr_lock_bh(bp->dev);
12032
12033         if (bp->dev->flags & IFF_PROMISC) {
12034                 rx_mode = BNX2X_RX_MODE_PROMISC;
12035         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12036                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12037                     CHIP_IS_E1(bp))) {
12038                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12039         } else {
12040                 if (IS_PF(bp)) {
12041                         /* some multicasts */
12042                         if (bnx2x_set_mc_list(bp) < 0)
12043                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12044
12045                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12046                         netif_addr_unlock_bh(bp->dev);
12047                         if (bnx2x_set_uc_list(bp) < 0)
12048                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12049                         netif_addr_lock_bh(bp->dev);
12050                 } else {
12051                         /* configuring mcast to a vf involves sleeping (when we
12052                          * wait for the pf's response).
12053                          */
12054                         smp_mb__before_clear_bit();
12055                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
12056                                 &bp->sp_rtnl_state);
12057                         smp_mb__after_clear_bit();
12058                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
12059                 }
12060         }
12061
12062         bp->rx_mode = rx_mode;
12063         /* handle ISCSI SD mode */
12064         if (IS_MF_ISCSI_SD(bp))
12065                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12066
12067         /* Schedule the rx_mode command */
12068         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12069                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12070                 netif_addr_unlock_bh(bp->dev);
12071                 return;
12072         }
12073
12074         if (IS_PF(bp)) {
12075                 bnx2x_set_storm_rx_mode(bp);
12076                 netif_addr_unlock_bh(bp->dev);
12077         } else {
12078                 /* VF will need to request the PF to make this change, and so
12079                  * the VF needs to release the bottom-half lock prior to the
12080                  * request (as it will likely require sleep on the VF side)
12081                  */
12082                 netif_addr_unlock_bh(bp->dev);
12083                 bnx2x_vfpf_storm_rx_mode(bp);
12084         }
12085 }
12086
12087 /* called with rtnl_lock */
12088 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12089                            int devad, u16 addr)
12090 {
12091         struct bnx2x *bp = netdev_priv(netdev);
12092         u16 value;
12093         int rc;
12094
12095         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12096            prtad, devad, addr);
12097
12098         /* The HW expects different devad if CL22 is used */
12099         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12100
12101         bnx2x_acquire_phy_lock(bp);
12102         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12103         bnx2x_release_phy_lock(bp);
12104         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12105
12106         if (!rc)
12107                 rc = value;
12108         return rc;
12109 }
12110
12111 /* called with rtnl_lock */
12112 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12113                             u16 addr, u16 value)
12114 {
12115         struct bnx2x *bp = netdev_priv(netdev);
12116         int rc;
12117
12118         DP(NETIF_MSG_LINK,
12119            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12120            prtad, devad, addr, value);
12121
12122         /* The HW expects different devad if CL22 is used */
12123         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12124
12125         bnx2x_acquire_phy_lock(bp);
12126         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12127         bnx2x_release_phy_lock(bp);
12128         return rc;
12129 }
12130
12131 /* called with rtnl_lock */
12132 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12133 {
12134         struct bnx2x *bp = netdev_priv(dev);
12135         struct mii_ioctl_data *mdio = if_mii(ifr);
12136
12137         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12138            mdio->phy_id, mdio->reg_num, mdio->val_in);
12139
12140         if (!netif_running(dev))
12141                 return -EAGAIN;
12142
12143         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12144 }
12145
12146 #ifdef CONFIG_NET_POLL_CONTROLLER
12147 static void poll_bnx2x(struct net_device *dev)
12148 {
12149         struct bnx2x *bp = netdev_priv(dev);
12150         int i;
12151
12152         for_each_eth_queue(bp, i) {
12153                 struct bnx2x_fastpath *fp = &bp->fp[i];
12154                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12155         }
12156 }
12157 #endif
12158
12159 static int bnx2x_validate_addr(struct net_device *dev)
12160 {
12161         struct bnx2x *bp = netdev_priv(dev);
12162
12163         /* query the bulletin board for mac address configured by the PF */
12164         if (IS_VF(bp))
12165                 bnx2x_sample_bulletin(bp);
12166
12167         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12168                 BNX2X_ERR("Non-valid Ethernet address\n");
12169                 return -EADDRNOTAVAIL;
12170         }
12171         return 0;
12172 }
12173
12174 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12175                                   struct netdev_phys_port_id *ppid)
12176 {
12177         struct bnx2x *bp = netdev_priv(netdev);
12178
12179         if (!(bp->flags & HAS_PHYS_PORT_ID))
12180                 return -EOPNOTSUPP;
12181
12182         ppid->id_len = sizeof(bp->phys_port_id);
12183         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12184
12185         return 0;
12186 }
12187
12188 static const struct net_device_ops bnx2x_netdev_ops = {
12189         .ndo_open               = bnx2x_open,
12190         .ndo_stop               = bnx2x_close,
12191         .ndo_start_xmit         = bnx2x_start_xmit,
12192         .ndo_select_queue       = bnx2x_select_queue,
12193         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12194         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12195         .ndo_validate_addr      = bnx2x_validate_addr,
12196         .ndo_do_ioctl           = bnx2x_ioctl,
12197         .ndo_change_mtu         = bnx2x_change_mtu,
12198         .ndo_fix_features       = bnx2x_fix_features,
12199         .ndo_set_features       = bnx2x_set_features,
12200         .ndo_tx_timeout         = bnx2x_tx_timeout,
12201 #ifdef CONFIG_NET_POLL_CONTROLLER
12202         .ndo_poll_controller    = poll_bnx2x,
12203 #endif
12204         .ndo_setup_tc           = bnx2x_setup_tc,
12205 #ifdef CONFIG_BNX2X_SRIOV
12206         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12207         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12208         .ndo_get_vf_config      = bnx2x_get_vf_config,
12209 #endif
12210 #ifdef NETDEV_FCOE_WWNN
12211         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12212 #endif
12213
12214 #ifdef CONFIG_NET_RX_BUSY_POLL
12215         .ndo_busy_poll          = bnx2x_low_latency_recv,
12216 #endif
12217         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12218 };
12219
12220 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12221 {
12222         struct device *dev = &bp->pdev->dev;
12223
12224         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12225             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12226                 dev_err(dev, "System does not support DMA, aborting\n");
12227                 return -EIO;
12228         }
12229
12230         return 0;
12231 }
12232
12233 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12234 {
12235         if (bp->flags & AER_ENABLED) {
12236                 pci_disable_pcie_error_reporting(bp->pdev);
12237                 bp->flags &= ~AER_ENABLED;
12238         }
12239 }
12240
12241 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12242                           struct net_device *dev, unsigned long board_type)
12243 {
12244         int rc;
12245         u32 pci_cfg_dword;
12246         bool chip_is_e1x = (board_type == BCM57710 ||
12247                             board_type == BCM57711 ||
12248                             board_type == BCM57711E);
12249
12250         SET_NETDEV_DEV(dev, &pdev->dev);
12251
12252         bp->dev = dev;
12253         bp->pdev = pdev;
12254
12255         rc = pci_enable_device(pdev);
12256         if (rc) {
12257                 dev_err(&bp->pdev->dev,
12258                         "Cannot enable PCI device, aborting\n");
12259                 goto err_out;
12260         }
12261
12262         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12263                 dev_err(&bp->pdev->dev,
12264                         "Cannot find PCI device base address, aborting\n");
12265                 rc = -ENODEV;
12266                 goto err_out_disable;
12267         }
12268
12269         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12270                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12271                 rc = -ENODEV;
12272                 goto err_out_disable;
12273         }
12274
12275         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12276         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12277             PCICFG_REVESION_ID_ERROR_VAL) {
12278                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12279                 rc = -ENODEV;
12280                 goto err_out_disable;
12281         }
12282
12283         if (atomic_read(&pdev->enable_cnt) == 1) {
12284                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12285                 if (rc) {
12286                         dev_err(&bp->pdev->dev,
12287                                 "Cannot obtain PCI resources, aborting\n");
12288                         goto err_out_disable;
12289                 }
12290
12291                 pci_set_master(pdev);
12292                 pci_save_state(pdev);
12293         }
12294
12295         if (IS_PF(bp)) {
12296                 if (!pdev->pm_cap) {
12297                         dev_err(&bp->pdev->dev,
12298                                 "Cannot find power management capability, aborting\n");
12299                         rc = -EIO;
12300                         goto err_out_release;
12301                 }
12302         }
12303
12304         if (!pci_is_pcie(pdev)) {
12305                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12306                 rc = -EIO;
12307                 goto err_out_release;
12308         }
12309
12310         rc = bnx2x_set_coherency_mask(bp);
12311         if (rc)
12312                 goto err_out_release;
12313
12314         dev->mem_start = pci_resource_start(pdev, 0);
12315         dev->base_addr = dev->mem_start;
12316         dev->mem_end = pci_resource_end(pdev, 0);
12317
12318         dev->irq = pdev->irq;
12319
12320         bp->regview = pci_ioremap_bar(pdev, 0);
12321         if (!bp->regview) {
12322                 dev_err(&bp->pdev->dev,
12323                         "Cannot map register space, aborting\n");
12324                 rc = -ENOMEM;
12325                 goto err_out_release;
12326         }
12327
12328         /* In E1/E1H use pci device function given by kernel.
12329          * In E2/E3 read physical function from ME register since these chips
12330          * support Physical Device Assignment where kernel BDF maybe arbitrary
12331          * (depending on hypervisor).
12332          */
12333         if (chip_is_e1x) {
12334                 bp->pf_num = PCI_FUNC(pdev->devfn);
12335         } else {
12336                 /* chip is E2/3*/
12337                 pci_read_config_dword(bp->pdev,
12338                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12339                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12340                                   ME_REG_ABS_PF_NUM_SHIFT);
12341         }
12342         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12343
12344         /* clean indirect addresses */
12345         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12346                                PCICFG_VENDOR_ID_OFFSET);
12347
12348         /* AER (Advanced Error reporting) configuration */
12349         rc = pci_enable_pcie_error_reporting(pdev);
12350         if (!rc)
12351                 bp->flags |= AER_ENABLED;
12352         else
12353                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12354
12355         /*
12356          * Clean the following indirect addresses for all functions since it
12357          * is not used by the driver.
12358          */
12359         if (IS_PF(bp)) {
12360                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12361                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12362                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12363                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12364
12365                 if (chip_is_e1x) {
12366                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12367                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12368                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12369                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12370                 }
12371
12372                 /* Enable internal target-read (in case we are probed after PF
12373                  * FLR). Must be done prior to any BAR read access. Only for
12374                  * 57712 and up
12375                  */
12376                 if (!chip_is_e1x)
12377                         REG_WR(bp,
12378                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12379         }
12380
12381         dev->watchdog_timeo = TX_TIMEOUT;
12382
12383         dev->netdev_ops = &bnx2x_netdev_ops;
12384         bnx2x_set_ethtool_ops(bp, dev);
12385
12386         dev->priv_flags |= IFF_UNICAST_FLT;
12387
12388         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12389                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12390                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12391                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12392         if (!CHIP_IS_E1x(bp)) {
12393                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12394                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12395                 dev->hw_enc_features =
12396                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12397                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12398                         NETIF_F_GSO_IPIP |
12399                         NETIF_F_GSO_SIT |
12400                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12401         }
12402
12403         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12404                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12405
12406         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12407         dev->features |= NETIF_F_HIGHDMA;
12408
12409         /* Add Loopback capability to the device */
12410         dev->hw_features |= NETIF_F_LOOPBACK;
12411
12412 #ifdef BCM_DCBNL
12413         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12414 #endif
12415
12416         /* get_port_hwinfo() will set prtad and mmds properly */
12417         bp->mdio.prtad = MDIO_PRTAD_NONE;
12418         bp->mdio.mmds = 0;
12419         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12420         bp->mdio.dev = dev;
12421         bp->mdio.mdio_read = bnx2x_mdio_read;
12422         bp->mdio.mdio_write = bnx2x_mdio_write;
12423
12424         return 0;
12425
12426 err_out_release:
12427         if (atomic_read(&pdev->enable_cnt) == 1)
12428                 pci_release_regions(pdev);
12429
12430 err_out_disable:
12431         pci_disable_device(pdev);
12432
12433 err_out:
12434         return rc;
12435 }
12436
12437 static int bnx2x_check_firmware(struct bnx2x *bp)
12438 {
12439         const struct firmware *firmware = bp->firmware;
12440         struct bnx2x_fw_file_hdr *fw_hdr;
12441         struct bnx2x_fw_file_section *sections;
12442         u32 offset, len, num_ops;
12443         __be16 *ops_offsets;
12444         int i;
12445         const u8 *fw_ver;
12446
12447         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12448                 BNX2X_ERR("Wrong FW size\n");
12449                 return -EINVAL;
12450         }
12451
12452         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12453         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12454
12455         /* Make sure none of the offsets and sizes make us read beyond
12456          * the end of the firmware data */
12457         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12458                 offset = be32_to_cpu(sections[i].offset);
12459                 len = be32_to_cpu(sections[i].len);
12460                 if (offset + len > firmware->size) {
12461                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12462                         return -EINVAL;
12463                 }
12464         }
12465
12466         /* Likewise for the init_ops offsets */
12467         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12468         ops_offsets = (__force __be16 *)(firmware->data + offset);
12469         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12470
12471         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12472                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12473                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12474                         return -EINVAL;
12475                 }
12476         }
12477
12478         /* Check FW version */
12479         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12480         fw_ver = firmware->data + offset;
12481         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12482             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12483             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12484             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12485                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12486                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12487                        BCM_5710_FW_MAJOR_VERSION,
12488                        BCM_5710_FW_MINOR_VERSION,
12489                        BCM_5710_FW_REVISION_VERSION,
12490                        BCM_5710_FW_ENGINEERING_VERSION);
12491                 return -EINVAL;
12492         }
12493
12494         return 0;
12495 }
12496
12497 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12498 {
12499         const __be32 *source = (const __be32 *)_source;
12500         u32 *target = (u32 *)_target;
12501         u32 i;
12502
12503         for (i = 0; i < n/4; i++)
12504                 target[i] = be32_to_cpu(source[i]);
12505 }
12506
12507 /*
12508    Ops array is stored in the following format:
12509    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12510  */
12511 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12512 {
12513         const __be32 *source = (const __be32 *)_source;
12514         struct raw_op *target = (struct raw_op *)_target;
12515         u32 i, j, tmp;
12516
12517         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12518                 tmp = be32_to_cpu(source[j]);
12519                 target[i].op = (tmp >> 24) & 0xff;
12520                 target[i].offset = tmp & 0xffffff;
12521                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12522         }
12523 }
12524
12525 /* IRO array is stored in the following format:
12526  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12527  */
12528 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12529 {
12530         const __be32 *source = (const __be32 *)_source;
12531         struct iro *target = (struct iro *)_target;
12532         u32 i, j, tmp;
12533
12534         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12535                 target[i].base = be32_to_cpu(source[j]);
12536                 j++;
12537                 tmp = be32_to_cpu(source[j]);
12538                 target[i].m1 = (tmp >> 16) & 0xffff;
12539                 target[i].m2 = tmp & 0xffff;
12540                 j++;
12541                 tmp = be32_to_cpu(source[j]);
12542                 target[i].m3 = (tmp >> 16) & 0xffff;
12543                 target[i].size = tmp & 0xffff;
12544                 j++;
12545         }
12546 }
12547
12548 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12549 {
12550         const __be16 *source = (const __be16 *)_source;
12551         u16 *target = (u16 *)_target;
12552         u32 i;
12553
12554         for (i = 0; i < n/2; i++)
12555                 target[i] = be16_to_cpu(source[i]);
12556 }
12557
12558 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12559 do {                                                                    \
12560         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12561         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12562         if (!bp->arr)                                                   \
12563                 goto lbl;                                               \
12564         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12565              (u8 *)bp->arr, len);                                       \
12566 } while (0)
12567
12568 static int bnx2x_init_firmware(struct bnx2x *bp)
12569 {
12570         const char *fw_file_name;
12571         struct bnx2x_fw_file_hdr *fw_hdr;
12572         int rc;
12573
12574         if (bp->firmware)
12575                 return 0;
12576
12577         if (CHIP_IS_E1(bp))
12578                 fw_file_name = FW_FILE_NAME_E1;
12579         else if (CHIP_IS_E1H(bp))
12580                 fw_file_name = FW_FILE_NAME_E1H;
12581         else if (!CHIP_IS_E1x(bp))
12582                 fw_file_name = FW_FILE_NAME_E2;
12583         else {
12584                 BNX2X_ERR("Unsupported chip revision\n");
12585                 return -EINVAL;
12586         }
12587         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12588
12589         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12590         if (rc) {
12591                 BNX2X_ERR("Can't load firmware file %s\n",
12592                           fw_file_name);
12593                 goto request_firmware_exit;
12594         }
12595
12596         rc = bnx2x_check_firmware(bp);
12597         if (rc) {
12598                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12599                 goto request_firmware_exit;
12600         }
12601
12602         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12603
12604         /* Initialize the pointers to the init arrays */
12605         /* Blob */
12606         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12607
12608         /* Opcodes */
12609         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12610
12611         /* Offsets */
12612         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12613                             be16_to_cpu_n);
12614
12615         /* STORMs firmware */
12616         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12617                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12618         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12619                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12620         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12621                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12622         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12623                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12624         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12625                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12626         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12627                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12628         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12629                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12630         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12631                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12632         /* IRO */
12633         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12634
12635         return 0;
12636
12637 iro_alloc_err:
12638         kfree(bp->init_ops_offsets);
12639 init_offsets_alloc_err:
12640         kfree(bp->init_ops);
12641 init_ops_alloc_err:
12642         kfree(bp->init_data);
12643 request_firmware_exit:
12644         release_firmware(bp->firmware);
12645         bp->firmware = NULL;
12646
12647         return rc;
12648 }
12649
12650 static void bnx2x_release_firmware(struct bnx2x *bp)
12651 {
12652         kfree(bp->init_ops_offsets);
12653         kfree(bp->init_ops);
12654         kfree(bp->init_data);
12655         release_firmware(bp->firmware);
12656         bp->firmware = NULL;
12657 }
12658
12659 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12660         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12661         .init_hw_cmn      = bnx2x_init_hw_common,
12662         .init_hw_port     = bnx2x_init_hw_port,
12663         .init_hw_func     = bnx2x_init_hw_func,
12664
12665         .reset_hw_cmn     = bnx2x_reset_common,
12666         .reset_hw_port    = bnx2x_reset_port,
12667         .reset_hw_func    = bnx2x_reset_func,
12668
12669         .gunzip_init      = bnx2x_gunzip_init,
12670         .gunzip_end       = bnx2x_gunzip_end,
12671
12672         .init_fw          = bnx2x_init_firmware,
12673         .release_fw       = bnx2x_release_firmware,
12674 };
12675
12676 void bnx2x__init_func_obj(struct bnx2x *bp)
12677 {
12678         /* Prepare DMAE related driver resources */
12679         bnx2x_setup_dmae(bp);
12680
12681         bnx2x_init_func_obj(bp, &bp->func_obj,
12682                             bnx2x_sp(bp, func_rdata),
12683                             bnx2x_sp_mapping(bp, func_rdata),
12684                             bnx2x_sp(bp, func_afex_rdata),
12685                             bnx2x_sp_mapping(bp, func_afex_rdata),
12686                             &bnx2x_func_sp_drv);
12687 }
12688
12689 /* must be called after sriov-enable */
12690 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12691 {
12692         int cid_count = BNX2X_L2_MAX_CID(bp);
12693
12694         if (IS_SRIOV(bp))
12695                 cid_count += BNX2X_VF_CIDS;
12696
12697         if (CNIC_SUPPORT(bp))
12698                 cid_count += CNIC_CID_MAX;
12699
12700         return roundup(cid_count, QM_CID_ROUND);
12701 }
12702
12703 /**
12704  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12705  *
12706  * @dev:        pci device
12707  *
12708  */
12709 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
12710 {
12711         int index;
12712         u16 control = 0;
12713
12714         /*
12715          * If MSI-X is not supported - return number of SBs needed to support
12716          * one fast path queue: one FP queue + SB for CNIC
12717          */
12718         if (!pdev->msix_cap) {
12719                 dev_info(&pdev->dev, "no msix capability found\n");
12720                 return 1 + cnic_cnt;
12721         }
12722         dev_info(&pdev->dev, "msix capability found\n");
12723
12724         /*
12725          * The value in the PCI configuration space is the index of the last
12726          * entry, namely one less than the actual size of the table, which is
12727          * exactly what we want to return from this function: number of all SBs
12728          * without the default SB.
12729          * For VFs there is no default SB, then we return (index+1).
12730          */
12731         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
12732
12733         index = control & PCI_MSIX_FLAGS_QSIZE;
12734
12735         return index;
12736 }
12737
12738 static int set_max_cos_est(int chip_id)
12739 {
12740         switch (chip_id) {
12741         case BCM57710:
12742         case BCM57711:
12743         case BCM57711E:
12744                 return BNX2X_MULTI_TX_COS_E1X;
12745         case BCM57712:
12746         case BCM57712_MF:
12747                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12748         case BCM57800:
12749         case BCM57800_MF:
12750         case BCM57810:
12751         case BCM57810_MF:
12752         case BCM57840_4_10:
12753         case BCM57840_2_20:
12754         case BCM57840_O:
12755         case BCM57840_MFO:
12756         case BCM57840_MF:
12757         case BCM57811:
12758         case BCM57811_MF:
12759                 return BNX2X_MULTI_TX_COS_E3B0;
12760         case BCM57712_VF:
12761         case BCM57800_VF:
12762         case BCM57810_VF:
12763         case BCM57840_VF:
12764         case BCM57811_VF:
12765                 return 1;
12766         default:
12767                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12768                 return -ENODEV;
12769         }
12770 }
12771
12772 static int set_is_vf(int chip_id)
12773 {
12774         switch (chip_id) {
12775         case BCM57712_VF:
12776         case BCM57800_VF:
12777         case BCM57810_VF:
12778         case BCM57840_VF:
12779         case BCM57811_VF:
12780                 return true;
12781         default:
12782                 return false;
12783         }
12784 }
12785
12786 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12787
12788 static int bnx2x_init_one(struct pci_dev *pdev,
12789                                     const struct pci_device_id *ent)
12790 {
12791         struct net_device *dev = NULL;
12792         struct bnx2x *bp;
12793         enum pcie_link_width pcie_width;
12794         enum pci_bus_speed pcie_speed;
12795         int rc, max_non_def_sbs;
12796         int rx_count, tx_count, rss_count, doorbell_size;
12797         int max_cos_est;
12798         bool is_vf;
12799         int cnic_cnt;
12800
12801         /* An estimated maximum supported CoS number according to the chip
12802          * version.
12803          * We will try to roughly estimate the maximum number of CoSes this chip
12804          * may support in order to minimize the memory allocated for Tx
12805          * netdev_queue's. This number will be accurately calculated during the
12806          * initialization of bp->max_cos based on the chip versions AND chip
12807          * revision in the bnx2x_init_bp().
12808          */
12809         max_cos_est = set_max_cos_est(ent->driver_data);
12810         if (max_cos_est < 0)
12811                 return max_cos_est;
12812         is_vf = set_is_vf(ent->driver_data);
12813         cnic_cnt = is_vf ? 0 : 1;
12814
12815         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12816
12817         /* add another SB for VF as it has no default SB */
12818         max_non_def_sbs += is_vf ? 1 : 0;
12819
12820         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12821         rss_count = max_non_def_sbs - cnic_cnt;
12822
12823         if (rss_count < 1)
12824                 return -EINVAL;
12825
12826         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12827         rx_count = rss_count + cnic_cnt;
12828
12829         /* Maximum number of netdev Tx queues:
12830          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12831          */
12832         tx_count = rss_count * max_cos_est + cnic_cnt;
12833
12834         /* dev zeroed in init_etherdev */
12835         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12836         if (!dev)
12837                 return -ENOMEM;
12838
12839         bp = netdev_priv(dev);
12840
12841         bp->flags = 0;
12842         if (is_vf)
12843                 bp->flags |= IS_VF_FLAG;
12844
12845         bp->igu_sb_cnt = max_non_def_sbs;
12846         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12847         bp->msg_enable = debug;
12848         bp->cnic_support = cnic_cnt;
12849         bp->cnic_probe = bnx2x_cnic_probe;
12850
12851         pci_set_drvdata(pdev, dev);
12852
12853         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12854         if (rc < 0) {
12855                 free_netdev(dev);
12856                 return rc;
12857         }
12858
12859         BNX2X_DEV_INFO("This is a %s function\n",
12860                        IS_PF(bp) ? "physical" : "virtual");
12861         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12862         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12863         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12864                        tx_count, rx_count);
12865
12866         rc = bnx2x_init_bp(bp);
12867         if (rc)
12868                 goto init_one_exit;
12869
12870         /* Map doorbells here as we need the real value of bp->max_cos which
12871          * is initialized in bnx2x_init_bp() to determine the number of
12872          * l2 connections.
12873          */
12874         if (IS_VF(bp)) {
12875                 bp->doorbells = bnx2x_vf_doorbells(bp);
12876                 rc = bnx2x_vf_pci_alloc(bp);
12877                 if (rc)
12878                         goto init_one_exit;
12879         } else {
12880                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12881                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12882                         dev_err(&bp->pdev->dev,
12883                                 "Cannot map doorbells, bar size too small, aborting\n");
12884                         rc = -ENOMEM;
12885                         goto init_one_exit;
12886                 }
12887                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12888                                                 doorbell_size);
12889         }
12890         if (!bp->doorbells) {
12891                 dev_err(&bp->pdev->dev,
12892                         "Cannot map doorbell space, aborting\n");
12893                 rc = -ENOMEM;
12894                 goto init_one_exit;
12895         }
12896
12897         if (IS_VF(bp)) {
12898                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12899                 if (rc)
12900                         goto init_one_exit;
12901         }
12902
12903         /* Enable SRIOV if capability found in configuration space */
12904         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12905         if (rc)
12906                 goto init_one_exit;
12907
12908         /* calc qm_cid_count */
12909         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12910         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12911
12912         /* disable FCOE L2 queue for E1x*/
12913         if (CHIP_IS_E1x(bp))
12914                 bp->flags |= NO_FCOE_FLAG;
12915
12916         /* Set bp->num_queues for MSI-X mode*/
12917         bnx2x_set_num_queues(bp);
12918
12919         /* Configure interrupt mode: try to enable MSI-X/MSI if
12920          * needed.
12921          */
12922         rc = bnx2x_set_int_mode(bp);
12923         if (rc) {
12924                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12925                 goto init_one_exit;
12926         }
12927         BNX2X_DEV_INFO("set interrupts successfully\n");
12928
12929         /* register the net device */
12930         rc = register_netdev(dev);
12931         if (rc) {
12932                 dev_err(&pdev->dev, "Cannot register net device\n");
12933                 goto init_one_exit;
12934         }
12935         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12936
12937         if (!NO_FCOE(bp)) {
12938                 /* Add storage MAC address */
12939                 rtnl_lock();
12940                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12941                 rtnl_unlock();
12942         }
12943         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
12944             pcie_speed == PCI_SPEED_UNKNOWN ||
12945             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
12946                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
12947         else
12948                 BNX2X_DEV_INFO(
12949                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12950                        board_info[ent->driver_data].name,
12951                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12952                        pcie_width,
12953                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
12954                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
12955                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
12956                        "Unknown",
12957                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
12958
12959         return 0;
12960
12961 init_one_exit:
12962         bnx2x_disable_pcie_error_reporting(bp);
12963
12964         if (bp->regview)
12965                 iounmap(bp->regview);
12966
12967         if (IS_PF(bp) && bp->doorbells)
12968                 iounmap(bp->doorbells);
12969
12970         free_netdev(dev);
12971
12972         if (atomic_read(&pdev->enable_cnt) == 1)
12973                 pci_release_regions(pdev);
12974
12975         pci_disable_device(pdev);
12976
12977         return rc;
12978 }
12979
12980 static void __bnx2x_remove(struct pci_dev *pdev,
12981                            struct net_device *dev,
12982                            struct bnx2x *bp,
12983                            bool remove_netdev)
12984 {
12985         /* Delete storage MAC address */
12986         if (!NO_FCOE(bp)) {
12987                 rtnl_lock();
12988                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12989                 rtnl_unlock();
12990         }
12991
12992 #ifdef BCM_DCBNL
12993         /* Delete app tlvs from dcbnl */
12994         bnx2x_dcbnl_update_applist(bp, true);
12995 #endif
12996
12997         if (IS_PF(bp) &&
12998             !BP_NOMCP(bp) &&
12999             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13000                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13001
13002         /* Close the interface - either directly or implicitly */
13003         if (remove_netdev) {
13004                 unregister_netdev(dev);
13005         } else {
13006                 rtnl_lock();
13007                 dev_close(dev);
13008                 rtnl_unlock();
13009         }
13010
13011         bnx2x_iov_remove_one(bp);
13012
13013         /* Power on: we can't let PCI layer write to us while we are in D3 */
13014         if (IS_PF(bp))
13015                 bnx2x_set_power_state(bp, PCI_D0);
13016
13017         /* Disable MSI/MSI-X */
13018         bnx2x_disable_msi(bp);
13019
13020         /* Power off */
13021         if (IS_PF(bp))
13022                 bnx2x_set_power_state(bp, PCI_D3hot);
13023
13024         /* Make sure RESET task is not scheduled before continuing */
13025         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13026
13027         /* send message via vfpf channel to release the resources of this vf */
13028         if (IS_VF(bp))
13029                 bnx2x_vfpf_release(bp);
13030
13031         /* Assumes no further PCIe PM changes will occur */
13032         if (system_state == SYSTEM_POWER_OFF) {
13033                 pci_wake_from_d3(pdev, bp->wol);
13034                 pci_set_power_state(pdev, PCI_D3hot);
13035         }
13036
13037         bnx2x_disable_pcie_error_reporting(bp);
13038
13039         if (bp->regview)
13040                 iounmap(bp->regview);
13041
13042         /* for vf doorbells are part of the regview and were unmapped along with
13043          * it. FW is only loaded by PF.
13044          */
13045         if (IS_PF(bp)) {
13046                 if (bp->doorbells)
13047                         iounmap(bp->doorbells);
13048
13049                 bnx2x_release_firmware(bp);
13050         }
13051         bnx2x_free_mem_bp(bp);
13052
13053         if (remove_netdev)
13054                 free_netdev(dev);
13055
13056         if (atomic_read(&pdev->enable_cnt) == 1)
13057                 pci_release_regions(pdev);
13058
13059         pci_disable_device(pdev);
13060 }
13061
13062 static void bnx2x_remove_one(struct pci_dev *pdev)
13063 {
13064         struct net_device *dev = pci_get_drvdata(pdev);
13065         struct bnx2x *bp;
13066
13067         if (!dev) {
13068                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13069                 return;
13070         }
13071         bp = netdev_priv(dev);
13072
13073         __bnx2x_remove(pdev, dev, bp, true);
13074 }
13075
13076 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13077 {
13078         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13079
13080         bp->rx_mode = BNX2X_RX_MODE_NONE;
13081
13082         if (CNIC_LOADED(bp))
13083                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13084
13085         /* Stop Tx */
13086         bnx2x_tx_disable(bp);
13087         /* Delete all NAPI objects */
13088         bnx2x_del_all_napi(bp);
13089         if (CNIC_LOADED(bp))
13090                 bnx2x_del_all_napi_cnic(bp);
13091         netdev_reset_tc(bp->dev);
13092
13093         del_timer_sync(&bp->timer);
13094         cancel_delayed_work(&bp->sp_task);
13095         cancel_delayed_work(&bp->period_task);
13096
13097         spin_lock_bh(&bp->stats_lock);
13098         bp->stats_state = STATS_STATE_DISABLED;
13099         spin_unlock_bh(&bp->stats_lock);
13100
13101         bnx2x_save_statistics(bp);
13102
13103         netif_carrier_off(bp->dev);
13104
13105         return 0;
13106 }
13107
13108 /**
13109  * bnx2x_io_error_detected - called when PCI error is detected
13110  * @pdev: Pointer to PCI device
13111  * @state: The current pci connection state
13112  *
13113  * This function is called after a PCI bus error affecting
13114  * this device has been detected.
13115  */
13116 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13117                                                 pci_channel_state_t state)
13118 {
13119         struct net_device *dev = pci_get_drvdata(pdev);
13120         struct bnx2x *bp = netdev_priv(dev);
13121
13122         rtnl_lock();
13123
13124         BNX2X_ERR("IO error detected\n");
13125
13126         netif_device_detach(dev);
13127
13128         if (state == pci_channel_io_perm_failure) {
13129                 rtnl_unlock();
13130                 return PCI_ERS_RESULT_DISCONNECT;
13131         }
13132
13133         if (netif_running(dev))
13134                 bnx2x_eeh_nic_unload(bp);
13135
13136         bnx2x_prev_path_mark_eeh(bp);
13137
13138         pci_disable_device(pdev);
13139
13140         rtnl_unlock();
13141
13142         /* Request a slot reset */
13143         return PCI_ERS_RESULT_NEED_RESET;
13144 }
13145
13146 /**
13147  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13148  * @pdev: Pointer to PCI device
13149  *
13150  * Restart the card from scratch, as if from a cold-boot.
13151  */
13152 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13153 {
13154         struct net_device *dev = pci_get_drvdata(pdev);
13155         struct bnx2x *bp = netdev_priv(dev);
13156         int i;
13157
13158         rtnl_lock();
13159         BNX2X_ERR("IO slot reset initializing...\n");
13160         if (pci_enable_device(pdev)) {
13161                 dev_err(&pdev->dev,
13162                         "Cannot re-enable PCI device after reset\n");
13163                 rtnl_unlock();
13164                 return PCI_ERS_RESULT_DISCONNECT;
13165         }
13166
13167         pci_set_master(pdev);
13168         pci_restore_state(pdev);
13169         pci_save_state(pdev);
13170
13171         if (netif_running(dev))
13172                 bnx2x_set_power_state(bp, PCI_D0);
13173
13174         if (netif_running(dev)) {
13175                 BNX2X_ERR("IO slot reset --> driver unload\n");
13176
13177                 /* MCP should have been reset; Need to wait for validity */
13178                 bnx2x_init_shmem(bp);
13179
13180                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13181                         u32 v;
13182
13183                         v = SHMEM2_RD(bp,
13184                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13185                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13186                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13187                 }
13188                 bnx2x_drain_tx_queues(bp);
13189                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13190                 bnx2x_netif_stop(bp, 1);
13191                 bnx2x_free_irq(bp);
13192
13193                 /* Report UNLOAD_DONE to MCP */
13194                 bnx2x_send_unload_done(bp, true);
13195
13196                 bp->sp_state = 0;
13197                 bp->port.pmf = 0;
13198
13199                 bnx2x_prev_unload(bp);
13200
13201                 /* We should have reseted the engine, so It's fair to
13202                  * assume the FW will no longer write to the bnx2x driver.
13203                  */
13204                 bnx2x_squeeze_objects(bp);
13205                 bnx2x_free_skbs(bp);
13206                 for_each_rx_queue(bp, i)
13207                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13208                 bnx2x_free_fp_mem(bp);
13209                 bnx2x_free_mem(bp);
13210
13211                 bp->state = BNX2X_STATE_CLOSED;
13212         }
13213
13214         rtnl_unlock();
13215
13216         /* If AER, perform cleanup of the PCIe registers */
13217         if (bp->flags & AER_ENABLED) {
13218                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13219                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13220                 else
13221                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13222         }
13223
13224         return PCI_ERS_RESULT_RECOVERED;
13225 }
13226
13227 /**
13228  * bnx2x_io_resume - called when traffic can start flowing again
13229  * @pdev: Pointer to PCI device
13230  *
13231  * This callback is called when the error recovery driver tells us that
13232  * its OK to resume normal operation.
13233  */
13234 static void bnx2x_io_resume(struct pci_dev *pdev)
13235 {
13236         struct net_device *dev = pci_get_drvdata(pdev);
13237         struct bnx2x *bp = netdev_priv(dev);
13238
13239         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13240                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13241                 return;
13242         }
13243
13244         rtnl_lock();
13245
13246         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13247                                                         DRV_MSG_SEQ_NUMBER_MASK;
13248
13249         if (netif_running(dev))
13250                 bnx2x_nic_load(bp, LOAD_NORMAL);
13251
13252         netif_device_attach(dev);
13253
13254         rtnl_unlock();
13255 }
13256
13257 static const struct pci_error_handlers bnx2x_err_handler = {
13258         .error_detected = bnx2x_io_error_detected,
13259         .slot_reset     = bnx2x_io_slot_reset,
13260         .resume         = bnx2x_io_resume,
13261 };
13262
13263 static void bnx2x_shutdown(struct pci_dev *pdev)
13264 {
13265         struct net_device *dev = pci_get_drvdata(pdev);
13266         struct bnx2x *bp;
13267
13268         if (!dev)
13269                 return;
13270
13271         bp = netdev_priv(dev);
13272         if (!bp)
13273                 return;
13274
13275         rtnl_lock();
13276         netif_device_detach(dev);
13277         rtnl_unlock();
13278
13279         /* Don't remove the netdevice, as there are scenarios which will cause
13280          * the kernel to hang, e.g., when trying to remove bnx2i while the
13281          * rootfs is mounted from SAN.
13282          */
13283         __bnx2x_remove(pdev, dev, bp, false);
13284 }
13285
13286 static struct pci_driver bnx2x_pci_driver = {
13287         .name        = DRV_MODULE_NAME,
13288         .id_table    = bnx2x_pci_tbl,
13289         .probe       = bnx2x_init_one,
13290         .remove      = bnx2x_remove_one,
13291         .suspend     = bnx2x_suspend,
13292         .resume      = bnx2x_resume,
13293         .err_handler = &bnx2x_err_handler,
13294 #ifdef CONFIG_BNX2X_SRIOV
13295         .sriov_configure = bnx2x_sriov_configure,
13296 #endif
13297         .shutdown    = bnx2x_shutdown,
13298 };
13299
13300 static int __init bnx2x_init(void)
13301 {
13302         int ret;
13303
13304         pr_info("%s", version);
13305
13306         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13307         if (bnx2x_wq == NULL) {
13308                 pr_err("Cannot create workqueue\n");
13309                 return -ENOMEM;
13310         }
13311
13312         ret = pci_register_driver(&bnx2x_pci_driver);
13313         if (ret) {
13314                 pr_err("Cannot register driver\n");
13315                 destroy_workqueue(bnx2x_wq);
13316         }
13317         return ret;
13318 }
13319
13320 static void __exit bnx2x_cleanup(void)
13321 {
13322         struct list_head *pos, *q;
13323
13324         pci_unregister_driver(&bnx2x_pci_driver);
13325
13326         destroy_workqueue(bnx2x_wq);
13327
13328         /* Free globally allocated resources */
13329         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13330                 struct bnx2x_prev_path_list *tmp =
13331                         list_entry(pos, struct bnx2x_prev_path_list, list);
13332                 list_del(pos);
13333                 kfree(tmp);
13334         }
13335 }
13336
13337 void bnx2x_notify_link_changed(struct bnx2x *bp)
13338 {
13339         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13340 }
13341
13342 module_init(bnx2x_init);
13343 module_exit(bnx2x_cleanup);
13344
13345 /**
13346  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13347  *
13348  * @bp:         driver handle
13349  * @set:        set or clear the CAM entry
13350  *
13351  * This function will wait until the ramrod completion returns.
13352  * Return 0 if success, -ENODEV if ramrod doesn't return.
13353  */
13354 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13355 {
13356         unsigned long ramrod_flags = 0;
13357
13358         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13359         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13360                                  &bp->iscsi_l2_mac_obj, true,
13361                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13362 }
13363
13364 /* count denotes the number of new completions we have seen */
13365 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13366 {
13367         struct eth_spe *spe;
13368         int cxt_index, cxt_offset;
13369
13370 #ifdef BNX2X_STOP_ON_ERROR
13371         if (unlikely(bp->panic))
13372                 return;
13373 #endif
13374
13375         spin_lock_bh(&bp->spq_lock);
13376         BUG_ON(bp->cnic_spq_pending < count);
13377         bp->cnic_spq_pending -= count;
13378
13379         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13380                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13381                                 & SPE_HDR_CONN_TYPE) >>
13382                                 SPE_HDR_CONN_TYPE_SHIFT;
13383                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13384                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13385
13386                 /* Set validation for iSCSI L2 client before sending SETUP
13387                  *  ramrod
13388                  */
13389                 if (type == ETH_CONNECTION_TYPE) {
13390                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13391                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13392                                         ILT_PAGE_CIDS;
13393                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13394                                         (cxt_index * ILT_PAGE_CIDS);
13395                                 bnx2x_set_ctx_validation(bp,
13396                                         &bp->context[cxt_index].
13397                                                          vcxt[cxt_offset].eth,
13398                                         BNX2X_ISCSI_ETH_CID(bp));
13399                         }
13400                 }
13401
13402                 /*
13403                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13404                  * and in the air. We also check that number of outstanding
13405                  * COMMON ramrods is not more than the EQ and SPQ can
13406                  * accommodate.
13407                  */
13408                 if (type == ETH_CONNECTION_TYPE) {
13409                         if (!atomic_read(&bp->cq_spq_left))
13410                                 break;
13411                         else
13412                                 atomic_dec(&bp->cq_spq_left);
13413                 } else if (type == NONE_CONNECTION_TYPE) {
13414                         if (!atomic_read(&bp->eq_spq_left))
13415                                 break;
13416                         else
13417                                 atomic_dec(&bp->eq_spq_left);
13418                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13419                            (type == FCOE_CONNECTION_TYPE)) {
13420                         if (bp->cnic_spq_pending >=
13421                             bp->cnic_eth_dev.max_kwqe_pending)
13422                                 break;
13423                         else
13424                                 bp->cnic_spq_pending++;
13425                 } else {
13426                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13427                         bnx2x_panic();
13428                         break;
13429                 }
13430
13431                 spe = bnx2x_sp_get_next(bp);
13432                 *spe = *bp->cnic_kwq_cons;
13433
13434                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13435                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13436
13437                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13438                         bp->cnic_kwq_cons = bp->cnic_kwq;
13439                 else
13440                         bp->cnic_kwq_cons++;
13441         }
13442         bnx2x_sp_prod_update(bp);
13443         spin_unlock_bh(&bp->spq_lock);
13444 }
13445
13446 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13447                                struct kwqe_16 *kwqes[], u32 count)
13448 {
13449         struct bnx2x *bp = netdev_priv(dev);
13450         int i;
13451
13452 #ifdef BNX2X_STOP_ON_ERROR
13453         if (unlikely(bp->panic)) {
13454                 BNX2X_ERR("Can't post to SP queue while panic\n");
13455                 return -EIO;
13456         }
13457 #endif
13458
13459         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13460             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13461                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13462                 return -EAGAIN;
13463         }
13464
13465         spin_lock_bh(&bp->spq_lock);
13466
13467         for (i = 0; i < count; i++) {
13468                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13469
13470                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13471                         break;
13472
13473                 *bp->cnic_kwq_prod = *spe;
13474
13475                 bp->cnic_kwq_pending++;
13476
13477                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13478                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13479                    spe->data.update_data_addr.hi,
13480                    spe->data.update_data_addr.lo,
13481                    bp->cnic_kwq_pending);
13482
13483                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13484                         bp->cnic_kwq_prod = bp->cnic_kwq;
13485                 else
13486                         bp->cnic_kwq_prod++;
13487         }
13488
13489         spin_unlock_bh(&bp->spq_lock);
13490
13491         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13492                 bnx2x_cnic_sp_post(bp, 0);
13493
13494         return i;
13495 }
13496
13497 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13498 {
13499         struct cnic_ops *c_ops;
13500         int rc = 0;
13501
13502         mutex_lock(&bp->cnic_mutex);
13503         c_ops = rcu_dereference_protected(bp->cnic_ops,
13504                                           lockdep_is_held(&bp->cnic_mutex));
13505         if (c_ops)
13506                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13507         mutex_unlock(&bp->cnic_mutex);
13508
13509         return rc;
13510 }
13511
13512 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13513 {
13514         struct cnic_ops *c_ops;
13515         int rc = 0;
13516
13517         rcu_read_lock();
13518         c_ops = rcu_dereference(bp->cnic_ops);
13519         if (c_ops)
13520                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13521         rcu_read_unlock();
13522
13523         return rc;
13524 }
13525
13526 /*
13527  * for commands that have no data
13528  */
13529 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13530 {
13531         struct cnic_ctl_info ctl = {0};
13532
13533         ctl.cmd = cmd;
13534
13535         return bnx2x_cnic_ctl_send(bp, &ctl);
13536 }
13537
13538 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13539 {
13540         struct cnic_ctl_info ctl = {0};
13541
13542         /* first we tell CNIC and only then we count this as a completion */
13543         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13544         ctl.data.comp.cid = cid;
13545         ctl.data.comp.error = err;
13546
13547         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13548         bnx2x_cnic_sp_post(bp, 0);
13549 }
13550
13551 /* Called with netif_addr_lock_bh() taken.
13552  * Sets an rx_mode config for an iSCSI ETH client.
13553  * Doesn't block.
13554  * Completion should be checked outside.
13555  */
13556 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13557 {
13558         unsigned long accept_flags = 0, ramrod_flags = 0;
13559         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13560         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13561
13562         if (start) {
13563                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13564                  * because it's the only way for UIO Queue to accept
13565                  * multicasts (in non-promiscuous mode only one Queue per
13566                  * function will receive multicast packets (leading in our
13567                  * case).
13568                  */
13569                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13570                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13571                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13572                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13573
13574                 /* Clear STOP_PENDING bit if START is requested */
13575                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13576
13577                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13578         } else
13579                 /* Clear START_PENDING bit if STOP is requested */
13580                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13581
13582         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13583                 set_bit(sched_state, &bp->sp_state);
13584         else {
13585                 __set_bit(RAMROD_RX, &ramrod_flags);
13586                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13587                                     ramrod_flags);
13588         }
13589 }
13590
13591 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13592 {
13593         struct bnx2x *bp = netdev_priv(dev);
13594         int rc = 0;
13595
13596         switch (ctl->cmd) {
13597         case DRV_CTL_CTXTBL_WR_CMD: {
13598                 u32 index = ctl->data.io.offset;
13599                 dma_addr_t addr = ctl->data.io.dma_addr;
13600
13601                 bnx2x_ilt_wr(bp, index, addr);
13602                 break;
13603         }
13604
13605         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13606                 int count = ctl->data.credit.credit_count;
13607
13608                 bnx2x_cnic_sp_post(bp, count);
13609                 break;
13610         }
13611
13612         /* rtnl_lock is held.  */
13613         case DRV_CTL_START_L2_CMD: {
13614                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13615                 unsigned long sp_bits = 0;
13616
13617                 /* Configure the iSCSI classification object */
13618                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13619                                    cp->iscsi_l2_client_id,
13620                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13621                                    bnx2x_sp(bp, mac_rdata),
13622                                    bnx2x_sp_mapping(bp, mac_rdata),
13623                                    BNX2X_FILTER_MAC_PENDING,
13624                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13625                                    &bp->macs_pool);
13626
13627                 /* Set iSCSI MAC address */
13628                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13629                 if (rc)
13630                         break;
13631
13632                 mmiowb();
13633                 barrier();
13634
13635                 /* Start accepting on iSCSI L2 ring */
13636
13637                 netif_addr_lock_bh(dev);
13638                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13639                 netif_addr_unlock_bh(dev);
13640
13641                 /* bits to wait on */
13642                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13643                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13644
13645                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13646                         BNX2X_ERR("rx_mode completion timed out!\n");
13647
13648                 break;
13649         }
13650
13651         /* rtnl_lock is held.  */
13652         case DRV_CTL_STOP_L2_CMD: {
13653                 unsigned long sp_bits = 0;
13654
13655                 /* Stop accepting on iSCSI L2 ring */
13656                 netif_addr_lock_bh(dev);
13657                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13658                 netif_addr_unlock_bh(dev);
13659
13660                 /* bits to wait on */
13661                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13662                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13663
13664                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13665                         BNX2X_ERR("rx_mode completion timed out!\n");
13666
13667                 mmiowb();
13668                 barrier();
13669
13670                 /* Unset iSCSI L2 MAC */
13671                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13672                                         BNX2X_ISCSI_ETH_MAC, true);
13673                 break;
13674         }
13675         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13676                 int count = ctl->data.credit.credit_count;
13677
13678                 smp_mb__before_atomic_inc();
13679                 atomic_add(count, &bp->cq_spq_left);
13680                 smp_mb__after_atomic_inc();
13681                 break;
13682         }
13683         case DRV_CTL_ULP_REGISTER_CMD: {
13684                 int ulp_type = ctl->data.register_data.ulp_type;
13685
13686                 if (CHIP_IS_E3(bp)) {
13687                         int idx = BP_FW_MB_IDX(bp);
13688                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13689                         int path = BP_PATH(bp);
13690                         int port = BP_PORT(bp);
13691                         int i;
13692                         u32 scratch_offset;
13693                         u32 *host_addr;
13694
13695                         /* first write capability to shmem2 */
13696                         if (ulp_type == CNIC_ULP_ISCSI)
13697                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13698                         else if (ulp_type == CNIC_ULP_FCOE)
13699                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13700                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13701
13702                         if ((ulp_type != CNIC_ULP_FCOE) ||
13703                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13704                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13705                                 break;
13706
13707                         /* if reached here - should write fcoe capabilities */
13708                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13709                         if (!scratch_offset)
13710                                 break;
13711                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13712                                                    fcoe_features[path][port]);
13713                         host_addr = (u32 *) &(ctl->data.register_data.
13714                                               fcoe_features);
13715                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13716                              i += 4)
13717                                 REG_WR(bp, scratch_offset + i,
13718                                        *(host_addr + i/4));
13719                 }
13720                 break;
13721         }
13722
13723         case DRV_CTL_ULP_UNREGISTER_CMD: {
13724                 int ulp_type = ctl->data.ulp_type;
13725
13726                 if (CHIP_IS_E3(bp)) {
13727                         int idx = BP_FW_MB_IDX(bp);
13728                         u32 cap;
13729
13730                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13731                         if (ulp_type == CNIC_ULP_ISCSI)
13732                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13733                         else if (ulp_type == CNIC_ULP_FCOE)
13734                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13735                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13736                 }
13737                 break;
13738         }
13739
13740         default:
13741                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13742                 rc = -EINVAL;
13743         }
13744
13745         return rc;
13746 }
13747
13748 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13749 {
13750         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13751
13752         if (bp->flags & USING_MSIX_FLAG) {
13753                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13754                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13755                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13756         } else {
13757                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13758                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13759         }
13760         if (!CHIP_IS_E1x(bp))
13761                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13762         else
13763                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13764
13765         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13766         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13767         cp->irq_arr[1].status_blk = bp->def_status_blk;
13768         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13769         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13770
13771         cp->num_irq = 2;
13772 }
13773
13774 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13775 {
13776         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13777
13778         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13779                              bnx2x_cid_ilt_lines(bp);
13780         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13781         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13782         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13783
13784         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
13785            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
13786            cp->iscsi_l2_cid);
13787
13788         if (NO_ISCSI_OOO(bp))
13789                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13790 }
13791
13792 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13793                                void *data)
13794 {
13795         struct bnx2x *bp = netdev_priv(dev);
13796         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13797         int rc;
13798
13799         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13800
13801         if (ops == NULL) {
13802                 BNX2X_ERR("NULL ops received\n");
13803                 return -EINVAL;
13804         }
13805
13806         if (!CNIC_SUPPORT(bp)) {
13807                 BNX2X_ERR("Can't register CNIC when not supported\n");
13808                 return -EOPNOTSUPP;
13809         }
13810
13811         if (!CNIC_LOADED(bp)) {
13812                 rc = bnx2x_load_cnic(bp);
13813                 if (rc) {
13814                         BNX2X_ERR("CNIC-related load failed\n");
13815                         return rc;
13816                 }
13817         }
13818
13819         bp->cnic_enabled = true;
13820
13821         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13822         if (!bp->cnic_kwq)
13823                 return -ENOMEM;
13824
13825         bp->cnic_kwq_cons = bp->cnic_kwq;
13826         bp->cnic_kwq_prod = bp->cnic_kwq;
13827         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13828
13829         bp->cnic_spq_pending = 0;
13830         bp->cnic_kwq_pending = 0;
13831
13832         bp->cnic_data = data;
13833
13834         cp->num_irq = 0;
13835         cp->drv_state |= CNIC_DRV_STATE_REGD;
13836         cp->iro_arr = bp->iro_arr;
13837
13838         bnx2x_setup_cnic_irq_info(bp);
13839
13840         rcu_assign_pointer(bp->cnic_ops, ops);
13841
13842         return 0;
13843 }
13844
13845 static int bnx2x_unregister_cnic(struct net_device *dev)
13846 {
13847         struct bnx2x *bp = netdev_priv(dev);
13848         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13849
13850         mutex_lock(&bp->cnic_mutex);
13851         cp->drv_state = 0;
13852         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13853         mutex_unlock(&bp->cnic_mutex);
13854         synchronize_rcu();
13855         bp->cnic_enabled = false;
13856         kfree(bp->cnic_kwq);
13857         bp->cnic_kwq = NULL;
13858
13859         return 0;
13860 }
13861
13862 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13863 {
13864         struct bnx2x *bp = netdev_priv(dev);
13865         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13866
13867         /* If both iSCSI and FCoE are disabled - return NULL in
13868          * order to indicate CNIC that it should not try to work
13869          * with this device.
13870          */
13871         if (NO_ISCSI(bp) && NO_FCOE(bp))
13872                 return NULL;
13873
13874         cp->drv_owner = THIS_MODULE;
13875         cp->chip_id = CHIP_ID(bp);
13876         cp->pdev = bp->pdev;
13877         cp->io_base = bp->regview;
13878         cp->io_base2 = bp->doorbells;
13879         cp->max_kwqe_pending = 8;
13880         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13881         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13882                              bnx2x_cid_ilt_lines(bp);
13883         cp->ctx_tbl_len = CNIC_ILT_LINES;
13884         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13885         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13886         cp->drv_ctl = bnx2x_drv_ctl;
13887         cp->drv_register_cnic = bnx2x_register_cnic;
13888         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13889         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13890         cp->iscsi_l2_client_id =
13891                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13892         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13893
13894         if (NO_ISCSI_OOO(bp))
13895                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13896
13897         if (NO_ISCSI(bp))
13898                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13899
13900         if (NO_FCOE(bp))
13901                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13902
13903         BNX2X_DEV_INFO(
13904                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13905            cp->ctx_blk_size,
13906            cp->ctx_tbl_offset,
13907            cp->ctx_tbl_len,
13908            cp->starting_cid);
13909         return cp;
13910 }
13911
13912 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13913 {
13914         struct bnx2x *bp = fp->bp;
13915         u32 offset = BAR_USTRORM_INTMEM;
13916
13917         if (IS_VF(bp))
13918                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13919         else if (!CHIP_IS_E1x(bp))
13920                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13921         else
13922                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13923
13924         return offset;
13925 }
13926
13927 /* called only on E1H or E2.
13928  * When pretending to be PF, the pretend value is the function number 0...7
13929  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13930  * combination
13931  */
13932 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13933 {
13934         u32 pretend_reg;
13935
13936         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13937                 return -1;
13938
13939         /* get my own pretend register */
13940         pretend_reg = bnx2x_get_pretend_reg(bp);
13941         REG_WR(bp, pretend_reg, pretend_func_val);
13942         REG_RD(bp, pretend_reg);
13943         return 0;
13944 }