Pileus Git - ~andy/linux/blob - drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
  31                                              struct link_params *params,
  32                                              u8 dev_addr, u16 addr, u8 byte_cnt,
  33                                              u8 *o_buf, u8);
  34 /********************************************************/
  35 #define ETH_HLEN                        14
  36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  37 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  38 #define ETH_MIN_PACKET_SIZE             60
  39 #define ETH_MAX_PACKET_SIZE             1500
  40 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  41 #define MDIO_ACCESS_TIMEOUT             1000
  42 #define WC_LANE_MAX                     4
  43 #define I2C_SWITCH_WIDTH                2
  44 #define I2C_BSC0                        0
  45 #define I2C_BSC1                        1
  46 #define I2C_WA_RETRY_CNT                3
  47 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  48 #define MCPR_IMC_COMMAND_READ_OP        1
  49 #define MCPR_IMC_COMMAND_WRITE_OP       2
  50
  51 /* LED Blink rate that will achieve ~15.9Hz */
  52 #define LED_BLINK_RATE_VAL_E3           354
  53 #define LED_BLINK_RATE_VAL_E1X_E2       480
  54 /***********************************************************/
  55 /*                      Shortcut definitions               */
  56 /***********************************************************/
  57
  58 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  59
  60 #define NIG_STATUS_EMAC0_MI_INT \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  62 #define NIG_STATUS_XGXS0_LINK10G \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  64 #define NIG_STATUS_XGXS0_LINK_STATUS \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  67                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  68 #define NIG_STATUS_SERDES0_LINK_STATUS \
  69                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  70 #define NIG_MASK_MI_INT \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  72 #define NIG_MASK_XGXS0_LINK10G \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  74 #define NIG_MASK_XGXS0_LINK_STATUS \
  75                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  76 #define NIG_MASK_SERDES0_LINK_STATUS \
  77                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  78
  79 #define MDIO_AN_CL73_OR_37_COMPLETE \
  80                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  81                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  82
  83 #define XGXS_RESET_BITS \
  84         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  85          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  89
  90 #define SERDES_RESET_BITS \
  91         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  92          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  93          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  94          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  95
  96 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  97 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  98 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  99 #define AUTONEG_PARALLEL \
 100                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
 101 #define AUTONEG_SGMII_FIBER_AUTODET \
 102                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
 103 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 104
 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 108                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 109 #define GP_STATUS_SPEED_MASK \
 110                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 111 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 112 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 113 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 114 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 115 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 116 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 117 #define GP_STATUS_10G_HIG \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 119 #define GP_STATUS_10G_CX4 \
 120                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 122 #define GP_STATUS_10G_KX4 \
 123                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 125 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 127 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 129 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 130 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 131 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 132 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 133 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 134 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 135 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 136 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 137 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 138 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 139 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 140 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 141 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 142 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 143 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 144
 145 #define LINK_UPDATE_MASK \
 146                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 147                          LINK_STATUS_LINK_UP | \
 148                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 149                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 150                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 151                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 152                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 153                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 154                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 155
 156 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 157         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 158         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 159         #define SFP_EEPROM_CON_TYPE_VAL_RJ45    0x22
 160
 161
 162 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 163         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 164         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 165         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 166
 167 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 168         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 169         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 170
 171 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 172         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 173 #define SFP_EEPROM_OPTIONS_SIZE                 2
 174
 175 #define EDC_MODE_LINEAR                         0x0022
 176 #define EDC_MODE_LIMITING                               0x0044
 177 #define EDC_MODE_PASSIVE_DAC                    0x0055
 178
 179 /* ETS defines*/
 180 #define DCBX_INVALID_COS                                        (0xFF)
 181
 182 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 183 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 184 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 185 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 186 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 187
 188 #define MAX_PACKET_SIZE                                 (9700)
 189 #define MAX_KR_LINK_RETRY                               4
 190
 191 /**********************************************************/
 192 /*                     INTERFACE                          */
 193 /**********************************************************/
 194
 195 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 196         bnx2x_cl45_write(_bp, _phy, \
 197                 (_phy)->def_md_devad, \
 198                 (_bank + (_addr & 0xf)), \
 199                 _val)
 200
 201 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 202         bnx2x_cl45_read(_bp, _phy, \
 203                 (_phy)->def_md_devad, \
 204                 (_bank + (_addr & 0xf)), \
 205                 _val)
 206
 207 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 208 {
 209         u32 val = REG_RD(bp, reg);
 210
 211         val |= bits;
 212         REG_WR(bp, reg, val);
 213         return val;
 214 }
 215
 216 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 217 {
 218         u32 val = REG_RD(bp, reg);
 219
 220         val &= ~bits;
 221         REG_WR(bp, reg, val);
 222         return val;
 223 }
 224
 225 /*
 226  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 227  *                   or link flap can be avoided.
 228  *
 229  * @params:     link parameters
 230  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 231  *         condition code.
 232  */
 233 static int bnx2x_check_lfa(struct link_params *params)
 234 {
 235         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 236         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 237         u32 saved_val, req_val, eee_status;
 238         struct bnx2x *bp = params->bp;
 239
 240         additional_config =
 241                 REG_RD(bp, params->lfa_base +
 242                            offsetof(struct shmem_lfa, additional_config));
 243
 244         /* NOTE: must be first condition checked -
 245         * to verify DCC bit is cleared in any case!
 246         */
 247         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 248                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 249                 REG_WR(bp, params->lfa_base +
 250                            offsetof(struct shmem_lfa, additional_config),
 251                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 252                 return LFA_DCC_LFA_DISABLED;
 253         }
 254
 255         /* Verify that link is up */
 256         link_status = REG_RD(bp, params->shmem_base +
 257                              offsetof(struct shmem_region,
 258                                       port_mb[params->port].link_status));
 259         if (!(link_status & LINK_STATUS_LINK_UP))
 260                 return LFA_LINK_DOWN;
 261
 262         /* if loaded after BOOT from SAN, don't flap the link in any case and
 263          * rely on link set by preboot driver
 264          */
 265         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 266                 return 0;
 267
 268         /* Verify that loopback mode is not set */
 269         if (params->loopback_mode)
 270                 return LFA_LOOPBACK_ENABLED;
 271
 272         /* Verify that MFW supports LFA */
 273         if (!params->lfa_base)
 274                 return LFA_MFW_IS_TOO_OLD;
 275
 276         if (params->num_phys == 3) {
 277                 cfg_size = 2;
 278                 lfa_mask = 0xffffffff;
 279         } else {
 280                 cfg_size = 1;
 281                 lfa_mask = 0xffff;
 282         }
 283
 284         /* Compare Duplex */
 285         saved_val = REG_RD(bp, params->lfa_base +
 286                            offsetof(struct shmem_lfa, req_duplex));
 287         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 288         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 289                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 290                                (saved_val & lfa_mask), (req_val & lfa_mask));
 291                 return LFA_DUPLEX_MISMATCH;
 292         }
 293         /* Compare Flow Control */
 294         saved_val = REG_RD(bp, params->lfa_base +
 295                            offsetof(struct shmem_lfa, req_flow_ctrl));
 296         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 297         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 298                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 299                                (saved_val & lfa_mask), (req_val & lfa_mask));
 300                 return LFA_FLOW_CTRL_MISMATCH;
 301         }
 302         /* Compare Link Speed */
 303         saved_val = REG_RD(bp, params->lfa_base +
 304                            offsetof(struct shmem_lfa, req_line_speed));
 305         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 306         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 307                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 308                                (saved_val & lfa_mask), (req_val & lfa_mask));
 309                 return LFA_LINK_SPEED_MISMATCH;
 310         }
 311
 312         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 313                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 314                                             offsetof(struct shmem_lfa,
 315                                                      speed_cap_mask[cfg_idx]));
 316
 317                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 318                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 319                                        cur_speed_cap_mask,
 320                                        params->speed_cap_mask[cfg_idx]);
 321                         return LFA_SPEED_CAP_MISMATCH;
 322                 }
 323         }
 324
 325         cur_req_fc_auto_adv =
 326                 REG_RD(bp, params->lfa_base +
 327                        offsetof(struct shmem_lfa, additional_config)) &
 328                 REQ_FC_AUTO_ADV_MASK;
 329
 330         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 331                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 332                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 333                 return LFA_FLOW_CTRL_MISMATCH;
 334         }
 335
 336         eee_status = REG_RD(bp, params->shmem2_base +
 337                             offsetof(struct shmem2_region,
 338                                      eee_status[params->port]));
 339
 340         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 341              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 342             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 343              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 344                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 345                                eee_status);
 346                 return LFA_EEE_MISMATCH;
 347         }
 348
 349         /* LFA conditions are met */
 350         return 0;
 351 }
 352 /******************************************************************/
 353 /*                      EPIO/GPIO section                         */
 354 /******************************************************************/
 355 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 356 {
 357         u32 epio_mask, gp_oenable;
 358         *en = 0;
 359         /* Sanity check */
 360         if (epio_pin > 31) {
 361                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 362                 return;
 363         }
 364
 365         epio_mask = 1 << epio_pin;
 366         /* Set this EPIO to output */
 367         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 368         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 369
 370         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 371 }
 372 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 373 {
 374         u32 epio_mask, gp_output, gp_oenable;
 375
 376         /* Sanity check */
 377         if (epio_pin > 31) {
 378                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 379                 return;
 380         }
 381         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 382         epio_mask = 1 << epio_pin;
 383         /* Set this EPIO to output */
 384         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 385         if (en)
 386                 gp_output |= epio_mask;
 387         else
 388                 gp_output &= ~epio_mask;
 389
 390         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 391
 392         /* Set the value for this EPIO */
 393         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 394         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 395 }
 396
 397 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 398 {
 399         if (pin_cfg == PIN_CFG_NA)
 400                 return;
 401         if (pin_cfg >= PIN_CFG_EPIO0) {
 402                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 403         } else {
 404                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 405                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 406                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 407         }
 408 }
 409
 410 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 411 {
 412         if (pin_cfg == PIN_CFG_NA)
 413                 return -EINVAL;
 414         if (pin_cfg >= PIN_CFG_EPIO0) {
 415                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 416         } else {
 417                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 418                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 419                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 420         }
 421         return 0;
 422
 423 }
 424 /******************************************************************/
 425 /*                              ETS section                       */
 426 /******************************************************************/
 427 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 428 {
 429         /* ETS disabled configuration*/
 430         struct bnx2x *bp = params->bp;
 431
 432         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 433
 434         /* mapping between entry  priority to client number (0,1,2 -debug and
 435          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 436          * 3bits client num.
 437          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 438          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 439          */
 440
 441         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 442         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 443          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 444          * COS0 entry, 4 - COS1 entry.
 445          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 446          * bit4   bit3    bit2   bit1     bit0
 447          * MCP and debug are strict
 448          */
 449
 450         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 451         /* defines which entries (clients) are subjected to WFQ arbitration */
 452         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 453         /* For strict priority entries defines the number of consecutive
 454          * slots for the highest priority.
 455          */
 456         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 457         /* mapping between the CREDIT_WEIGHT registers and actual client
 458          * numbers
 459          */
 460         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 461         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 462         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 463
 464         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 465         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 466         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 467         /* ETS mode disable */
 468         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 469         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 470          * weight for COS0/COS1.
 471          */
 472         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 473         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 474         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 475         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 476         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 477         /* Defines the number of consecutive slots for the strict priority */
 478         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 479 }
 480 /******************************************************************************
 481 * Description:
 482 *       Getting min_w_val will be set according to line speed .
 483 *.
 484 ******************************************************************************/
 485 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 486 {
 487         u32 min_w_val = 0;
 488         /* Calculate min_w_val.*/
 489         if (vars->link_up) {
 490                 if (vars->line_speed == SPEED_20000)
 491                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 492                 else
 493                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 494         } else
 495                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 496         /* If the link isn't up (static configuration for example ) The
 497          * link will be according to 20GBPS.
 498          */
 499         return min_w_val;
 500 }
 501 /******************************************************************************
 502 * Description:
 503 *       Getting credit upper bound form min_w_val.
 504 *.
 505 ******************************************************************************/
 506 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 507 {
 508         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 509                                                 MAX_PACKET_SIZE);
 510         return credit_upper_bound;
 511 }
 512 /******************************************************************************
 513 * Description:
 514 *       Set credit upper bound for NIG.
 515 *.
 516 ******************************************************************************/
 517 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 518         const struct link_params *params,
 519         const u32 min_w_val)
 520 {
 521         struct bnx2x *bp = params->bp;
 522         const u8 port = params->port;
 523         const u32 credit_upper_bound =
 524             bnx2x_ets_get_credit_upper_bound(min_w_val);
 525
 526         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 527                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 528         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 529                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 530         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 531                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 532         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 533                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 534         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 535                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 536         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 537                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 538
 539         if (!port) {
 540                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 541                         credit_upper_bound);
 542                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 543                         credit_upper_bound);
 544                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 545                         credit_upper_bound);
 546         }
 547 }
 548 /******************************************************************************
 549 * Description:
 550 *       Will return the NIG ETS registers to init values.Except
 551 *       credit_upper_bound.
 552 *       That isn't used in this configuration (No WFQ is enabled) and will be
 553 *       configured acording to spec
 554 *.
 555 ******************************************************************************/
 556 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 557                                         const struct link_vars *vars)
 558 {
 559         struct bnx2x *bp = params->bp;
 560         const u8 port = params->port;
 561         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 562         /* Mapping between entry  priority to client number (0,1,2 -debug and
 563          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 564          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 565          * reset value or init tool
 566          */
 567         if (port) {
 568                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 569                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 570         } else {
 571                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 572                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 573         }
 574         /* For strict priority entries defines the number of consecutive
 575          * slots for the highest priority.
 576          */
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 578                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 579         /* Mapping between the CREDIT_WEIGHT registers and actual client
 580          * numbers
 581          */
 582         if (port) {
 583                 /*Port 1 has 6 COS*/
 584                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 585                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 586         } else {
 587                 /*Port 0 has 9 COS*/
 588                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 589                        0x43210876);
 590                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 591         }
 592
 593         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 594          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 595          * COS0 entry, 4 - COS1 entry.
 596          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 597          * bit4   bit3    bit2   bit1     bit0
 598          * MCP and debug are strict
 599          */
 600         if (port)
 601                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 602         else
 603                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 604         /* defines which entries (clients) are subjected to WFQ arbitration */
 605         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 606                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 607
 608         /* Please notice the register address are note continuous and a
 609          * for here is note appropriate.In 2 port mode port0 only COS0-5
 610          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 611          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 612          * are never used for WFQ
 613          */
 614         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 615                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 616         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 617                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 618         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 619                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 620         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 621                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 622         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 623                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 624         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 625                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 626         if (!port) {
 627                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 628                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 629                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 630         }
 631
 632         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 633 }
 634 /******************************************************************************
 635 * Description:
 636 *       Set credit upper bound for PBF.
 637 *.
 638 ******************************************************************************/
 639 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 640         const struct link_params *params,
 641         const u32 min_w_val)
 642 {
 643         struct bnx2x *bp = params->bp;
 644         const u32 credit_upper_bound =
 645             bnx2x_ets_get_credit_upper_bound(min_w_val);
 646         const u8 port = params->port;
 647         u32 base_upper_bound = 0;
 648         u8 max_cos = 0;
 649         u8 i = 0;
 650         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 651          * port mode port1 has COS0-2 that can be used for WFQ.
 652          */
 653         if (!port) {
 654                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 655                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 656         } else {
 657                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 658                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 659         }
 660
 661         for (i = 0; i < max_cos; i++)
 662                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 663 }
 664
 665 /******************************************************************************
 666 * Description:
 667 *       Will return the PBF ETS registers to init values.Except
 668 *       credit_upper_bound.
 669 *       That isn't used in this configuration (No WFQ is enabled) and will be
 670 *       configured acording to spec
 671 *.
 672 ******************************************************************************/
 673 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 674 {
 675         struct bnx2x *bp = params->bp;
 676         const u8 port = params->port;
 677         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 678         u8 i = 0;
 679         u32 base_weight = 0;
 680         u8 max_cos = 0;
 681
 682         /* Mapping between entry  priority to client number 0 - COS0
 683          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 684          * TODO_ETS - Should be done by reset value or init tool
 685          */
 686         if (port)
 687                 /*  0x688 (|011|0 10|00 1|000) */
 688                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 689         else
 690                 /*  (10 1|100 |011|0 10|00 1|000) */
 691                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 692
 693         /* TODO_ETS - Should be done by reset value or init tool */
 694         if (port)
 695                 /* 0x688 (|011|0 10|00 1|000)*/
 696                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 697         else
 698         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 699         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 700
 701         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 702                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 703
 704
 705         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 706                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 707
 708         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 709                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 710         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 711          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 712          */
 713         if (!port) {
 714                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 715                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 716         } else {
 717                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 718                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 719         }
 720
 721         for (i = 0; i < max_cos; i++)
 722                 REG_WR(bp, base_weight + (0x4 * i), 0);
 723
 724         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 725 }
 726 /******************************************************************************
 727 * Description:
 728 *       E3B0 disable will return basicly the values to init values.
 729 *.
 730 ******************************************************************************/
 731 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 732                                    const struct link_vars *vars)
 733 {
 734         struct bnx2x *bp = params->bp;
 735
 736         if (!CHIP_IS_E3B0(bp)) {
 737                 DP(NETIF_MSG_LINK,
 738                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 739                 return -EINVAL;
 740         }
 741
 742         bnx2x_ets_e3b0_nig_disabled(params, vars);
 743
 744         bnx2x_ets_e3b0_pbf_disabled(params);
 745
 746         return 0;
 747 }
 748
 749 /******************************************************************************
 750 * Description:
 751 *       Disable will return basicly the values to init values.
 752 *
 753 ******************************************************************************/
 754 int bnx2x_ets_disabled(struct link_params *params,
 755                       struct link_vars *vars)
 756 {
 757         struct bnx2x *bp = params->bp;
 758         int bnx2x_status = 0;
 759
 760         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 761                 bnx2x_ets_e2e3a0_disabled(params);
 762         else if (CHIP_IS_E3B0(bp))
 763                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 764         else {
 765                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 766                 return -EINVAL;
 767         }
 768
 769         return bnx2x_status;
 770 }
 771
 772 /******************************************************************************
 773 * Description
 774 *       Set the COS mappimg to SP and BW until this point all the COS are not
 775 *       set as SP or BW.
 776 ******************************************************************************/
 777 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 778                                   const struct bnx2x_ets_params *ets_params,
 779                                   const u8 cos_sp_bitmap,
 780                                   const u8 cos_bw_bitmap)
 781 {
 782         struct bnx2x *bp = params->bp;
 783         const u8 port = params->port;
 784         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 785         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 786         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 787         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 788
 789         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 790                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 791
 792         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 793                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 794
 795         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 796                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 797                nig_cli_subject2wfq_bitmap);
 798
 799         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 800                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 801                pbf_cli_subject2wfq_bitmap);
 802
 803         return 0;
 804 }
 805
 806 /******************************************************************************
 807 * Description:
 808 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 809 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 810 ******************************************************************************/
 811 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 812                                      const u8 cos_entry,
 813                                      const u32 min_w_val_nig,
 814                                      const u32 min_w_val_pbf,
 815                                      const u16 total_bw,
 816                                      const u8 bw,
 817                                      const u8 port)
 818 {
 819         u32 nig_reg_adress_crd_weight = 0;
 820         u32 pbf_reg_adress_crd_weight = 0;
 821         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 822         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 823         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 824
 825         switch (cos_entry) {
 826         case 0:
 827             nig_reg_adress_crd_weight =
 828                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 829                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 830              pbf_reg_adress_crd_weight = (port) ?
 831                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 832              break;
 833         case 1:
 834              nig_reg_adress_crd_weight = (port) ?
 835                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 836                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 837              pbf_reg_adress_crd_weight = (port) ?
 838                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 839              break;
 840         case 2:
 841              nig_reg_adress_crd_weight = (port) ?
 842                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 843                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 844
 845                  pbf_reg_adress_crd_weight = (port) ?
 846                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 847              break;
 848         case 3:
 849             if (port)
 850                         return -EINVAL;
 851              nig_reg_adress_crd_weight =
 852                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 853              pbf_reg_adress_crd_weight =
 854                  PBF_REG_COS3_WEIGHT_P0;
 855              break;
 856         case 4:
 857             if (port)
 858                 return -EINVAL;
 859              nig_reg_adress_crd_weight =
 860                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 861              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 862              break;
 863         case 5:
 864             if (port)
 865                 return -EINVAL;
 866              nig_reg_adress_crd_weight =
 867                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 868              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 869              break;
 870         }
 871
 872         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 873
 874         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 875
 876         return 0;
 877 }
 878 /******************************************************************************
 879 * Description:
 880 *       Calculate the total BW.A value of 0 isn't legal.
 881 *
 882 ******************************************************************************/
 883 static int bnx2x_ets_e3b0_get_total_bw(
 884         const struct link_params *params,
 885         struct bnx2x_ets_params *ets_params,
 886         u16 *total_bw)
 887 {
 888         struct bnx2x *bp = params->bp;
 889         u8 cos_idx = 0;
 890         u8 is_bw_cos_exist = 0;
 891
 892         *total_bw = 0 ;
 893         /* Calculate total BW requested */
 894         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 895                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 896                         is_bw_cos_exist = 1;
 897                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 898                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 899                                                    "was set to 0\n");
 900                                 /* This is to prevent a state when ramrods
 901                                  * can't be sent
 902                                  */
 903                                 ets_params->cos[cos_idx].params.bw_params.bw
 904                                          = 1;
 905                         }
 906                         *total_bw +=
 907                                 ets_params->cos[cos_idx].params.bw_params.bw;
 908                 }
 909         }
 910
 911         /* Check total BW is valid */
 912         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 913                 if (*total_bw == 0) {
 914                         DP(NETIF_MSG_LINK,
 915                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 916                         return -EINVAL;
 917                 }
 918                 DP(NETIF_MSG_LINK,
 919                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 920                 /* We can handle a case whre the BW isn't 100 this can happen
 921                  * if the TC are joined.
 922                  */
 923         }
 924         return 0;
 925 }
 926
 927 /******************************************************************************
 928 * Description:
 929 *       Invalidate all the sp_pri_to_cos.
 930 *
 931 ******************************************************************************/
 932 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 933 {
 934         u8 pri = 0;
 935         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 936                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 937 }
 938 /******************************************************************************
 939 * Description:
 940 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 941 *       according to sp_pri_to_cos.
 942 *
 943 ******************************************************************************/
 944 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 945                                             u8 *sp_pri_to_cos, const u8 pri,
 946                                             const u8 cos_entry)
 947 {
 948         struct bnx2x *bp = params->bp;
 949         const u8 port = params->port;
 950         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 951                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 952
 953         if (pri >= max_num_of_cos) {
 954                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 955                    "parameter Illegal strict priority\n");
 956             return -EINVAL;
 957         }
 958
 959         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 960                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 961                                    "parameter There can't be two COS's with "
 962                                    "the same strict pri\n");
 963                 return -EINVAL;
 964         }
 965
 966         sp_pri_to_cos[pri] = cos_entry;
 967         return 0;
 968
 969 }
 970
 971 /******************************************************************************
 972 * Description:
 973 *       Returns the correct value according to COS and priority in
 974 *       the sp_pri_cli register.
 975 *
 976 ******************************************************************************/
 977 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 978                                          const u8 pri_set,
 979                                          const u8 pri_offset,
 980                                          const u8 entry_size)
 981 {
 982         u64 pri_cli_nig = 0;
 983         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 984                                                     (pri_set + pri_offset));
 985
 986         return pri_cli_nig;
 987 }
 988 /******************************************************************************
 989 * Description:
 990 *       Returns the correct value according to COS and priority in the
 991 *       sp_pri_cli register for NIG.
 992 *
 993 ******************************************************************************/
 994 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 995 {
 996         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 997         const u8 nig_cos_offset = 3;
 998         const u8 nig_pri_offset = 3;
 999
1000         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1001                 nig_pri_offset, 4);
1002
1003 }
1004 /******************************************************************************
1005 * Description:
1006 *       Returns the correct value according to COS and priority in the
1007 *       sp_pri_cli register for PBF.
1008 *
1009 ******************************************************************************/
1010 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1011 {
1012         const u8 pbf_cos_offset = 0;
1013         const u8 pbf_pri_offset = 0;
1014
1015         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1016                 pbf_pri_offset, 3);
1017
1018 }
1019
1020 /******************************************************************************
1021 * Description:
1022 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1023 *       according to sp_pri_to_cos.(which COS has higher priority)
1024 *
1025 ******************************************************************************/
1026 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1027                                              u8 *sp_pri_to_cos)
1028 {
1029         struct bnx2x *bp = params->bp;
1030         u8 i = 0;
1031         const u8 port = params->port;
1032         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1033         u64 pri_cli_nig = 0x210;
1034         u32 pri_cli_pbf = 0x0;
1035         u8 pri_set = 0;
1036         u8 pri_bitmask = 0;
1037         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1038                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1039
1040         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1041
1042         /* Set all the strict priority first */
1043         for (i = 0; i < max_num_of_cos; i++) {
1044                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1045                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1046                                 DP(NETIF_MSG_LINK,
1047                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1048                                            "invalid cos entry\n");
1049                                 return -EINVAL;
1050                         }
1051
1052                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1053                             sp_pri_to_cos[i], pri_set);
1054
1055                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1056                             sp_pri_to_cos[i], pri_set);
1057                         pri_bitmask = 1 << sp_pri_to_cos[i];
1058                         /* COS is used remove it from bitmap.*/
1059                         if (!(pri_bitmask & cos_bit_to_set)) {
1060                                 DP(NETIF_MSG_LINK,
1061                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1062                                         "invalid There can't be two COS's with"
1063                                         " the same strict pri\n");
1064                                 return -EINVAL;
1065                         }
1066                         cos_bit_to_set &= ~pri_bitmask;
1067                         pri_set++;
1068                 }
1069         }
1070
1071         /* Set all the Non strict priority i= COS*/
1072         for (i = 0; i < max_num_of_cos; i++) {
1073                 pri_bitmask = 1 << i;
1074                 /* Check if COS was already used for SP */
1075                 if (pri_bitmask & cos_bit_to_set) {
1076                         /* COS wasn't used for SP */
1077                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1078                             i, pri_set);
1079
1080                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1081                             i, pri_set);
1082                         /* COS is used remove it from bitmap.*/
1083                         cos_bit_to_set &= ~pri_bitmask;
1084                         pri_set++;
1085                 }
1086         }
1087
1088         if (pri_set != max_num_of_cos) {
1089                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1090                                    "entries were set\n");
1091                 return -EINVAL;
1092         }
1093
1094         if (port) {
1095                 /* Only 6 usable clients*/
1096                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1097                        (u32)pri_cli_nig);
1098
1099                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1100         } else {
1101                 /* Only 9 usable clients*/
1102                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1103                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1104
1105                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1106                        pri_cli_nig_lsb);
1107                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1108                        pri_cli_nig_msb);
1109
1110                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1111         }
1112         return 0;
1113 }
1114
1115 /******************************************************************************
1116 * Description:
1117 *       Configure the COS to ETS according to BW and SP settings.
1118 ******************************************************************************/
1119 int bnx2x_ets_e3b0_config(const struct link_params *params,
1120                          const struct link_vars *vars,
1121                          struct bnx2x_ets_params *ets_params)
1122 {
1123         struct bnx2x *bp = params->bp;
1124         int bnx2x_status = 0;
1125         const u8 port = params->port;
1126         u16 total_bw = 0;
1127         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1128         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1129         u8 cos_bw_bitmap = 0;
1130         u8 cos_sp_bitmap = 0;
1131         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1132         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1133                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1134         u8 cos_entry = 0;
1135
1136         if (!CHIP_IS_E3B0(bp)) {
1137                 DP(NETIF_MSG_LINK,
1138                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1139                 return -EINVAL;
1140         }
1141
1142         if ((ets_params->num_of_cos > max_num_of_cos)) {
1143                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1144                                    "isn't supported\n");
1145                 return -EINVAL;
1146         }
1147
1148         /* Prepare sp strict priority parameters*/
1149         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1150
1151         /* Prepare BW parameters*/
1152         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1153                                                    &total_bw);
1154         if (bnx2x_status) {
1155                 DP(NETIF_MSG_LINK,
1156                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1157                 return -EINVAL;
1158         }
1159
1160         /* Upper bound is set according to current link speed (min_w_val
1161          * should be the same for upper bound and COS credit val).
1162          */
1163         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1164         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1165
1166
1167         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1168                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1169                         cos_bw_bitmap |= (1 << cos_entry);
1170                         /* The function also sets the BW in HW(not the mappin
1171                          * yet)
1172                          */
1173                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1174                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1175                                 total_bw,
1176                                 ets_params->cos[cos_entry].params.bw_params.bw,
1177                                  port);
1178                 } else if (bnx2x_cos_state_strict ==
1179                         ets_params->cos[cos_entry].state){
1180                         cos_sp_bitmap |= (1 << cos_entry);
1181
1182                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1183                                 params,
1184                                 sp_pri_to_cos,
1185                                 ets_params->cos[cos_entry].params.sp_params.pri,
1186                                 cos_entry);
1187
1188                 } else {
1189                         DP(NETIF_MSG_LINK,
1190                            "bnx2x_ets_e3b0_config cos state not valid\n");
1191                         return -EINVAL;
1192                 }
1193                 if (bnx2x_status) {
1194                         DP(NETIF_MSG_LINK,
1195                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1196                         return bnx2x_status;
1197                 }
1198         }
1199
1200         /* Set SP register (which COS has higher priority) */
1201         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1202                                                          sp_pri_to_cos);
1203
1204         if (bnx2x_status) {
1205                 DP(NETIF_MSG_LINK,
1206                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1207                 return bnx2x_status;
1208         }
1209
1210         /* Set client mapping of BW and strict */
1211         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1212                                               cos_sp_bitmap,
1213                                               cos_bw_bitmap);
1214
1215         if (bnx2x_status) {
1216                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1217                 return bnx2x_status;
1218         }
1219         return 0;
1220 }
1221 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1222 {
1223         /* ETS disabled configuration */
1224         struct bnx2x *bp = params->bp;
1225         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1226         /* Defines which entries (clients) are subjected to WFQ arbitration
1227          * COS0 0x8
1228          * COS1 0x10
1229          */
1230         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1231         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1232          * client numbers (WEIGHT_0 does not actually have to represent
1233          * client 0)
1234          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1235          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1236          */
1237         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1238
1239         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1240                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1241         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1242                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1243
1244         /* ETS mode enabled*/
1245         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1246
1247         /* Defines the number of consecutive slots for the strict priority */
1248         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1249         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1250          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1251          * entry, 4 - COS1 entry.
1252          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1253          * bit4   bit3    bit2     bit1    bit0
1254          * MCP and debug are strict
1255          */
1256         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1257
1258         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1259         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1260                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1261         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1262                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1263 }
1264
1265 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1266                         const u32 cos1_bw)
1267 {
1268         /* ETS disabled configuration*/
1269         struct bnx2x *bp = params->bp;
1270         const u32 total_bw = cos0_bw + cos1_bw;
1271         u32 cos0_credit_weight = 0;
1272         u32 cos1_credit_weight = 0;
1273
1274         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1275
1276         if ((!total_bw) ||
1277             (!cos0_bw) ||
1278             (!cos1_bw)) {
1279                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1280                 return;
1281         }
1282
1283         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1284                 total_bw;
1285         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1286                 total_bw;
1287
1288         bnx2x_ets_bw_limit_common(params);
1289
1290         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1291         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1292
1293         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1294         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1295 }
1296
1297 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1298 {
1299         /* ETS disabled configuration*/
1300         struct bnx2x *bp = params->bp;
1301         u32 val = 0;
1302
1303         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1304         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1305          * as strict.  Bits 0,1,2 - debug and management entries,
1306          * 3 - COS0 entry, 4 - COS1 entry.
1307          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1308          *  bit4   bit3   bit2      bit1     bit0
1309          * MCP and debug are strict
1310          */
1311         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1312         /* For strict priority entries defines the number of consecutive slots
1313          * for the highest priority.
1314          */
1315         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1316         /* ETS mode disable */
1317         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1318         /* Defines the number of consecutive slots for the strict priority */
1319         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1320
1321         /* Defines the number of consecutive slots for the strict priority */
1322         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1323
1324         /* Mapping between entry  priority to client number (0,1,2 -debug and
1325          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1326          * 3bits client num.
1327          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1328          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1329          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1330          */
1331         val = (!strict_cos) ? 0x2318 : 0x22E0;
1332         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1333
1334         return 0;
1335 }
1336
1337 /******************************************************************/
1338 /*                      PFC section                               */
1339 /******************************************************************/
1340 static void bnx2x_update_pfc_xmac(struct link_params *params,
1341                                   struct link_vars *vars,
1342                                   u8 is_lb)
1343 {
1344         struct bnx2x *bp = params->bp;
1345         u32 xmac_base;
1346         u32 pause_val, pfc0_val, pfc1_val;
1347
1348         /* XMAC base adrr */
1349         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1350
1351         /* Initialize pause and pfc registers */
1352         pause_val = 0x18000;
1353         pfc0_val = 0xFFFF8000;
1354         pfc1_val = 0x2;
1355
1356         /* No PFC support */
1357         if (!(params->feature_config_flags &
1358               FEATURE_CONFIG_PFC_ENABLED)) {
1359
1360                 /* RX flow control - Process pause frame in receive direction
1361                  */
1362                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1363                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1364
1365                 /* TX flow control - Send pause packet when buffer is full */
1366                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1367                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1368         } else {/* PFC support */
1369                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1370                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1371                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1372                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1373                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1374                 /* Write pause and PFC registers */
1375                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1376                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1377                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1378                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1379
1380         }
1381
1382         /* Write pause and PFC registers */
1383         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1384         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1385         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1386
1387
1388         /* Set MAC address for source TX Pause/PFC frames */
1389         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1390                ((params->mac_addr[2] << 24) |
1391                 (params->mac_addr[3] << 16) |
1392                 (params->mac_addr[4] << 8) |
1393                 (params->mac_addr[5])));
1394         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1395                ((params->mac_addr[0] << 8) |
1396                 (params->mac_addr[1])));
1397
1398         udelay(30);
1399 }
1400
1401
1402 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1403                                     u32 pfc_frames_sent[2],
1404                                     u32 pfc_frames_received[2])
1405 {
1406         /* Read pfc statistic */
1407         struct bnx2x *bp = params->bp;
1408         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1409         u32 val_xon = 0;
1410         u32 val_xoff = 0;
1411
1412         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1413
1414         /* PFC received frames */
1415         val_xoff = REG_RD(bp, emac_base +
1416                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1417         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1418         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1419         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1420
1421         pfc_frames_received[0] = val_xon + val_xoff;
1422
1423         /* PFC received sent */
1424         val_xoff = REG_RD(bp, emac_base +
1425                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1426         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1427         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1428         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1429
1430         pfc_frames_sent[0] = val_xon + val_xoff;
1431 }
1432
1433 /* Read pfc statistic*/
1434 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1435                          u32 pfc_frames_sent[2],
1436                          u32 pfc_frames_received[2])
1437 {
1438         /* Read pfc statistic */
1439         struct bnx2x *bp = params->bp;
1440
1441         DP(NETIF_MSG_LINK, "pfc statistic\n");
1442
1443         if (!vars->link_up)
1444                 return;
1445
1446         if (vars->mac_type == MAC_TYPE_EMAC) {
1447                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1448                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1449                                         pfc_frames_received);
1450         }
1451 }
1452 /******************************************************************/
1453 /*                      MAC/PBF section                           */
1454 /******************************************************************/
1455 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1456                                u32 emac_base)
1457 {
1458         u32 new_mode, cur_mode;
1459         u32 clc_cnt;
1460         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1461          * (a value of 49==0x31) and make sure that the AUTO poll is off
1462          */
1463         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1464
1465         if (USES_WARPCORE(bp))
1466                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1467         else
1468                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1469
1470         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1471             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1472                 return;
1473
1474         new_mode = cur_mode &
1475                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1476         new_mode |= clc_cnt;
1477         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1478
1479         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1480            cur_mode, new_mode);
1481         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1482         udelay(40);
1483 }
1484
1485 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1486                                         struct link_params *params)
1487 {
1488         u8 phy_index;
1489         /* Set mdio clock per phy */
1490         for (phy_index = INT_PHY; phy_index < params->num_phys;
1491               phy_index++)
1492                 bnx2x_set_mdio_clk(bp, params->chip_id,
1493                                    params->phy[phy_index].mdio_ctrl);
1494 }
1495
1496 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1497 {
1498         u32 port4mode_ovwr_val;
1499         /* Check 4-port override enabled */
1500         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1501         if (port4mode_ovwr_val & (1<<0)) {
1502                 /* Return 4-port mode override value */
1503                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1504         }
1505         /* Return 4-port mode from input pin */
1506         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1507 }
1508
1509 static void bnx2x_emac_init(struct link_params *params,
1510                             struct link_vars *vars)
1511 {
1512         /* reset and unreset the emac core */
1513         struct bnx2x *bp = params->bp;
1514         u8 port = params->port;
1515         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1516         u32 val;
1517         u16 timeout;
1518
1519         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1520                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1521         udelay(5);
1522         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1523                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1524
1525         /* init emac - use read-modify-write */
1526         /* self clear reset */
1527         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1528         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1529
1530         timeout = 200;
1531         do {
1532                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1533                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1534                 if (!timeout) {
1535                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1536                         return;
1537                 }
1538                 timeout--;
1539         } while (val & EMAC_MODE_RESET);
1540
1541         bnx2x_set_mdio_emac_per_phy(bp, params);
1542         /* Set mac address */
1543         val = ((params->mac_addr[0] << 8) |
1544                 params->mac_addr[1]);
1545         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1546
1547         val = ((params->mac_addr[2] << 24) |
1548                (params->mac_addr[3] << 16) |
1549                (params->mac_addr[4] << 8) |
1550                 params->mac_addr[5]);
1551         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1552 }
1553
1554 static void bnx2x_set_xumac_nig(struct link_params *params,
1555                                 u16 tx_pause_en,
1556                                 u8 enable)
1557 {
1558         struct bnx2x *bp = params->bp;
1559
1560         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1561                enable);
1562         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1563                enable);
1564         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1565                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1566 }
1567
1568 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1569 {
1570         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1571         u32 val;
1572         struct bnx2x *bp = params->bp;
1573         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1574                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1575                 return;
1576         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1577         if (en)
1578                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1579                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1580         else
1581                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1582                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1583         /* Disable RX and TX */
1584         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1585 }
1586
1587 static void bnx2x_umac_enable(struct link_params *params,
1588                             struct link_vars *vars, u8 lb)
1589 {
1590         u32 val;
1591         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1592         struct bnx2x *bp = params->bp;
1593         /* Reset UMAC */
1594         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1595                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1596         usleep_range(1000, 2000);
1597
1598         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1599                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1600
1601         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1602
1603         /* This register opens the gate for the UMAC despite its name */
1604         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1605
1606         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1607                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1608                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1609                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1610         switch (vars->line_speed) {
1611         case SPEED_10:
1612                 val |= (0<<2);
1613                 break;
1614         case SPEED_100:
1615                 val |= (1<<2);
1616                 break;
1617         case SPEED_1000:
1618                 val |= (2<<2);
1619                 break;
1620         case SPEED_2500:
1621                 val |= (3<<2);
1622                 break;
1623         default:
1624                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1625                                vars->line_speed);
1626                 break;
1627         }
1628         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1629                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1630
1631         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1632                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1633
1634         if (vars->duplex == DUPLEX_HALF)
1635                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1636
1637         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1638         udelay(50);
1639
1640         /* Configure UMAC for EEE */
1641         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1642                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1643                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1644                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1645                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1646         } else {
1647                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1648         }
1649
1650         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1651         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1652                ((params->mac_addr[2] << 24) |
1653                 (params->mac_addr[3] << 16) |
1654                 (params->mac_addr[4] << 8) |
1655                 (params->mac_addr[5])));
1656         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1657                ((params->mac_addr[0] << 8) |
1658                 (params->mac_addr[1])));
1659
1660         /* Enable RX and TX */
1661         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1662         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1663                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1664         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1665         udelay(50);
1666
1667         /* Remove SW Reset */
1668         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1669
1670         /* Check loopback mode */
1671         if (lb)
1672                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1673         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1674
1675         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1676          * length used by the MAC receive logic to check frames.
1677          */
1678         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1679         bnx2x_set_xumac_nig(params,
1680                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1681         vars->mac_type = MAC_TYPE_UMAC;
1682
1683 }
1684
1685 /* Define the XMAC mode */
1686 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1687 {
1688         struct bnx2x *bp = params->bp;
1689         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1690
1691         /* In 4-port mode, need to set the mode only once, so if XMAC is
1692          * already out of reset, it means the mode has already been set,
1693          * and it must not* reset the XMAC again, since it controls both
1694          * ports of the path
1695          */
1696
1697         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1698              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1699              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1700             is_port4mode &&
1701             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1702              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1703                 DP(NETIF_MSG_LINK,
1704                    "XMAC already out of reset in 4-port mode\n");
1705                 return;
1706         }
1707
1708         /* Hard reset */
1709         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1710                MISC_REGISTERS_RESET_REG_2_XMAC);
1711         usleep_range(1000, 2000);
1712
1713         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1714                MISC_REGISTERS_RESET_REG_2_XMAC);
1715         if (is_port4mode) {
1716                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1717
1718                 /* Set the number of ports on the system side to up to 2 */
1719                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1720
1721                 /* Set the number of ports on the Warp Core to 10G */
1722                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1723         } else {
1724                 /* Set the number of ports on the system side to 1 */
1725                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1726                 if (max_speed == SPEED_10000) {
1727                         DP(NETIF_MSG_LINK,
1728                            "Init XMAC to 10G x 1 port per path\n");
1729                         /* Set the number of ports on the Warp Core to 10G */
1730                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1731                 } else {
1732                         DP(NETIF_MSG_LINK,
1733                            "Init XMAC to 20G x 2 ports per path\n");
1734                         /* Set the number of ports on the Warp Core to 20G */
1735                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1736                 }
1737         }
1738         /* Soft reset */
1739         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1740                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1741         usleep_range(1000, 2000);
1742
1743         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1744                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1745
1746 }
1747
1748 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1749 {
1750         u8 port = params->port;
1751         struct bnx2x *bp = params->bp;
1752         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1753         u32 val;
1754
1755         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1756             MISC_REGISTERS_RESET_REG_2_XMAC) {
1757                 /* Send an indication to change the state in the NIG back to XON
1758                  * Clearing this bit enables the next set of this bit to get
1759                  * rising edge
1760                  */
1761                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1762                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1763                        (pfc_ctrl & ~(1<<1)));
1764                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1765                        (pfc_ctrl | (1<<1)));
1766                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1767                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1768                 if (en)
1769                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1770                 else
1771                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1772                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1773         }
1774 }
1775
1776 static int bnx2x_xmac_enable(struct link_params *params,
1777                              struct link_vars *vars, u8 lb)
1778 {
1779         u32 val, xmac_base;
1780         struct bnx2x *bp = params->bp;
1781         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1782
1783         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1784
1785         bnx2x_xmac_init(params, vars->line_speed);
1786
1787         /* This register determines on which events the MAC will assert
1788          * error on the i/f to the NIG along w/ EOP.
1789          */
1790
1791         /* This register tells the NIG whether to send traffic to UMAC
1792          * or XMAC
1793          */
1794         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1795
1796         /* When XMAC is in XLGMII mode, disable sending idles for fault
1797          * detection.
1798          */
1799         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1800                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1801                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1802                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1803                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1804                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1805                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1806                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1807         }
1808         /* Set Max packet size */
1809         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1810
1811         /* CRC append for Tx packets */
1812         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1813
1814         /* update PFC */
1815         bnx2x_update_pfc_xmac(params, vars, 0);
1816
1817         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1818                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1819                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1820                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1821         } else {
1822                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1823         }
1824
1825         /* Enable TX and RX */
1826         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1827
1828         /* Set MAC in XLGMII mode for dual-mode */
1829         if ((vars->line_speed == SPEED_20000) &&
1830             (params->phy[INT_PHY].supported &
1831              SUPPORTED_20000baseKR2_Full))
1832                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1833
1834         /* Check loopback mode */
1835         if (lb)
1836                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1837         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1838         bnx2x_set_xumac_nig(params,
1839                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1840
1841         vars->mac_type = MAC_TYPE_XMAC;
1842
1843         return 0;
1844 }
1845
1846 static int bnx2x_emac_enable(struct link_params *params,
1847                              struct link_vars *vars, u8 lb)
1848 {
1849         struct bnx2x *bp = params->bp;
1850         u8 port = params->port;
1851         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1852         u32 val;
1853
1854         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1855
1856         /* Disable BMAC */
1857         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1858                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1859
1860         /* enable emac and not bmac */
1861         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1862
1863         /* ASIC */
1864         if (vars->phy_flags & PHY_XGXS_FLAG) {
1865                 u32 ser_lane = ((params->lane_config &
1866                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1867                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1868
1869                 DP(NETIF_MSG_LINK, "XGXS\n");
1870                 /* select the master lanes (out of 0-3) */
1871                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1872                 /* select XGXS */
1873                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1874
1875         } else { /* SerDes */
1876                 DP(NETIF_MSG_LINK, "SerDes\n");
1877                 /* select SerDes */
1878                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1879         }
1880
1881         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1882                       EMAC_RX_MODE_RESET);
1883         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1884                       EMAC_TX_MODE_RESET);
1885
1886                 /* pause enable/disable */
1887                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1888                                EMAC_RX_MODE_FLOW_EN);
1889
1890                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1891                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1892                                 EMAC_TX_MODE_FLOW_EN));
1893                 if (!(params->feature_config_flags &
1894                       FEATURE_CONFIG_PFC_ENABLED)) {
1895                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1896                                 bnx2x_bits_en(bp, emac_base +
1897                                               EMAC_REG_EMAC_RX_MODE,
1898                                               EMAC_RX_MODE_FLOW_EN);
1899
1900                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1901                                 bnx2x_bits_en(bp, emac_base +
1902                                               EMAC_REG_EMAC_TX_MODE,
1903                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1904                                                EMAC_TX_MODE_FLOW_EN));
1905                 } else
1906                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1907                                       EMAC_TX_MODE_FLOW_EN);
1908
1909         /* KEEP_VLAN_TAG, promiscuous */
1910         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1911         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1912
1913         /* Setting this bit causes MAC control frames (except for pause
1914          * frames) to be passed on for processing. This setting has no
1915          * affect on the operation of the pause frames. This bit effects
1916          * all packets regardless of RX Parser packet sorting logic.
1917          * Turn the PFC off to make sure we are in Xon state before
1918          * enabling it.
1919          */
1920         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1921         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1922                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1923                 /* Enable PFC again */
1924                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1925                         EMAC_REG_RX_PFC_MODE_RX_EN |
1926                         EMAC_REG_RX_PFC_MODE_TX_EN |
1927                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1928
1929                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1930                         ((0x0101 <<
1931                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1932                          (0x00ff <<
1933                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1934                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1935         }
1936         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1937
1938         /* Set Loopback */
1939         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1940         if (lb)
1941                 val |= 0x810;
1942         else
1943                 val &= ~0x810;
1944         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1945
1946         /* Enable emac */
1947         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1948
1949         /* Enable emac for jumbo packets */
1950         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1951                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1952                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1953
1954         /* Strip CRC */
1955         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1956
1957         /* Disable the NIG in/out to the bmac */
1958         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1959         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1960         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1961
1962         /* Enable the NIG in/out to the emac */
1963         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1964         val = 0;
1965         if ((params->feature_config_flags &
1966               FEATURE_CONFIG_PFC_ENABLED) ||
1967             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1968                 val = 1;
1969
1970         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1971         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1972
1973         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1974
1975         vars->mac_type = MAC_TYPE_EMAC;
1976         return 0;
1977 }
1978
1979 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1980                                    struct link_vars *vars)
1981 {
1982         u32 wb_data[2];
1983         struct bnx2x *bp = params->bp;
1984         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1985                 NIG_REG_INGRESS_BMAC0_MEM;
1986
1987         u32 val = 0x14;
1988         if ((!(params->feature_config_flags &
1989               FEATURE_CONFIG_PFC_ENABLED)) &&
1990                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1991                 /* Enable BigMAC to react on received Pause packets */
1992                 val |= (1<<5);
1993         wb_data[0] = val;
1994         wb_data[1] = 0;
1995         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1996
1997         /* TX control */
1998         val = 0xc0;
1999         if (!(params->feature_config_flags &
2000               FEATURE_CONFIG_PFC_ENABLED) &&
2001                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2002                 val |= 0x800000;
2003         wb_data[0] = val;
2004         wb_data[1] = 0;
2005         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2006 }
2007
2008 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2009                                    struct link_vars *vars,
2010                                    u8 is_lb)
2011 {
2012         /* Set rx control: Strip CRC and enable BigMAC to relay
2013          * control packets to the system as well
2014          */
2015         u32 wb_data[2];
2016         struct bnx2x *bp = params->bp;
2017         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2018                 NIG_REG_INGRESS_BMAC0_MEM;
2019         u32 val = 0x14;
2020
2021         if ((!(params->feature_config_flags &
2022               FEATURE_CONFIG_PFC_ENABLED)) &&
2023                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2024                 /* Enable BigMAC to react on received Pause packets */
2025                 val |= (1<<5);
2026         wb_data[0] = val;
2027         wb_data[1] = 0;
2028         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2029         udelay(30);
2030
2031         /* Tx control */
2032         val = 0xc0;
2033         if (!(params->feature_config_flags &
2034                                 FEATURE_CONFIG_PFC_ENABLED) &&
2035             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2036                 val |= 0x800000;
2037         wb_data[0] = val;
2038         wb_data[1] = 0;
2039         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2040
2041         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2042                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2043                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2044                 wb_data[0] = 0x0;
2045                 wb_data[0] |= (1<<0);  /* RX */
2046                 wb_data[0] |= (1<<1);  /* TX */
2047                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2048                 wb_data[0] |= (1<<3);  /* 8 cos */
2049                 wb_data[0] |= (1<<5);  /* STATS */
2050                 wb_data[1] = 0;
2051                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2052                             wb_data, 2);
2053                 /* Clear the force Xon */
2054                 wb_data[0] &= ~(1<<2);
2055         } else {
2056                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2057                 /* Disable PFC RX & TX & STATS and set 8 COS */
2058                 wb_data[0] = 0x8;
2059                 wb_data[1] = 0;
2060         }
2061
2062         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2063
2064         /* Set Time (based unit is 512 bit time) between automatic
2065          * re-sending of PP packets amd enable automatic re-send of
2066          * Per-Priroity Packet as long as pp_gen is asserted and
2067          * pp_disable is low.
2068          */
2069         val = 0x8000;
2070         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2071                 val |= (1<<16); /* enable automatic re-send */
2072
2073         wb_data[0] = val;
2074         wb_data[1] = 0;
2075         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2076                     wb_data, 2);
2077
2078         /* mac control */
2079         val = 0x3; /* Enable RX and TX */
2080         if (is_lb) {
2081                 val |= 0x4; /* Local loopback */
2082                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2083         }
2084         /* When PFC enabled, Pass pause frames towards the NIG. */
2085         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2086                 val |= ((1<<6)|(1<<5));
2087
2088         wb_data[0] = val;
2089         wb_data[1] = 0;
2090         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2091 }
2092
2093 /******************************************************************************
2094 * Description:
2095 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2096 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2097 ******************************************************************************/
2098 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2099                                            u8 cos_entry,
2100                                            u32 priority_mask, u8 port)
2101 {
2102         u32 nig_reg_rx_priority_mask_add = 0;
2103
2104         switch (cos_entry) {
2105         case 0:
2106              nig_reg_rx_priority_mask_add = (port) ?
2107                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2108                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2109              break;
2110         case 1:
2111             nig_reg_rx_priority_mask_add = (port) ?
2112                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2113                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2114             break;
2115         case 2:
2116             nig_reg_rx_priority_mask_add = (port) ?
2117                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2118                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2119             break;
2120         case 3:
2121             if (port)
2122                 return -EINVAL;
2123             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2124             break;
2125         case 4:
2126             if (port)
2127                 return -EINVAL;
2128             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2129             break;
2130         case 5:
2131             if (port)
2132                 return -EINVAL;
2133             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2134             break;
2135         }
2136
2137         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2138
2139         return 0;
2140 }
2141 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2142 {
2143         struct bnx2x *bp = params->bp;
2144
2145         REG_WR(bp, params->shmem_base +
2146                offsetof(struct shmem_region,
2147                         port_mb[params->port].link_status), link_status);
2148 }
2149
2150 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2151 {
2152         struct bnx2x *bp = params->bp;
2153
2154         if (SHMEM2_HAS(bp, link_attr_sync))
2155                 REG_WR(bp, params->shmem2_base +
2156                        offsetof(struct shmem2_region,
2157                                 link_attr_sync[params->port]), link_attr);
2158 }
2159
2160 static void bnx2x_update_pfc_nig(struct link_params *params,
2161                 struct link_vars *vars,
2162                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2163 {
2164         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2165         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2166         u32 pkt_priority_to_cos = 0;
2167         struct bnx2x *bp = params->bp;
2168         u8 port = params->port;
2169
2170         int set_pfc = params->feature_config_flags &
2171                 FEATURE_CONFIG_PFC_ENABLED;
2172         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2173
2174         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2175          * MAC control frames (that are not pause packets)
2176          * will be forwarded to the XCM.
2177          */
2178         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2179                           NIG_REG_LLH0_XCM_MASK);
2180         /* NIG params will override non PFC params, since it's possible to
2181          * do transition from PFC to SAFC
2182          */
2183         if (set_pfc) {
2184                 pause_enable = 0;
2185                 llfc_out_en = 0;
2186                 llfc_enable = 0;
2187                 if (CHIP_IS_E3(bp))
2188                         ppp_enable = 0;
2189                 else
2190                         ppp_enable = 1;
2191                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2192                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2193                 xcm_out_en = 0;
2194                 hwpfc_enable = 1;
2195         } else  {
2196                 if (nig_params) {
2197                         llfc_out_en = nig_params->llfc_out_en;
2198                         llfc_enable = nig_params->llfc_enable;
2199                         pause_enable = nig_params->pause_enable;
2200                 } else  /* Default non PFC mode - PAUSE */
2201                         pause_enable = 1;
2202
2203                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2204                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2205                 xcm_out_en = 1;
2206         }
2207
2208         if (CHIP_IS_E3(bp))
2209                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2210                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2211         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2212                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2213         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2214                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2215         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2216                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2217
2218         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2219                NIG_REG_PPP_ENABLE_0, ppp_enable);
2220
2221         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2222                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2223
2224         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2225                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2226
2227         /* Output enable for RX_XCM # IF */
2228         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2229                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2230
2231         /* HW PFC TX enable */
2232         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2233                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2234
2235         if (nig_params) {
2236                 u8 i = 0;
2237                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2238
2239                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2240                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2241                 nig_params->rx_cos_priority_mask[i], port);
2242
2243                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2244                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2245                        nig_params->llfc_high_priority_classes);
2246
2247                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2248                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2249                        nig_params->llfc_low_priority_classes);
2250         }
2251         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2252                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2253                pkt_priority_to_cos);
2254 }
2255
2256 int bnx2x_update_pfc(struct link_params *params,
2257                       struct link_vars *vars,
2258                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2259 {
2260         /* The PFC and pause are orthogonal to one another, meaning when
2261          * PFC is enabled, the pause are disabled, and when PFC is
2262          * disabled, pause are set according to the pause result.
2263          */
2264         u32 val;
2265         struct bnx2x *bp = params->bp;
2266         int bnx2x_status = 0;
2267         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2268
2269         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2270                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2271         else
2272                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2273
2274         bnx2x_update_mng(params, vars->link_status);
2275
2276         /* Update NIG params */
2277         bnx2x_update_pfc_nig(params, vars, pfc_params);
2278
2279         if (!vars->link_up)
2280                 return bnx2x_status;
2281
2282         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2283
2284         if (CHIP_IS_E3(bp)) {
2285                 if (vars->mac_type == MAC_TYPE_XMAC)
2286                         bnx2x_update_pfc_xmac(params, vars, 0);
2287         } else {
2288                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2289                 if ((val &
2290                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2291                     == 0) {
2292                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2293                         bnx2x_emac_enable(params, vars, 0);
2294                         return bnx2x_status;
2295                 }
2296                 if (CHIP_IS_E2(bp))
2297                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2298                 else
2299                         bnx2x_update_pfc_bmac1(params, vars);
2300
2301                 val = 0;
2302                 if ((params->feature_config_flags &
2303                      FEATURE_CONFIG_PFC_ENABLED) ||
2304                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2305                         val = 1;
2306                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2307         }
2308         return bnx2x_status;
2309 }
2310
2311 static int bnx2x_bmac1_enable(struct link_params *params,
2312                               struct link_vars *vars,
2313                               u8 is_lb)
2314 {
2315         struct bnx2x *bp = params->bp;
2316         u8 port = params->port;
2317         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2318                                NIG_REG_INGRESS_BMAC0_MEM;
2319         u32 wb_data[2];
2320         u32 val;
2321
2322         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2323
2324         /* XGXS control */
2325         wb_data[0] = 0x3c;
2326         wb_data[1] = 0;
2327         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2328                     wb_data, 2);
2329
2330         /* TX MAC SA */
2331         wb_data[0] = ((params->mac_addr[2] << 24) |
2332                        (params->mac_addr[3] << 16) |
2333                        (params->mac_addr[4] << 8) |
2334                         params->mac_addr[5]);
2335         wb_data[1] = ((params->mac_addr[0] << 8) |
2336                         params->mac_addr[1]);
2337         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2338
2339         /* MAC control */
2340         val = 0x3;
2341         if (is_lb) {
2342                 val |= 0x4;
2343                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2344         }
2345         wb_data[0] = val;
2346         wb_data[1] = 0;
2347         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2348
2349         /* Set rx mtu */
2350         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2351         wb_data[1] = 0;
2352         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2353
2354         bnx2x_update_pfc_bmac1(params, vars);
2355
2356         /* Set tx mtu */
2357         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2358         wb_data[1] = 0;
2359         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2360
2361         /* Set cnt max size */
2362         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2363         wb_data[1] = 0;
2364         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2365
2366         /* Configure SAFC */
2367         wb_data[0] = 0x1000200;
2368         wb_data[1] = 0;
2369         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2370                     wb_data, 2);
2371
2372         return 0;
2373 }
2374
2375 static int bnx2x_bmac2_enable(struct link_params *params,
2376                               struct link_vars *vars,
2377                               u8 is_lb)
2378 {
2379         struct bnx2x *bp = params->bp;
2380         u8 port = params->port;
2381         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2382                                NIG_REG_INGRESS_BMAC0_MEM;
2383         u32 wb_data[2];
2384
2385         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2386
2387         wb_data[0] = 0;
2388         wb_data[1] = 0;
2389         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2390         udelay(30);
2391
2392         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2393         wb_data[0] = 0x3c;
2394         wb_data[1] = 0;
2395         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2396                     wb_data, 2);
2397
2398         udelay(30);
2399
2400         /* TX MAC SA */
2401         wb_data[0] = ((params->mac_addr[2] << 24) |
2402                        (params->mac_addr[3] << 16) |
2403                        (params->mac_addr[4] << 8) |
2404                         params->mac_addr[5]);
2405         wb_data[1] = ((params->mac_addr[0] << 8) |
2406                         params->mac_addr[1]);
2407         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2408                     wb_data, 2);
2409
2410         udelay(30);
2411
2412         /* Configure SAFC */
2413         wb_data[0] = 0x1000200;
2414         wb_data[1] = 0;
2415         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2416                     wb_data, 2);
2417         udelay(30);
2418
2419         /* Set RX MTU */
2420         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2421         wb_data[1] = 0;
2422         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2423         udelay(30);
2424
2425         /* Set TX MTU */
2426         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2427         wb_data[1] = 0;
2428         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2429         udelay(30);
2430         /* Set cnt max size */
2431         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2432         wb_data[1] = 0;
2433         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2434         udelay(30);
2435         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2436
2437         return 0;
2438 }
2439
2440 static int bnx2x_bmac_enable(struct link_params *params,
2441                              struct link_vars *vars,
2442                              u8 is_lb, u8 reset_bmac)
2443 {
2444         int rc = 0;
2445         u8 port = params->port;
2446         struct bnx2x *bp = params->bp;
2447         u32 val;
2448         /* Reset and unreset the BigMac */
2449         if (reset_bmac) {
2450                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2451                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2452                 usleep_range(1000, 2000);
2453         }
2454
2455         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2456                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2457
2458         /* Enable access for bmac registers */
2459         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2460
2461         /* Enable BMAC according to BMAC type*/
2462         if (CHIP_IS_E2(bp))
2463                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2464         else
2465                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2466         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2467         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2468         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2469         val = 0;
2470         if ((params->feature_config_flags &
2471               FEATURE_CONFIG_PFC_ENABLED) ||
2472             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2473                 val = 1;
2474         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2475         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2476         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2477         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2478         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2479         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2480
2481         vars->mac_type = MAC_TYPE_BMAC;
2482         return rc;
2483 }
2484
2485 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2486 {
2487         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2488                         NIG_REG_INGRESS_BMAC0_MEM;
2489         u32 wb_data[2];
2490         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2491
2492         if (CHIP_IS_E2(bp))
2493                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2494         else
2495                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2496         /* Only if the bmac is out of reset */
2497         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2498                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2499             nig_bmac_enable) {
2500                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2501                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2502                 if (en)
2503                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2504                 else
2505                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2506                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2507                 usleep_range(1000, 2000);
2508         }
2509 }
2510
2511 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2512                             u32 line_speed)
2513 {
2514         struct bnx2x *bp = params->bp;
2515         u8 port = params->port;
2516         u32 init_crd, crd;
2517         u32 count = 1000;
2518
2519         /* Disable port */
2520         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2521
2522         /* Wait for init credit */
2523         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2524         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2525         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2526
2527         while ((init_crd != crd) && count) {
2528                 usleep_range(5000, 10000);
2529                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2530                 count--;
2531         }
2532         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2533         if (init_crd != crd) {
2534                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2535                           init_crd, crd);
2536                 return -EINVAL;
2537         }
2538
2539         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2540             line_speed == SPEED_10 ||
2541             line_speed == SPEED_100 ||
2542             line_speed == SPEED_1000 ||
2543             line_speed == SPEED_2500) {
2544                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2545                 /* Update threshold */
2546                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2547                 /* Update init credit */
2548                 init_crd = 778;         /* (800-18-4) */
2549
2550         } else {
2551                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2552                               ETH_OVREHEAD)/16;
2553                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2554                 /* Update threshold */
2555                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2556                 /* Update init credit */
2557                 switch (line_speed) {
2558                 case SPEED_10000:
2559                         init_crd = thresh + 553 - 22;
2560                         break;
2561                 default:
2562                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2563                                   line_speed);
2564                         return -EINVAL;
2565                 }
2566         }
2567         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2568         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2569                  line_speed, init_crd);
2570
2571         /* Probe the credit changes */
2572         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2573         usleep_range(5000, 10000);
2574         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2575
2576         /* Enable port */
2577         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2578         return 0;
2579 }
2580
2581 /**
2582  * bnx2x_get_emac_base - retrive emac base address
2583  *
2584  * @bp:                 driver handle
2585  * @mdc_mdio_access:    access type
2586  * @port:               port id
2587  *
2588  * This function selects the MDC/MDIO access (through emac0 or
2589  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2590  * phy has a default access mode, which could also be overridden
2591  * by nvram configuration. This parameter, whether this is the
2592  * default phy configuration, or the nvram overrun
2593  * configuration, is passed here as mdc_mdio_access and selects
2594  * the emac_base for the CL45 read/writes operations
2595  */
2596 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2597                                u32 mdc_mdio_access, u8 port)
2598 {
2599         u32 emac_base = 0;
2600         switch (mdc_mdio_access) {
2601         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2602                 break;
2603         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2604                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2605                         emac_base = GRCBASE_EMAC1;
2606                 else
2607                         emac_base = GRCBASE_EMAC0;
2608                 break;
2609         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2610                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2611                         emac_base = GRCBASE_EMAC0;
2612                 else
2613                         emac_base = GRCBASE_EMAC1;
2614                 break;
2615         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2616                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2617                 break;
2618         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2619                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2620                 break;
2621         default:
2622                 break;
2623         }
2624         return emac_base;
2625
2626 }
2627
2628 /******************************************************************/
2629 /*                      CL22 access functions                     */
2630 /******************************************************************/
2631 static int bnx2x_cl22_write(struct bnx2x *bp,
2632                                        struct bnx2x_phy *phy,
2633                                        u16 reg, u16 val)
2634 {
2635         u32 tmp, mode;
2636         u8 i;
2637         int rc = 0;
2638         /* Switch to CL22 */
2639         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2640         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2641                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2642
2643         /* Address */
2644         tmp = ((phy->addr << 21) | (reg << 16) | val |
2645                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2646                EMAC_MDIO_COMM_START_BUSY);
2647         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2648
2649         for (i = 0; i < 50; i++) {
2650                 udelay(10);
2651
2652                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2653                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2654                         udelay(5);
2655                         break;
2656                 }
2657         }
2658         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2659                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2660                 rc = -EFAULT;
2661         }
2662         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2663         return rc;
2664 }
2665
2666 static int bnx2x_cl22_read(struct bnx2x *bp,
2667                                       struct bnx2x_phy *phy,
2668                                       u16 reg, u16 *ret_val)
2669 {
2670         u32 val, mode;
2671         u16 i;
2672         int rc = 0;
2673
2674         /* Switch to CL22 */
2675         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2676         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2677                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2678
2679         /* Address */
2680         val = ((phy->addr << 21) | (reg << 16) |
2681                EMAC_MDIO_COMM_COMMAND_READ_22 |
2682                EMAC_MDIO_COMM_START_BUSY);
2683         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2684
2685         for (i = 0; i < 50; i++) {
2686                 udelay(10);
2687
2688                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2689                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2690                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2691                         udelay(5);
2692                         break;
2693                 }
2694         }
2695         if (val & EMAC_MDIO_COMM_START_BUSY) {
2696                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2697
2698                 *ret_val = 0;
2699                 rc = -EFAULT;
2700         }
2701         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2702         return rc;
2703 }
2704
2705 /******************************************************************/
2706 /*                      CL45 access functions                     */
2707 /******************************************************************/
2708 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2709                            u8 devad, u16 reg, u16 *ret_val)
2710 {
2711         u32 val;
2712         u16 i;
2713         int rc = 0;
2714         u32 chip_id;
2715         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2716                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2717                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2718                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2719         }
2720
2721         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2722                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2723                               EMAC_MDIO_STATUS_10MB);
2724         /* Address */
2725         val = ((phy->addr << 21) | (devad << 16) | reg |
2726                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2727                EMAC_MDIO_COMM_START_BUSY);
2728         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2729
2730         for (i = 0; i < 50; i++) {
2731                 udelay(10);
2732
2733                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2734                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2735                         udelay(5);
2736                         break;
2737                 }
2738         }
2739         if (val & EMAC_MDIO_COMM_START_BUSY) {
2740                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2741                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2742                 *ret_val = 0;
2743                 rc = -EFAULT;
2744         } else {
2745                 /* Data */
2746                 val = ((phy->addr << 21) | (devad << 16) |
2747                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2748                        EMAC_MDIO_COMM_START_BUSY);
2749                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2750
2751                 for (i = 0; i < 50; i++) {
2752                         udelay(10);
2753
2754                         val = REG_RD(bp, phy->mdio_ctrl +
2755                                      EMAC_REG_EMAC_MDIO_COMM);
2756                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2757                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2758                                 break;
2759                         }
2760                 }
2761                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2762                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2763                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2764                         *ret_val = 0;
2765                         rc = -EFAULT;
2766                 }
2767         }
2768         /* Work around for E3 A0 */
2769         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2770                 phy->flags ^= FLAGS_DUMMY_READ;
2771                 if (phy->flags & FLAGS_DUMMY_READ) {
2772                         u16 temp_val;
2773                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2774                 }
2775         }
2776
2777         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2778                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2779                                EMAC_MDIO_STATUS_10MB);
2780         return rc;
2781 }
2782
2783 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2784                             u8 devad, u16 reg, u16 val)
2785 {
2786         u32 tmp;
2787         u8 i;
2788         int rc = 0;
2789         u32 chip_id;
2790         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2791                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2792                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2793                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2794         }
2795
2796         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2797                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2798                               EMAC_MDIO_STATUS_10MB);
2799
2800         /* Address */
2801         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2802                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2803                EMAC_MDIO_COMM_START_BUSY);
2804         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2805
2806         for (i = 0; i < 50; i++) {
2807                 udelay(10);
2808
2809                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2810                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2811                         udelay(5);
2812                         break;
2813                 }
2814         }
2815         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2816                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2817                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2818                 rc = -EFAULT;
2819         } else {
2820                 /* Data */
2821                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2822                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2823                        EMAC_MDIO_COMM_START_BUSY);
2824                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2825
2826                 for (i = 0; i < 50; i++) {
2827                         udelay(10);
2828
2829                         tmp = REG_RD(bp, phy->mdio_ctrl +
2830                                      EMAC_REG_EMAC_MDIO_COMM);
2831                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2832                                 udelay(5);
2833                                 break;
2834                         }
2835                 }
2836                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2837                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2838                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2839                         rc = -EFAULT;
2840                 }
2841         }
2842         /* Work around for E3 A0 */
2843         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2844                 phy->flags ^= FLAGS_DUMMY_READ;
2845                 if (phy->flags & FLAGS_DUMMY_READ) {
2846                         u16 temp_val;
2847                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2848                 }
2849         }
2850         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2851                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2852                                EMAC_MDIO_STATUS_10MB);
2853         return rc;
2854 }
2855
2856 /******************************************************************/
2857 /*                      EEE section                                */
2858 /******************************************************************/
2859 static u8 bnx2x_eee_has_cap(struct link_params *params)
2860 {
2861         struct bnx2x *bp = params->bp;
2862
2863         if (REG_RD(bp, params->shmem2_base) <=
2864                    offsetof(struct shmem2_region, eee_status[params->port]))
2865                 return 0;
2866
2867         return 1;
2868 }
2869
2870 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2871 {
2872         switch (nvram_mode) {
2873         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2874                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2875                 break;
2876         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2877                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2878                 break;
2879         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2880                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2881                 break;
2882         default:
2883                 *idle_timer = 0;
2884                 break;
2885         }
2886
2887         return 0;
2888 }
2889
2890 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2891 {
2892         switch (idle_timer) {
2893         case EEE_MODE_NVRAM_BALANCED_TIME:
2894                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2895                 break;
2896         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2897                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2898                 break;
2899         case EEE_MODE_NVRAM_LATENCY_TIME:
2900                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2901                 break;
2902         default:
2903                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2904                 break;
2905         }
2906
2907         return 0;
2908 }
2909
2910 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2911 {
2912         u32 eee_mode, eee_idle;
2913         struct bnx2x *bp = params->bp;
2914
2915         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2916                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2917                         /* time value in eee_mode --> used directly*/
2918                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2919                 } else {
2920                         /* hsi value in eee_mode --> time */
2921                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2922                                                     EEE_MODE_NVRAM_MASK,
2923                                                     &eee_idle))
2924                                 return 0;
2925                 }
2926         } else {
2927                 /* hsi values in nvram --> time*/
2928                 eee_mode = ((REG_RD(bp, params->shmem_base +
2929                                     offsetof(struct shmem_region, dev_info.
2930                                     port_feature_config[params->port].
2931                                     eee_power_mode)) &
2932                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2933                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2934
2935                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2936                         return 0;
2937         }
2938
2939         return eee_idle;
2940 }
2941
2942 static int bnx2x_eee_set_timers(struct link_params *params,
2943                                    struct link_vars *vars)
2944 {
2945         u32 eee_idle = 0, eee_mode;
2946         struct bnx2x *bp = params->bp;
2947
2948         eee_idle = bnx2x_eee_calc_timer(params);
2949
2950         if (eee_idle) {
2951                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2952                        eee_idle);
2953         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2954                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2955                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2956                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2957                 return -EINVAL;
2958         }
2959
2960         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2961         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2962                 /* eee_idle in 1u --> eee_status in 16u */
2963                 eee_idle >>= 4;
2964                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2965                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2966         } else {
2967                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2968                         return -EINVAL;
2969                 vars->eee_status |= eee_mode;
2970         }
2971
2972         return 0;
2973 }
2974
2975 static int bnx2x_eee_initial_config(struct link_params *params,
2976                                      struct link_vars *vars, u8 mode)
2977 {
2978         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2979
2980         /* Propogate params' bits --> vars (for migration exposure) */
2981         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2982                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2983         else
2984                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2985
2986         if (params->eee_mode & EEE_MODE_ADV_LPI)
2987                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2988         else
2989                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2990
2991         return bnx2x_eee_set_timers(params, vars);
2992 }
2993
2994 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2995                                 struct link_params *params,
2996                                 struct link_vars *vars)
2997 {
2998         struct bnx2x *bp = params->bp;
2999
3000         /* Make Certain LPI is disabled */
3001         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3002
3003         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3004
3005         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3006
3007         return 0;
3008 }
3009
3010 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3011                                   struct link_params *params,
3012                                   struct link_vars *vars, u8 modes)
3013 {
3014         struct bnx2x *bp = params->bp;
3015         u16 val = 0;
3016
3017         /* Mask events preventing LPI generation */
3018         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3019
3020         if (modes & SHMEM_EEE_10G_ADV) {
3021                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3022                 val |= 0x8;
3023         }
3024         if (modes & SHMEM_EEE_1G_ADV) {
3025                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3026                 val |= 0x4;
3027         }
3028
3029         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3030
3031         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3032         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3033
3034         return 0;
3035 }
3036
3037 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3038 {
3039         struct bnx2x *bp = params->bp;
3040
3041         if (bnx2x_eee_has_cap(params))
3042                 REG_WR(bp, params->shmem2_base +
3043                        offsetof(struct shmem2_region,
3044                                 eee_status[params->port]), eee_status);
3045 }
3046
3047 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3048                                   struct link_params *params,
3049                                   struct link_vars *vars)
3050 {
3051         struct bnx2x *bp = params->bp;
3052         u16 adv = 0, lp = 0;
3053         u32 lp_adv = 0;
3054         u8 neg = 0;
3055
3056         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3057         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3058
3059         if (lp & 0x2) {
3060                 lp_adv |= SHMEM_EEE_100M_ADV;
3061                 if (adv & 0x2) {
3062                         if (vars->line_speed == SPEED_100)
3063                                 neg = 1;
3064                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3065                 }
3066         }
3067         if (lp & 0x14) {
3068                 lp_adv |= SHMEM_EEE_1G_ADV;
3069                 if (adv & 0x14) {
3070                         if (vars->line_speed == SPEED_1000)
3071                                 neg = 1;
3072                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3073                 }
3074         }
3075         if (lp & 0x68) {
3076                 lp_adv |= SHMEM_EEE_10G_ADV;
3077                 if (adv & 0x68) {
3078                         if (vars->line_speed == SPEED_10000)
3079                                 neg = 1;
3080                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3081                 }
3082         }
3083
3084         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3085         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3086
3087         if (neg) {
3088                 DP(NETIF_MSG_LINK, "EEE is active\n");
3089                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3090         }
3091
3092 }
3093
3094 /******************************************************************/
3095 /*                      BSC access functions from E3              */
3096 /******************************************************************/
3097 static void bnx2x_bsc_module_sel(struct link_params *params)
3098 {
3099         int idx;
3100         u32 board_cfg, sfp_ctrl;
3101         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3102         struct bnx2x *bp = params->bp;
3103         u8 port = params->port;
3104         /* Read I2C output PINs */
3105         board_cfg = REG_RD(bp, params->shmem_base +
3106                            offsetof(struct shmem_region,
3107                                     dev_info.shared_hw_config.board));
3108         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3109         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3110                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3111
3112         /* Read I2C output value */
3113         sfp_ctrl = REG_RD(bp, params->shmem_base +
3114                           offsetof(struct shmem_region,
3115                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3116         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3117         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3118         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3119         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3120                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3121 }
3122
3123 static int bnx2x_bsc_read(struct link_params *params,
3124                           struct bnx2x_phy *phy,
3125                           u8 sl_devid,
3126                           u16 sl_addr,
3127                           u8 lc_addr,
3128                           u8 xfer_cnt,
3129                           u32 *data_array)
3130 {
3131         u32 val, i;
3132         int rc = 0;
3133         struct bnx2x *bp = params->bp;
3134
3135         if (xfer_cnt > 16) {
3136                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3137                                         xfer_cnt);
3138                 return -EINVAL;
3139         }
3140         bnx2x_bsc_module_sel(params);
3141
3142         xfer_cnt = 16 - lc_addr;
3143
3144         /* Enable the engine */
3145         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146         val |= MCPR_IMC_COMMAND_ENABLE;
3147         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3148
3149         /* Program slave device ID */
3150         val = (sl_devid << 16) | sl_addr;
3151         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3152
3153         /* Start xfer with 0 byte to update the address pointer ???*/
3154         val = (MCPR_IMC_COMMAND_ENABLE) |
3155               (MCPR_IMC_COMMAND_WRITE_OP <<
3156                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3157                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3158         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3159
3160         /* Poll for completion */
3161         i = 0;
3162         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3163         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3164                 udelay(10);
3165                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3166                 if (i++ > 1000) {
3167                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3168                                                                 i);
3169                         rc = -EFAULT;
3170                         break;
3171                 }
3172         }
3173         if (rc == -EFAULT)
3174                 return rc;
3175
3176         /* Start xfer with read op */
3177         val = (MCPR_IMC_COMMAND_ENABLE) |
3178                 (MCPR_IMC_COMMAND_READ_OP <<
3179                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3180                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3181                   (xfer_cnt);
3182         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3183
3184         /* Poll for completion */
3185         i = 0;
3186         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3187         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3188                 udelay(10);
3189                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3190                 if (i++ > 1000) {
3191                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3192                         rc = -EFAULT;
3193                         break;
3194                 }
3195         }
3196         if (rc == -EFAULT)
3197                 return rc;
3198
3199         for (i = (lc_addr >> 2); i < 4; i++) {
3200                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3201 #ifdef __BIG_ENDIAN
3202                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3203                                 ((data_array[i] & 0x0000ff00) << 8) |
3204                                 ((data_array[i] & 0x00ff0000) >> 8) |
3205                                 ((data_array[i] & 0xff000000) >> 24);
3206 #endif
3207         }
3208         return rc;
3209 }
3210
3211 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3212                                      u8 devad, u16 reg, u16 or_val)
3213 {
3214         u16 val;
3215         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3216         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3217 }
3218
3219 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3220                                       struct bnx2x_phy *phy,
3221                                       u8 devad, u16 reg, u16 and_val)
3222 {
3223         u16 val;
3224         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3225         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3226 }
3227
3228 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3229                    u8 devad, u16 reg, u16 *ret_val)
3230 {
3231         u8 phy_index;
3232         /* Probe for the phy according to the given phy_addr, and execute
3233          * the read request on it
3234          */
3235         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236                 if (params->phy[phy_index].addr == phy_addr) {
3237                         return bnx2x_cl45_read(params->bp,
3238                                                &params->phy[phy_index], devad,
3239                                                reg, ret_val);
3240                 }
3241         }
3242         return -EINVAL;
3243 }
3244
3245 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3246                     u8 devad, u16 reg, u16 val)
3247 {
3248         u8 phy_index;
3249         /* Probe for the phy according to the given phy_addr, and execute
3250          * the write request on it
3251          */
3252         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3253                 if (params->phy[phy_index].addr == phy_addr) {
3254                         return bnx2x_cl45_write(params->bp,
3255                                                 &params->phy[phy_index], devad,
3256                                                 reg, val);
3257                 }
3258         }
3259         return -EINVAL;
3260 }
3261 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3262                                   struct link_params *params)
3263 {
3264         u8 lane = 0;
3265         struct bnx2x *bp = params->bp;
3266         u32 path_swap, path_swap_ovr;
3267         u8 path, port;
3268
3269         path = BP_PATH(bp);
3270         port = params->port;
3271
3272         if (bnx2x_is_4_port_mode(bp)) {
3273                 u32 port_swap, port_swap_ovr;
3274
3275                 /* Figure out path swap value */
3276                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3277                 if (path_swap_ovr & 0x1)
3278                         path_swap = (path_swap_ovr & 0x2);
3279                 else
3280                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3281
3282                 if (path_swap)
3283                         path = path ^ 1;
3284
3285                 /* Figure out port swap value */
3286                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3287                 if (port_swap_ovr & 0x1)
3288                         port_swap = (port_swap_ovr & 0x2);
3289                 else
3290                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3291
3292                 if (port_swap)
3293                         port = port ^ 1;
3294
3295                 lane = (port<<1) + path;
3296         } else { /* Two port mode - no port swap */
3297
3298                 /* Figure out path swap value */
3299                 path_swap_ovr =
3300                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3301                 if (path_swap_ovr & 0x1) {
3302                         path_swap = (path_swap_ovr & 0x2);
3303                 } else {
3304                         path_swap =
3305                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3306                 }
3307                 if (path_swap)
3308                         path = path ^ 1;
3309
3310                 lane = path << 1 ;
3311         }
3312         return lane;
3313 }
3314
3315 static void bnx2x_set_aer_mmd(struct link_params *params,
3316                               struct bnx2x_phy *phy)
3317 {
3318         u32 ser_lane;
3319         u16 offset, aer_val;
3320         struct bnx2x *bp = params->bp;
3321         ser_lane = ((params->lane_config &
3322                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3323                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3324
3325         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3326                 (phy->addr + ser_lane) : 0;
3327
3328         if (USES_WARPCORE(bp)) {
3329                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3330                 /* In Dual-lane mode, two lanes are joined together,
3331                  * so in order to configure them, the AER broadcast method is
3332                  * used here.
3333                  * 0x200 is the broadcast address for lanes 0,1
3334                  * 0x201 is the broadcast address for lanes 2,3
3335                  */
3336                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3337                         aer_val = (aer_val >> 1) | 0x200;
3338         } else if (CHIP_IS_E2(bp))
3339                 aer_val = 0x3800 + offset - 1;
3340         else
3341                 aer_val = 0x3800 + offset;
3342
3343         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3344                           MDIO_AER_BLOCK_AER_REG, aer_val);
3345
3346 }
3347
3348 /******************************************************************/
3349 /*                      Internal phy section                      */
3350 /******************************************************************/
3351
3352 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3353 {
3354         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3355
3356         /* Set Clause 22 */
3357         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3358         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3359         udelay(500);
3360         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3361         udelay(500);
3362          /* Set Clause 45 */
3363         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3364 }
3365
3366 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3367 {
3368         u32 val;
3369
3370         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3371
3372         val = SERDES_RESET_BITS << (port*16);
3373
3374         /* Reset and unreset the SerDes/XGXS */
3375         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3376         udelay(500);
3377         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3378
3379         bnx2x_set_serdes_access(bp, port);
3380
3381         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3382                DEFAULT_PHY_DEV_ADDR);
3383 }
3384
3385 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3386                                      struct link_params *params,
3387                                      u32 action)
3388 {
3389         struct bnx2x *bp = params->bp;
3390         switch (action) {
3391         case PHY_INIT:
3392                 /* Set correct devad */
3393                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3394                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3395                        phy->def_md_devad);
3396                 break;
3397         }
3398 }
3399
3400 static void bnx2x_xgxs_deassert(struct link_params *params)
3401 {
3402         struct bnx2x *bp = params->bp;
3403         u8 port;
3404         u32 val;
3405         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3406         port = params->port;
3407
3408         val = XGXS_RESET_BITS << (port*16);
3409
3410         /* Reset and unreset the SerDes/XGXS */
3411         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3412         udelay(500);
3413         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3414         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3415                                  PHY_INIT);
3416 }
3417
3418 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3419                                      struct link_params *params, u16 *ieee_fc)
3420 {
3421         struct bnx2x *bp = params->bp;
3422         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3423         /* Resolve pause mode and advertisement Please refer to Table
3424          * 28B-3 of the 802.3ab-1999 spec
3425          */
3426
3427         switch (phy->req_flow_ctrl) {
3428         case BNX2X_FLOW_CTRL_AUTO:
3429                 switch (params->req_fc_auto_adv) {
3430                 case BNX2X_FLOW_CTRL_BOTH:
3431                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3432                         break;
3433                 case BNX2X_FLOW_CTRL_RX:
3434                 case BNX2X_FLOW_CTRL_TX:
3435                         *ieee_fc |=
3436                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3437                         break;
3438                 default:
3439                         break;
3440                 }
3441                 break;
3442         case BNX2X_FLOW_CTRL_TX:
3443                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3444                 break;
3445
3446         case BNX2X_FLOW_CTRL_RX:
3447         case BNX2X_FLOW_CTRL_BOTH:
3448                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3449                 break;
3450
3451         case BNX2X_FLOW_CTRL_NONE:
3452         default:
3453                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3454                 break;
3455         }
3456         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3457 }
3458
3459 static void set_phy_vars(struct link_params *params,
3460                          struct link_vars *vars)
3461 {
3462         struct bnx2x *bp = params->bp;
3463         u8 actual_phy_idx, phy_index, link_cfg_idx;
3464         u8 phy_config_swapped = params->multi_phy_config &
3465                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3466         for (phy_index = INT_PHY; phy_index < params->num_phys;
3467               phy_index++) {
3468                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3469                 actual_phy_idx = phy_index;
3470                 if (phy_config_swapped) {
3471                         if (phy_index == EXT_PHY1)
3472                                 actual_phy_idx = EXT_PHY2;
3473                         else if (phy_index == EXT_PHY2)
3474                                 actual_phy_idx = EXT_PHY1;
3475                 }
3476                 params->phy[actual_phy_idx].req_flow_ctrl =
3477                         params->req_flow_ctrl[link_cfg_idx];
3478
3479                 params->phy[actual_phy_idx].req_line_speed =
3480                         params->req_line_speed[link_cfg_idx];
3481
3482                 params->phy[actual_phy_idx].speed_cap_mask =
3483                         params->speed_cap_mask[link_cfg_idx];
3484
3485                 params->phy[actual_phy_idx].req_duplex =
3486                         params->req_duplex[link_cfg_idx];
3487
3488                 if (params->req_line_speed[link_cfg_idx] ==
3489                     SPEED_AUTO_NEG)
3490                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3491
3492                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3493                            " speed_cap_mask %x\n",
3494                            params->phy[actual_phy_idx].req_flow_ctrl,
3495                            params->phy[actual_phy_idx].req_line_speed,
3496                            params->phy[actual_phy_idx].speed_cap_mask);
3497         }
3498 }
3499
3500 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3501                                     struct bnx2x_phy *phy,
3502                                     struct link_vars *vars)
3503 {
3504         u16 val;
3505         struct bnx2x *bp = params->bp;
3506         /* Read modify write pause advertizing */
3507         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3508
3509         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3510
3511         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3512         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3513         if ((vars->ieee_fc &
3514             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3515             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3516                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3517         }
3518         if ((vars->ieee_fc &
3519             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3520             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3521                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3522         }
3523         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3524         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3525 }
3526
3527 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3528 {                                               /*  LD      LP   */
3529         switch (pause_result) {                 /* ASYM P ASYM P */
3530         case 0xb:                               /*   1  0   1  1 */
3531                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3532                 break;
3533
3534         case 0xe:                               /*   1  1   1  0 */
3535                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3536                 break;
3537
3538         case 0x5:                               /*   0  1   0  1 */
3539         case 0x7:                               /*   0  1   1  1 */
3540         case 0xd:                               /*   1  1   0  1 */
3541         case 0xf:                               /*   1  1   1  1 */
3542                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3543                 break;
3544
3545         default:
3546                 break;
3547         }
3548         if (pause_result & (1<<0))
3549                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3550         if (pause_result & (1<<1))
3551                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3552
3553 }
3554
3555 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3556                                         struct link_params *params,
3557                                         struct link_vars *vars)
3558 {
3559         u16 ld_pause;           /* local */
3560         u16 lp_pause;           /* link partner */
3561         u16 pause_result;
3562         struct bnx2x *bp = params->bp;
3563         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3564                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3565                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3566         } else if (CHIP_IS_E3(bp) &&
3567                 SINGLE_MEDIA_DIRECT(params)) {
3568                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3569                 u16 gp_status, gp_mask;
3570                 bnx2x_cl45_read(bp, phy,
3571                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3572                                 &gp_status);
3573                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3574                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3575                         lane;
3576                 if ((gp_status & gp_mask) == gp_mask) {
3577                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3578                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3579                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3580                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3581                 } else {
3582                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3583                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3584                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3585                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3586                         ld_pause = ((ld_pause &
3587                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3588                                     << 3);
3589                         lp_pause = ((lp_pause &
3590                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3591                                     << 3);
3592                 }
3593         } else {
3594                 bnx2x_cl45_read(bp, phy,
3595                                 MDIO_AN_DEVAD,
3596                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3597                 bnx2x_cl45_read(bp, phy,
3598                                 MDIO_AN_DEVAD,
3599                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3600         }
3601         pause_result = (ld_pause &
3602                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3603         pause_result |= (lp_pause &
3604                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3605         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3606         bnx2x_pause_resolve(vars, pause_result);
3607
3608 }
3609
3610 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3611                                    struct link_params *params,
3612                                    struct link_vars *vars)
3613 {
3614         u8 ret = 0;
3615         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3616         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3617                 /* Update the advertised flow-controled of LD/LP in AN */
3618                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3619                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3620                 /* But set the flow-control result as the requested one */
3621                 vars->flow_ctrl = phy->req_flow_ctrl;
3622         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3623                 vars->flow_ctrl = params->req_fc_auto_adv;
3624         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3625                 ret = 1;
3626                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3627         }
3628         return ret;
3629 }
3630 /******************************************************************/
3631 /*                      Warpcore section                          */
3632 /******************************************************************/
3633 /* The init_internal_warpcore should mirror the xgxs,
3634  * i.e. reset the lane (if needed), set aer for the
3635  * init configuration, and set/clear SGMII flag. Internal
3636  * phy init is done purely in phy_init stage.
3637  */
3638 #define WC_TX_DRIVER(post2, idriver, ipre) \
3639         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3640          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3641          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3642
3643 #define WC_TX_FIR(post, main, pre) \
3644         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3645          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3646          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3647
3648 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3649                                          struct link_params *params,
3650                                          struct link_vars *vars)
3651 {
3652         struct bnx2x *bp = params->bp;
3653         u16 i;
3654         static struct bnx2x_reg_set reg_set[] = {
3655                 /* Step 1 - Program the TX/RX alignment markers */
3656                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3657                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3658                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3659                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3660                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3661                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3662                 /* Step 2 - Configure the NP registers */
3663                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3664                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3665                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3666                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3667                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3668                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3669                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3670                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3671                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3672         };
3673         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3674
3675         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3676                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3677
3678         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3679                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3680                                  reg_set[i].val);
3681
3682         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3683         vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3684         bnx2x_update_link_attr(params, vars->link_attr_sync);
3685 }
3686
3687 static void bnx2x_disable_kr2(struct link_params *params,
3688                               struct link_vars *vars,
3689                               struct bnx2x_phy *phy)
3690 {
3691         struct bnx2x *bp = params->bp;
3692         int i;
3693         static struct bnx2x_reg_set reg_set[] = {
3694                 /* Step 1 - Program the TX/RX alignment markers */
3695                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3696                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3697                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3698                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3699                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3700                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3701                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3702                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3703                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3704                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3705                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3706                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3707                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3708                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3709                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3710         };
3711         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3712
3713         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3714                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3715                                  reg_set[i].val);
3716         vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3717         bnx2x_update_link_attr(params, vars->link_attr_sync);
3718
3719         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3720 }
3721
3722 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3723                                                struct link_params *params)
3724 {
3725         struct bnx2x *bp = params->bp;
3726
3727         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3728         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3729                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3730         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3731                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3732 }
3733
3734 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3735                                          struct link_params *params)
3736 {
3737         /* Restart autoneg on the leading lane only */
3738         struct bnx2x *bp = params->bp;
3739         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3740         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3741                           MDIO_AER_BLOCK_AER_REG, lane);
3742         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3743                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3744
3745         /* Restore AER */
3746         bnx2x_set_aer_mmd(params, phy);
3747 }
3748
3749 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3750                                         struct link_params *params,
3751                                         struct link_vars *vars) {
3752         u16 lane, i, cl72_ctrl, an_adv = 0;
3753         struct bnx2x *bp = params->bp;
3754         static struct bnx2x_reg_set reg_set[] = {
3755                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3756                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3757                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3758                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3759                 /* Disable Autoneg: re-enable it after adv is done. */
3760                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3761                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3762                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3763         };
3764         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3765         /* Set to default registers that may be overriden by 10G force */
3766         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3767                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3768                                  reg_set[i].val);
3769
3770         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3771                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3772         cl72_ctrl &= 0x08ff;
3773         cl72_ctrl |= 0x3800;
3774         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3775                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3776
3777         /* Check adding advertisement for 1G KX */
3778         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3779              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3780             (vars->line_speed == SPEED_1000)) {
3781                 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3782                 an_adv |= (1<<5);
3783
3784                 /* Enable CL37 1G Parallel Detect */
3785                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3786                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3787         }
3788         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3789              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3790             (vars->line_speed ==  SPEED_10000)) {
3791                 /* Check adding advertisement for 10G KR */
3792                 an_adv |= (1<<7);
3793                 /* Enable 10G Parallel Detect */
3794                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3795                                   MDIO_AER_BLOCK_AER_REG, 0);
3796
3797                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3798                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3799                 bnx2x_set_aer_mmd(params, phy);
3800                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3801         }
3802
3803         /* Set Transmit PMD settings */
3804         lane = bnx2x_get_warpcore_lane(phy, params);
3805         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3806                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3807                          WC_TX_DRIVER(0x02, 0x06, 0x09));
3808         /* Configure the next lane if dual mode */
3809         if (phy->flags & FLAGS_WC_DUAL_MODE)
3810                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3811                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3812                                  WC_TX_DRIVER(0x02, 0x06, 0x09));
3813         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3814                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3815                          0x03f0);
3816         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3817                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3818                          0x03f0);
3819
3820         /* Advertised speeds */
3821         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3822                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3823
3824         /* Advertised and set FEC (Forward Error Correction) */
3825         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3826                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3827                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3828                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3829
3830         /* Enable CL37 BAM */
3831         if (REG_RD(bp, params->shmem_base +
3832                    offsetof(struct shmem_region, dev_info.
3833                             port_hw_config[params->port].default_cfg)) &
3834             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3835                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3836                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3837                                          1);
3838                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3839         }
3840
3841         /* Advertise pause */
3842         bnx2x_ext_phy_set_pause(params, phy, vars);
3843         vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3844         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3845                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3846
3847         /* Over 1G - AN local device user page 1 */
3848         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3849                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3850
3851         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3852              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3853             (phy->req_line_speed == SPEED_20000)) {
3854
3855                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3856                                   MDIO_AER_BLOCK_AER_REG, lane);
3857
3858                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3859                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3860                                          (1<<11));
3861
3862                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3863                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3864                 bnx2x_set_aer_mmd(params, phy);
3865
3866                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3867         } else {
3868                 bnx2x_disable_kr2(params, vars, phy);
3869         }
3870
3871         /* Enable Autoneg: only on the main lane */
3872         bnx2x_warpcore_restart_AN_KR(phy, params);
3873 }
3874
3875 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3876                                       struct link_params *params,
3877                                       struct link_vars *vars)
3878 {
3879         struct bnx2x *bp = params->bp;
3880         u16 val16, i, lane;
3881         static struct bnx2x_reg_set reg_set[] = {
3882                 /* Disable Autoneg */
3883                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3884                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3885                         0x3f00},
3886                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3887                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3888                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3889                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3890                 /* Leave cl72 training enable, needed for KR */
3891                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3892         };
3893
3894         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3895                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3896                                  reg_set[i].val);
3897
3898         lane = bnx2x_get_warpcore_lane(phy, params);
3899         /* Global registers */
3900         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3901                           MDIO_AER_BLOCK_AER_REG, 0);
3902         /* Disable CL36 PCS Tx */
3903         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3904                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3905         val16 &= ~(0x0011 << lane);
3906         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3907                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3908
3909         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3910                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3911         val16 |= (0x0303 << (lane << 1));
3912         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3913                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3914         /* Restore AER */
3915         bnx2x_set_aer_mmd(params, phy);
3916         /* Set speed via PMA/PMD register */
3917         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3918                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3919
3920         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3921                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3922
3923         /* Enable encoded forced speed */
3924         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3925                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3926
3927         /* Turn TX scramble payload only the 64/66 scrambler */
3928         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3929                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3930
3931         /* Turn RX scramble payload only the 64/66 scrambler */
3932         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3933                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3934
3935         /* Set and clear loopback to cause a reset to 64/66 decoder */
3936         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3937                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3938         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3939                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3940
3941 }
3942
3943 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3944                                        struct link_params *params,
3945                                        u8 is_xfi)
3946 {
3947         struct bnx2x *bp = params->bp;
3948         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3949         u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3950
3951         /* Hold rxSeqStart */
3952         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3953                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3954
3955         /* Hold tx_fifo_reset */
3956         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3957                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3958
3959         /* Disable CL73 AN */
3960         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3961
3962         /* Disable 100FX Enable and Auto-Detect */
3963         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3964                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3965
3966         /* Disable 100FX Idle detect */
3967         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3968                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3969
3970         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3971         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3972                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3973
3974         /* Turn off auto-detect & fiber mode */
3975         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3976                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3977                                   0xFFEE);
3978
3979         /* Set filter_force_link, disable_false_link and parallel_detect */
3980         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3981                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3982         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3983                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3984                          ((val | 0x0006) & 0xFFFE));
3985
3986         /* Set XFI / SFI */
3987         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3988                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3989
3990         misc1_val &= ~(0x1f);
3991
3992         if (is_xfi) {
3993                 misc1_val |= 0x5;
3994                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3995                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3996         } else {
3997                 cfg_tap_val = REG_RD(bp, params->shmem_base +
3998                                      offsetof(struct shmem_region, dev_info.
3999                                               port_hw_config[params->port].
4000                                               sfi_tap_values));
4001
4002                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4003
4004                 tx_drv_brdct = (cfg_tap_val &
4005                                 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4006                                PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4007
4008                 misc1_val |= 0x9;
4009
4010                 /* TAP values are controlled by nvram, if value there isn't 0 */
4011                 if (tx_equal)
4012                         tap_val = (u16)tx_equal;
4013                 else
4014                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4015
4016                 if (tx_drv_brdct)
4017                         tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
4018                                                      0x06);
4019                 else
4020                         tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
4021         }
4022         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4023                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4024
4025         /* Set Transmit PMD settings */
4026         lane = bnx2x_get_warpcore_lane(phy, params);
4027         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4028                          MDIO_WC_REG_TX_FIR_TAP,
4029                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4030         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4031                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4032                          tx_driver_val);
4033
4034         /* Enable fiber mode, enable and invert sig_det */
4035         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4036                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4037
4038         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4039         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4040                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4041
4042         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4043
4044         /* 10G XFI Full Duplex */
4045         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4046                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4047
4048         /* Release tx_fifo_reset */
4049         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4050                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4051                                   0xFFFE);
4052         /* Release rxSeqStart */
4053         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4054                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4055 }
4056
4057 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4058                                              struct link_params *params)
4059 {
4060         u16 val;
4061         struct bnx2x *bp = params->bp;
4062         /* Set global registers, so set AER lane to 0 */
4063         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4064                           MDIO_AER_BLOCK_AER_REG, 0);
4065
4066         /* Disable sequencer */
4067         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4068                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4069
4070         bnx2x_set_aer_mmd(params, phy);
4071
4072         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4073                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4074         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4075                          MDIO_AN_REG_CTRL, 0);
4076         /* Turn off CL73 */
4077         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4078                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4079         val &= ~(1<<5);
4080         val |= (1<<6);
4081         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4082                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4083
4084         /* Set 20G KR2 force speed */
4085         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4086                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4087
4088         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4089                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4090
4091         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4092                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4093         val &= ~(3<<14);
4094         val |= (1<<15);
4095         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4096                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4097         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4098                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4099
4100         /* Enable sequencer (over lane 0) */
4101         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4102                           MDIO_AER_BLOCK_AER_REG, 0);
4103
4104         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4105                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4106
4107         bnx2x_set_aer_mmd(params, phy);
4108 }
4109
4110 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4111                                          struct bnx2x_phy *phy,
4112                                          u16 lane)
4113 {
4114         /* Rx0 anaRxControl1G */
4115         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4116                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4117
4118         /* Rx2 anaRxControl1G */
4119         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4120                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4121
4122         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4123                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4124
4125         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4126                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4127
4128         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4129                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4130
4131         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4132                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4133
4134         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4135                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4136
4137         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4138                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4139
4140         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4141                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4142
4143         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4144                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4145
4146         /* Serdes Digital Misc1 */
4147         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4148                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4149
4150         /* Serdes Digital4 Misc3 */
4151         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4152                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4153
4154         /* Set Transmit PMD settings */
4155         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4156                          MDIO_WC_REG_TX_FIR_TAP,
4157                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
4158                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4159         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4160                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4161                          WC_TX_DRIVER(0x02, 0x02, 0x02));
4162 }
4163
4164 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4165                                            struct link_params *params,
4166                                            u8 fiber_mode,
4167                                            u8 always_autoneg)
4168 {
4169         struct bnx2x *bp = params->bp;
4170         u16 val16, digctrl_kx1, digctrl_kx2;
4171
4172         /* Clear XFI clock comp in non-10G single lane mode. */
4173         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4174                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4175
4176         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4177
4178         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4179                 /* SGMII Autoneg */
4180                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4181                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4182                                          0x1000);
4183                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4184         } else {
4185                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4186                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4187                 val16 &= 0xcebf;
4188                 switch (phy->req_line_speed) {
4189                 case SPEED_10:
4190                         break;
4191                 case SPEED_100:
4192                         val16 |= 0x2000;
4193                         break;
4194                 case SPEED_1000:
4195                         val16 |= 0x0040;
4196                         break;
4197                 default:
4198                         DP(NETIF_MSG_LINK,
4199                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4200                         return;
4201                 }
4202
4203                 if (phy->req_duplex == DUPLEX_FULL)
4204                         val16 |= 0x0100;
4205
4206                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4207                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4208
4209                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4210                                phy->req_line_speed);
4211                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4212                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4213                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4214         }
4215
4216         /* SGMII Slave mode and disable signal detect */
4217         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4218                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4219         if (fiber_mode)
4220                 digctrl_kx1 = 1;
4221         else
4222                 digctrl_kx1 &= 0xff4a;
4223
4224         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4225                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4226                         digctrl_kx1);
4227
4228         /* Turn off parallel detect */
4229         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4230                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4231         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4232                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4233                         (digctrl_kx2 & ~(1<<2)));
4234
4235         /* Re-enable parallel detect */
4236         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4237                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4238                         (digctrl_kx2 | (1<<2)));
4239
4240         /* Enable autodet */
4241         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4242                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4243                         (digctrl_kx1 | 0x10));
4244 }
4245
4246 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4247                                       struct bnx2x_phy *phy,
4248                                       u8 reset)
4249 {
4250         u16 val;
4251         /* Take lane out of reset after configuration is finished */
4252         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4253                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4254         if (reset)
4255                 val |= 0xC000;
4256         else
4257                 val &= 0x3FFF;
4258         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4259                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4260         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4261                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4262 }
4263 /* Clear SFI/XFI link settings registers */
4264 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4265                                       struct link_params *params,
4266                                       u16 lane)
4267 {
4268         struct bnx2x *bp = params->bp;
4269         u16 i;
4270         static struct bnx2x_reg_set wc_regs[] = {
4271                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4272                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4273                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4274                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4275                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4276                         0x0195},
4277                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4278                         0x0007},
4279                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4280                         0x0002},
4281                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4282                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4283                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4284                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4285         };
4286         /* Set XFI clock comp as default. */
4287         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4288                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4289
4290         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4291                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4292                                  wc_regs[i].val);
4293
4294         lane = bnx2x_get_warpcore_lane(phy, params);
4295         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4296                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4297
4298 }
4299
4300 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4301                                                 u32 chip_id,
4302                                                 u32 shmem_base, u8 port,
4303                                                 u8 *gpio_num, u8 *gpio_port)
4304 {
4305         u32 cfg_pin;
4306         *gpio_num = 0;
4307         *gpio_port = 0;
4308         if (CHIP_IS_E3(bp)) {
4309                 cfg_pin = (REG_RD(bp, shmem_base +
4310                                 offsetof(struct shmem_region,
4311                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4312                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4313                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4314
4315                 /* Should not happen. This function called upon interrupt
4316                  * triggered by GPIO ( since EPIO can only generate interrupts
4317                  * to MCP).
4318                  * So if this function was called and none of the GPIOs was set,
4319                  * it means the shit hit the fan.
4320                  */
4321                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4322                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4323                         DP(NETIF_MSG_LINK,
4324                            "No cfg pin %x for module detect indication\n",
4325                            cfg_pin);
4326                         return -EINVAL;
4327                 }
4328
4329                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4330                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4331         } else {
4332                 *gpio_num = MISC_REGISTERS_GPIO_3;
4333                 *gpio_port = port;
4334         }
4335
4336         return 0;
4337 }
4338
4339 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4340                                        struct link_params *params)
4341 {
4342         struct bnx2x *bp = params->bp;
4343         u8 gpio_num, gpio_port;
4344         u32 gpio_val;
4345         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4346                                       params->shmem_base, params->port,
4347                                       &gpio_num, &gpio_port) != 0)
4348                 return 0;
4349         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4350
4351         /* Call the handling function in case module is detected */
4352         if (gpio_val == 0)
4353                 return 1;
4354         else
4355                 return 0;
4356 }
4357 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4358                                      struct link_params *params)
4359 {
4360         u16 gp2_status_reg0, lane;
4361         struct bnx2x *bp = params->bp;
4362
4363         lane = bnx2x_get_warpcore_lane(phy, params);
4364
4365         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4366                                  &gp2_status_reg0);
4367
4368         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4369 }
4370
4371 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4372                                           struct link_params *params,
4373                                           struct link_vars *vars)
4374 {
4375         struct bnx2x *bp = params->bp;
4376         u32 serdes_net_if;
4377         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4378
4379         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4380
4381         if (!vars->turn_to_run_wc_rt)
4382                 return;
4383
4384         if (vars->rx_tx_asic_rst) {
4385                 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4386                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4387                                 offsetof(struct shmem_region, dev_info.
4388                                 port_hw_config[params->port].default_cfg)) &
4389                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4390
4391                 switch (serdes_net_if) {
4392                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4393                         /* Do we get link yet? */
4394                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4395                                         &gp_status1);
4396                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4397                                 /*10G KR*/
4398                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4399
4400                         if (lnkup_kr || lnkup) {
4401                                 vars->rx_tx_asic_rst = 0;
4402                         } else {
4403                                 /* Reset the lane to see if link comes up.*/
4404                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4405                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4406
4407                                 /* Restart Autoneg */
4408                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4409                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4410
4411                                 vars->rx_tx_asic_rst--;
4412                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4413                                 vars->rx_tx_asic_rst);
4414                         }
4415                         break;
4416
4417                 default:
4418                         break;
4419                 }
4420
4421         } /*params->rx_tx_asic_rst*/
4422
4423 }
4424 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4425                                       struct link_params *params)
4426 {
4427         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4428         struct bnx2x *bp = params->bp;
4429         bnx2x_warpcore_clear_regs(phy, params, lane);
4430         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4431              SPEED_10000) &&
4432             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4433                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4434                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4435         } else {
4436                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4437                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4438         }
4439 }
4440
4441 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4442                                          struct bnx2x_phy *phy,
4443                                          u8 tx_en)
4444 {
4445         struct bnx2x *bp = params->bp;
4446         u32 cfg_pin;
4447         u8 port = params->port;
4448
4449         cfg_pin = REG_RD(bp, params->shmem_base +
4450                          offsetof(struct shmem_region,
4451                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4452                 PORT_HW_CFG_E3_TX_LASER_MASK;
4453         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4454         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4455
4456         /* For 20G, the expected pin to be used is 3 pins after the current */
4457         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4458         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4459                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4460 }
4461
4462 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4463                                        struct link_params *params,
4464                                        struct link_vars *vars)
4465 {
4466         struct bnx2x *bp = params->bp;
4467         u32 serdes_net_if;
4468         u8 fiber_mode;
4469         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4470         serdes_net_if = (REG_RD(bp, params->shmem_base +
4471                          offsetof(struct shmem_region, dev_info.
4472                                   port_hw_config[params->port].default_cfg)) &
4473                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4474         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4475                            "serdes_net_if = 0x%x\n",
4476                        vars->line_speed, serdes_net_if);
4477         bnx2x_set_aer_mmd(params, phy);
4478         bnx2x_warpcore_reset_lane(bp, phy, 1);
4479         vars->phy_flags |= PHY_XGXS_FLAG;
4480         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4481             (phy->req_line_speed &&
4482              ((phy->req_line_speed == SPEED_100) ||
4483               (phy->req_line_speed == SPEED_10)))) {
4484                 vars->phy_flags |= PHY_SGMII_FLAG;
4485                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4486                 bnx2x_warpcore_clear_regs(phy, params, lane);
4487                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4488         } else {
4489                 switch (serdes_net_if) {
4490                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4491                         /* Enable KR Auto Neg */
4492                         if (params->loopback_mode != LOOPBACK_EXT)
4493                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4494                         else {
4495                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4496                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4497                         }
4498                         break;
4499
4500                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4501                         bnx2x_warpcore_clear_regs(phy, params, lane);
4502                         if (vars->line_speed == SPEED_10000) {
4503                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4504                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4505                         } else {
4506                                 if (SINGLE_MEDIA_DIRECT(params)) {
4507                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4508                                         fiber_mode = 1;
4509                                 } else {
4510                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4511                                         fiber_mode = 0;
4512                                 }
4513                                 bnx2x_warpcore_set_sgmii_speed(phy,
4514                                                                 params,
4515                                                                 fiber_mode,
4516                                                                 0);
4517                         }
4518
4519                         break;
4520
4521                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4522                         /* Issue Module detection if module is plugged, or
4523                          * enabled transmitter to avoid current leakage in case
4524                          * no module is connected
4525                          */
4526                         if (bnx2x_is_sfp_module_plugged(phy, params))
4527                                 bnx2x_sfp_module_detection(phy, params);
4528                         else
4529                                 bnx2x_sfp_e3_set_transmitter(params, phy, 1);
4530
4531                         bnx2x_warpcore_config_sfi(phy, params);
4532                         break;
4533
4534                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4535                         if (vars->line_speed != SPEED_20000) {
4536                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4537                                 return;
4538                         }
4539                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4540                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4541                         /* Issue Module detection */
4542
4543                         bnx2x_sfp_module_detection(phy, params);
4544                         break;
4545                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4546                         if (!params->loopback_mode) {
4547                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4548                         } else {
4549                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4550                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4551                         }
4552                         break;
4553                 default:
4554                         DP(NETIF_MSG_LINK,
4555                            "Unsupported Serdes Net Interface 0x%x\n",
4556                            serdes_net_if);
4557                         return;
4558                 }
4559         }
4560
4561         /* Take lane out of reset after configuration is finished */
4562         bnx2x_warpcore_reset_lane(bp, phy, 0);
4563         DP(NETIF_MSG_LINK, "Exit config init\n");
4564 }
4565
4566 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4567                                       struct link_params *params)
4568 {
4569         struct bnx2x *bp = params->bp;
4570         u16 val16, lane;
4571         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4572         bnx2x_set_mdio_emac_per_phy(bp, params);
4573         bnx2x_set_aer_mmd(params, phy);
4574         /* Global register */
4575         bnx2x_warpcore_reset_lane(bp, phy, 1);
4576
4577         /* Clear loopback settings (if any) */
4578         /* 10G & 20G */
4579         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4580                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4581
4582         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4583                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4584
4585         /* Update those 1-copy registers */
4586         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4587                           MDIO_AER_BLOCK_AER_REG, 0);
4588         /* Enable 1G MDIO (1-copy) */
4589         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4590                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4591                                   ~0x10);
4592
4593         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4594                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4595         lane = bnx2x_get_warpcore_lane(phy, params);
4596         /* Disable CL36 PCS Tx */
4597         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4598                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4599         val16 |= (0x11 << lane);
4600         if (phy->flags & FLAGS_WC_DUAL_MODE)
4601                 val16 |= (0x22 << lane);
4602         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4603                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4604
4605         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4606                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4607         val16 &= ~(0x0303 << (lane << 1));
4608         val16 |= (0x0101 << (lane << 1));
4609         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4610                 val16 &= ~(0x0c0c << (lane << 1));
4611                 val16 |= (0x0404 << (lane << 1));
4612         }
4613
4614         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4615                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4616         /* Restore AER */
4617         bnx2x_set_aer_mmd(params, phy);
4618
4619 }
4620
4621 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4622                                         struct link_params *params)
4623 {
4624         struct bnx2x *bp = params->bp;
4625         u16 val16;
4626         u32 lane;
4627         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4628                        params->loopback_mode, phy->req_line_speed);
4629
4630         if (phy->req_line_speed < SPEED_10000 ||
4631             phy->supported & SUPPORTED_20000baseKR2_Full) {
4632                 /* 10/100/1000/20G-KR2 */
4633
4634                 /* Update those 1-copy registers */
4635                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4636                                   MDIO_AER_BLOCK_AER_REG, 0);
4637                 /* Enable 1G MDIO (1-copy) */
4638                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4639                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4640                                          0x10);
4641                 /* Set 1G loopback based on lane (1-copy) */
4642                 lane = bnx2x_get_warpcore_lane(phy, params);
4643                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4644                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4645                 val16 |= (1<<lane);
4646                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4647                         val16 |= (2<<lane);
4648                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4649                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4650                                  val16);
4651
4652                 /* Switch back to 4-copy registers */
4653                 bnx2x_set_aer_mmd(params, phy);
4654         } else {
4655                 /* 10G / 20G-DXGXS */
4656                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4657                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4658                                          0x4000);
4659                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4660                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4661         }
4662 }
4663
4664
4665
4666 static void bnx2x_sync_link(struct link_params *params,
4667                              struct link_vars *vars)
4668 {
4669         struct bnx2x *bp = params->bp;
4670         u8 link_10g_plus;
4671         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4672                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4673         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4674         if (vars->link_up) {
4675                 DP(NETIF_MSG_LINK, "phy link up\n");
4676
4677                 vars->phy_link_up = 1;
4678                 vars->duplex = DUPLEX_FULL;
4679                 switch (vars->link_status &
4680                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4681                 case LINK_10THD:
4682                         vars->duplex = DUPLEX_HALF;
4683                         /* Fall thru */
4684                 case LINK_10TFD:
4685                         vars->line_speed = SPEED_10;
4686                         break;
4687
4688                 case LINK_100TXHD:
4689                         vars->duplex = DUPLEX_HALF;
4690                         /* Fall thru */
4691                 case LINK_100T4:
4692                 case LINK_100TXFD:
4693                         vars->line_speed = SPEED_100;
4694                         break;
4695
4696                 case LINK_1000THD:
4697                         vars->duplex = DUPLEX_HALF;
4698                         /* Fall thru */
4699                 case LINK_1000TFD:
4700                         vars->line_speed = SPEED_1000;
4701                         break;
4702
4703                 case LINK_2500THD:
4704                         vars->duplex = DUPLEX_HALF;
4705                         /* Fall thru */
4706                 case LINK_2500TFD:
4707                         vars->line_speed = SPEED_2500;
4708                         break;
4709
4710                 case LINK_10GTFD:
4711                         vars->line_speed = SPEED_10000;
4712                         break;
4713                 case LINK_20GTFD:
4714                         vars->line_speed = SPEED_20000;
4715                         break;
4716                 default:
4717                         break;
4718                 }
4719                 vars->flow_ctrl = 0;
4720                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4721                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4722
4723                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4724                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4725
4726                 if (!vars->flow_ctrl)
4727                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4728
4729                 if (vars->line_speed &&
4730                     ((vars->line_speed == SPEED_10) ||
4731                      (vars->line_speed == SPEED_100))) {
4732                         vars->phy_flags |= PHY_SGMII_FLAG;
4733                 } else {
4734                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4735                 }
4736                 if (vars->line_speed &&
4737                     USES_WARPCORE(bp) &&
4738                     (vars->line_speed == SPEED_1000))
4739                         vars->phy_flags |= PHY_SGMII_FLAG;
4740                 /* Anything 10 and over uses the bmac */
4741                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4742
4743                 if (link_10g_plus) {
4744                         if (USES_WARPCORE(bp))
4745                                 vars->mac_type = MAC_TYPE_XMAC;
4746                         else
4747                                 vars->mac_type = MAC_TYPE_BMAC;
4748                 } else {
4749                         if (USES_WARPCORE(bp))
4750                                 vars->mac_type = MAC_TYPE_UMAC;
4751                         else
4752                                 vars->mac_type = MAC_TYPE_EMAC;
4753                 }
4754         } else { /* Link down */
4755                 DP(NETIF_MSG_LINK, "phy link down\n");
4756
4757                 vars->phy_link_up = 0;
4758
4759                 vars->line_speed = 0;
4760                 vars->duplex = DUPLEX_FULL;
4761                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4762
4763                 /* Indicate no mac active */
4764                 vars->mac_type = MAC_TYPE_NONE;
4765                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4766                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4767                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4768                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4769         }
4770 }
4771
4772 void bnx2x_link_status_update(struct link_params *params,
4773                               struct link_vars *vars)
4774 {
4775         struct bnx2x *bp = params->bp;
4776         u8 port = params->port;
4777         u32 sync_offset, media_types;
4778         /* Update PHY configuration */
4779         set_phy_vars(params, vars);
4780
4781         vars->link_status = REG_RD(bp, params->shmem_base +
4782                                    offsetof(struct shmem_region,
4783                                             port_mb[port].link_status));
4784
4785         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4786         if (params->loopback_mode != LOOPBACK_NONE &&
4787             params->loopback_mode != LOOPBACK_EXT)
4788                 vars->link_status |= LINK_STATUS_LINK_UP;
4789
4790         if (bnx2x_eee_has_cap(params))
4791                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4792                                           offsetof(struct shmem2_region,
4793                                                    eee_status[params->port]));
4794
4795         vars->phy_flags = PHY_XGXS_FLAG;
4796         bnx2x_sync_link(params, vars);
4797         /* Sync media type */
4798         sync_offset = params->shmem_base +
4799                         offsetof(struct shmem_region,
4800                                  dev_info.port_hw_config[port].media_type);
4801         media_types = REG_RD(bp, sync_offset);
4802
4803         params->phy[INT_PHY].media_type =
4804                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4805                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4806         params->phy[EXT_PHY1].media_type =
4807                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4808                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4809         params->phy[EXT_PHY2].media_type =
4810                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4811                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4812         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4813
4814         /* Sync AEU offset */
4815         sync_offset = params->shmem_base +
4816                         offsetof(struct shmem_region,
4817                                  dev_info.port_hw_config[port].aeu_int_mask);
4818
4819         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4820
4821         /* Sync PFC status */
4822         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4823                 params->feature_config_flags |=
4824                                         FEATURE_CONFIG_PFC_ENABLED;
4825         else
4826                 params->feature_config_flags &=
4827                                         ~FEATURE_CONFIG_PFC_ENABLED;
4828
4829         if (SHMEM2_HAS(bp, link_attr_sync))
4830                 vars->link_attr_sync = SHMEM2_RD(bp,
4831                                                  link_attr_sync[params->port]);
4832
4833         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4834                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4835         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4836                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4837 }
4838
4839 static void bnx2x_set_master_ln(struct link_params *params,
4840                                 struct bnx2x_phy *phy)
4841 {
4842         struct bnx2x *bp = params->bp;
4843         u16 new_master_ln, ser_lane;
4844         ser_lane = ((params->lane_config &
4845                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4846                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4847
4848         /* Set the master_ln for AN */
4849         CL22_RD_OVER_CL45(bp, phy,
4850                           MDIO_REG_BANK_XGXS_BLOCK2,
4851                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4852                           &new_master_ln);
4853
4854         CL22_WR_OVER_CL45(bp, phy,
4855                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4856                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4857                           (new_master_ln | ser_lane));
4858 }
4859
4860 static int bnx2x_reset_unicore(struct link_params *params,
4861                                struct bnx2x_phy *phy,
4862                                u8 set_serdes)
4863 {
4864         struct bnx2x *bp = params->bp;
4865         u16 mii_control;
4866         u16 i;
4867         CL22_RD_OVER_CL45(bp, phy,
4868                           MDIO_REG_BANK_COMBO_IEEE0,
4869                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4870
4871         /* Reset the unicore */
4872         CL22_WR_OVER_CL45(bp, phy,
4873                           MDIO_REG_BANK_COMBO_IEEE0,
4874                           MDIO_COMBO_IEEE0_MII_CONTROL,
4875                           (mii_control |
4876                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4877         if (set_serdes)
4878                 bnx2x_set_serdes_access(bp, params->port);
4879
4880         /* Wait for the reset to self clear */
4881         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4882                 udelay(5);
4883
4884                 /* The reset erased the previous bank value */
4885                 CL22_RD_OVER_CL45(bp, phy,
4886                                   MDIO_REG_BANK_COMBO_IEEE0,
4887                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4888                                   &mii_control);
4889
4890                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4891                         udelay(5);
4892                         return 0;
4893                 }
4894         }
4895
4896         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4897                               " Port %d\n",
4898                          params->port);
4899         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4900         return -EINVAL;
4901
4902 }
4903
4904 static void bnx2x_set_swap_lanes(struct link_params *params,
4905                                  struct bnx2x_phy *phy)
4906 {
4907         struct bnx2x *bp = params->bp;
4908         /* Each two bits represents a lane number:
4909          * No swap is 0123 => 0x1b no need to enable the swap
4910          */
4911         u16 rx_lane_swap, tx_lane_swap;
4912
4913         rx_lane_swap = ((params->lane_config &
4914                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4915                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4916         tx_lane_swap = ((params->lane_config &
4917                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4918                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4919
4920         if (rx_lane_swap != 0x1b) {
4921                 CL22_WR_OVER_CL45(bp, phy,
4922                                   MDIO_REG_BANK_XGXS_BLOCK2,
4923                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4924                                   (rx_lane_swap |
4925                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4926                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4927         } else {
4928                 CL22_WR_OVER_CL45(bp, phy,
4929                                   MDIO_REG_BANK_XGXS_BLOCK2,
4930                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4931         }
4932
4933         if (tx_lane_swap != 0x1b) {
4934                 CL22_WR_OVER_CL45(bp, phy,
4935                                   MDIO_REG_BANK_XGXS_BLOCK2,
4936                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4937                                   (tx_lane_swap |
4938                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4939         } else {
4940                 CL22_WR_OVER_CL45(bp, phy,
4941                                   MDIO_REG_BANK_XGXS_BLOCK2,
4942                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4943         }
4944 }
4945
4946 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4947                                          struct link_params *params)
4948 {
4949         struct bnx2x *bp = params->bp;
4950         u16 control2;
4951         CL22_RD_OVER_CL45(bp, phy,
4952                           MDIO_REG_BANK_SERDES_DIGITAL,
4953                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4954                           &control2);
4955         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4956                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4957         else
4958                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4959         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4960                 phy->speed_cap_mask, control2);
4961         CL22_WR_OVER_CL45(bp, phy,
4962                           MDIO_REG_BANK_SERDES_DIGITAL,
4963                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4964                           control2);
4965
4966         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4967              (phy->speed_cap_mask &
4968                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4969                 DP(NETIF_MSG_LINK, "XGXS\n");
4970
4971                 CL22_WR_OVER_CL45(bp, phy,
4972                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4973                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4974                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4975
4976                 CL22_RD_OVER_CL45(bp, phy,
4977                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4978                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4979                                   &control2);
4980
4981
4982                 control2 |=
4983                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4984
4985                 CL22_WR_OVER_CL45(bp, phy,
4986                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4987                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4988                                   control2);
4989
4990                 /* Disable parallel detection of HiG */
4991                 CL22_WR_OVER_CL45(bp, phy,
4992                                   MDIO_REG_BANK_XGXS_BLOCK2,
4993                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4994                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4995                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4996         }
4997 }
4998
4999 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5000                               struct link_params *params,
5001                               struct link_vars *vars,
5002                               u8 enable_cl73)
5003 {
5004         struct bnx2x *bp = params->bp;
5005         u16 reg_val;
5006
5007         /* CL37 Autoneg */
5008         CL22_RD_OVER_CL45(bp, phy,
5009                           MDIO_REG_BANK_COMBO_IEEE0,
5010                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5011
5012         /* CL37 Autoneg Enabled */
5013         if (vars->line_speed == SPEED_AUTO_NEG)
5014                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5015         else /* CL37 Autoneg Disabled */
5016                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5017                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5018
5019         CL22_WR_OVER_CL45(bp, phy,
5020                           MDIO_REG_BANK_COMBO_IEEE0,
5021                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5022
5023         /* Enable/Disable Autodetection */
5024
5025         CL22_RD_OVER_CL45(bp, phy,
5026                           MDIO_REG_BANK_SERDES_DIGITAL,
5027                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5028         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5029                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5030         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5031         if (vars->line_speed == SPEED_AUTO_NEG)
5032                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5033         else
5034                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5035
5036         CL22_WR_OVER_CL45(bp, phy,
5037                           MDIO_REG_BANK_SERDES_DIGITAL,
5038                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5039
5040         /* Enable TetonII and BAM autoneg */
5041         CL22_RD_OVER_CL45(bp, phy,
5042                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5043                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5044                           &reg_val);
5045         if (vars->line_speed == SPEED_AUTO_NEG) {
5046                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5047                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5048                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5049         } else {
5050                 /* TetonII and BAM Autoneg Disabled */
5051                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5052                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5053         }
5054         CL22_WR_OVER_CL45(bp, phy,
5055                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5056                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5057                           reg_val);
5058
5059         if (enable_cl73) {
5060                 /* Enable Cl73 FSM status bits */
5061                 CL22_WR_OVER_CL45(bp, phy,
5062                                   MDIO_REG_BANK_CL73_USERB0,
5063                                   MDIO_CL73_USERB0_CL73_UCTRL,
5064                                   0xe);
5065
5066                 /* Enable BAM Station Manager*/
5067                 CL22_WR_OVER_CL45(bp, phy,
5068                         MDIO_REG_BANK_CL73_USERB0,
5069                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5070                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5071                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5072                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5073
5074                 /* Advertise CL73 link speeds */
5075                 CL22_RD_OVER_CL45(bp, phy,
5076                                   MDIO_REG_BANK_CL73_IEEEB1,
5077                                   MDIO_CL73_IEEEB1_AN_ADV2,
5078                                   &reg_val);
5079                 if (phy->speed_cap_mask &
5080                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5081                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5082                 if (phy->speed_cap_mask &
5083                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5084                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5085
5086                 CL22_WR_OVER_CL45(bp, phy,
5087                                   MDIO_REG_BANK_CL73_IEEEB1,
5088                                   MDIO_CL73_IEEEB1_AN_ADV2,
5089                                   reg_val);
5090
5091                 /* CL73 Autoneg Enabled */
5092                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5093
5094         } else /* CL73 Autoneg Disabled */
5095                 reg_val = 0;
5096
5097         CL22_WR_OVER_CL45(bp, phy,
5098                           MDIO_REG_BANK_CL73_IEEEB0,
5099                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5100 }
5101
5102 /* Program SerDes, forced speed */
5103 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5104                                  struct link_params *params,
5105                                  struct link_vars *vars)
5106 {
5107         struct bnx2x *bp = params->bp;
5108         u16 reg_val;
5109
5110         /* Program duplex, disable autoneg and sgmii*/
5111         CL22_RD_OVER_CL45(bp, phy,
5112                           MDIO_REG_BANK_COMBO_IEEE0,
5113                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5114         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5115                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5116                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5117         if (phy->req_duplex == DUPLEX_FULL)
5118                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5119         CL22_WR_OVER_CL45(bp, phy,
5120                           MDIO_REG_BANK_COMBO_IEEE0,
5121                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5122
5123         /* Program speed
5124          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5125          */
5126         CL22_RD_OVER_CL45(bp, phy,
5127                           MDIO_REG_BANK_SERDES_DIGITAL,
5128                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5129         /* Clearing the speed value before setting the right speed */
5130         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5131
5132         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5133                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5134
5135         if (!((vars->line_speed == SPEED_1000) ||
5136               (vars->line_speed == SPEED_100) ||
5137               (vars->line_speed == SPEED_10))) {
5138
5139                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5140                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5141                 if (vars->line_speed == SPEED_10000)
5142                         reg_val |=
5143                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5144         }
5145
5146         CL22_WR_OVER_CL45(bp, phy,
5147                           MDIO_REG_BANK_SERDES_DIGITAL,
5148                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5149
5150 }
5151
5152 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5153                                               struct link_params *params)
5154 {
5155         struct bnx2x *bp = params->bp;
5156         u16 val = 0;
5157
5158         /* Set extended capabilities */
5159         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5160                 val |= MDIO_OVER_1G_UP1_2_5G;
5161         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5162                 val |= MDIO_OVER_1G_UP1_10G;
5163         CL22_WR_OVER_CL45(bp, phy,
5164                           MDIO_REG_BANK_OVER_1G,
5165                           MDIO_OVER_1G_UP1, val);
5166
5167         CL22_WR_OVER_CL45(bp, phy,
5168                           MDIO_REG_BANK_OVER_1G,
5169                           MDIO_OVER_1G_UP3, 0x400);
5170 }
5171
5172 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5173                                               struct link_params *params,
5174                                               u16 ieee_fc)
5175 {
5176         struct bnx2x *bp = params->bp;
5177         u16 val;
5178         /* For AN, we are always publishing full duplex */
5179
5180         CL22_WR_OVER_CL45(bp, phy,
5181                           MDIO_REG_BANK_COMBO_IEEE0,
5182                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5183         CL22_RD_OVER_CL45(bp, phy,
5184                           MDIO_REG_BANK_CL73_IEEEB1,
5185                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5186         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5187         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5188         CL22_WR_OVER_CL45(bp, phy,
5189                           MDIO_REG_BANK_CL73_IEEEB1,
5190                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5191 }
5192
5193 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5194                                   struct link_params *params,
5195                                   u8 enable_cl73)
5196 {
5197         struct bnx2x *bp = params->bp;
5198         u16 mii_control;
5199
5200         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5201         /* Enable and restart BAM/CL37 aneg */
5202
5203         if (enable_cl73) {
5204                 CL22_RD_OVER_CL45(bp, phy,
5205                                   MDIO_REG_BANK_CL73_IEEEB0,
5206                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5207                                   &mii_control);
5208
5209                 CL22_WR_OVER_CL45(bp, phy,
5210                                   MDIO_REG_BANK_CL73_IEEEB0,
5211                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5212                                   (mii_control |
5213                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5214                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5215         } else {
5216
5217                 CL22_RD_OVER_CL45(bp, phy,
5218                                   MDIO_REG_BANK_COMBO_IEEE0,
5219                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5220                                   &mii_control);
5221                 DP(NETIF_MSG_LINK,
5222                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5223                          mii_control);
5224                 CL22_WR_OVER_CL45(bp, phy,
5225                                   MDIO_REG_BANK_COMBO_IEEE0,
5226                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5227                                   (mii_control |
5228                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5229                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5230         }
5231 }
5232
5233 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5234                                            struct link_params *params,
5235                                            struct link_vars *vars)
5236 {
5237         struct bnx2x *bp = params->bp;
5238         u16 control1;
5239
5240         /* In SGMII mode, the unicore is always slave */
5241
5242         CL22_RD_OVER_CL45(bp, phy,
5243                           MDIO_REG_BANK_SERDES_DIGITAL,
5244                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5245                           &control1);
5246         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5247         /* Set sgmii mode (and not fiber) */
5248         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5249                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5250                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5251         CL22_WR_OVER_CL45(bp, phy,
5252                           MDIO_REG_BANK_SERDES_DIGITAL,
5253                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5254                           control1);
5255
5256         /* If forced speed */
5257         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5258                 /* Set speed, disable autoneg */
5259                 u16 mii_control;
5260
5261                 CL22_RD_OVER_CL45(bp, phy,
5262                                   MDIO_REG_BANK_COMBO_IEEE0,
5263                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5264                                   &mii_control);
5265                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5266                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5267                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5268
5269                 switch (vars->line_speed) {
5270                 case SPEED_100:
5271                         mii_control |=
5272                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5273                         break;
5274                 case SPEED_1000:
5275                         mii_control |=
5276                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5277                         break;
5278                 case SPEED_10:
5279                         /* There is nothing to set for 10M */
5280                         break;
5281                 default:
5282                         /* Invalid speed for SGMII */
5283                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5284                                   vars->line_speed);
5285                         break;
5286                 }
5287
5288                 /* Setting the full duplex */
5289                 if (phy->req_duplex == DUPLEX_FULL)
5290                         mii_control |=
5291                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5292                 CL22_WR_OVER_CL45(bp, phy,
5293                                   MDIO_REG_BANK_COMBO_IEEE0,
5294                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5295                                   mii_control);
5296
5297         } else { /* AN mode */
5298                 /* Enable and restart AN */
5299                 bnx2x_restart_autoneg(phy, params, 0);
5300         }
5301 }
5302
5303 /* Link management
5304  */
5305 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5306                                              struct link_params *params)
5307 {
5308         struct bnx2x *bp = params->bp;
5309         u16 pd_10g, status2_1000x;
5310         if (phy->req_line_speed != SPEED_AUTO_NEG)
5311                 return 0;
5312         CL22_RD_OVER_CL45(bp, phy,
5313                           MDIO_REG_BANK_SERDES_DIGITAL,
5314                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5315                           &status2_1000x);
5316         CL22_RD_OVER_CL45(bp, phy,
5317                           MDIO_REG_BANK_SERDES_DIGITAL,
5318                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5319                           &status2_1000x);
5320         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5321                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5322                          params->port);
5323                 return 1;
5324         }
5325
5326         CL22_RD_OVER_CL45(bp, phy,
5327                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5328                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5329                           &pd_10g);
5330
5331         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5332                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5333                          params->port);
5334                 return 1;
5335         }
5336         return 0;
5337 }
5338
5339 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5340                                 struct link_params *params,
5341                                 struct link_vars *vars,
5342                                 u32 gp_status)
5343 {
5344         u16 ld_pause;   /* local driver */
5345         u16 lp_pause;   /* link partner */
5346         u16 pause_result;
5347         struct bnx2x *bp = params->bp;
5348         if ((gp_status &
5349              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5350               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5351             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5352              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5353
5354                 CL22_RD_OVER_CL45(bp, phy,
5355                                   MDIO_REG_BANK_CL73_IEEEB1,
5356                                   MDIO_CL73_IEEEB1_AN_ADV1,
5357                                   &ld_pause);
5358                 CL22_RD_OVER_CL45(bp, phy,
5359                                   MDIO_REG_BANK_CL73_IEEEB1,
5360                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5361                                   &lp_pause);
5362                 pause_result = (ld_pause &
5363                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5364                 pause_result |= (lp_pause &
5365                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5366                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5367         } else {
5368                 CL22_RD_OVER_CL45(bp, phy,
5369                                   MDIO_REG_BANK_COMBO_IEEE0,
5370                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5371                                   &ld_pause);
5372                 CL22_RD_OVER_CL45(bp, phy,
5373                         MDIO_REG_BANK_COMBO_IEEE0,
5374                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5375                         &lp_pause);
5376                 pause_result = (ld_pause &
5377                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5378                 pause_result |= (lp_pause &
5379                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5380                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5381         }
5382         bnx2x_pause_resolve(vars, pause_result);
5383
5384 }
5385
5386 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5387                                     struct link_params *params,
5388                                     struct link_vars *vars,
5389                                     u32 gp_status)
5390 {
5391         struct bnx2x *bp = params->bp;
5392         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5393
5394         /* Resolve from gp_status in case of AN complete and not sgmii */
5395         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5396                 /* Update the advertised flow-controled of LD/LP in AN */
5397                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5398                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5399                 /* But set the flow-control result as the requested one */
5400                 vars->flow_ctrl = phy->req_flow_ctrl;
5401         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5402                 vars->flow_ctrl = params->req_fc_auto_adv;
5403         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5404                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5405                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5406                         vars->flow_ctrl = params->req_fc_auto_adv;
5407                         return;
5408                 }
5409                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5410         }
5411         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5412 }
5413
5414 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5415                                          struct link_params *params)
5416 {
5417         struct bnx2x *bp = params->bp;
5418         u16 rx_status, ustat_val, cl37_fsm_received;
5419         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5420         /* Step 1: Make sure signal is detected */
5421         CL22_RD_OVER_CL45(bp, phy,
5422                           MDIO_REG_BANK_RX0,
5423                           MDIO_RX0_RX_STATUS,
5424                           &rx_status);
5425         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5426             (MDIO_RX0_RX_STATUS_SIGDET)) {
5427                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5428                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5429                 CL22_WR_OVER_CL45(bp, phy,
5430                                   MDIO_REG_BANK_CL73_IEEEB0,
5431                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5432                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5433                 return;
5434         }
5435         /* Step 2: Check CL73 state machine */
5436         CL22_RD_OVER_CL45(bp, phy,
5437                           MDIO_REG_BANK_CL73_USERB0,
5438                           MDIO_CL73_USERB0_CL73_USTAT1,
5439                           &ustat_val);
5440         if ((ustat_val &
5441              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5442               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5443             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5444               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5445                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5446                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5447                 return;
5448         }
5449         /* Step 3: Check CL37 Message Pages received to indicate LP
5450          * supports only CL37
5451          */
5452         CL22_RD_OVER_CL45(bp, phy,
5453                           MDIO_REG_BANK_REMOTE_PHY,
5454                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5455                           &cl37_fsm_received);
5456         if ((cl37_fsm_received &
5457              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5458              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5459             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5460               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5461                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5462                              "misc_rx_status(0x8330) = 0x%x\n",
5463                          cl37_fsm_received);
5464                 return;
5465         }
5466         /* The combined cl37/cl73 fsm state information indicating that
5467          * we are connected to a device which does not support cl73, but
5468          * does support cl37 BAM. In this case we disable cl73 and
5469          * restart cl37 auto-neg
5470          */
5471
5472         /* Disable CL73 */
5473         CL22_WR_OVER_CL45(bp, phy,
5474                           MDIO_REG_BANK_CL73_IEEEB0,
5475                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5476                           0);
5477         /* Restart CL37 autoneg */
5478         bnx2x_restart_autoneg(phy, params, 0);
5479         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5480 }
5481
5482 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5483                                   struct link_params *params,
5484                                   struct link_vars *vars,
5485                                   u32 gp_status)
5486 {
5487         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5488                 vars->link_status |=
5489                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5490
5491         if (bnx2x_direct_parallel_detect_used(phy, params))
5492                 vars->link_status |=
5493                         LINK_STATUS_PARALLEL_DETECTION_USED;
5494 }
5495 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5496                                      struct link_params *params,
5497                                       struct link_vars *vars,
5498                                       u16 is_link_up,
5499                                       u16 speed_mask,
5500                                       u16 is_duplex)
5501 {
5502         struct bnx2x *bp = params->bp;
5503         if (phy->req_line_speed == SPEED_AUTO_NEG)
5504                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5505         if (is_link_up) {
5506                 DP(NETIF_MSG_LINK, "phy link up\n");
5507
5508                 vars->phy_link_up = 1;
5509                 vars->link_status |= LINK_STATUS_LINK_UP;
5510
5511                 switch (speed_mask) {
5512                 case GP_STATUS_10M:
5513                         vars->line_speed = SPEED_10;
5514                         if (is_duplex == DUPLEX_FULL)
5515                                 vars->link_status |= LINK_10TFD;
5516                         else
5517                                 vars->link_status |= LINK_10THD;
5518                         break;
5519
5520                 case GP_STATUS_100M:
5521                         vars->line_speed = SPEED_100;
5522                         if (is_duplex == DUPLEX_FULL)
5523                                 vars->link_status |= LINK_100TXFD;
5524                         else
5525                                 vars->link_status |= LINK_100TXHD;
5526                         break;
5527
5528                 case GP_STATUS_1G:
5529                 case GP_STATUS_1G_KX:
5530                         vars->line_speed = SPEED_1000;
5531                         if (is_duplex == DUPLEX_FULL)
5532                                 vars->link_status |= LINK_1000TFD;
5533                         else
5534                                 vars->link_status |= LINK_1000THD;
5535                         break;
5536
5537                 case GP_STATUS_2_5G:
5538                         vars->line_speed = SPEED_2500;
5539                         if (is_duplex == DUPLEX_FULL)
5540                                 vars->link_status |= LINK_2500TFD;
5541                         else
5542                                 vars->link_status |= LINK_2500THD;
5543                         break;
5544
5545                 case GP_STATUS_5G:
5546                 case GP_STATUS_6G:
5547                         DP(NETIF_MSG_LINK,
5548                                  "link speed unsupported  gp_status 0x%x\n",
5549                                   speed_mask);
5550                         return -EINVAL;
5551
5552                 case GP_STATUS_10G_KX4:
5553                 case GP_STATUS_10G_HIG:
5554                 case GP_STATUS_10G_CX4:
5555                 case GP_STATUS_10G_KR:
5556                 case GP_STATUS_10G_SFI:
5557                 case GP_STATUS_10G_XFI:
5558                         vars->line_speed = SPEED_10000;
5559                         vars->link_status |= LINK_10GTFD;
5560                         break;
5561                 case GP_STATUS_20G_DXGXS:
5562                 case GP_STATUS_20G_KR2:
5563                         vars->line_speed = SPEED_20000;
5564                         vars->link_status |= LINK_20GTFD;
5565                         break;
5566                 default:
5567                         DP(NETIF_MSG_LINK,
5568                                   "link speed unsupported gp_status 0x%x\n",
5569                                   speed_mask);
5570                         return -EINVAL;
5571                 }
5572         } else { /* link_down */
5573                 DP(NETIF_MSG_LINK, "phy link down\n");
5574
5575                 vars->phy_link_up = 0;
5576
5577                 vars->duplex = DUPLEX_FULL;
5578                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5579                 vars->mac_type = MAC_TYPE_NONE;
5580         }
5581         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5582                     vars->phy_link_up, vars->line_speed);
5583         return 0;
5584 }
5585
5586 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5587                                       struct link_params *params,
5588                                       struct link_vars *vars)
5589 {
5590         struct bnx2x *bp = params->bp;
5591
5592         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5593         int rc = 0;
5594
5595         /* Read gp_status */
5596         CL22_RD_OVER_CL45(bp, phy,
5597                           MDIO_REG_BANK_GP_STATUS,
5598                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5599                           &gp_status);
5600         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5601                 duplex = DUPLEX_FULL;
5602         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5603                 link_up = 1;
5604         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5605         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5606                        gp_status, link_up, speed_mask);
5607         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5608                                          duplex);
5609         if (rc == -EINVAL)
5610                 return rc;
5611
5612         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5613                 if (SINGLE_MEDIA_DIRECT(params)) {
5614                         vars->duplex = duplex;
5615                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5616                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5617                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5618                                                       gp_status);
5619                 }
5620         } else { /* Link_down */
5621                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5622                     SINGLE_MEDIA_DIRECT(params)) {
5623                         /* Check signal is detected */
5624                         bnx2x_check_fallback_to_cl37(phy, params);
5625                 }
5626         }
5627
5628         /* Read LP advertised speeds*/
5629         if (SINGLE_MEDIA_DIRECT(params) &&
5630             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5631                 u16 val;
5632
5633                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5634                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5635
5636                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5637                         vars->link_status |=
5638                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5639                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5640                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5641                         vars->link_status |=
5642                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5643
5644                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5645                                   MDIO_OVER_1G_LP_UP1, &val);
5646
5647                 if (val & MDIO_OVER_1G_UP1_2_5G)
5648                         vars->link_status |=
5649                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5650                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5651                         vars->link_status |=
5652                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5653         }
5654
5655         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5656                    vars->duplex, vars->flow_ctrl, vars->link_status);
5657         return rc;
5658 }
5659
5660 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5661                                      struct link_params *params,
5662                                      struct link_vars *vars)
5663 {
5664         struct bnx2x *bp = params->bp;
5665         u8 lane;
5666         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5667         int rc = 0;
5668         lane = bnx2x_get_warpcore_lane(phy, params);
5669         /* Read gp_status */
5670         if ((params->loopback_mode) &&
5671             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5672                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5673                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5674                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5675                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5676                 link_up &= 0x1;
5677         } else if ((phy->req_line_speed > SPEED_10000) &&
5678                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5679                 u16 temp_link_up;
5680                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5681                                 1, &temp_link_up);
5682                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5683                                 1, &link_up);
5684                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5685                                temp_link_up, link_up);
5686                 link_up &= (1<<2);
5687                 if (link_up)
5688                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5689         } else {
5690                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5691                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5692                                 &gp_status1);
5693                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5694                 /* Check for either KR, 1G, or AN up. */
5695                 link_up = ((gp_status1 >> 8) |
5696                            (gp_status1 >> 12) |
5697                            (gp_status1)) &
5698                         (1 << lane);
5699                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5700                         u16 an_link;
5701                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5702                                         MDIO_AN_REG_STATUS, &an_link);
5703                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5704                                         MDIO_AN_REG_STATUS, &an_link);
5705                         link_up |= (an_link & (1<<2));
5706                 }
5707                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5708                         u16 pd, gp_status4;
5709                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5710                                 /* Check Autoneg complete */
5711                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5712                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5713                                                 &gp_status4);
5714                                 if (gp_status4 & ((1<<12)<<lane))
5715                                         vars->link_status |=
5716                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5717
5718                                 /* Check parallel detect used */
5719                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5720                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5721                                                 &pd);
5722                                 if (pd & (1<<15))
5723                                         vars->link_status |=
5724                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5725                         }
5726                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5727                         vars->duplex = duplex;
5728                 }
5729         }
5730
5731         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5732             SINGLE_MEDIA_DIRECT(params)) {
5733                 u16 val;
5734
5735                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5736                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5737
5738                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5739                         vars->link_status |=
5740                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5741                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5742                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5743                         vars->link_status |=
5744                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5745
5746                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5747                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5748
5749                 if (val & MDIO_OVER_1G_UP1_2_5G)
5750                         vars->link_status |=
5751                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5752                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5753                         vars->link_status |=
5754                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5755
5756         }
5757
5758
5759         if (lane < 2) {
5760                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5761                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5762         } else {
5763                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5764                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5765         }
5766         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5767
5768         if ((lane & 1) == 0)
5769                 gp_speed <<= 8;
5770         gp_speed &= 0x3f00;
5771         link_up = !!link_up;
5772
5773         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5774                                          duplex);
5775
5776         /* In case of KR link down, start up the recovering procedure */
5777         if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5778             (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5779                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5780
5781         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5782                    vars->duplex, vars->flow_ctrl, vars->link_status);
5783         return rc;
5784 }
5785 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5786 {
5787         struct bnx2x *bp = params->bp;
5788         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5789         u16 lp_up2;
5790         u16 tx_driver;
5791         u16 bank;
5792
5793         /* Read precomp */
5794         CL22_RD_OVER_CL45(bp, phy,
5795                           MDIO_REG_BANK_OVER_1G,
5796                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5797
5798         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5799         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5800                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5801                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5802
5803         if (lp_up2 == 0)
5804                 return;
5805
5806         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5807               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5808                 CL22_RD_OVER_CL45(bp, phy,
5809                                   bank,
5810                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5811
5812                 /* Replace tx_driver bits [15:12] */
5813                 if (lp_up2 !=
5814                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5815                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5816                         tx_driver |= lp_up2;
5817                         CL22_WR_OVER_CL45(bp, phy,
5818                                           bank,
5819                                           MDIO_TX0_TX_DRIVER, tx_driver);
5820                 }
5821         }
5822 }
5823
5824 static int bnx2x_emac_program(struct link_params *params,
5825                               struct link_vars *vars)
5826 {
5827         struct bnx2x *bp = params->bp;
5828         u8 port = params->port;
5829         u16 mode = 0;
5830
5831         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5832         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5833                        EMAC_REG_EMAC_MODE,
5834                        (EMAC_MODE_25G_MODE |
5835                         EMAC_MODE_PORT_MII_10M |
5836                         EMAC_MODE_HALF_DUPLEX));
5837         switch (vars->line_speed) {
5838         case SPEED_10:
5839                 mode |= EMAC_MODE_PORT_MII_10M;
5840                 break;
5841
5842         case SPEED_100:
5843                 mode |= EMAC_MODE_PORT_MII;
5844                 break;
5845
5846         case SPEED_1000:
5847                 mode |= EMAC_MODE_PORT_GMII;
5848                 break;
5849
5850         case SPEED_2500:
5851                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5852                 break;
5853
5854         default:
5855                 /* 10G not valid for EMAC */
5856                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5857                            vars->line_speed);
5858                 return -EINVAL;
5859         }
5860
5861         if (vars->duplex == DUPLEX_HALF)
5862                 mode |= EMAC_MODE_HALF_DUPLEX;
5863         bnx2x_bits_en(bp,
5864                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5865                       mode);
5866
5867         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5868         return 0;
5869 }
5870
5871 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5872                                   struct link_params *params)
5873 {
5874
5875         u16 bank, i = 0;
5876         struct bnx2x *bp = params->bp;
5877
5878         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5879               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5880                         CL22_WR_OVER_CL45(bp, phy,
5881                                           bank,
5882                                           MDIO_RX0_RX_EQ_BOOST,
5883                                           phy->rx_preemphasis[i]);
5884         }
5885
5886         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5887                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5888                         CL22_WR_OVER_CL45(bp, phy,
5889                                           bank,
5890                                           MDIO_TX0_TX_DRIVER,
5891                                           phy->tx_preemphasis[i]);
5892         }
5893 }
5894
5895 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5896                                    struct link_params *params,
5897                                    struct link_vars *vars)
5898 {
5899         struct bnx2x *bp = params->bp;
5900         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5901                           (params->loopback_mode == LOOPBACK_XGXS));
5902         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5903                 if (SINGLE_MEDIA_DIRECT(params) &&
5904                     (params->feature_config_flags &
5905                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5906                         bnx2x_set_preemphasis(phy, params);
5907
5908                 /* Forced speed requested? */
5909                 if (vars->line_speed != SPEED_AUTO_NEG ||
5910                     (SINGLE_MEDIA_DIRECT(params) &&
5911                      params->loopback_mode == LOOPBACK_EXT)) {
5912                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5913
5914                         /* Disable autoneg */
5915                         bnx2x_set_autoneg(phy, params, vars, 0);
5916
5917                         /* Program speed and duplex */
5918                         bnx2x_program_serdes(phy, params, vars);
5919
5920                 } else { /* AN_mode */
5921                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5922
5923                         /* AN enabled */
5924                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5925
5926                         /* Program duplex & pause advertisement (for aneg) */
5927                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5928                                                           vars->ieee_fc);
5929
5930                         /* Enable autoneg */
5931                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5932
5933                         /* Enable and restart AN */
5934                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5935                 }
5936
5937         } else { /* SGMII mode */
5938                 DP(NETIF_MSG_LINK, "SGMII\n");
5939
5940                 bnx2x_initialize_sgmii_process(phy, params, vars);
5941         }
5942 }
5943
5944 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5945                           struct link_params *params,
5946                           struct link_vars *vars)
5947 {
5948         int rc;
5949         vars->phy_flags |= PHY_XGXS_FLAG;
5950         if ((phy->req_line_speed &&
5951              ((phy->req_line_speed == SPEED_100) ||
5952               (phy->req_line_speed == SPEED_10))) ||
5953             (!phy->req_line_speed &&
5954              (phy->speed_cap_mask >=
5955               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5956              (phy->speed_cap_mask <
5957               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5958             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5959                 vars->phy_flags |= PHY_SGMII_FLAG;
5960         else
5961                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5962
5963         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5964         bnx2x_set_aer_mmd(params, phy);
5965         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5966                 bnx2x_set_master_ln(params, phy);
5967
5968         rc = bnx2x_reset_unicore(params, phy, 0);
5969         /* Reset the SerDes and wait for reset bit return low */
5970         if (rc)
5971                 return rc;
5972
5973         bnx2x_set_aer_mmd(params, phy);
5974         /* Setting the masterLn_def again after the reset */
5975         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5976                 bnx2x_set_master_ln(params, phy);
5977                 bnx2x_set_swap_lanes(params, phy);
5978         }
5979
5980         return rc;
5981 }
5982
5983 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5984                                      struct bnx2x_phy *phy,
5985                                      struct link_params *params)
5986 {
5987         u16 cnt, ctrl;
5988         /* Wait for soft reset to get cleared up to 1 sec */
5989         for (cnt = 0; cnt < 1000; cnt++) {
5990                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5991                         bnx2x_cl22_read(bp, phy,
5992                                 MDIO_PMA_REG_CTRL, &ctrl);
5993                 else
5994                         bnx2x_cl45_read(bp, phy,
5995                                 MDIO_PMA_DEVAD,
5996                                 MDIO_PMA_REG_CTRL, &ctrl);
5997                 if (!(ctrl & (1<<15)))
5998                         break;
5999                 usleep_range(1000, 2000);
6000         }
6001
6002         if (cnt == 1000)
6003                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
6004                                       " Port %d\n",
6005                          params->port);
6006         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6007         return cnt;
6008 }
6009
6010 static void bnx2x_link_int_enable(struct link_params *params)
6011 {
6012         u8 port = params->port;
6013         u32 mask;
6014         struct bnx2x *bp = params->bp;
6015
6016         /* Setting the status to report on link up for either XGXS or SerDes */
6017         if (CHIP_IS_E3(bp)) {
6018                 mask = NIG_MASK_XGXS0_LINK_STATUS;
6019                 if (!(SINGLE_MEDIA_DIRECT(params)))
6020                         mask |= NIG_MASK_MI_INT;
6021         } else if (params->switch_cfg == SWITCH_CFG_10G) {
6022                 mask = (NIG_MASK_XGXS0_LINK10G |
6023                         NIG_MASK_XGXS0_LINK_STATUS);
6024                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6025                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6026                         params->phy[INT_PHY].type !=
6027                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6028                         mask |= NIG_MASK_MI_INT;
6029                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6030                 }
6031
6032         } else { /* SerDes */
6033                 mask = NIG_MASK_SERDES0_LINK_STATUS;
6034                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6035                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6036                         params->phy[INT_PHY].type !=
6037                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6038                         mask |= NIG_MASK_MI_INT;
6039                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6040                 }
6041         }
6042         bnx2x_bits_en(bp,
6043                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6044                       mask);
6045
6046         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6047                  (params->switch_cfg == SWITCH_CFG_10G),
6048                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6049         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6050                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6051                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6052                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6053         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6054            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6055            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6056 }
6057
6058 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6059                                      u8 exp_mi_int)
6060 {
6061         u32 latch_status = 0;
6062
6063         /* Disable the MI INT ( external phy int ) by writing 1 to the
6064          * status register. Link down indication is high-active-signal,
6065          * so in this case we need to write the status to clear the XOR
6066          */
6067         /* Read Latched signals */
6068         latch_status = REG_RD(bp,
6069                                     NIG_REG_LATCH_STATUS_0 + port*8);
6070         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6071         /* Handle only those with latched-signal=up.*/
6072         if (exp_mi_int)
6073                 bnx2x_bits_en(bp,
6074                               NIG_REG_STATUS_INTERRUPT_PORT0
6075                               + port*4,
6076                               NIG_STATUS_EMAC0_MI_INT);
6077         else
6078                 bnx2x_bits_dis(bp,
6079                                NIG_REG_STATUS_INTERRUPT_PORT0
6080                                + port*4,
6081                                NIG_STATUS_EMAC0_MI_INT);
6082
6083         if (latch_status & 1) {
6084
6085                 /* For all latched-signal=up : Re-Arm Latch signals */
6086                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6087                        (latch_status & 0xfffe) | (latch_status & 1));
6088         }
6089         /* For all latched-signal=up,Write original_signal to status */
6090 }
6091
6092 static void bnx2x_link_int_ack(struct link_params *params,
6093                                struct link_vars *vars, u8 is_10g_plus)
6094 {
6095         struct bnx2x *bp = params->bp;
6096         u8 port = params->port;
6097         u32 mask;
6098         /* First reset all status we assume only one line will be
6099          * change at a time
6100          */
6101         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6102                        (NIG_STATUS_XGXS0_LINK10G |
6103                         NIG_STATUS_XGXS0_LINK_STATUS |
6104                         NIG_STATUS_SERDES0_LINK_STATUS));
6105         if (vars->phy_link_up) {
6106                 if (USES_WARPCORE(bp))
6107                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6108                 else {
6109                         if (is_10g_plus)
6110                                 mask = NIG_STATUS_XGXS0_LINK10G;
6111                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6112                                 /* Disable the link interrupt by writing 1 to
6113                                  * the relevant lane in the status register
6114                                  */
6115                                 u32 ser_lane =
6116                                         ((params->lane_config &
6117                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6118                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6119                                 mask = ((1 << ser_lane) <<
6120                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6121                         } else
6122                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6123                 }
6124                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6125                                mask);
6126                 bnx2x_bits_en(bp,
6127                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6128                               mask);
6129         }
6130 }
6131
6132 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6133 {
6134         u8 *str_ptr = str;
6135         u32 mask = 0xf0000000;
6136         u8 shift = 8*4;
6137         u8 digit;
6138         u8 remove_leading_zeros = 1;
6139         if (*len < 10) {
6140                 /* Need more than 10chars for this format */
6141                 *str_ptr = '\0';
6142                 (*len)--;
6143                 return -EINVAL;
6144         }
6145         while (shift > 0) {
6146
6147                 shift -= 4;
6148                 digit = ((num & mask) >> shift);
6149                 if (digit == 0 && remove_leading_zeros) {
6150                         mask = mask >> 4;
6151                         continue;
6152                 } else if (digit < 0xa)
6153                         *str_ptr = digit + '0';
6154                 else
6155                         *str_ptr = digit - 0xa + 'a';
6156                 remove_leading_zeros = 0;
6157                 str_ptr++;
6158                 (*len)--;
6159                 mask = mask >> 4;
6160                 if (shift == 4*4) {
6161                         *str_ptr = '.';
6162                         str_ptr++;
6163                         (*len)--;
6164                         remove_leading_zeros = 1;
6165                 }
6166         }
6167         return 0;
6168 }
6169
6170
6171 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6172 {
6173         str[0] = '\0';
6174         (*len)--;
6175         return 0;
6176 }
6177
6178 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6179                                  u16 len)
6180 {
6181         struct bnx2x *bp;
6182         u32 spirom_ver = 0;
6183         int status = 0;
6184         u8 *ver_p = version;
6185         u16 remain_len = len;
6186         if (version == NULL || params == NULL)
6187                 return -EINVAL;
6188         bp = params->bp;
6189
6190         /* Extract first external phy*/
6191         version[0] = '\0';
6192         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6193
6194         if (params->phy[EXT_PHY1].format_fw_ver) {
6195                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6196                                                               ver_p,
6197                                                               &remain_len);
6198                 ver_p += (len - remain_len);
6199         }
6200         if ((params->num_phys == MAX_PHYS) &&
6201             (params->phy[EXT_PHY2].ver_addr != 0)) {
6202                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6203                 if (params->phy[EXT_PHY2].format_fw_ver) {
6204                         *ver_p = '/';
6205                         ver_p++;
6206                         remain_len--;
6207                         status |= params->phy[EXT_PHY2].format_fw_ver(
6208                                 spirom_ver,
6209                                 ver_p,
6210                                 &remain_len);
6211                         ver_p = version + (len - remain_len);
6212                 }
6213         }
6214         *ver_p = '\0';
6215         return status;
6216 }
6217
6218 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6219                                     struct link_params *params)
6220 {
6221         u8 port = params->port;
6222         struct bnx2x *bp = params->bp;
6223
6224         if (phy->req_line_speed != SPEED_1000) {
6225                 u32 md_devad = 0;
6226
6227                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6228
6229                 if (!CHIP_IS_E3(bp)) {
6230                         /* Change the uni_phy_addr in the nig */
6231                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6232                                                port*0x18));
6233
6234                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6235                                0x5);
6236                 }
6237
6238                 bnx2x_cl45_write(bp, phy,
6239                                  5,
6240                                  (MDIO_REG_BANK_AER_BLOCK +
6241                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6242                                  0x2800);
6243
6244                 bnx2x_cl45_write(bp, phy,
6245                                  5,
6246                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6247                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6248                                  0x6041);
6249                 msleep(200);
6250                 /* Set aer mmd back */
6251                 bnx2x_set_aer_mmd(params, phy);
6252
6253                 if (!CHIP_IS_E3(bp)) {
6254                         /* And md_devad */
6255                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6256                                md_devad);
6257                 }
6258         } else {
6259                 u16 mii_ctrl;
6260                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6261                 bnx2x_cl45_read(bp, phy, 5,
6262                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6263                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6264                                 &mii_ctrl);
6265                 bnx2x_cl45_write(bp, phy, 5,
6266                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6267                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6268                                  mii_ctrl |
6269                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6270         }
6271 }
6272
6273 int bnx2x_set_led(struct link_params *params,
6274                   struct link_vars *vars, u8 mode, u32 speed)
6275 {
6276         u8 port = params->port;
6277         u16 hw_led_mode = params->hw_led_mode;
6278         int rc = 0;
6279         u8 phy_idx;
6280         u32 tmp;
6281         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6282         struct bnx2x *bp = params->bp;
6283         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6284         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6285                  speed, hw_led_mode);
6286         /* In case */
6287         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6288                 if (params->phy[phy_idx].set_link_led) {
6289                         params->phy[phy_idx].set_link_led(
6290                                 &params->phy[phy_idx], params, mode);
6291                 }
6292         }
6293
6294         switch (mode) {
6295         case LED_MODE_FRONT_PANEL_OFF:
6296         case LED_MODE_OFF:
6297                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6298                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6299                        SHARED_HW_CFG_LED_MAC1);
6300
6301                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6302                 if (params->phy[EXT_PHY1].type ==
6303                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6304                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6305                                 EMAC_LED_100MB_OVERRIDE |
6306                                 EMAC_LED_10MB_OVERRIDE);
6307                 else
6308                         tmp |= EMAC_LED_OVERRIDE;
6309
6310                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6311                 break;
6312
6313         case LED_MODE_OPER:
6314                 /* For all other phys, OPER mode is same as ON, so in case
6315                  * link is down, do nothing
6316                  */
6317                 if (!vars->link_up)
6318                         break;
6319         case LED_MODE_ON:
6320                 if (((params->phy[EXT_PHY1].type ==
6321                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6322                          (params->phy[EXT_PHY1].type ==
6323                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6324                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6325                         /* This is a work-around for E2+8727 Configurations */
6326                         if (mode == LED_MODE_ON ||
6327                                 speed == SPEED_10000){
6328                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6329                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6330
6331                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6332                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6333                                         (tmp | EMAC_LED_OVERRIDE));
6334                                 /* Return here without enabling traffic
6335                                  * LED blink and setting rate in ON mode.
6336                                  * In oper mode, enabling LED blink
6337                                  * and setting rate is needed.
6338                                  */
6339                                 if (mode == LED_MODE_ON)
6340                                         return rc;
6341                         }
6342                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6343                         /* This is a work-around for HW issue found when link
6344                          * is up in CL73
6345                          */
6346                         if ((!CHIP_IS_E3(bp)) ||
6347                             (CHIP_IS_E3(bp) &&
6348                              mode == LED_MODE_ON))
6349                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6350
6351                         if (CHIP_IS_E1x(bp) ||
6352                             CHIP_IS_E2(bp) ||
6353                             (mode == LED_MODE_ON))
6354                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6355                         else
6356                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6357                                        hw_led_mode);
6358                 } else if ((params->phy[EXT_PHY1].type ==
6359                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6360                            (mode == LED_MODE_ON)) {
6361                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6362                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6363                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6364                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6365                         /* Break here; otherwise, it'll disable the
6366                          * intended override.
6367                          */
6368                         break;
6369                 } else
6370                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6371                                hw_led_mode);
6372
6373                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6374                 /* Set blinking rate to ~15.9Hz */
6375                 if (CHIP_IS_E3(bp))
6376                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6377                                LED_BLINK_RATE_VAL_E3);
6378                 else
6379                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6380                                LED_BLINK_RATE_VAL_E1X_E2);
6381                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6382                        port*4, 1);
6383                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6384                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6385                         (tmp & (~EMAC_LED_OVERRIDE)));
6386
6387                 if (CHIP_IS_E1(bp) &&
6388                     ((speed == SPEED_2500) ||
6389                      (speed == SPEED_1000) ||
6390                      (speed == SPEED_100) ||
6391                      (speed == SPEED_10))) {
6392                         /* For speeds less than 10G LED scheme is different */
6393                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6394                                + port*4, 1);
6395                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6396                                port*4, 0);
6397                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6398                                port*4, 1);
6399                 }
6400                 break;
6401
6402         default:
6403                 rc = -EINVAL;
6404                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6405                          mode);
6406                 break;
6407         }
6408         return rc;
6409
6410 }
6411
6412 /* This function comes to reflect the actual link state read DIRECTLY from the
6413  * HW
6414  */
6415 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6416                     u8 is_serdes)
6417 {
6418         struct bnx2x *bp = params->bp;
6419         u16 gp_status = 0, phy_index = 0;
6420         u8 ext_phy_link_up = 0, serdes_phy_type;
6421         struct link_vars temp_vars;
6422         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6423
6424         if (CHIP_IS_E3(bp)) {
6425                 u16 link_up;
6426                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6427                     > SPEED_10000) {
6428                         /* Check 20G link */
6429                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6430                                         1, &link_up);
6431                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6432                                         1, &link_up);
6433                         link_up &= (1<<2);
6434                 } else {
6435                         /* Check 10G link and below*/
6436                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6437                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6438                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6439                                         &gp_status);
6440                         gp_status = ((gp_status >> 8) & 0xf) |
6441                                 ((gp_status >> 12) & 0xf);
6442                         link_up = gp_status & (1 << lane);
6443                 }
6444                 if (!link_up)
6445                         return -ESRCH;
6446         } else {
6447                 CL22_RD_OVER_CL45(bp, int_phy,
6448                           MDIO_REG_BANK_GP_STATUS,
6449                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6450                           &gp_status);
6451         /* Link is up only if both local phy and external phy are up */
6452         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6453                 return -ESRCH;
6454         }
6455         /* In XGXS loopback mode, do not check external PHY */
6456         if (params->loopback_mode == LOOPBACK_XGXS)
6457                 return 0;
6458
6459         switch (params->num_phys) {
6460         case 1:
6461                 /* No external PHY */
6462                 return 0;
6463         case 2:
6464                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6465                         &params->phy[EXT_PHY1],
6466                         params, &temp_vars);
6467                 break;
6468         case 3: /* Dual Media */
6469                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6470                       phy_index++) {
6471                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6472                                             ETH_PHY_SFPP_10G_FIBER) ||
6473                                            (params->phy[phy_index].media_type ==
6474                                             ETH_PHY_SFP_1G_FIBER) ||
6475                                            (params->phy[phy_index].media_type ==
6476                                             ETH_PHY_XFP_FIBER) ||
6477                                            (params->phy[phy_index].media_type ==
6478                                             ETH_PHY_DA_TWINAX));
6479
6480                         if (is_serdes != serdes_phy_type)
6481                                 continue;
6482                         if (params->phy[phy_index].read_status) {
6483                                 ext_phy_link_up |=
6484                                         params->phy[phy_index].read_status(
6485                                                 &params->phy[phy_index],
6486                                                 params, &temp_vars);
6487                         }
6488                 }
6489                 break;
6490         }
6491         if (ext_phy_link_up)
6492                 return 0;
6493         return -ESRCH;
6494 }
6495
6496 static int bnx2x_link_initialize(struct link_params *params,
6497                                  struct link_vars *vars)
6498 {
6499         int rc = 0;
6500         u8 phy_index, non_ext_phy;
6501         struct bnx2x *bp = params->bp;
6502         /* In case of external phy existence, the line speed would be the
6503          * line speed linked up by the external phy. In case it is direct
6504          * only, then the line_speed during initialization will be
6505          * equal to the req_line_speed
6506          */
6507         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6508
6509         /* Initialize the internal phy in case this is a direct board
6510          * (no external phys), or this board has external phy which requires
6511          * to first.
6512          */
6513         if (!USES_WARPCORE(bp))
6514                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6515         /* init ext phy and enable link state int */
6516         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6517                        (params->loopback_mode == LOOPBACK_XGXS));
6518
6519         if (non_ext_phy ||
6520             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6521             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6522                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6523                 if (vars->line_speed == SPEED_AUTO_NEG &&
6524                     (CHIP_IS_E1x(bp) ||
6525                      CHIP_IS_E2(bp)))
6526                         bnx2x_set_parallel_detection(phy, params);
6527                 if (params->phy[INT_PHY].config_init)
6528                         params->phy[INT_PHY].config_init(phy, params, vars);
6529         }
6530
6531         /* Init external phy*/
6532         if (non_ext_phy) {
6533                 if (params->phy[INT_PHY].supported &
6534                     SUPPORTED_FIBRE)
6535                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6536         } else {
6537                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6538                       phy_index++) {
6539                         /* No need to initialize second phy in case of first
6540                          * phy only selection. In case of second phy, we do
6541                          * need to initialize the first phy, since they are
6542                          * connected.
6543                          */
6544                         if (params->phy[phy_index].supported &
6545                             SUPPORTED_FIBRE)
6546                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6547
6548                         if (phy_index == EXT_PHY2 &&
6549                             (bnx2x_phy_selection(params) ==
6550                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6551                                 DP(NETIF_MSG_LINK,
6552                                    "Not initializing second phy\n");
6553                                 continue;
6554                         }
6555                         params->phy[phy_index].config_init(
6556                                 &params->phy[phy_index],
6557                                 params, vars);
6558                 }
6559         }
6560         /* Reset the interrupt indication after phy was initialized */
6561         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6562                        params->port*4,
6563                        (NIG_STATUS_XGXS0_LINK10G |
6564                         NIG_STATUS_XGXS0_LINK_STATUS |
6565                         NIG_STATUS_SERDES0_LINK_STATUS |
6566                         NIG_MASK_MI_INT));
6567         return rc;
6568 }
6569
6570 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6571                                  struct link_params *params)
6572 {
6573         /* Reset the SerDes/XGXS */
6574         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6575                (0x1ff << (params->port*16)));
6576 }
6577
6578 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6579                                         struct link_params *params)
6580 {
6581         struct bnx2x *bp = params->bp;
6582         u8 gpio_port;
6583         /* HW reset */
6584         if (CHIP_IS_E2(bp))
6585                 gpio_port = BP_PATH(bp);
6586         else
6587                 gpio_port = params->port;
6588         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6589                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6590                        gpio_port);
6591         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6592                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6593                        gpio_port);
6594         DP(NETIF_MSG_LINK, "reset external PHY\n");
6595 }
6596
6597 static int bnx2x_update_link_down(struct link_params *params,
6598                                   struct link_vars *vars)
6599 {
6600         struct bnx2x *bp = params->bp;
6601         u8 port = params->port;
6602
6603         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6604         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6605         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6606         /* Indicate no mac active */
6607         vars->mac_type = MAC_TYPE_NONE;
6608
6609         /* Update shared memory */
6610         vars->link_status &= ~LINK_UPDATE_MASK;
6611         vars->line_speed = 0;
6612         bnx2x_update_mng(params, vars->link_status);
6613
6614         /* Activate nig drain */
6615         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6616
6617         /* Disable emac */
6618         if (!CHIP_IS_E3(bp))
6619                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6620
6621         usleep_range(10000, 20000);
6622         /* Reset BigMac/Xmac */
6623         if (CHIP_IS_E1x(bp) ||
6624             CHIP_IS_E2(bp))
6625                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6626
6627         if (CHIP_IS_E3(bp)) {
6628                 /* Prevent LPI Generation by chip */
6629                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6630                        0);
6631                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6632                        0);
6633                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6634                                       SHMEM_EEE_ACTIVE_BIT);
6635
6636                 bnx2x_update_mng_eee(params, vars->eee_status);
6637                 bnx2x_set_xmac_rxtx(params, 0);
6638                 bnx2x_set_umac_rxtx(params, 0);
6639         }
6640
6641         return 0;
6642 }
6643
6644 static int bnx2x_update_link_up(struct link_params *params,
6645                                 struct link_vars *vars,
6646                                 u8 link_10g)
6647 {
6648         struct bnx2x *bp = params->bp;
6649         u8 phy_idx, port = params->port;
6650         int rc = 0;
6651
6652         vars->link_status |= (LINK_STATUS_LINK_UP |
6653                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6654         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6655
6656         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6657                 vars->link_status |=
6658                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6659
6660         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6661                 vars->link_status |=
6662                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6663         if (USES_WARPCORE(bp)) {
6664                 if (link_10g) {
6665                         if (bnx2x_xmac_enable(params, vars, 0) ==
6666                             -ESRCH) {
6667                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6668                                 vars->link_up = 0;
6669                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6670                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6671                         }
6672                 } else
6673                         bnx2x_umac_enable(params, vars, 0);
6674                 bnx2x_set_led(params, vars,
6675                               LED_MODE_OPER, vars->line_speed);
6676
6677                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6678                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6679                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6680                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6681                                (params->port << 2), 1);
6682                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6683                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6684                                (params->port << 2), 0xfc20);
6685                 }
6686         }
6687         if ((CHIP_IS_E1x(bp) ||
6688              CHIP_IS_E2(bp))) {
6689                 if (link_10g) {
6690                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6691                             -ESRCH) {
6692                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6693                                 vars->link_up = 0;
6694                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6695                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6696                         }
6697
6698                         bnx2x_set_led(params, vars,
6699                                       LED_MODE_OPER, SPEED_10000);
6700                 } else {
6701                         rc = bnx2x_emac_program(params, vars);
6702                         bnx2x_emac_enable(params, vars, 0);
6703
6704                         /* AN complete? */
6705                         if ((vars->link_status &
6706                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6707                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6708                             SINGLE_MEDIA_DIRECT(params))
6709                                 bnx2x_set_gmii_tx_driver(params);
6710                 }
6711         }
6712
6713         /* PBF - link up */
6714         if (CHIP_IS_E1x(bp))
6715                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6716                                        vars->line_speed);
6717
6718         /* Disable drain */
6719         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6720
6721         /* Update shared memory */
6722         bnx2x_update_mng(params, vars->link_status);
6723         bnx2x_update_mng_eee(params, vars->eee_status);
6724         /* Check remote fault */
6725         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6726                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6727                         bnx2x_check_half_open_conn(params, vars, 0);
6728                         break;
6729                 }
6730         }
6731         msleep(20);
6732         return rc;
6733 }
6734 /* The bnx2x_link_update function should be called upon link
6735  * interrupt.
6736  * Link is considered up as follows:
6737  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6738  *   to be up
6739  * - SINGLE_MEDIA - The link between the 577xx and the external
6740  *   phy (XGXS) need to up as well as the external link of the
6741  *   phy (PHY_EXT1)
6742  * - DUAL_MEDIA - The link between the 577xx and the first
6743  *   external phy needs to be up, and at least one of the 2
6744  *   external phy link must be up.
6745  */
6746 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6747 {
6748         struct bnx2x *bp = params->bp;
6749         struct link_vars phy_vars[MAX_PHYS];
6750         u8 port = params->port;
6751         u8 link_10g_plus, phy_index;
6752         u8 ext_phy_link_up = 0, cur_link_up;
6753         int rc = 0;
6754         u8 is_mi_int = 0;
6755         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6756         u8 active_external_phy = INT_PHY;
6757         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6758         vars->link_status &= ~LINK_UPDATE_MASK;
6759         for (phy_index = INT_PHY; phy_index < params->num_phys;
6760               phy_index++) {
6761                 phy_vars[phy_index].flow_ctrl = 0;
6762                 phy_vars[phy_index].link_status = 0;
6763                 phy_vars[phy_index].line_speed = 0;
6764                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6765                 phy_vars[phy_index].phy_link_up = 0;
6766                 phy_vars[phy_index].link_up = 0;
6767                 phy_vars[phy_index].fault_detected = 0;
6768                 /* different consideration, since vars holds inner state */
6769                 phy_vars[phy_index].eee_status = vars->eee_status;
6770         }
6771
6772         if (USES_WARPCORE(bp))
6773                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6774
6775         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6776                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6777                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6778
6779         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6780                                 port*0x18) > 0);
6781         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6782                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6783                  is_mi_int,
6784                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6785
6786         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6787           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6788           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6789
6790         /* Disable emac */
6791         if (!CHIP_IS_E3(bp))
6792                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6793
6794         /* Step 1:
6795          * Check external link change only for external phys, and apply
6796          * priority selection between them in case the link on both phys
6797          * is up. Note that instead of the common vars, a temporary
6798          * vars argument is used since each phy may have different link/
6799          * speed/duplex result
6800          */
6801         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6802               phy_index++) {
6803                 struct bnx2x_phy *phy = &params->phy[phy_index];
6804                 if (!phy->read_status)
6805                         continue;
6806                 /* Read link status and params of this ext phy */
6807                 cur_link_up = phy->read_status(phy, params,
6808                                                &phy_vars[phy_index]);
6809                 if (cur_link_up) {
6810                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6811                                    phy_index);
6812                 } else {
6813                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6814                                    phy_index);
6815                         continue;
6816                 }
6817
6818                 if (!ext_phy_link_up) {
6819                         ext_phy_link_up = 1;
6820                         active_external_phy = phy_index;
6821                 } else {
6822                         switch (bnx2x_phy_selection(params)) {
6823                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6824                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6825                         /* In this option, the first PHY makes sure to pass the
6826                          * traffic through itself only.
6827                          * Its not clear how to reset the link on the second phy
6828                          */
6829                                 active_external_phy = EXT_PHY1;
6830                                 break;
6831                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6832                         /* In this option, the first PHY makes sure to pass the
6833                          * traffic through the second PHY.
6834                          */
6835                                 active_external_phy = EXT_PHY2;
6836                                 break;
6837                         default:
6838                         /* Link indication on both PHYs with the following cases
6839                          * is invalid:
6840                          * - FIRST_PHY means that second phy wasn't initialized,
6841                          * hence its link is expected to be down
6842                          * - SECOND_PHY means that first phy should not be able
6843                          * to link up by itself (using configuration)
6844                          * - DEFAULT should be overriden during initialiazation
6845                          */
6846                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6847                                            "mpc=0x%x. DISABLING LINK !!!\n",
6848                                            params->multi_phy_config);
6849                                 ext_phy_link_up = 0;
6850                                 break;
6851                         }
6852                 }
6853         }
6854         prev_line_speed = vars->line_speed;
6855         /* Step 2:
6856          * Read the status of the internal phy. In case of
6857          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6858          * otherwise this is the link between the 577xx and the first
6859          * external phy
6860          */
6861         if (params->phy[INT_PHY].read_status)
6862                 params->phy[INT_PHY].read_status(
6863                         &params->phy[INT_PHY],
6864                         params, vars);
6865         /* The INT_PHY flow control reside in the vars. This include the
6866          * case where the speed or flow control are not set to AUTO.
6867          * Otherwise, the active external phy flow control result is set
6868          * to the vars. The ext_phy_line_speed is needed to check if the
6869          * speed is different between the internal phy and external phy.
6870          * This case may be result of intermediate link speed change.
6871          */
6872         if (active_external_phy > INT_PHY) {
6873                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6874                 /* Link speed is taken from the XGXS. AN and FC result from
6875                  * the external phy.
6876                  */
6877                 vars->link_status |= phy_vars[active_external_phy].link_status;
6878
6879                 /* if active_external_phy is first PHY and link is up - disable
6880                  * disable TX on second external PHY
6881                  */
6882                 if (active_external_phy == EXT_PHY1) {
6883                         if (params->phy[EXT_PHY2].phy_specific_func) {
6884                                 DP(NETIF_MSG_LINK,
6885                                    "Disabling TX on EXT_PHY2\n");
6886                                 params->phy[EXT_PHY2].phy_specific_func(
6887                                         &params->phy[EXT_PHY2],
6888                                         params, DISABLE_TX);
6889                         }
6890                 }
6891
6892                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6893                 vars->duplex = phy_vars[active_external_phy].duplex;
6894                 if (params->phy[active_external_phy].supported &
6895                     SUPPORTED_FIBRE)
6896                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6897                 else
6898                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6899
6900                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6901
6902                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6903                            active_external_phy);
6904         }
6905
6906         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6907               phy_index++) {
6908                 if (params->phy[phy_index].flags &
6909                     FLAGS_REARM_LATCH_SIGNAL) {
6910                         bnx2x_rearm_latch_signal(bp, port,
6911                                                  phy_index ==
6912                                                  active_external_phy);
6913                         break;
6914                 }
6915         }
6916         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6917                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6918                    vars->link_status, ext_phy_line_speed);
6919         /* Upon link speed change set the NIG into drain mode. Comes to
6920          * deals with possible FIFO glitch due to clk change when speed
6921          * is decreased without link down indicator
6922          */
6923
6924         if (vars->phy_link_up) {
6925                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6926                     (ext_phy_line_speed != vars->line_speed)) {
6927                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6928                                    " different than the external"
6929                                    " link speed %d\n", vars->line_speed,
6930                                    ext_phy_line_speed);
6931                         vars->phy_link_up = 0;
6932                 } else if (prev_line_speed != vars->line_speed) {
6933                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6934                                0);
6935                         usleep_range(1000, 2000);
6936                 }
6937         }
6938
6939         /* Anything 10 and over uses the bmac */
6940         link_10g_plus = (vars->line_speed >= SPEED_10000);
6941
6942         bnx2x_link_int_ack(params, vars, link_10g_plus);
6943
6944         /* In case external phy link is up, and internal link is down
6945          * (not initialized yet probably after link initialization, it
6946          * needs to be initialized.
6947          * Note that after link down-up as result of cable plug, the xgxs
6948          * link would probably become up again without the need
6949          * initialize it
6950          */
6951         if (!(SINGLE_MEDIA_DIRECT(params))) {
6952                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6953                            " init_preceding = %d\n", ext_phy_link_up,
6954                            vars->phy_link_up,
6955                            params->phy[EXT_PHY1].flags &
6956                            FLAGS_INIT_XGXS_FIRST);
6957                 if (!(params->phy[EXT_PHY1].flags &
6958                       FLAGS_INIT_XGXS_FIRST)
6959                     && ext_phy_link_up && !vars->phy_link_up) {
6960                         vars->line_speed = ext_phy_line_speed;
6961                         if (vars->line_speed < SPEED_1000)
6962                                 vars->phy_flags |= PHY_SGMII_FLAG;
6963                         else
6964                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6965
6966                         if (params->phy[INT_PHY].config_init)
6967                                 params->phy[INT_PHY].config_init(
6968                                         &params->phy[INT_PHY], params,
6969                                                 vars);
6970                 }
6971         }
6972         /* Link is up only if both local phy and external phy (in case of
6973          * non-direct board) are up and no fault detected on active PHY.
6974          */
6975         vars->link_up = (vars->phy_link_up &&
6976                          (ext_phy_link_up ||
6977                           SINGLE_MEDIA_DIRECT(params)) &&
6978                          (phy_vars[active_external_phy].fault_detected == 0));
6979
6980         /* Update the PFC configuration in case it was changed */
6981         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6982                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6983         else
6984                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6985
6986         if (vars->link_up)
6987                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6988         else
6989                 rc = bnx2x_update_link_down(params, vars);
6990
6991         /* Update MCP link status was changed */
6992         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6993                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6994
6995         return rc;
6996 }
6997
6998 /*****************************************************************************/
6999 /*                          External Phy section                             */
7000 /*****************************************************************************/
7001 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7002 {
7003         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7004                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7005         usleep_range(1000, 2000);
7006         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7007                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7008 }
7009
7010 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7011                                       u32 spirom_ver, u32 ver_addr)
7012 {
7013         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7014                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7015
7016         if (ver_addr)
7017                 REG_WR(bp, ver_addr, spirom_ver);
7018 }
7019
7020 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7021                                       struct bnx2x_phy *phy,
7022                                       u8 port)
7023 {
7024         u16 fw_ver1, fw_ver2;
7025
7026         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7027                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7028         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7029                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7030         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7031                                   phy->ver_addr);
7032 }
7033
7034 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7035                                        struct bnx2x_phy *phy,
7036                                        struct link_vars *vars)
7037 {
7038         u16 val;
7039         bnx2x_cl45_read(bp, phy,
7040                         MDIO_AN_DEVAD,
7041                         MDIO_AN_REG_STATUS, &val);
7042         bnx2x_cl45_read(bp, phy,
7043                         MDIO_AN_DEVAD,
7044                         MDIO_AN_REG_STATUS, &val);
7045         if (val & (1<<5))
7046                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7047         if ((val & (1<<0)) == 0)
7048                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7049 }
7050
7051 /******************************************************************/
7052 /*              common BCM8073/BCM8727 PHY SECTION                */
7053 /******************************************************************/
7054 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7055                                   struct link_params *params,
7056                                   struct link_vars *vars)
7057 {
7058         struct bnx2x *bp = params->bp;
7059         if (phy->req_line_speed == SPEED_10 ||
7060             phy->req_line_speed == SPEED_100) {
7061                 vars->flow_ctrl = phy->req_flow_ctrl;
7062                 return;
7063         }
7064
7065         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7066             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7067                 u16 pause_result;
7068                 u16 ld_pause;           /* local */
7069                 u16 lp_pause;           /* link partner */
7070                 bnx2x_cl45_read(bp, phy,
7071                                 MDIO_AN_DEVAD,
7072                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7073
7074                 bnx2x_cl45_read(bp, phy,
7075                                 MDIO_AN_DEVAD,
7076                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7077                 pause_result = (ld_pause &
7078                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7079                 pause_result |= (lp_pause &
7080                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7081
7082                 bnx2x_pause_resolve(vars, pause_result);
7083                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7084                            pause_result);
7085         }
7086 }
7087 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7088                                              struct bnx2x_phy *phy,
7089                                              u8 port)
7090 {
7091         u32 count = 0;
7092         u16 fw_ver1, fw_msgout;
7093         int rc = 0;
7094
7095         /* Boot port from external ROM  */
7096         /* EDC grst */
7097         bnx2x_cl45_write(bp, phy,
7098                          MDIO_PMA_DEVAD,
7099                          MDIO_PMA_REG_GEN_CTRL,
7100                          0x0001);
7101
7102         /* Ucode reboot and rst */
7103         bnx2x_cl45_write(bp, phy,
7104                          MDIO_PMA_DEVAD,
7105                          MDIO_PMA_REG_GEN_CTRL,
7106                          0x008c);
7107
7108         bnx2x_cl45_write(bp, phy,
7109                          MDIO_PMA_DEVAD,
7110                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7111
7112         /* Reset internal microprocessor */
7113         bnx2x_cl45_write(bp, phy,
7114                          MDIO_PMA_DEVAD,
7115                          MDIO_PMA_REG_GEN_CTRL,
7116                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7117
7118         /* Release srst bit */
7119         bnx2x_cl45_write(bp, phy,
7120                          MDIO_PMA_DEVAD,
7121                          MDIO_PMA_REG_GEN_CTRL,
7122                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7123
7124         /* Delay 100ms per the PHY specifications */
7125         msleep(100);
7126
7127         /* 8073 sometimes taking longer to download */
7128         do {
7129                 count++;
7130                 if (count > 300) {
7131                         DP(NETIF_MSG_LINK,
7132                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7133                                  "Download failed. fw version = 0x%x\n",
7134                                  port, fw_ver1);
7135                         rc = -EINVAL;
7136                         break;
7137                 }
7138
7139                 bnx2x_cl45_read(bp, phy,
7140                                 MDIO_PMA_DEVAD,
7141                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7142                 bnx2x_cl45_read(bp, phy,
7143                                 MDIO_PMA_DEVAD,
7144                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7145
7146                 usleep_range(1000, 2000);
7147         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7148                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7149                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7150
7151         /* Clear ser_boot_ctl bit */
7152         bnx2x_cl45_write(bp, phy,
7153                          MDIO_PMA_DEVAD,
7154                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7155         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7156
7157         DP(NETIF_MSG_LINK,
7158                  "bnx2x_8073_8727_external_rom_boot port %x:"
7159                  "Download complete. fw version = 0x%x\n",
7160                  port, fw_ver1);
7161
7162         return rc;
7163 }
7164
7165 /******************************************************************/
7166 /*                      BCM8073 PHY SECTION                       */
7167 /******************************************************************/
7168 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7169 {
7170         /* This is only required for 8073A1, version 102 only */
7171         u16 val;
7172
7173         /* Read 8073 HW revision*/
7174         bnx2x_cl45_read(bp, phy,
7175                         MDIO_PMA_DEVAD,
7176                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7177
7178         if (val != 1) {
7179                 /* No need to workaround in 8073 A1 */
7180                 return 0;
7181         }
7182
7183         bnx2x_cl45_read(bp, phy,
7184                         MDIO_PMA_DEVAD,
7185                         MDIO_PMA_REG_ROM_VER2, &val);
7186
7187         /* SNR should be applied only for version 0x102 */
7188         if (val != 0x102)
7189                 return 0;
7190
7191         return 1;
7192 }
7193
7194 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7195 {
7196         u16 val, cnt, cnt1 ;
7197
7198         bnx2x_cl45_read(bp, phy,
7199                         MDIO_PMA_DEVAD,
7200                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7201
7202         if (val > 0) {
7203                 /* No need to workaround in 8073 A1 */
7204                 return 0;
7205         }
7206         /* XAUI workaround in 8073 A0: */
7207
7208         /* After loading the boot ROM and restarting Autoneg, poll
7209          * Dev1, Reg $C820:
7210          */
7211
7212         for (cnt = 0; cnt < 1000; cnt++) {
7213                 bnx2x_cl45_read(bp, phy,
7214                                 MDIO_PMA_DEVAD,
7215                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7216                                 &val);
7217                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7218                    * system initialization (XAUI work-around not required, as
7219                    * these bits indicate 2.5G or 1G link up).
7220                    */
7221                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7222                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7223                         return 0;
7224                 } else if (!(val & (1<<15))) {
7225                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7226                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7227                          * MSB (bit15) goes to 1 (indicating that the XAUI
7228                          * workaround has completed), then continue on with
7229                          * system initialization.
7230                          */
7231                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7232                                 bnx2x_cl45_read(bp, phy,
7233                                         MDIO_PMA_DEVAD,
7234                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7235                                 if (val & (1<<15)) {
7236                                         DP(NETIF_MSG_LINK,
7237                                           "XAUI workaround has completed\n");
7238                                         return 0;
7239                                  }
7240                                  usleep_range(3000, 6000);
7241                         }
7242                         break;
7243                 }
7244                 usleep_range(3000, 6000);
7245         }
7246         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7247         return -EINVAL;
7248 }
7249
7250 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7251 {
7252         /* Force KR or KX */
7253         bnx2x_cl45_write(bp, phy,
7254                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7255         bnx2x_cl45_write(bp, phy,
7256                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7257         bnx2x_cl45_write(bp, phy,
7258                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7259         bnx2x_cl45_write(bp, phy,
7260                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7261 }
7262
7263 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7264                                       struct bnx2x_phy *phy,
7265                                       struct link_vars *vars)
7266 {
7267         u16 cl37_val;
7268         struct bnx2x *bp = params->bp;
7269         bnx2x_cl45_read(bp, phy,
7270                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7271
7272         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7273         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7274         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7275         if ((vars->ieee_fc &
7276             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7277             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7278                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7279         }
7280         if ((vars->ieee_fc &
7281             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7282             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7283                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7284         }
7285         if ((vars->ieee_fc &
7286             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7287             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7288                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7289         }
7290         DP(NETIF_MSG_LINK,
7291                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7292
7293         bnx2x_cl45_write(bp, phy,
7294                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7295         msleep(500);
7296 }
7297
7298 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7299                                      struct link_params *params,
7300                                      u32 action)
7301 {
7302         struct bnx2x *bp = params->bp;
7303         switch (action) {
7304         case PHY_INIT:
7305                 /* Enable LASI */
7306                 bnx2x_cl45_write(bp, phy,
7307                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7308                 bnx2x_cl45_write(bp, phy,
7309                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7310                 break;
7311         }
7312 }
7313
7314 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7315                                   struct link_params *params,
7316                                   struct link_vars *vars)
7317 {
7318         struct bnx2x *bp = params->bp;
7319         u16 val = 0, tmp1;
7320         u8 gpio_port;
7321         DP(NETIF_MSG_LINK, "Init 8073\n");
7322
7323         if (CHIP_IS_E2(bp))
7324                 gpio_port = BP_PATH(bp);
7325         else
7326                 gpio_port = params->port;
7327         /* Restore normal power mode*/
7328         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7329                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7330
7331         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7332                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7333
7334         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7335         bnx2x_8073_set_pause_cl37(params, phy, vars);
7336
7337         bnx2x_cl45_read(bp, phy,
7338                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7339
7340         bnx2x_cl45_read(bp, phy,
7341                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7342
7343         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7344
7345         /* Swap polarity if required - Must be done only in non-1G mode */
7346         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7347                 /* Configure the 8073 to swap _P and _N of the KR lines */
7348                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7349                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7350                 bnx2x_cl45_read(bp, phy,
7351                                 MDIO_PMA_DEVAD,
7352                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7353                 bnx2x_cl45_write(bp, phy,
7354                                  MDIO_PMA_DEVAD,
7355                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7356                                  (val | (3<<9)));
7357         }
7358
7359
7360         /* Enable CL37 BAM */
7361         if (REG_RD(bp, params->shmem_base +
7362                          offsetof(struct shmem_region, dev_info.
7363                                   port_hw_config[params->port].default_cfg)) &
7364             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7365
7366                 bnx2x_cl45_read(bp, phy,
7367                                 MDIO_AN_DEVAD,
7368                                 MDIO_AN_REG_8073_BAM, &val);
7369                 bnx2x_cl45_write(bp, phy,
7370                                  MDIO_AN_DEVAD,
7371                                  MDIO_AN_REG_8073_BAM, val | 1);
7372                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7373         }
7374         if (params->loopback_mode == LOOPBACK_EXT) {
7375                 bnx2x_807x_force_10G(bp, phy);
7376                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7377                 return 0;
7378         } else {
7379                 bnx2x_cl45_write(bp, phy,
7380                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7381         }
7382         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7383                 if (phy->req_line_speed == SPEED_10000) {
7384                         val = (1<<7);
7385                 } else if (phy->req_line_speed ==  SPEED_2500) {
7386                         val = (1<<5);
7387                         /* Note that 2.5G works only when used with 1G
7388                          * advertisement
7389                          */
7390                 } else
7391                         val = (1<<5);
7392         } else {
7393                 val = 0;
7394                 if (phy->speed_cap_mask &
7395                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7396                         val |= (1<<7);
7397
7398                 /* Note that 2.5G works only when used with 1G advertisement */
7399                 if (phy->speed_cap_mask &
7400                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7401                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7402                         val |= (1<<5);
7403                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7404         }
7405
7406         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7407         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7408
7409         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7410              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7411             (phy->req_line_speed == SPEED_2500)) {
7412                 u16 phy_ver;
7413                 /* Allow 2.5G for A1 and above */
7414                 bnx2x_cl45_read(bp, phy,
7415                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7416                                 &phy_ver);
7417                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7418                 if (phy_ver > 0)
7419                         tmp1 |= 1;
7420                 else
7421                         tmp1 &= 0xfffe;
7422         } else {
7423                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7424                 tmp1 &= 0xfffe;
7425         }
7426
7427         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7428         /* Add support for CL37 (passive mode) II */
7429
7430         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7431         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7432                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7433                                   0x20 : 0x40)));
7434
7435         /* Add support for CL37 (passive mode) III */
7436         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7437
7438         /* The SNR will improve about 2db by changing BW and FEE main
7439          * tap. Rest commands are executed after link is up
7440          * Change FFE main cursor to 5 in EDC register
7441          */
7442         if (bnx2x_8073_is_snr_needed(bp, phy))
7443                 bnx2x_cl45_write(bp, phy,
7444                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7445                                  0xFB0C);
7446
7447         /* Enable FEC (Forware Error Correction) Request in the AN */
7448         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7449         tmp1 |= (1<<15);
7450         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7451
7452         bnx2x_ext_phy_set_pause(params, phy, vars);
7453
7454         /* Restart autoneg */
7455         msleep(500);
7456         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7457         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7458                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7459         return 0;
7460 }
7461
7462 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7463                                  struct link_params *params,
7464                                  struct link_vars *vars)
7465 {
7466         struct bnx2x *bp = params->bp;
7467         u8 link_up = 0;
7468         u16 val1, val2;
7469         u16 link_status = 0;
7470         u16 an1000_status = 0;
7471
7472         bnx2x_cl45_read(bp, phy,
7473                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7474
7475         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7476
7477         /* Clear the interrupt LASI status register */
7478         bnx2x_cl45_read(bp, phy,
7479                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7480         bnx2x_cl45_read(bp, phy,
7481                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7482         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7483         /* Clear MSG-OUT */
7484         bnx2x_cl45_read(bp, phy,
7485                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7486
7487         /* Check the LASI */
7488         bnx2x_cl45_read(bp, phy,
7489                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7490
7491         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7492
7493         /* Check the link status */
7494         bnx2x_cl45_read(bp, phy,
7495                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7496         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7497
7498         bnx2x_cl45_read(bp, phy,
7499                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7500         bnx2x_cl45_read(bp, phy,
7501                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7502         link_up = ((val1 & 4) == 4);
7503         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7504
7505         if (link_up &&
7506              ((phy->req_line_speed != SPEED_10000))) {
7507                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7508                         return 0;
7509         }
7510         bnx2x_cl45_read(bp, phy,
7511                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7512         bnx2x_cl45_read(bp, phy,
7513                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7514
7515         /* Check the link status on 1.1.2 */
7516         bnx2x_cl45_read(bp, phy,
7517                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7518         bnx2x_cl45_read(bp, phy,
7519                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7520         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7521                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7522
7523         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7524         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7525                 /* The SNR will improve about 2dbby changing the BW and FEE main
7526                  * tap. The 1st write to change FFE main tap is set before
7527                  * restart AN. Change PLL Bandwidth in EDC register
7528                  */
7529                 bnx2x_cl45_write(bp, phy,
7530                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7531                                  0x26BC);
7532
7533                 /* Change CDR Bandwidth in EDC register */
7534                 bnx2x_cl45_write(bp, phy,
7535                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7536                                  0x0333);
7537         }
7538         bnx2x_cl45_read(bp, phy,
7539                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7540                         &link_status);
7541
7542         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7543         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7544                 link_up = 1;
7545                 vars->line_speed = SPEED_10000;
7546                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7547                            params->port);
7548         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7549                 link_up = 1;
7550                 vars->line_speed = SPEED_2500;
7551                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7552                            params->port);
7553         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7554                 link_up = 1;
7555                 vars->line_speed = SPEED_1000;
7556                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7557                            params->port);
7558         } else {
7559                 link_up = 0;
7560                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7561                            params->port);
7562         }
7563
7564         if (link_up) {
7565                 /* Swap polarity if required */
7566                 if (params->lane_config &
7567                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7568                         /* Configure the 8073 to swap P and N of the KR lines */
7569                         bnx2x_cl45_read(bp, phy,
7570                                         MDIO_XS_DEVAD,
7571                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7572                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7573                          * when it`s in 10G mode.
7574                          */
7575                         if (vars->line_speed == SPEED_1000) {
7576                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7577                                               "the 8073\n");
7578                                 val1 |= (1<<3);
7579                         } else
7580                                 val1 &= ~(1<<3);
7581
7582                         bnx2x_cl45_write(bp, phy,
7583                                          MDIO_XS_DEVAD,
7584                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7585                                          val1);
7586                 }
7587                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7588                 bnx2x_8073_resolve_fc(phy, params, vars);
7589                 vars->duplex = DUPLEX_FULL;
7590         }
7591
7592         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7593                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7594                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7595
7596                 if (val1 & (1<<5))
7597                         vars->link_status |=
7598                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7599                 if (val1 & (1<<7))
7600                         vars->link_status |=
7601                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7602         }
7603
7604         return link_up;
7605 }
7606
7607 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7608                                   struct link_params *params)
7609 {
7610         struct bnx2x *bp = params->bp;
7611         u8 gpio_port;
7612         if (CHIP_IS_E2(bp))
7613                 gpio_port = BP_PATH(bp);
7614         else
7615                 gpio_port = params->port;
7616         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7617            gpio_port);
7618         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7619                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7620                        gpio_port);
7621 }
7622
7623 /******************************************************************/
7624 /*                      BCM8705 PHY SECTION                       */
7625 /******************************************************************/
7626 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7627                                   struct link_params *params,
7628                                   struct link_vars *vars)
7629 {
7630         struct bnx2x *bp = params->bp;
7631         DP(NETIF_MSG_LINK, "init 8705\n");
7632         /* Restore normal power mode*/
7633         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7634                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7635         /* HW reset */
7636         bnx2x_ext_phy_hw_reset(bp, params->port);
7637         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7638         bnx2x_wait_reset_complete(bp, phy, params);
7639
7640         bnx2x_cl45_write(bp, phy,
7641                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7642         bnx2x_cl45_write(bp, phy,
7643                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7644         bnx2x_cl45_write(bp, phy,
7645                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7646         bnx2x_cl45_write(bp, phy,
7647                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7648         /* BCM8705 doesn't have microcode, hence the 0 */
7649         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7650         return 0;
7651 }
7652
7653 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7654                                  struct link_params *params,
7655                                  struct link_vars *vars)
7656 {
7657         u8 link_up = 0;
7658         u16 val1, rx_sd;
7659         struct bnx2x *bp = params->bp;
7660         DP(NETIF_MSG_LINK, "read status 8705\n");
7661         bnx2x_cl45_read(bp, phy,
7662                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7663         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7664
7665         bnx2x_cl45_read(bp, phy,
7666                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7667         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7668
7669         bnx2x_cl45_read(bp, phy,
7670                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7671
7672         bnx2x_cl45_read(bp, phy,
7673                       MDIO_PMA_DEVAD, 0xc809, &val1);
7674         bnx2x_cl45_read(bp, phy,
7675                       MDIO_PMA_DEVAD, 0xc809, &val1);
7676
7677         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7678         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7679         if (link_up) {
7680                 vars->line_speed = SPEED_10000;
7681                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7682         }
7683         return link_up;
7684 }
7685
7686 /******************************************************************/
7687 /*                      SFP+ module Section                       */
7688 /******************************************************************/
7689 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7690                                            struct bnx2x_phy *phy,
7691                                            u8 pmd_dis)
7692 {
7693         struct bnx2x *bp = params->bp;
7694         /* Disable transmitter only for bootcodes which can enable it afterwards
7695          * (for D3 link)
7696          */
7697         if (pmd_dis) {
7698                 if (params->feature_config_flags &
7699                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7700                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7701                 else {
7702                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7703                         return;
7704                 }
7705         } else
7706                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7707         bnx2x_cl45_write(bp, phy,
7708                          MDIO_PMA_DEVAD,
7709                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7710 }
7711
7712 static u8 bnx2x_get_gpio_port(struct link_params *params)
7713 {
7714         u8 gpio_port;
7715         u32 swap_val, swap_override;
7716         struct bnx2x *bp = params->bp;
7717         if (CHIP_IS_E2(bp))
7718                 gpio_port = BP_PATH(bp);
7719         else
7720                 gpio_port = params->port;
7721         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7722         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7723         return gpio_port ^ (swap_val && swap_override);
7724 }
7725
7726 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7727                                            struct bnx2x_phy *phy,
7728                                            u8 tx_en)
7729 {
7730         u16 val;
7731         u8 port = params->port;
7732         struct bnx2x *bp = params->bp;
7733         u32 tx_en_mode;
7734
7735         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7736         tx_en_mode = REG_RD(bp, params->shmem_base +
7737                             offsetof(struct shmem_region,
7738                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7739                 PORT_HW_CFG_TX_LASER_MASK;
7740         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7741                            "mode = %x\n", tx_en, port, tx_en_mode);
7742         switch (tx_en_mode) {
7743         case PORT_HW_CFG_TX_LASER_MDIO:
7744
7745                 bnx2x_cl45_read(bp, phy,
7746                                 MDIO_PMA_DEVAD,
7747                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7748                                 &val);
7749
7750                 if (tx_en)
7751                         val &= ~(1<<15);
7752                 else
7753                         val |= (1<<15);
7754
7755                 bnx2x_cl45_write(bp, phy,
7756                                  MDIO_PMA_DEVAD,
7757                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7758                                  val);
7759         break;
7760         case PORT_HW_CFG_TX_LASER_GPIO0:
7761         case PORT_HW_CFG_TX_LASER_GPIO1:
7762         case PORT_HW_CFG_TX_LASER_GPIO2:
7763         case PORT_HW_CFG_TX_LASER_GPIO3:
7764         {
7765                 u16 gpio_pin;
7766                 u8 gpio_port, gpio_mode;
7767                 if (tx_en)
7768                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7769                 else
7770                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7771
7772                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7773                 gpio_port = bnx2x_get_gpio_port(params);
7774                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7775                 break;
7776         }
7777         default:
7778                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7779                 break;
7780         }
7781 }
7782
7783 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7784                                       struct bnx2x_phy *phy,
7785                                       u8 tx_en)
7786 {
7787         struct bnx2x *bp = params->bp;
7788         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7789         if (CHIP_IS_E3(bp))
7790                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7791         else
7792                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7793 }
7794
7795 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7796                                              struct link_params *params,
7797                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7798                                              u8 *o_buf, u8 is_init)
7799 {
7800         struct bnx2x *bp = params->bp;
7801         u16 val = 0;
7802         u16 i;
7803         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7804                 DP(NETIF_MSG_LINK,
7805                    "Reading from eeprom is limited to 0xf\n");
7806                 return -EINVAL;
7807         }
7808         /* Set the read command byte count */
7809         bnx2x_cl45_write(bp, phy,
7810                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7811                          (byte_cnt | (dev_addr << 8)));
7812
7813         /* Set the read command address */
7814         bnx2x_cl45_write(bp, phy,
7815                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7816                          addr);
7817
7818         /* Activate read command */
7819         bnx2x_cl45_write(bp, phy,
7820                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7821                          0x2c0f);
7822
7823         /* Wait up to 500us for command complete status */
7824         for (i = 0; i < 100; i++) {
7825                 bnx2x_cl45_read(bp, phy,
7826                                 MDIO_PMA_DEVAD,
7827                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7828                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7829                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7830                         break;
7831                 udelay(5);
7832         }
7833
7834         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7835                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7836                 DP(NETIF_MSG_LINK,
7837                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7838                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7839                 return -EINVAL;
7840         }
7841
7842         /* Read the buffer */
7843         for (i = 0; i < byte_cnt; i++) {
7844                 bnx2x_cl45_read(bp, phy,
7845                                 MDIO_PMA_DEVAD,
7846                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7847                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7848         }
7849
7850         for (i = 0; i < 100; i++) {
7851                 bnx2x_cl45_read(bp, phy,
7852                                 MDIO_PMA_DEVAD,
7853                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7854                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7855                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7856                         return 0;
7857                 usleep_range(1000, 2000);
7858         }
7859         return -EINVAL;
7860 }
7861
7862 static void bnx2x_warpcore_power_module(struct link_params *params,
7863                                         u8 power)
7864 {
7865         u32 pin_cfg;
7866         struct bnx2x *bp = params->bp;
7867
7868         pin_cfg = (REG_RD(bp, params->shmem_base +
7869                           offsetof(struct shmem_region,
7870                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7871                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7872                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7873
7874         if (pin_cfg == PIN_CFG_NA)
7875                 return;
7876         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7877                        power, pin_cfg);
7878         /* Low ==> corresponding SFP+ module is powered
7879          * high ==> the SFP+ module is powered down
7880          */
7881         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7882 }
7883 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7884                                                  struct link_params *params,
7885                                                  u8 dev_addr,
7886                                                  u16 addr, u8 byte_cnt,
7887                                                  u8 *o_buf, u8 is_init)
7888 {
7889         int rc = 0;
7890         u8 i, j = 0, cnt = 0;
7891         u32 data_array[4];
7892         u16 addr32;
7893         struct bnx2x *bp = params->bp;
7894
7895         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7896                 DP(NETIF_MSG_LINK,
7897                    "Reading from eeprom is limited to 16 bytes\n");
7898                 return -EINVAL;
7899         }
7900
7901         /* 4 byte aligned address */
7902         addr32 = addr & (~0x3);
7903         do {
7904                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7905                         bnx2x_warpcore_power_module(params, 0);
7906                         /* Note that 100us are not enough here */
7907                         usleep_range(1000, 2000);
7908                         bnx2x_warpcore_power_module(params, 1);
7909                 }
7910                 rc = bnx2x_bsc_read(params, phy, dev_addr, addr32, 0, byte_cnt,
7911                                     data_array);
7912         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7913
7914         if (rc == 0) {
7915                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7916                         o_buf[j] = *((u8 *)data_array + i);
7917                         j++;
7918                 }
7919         }
7920
7921         return rc;
7922 }
7923
7924 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7925                                              struct link_params *params,
7926                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7927                                              u8 *o_buf, u8 is_init)
7928 {
7929         struct bnx2x *bp = params->bp;
7930         u16 val, i;
7931
7932         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7933                 DP(NETIF_MSG_LINK,
7934                    "Reading from eeprom is limited to 0xf\n");
7935                 return -EINVAL;
7936         }
7937
7938         /* Set 2-wire transfer rate of SFP+ module EEPROM
7939          * to 100Khz since some DACs(direct attached cables) do
7940          * not work at 400Khz.
7941          */
7942         bnx2x_cl45_write(bp, phy,
7943                          MDIO_PMA_DEVAD,
7944                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7945                          ((dev_addr << 8) | 1));
7946
7947         /* Need to read from 1.8000 to clear it */
7948         bnx2x_cl45_read(bp, phy,
7949                         MDIO_PMA_DEVAD,
7950                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7951                         &val);
7952
7953         /* Set the read command byte count */
7954         bnx2x_cl45_write(bp, phy,
7955                          MDIO_PMA_DEVAD,
7956                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7957                          ((byte_cnt < 2) ? 2 : byte_cnt));
7958
7959         /* Set the read command address */
7960         bnx2x_cl45_write(bp, phy,
7961                          MDIO_PMA_DEVAD,
7962                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7963                          addr);
7964         /* Set the destination address */
7965         bnx2x_cl45_write(bp, phy,
7966                          MDIO_PMA_DEVAD,
7967                          0x8004,
7968                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7969
7970         /* Activate read command */
7971         bnx2x_cl45_write(bp, phy,
7972                          MDIO_PMA_DEVAD,
7973                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7974                          0x8002);
7975         /* Wait appropriate time for two-wire command to finish before
7976          * polling the status register
7977          */
7978         usleep_range(1000, 2000);
7979
7980         /* Wait up to 500us for command complete status */
7981         for (i = 0; i < 100; i++) {
7982                 bnx2x_cl45_read(bp, phy,
7983                                 MDIO_PMA_DEVAD,
7984                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7985                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7986                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7987                         break;
7988                 udelay(5);
7989         }
7990
7991         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7992                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7993                 DP(NETIF_MSG_LINK,
7994                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7995                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7996                 return -EFAULT;
7997         }
7998
7999         /* Read the buffer */
8000         for (i = 0; i < byte_cnt; i++) {
8001                 bnx2x_cl45_read(bp, phy,
8002                                 MDIO_PMA_DEVAD,
8003                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8004                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8005         }
8006
8007         for (i = 0; i < 100; i++) {
8008                 bnx2x_cl45_read(bp, phy,
8009                                 MDIO_PMA_DEVAD,
8010                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8011                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8012                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8013                         return 0;
8014                 usleep_range(1000, 2000);
8015         }
8016
8017         return -EINVAL;
8018 }
8019 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8020                                  struct link_params *params, u8 dev_addr,
8021                                  u16 addr, u16 byte_cnt, u8 *o_buf)
8022 {
8023         int rc = 0;
8024         struct bnx2x *bp = params->bp;
8025         u8 xfer_size;
8026         u8 *user_data = o_buf;
8027         read_sfp_module_eeprom_func_p read_func;
8028
8029         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8030                 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8031                 return -EINVAL;
8032         }
8033
8034         switch (phy->type) {
8035         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8036                 read_func = bnx2x_8726_read_sfp_module_eeprom;
8037                 break;
8038         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8039         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8040                 read_func = bnx2x_8727_read_sfp_module_eeprom;
8041                 break;
8042         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8043                 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8044                 break;
8045         default:
8046                 return -EOPNOTSUPP;
8047         }
8048
8049         while (!rc && (byte_cnt > 0)) {
8050                 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8051                         SFP_EEPROM_PAGE_SIZE : byte_cnt;
8052                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8053                                user_data, 0);
8054                 byte_cnt -= xfer_size;
8055                 user_data += xfer_size;
8056                 addr += xfer_size;
8057         }
8058         return rc;
8059 }
8060
8061 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8062                               struct link_params *params,
8063                               u16 *edc_mode)
8064 {
8065         struct bnx2x *bp = params->bp;
8066         u32 sync_offset = 0, phy_idx, media_types;
8067         u8 gport, val[2], check_limiting_mode = 0;
8068         *edc_mode = EDC_MODE_LIMITING;
8069         phy->media_type = ETH_PHY_UNSPECIFIED;
8070         /* First check for copper cable */
8071         if (bnx2x_read_sfp_module_eeprom(phy,
8072                                          params,
8073                                          I2C_DEV_ADDR_A0,
8074                                          SFP_EEPROM_CON_TYPE_ADDR,
8075                                          2,
8076                                          (u8 *)val) != 0) {
8077                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8078                 return -EINVAL;
8079         }
8080
8081         switch (val[0]) {
8082         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8083         {
8084                 u8 copper_module_type;
8085                 phy->media_type = ETH_PHY_DA_TWINAX;
8086                 /* Check if its active cable (includes SFP+ module)
8087                  * of passive cable
8088                  */
8089                 if (bnx2x_read_sfp_module_eeprom(phy,
8090                                                params,
8091                                                I2C_DEV_ADDR_A0,
8092                                                SFP_EEPROM_FC_TX_TECH_ADDR,
8093                                                1,
8094                                                &copper_module_type) != 0) {
8095                         DP(NETIF_MSG_LINK,
8096                                 "Failed to read copper-cable-type"
8097                                 " from SFP+ EEPROM\n");
8098                         return -EINVAL;
8099                 }
8100
8101                 if (copper_module_type &
8102                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8103                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8104                         check_limiting_mode = 1;
8105                 } else if (copper_module_type &
8106                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8107                                 DP(NETIF_MSG_LINK,
8108                                    "Passive Copper cable detected\n");
8109                                 *edc_mode =
8110                                       EDC_MODE_PASSIVE_DAC;
8111                 } else {
8112                         DP(NETIF_MSG_LINK,
8113                            "Unknown copper-cable-type 0x%x !!!\n",
8114                            copper_module_type);
8115                         return -EINVAL;
8116                 }
8117                 break;
8118         }
8119         case SFP_EEPROM_CON_TYPE_VAL_LC:
8120         case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8121                 check_limiting_mode = 1;
8122                 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8123                                SFP_EEPROM_COMP_CODE_LR_MASK |
8124                                SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8125                         DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8126                         gport = params->port;
8127                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8128                         if (phy->req_line_speed != SPEED_1000) {
8129                                 phy->req_line_speed = SPEED_1000;
8130                                 if (!CHIP_IS_E1x(bp)) {
8131                                         gport = BP_PATH(bp) +
8132                                         (params->port << 1);
8133                                 }
8134                                 netdev_err(bp->dev,
8135                                            "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8136                                            gport);
8137                         }
8138                 } else {
8139                         int idx, cfg_idx = 0;
8140                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8141                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8142                                 if (params->phy[idx].type == phy->type) {
8143                                         cfg_idx = LINK_CONFIG_IDX(idx);
8144                                         break;
8145                                 }
8146                         }
8147                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8148                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8149                 }
8150                 break;
8151         default:
8152                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8153                          val[0]);
8154                 return -EINVAL;
8155         }
8156         sync_offset = params->shmem_base +
8157                 offsetof(struct shmem_region,
8158                          dev_info.port_hw_config[params->port].media_type);
8159         media_types = REG_RD(bp, sync_offset);
8160         /* Update media type for non-PMF sync */
8161         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8162                 if (&(params->phy[phy_idx]) == phy) {
8163                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8164                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8165                         media_types |= ((phy->media_type &
8166                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8167                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8168                         break;
8169                 }
8170         }
8171         REG_WR(bp, sync_offset, media_types);
8172         if (check_limiting_mode) {
8173                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8174                 if (bnx2x_read_sfp_module_eeprom(phy,
8175                                                  params,
8176                                                  I2C_DEV_ADDR_A0,
8177                                                  SFP_EEPROM_OPTIONS_ADDR,
8178                                                  SFP_EEPROM_OPTIONS_SIZE,
8179                                                  options) != 0) {
8180                         DP(NETIF_MSG_LINK,
8181                            "Failed to read Option field from module EEPROM\n");
8182                         return -EINVAL;
8183                 }
8184                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8185                         *edc_mode = EDC_MODE_LINEAR;
8186                 else
8187                         *edc_mode = EDC_MODE_LIMITING;
8188         }
8189         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8190         return 0;
8191 }
8192 /* This function read the relevant field from the module (SFP+), and verify it
8193  * is compliant with this board
8194  */
8195 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8196                                    struct link_params *params)
8197 {
8198         struct bnx2x *bp = params->bp;
8199         u32 val, cmd;
8200         u32 fw_resp, fw_cmd_param;
8201         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8202         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8203         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8204         val = REG_RD(bp, params->shmem_base +
8205                          offsetof(struct shmem_region, dev_info.
8206                                   port_feature_config[params->port].config));
8207         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8208             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8209                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8210                 return 0;
8211         }
8212
8213         if (params->feature_config_flags &
8214             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8215                 /* Use specific phy request */
8216                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8217         } else if (params->feature_config_flags &
8218                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8219                 /* Use first phy request only in case of non-dual media*/
8220                 if (DUAL_MEDIA(params)) {
8221                         DP(NETIF_MSG_LINK,
8222                            "FW does not support OPT MDL verification\n");
8223                         return -EINVAL;
8224                 }
8225                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8226         } else {
8227                 /* No support in OPT MDL detection */
8228                 DP(NETIF_MSG_LINK,
8229                    "FW does not support OPT MDL verification\n");
8230                 return -EINVAL;
8231         }
8232
8233         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8234         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8235         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8236                 DP(NETIF_MSG_LINK, "Approved module\n");
8237                 return 0;
8238         }
8239
8240         /* Format the warning message */
8241         if (bnx2x_read_sfp_module_eeprom(phy,
8242                                          params,
8243                                          I2C_DEV_ADDR_A0,
8244                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8245                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8246                                          (u8 *)vendor_name))
8247                 vendor_name[0] = '\0';
8248         else
8249                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8250         if (bnx2x_read_sfp_module_eeprom(phy,
8251                                          params,
8252                                          I2C_DEV_ADDR_A0,
8253                                          SFP_EEPROM_PART_NO_ADDR,
8254                                          SFP_EEPROM_PART_NO_SIZE,
8255                                          (u8 *)vendor_pn))
8256                 vendor_pn[0] = '\0';
8257         else
8258                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8259
8260         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8261                               " Port %d from %s part number %s\n",
8262                          params->port, vendor_name, vendor_pn);
8263         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8264             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8265                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8266         return -EINVAL;
8267 }
8268
8269 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8270                                                  struct link_params *params)
8271
8272 {
8273         u8 val;
8274         int rc;
8275         struct bnx2x *bp = params->bp;
8276         u16 timeout;
8277         /* Initialization time after hot-plug may take up to 300ms for
8278          * some phys type ( e.g. JDSU )
8279          */
8280
8281         for (timeout = 0; timeout < 60; timeout++) {
8282                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8283                         rc = bnx2x_warpcore_read_sfp_module_eeprom(
8284                                 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8285                                 1);
8286                 else
8287                         rc = bnx2x_read_sfp_module_eeprom(phy, params,
8288                                                           I2C_DEV_ADDR_A0,
8289                                                           1, 1, &val);
8290                 if (rc == 0) {
8291                         DP(NETIF_MSG_LINK,
8292                            "SFP+ module initialization took %d ms\n",
8293                            timeout * 5);
8294                         return 0;
8295                 }
8296                 usleep_range(5000, 10000);
8297         }
8298         rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8299                                           1, 1, &val);
8300         return rc;
8301 }
8302
8303 static void bnx2x_8727_power_module(struct bnx2x *bp,
8304                                     struct bnx2x_phy *phy,
8305                                     u8 is_power_up) {
8306         /* Make sure GPIOs are not using for LED mode */
8307         u16 val;
8308         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8309          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8310          * output
8311          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8312          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8313          * where the 1st bit is the over-current(only input), and 2nd bit is
8314          * for power( only output )
8315          *
8316          * In case of NOC feature is disabled and power is up, set GPIO control
8317          *  as input to enable listening of over-current indication
8318          */
8319         if (phy->flags & FLAGS_NOC)
8320                 return;
8321         if (is_power_up)
8322                 val = (1<<4);
8323         else
8324                 /* Set GPIO control to OUTPUT, and set the power bit
8325                  * to according to the is_power_up
8326                  */
8327                 val = (1<<1);
8328
8329         bnx2x_cl45_write(bp, phy,
8330                          MDIO_PMA_DEVAD,
8331                          MDIO_PMA_REG_8727_GPIO_CTRL,
8332                          val);
8333 }
8334
8335 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8336                                         struct bnx2x_phy *phy,
8337                                         u16 edc_mode)
8338 {
8339         u16 cur_limiting_mode;
8340
8341         bnx2x_cl45_read(bp, phy,
8342                         MDIO_PMA_DEVAD,
8343                         MDIO_PMA_REG_ROM_VER2,
8344                         &cur_limiting_mode);
8345         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8346                  cur_limiting_mode);
8347
8348         if (edc_mode == EDC_MODE_LIMITING) {
8349                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8350                 bnx2x_cl45_write(bp, phy,
8351                                  MDIO_PMA_DEVAD,
8352                                  MDIO_PMA_REG_ROM_VER2,
8353                                  EDC_MODE_LIMITING);
8354         } else { /* LRM mode ( default )*/
8355
8356                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8357
8358                 /* Changing to LRM mode takes quite few seconds. So do it only
8359                  * if current mode is limiting (default is LRM)
8360                  */
8361                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8362                         return 0;
8363
8364                 bnx2x_cl45_write(bp, phy,
8365                                  MDIO_PMA_DEVAD,
8366                                  MDIO_PMA_REG_LRM_MODE,
8367                                  0);
8368                 bnx2x_cl45_write(bp, phy,
8369                                  MDIO_PMA_DEVAD,
8370                                  MDIO_PMA_REG_ROM_VER2,
8371                                  0x128);
8372                 bnx2x_cl45_write(bp, phy,
8373                                  MDIO_PMA_DEVAD,
8374                                  MDIO_PMA_REG_MISC_CTRL0,
8375                                  0x4008);
8376                 bnx2x_cl45_write(bp, phy,
8377                                  MDIO_PMA_DEVAD,
8378                                  MDIO_PMA_REG_LRM_MODE,
8379                                  0xaaaa);
8380         }
8381         return 0;
8382 }
8383
8384 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8385                                         struct bnx2x_phy *phy,
8386                                         u16 edc_mode)
8387 {
8388         u16 phy_identifier;
8389         u16 rom_ver2_val;
8390         bnx2x_cl45_read(bp, phy,
8391                         MDIO_PMA_DEVAD,
8392                         MDIO_PMA_REG_PHY_IDENTIFIER,
8393                         &phy_identifier);
8394
8395         bnx2x_cl45_write(bp, phy,
8396                          MDIO_PMA_DEVAD,
8397                          MDIO_PMA_REG_PHY_IDENTIFIER,
8398                          (phy_identifier & ~(1<<9)));
8399
8400         bnx2x_cl45_read(bp, phy,
8401                         MDIO_PMA_DEVAD,
8402                         MDIO_PMA_REG_ROM_VER2,
8403                         &rom_ver2_val);
8404         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8405         bnx2x_cl45_write(bp, phy,
8406                          MDIO_PMA_DEVAD,
8407                          MDIO_PMA_REG_ROM_VER2,
8408                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8409
8410         bnx2x_cl45_write(bp, phy,
8411                          MDIO_PMA_DEVAD,
8412                          MDIO_PMA_REG_PHY_IDENTIFIER,
8413                          (phy_identifier | (1<<9)));
8414
8415         return 0;
8416 }
8417
8418 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8419                                      struct link_params *params,
8420                                      u32 action)
8421 {
8422         struct bnx2x *bp = params->bp;
8423         u16 val;
8424         switch (action) {
8425         case DISABLE_TX:
8426                 bnx2x_sfp_set_transmitter(params, phy, 0);
8427                 break;
8428         case ENABLE_TX:
8429                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8430                         bnx2x_sfp_set_transmitter(params, phy, 1);
8431                 break;
8432         case PHY_INIT:
8433                 bnx2x_cl45_write(bp, phy,
8434                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8435                                  (1<<2) | (1<<5));
8436                 bnx2x_cl45_write(bp, phy,
8437                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8438                                  0);
8439                 bnx2x_cl45_write(bp, phy,
8440                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8441                 /* Make MOD_ABS give interrupt on change */
8442                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8443                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8444                                 &val);
8445                 val |= (1<<12);
8446                 if (phy->flags & FLAGS_NOC)
8447                         val |= (3<<5);
8448                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8449                  * status which reflect SFP+ module over-current
8450                  */
8451                 if (!(phy->flags & FLAGS_NOC))
8452                         val &= 0xff8f; /* Reset bits 4-6 */
8453                 bnx2x_cl45_write(bp, phy,
8454                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8455                                  val);
8456                 break;
8457         default:
8458                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8459                    action);
8460                 return;
8461         }
8462 }
8463
8464 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8465                                            u8 gpio_mode)
8466 {
8467         struct bnx2x *bp = params->bp;
8468
8469         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8470                             offsetof(struct shmem_region,
8471                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8472                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8473         switch (fault_led_gpio) {
8474         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8475                 return;
8476         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8477         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8478         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8479         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8480         {
8481                 u8 gpio_port = bnx2x_get_gpio_port(params);
8482                 u16 gpio_pin = fault_led_gpio -
8483                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8484                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8485                                    "pin %x port %x mode %x\n",
8486                                gpio_pin, gpio_port, gpio_mode);
8487                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8488         }
8489         break;
8490         default:
8491                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8492                                fault_led_gpio);
8493         }
8494 }
8495
8496 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8497                                           u8 gpio_mode)
8498 {
8499         u32 pin_cfg;
8500         u8 port = params->port;
8501         struct bnx2x *bp = params->bp;
8502         pin_cfg = (REG_RD(bp, params->shmem_base +
8503                          offsetof(struct shmem_region,
8504                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8505                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8506                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8507         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8508                        gpio_mode, pin_cfg);
8509         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8510 }
8511
8512 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8513                                            u8 gpio_mode)
8514 {
8515         struct bnx2x *bp = params->bp;
8516         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8517         if (CHIP_IS_E3(bp)) {
8518                 /* Low ==> if SFP+ module is supported otherwise
8519                  * High ==> if SFP+ module is not on the approved vendor list
8520                  */
8521                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8522         } else
8523                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8524 }
8525
8526 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8527                                     struct link_params *params)
8528 {
8529         struct bnx2x *bp = params->bp;
8530         bnx2x_warpcore_power_module(params, 0);
8531         /* Put Warpcore in low power mode */
8532         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8533
8534         /* Put LCPLL in low power mode */
8535         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8536         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8537         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8538 }
8539
8540 static void bnx2x_power_sfp_module(struct link_params *params,
8541                                    struct bnx2x_phy *phy,
8542                                    u8 power)
8543 {
8544         struct bnx2x *bp = params->bp;
8545         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8546
8547         switch (phy->type) {
8548         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8549         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8550                 bnx2x_8727_power_module(params->bp, phy, power);
8551                 break;
8552         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8553                 bnx2x_warpcore_power_module(params, power);
8554                 break;
8555         default:
8556                 break;
8557         }
8558 }
8559 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8560                                              struct bnx2x_phy *phy,
8561                                              u16 edc_mode)
8562 {
8563         u16 val = 0;
8564         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8565         struct bnx2x *bp = params->bp;
8566
8567         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8568         /* This is a global register which controls all lanes */
8569         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8570                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8571         val &= ~(0xf << (lane << 2));
8572
8573         switch (edc_mode) {
8574         case EDC_MODE_LINEAR:
8575         case EDC_MODE_LIMITING:
8576                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8577                 break;
8578         case EDC_MODE_PASSIVE_DAC:
8579                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8580                 break;
8581         default:
8582                 break;
8583         }
8584
8585         val |= (mode << (lane << 2));
8586         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8587                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8588         /* A must read */
8589         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8590                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8591
8592         /* Restart microcode to re-read the new mode */
8593         bnx2x_warpcore_reset_lane(bp, phy, 1);
8594         bnx2x_warpcore_reset_lane(bp, phy, 0);
8595
8596 }
8597
8598 static void bnx2x_set_limiting_mode(struct link_params *params,
8599                                     struct bnx2x_phy *phy,
8600                                     u16 edc_mode)
8601 {
8602         switch (phy->type) {
8603         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8604                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8605                 break;
8606         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8607         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8608                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8609                 break;
8610         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8611                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8612                 break;
8613         }
8614 }
8615
8616 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8617                                struct link_params *params)
8618 {
8619         struct bnx2x *bp = params->bp;
8620         u16 edc_mode;
8621         int rc = 0;
8622
8623         u32 val = REG_RD(bp, params->shmem_base +
8624                              offsetof(struct shmem_region, dev_info.
8625                                      port_feature_config[params->port].config));
8626         /* Enabled transmitter by default */
8627         bnx2x_sfp_set_transmitter(params, phy, 1);
8628         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8629                  params->port);
8630         /* Power up module */
8631         bnx2x_power_sfp_module(params, phy, 1);
8632         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8633                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8634                 return -EINVAL;
8635         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8636                 /* Check SFP+ module compatibility */
8637                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8638                 rc = -EINVAL;
8639                 /* Turn on fault module-detected led */
8640                 bnx2x_set_sfp_module_fault_led(params,
8641                                                MISC_REGISTERS_GPIO_HIGH);
8642
8643                 /* Check if need to power down the SFP+ module */
8644                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8645                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8646                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8647                         bnx2x_power_sfp_module(params, phy, 0);
8648                         return rc;
8649                 }
8650         } else {
8651                 /* Turn off fault module-detected led */
8652                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8653         }
8654
8655         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8656          * is done automatically
8657          */
8658         bnx2x_set_limiting_mode(params, phy, edc_mode);
8659
8660         /* Disable transmit for this module if the module is not approved, and
8661          * laser needs to be disabled.
8662          */
8663         if ((rc) &&
8664             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8665              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8666                 bnx2x_sfp_set_transmitter(params, phy, 0);
8667
8668         return rc;
8669 }
8670
8671 void bnx2x_handle_module_detect_int(struct link_params *params)
8672 {
8673         struct bnx2x *bp = params->bp;
8674         struct bnx2x_phy *phy;
8675         u32 gpio_val;
8676         u8 gpio_num, gpio_port;
8677         if (CHIP_IS_E3(bp)) {
8678                 phy = &params->phy[INT_PHY];
8679                 /* Always enable TX laser,will be disabled in case of fault */
8680                 bnx2x_sfp_set_transmitter(params, phy, 1);
8681         } else {
8682                 phy = &params->phy[EXT_PHY1];
8683         }
8684         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8685                                       params->port, &gpio_num, &gpio_port) ==
8686             -EINVAL) {
8687                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8688                 return;
8689         }
8690
8691         /* Set valid module led off */
8692         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8693
8694         /* Get current gpio val reflecting module plugged in / out*/
8695         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8696
8697         /* Call the handling function in case module is detected */
8698         if (gpio_val == 0) {
8699                 bnx2x_set_mdio_emac_per_phy(bp, params);
8700                 bnx2x_set_aer_mmd(params, phy);
8701
8702                 bnx2x_power_sfp_module(params, phy, 1);
8703                 bnx2x_set_gpio_int(bp, gpio_num,
8704                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8705                                    gpio_port);
8706                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8707                         bnx2x_sfp_module_detection(phy, params);
8708                         if (CHIP_IS_E3(bp)) {
8709                                 u16 rx_tx_in_reset;
8710                                 /* In case WC is out of reset, reconfigure the
8711                                  * link speed while taking into account 1G
8712                                  * module limitation.
8713                                  */
8714                                 bnx2x_cl45_read(bp, phy,
8715                                                 MDIO_WC_DEVAD,
8716                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8717                                                 &rx_tx_in_reset);
8718                                 if ((!rx_tx_in_reset) &&
8719                                     (params->link_flags &
8720                                      PHY_INITIALIZED)) {
8721                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8722                                         bnx2x_warpcore_config_sfi(phy, params);
8723                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8724                                 }
8725                         }
8726                 } else {
8727                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8728                 }
8729         } else {
8730                 bnx2x_set_gpio_int(bp, gpio_num,
8731                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8732                                    gpio_port);
8733                 /* Module was plugged out.
8734                  * Disable transmit for this module
8735                  */
8736                 phy->media_type = ETH_PHY_NOT_PRESENT;
8737         }
8738 }
8739
8740 /******************************************************************/
8741 /*              Used by 8706 and 8727                             */
8742 /******************************************************************/
8743 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8744                                  struct bnx2x_phy *phy,
8745                                  u16 alarm_status_offset,
8746                                  u16 alarm_ctrl_offset)
8747 {
8748         u16 alarm_status, val;
8749         bnx2x_cl45_read(bp, phy,
8750                         MDIO_PMA_DEVAD, alarm_status_offset,
8751                         &alarm_status);
8752         bnx2x_cl45_read(bp, phy,
8753                         MDIO_PMA_DEVAD, alarm_status_offset,
8754                         &alarm_status);
8755         /* Mask or enable the fault event. */
8756         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8757         if (alarm_status & (1<<0))
8758                 val &= ~(1<<0);
8759         else
8760                 val |= (1<<0);
8761         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8762 }
8763 /******************************************************************/
8764 /*              common BCM8706/BCM8726 PHY SECTION                */
8765 /******************************************************************/
8766 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8767                                       struct link_params *params,
8768                                       struct link_vars *vars)
8769 {
8770         u8 link_up = 0;
8771         u16 val1, val2, rx_sd, pcs_status;
8772         struct bnx2x *bp = params->bp;
8773         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8774         /* Clear RX Alarm*/
8775         bnx2x_cl45_read(bp, phy,
8776                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8777
8778         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8779                              MDIO_PMA_LASI_TXCTRL);
8780
8781         /* Clear LASI indication*/
8782         bnx2x_cl45_read(bp, phy,
8783                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8784         bnx2x_cl45_read(bp, phy,
8785                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8786         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8787
8788         bnx2x_cl45_read(bp, phy,
8789                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8790         bnx2x_cl45_read(bp, phy,
8791                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8792         bnx2x_cl45_read(bp, phy,
8793                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8794         bnx2x_cl45_read(bp, phy,
8795                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8796
8797         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8798                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8799         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8800          * are set, or if the autoneg bit 1 is set
8801          */
8802         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8803         if (link_up) {
8804                 if (val2 & (1<<1))
8805                         vars->line_speed = SPEED_1000;
8806                 else
8807                         vars->line_speed = SPEED_10000;
8808                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8809                 vars->duplex = DUPLEX_FULL;
8810         }
8811
8812         /* Capture 10G link fault. Read twice to clear stale value. */
8813         if (vars->line_speed == SPEED_10000) {
8814                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8815                             MDIO_PMA_LASI_TXSTAT, &val1);
8816                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8817                             MDIO_PMA_LASI_TXSTAT, &val1);
8818                 if (val1 & (1<<0))
8819                         vars->fault_detected = 1;
8820         }
8821
8822         return link_up;
8823 }
8824
8825 /******************************************************************/
8826 /*                      BCM8706 PHY SECTION                       */
8827 /******************************************************************/
8828 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8829                                  struct link_params *params,
8830                                  struct link_vars *vars)
8831 {
8832         u32 tx_en_mode;
8833         u16 cnt, val, tmp1;
8834         struct bnx2x *bp = params->bp;
8835
8836         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8837                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8838         /* HW reset */
8839         bnx2x_ext_phy_hw_reset(bp, params->port);
8840         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8841         bnx2x_wait_reset_complete(bp, phy, params);
8842
8843         /* Wait until fw is loaded */
8844         for (cnt = 0; cnt < 100; cnt++) {
8845                 bnx2x_cl45_read(bp, phy,
8846                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8847                 if (val)
8848                         break;
8849                 usleep_range(10000, 20000);
8850         }
8851         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8852         if ((params->feature_config_flags &
8853              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8854                 u8 i;
8855                 u16 reg;
8856                 for (i = 0; i < 4; i++) {
8857                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8858                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8859                                    MDIO_XS_8706_REG_BANK_RX0);
8860                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8861                         /* Clear first 3 bits of the control */
8862                         val &= ~0x7;
8863                         /* Set control bits according to configuration */
8864                         val |= (phy->rx_preemphasis[i] & 0x7);
8865                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8866                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8867                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8868                 }
8869         }
8870         /* Force speed */
8871         if (phy->req_line_speed == SPEED_10000) {
8872                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8873
8874                 bnx2x_cl45_write(bp, phy,
8875                                  MDIO_PMA_DEVAD,
8876                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8877                 bnx2x_cl45_write(bp, phy,
8878                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8879                                  0);
8880                 /* Arm LASI for link and Tx fault. */
8881                 bnx2x_cl45_write(bp, phy,
8882                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8883         } else {
8884                 /* Force 1Gbps using autoneg with 1G advertisement */
8885
8886                 /* Allow CL37 through CL73 */
8887                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8888                 bnx2x_cl45_write(bp, phy,
8889                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8890
8891                 /* Enable Full-Duplex advertisement on CL37 */
8892                 bnx2x_cl45_write(bp, phy,
8893                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8894                 /* Enable CL37 AN */
8895                 bnx2x_cl45_write(bp, phy,
8896                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8897                 /* 1G support */
8898                 bnx2x_cl45_write(bp, phy,
8899                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8900
8901                 /* Enable clause 73 AN */
8902                 bnx2x_cl45_write(bp, phy,
8903                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8904                 bnx2x_cl45_write(bp, phy,
8905                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8906                                  0x0400);
8907                 bnx2x_cl45_write(bp, phy,
8908                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8909                                  0x0004);
8910         }
8911         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8912
8913         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8914          * power mode, if TX Laser is disabled
8915          */
8916
8917         tx_en_mode = REG_RD(bp, params->shmem_base +
8918                             offsetof(struct shmem_region,
8919                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8920                         & PORT_HW_CFG_TX_LASER_MASK;
8921
8922         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8923                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8924                 bnx2x_cl45_read(bp, phy,
8925                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8926                 tmp1 |= 0x1;
8927                 bnx2x_cl45_write(bp, phy,
8928                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8929         }
8930
8931         return 0;
8932 }
8933
8934 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8935                                   struct link_params *params,
8936                                   struct link_vars *vars)
8937 {
8938         return bnx2x_8706_8726_read_status(phy, params, vars);
8939 }
8940
8941 /******************************************************************/
8942 /*                      BCM8726 PHY SECTION                       */
8943 /******************************************************************/
8944 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8945                                        struct link_params *params)
8946 {
8947         struct bnx2x *bp = params->bp;
8948         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8949         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8950 }
8951
8952 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8953                                          struct link_params *params)
8954 {
8955         struct bnx2x *bp = params->bp;
8956         /* Need to wait 100ms after reset */
8957         msleep(100);
8958
8959         /* Micro controller re-boot */
8960         bnx2x_cl45_write(bp, phy,
8961                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8962
8963         /* Set soft reset */
8964         bnx2x_cl45_write(bp, phy,
8965                          MDIO_PMA_DEVAD,
8966                          MDIO_PMA_REG_GEN_CTRL,
8967                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8968
8969         bnx2x_cl45_write(bp, phy,
8970                          MDIO_PMA_DEVAD,
8971                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8972
8973         bnx2x_cl45_write(bp, phy,
8974                          MDIO_PMA_DEVAD,
8975                          MDIO_PMA_REG_GEN_CTRL,
8976                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8977
8978         /* Wait for 150ms for microcode load */
8979         msleep(150);
8980
8981         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8982         bnx2x_cl45_write(bp, phy,
8983                          MDIO_PMA_DEVAD,
8984                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8985
8986         msleep(200);
8987         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8988 }
8989
8990 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8991                                  struct link_params *params,
8992                                  struct link_vars *vars)
8993 {
8994         struct bnx2x *bp = params->bp;
8995         u16 val1;
8996         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8997         if (link_up) {
8998                 bnx2x_cl45_read(bp, phy,
8999                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9000                                 &val1);
9001                 if (val1 & (1<<15)) {
9002                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
9003                         link_up = 0;
9004                         vars->line_speed = 0;
9005                 }
9006         }
9007         return link_up;
9008 }
9009
9010
9011 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9012                                   struct link_params *params,
9013                                   struct link_vars *vars)
9014 {
9015         struct bnx2x *bp = params->bp;
9016         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9017
9018         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9019         bnx2x_wait_reset_complete(bp, phy, params);
9020
9021         bnx2x_8726_external_rom_boot(phy, params);
9022
9023         /* Need to call module detected on initialization since the module
9024          * detection triggered by actual module insertion might occur before
9025          * driver is loaded, and when driver is loaded, it reset all
9026          * registers, including the transmitter
9027          */
9028         bnx2x_sfp_module_detection(phy, params);
9029
9030         if (phy->req_line_speed == SPEED_1000) {
9031                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9032                 bnx2x_cl45_write(bp, phy,
9033                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9034                 bnx2x_cl45_write(bp, phy,
9035                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9036                 bnx2x_cl45_write(bp, phy,
9037                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9038                 bnx2x_cl45_write(bp, phy,
9039                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9040                                  0x400);
9041         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9042                    (phy->speed_cap_mask &
9043                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9044                    ((phy->speed_cap_mask &
9045                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9046                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9047                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9048                 /* Set Flow control */
9049                 bnx2x_ext_phy_set_pause(params, phy, vars);
9050                 bnx2x_cl45_write(bp, phy,
9051                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9052                 bnx2x_cl45_write(bp, phy,
9053                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9054                 bnx2x_cl45_write(bp, phy,
9055                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9056                 bnx2x_cl45_write(bp, phy,
9057                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9058                 bnx2x_cl45_write(bp, phy,
9059                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9060                 /* Enable RX-ALARM control to receive interrupt for 1G speed
9061                  * change
9062                  */
9063                 bnx2x_cl45_write(bp, phy,
9064                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9065                 bnx2x_cl45_write(bp, phy,
9066                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9067                                  0x400);
9068
9069         } else { /* Default 10G. Set only LASI control */
9070                 bnx2x_cl45_write(bp, phy,
9071                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9072         }
9073
9074         /* Set TX PreEmphasis if needed */
9075         if ((params->feature_config_flags &
9076              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9077                 DP(NETIF_MSG_LINK,
9078                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9079                          phy->tx_preemphasis[0],
9080                          phy->tx_preemphasis[1]);
9081                 bnx2x_cl45_write(bp, phy,
9082                                  MDIO_PMA_DEVAD,
9083                                  MDIO_PMA_REG_8726_TX_CTRL1,
9084                                  phy->tx_preemphasis[0]);
9085
9086                 bnx2x_cl45_write(bp, phy,
9087                                  MDIO_PMA_DEVAD,
9088                                  MDIO_PMA_REG_8726_TX_CTRL2,
9089                                  phy->tx_preemphasis[1]);
9090         }
9091
9092         return 0;
9093
9094 }
9095
9096 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9097                                   struct link_params *params)
9098 {
9099         struct bnx2x *bp = params->bp;
9100         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9101         /* Set serial boot control for external load */
9102         bnx2x_cl45_write(bp, phy,
9103                          MDIO_PMA_DEVAD,
9104                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9105 }
9106
9107 /******************************************************************/
9108 /*                      BCM8727 PHY SECTION                       */
9109 /******************************************************************/
9110
9111 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9112                                     struct link_params *params, u8 mode)
9113 {
9114         struct bnx2x *bp = params->bp;
9115         u16 led_mode_bitmask = 0;
9116         u16 gpio_pins_bitmask = 0;
9117         u16 val;
9118         /* Only NOC flavor requires to set the LED specifically */
9119         if (!(phy->flags & FLAGS_NOC))
9120                 return;
9121         switch (mode) {
9122         case LED_MODE_FRONT_PANEL_OFF:
9123         case LED_MODE_OFF:
9124                 led_mode_bitmask = 0;
9125                 gpio_pins_bitmask = 0x03;
9126                 break;
9127         case LED_MODE_ON:
9128                 led_mode_bitmask = 0;
9129                 gpio_pins_bitmask = 0x02;
9130                 break;
9131         case LED_MODE_OPER:
9132                 led_mode_bitmask = 0x60;
9133                 gpio_pins_bitmask = 0x11;
9134                 break;
9135         }
9136         bnx2x_cl45_read(bp, phy,
9137                         MDIO_PMA_DEVAD,
9138                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9139                         &val);
9140         val &= 0xff8f;
9141         val |= led_mode_bitmask;
9142         bnx2x_cl45_write(bp, phy,
9143                          MDIO_PMA_DEVAD,
9144                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9145                          val);
9146         bnx2x_cl45_read(bp, phy,
9147                         MDIO_PMA_DEVAD,
9148                         MDIO_PMA_REG_8727_GPIO_CTRL,
9149                         &val);
9150         val &= 0xffe0;
9151         val |= gpio_pins_bitmask;
9152         bnx2x_cl45_write(bp, phy,
9153                          MDIO_PMA_DEVAD,
9154                          MDIO_PMA_REG_8727_GPIO_CTRL,
9155                          val);
9156 }
9157 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9158                                 struct link_params *params) {
9159         u32 swap_val, swap_override;
9160         u8 port;
9161         /* The PHY reset is controlled by GPIO 1. Fake the port number
9162          * to cancel the swap done in set_gpio()
9163          */
9164         struct bnx2x *bp = params->bp;
9165         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9166         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9167         port = (swap_val && swap_override) ^ 1;
9168         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9169                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9170 }
9171
9172 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9173                                     struct link_params *params)
9174 {
9175         struct bnx2x *bp = params->bp;
9176         u16 tmp1, val;
9177         /* Set option 1G speed */
9178         if ((phy->req_line_speed == SPEED_1000) ||
9179             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9180                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9181                 bnx2x_cl45_write(bp, phy,
9182                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9183                 bnx2x_cl45_write(bp, phy,
9184                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9185                 bnx2x_cl45_read(bp, phy,
9186                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9187                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9188                 /* Power down the XAUI until link is up in case of dual-media
9189                  * and 1G
9190                  */
9191                 if (DUAL_MEDIA(params)) {
9192                         bnx2x_cl45_read(bp, phy,
9193                                         MDIO_PMA_DEVAD,
9194                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9195                         val |= (3<<10);
9196                         bnx2x_cl45_write(bp, phy,
9197                                          MDIO_PMA_DEVAD,
9198                                          MDIO_PMA_REG_8727_PCS_GP, val);
9199                 }
9200         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9201                    ((phy->speed_cap_mask &
9202                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9203                    ((phy->speed_cap_mask &
9204                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9205                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9206
9207                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9208                 bnx2x_cl45_write(bp, phy,
9209                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9210                 bnx2x_cl45_write(bp, phy,
9211                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9212         } else {
9213                 /* Since the 8727 has only single reset pin, need to set the 10G
9214                  * registers although it is default
9215                  */
9216                 bnx2x_cl45_write(bp, phy,
9217                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9218                                  0x0020);
9219                 bnx2x_cl45_write(bp, phy,
9220                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9221                 bnx2x_cl45_write(bp, phy,
9222                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9223                 bnx2x_cl45_write(bp, phy,
9224                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9225                                  0x0008);
9226         }
9227 }
9228
9229 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9230                                   struct link_params *params,
9231                                   struct link_vars *vars)
9232 {
9233         u32 tx_en_mode;
9234         u16 tmp1, mod_abs, tmp2;
9235         struct bnx2x *bp = params->bp;
9236         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9237
9238         bnx2x_wait_reset_complete(bp, phy, params);
9239
9240         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9241
9242         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9243         /* Initially configure MOD_ABS to interrupt when module is
9244          * presence( bit 8)
9245          */
9246         bnx2x_cl45_read(bp, phy,
9247                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9248         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9249          * When the EDC is off it locks onto a reference clock and avoids
9250          * becoming 'lost'
9251          */
9252         mod_abs &= ~(1<<8);
9253         if (!(phy->flags & FLAGS_NOC))
9254                 mod_abs &= ~(1<<9);
9255         bnx2x_cl45_write(bp, phy,
9256                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9257
9258         /* Enable/Disable PHY transmitter output */
9259         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9260
9261         bnx2x_8727_power_module(bp, phy, 1);
9262
9263         bnx2x_cl45_read(bp, phy,
9264                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9265
9266         bnx2x_cl45_read(bp, phy,
9267                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9268
9269         bnx2x_8727_config_speed(phy, params);
9270
9271
9272         /* Set TX PreEmphasis if needed */
9273         if ((params->feature_config_flags &
9274              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9275                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9276                            phy->tx_preemphasis[0],
9277                            phy->tx_preemphasis[1]);
9278                 bnx2x_cl45_write(bp, phy,
9279                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9280                                  phy->tx_preemphasis[0]);
9281
9282                 bnx2x_cl45_write(bp, phy,
9283                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9284                                  phy->tx_preemphasis[1]);
9285         }
9286
9287         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9288          * power mode, if TX Laser is disabled
9289          */
9290         tx_en_mode = REG_RD(bp, params->shmem_base +
9291                             offsetof(struct shmem_region,
9292                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9293                         & PORT_HW_CFG_TX_LASER_MASK;
9294
9295         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9296
9297                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9298                 bnx2x_cl45_read(bp, phy,
9299                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9300                 tmp2 |= 0x1000;
9301                 tmp2 &= 0xFFEF;
9302                 bnx2x_cl45_write(bp, phy,
9303                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9304                 bnx2x_cl45_read(bp, phy,
9305                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9306                                 &tmp2);
9307                 bnx2x_cl45_write(bp, phy,
9308                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9309                                  (tmp2 & 0x7fff));
9310         }
9311
9312         return 0;
9313 }
9314
9315 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9316                                       struct link_params *params)
9317 {
9318         struct bnx2x *bp = params->bp;
9319         u16 mod_abs, rx_alarm_status;
9320         u32 val = REG_RD(bp, params->shmem_base +
9321                              offsetof(struct shmem_region, dev_info.
9322                                       port_feature_config[params->port].
9323                                       config));
9324         bnx2x_cl45_read(bp, phy,
9325                         MDIO_PMA_DEVAD,
9326                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9327         if (mod_abs & (1<<8)) {
9328
9329                 /* Module is absent */
9330                 DP(NETIF_MSG_LINK,
9331                    "MOD_ABS indication show module is absent\n");
9332                 phy->media_type = ETH_PHY_NOT_PRESENT;
9333                 /* 1. Set mod_abs to detect next module
9334                  *    presence event
9335                  * 2. Set EDC off by setting OPTXLOS signal input to low
9336                  *    (bit 9).
9337                  *    When the EDC is off it locks onto a reference clock and
9338                  *    avoids becoming 'lost'.
9339                  */
9340                 mod_abs &= ~(1<<8);
9341                 if (!(phy->flags & FLAGS_NOC))
9342                         mod_abs &= ~(1<<9);
9343                 bnx2x_cl45_write(bp, phy,
9344                                  MDIO_PMA_DEVAD,
9345                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9346
9347                 /* Clear RX alarm since it stays up as long as
9348                  * the mod_abs wasn't changed
9349                  */
9350                 bnx2x_cl45_read(bp, phy,
9351                                 MDIO_PMA_DEVAD,
9352                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9353
9354         } else {
9355                 /* Module is present */
9356                 DP(NETIF_MSG_LINK,
9357                    "MOD_ABS indication show module is present\n");
9358                 /* First disable transmitter, and if the module is ok, the
9359                  * module_detection will enable it
9360                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9361                  * 2. Restore the default polarity of the OPRXLOS signal and
9362                  * this signal will then correctly indicate the presence or
9363                  * absence of the Rx signal. (bit 9)
9364                  */
9365                 mod_abs |= (1<<8);
9366                 if (!(phy->flags & FLAGS_NOC))
9367                         mod_abs |= (1<<9);
9368                 bnx2x_cl45_write(bp, phy,
9369                                  MDIO_PMA_DEVAD,
9370                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9371
9372                 /* Clear RX alarm since it stays up as long as the mod_abs
9373                  * wasn't changed. This is need to be done before calling the
9374                  * module detection, otherwise it will clear* the link update
9375                  * alarm
9376                  */
9377                 bnx2x_cl45_read(bp, phy,
9378                                 MDIO_PMA_DEVAD,
9379                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9380
9381
9382                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9383                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9384                         bnx2x_sfp_set_transmitter(params, phy, 0);
9385
9386                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9387                         bnx2x_sfp_module_detection(phy, params);
9388                 else
9389                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9390
9391                 /* Reconfigure link speed based on module type limitations */
9392                 bnx2x_8727_config_speed(phy, params);
9393         }
9394
9395         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9396                    rx_alarm_status);
9397         /* No need to check link status in case of module plugged in/out */
9398 }
9399
9400 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9401                                  struct link_params *params,
9402                                  struct link_vars *vars)
9403
9404 {
9405         struct bnx2x *bp = params->bp;
9406         u8 link_up = 0, oc_port = params->port;
9407         u16 link_status = 0;
9408         u16 rx_alarm_status, lasi_ctrl, val1;
9409
9410         /* If PHY is not initialized, do not check link status */
9411         bnx2x_cl45_read(bp, phy,
9412                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9413                         &lasi_ctrl);
9414         if (!lasi_ctrl)
9415                 return 0;
9416
9417         /* Check the LASI on Rx */
9418         bnx2x_cl45_read(bp, phy,
9419                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9420                         &rx_alarm_status);
9421         vars->line_speed = 0;
9422         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9423
9424         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9425                              MDIO_PMA_LASI_TXCTRL);
9426
9427         bnx2x_cl45_read(bp, phy,
9428                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9429
9430         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9431
9432         /* Clear MSG-OUT */
9433         bnx2x_cl45_read(bp, phy,
9434                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9435
9436         /* If a module is present and there is need to check
9437          * for over current
9438          */
9439         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9440                 /* Check over-current using 8727 GPIO0 input*/
9441                 bnx2x_cl45_read(bp, phy,
9442                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9443                                 &val1);
9444
9445                 if ((val1 & (1<<8)) == 0) {
9446                         if (!CHIP_IS_E1x(bp))
9447                                 oc_port = BP_PATH(bp) + (params->port << 1);
9448                         DP(NETIF_MSG_LINK,
9449                            "8727 Power fault has been detected on port %d\n",
9450                            oc_port);
9451                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9452                                             "been detected and the power to "
9453                                             "that SFP+ module has been removed "
9454                                             "to prevent failure of the card. "
9455                                             "Please remove the SFP+ module and "
9456                                             "restart the system to clear this "
9457                                             "error.\n",
9458                          oc_port);
9459                         /* Disable all RX_ALARMs except for mod_abs */
9460                         bnx2x_cl45_write(bp, phy,
9461                                          MDIO_PMA_DEVAD,
9462                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9463
9464                         bnx2x_cl45_read(bp, phy,
9465                                         MDIO_PMA_DEVAD,
9466                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9467                         /* Wait for module_absent_event */
9468                         val1 |= (1<<8);
9469                         bnx2x_cl45_write(bp, phy,
9470                                          MDIO_PMA_DEVAD,
9471                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9472                         /* Clear RX alarm */
9473                         bnx2x_cl45_read(bp, phy,
9474                                 MDIO_PMA_DEVAD,
9475                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9476                         bnx2x_8727_power_module(params->bp, phy, 0);
9477                         return 0;
9478                 }
9479         } /* Over current check */
9480
9481         /* When module absent bit is set, check module */
9482         if (rx_alarm_status & (1<<5)) {
9483                 bnx2x_8727_handle_mod_abs(phy, params);
9484                 /* Enable all mod_abs and link detection bits */
9485                 bnx2x_cl45_write(bp, phy,
9486                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9487                                  ((1<<5) | (1<<2)));
9488         }
9489
9490         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9491                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9492                 bnx2x_sfp_set_transmitter(params, phy, 1);
9493         } else {
9494                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9495                 return 0;
9496         }
9497
9498         bnx2x_cl45_read(bp, phy,
9499                         MDIO_PMA_DEVAD,
9500                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9501
9502         /* Bits 0..2 --> speed detected,
9503          * Bits 13..15--> link is down
9504          */
9505         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9506                 link_up = 1;
9507                 vars->line_speed = SPEED_10000;
9508                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9509                            params->port);
9510         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9511                 link_up = 1;
9512                 vars->line_speed = SPEED_1000;
9513                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9514                            params->port);
9515         } else {
9516                 link_up = 0;
9517                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9518                            params->port);
9519         }
9520
9521         /* Capture 10G link fault. */
9522         if (vars->line_speed == SPEED_10000) {
9523                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9524                             MDIO_PMA_LASI_TXSTAT, &val1);
9525
9526                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9527                             MDIO_PMA_LASI_TXSTAT, &val1);
9528
9529                 if (val1 & (1<<0)) {
9530                         vars->fault_detected = 1;
9531                 }
9532         }
9533
9534         if (link_up) {
9535                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9536                 vars->duplex = DUPLEX_FULL;
9537                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9538         }
9539
9540         if ((DUAL_MEDIA(params)) &&
9541             (phy->req_line_speed == SPEED_1000)) {
9542                 bnx2x_cl45_read(bp, phy,
9543                                 MDIO_PMA_DEVAD,
9544                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9545                 /* In case of dual-media board and 1G, power up the XAUI side,
9546                  * otherwise power it down. For 10G it is done automatically
9547                  */
9548                 if (link_up)
9549                         val1 &= ~(3<<10);
9550                 else
9551                         val1 |= (3<<10);
9552                 bnx2x_cl45_write(bp, phy,
9553                                  MDIO_PMA_DEVAD,
9554                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9555         }
9556         return link_up;
9557 }
9558
9559 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9560                                   struct link_params *params)
9561 {
9562         struct bnx2x *bp = params->bp;
9563
9564         /* Enable/Disable PHY transmitter output */
9565         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9566
9567         /* Disable Transmitter */
9568         bnx2x_sfp_set_transmitter(params, phy, 0);
9569         /* Clear LASI */
9570         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9571
9572 }
9573
9574 /******************************************************************/
9575 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9576 /******************************************************************/
9577 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9578                                             struct bnx2x *bp,
9579                                             u8 port)
9580 {
9581         u16 val, fw_ver2, cnt, i;
9582         static struct bnx2x_reg_set reg_set[] = {
9583                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9584                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9585                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9586                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9587                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9588         };
9589         u16 fw_ver1;
9590
9591         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9592             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9593                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9594                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9595                                 phy->ver_addr);
9596         } else {
9597                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9598                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9599                 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9600                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9601                                          reg_set[i].reg, reg_set[i].val);
9602
9603                 for (cnt = 0; cnt < 100; cnt++) {
9604                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9605                         if (val & 1)
9606                                 break;
9607                         udelay(5);
9608                 }
9609                 if (cnt == 100) {
9610                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9611                                         "phy fw version(1)\n");
9612                         bnx2x_save_spirom_version(bp, port, 0,
9613                                                   phy->ver_addr);
9614                         return;
9615                 }
9616
9617
9618                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9619                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9620                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9621                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9622                 for (cnt = 0; cnt < 100; cnt++) {
9623                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9624                         if (val & 1)
9625                                 break;
9626                         udelay(5);
9627                 }
9628                 if (cnt == 100) {
9629                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9630                                         "version(2)\n");
9631                         bnx2x_save_spirom_version(bp, port, 0,
9632                                                   phy->ver_addr);
9633                         return;
9634                 }
9635
9636                 /* lower 16 bits of the register SPI_FW_STATUS */
9637                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9638                 /* upper 16 bits of register SPI_FW_STATUS */
9639                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9640
9641                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9642                                           phy->ver_addr);
9643         }
9644
9645 }
9646 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9647                                 struct bnx2x_phy *phy)
9648 {
9649         u16 val, offset, i;
9650         static struct bnx2x_reg_set reg_set[] = {
9651                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9652                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9653                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9654                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9655                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9656                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9657                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9658         };
9659         /* PHYC_CTL_LED_CTL */
9660         bnx2x_cl45_read(bp, phy,
9661                         MDIO_PMA_DEVAD,
9662                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9663         val &= 0xFE00;
9664         val |= 0x0092;
9665
9666         bnx2x_cl45_write(bp, phy,
9667                          MDIO_PMA_DEVAD,
9668                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9669
9670         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9671                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9672                                  reg_set[i].val);
9673
9674         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9675             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9676                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9677         else
9678                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9679
9680         /* stretch_en for LED3*/
9681         bnx2x_cl45_read_or_write(bp, phy,
9682                                  MDIO_PMA_DEVAD, offset,
9683                                  MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9684 }
9685
9686 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9687                                       struct link_params *params,
9688                                       u32 action)
9689 {
9690         struct bnx2x *bp = params->bp;
9691         switch (action) {
9692         case PHY_INIT:
9693                 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9694                     (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9695                         /* Save spirom version */
9696                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9697                 }
9698                 /* This phy uses the NIG latch mechanism since link indication
9699                  * arrives through its LED4 and not via its LASI signal, so we
9700                  * get steady signal instead of clear on read
9701                  */
9702                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9703                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9704
9705                 bnx2x_848xx_set_led(bp, phy);
9706                 break;
9707         }
9708 }
9709
9710 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9711                                        struct link_params *params,
9712                                        struct link_vars *vars)
9713 {
9714         struct bnx2x *bp = params->bp;
9715         u16 autoneg_val, an_1000_val, an_10_100_val;
9716
9717         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9718         bnx2x_cl45_write(bp, phy,
9719                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9720
9721         /* set 1000 speed advertisement */
9722         bnx2x_cl45_read(bp, phy,
9723                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9724                         &an_1000_val);
9725
9726         bnx2x_ext_phy_set_pause(params, phy, vars);
9727         bnx2x_cl45_read(bp, phy,
9728                         MDIO_AN_DEVAD,
9729                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9730                         &an_10_100_val);
9731         bnx2x_cl45_read(bp, phy,
9732                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9733                         &autoneg_val);
9734         /* Disable forced speed */
9735         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9736         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9737
9738         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9739              (phy->speed_cap_mask &
9740              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9741             (phy->req_line_speed == SPEED_1000)) {
9742                 an_1000_val |= (1<<8);
9743                 autoneg_val |= (1<<9 | 1<<12);
9744                 if (phy->req_duplex == DUPLEX_FULL)
9745                         an_1000_val |= (1<<9);
9746                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9747         } else
9748                 an_1000_val &= ~((1<<8) | (1<<9));
9749
9750         bnx2x_cl45_write(bp, phy,
9751                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9752                          an_1000_val);
9753
9754         /* set 100 speed advertisement */
9755         if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9756              (phy->speed_cap_mask &
9757               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9758                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9759                 an_10_100_val |= (1<<7);
9760                 /* Enable autoneg and restart autoneg for legacy speeds */
9761                 autoneg_val |= (1<<9 | 1<<12);
9762
9763                 if (phy->req_duplex == DUPLEX_FULL)
9764                         an_10_100_val |= (1<<8);
9765                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9766         }
9767         /* set 10 speed advertisement */
9768         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9769              (phy->speed_cap_mask &
9770               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9771                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9772              (phy->supported &
9773               (SUPPORTED_10baseT_Half |
9774                SUPPORTED_10baseT_Full)))) {
9775                 an_10_100_val |= (1<<5);
9776                 autoneg_val |= (1<<9 | 1<<12);
9777                 if (phy->req_duplex == DUPLEX_FULL)
9778                         an_10_100_val |= (1<<6);
9779                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9780         }
9781
9782         /* Only 10/100 are allowed to work in FORCE mode */
9783         if ((phy->req_line_speed == SPEED_100) &&
9784             (phy->supported &
9785              (SUPPORTED_100baseT_Half |
9786               SUPPORTED_100baseT_Full))) {
9787                 autoneg_val |= (1<<13);
9788                 /* Enabled AUTO-MDIX when autoneg is disabled */
9789                 bnx2x_cl45_write(bp, phy,
9790                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9791                                  (1<<15 | 1<<9 | 7<<0));
9792                 /* The PHY needs this set even for forced link. */
9793                 an_10_100_val |= (1<<8) | (1<<7);
9794                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9795         }
9796         if ((phy->req_line_speed == SPEED_10) &&
9797             (phy->supported &
9798              (SUPPORTED_10baseT_Half |
9799               SUPPORTED_10baseT_Full))) {
9800                 /* Enabled AUTO-MDIX when autoneg is disabled */
9801                 bnx2x_cl45_write(bp, phy,
9802                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9803                                  (1<<15 | 1<<9 | 7<<0));
9804                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9805         }
9806
9807         bnx2x_cl45_write(bp, phy,
9808                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9809                          an_10_100_val);
9810
9811         if (phy->req_duplex == DUPLEX_FULL)
9812                 autoneg_val |= (1<<8);
9813
9814         /* Always write this if this is not 84833/4.
9815          * For 84833/4, write it only when it's a forced speed.
9816          */
9817         if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9818              (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9819             ((autoneg_val & (1<<12)) == 0))
9820                 bnx2x_cl45_write(bp, phy,
9821                          MDIO_AN_DEVAD,
9822                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9823
9824         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9825             (phy->speed_cap_mask &
9826              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9827                 (phy->req_line_speed == SPEED_10000)) {
9828                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9829                         /* Restart autoneg for 10G*/
9830
9831                         bnx2x_cl45_read_or_write(
9832                                 bp, phy,
9833                                 MDIO_AN_DEVAD,
9834                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9835                                 0x1000);
9836                         bnx2x_cl45_write(bp, phy,
9837                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9838                                          0x3200);
9839         } else
9840                 bnx2x_cl45_write(bp, phy,
9841                                  MDIO_AN_DEVAD,
9842                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9843                                  1);
9844
9845         return 0;
9846 }
9847
9848 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9849                                   struct link_params *params,
9850                                   struct link_vars *vars)
9851 {
9852         struct bnx2x *bp = params->bp;
9853         /* Restore normal power mode*/
9854         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9855                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9856
9857         /* HW reset */
9858         bnx2x_ext_phy_hw_reset(bp, params->port);
9859         bnx2x_wait_reset_complete(bp, phy, params);
9860
9861         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9862         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9863 }
9864
9865 #define PHY84833_CMDHDLR_WAIT 300
9866 #define PHY84833_CMDHDLR_MAX_ARGS 5
9867 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9868                                 struct link_params *params, u16 fw_cmd,
9869                                 u16 cmd_args[], int argc)
9870 {
9871         int idx;
9872         u16 val;
9873         struct bnx2x *bp = params->bp;
9874         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9875         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9876                         MDIO_84833_CMD_HDLR_STATUS,
9877                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9878         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9879                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9880                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9881                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9882                         break;
9883                 usleep_range(1000, 2000);
9884         }
9885         if (idx >= PHY84833_CMDHDLR_WAIT) {
9886                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9887                 return -EINVAL;
9888         }
9889
9890         /* Prepare argument(s) and issue command */
9891         for (idx = 0; idx < argc; idx++) {
9892                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9893                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9894                                 cmd_args[idx]);
9895         }
9896         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9897                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9898         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9899                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9900                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9901                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9902                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9903                         break;
9904                 usleep_range(1000, 2000);
9905         }
9906         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9907                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9908                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9909                 return -EINVAL;
9910         }
9911         /* Gather returning data */
9912         for (idx = 0; idx < argc; idx++) {
9913                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9914                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9915                                 &cmd_args[idx]);
9916         }
9917         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9918                         MDIO_84833_CMD_HDLR_STATUS,
9919                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9920         return 0;
9921 }
9922
9923 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9924                                    struct link_params *params,
9925                                    struct link_vars *vars)
9926 {
9927         u32 pair_swap;
9928         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9929         int status;
9930         struct bnx2x *bp = params->bp;
9931
9932         /* Check for configuration. */
9933         pair_swap = REG_RD(bp, params->shmem_base +
9934                            offsetof(struct shmem_region,
9935                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9936                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9937
9938         if (pair_swap == 0)
9939                 return 0;
9940
9941         /* Only the second argument is used for this command */
9942         data[1] = (u16)pair_swap;
9943
9944         status = bnx2x_84833_cmd_hdlr(phy, params,
9945                 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9946         if (status == 0)
9947                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9948
9949         return status;
9950 }
9951
9952 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9953                                       u32 shmem_base_path[],
9954                                       u32 chip_id)
9955 {
9956         u32 reset_pin[2];
9957         u32 idx;
9958         u8 reset_gpios;
9959         if (CHIP_IS_E3(bp)) {
9960                 /* Assume that these will be GPIOs, not EPIOs. */
9961                 for (idx = 0; idx < 2; idx++) {
9962                         /* Map config param to register bit. */
9963                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9964                                 offsetof(struct shmem_region,
9965                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9966                         reset_pin[idx] = (reset_pin[idx] &
9967                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9968                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9969                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9970                         reset_pin[idx] = (1 << reset_pin[idx]);
9971                 }
9972                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9973         } else {
9974                 /* E2, look from diff place of shmem. */
9975                 for (idx = 0; idx < 2; idx++) {
9976                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9977                                 offsetof(struct shmem_region,
9978                                 dev_info.port_hw_config[0].default_cfg));
9979                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9980                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9981                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9982                         reset_pin[idx] = (1 << reset_pin[idx]);
9983                 }
9984                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9985         }
9986
9987         return reset_gpios;
9988 }
9989
9990 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9991                                 struct link_params *params)
9992 {
9993         struct bnx2x *bp = params->bp;
9994         u8 reset_gpios;
9995         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9996                                 offsetof(struct shmem2_region,
9997                                 other_shmem_base_addr));
9998
9999         u32 shmem_base_path[2];
10000
10001         /* Work around for 84833 LED failure inside RESET status */
10002         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10003                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10004                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10005         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10006                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10007                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10008
10009         shmem_base_path[0] = params->shmem_base;
10010         shmem_base_path[1] = other_shmem_base_addr;
10011
10012         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10013                                                   params->chip_id);
10014
10015         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10016         udelay(10);
10017         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10018                 reset_gpios);
10019
10020         return 0;
10021 }
10022
10023 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10024                                    struct link_params *params,
10025                                    struct link_vars *vars)
10026 {
10027         int rc;
10028         struct bnx2x *bp = params->bp;
10029         u16 cmd_args = 0;
10030
10031         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10032
10033         /* Prevent Phy from working in EEE and advertising it */
10034         rc = bnx2x_84833_cmd_hdlr(phy, params,
10035                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10036         if (rc) {
10037                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10038                 return rc;
10039         }
10040
10041         return bnx2x_eee_disable(phy, params, vars);
10042 }
10043
10044 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10045                                    struct link_params *params,
10046                                    struct link_vars *vars)
10047 {
10048         int rc;
10049         struct bnx2x *bp = params->bp;
10050         u16 cmd_args = 1;
10051
10052         rc = bnx2x_84833_cmd_hdlr(phy, params,
10053                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10054         if (rc) {
10055                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10056                 return rc;
10057         }
10058
10059         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10060 }
10061
10062 #define PHY84833_CONSTANT_LATENCY 1193
10063 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10064                                    struct link_params *params,
10065                                    struct link_vars *vars)
10066 {
10067         struct bnx2x *bp = params->bp;
10068         u8 port, initialize = 1;
10069         u16 val;
10070         u32 actual_phy_selection;
10071         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10072         int rc = 0;
10073
10074         usleep_range(1000, 2000);
10075
10076         if (!(CHIP_IS_E1x(bp)))
10077                 port = BP_PATH(bp);
10078         else
10079                 port = params->port;
10080
10081         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10082                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10083                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10084                                port);
10085         } else {
10086                 /* MDIO reset */
10087                 bnx2x_cl45_write(bp, phy,
10088                                 MDIO_PMA_DEVAD,
10089                                 MDIO_PMA_REG_CTRL, 0x8000);
10090         }
10091
10092         bnx2x_wait_reset_complete(bp, phy, params);
10093
10094         /* Wait for GPHY to come out of reset */
10095         msleep(50);
10096         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10097             (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10098                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10099                  * behavior.
10100                  */
10101                 u16 temp;
10102                 temp = vars->line_speed;
10103                 vars->line_speed = SPEED_10000;
10104                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10105                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10106                 vars->line_speed = temp;
10107         }
10108
10109         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10110                         MDIO_CTL_REG_84823_MEDIA, &val);
10111         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10112                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10113                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10114                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10115                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10116
10117         if (CHIP_IS_E3(bp)) {
10118                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10119                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10120         } else {
10121                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10122                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10123         }
10124
10125         actual_phy_selection = bnx2x_phy_selection(params);
10126
10127         switch (actual_phy_selection) {
10128         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10129                 /* Do nothing. Essentially this is like the priority copper */
10130                 break;
10131         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10132                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10133                 break;
10134         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10135                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10136                 break;
10137         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10138                 /* Do nothing here. The first PHY won't be initialized at all */
10139                 break;
10140         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10141                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10142                 initialize = 0;
10143                 break;
10144         }
10145         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10146                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10147
10148         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10149                          MDIO_CTL_REG_84823_MEDIA, val);
10150         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10151                    params->multi_phy_config, val);
10152
10153         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10154             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10155                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10156
10157                 /* Keep AutogrEEEn disabled. */
10158                 cmd_args[0] = 0x0;
10159                 cmd_args[1] = 0x0;
10160                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10161                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10162                 rc = bnx2x_84833_cmd_hdlr(phy, params,
10163                         PHY84833_CMD_SET_EEE_MODE, cmd_args,
10164                         PHY84833_CMDHDLR_MAX_ARGS);
10165                 if (rc)
10166                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10167         }
10168         if (initialize)
10169                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10170         else
10171                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10172         /* 84833 PHY has a better feature and doesn't need to support this. */
10173         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10174                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10175                         offsetof(struct shmem_region,
10176                         dev_info.port_hw_config[params->port].default_cfg)) &
10177                         PORT_HW_CFG_ENABLE_CMS_MASK;
10178
10179                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10180                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10181                 if (cms_enable)
10182                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10183                 else
10184                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10185                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10186                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10187         }
10188
10189         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10190                         MDIO_84833_TOP_CFG_FW_REV, &val);
10191
10192         /* Configure EEE support */
10193         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10194             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10195             bnx2x_eee_has_cap(params)) {
10196                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10197                 if (rc) {
10198                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10199                         bnx2x_8483x_disable_eee(phy, params, vars);
10200                         return rc;
10201                 }
10202
10203                 if ((phy->req_duplex == DUPLEX_FULL) &&
10204                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10205                     (bnx2x_eee_calc_timer(params) ||
10206                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10207                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10208                 else
10209                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10210                 if (rc) {
10211                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10212                         return rc;
10213                 }
10214         } else {
10215                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10216         }
10217
10218         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10219             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10220                 /* Bring PHY out of super isolate mode as the final step. */
10221                 bnx2x_cl45_read_and_write(bp, phy,
10222                                           MDIO_CTL_DEVAD,
10223                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10224                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10225         }
10226         return rc;
10227 }
10228
10229 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10230                                   struct link_params *params,
10231                                   struct link_vars *vars)
10232 {
10233         struct bnx2x *bp = params->bp;
10234         u16 val, val1, val2;
10235         u8 link_up = 0;
10236
10237
10238         /* Check 10G-BaseT link status */
10239         /* Check PMD signal ok */
10240         bnx2x_cl45_read(bp, phy,
10241                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10242         bnx2x_cl45_read(bp, phy,
10243                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10244                         &val2);
10245         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10246
10247         /* Check link 10G */
10248         if (val2 & (1<<11)) {
10249                 vars->line_speed = SPEED_10000;
10250                 vars->duplex = DUPLEX_FULL;
10251                 link_up = 1;
10252                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10253         } else { /* Check Legacy speed link */
10254                 u16 legacy_status, legacy_speed;
10255
10256                 /* Enable expansion register 0x42 (Operation mode status) */
10257                 bnx2x_cl45_write(bp, phy,
10258                                  MDIO_AN_DEVAD,
10259                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10260
10261                 /* Get legacy speed operation status */
10262                 bnx2x_cl45_read(bp, phy,
10263                                 MDIO_AN_DEVAD,
10264                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10265                                 &legacy_status);
10266
10267                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10268                    legacy_status);
10269                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10270                 legacy_speed = (legacy_status & (3<<9));
10271                 if (legacy_speed == (0<<9))
10272                         vars->line_speed = SPEED_10;
10273                 else if (legacy_speed == (1<<9))
10274                         vars->line_speed = SPEED_100;
10275                 else if (legacy_speed == (2<<9))
10276                         vars->line_speed = SPEED_1000;
10277                 else { /* Should not happen: Treat as link down */
10278                         vars->line_speed = 0;
10279                         link_up = 0;
10280                 }
10281
10282                 if (link_up) {
10283                         if (legacy_status & (1<<8))
10284                                 vars->duplex = DUPLEX_FULL;
10285                         else
10286                                 vars->duplex = DUPLEX_HALF;
10287
10288                         DP(NETIF_MSG_LINK,
10289                            "Link is up in %dMbps, is_duplex_full= %d\n",
10290                            vars->line_speed,
10291                            (vars->duplex == DUPLEX_FULL));
10292                         /* Check legacy speed AN resolution */
10293                         bnx2x_cl45_read(bp, phy,
10294                                         MDIO_AN_DEVAD,
10295                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10296                                         &val);
10297                         if (val & (1<<5))
10298                                 vars->link_status |=
10299                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10300                         bnx2x_cl45_read(bp, phy,
10301                                         MDIO_AN_DEVAD,
10302                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10303                                         &val);
10304                         if ((val & (1<<0)) == 0)
10305                                 vars->link_status |=
10306                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10307                 }
10308         }
10309         if (link_up) {
10310                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10311                            vars->line_speed);
10312                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10313
10314                 /* Read LP advertised speeds */
10315                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10316                                 MDIO_AN_REG_CL37_FC_LP, &val);
10317                 if (val & (1<<5))
10318                         vars->link_status |=
10319                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10320                 if (val & (1<<6))
10321                         vars->link_status |=
10322                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10323                 if (val & (1<<7))
10324                         vars->link_status |=
10325                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10326                 if (val & (1<<8))
10327                         vars->link_status |=
10328                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10329                 if (val & (1<<9))
10330                         vars->link_status |=
10331                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10332
10333                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10334                                 MDIO_AN_REG_1000T_STATUS, &val);
10335
10336                 if (val & (1<<10))
10337                         vars->link_status |=
10338                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10339                 if (val & (1<<11))
10340                         vars->link_status |=
10341                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10342
10343                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10344                                 MDIO_AN_REG_MASTER_STATUS, &val);
10345
10346                 if (val & (1<<11))
10347                         vars->link_status |=
10348                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10349
10350                 /* Determine if EEE was negotiated */
10351                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10352                     (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10353                         bnx2x_eee_an_resolve(phy, params, vars);
10354         }
10355
10356         return link_up;
10357 }
10358
10359 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10360 {
10361         int status = 0;
10362         u32 spirom_ver;
10363         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10364         status = bnx2x_format_ver(spirom_ver, str, len);
10365         return status;
10366 }
10367
10368 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10369                                 struct link_params *params)
10370 {
10371         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10372                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10373         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10374                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10375 }
10376
10377 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10378                                         struct link_params *params)
10379 {
10380         bnx2x_cl45_write(params->bp, phy,
10381                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10382         bnx2x_cl45_write(params->bp, phy,
10383                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10384 }
10385
10386 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10387                                    struct link_params *params)
10388 {
10389         struct bnx2x *bp = params->bp;
10390         u8 port;
10391         u16 val16;
10392
10393         if (!(CHIP_IS_E1x(bp)))
10394                 port = BP_PATH(bp);
10395         else
10396                 port = params->port;
10397
10398         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10399                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10400                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10401                                port);
10402         } else {
10403                 bnx2x_cl45_read(bp, phy,
10404                                 MDIO_CTL_DEVAD,
10405                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10406                 val16 |= MDIO_84833_SUPER_ISOLATE;
10407                 bnx2x_cl45_write(bp, phy,
10408                                  MDIO_CTL_DEVAD,
10409                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10410         }
10411 }
10412
10413 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10414                                      struct link_params *params, u8 mode)
10415 {
10416         struct bnx2x *bp = params->bp;
10417         u16 val;
10418         u8 port;
10419
10420         if (!(CHIP_IS_E1x(bp)))
10421                 port = BP_PATH(bp);
10422         else
10423                 port = params->port;
10424
10425         switch (mode) {
10426         case LED_MODE_OFF:
10427
10428                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10429
10430                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10431                     SHARED_HW_CFG_LED_EXTPHY1) {
10432
10433                         /* Set LED masks */
10434                         bnx2x_cl45_write(bp, phy,
10435                                         MDIO_PMA_DEVAD,
10436                                         MDIO_PMA_REG_8481_LED1_MASK,
10437                                         0x0);
10438
10439                         bnx2x_cl45_write(bp, phy,
10440                                         MDIO_PMA_DEVAD,
10441                                         MDIO_PMA_REG_8481_LED2_MASK,
10442                                         0x0);
10443
10444                         bnx2x_cl45_write(bp, phy,
10445                                         MDIO_PMA_DEVAD,
10446                                         MDIO_PMA_REG_8481_LED3_MASK,
10447                                         0x0);
10448
10449                         bnx2x_cl45_write(bp, phy,
10450                                         MDIO_PMA_DEVAD,
10451                                         MDIO_PMA_REG_8481_LED5_MASK,
10452                                         0x0);
10453
10454                 } else {
10455                         bnx2x_cl45_write(bp, phy,
10456                                          MDIO_PMA_DEVAD,
10457                                          MDIO_PMA_REG_8481_LED1_MASK,
10458                                          0x0);
10459                 }
10460                 break;
10461         case LED_MODE_FRONT_PANEL_OFF:
10462
10463                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10464                    port);
10465
10466                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10467                     SHARED_HW_CFG_LED_EXTPHY1) {
10468
10469                         /* Set LED masks */
10470                         bnx2x_cl45_write(bp, phy,
10471                                          MDIO_PMA_DEVAD,
10472                                          MDIO_PMA_REG_8481_LED1_MASK,
10473                                          0x0);
10474
10475                         bnx2x_cl45_write(bp, phy,
10476                                          MDIO_PMA_DEVAD,
10477                                          MDIO_PMA_REG_8481_LED2_MASK,
10478                                          0x0);
10479
10480                         bnx2x_cl45_write(bp, phy,
10481                                          MDIO_PMA_DEVAD,
10482                                          MDIO_PMA_REG_8481_LED3_MASK,
10483                                          0x0);
10484
10485                         bnx2x_cl45_write(bp, phy,
10486                                          MDIO_PMA_DEVAD,
10487                                          MDIO_PMA_REG_8481_LED5_MASK,
10488                                          0x20);
10489
10490                 } else {
10491                         bnx2x_cl45_write(bp, phy,
10492                                          MDIO_PMA_DEVAD,
10493                                          MDIO_PMA_REG_8481_LED1_MASK,
10494                                          0x0);
10495                         if (phy->type ==
10496                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10497                                 /* Disable MI_INT interrupt before setting LED4
10498                                  * source to constant off.
10499                                  */
10500                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10501                                            params->port*4) &
10502                                     NIG_MASK_MI_INT) {
10503                                         params->link_flags |=
10504                                         LINK_FLAGS_INT_DISABLED;
10505
10506                                         bnx2x_bits_dis(
10507                                                 bp,
10508                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10509                                                 params->port*4,
10510                                                 NIG_MASK_MI_INT);
10511                                 }
10512                                 bnx2x_cl45_write(bp, phy,
10513                                                  MDIO_PMA_DEVAD,
10514                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10515                                                  0x0);
10516                         }
10517                 }
10518                 break;
10519         case LED_MODE_ON:
10520
10521                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10522
10523                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10524                     SHARED_HW_CFG_LED_EXTPHY1) {
10525                         /* Set control reg */
10526                         bnx2x_cl45_read(bp, phy,
10527                                         MDIO_PMA_DEVAD,
10528                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10529                                         &val);
10530                         val &= 0x8000;
10531                         val |= 0x2492;
10532
10533                         bnx2x_cl45_write(bp, phy,
10534                                          MDIO_PMA_DEVAD,
10535                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10536                                          val);
10537
10538                         /* Set LED masks */
10539                         bnx2x_cl45_write(bp, phy,
10540                                          MDIO_PMA_DEVAD,
10541                                          MDIO_PMA_REG_8481_LED1_MASK,
10542                                          0x0);
10543
10544                         bnx2x_cl45_write(bp, phy,
10545                                          MDIO_PMA_DEVAD,
10546                                          MDIO_PMA_REG_8481_LED2_MASK,
10547                                          0x20);
10548
10549                         bnx2x_cl45_write(bp, phy,
10550                                          MDIO_PMA_DEVAD,
10551                                          MDIO_PMA_REG_8481_LED3_MASK,
10552                                          0x20);
10553
10554                         bnx2x_cl45_write(bp, phy,
10555                                          MDIO_PMA_DEVAD,
10556                                          MDIO_PMA_REG_8481_LED5_MASK,
10557                                          0x0);
10558                 } else {
10559                         bnx2x_cl45_write(bp, phy,
10560                                          MDIO_PMA_DEVAD,
10561                                          MDIO_PMA_REG_8481_LED1_MASK,
10562                                          0x20);
10563                         if (phy->type ==
10564                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10565                                 /* Disable MI_INT interrupt before setting LED4
10566                                  * source to constant on.
10567                                  */
10568                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10569                                            params->port*4) &
10570                                     NIG_MASK_MI_INT) {
10571                                         params->link_flags |=
10572                                         LINK_FLAGS_INT_DISABLED;
10573
10574                                         bnx2x_bits_dis(
10575                                                 bp,
10576                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10577                                                 params->port*4,
10578                                                 NIG_MASK_MI_INT);
10579                                 }
10580                                 bnx2x_cl45_write(bp, phy,
10581                                                  MDIO_PMA_DEVAD,
10582                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10583                                                  0x20);
10584                         }
10585                 }
10586                 break;
10587
10588         case LED_MODE_OPER:
10589
10590                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10591
10592                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10593                     SHARED_HW_CFG_LED_EXTPHY1) {
10594
10595                         /* Set control reg */
10596                         bnx2x_cl45_read(bp, phy,
10597                                         MDIO_PMA_DEVAD,
10598                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10599                                         &val);
10600
10601                         if (!((val &
10602                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10603                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10604                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10605                                 bnx2x_cl45_write(bp, phy,
10606                                                  MDIO_PMA_DEVAD,
10607                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10608                                                  0xa492);
10609                         }
10610
10611                         /* Set LED masks */
10612                         bnx2x_cl45_write(bp, phy,
10613                                          MDIO_PMA_DEVAD,
10614                                          MDIO_PMA_REG_8481_LED1_MASK,
10615                                          0x10);
10616
10617                         bnx2x_cl45_write(bp, phy,
10618                                          MDIO_PMA_DEVAD,
10619                                          MDIO_PMA_REG_8481_LED2_MASK,
10620                                          0x80);
10621
10622                         bnx2x_cl45_write(bp, phy,
10623                                          MDIO_PMA_DEVAD,
10624                                          MDIO_PMA_REG_8481_LED3_MASK,
10625                                          0x98);
10626
10627                         bnx2x_cl45_write(bp, phy,
10628                                          MDIO_PMA_DEVAD,
10629                                          MDIO_PMA_REG_8481_LED5_MASK,
10630                                          0x40);
10631
10632                 } else {
10633                         bnx2x_cl45_write(bp, phy,
10634                                          MDIO_PMA_DEVAD,
10635                                          MDIO_PMA_REG_8481_LED1_MASK,
10636                                          0x80);
10637
10638                         /* Tell LED3 to blink on source */
10639                         bnx2x_cl45_read(bp, phy,
10640                                         MDIO_PMA_DEVAD,
10641                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10642                                         &val);
10643                         val &= ~(7<<6);
10644                         val |= (1<<6); /* A83B[8:6]= 1 */
10645                         bnx2x_cl45_write(bp, phy,
10646                                          MDIO_PMA_DEVAD,
10647                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10648                                          val);
10649                         if (phy->type ==
10650                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10651                                 /* Restore LED4 source to external link,
10652                                  * and re-enable interrupts.
10653                                  */
10654                                 bnx2x_cl45_write(bp, phy,
10655                                                  MDIO_PMA_DEVAD,
10656                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10657                                                  0x40);
10658                                 if (params->link_flags &
10659                                     LINK_FLAGS_INT_DISABLED) {
10660                                         bnx2x_link_int_enable(params);
10661                                         params->link_flags &=
10662                                                 ~LINK_FLAGS_INT_DISABLED;
10663                                 }
10664                         }
10665                 }
10666                 break;
10667         }
10668
10669         /* This is a workaround for E3+84833 until autoneg
10670          * restart is fixed in f/w
10671          */
10672         if (CHIP_IS_E3(bp)) {
10673                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10674                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10675         }
10676 }
10677
10678 /******************************************************************/
10679 /*                      54618SE PHY SECTION                       */
10680 /******************************************************************/
10681 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10682                                         struct link_params *params,
10683                                         u32 action)
10684 {
10685         struct bnx2x *bp = params->bp;
10686         u16 temp;
10687         switch (action) {
10688         case PHY_INIT:
10689                 /* Configure LED4: set to INTR (0x6). */
10690                 /* Accessing shadow register 0xe. */
10691                 bnx2x_cl22_write(bp, phy,
10692                                  MDIO_REG_GPHY_SHADOW,
10693                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
10694                 bnx2x_cl22_read(bp, phy,
10695                                 MDIO_REG_GPHY_SHADOW,
10696                                 &temp);
10697                 temp &= ~(0xf << 4);
10698                 temp |= (0x6 << 4);
10699                 bnx2x_cl22_write(bp, phy,
10700                                  MDIO_REG_GPHY_SHADOW,
10701                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10702                 /* Configure INTR based on link status change. */
10703                 bnx2x_cl22_write(bp, phy,
10704                                  MDIO_REG_INTR_MASK,
10705                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
10706                 break;
10707         }
10708 }
10709
10710 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10711                                                struct link_params *params,
10712                                                struct link_vars *vars)
10713 {
10714         struct bnx2x *bp = params->bp;
10715         u8 port;
10716         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10717         u32 cfg_pin;
10718
10719         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10720         usleep_range(1000, 2000);
10721
10722         /* This works with E3 only, no need to check the chip
10723          * before determining the port.
10724          */
10725         port = params->port;
10726
10727         cfg_pin = (REG_RD(bp, params->shmem_base +
10728                         offsetof(struct shmem_region,
10729                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10730                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10731                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10732
10733         /* Drive pin high to bring the GPHY out of reset. */
10734         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10735
10736         /* wait for GPHY to reset */
10737         msleep(50);
10738
10739         /* reset phy */
10740         bnx2x_cl22_write(bp, phy,
10741                          MDIO_PMA_REG_CTRL, 0x8000);
10742         bnx2x_wait_reset_complete(bp, phy, params);
10743
10744         /* Wait for GPHY to reset */
10745         msleep(50);
10746
10747
10748         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10749         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10750         bnx2x_cl22_write(bp, phy,
10751                         MDIO_REG_GPHY_SHADOW,
10752                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10753         bnx2x_cl22_read(bp, phy,
10754                         MDIO_REG_GPHY_SHADOW,
10755                         &temp);
10756         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10757         bnx2x_cl22_write(bp, phy,
10758                         MDIO_REG_GPHY_SHADOW,
10759                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10760
10761         /* Set up fc */
10762         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10763         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10764         fc_val = 0;
10765         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10766                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10767                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10768
10769         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10770                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10771                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10772
10773         /* Read all advertisement */
10774         bnx2x_cl22_read(bp, phy,
10775                         0x09,
10776                         &an_1000_val);
10777
10778         bnx2x_cl22_read(bp, phy,
10779                         0x04,
10780                         &an_10_100_val);
10781
10782         bnx2x_cl22_read(bp, phy,
10783                         MDIO_PMA_REG_CTRL,
10784                         &autoneg_val);
10785
10786         /* Disable forced speed */
10787         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10788         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10789                            (1<<11));
10790
10791         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10792                         (phy->speed_cap_mask &
10793                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10794                         (phy->req_line_speed == SPEED_1000)) {
10795                 an_1000_val |= (1<<8);
10796                 autoneg_val |= (1<<9 | 1<<12);
10797                 if (phy->req_duplex == DUPLEX_FULL)
10798                         an_1000_val |= (1<<9);
10799                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10800         } else
10801                 an_1000_val &= ~((1<<8) | (1<<9));
10802
10803         bnx2x_cl22_write(bp, phy,
10804                         0x09,
10805                         an_1000_val);
10806         bnx2x_cl22_read(bp, phy,
10807                         0x09,
10808                         &an_1000_val);
10809
10810         /* Set 100 speed advertisement */
10811         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10812                         (phy->speed_cap_mask &
10813                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10814                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10815                 an_10_100_val |= (1<<7);
10816                 /* Enable autoneg and restart autoneg for legacy speeds */
10817                 autoneg_val |= (1<<9 | 1<<12);
10818
10819                 if (phy->req_duplex == DUPLEX_FULL)
10820                         an_10_100_val |= (1<<8);
10821                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10822         }
10823
10824         /* Set 10 speed advertisement */
10825         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10826                         (phy->speed_cap_mask &
10827                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10828                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10829                 an_10_100_val |= (1<<5);
10830                 autoneg_val |= (1<<9 | 1<<12);
10831                 if (phy->req_duplex == DUPLEX_FULL)
10832                         an_10_100_val |= (1<<6);
10833                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10834         }
10835
10836         /* Only 10/100 are allowed to work in FORCE mode */
10837         if (phy->req_line_speed == SPEED_100) {
10838                 autoneg_val |= (1<<13);
10839                 /* Enabled AUTO-MDIX when autoneg is disabled */
10840                 bnx2x_cl22_write(bp, phy,
10841                                 0x18,
10842                                 (1<<15 | 1<<9 | 7<<0));
10843                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10844         }
10845         if (phy->req_line_speed == SPEED_10) {
10846                 /* Enabled AUTO-MDIX when autoneg is disabled */
10847                 bnx2x_cl22_write(bp, phy,
10848                                 0x18,
10849                                 (1<<15 | 1<<9 | 7<<0));
10850                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10851         }
10852
10853         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10854                 int rc;
10855
10856                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10857                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
10858                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10859                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10860                 temp &= 0xfffe;
10861                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10862
10863                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10864                 if (rc) {
10865                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10866                         bnx2x_eee_disable(phy, params, vars);
10867                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10868                            (phy->req_duplex == DUPLEX_FULL) &&
10869                            (bnx2x_eee_calc_timer(params) ||
10870                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10871                         /* Need to advertise EEE only when requested,
10872                          * and either no LPI assertion was requested,
10873                          * or it was requested and a valid timer was set.
10874                          * Also notice full duplex is required for EEE.
10875                          */
10876                         bnx2x_eee_advertise(phy, params, vars,
10877                                             SHMEM_EEE_1G_ADV);
10878                 } else {
10879                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10880                         bnx2x_eee_disable(phy, params, vars);
10881                 }
10882         } else {
10883                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10884                                     SHMEM_EEE_SUPPORTED_SHIFT;
10885
10886                 if (phy->flags & FLAGS_EEE) {
10887                         /* Handle legacy auto-grEEEn */
10888                         if (params->feature_config_flags &
10889                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10890                                 temp = 6;
10891                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10892                         } else {
10893                                 temp = 0;
10894                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10895                         }
10896                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10897                                          MDIO_AN_REG_EEE_ADV, temp);
10898                 }
10899         }
10900
10901         bnx2x_cl22_write(bp, phy,
10902                         0x04,
10903                         an_10_100_val | fc_val);
10904
10905         if (phy->req_duplex == DUPLEX_FULL)
10906                 autoneg_val |= (1<<8);
10907
10908         bnx2x_cl22_write(bp, phy,
10909                         MDIO_PMA_REG_CTRL, autoneg_val);
10910
10911         return 0;
10912 }
10913
10914
10915 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10916                                        struct link_params *params, u8 mode)
10917 {
10918         struct bnx2x *bp = params->bp;
10919         u16 temp;
10920
10921         bnx2x_cl22_write(bp, phy,
10922                 MDIO_REG_GPHY_SHADOW,
10923                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10924         bnx2x_cl22_read(bp, phy,
10925                 MDIO_REG_GPHY_SHADOW,
10926                 &temp);
10927         temp &= 0xff00;
10928
10929         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10930         switch (mode) {
10931         case LED_MODE_FRONT_PANEL_OFF:
10932         case LED_MODE_OFF:
10933                 temp |= 0x00ee;
10934                 break;
10935         case LED_MODE_OPER:
10936                 temp |= 0x0001;
10937                 break;
10938         case LED_MODE_ON:
10939                 temp |= 0x00ff;
10940                 break;
10941         default:
10942                 break;
10943         }
10944         bnx2x_cl22_write(bp, phy,
10945                 MDIO_REG_GPHY_SHADOW,
10946                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10947         return;
10948 }
10949
10950
10951 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10952                                      struct link_params *params)
10953 {
10954         struct bnx2x *bp = params->bp;
10955         u32 cfg_pin;
10956         u8 port;
10957
10958         /* In case of no EPIO routed to reset the GPHY, put it
10959          * in low power mode.
10960          */
10961         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10962         /* This works with E3 only, no need to check the chip
10963          * before determining the port.
10964          */
10965         port = params->port;
10966         cfg_pin = (REG_RD(bp, params->shmem_base +
10967                         offsetof(struct shmem_region,
10968                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10969                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10970                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10971
10972         /* Drive pin low to put GPHY in reset. */
10973         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10974 }
10975
10976 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10977                                     struct link_params *params,
10978                                     struct link_vars *vars)
10979 {
10980         struct bnx2x *bp = params->bp;
10981         u16 val;
10982         u8 link_up = 0;
10983         u16 legacy_status, legacy_speed;
10984
10985         /* Get speed operation status */
10986         bnx2x_cl22_read(bp, phy,
10987                         MDIO_REG_GPHY_AUX_STATUS,
10988                         &legacy_status);
10989         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10990
10991         /* Read status to clear the PHY interrupt. */
10992         bnx2x_cl22_read(bp, phy,
10993                         MDIO_REG_INTR_STATUS,
10994                         &val);
10995
10996         link_up = ((legacy_status & (1<<2)) == (1<<2));
10997
10998         if (link_up) {
10999                 legacy_speed = (legacy_status & (7<<8));
11000                 if (legacy_speed == (7<<8)) {
11001                         vars->line_speed = SPEED_1000;
11002                         vars->duplex = DUPLEX_FULL;
11003                 } else if (legacy_speed == (6<<8)) {
11004                         vars->line_speed = SPEED_1000;
11005                         vars->duplex = DUPLEX_HALF;
11006                 } else if (legacy_speed == (5<<8)) {
11007                         vars->line_speed = SPEED_100;
11008                         vars->duplex = DUPLEX_FULL;
11009                 }
11010                 /* Omitting 100Base-T4 for now */
11011                 else if (legacy_speed == (3<<8)) {
11012                         vars->line_speed = SPEED_100;
11013                         vars->duplex = DUPLEX_HALF;
11014                 } else if (legacy_speed == (2<<8)) {
11015                         vars->line_speed = SPEED_10;
11016                         vars->duplex = DUPLEX_FULL;
11017                 } else if (legacy_speed == (1<<8)) {
11018                         vars->line_speed = SPEED_10;
11019                         vars->duplex = DUPLEX_HALF;
11020                 } else /* Should not happen */
11021                         vars->line_speed = 0;
11022
11023                 DP(NETIF_MSG_LINK,
11024                    "Link is up in %dMbps, is_duplex_full= %d\n",
11025                    vars->line_speed,
11026                    (vars->duplex == DUPLEX_FULL));
11027
11028                 /* Check legacy speed AN resolution */
11029                 bnx2x_cl22_read(bp, phy,
11030                                 0x01,
11031                                 &val);
11032                 if (val & (1<<5))
11033                         vars->link_status |=
11034                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11035                 bnx2x_cl22_read(bp, phy,
11036                                 0x06,
11037                                 &val);
11038                 if ((val & (1<<0)) == 0)
11039                         vars->link_status |=
11040                                 LINK_STATUS_PARALLEL_DETECTION_USED;
11041
11042                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11043                            vars->line_speed);
11044
11045                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11046
11047                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11048                         /* Report LP advertised speeds */
11049                         bnx2x_cl22_read(bp, phy, 0x5, &val);
11050
11051                         if (val & (1<<5))
11052                                 vars->link_status |=
11053                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11054                         if (val & (1<<6))
11055                                 vars->link_status |=
11056                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11057                         if (val & (1<<7))
11058                                 vars->link_status |=
11059                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11060                         if (val & (1<<8))
11061                                 vars->link_status |=
11062                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11063                         if (val & (1<<9))
11064                                 vars->link_status |=
11065                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11066
11067                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11068                         if (val & (1<<10))
11069                                 vars->link_status |=
11070                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11071                         if (val & (1<<11))
11072                                 vars->link_status |=
11073                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11074
11075                         if ((phy->flags & FLAGS_EEE) &&
11076                             bnx2x_eee_has_cap(params))
11077                                 bnx2x_eee_an_resolve(phy, params, vars);
11078                 }
11079         }
11080         return link_up;
11081 }
11082
11083 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11084                                           struct link_params *params)
11085 {
11086         struct bnx2x *bp = params->bp;
11087         u16 val;
11088         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11089
11090         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11091
11092         /* Enable master/slave manual mmode and set to master */
11093         /* mii write 9 [bits set 11 12] */
11094         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11095
11096         /* forced 1G and disable autoneg */
11097         /* set val [mii read 0] */
11098         /* set val [expr $val & [bits clear 6 12 13]] */
11099         /* set val [expr $val | [bits set 6 8]] */
11100         /* mii write 0 $val */
11101         bnx2x_cl22_read(bp, phy, 0x00, &val);
11102         val &= ~((1<<6) | (1<<12) | (1<<13));
11103         val |= (1<<6) | (1<<8);
11104         bnx2x_cl22_write(bp, phy, 0x00, val);
11105
11106         /* Set external loopback and Tx using 6dB coding */
11107         /* mii write 0x18 7 */
11108         /* set val [mii read 0x18] */
11109         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11110         bnx2x_cl22_write(bp, phy, 0x18, 7);
11111         bnx2x_cl22_read(bp, phy, 0x18, &val);
11112         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11113
11114         /* This register opens the gate for the UMAC despite its name */
11115         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11116
11117         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11118          * length used by the MAC receive logic to check frames.
11119          */
11120         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11121 }
11122
11123 /******************************************************************/
11124 /*                      SFX7101 PHY SECTION                       */
11125 /******************************************************************/
11126 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11127                                        struct link_params *params)
11128 {
11129         struct bnx2x *bp = params->bp;
11130         /* SFX7101_XGXS_TEST1 */
11131         bnx2x_cl45_write(bp, phy,
11132                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11133 }
11134
11135 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11136                                   struct link_params *params,
11137                                   struct link_vars *vars)
11138 {
11139         u16 fw_ver1, fw_ver2, val;
11140         struct bnx2x *bp = params->bp;
11141         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11142
11143         /* Restore normal power mode*/
11144         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11145                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11146         /* HW reset */
11147         bnx2x_ext_phy_hw_reset(bp, params->port);
11148         bnx2x_wait_reset_complete(bp, phy, params);
11149
11150         bnx2x_cl45_write(bp, phy,
11151                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11152         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11153         bnx2x_cl45_write(bp, phy,
11154                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11155
11156         bnx2x_ext_phy_set_pause(params, phy, vars);
11157         /* Restart autoneg */
11158         bnx2x_cl45_read(bp, phy,
11159                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11160         val |= 0x200;
11161         bnx2x_cl45_write(bp, phy,
11162                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11163
11164         /* Save spirom version */
11165         bnx2x_cl45_read(bp, phy,
11166                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11167
11168         bnx2x_cl45_read(bp, phy,
11169                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11170         bnx2x_save_spirom_version(bp, params->port,
11171                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11172         return 0;
11173 }
11174
11175 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11176                                  struct link_params *params,
11177                                  struct link_vars *vars)
11178 {
11179         struct bnx2x *bp = params->bp;
11180         u8 link_up;
11181         u16 val1, val2;
11182         bnx2x_cl45_read(bp, phy,
11183                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11184         bnx2x_cl45_read(bp, phy,
11185                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11186         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11187                    val2, val1);
11188         bnx2x_cl45_read(bp, phy,
11189                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11190         bnx2x_cl45_read(bp, phy,
11191                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11192         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11193                    val2, val1);
11194         link_up = ((val1 & 4) == 4);
11195         /* If link is up print the AN outcome of the SFX7101 PHY */
11196         if (link_up) {
11197                 bnx2x_cl45_read(bp, phy,
11198                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11199                                 &val2);
11200                 vars->line_speed = SPEED_10000;
11201                 vars->duplex = DUPLEX_FULL;
11202                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11203                            val2, (val2 & (1<<14)));
11204                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11205                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11206
11207                 /* Read LP advertised speeds */
11208                 if (val2 & (1<<11))
11209                         vars->link_status |=
11210                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11211         }
11212         return link_up;
11213 }
11214
11215 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11216 {
11217         if (*len < 5)
11218                 return -EINVAL;
11219         str[0] = (spirom_ver & 0xFF);
11220         str[1] = (spirom_ver & 0xFF00) >> 8;
11221         str[2] = (spirom_ver & 0xFF0000) >> 16;
11222         str[3] = (spirom_ver & 0xFF000000) >> 24;
11223         str[4] = '\0';
11224         *len -= 5;
11225         return 0;
11226 }
11227
11228 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11229 {
11230         u16 val, cnt;
11231
11232         bnx2x_cl45_read(bp, phy,
11233                         MDIO_PMA_DEVAD,
11234                         MDIO_PMA_REG_7101_RESET, &val);
11235
11236         for (cnt = 0; cnt < 10; cnt++) {
11237                 msleep(50);
11238                 /* Writes a self-clearing reset */
11239                 bnx2x_cl45_write(bp, phy,
11240                                  MDIO_PMA_DEVAD,
11241                                  MDIO_PMA_REG_7101_RESET,
11242                                  (val | (1<<15)));
11243                 /* Wait for clear */
11244                 bnx2x_cl45_read(bp, phy,
11245                                 MDIO_PMA_DEVAD,
11246                                 MDIO_PMA_REG_7101_RESET, &val);
11247
11248                 if ((val & (1<<15)) == 0)
11249                         break;
11250         }
11251 }
11252
11253 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11254                                 struct link_params *params) {
11255         /* Low power mode is controlled by GPIO 2 */
11256         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11257                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11258         /* The PHY reset is controlled by GPIO 1 */
11259         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11260                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11261 }
11262
11263 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11264                                     struct link_params *params, u8 mode)
11265 {
11266         u16 val = 0;
11267         struct bnx2x *bp = params->bp;
11268         switch (mode) {
11269         case LED_MODE_FRONT_PANEL_OFF:
11270         case LED_MODE_OFF:
11271                 val = 2;
11272                 break;
11273         case LED_MODE_ON:
11274                 val = 1;
11275                 break;
11276         case LED_MODE_OPER:
11277                 val = 0;
11278                 break;
11279         }
11280         bnx2x_cl45_write(bp, phy,
11281                          MDIO_PMA_DEVAD,
11282                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11283                          val);
11284 }
11285
11286 /******************************************************************/
11287 /*                      STATIC PHY DECLARATION                    */
11288 /******************************************************************/
11289
11290 static const struct bnx2x_phy phy_null = {
11291         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11292         .addr           = 0,
11293         .def_md_devad   = 0,
11294         .flags          = FLAGS_INIT_XGXS_FIRST,
11295         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11296         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11297         .mdio_ctrl      = 0,
11298         .supported      = 0,
11299         .media_type     = ETH_PHY_NOT_PRESENT,
11300         .ver_addr       = 0,
11301         .req_flow_ctrl  = 0,
11302         .req_line_speed = 0,
11303         .speed_cap_mask = 0,
11304         .req_duplex     = 0,
11305         .rsrv           = 0,
11306         .config_init    = (config_init_t)NULL,
11307         .read_status    = (read_status_t)NULL,
11308         .link_reset     = (link_reset_t)NULL,
11309         .config_loopback = (config_loopback_t)NULL,
11310         .format_fw_ver  = (format_fw_ver_t)NULL,
11311         .hw_reset       = (hw_reset_t)NULL,
11312         .set_link_led   = (set_link_led_t)NULL,
11313         .phy_specific_func = (phy_specific_func_t)NULL
11314 };
11315
11316 static const struct bnx2x_phy phy_serdes = {
11317         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11318         .addr           = 0xff,
11319         .def_md_devad   = 0,
11320         .flags          = 0,
11321         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11322         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11323         .mdio_ctrl      = 0,
11324         .supported      = (SUPPORTED_10baseT_Half |
11325                            SUPPORTED_10baseT_Full |
11326                            SUPPORTED_100baseT_Half |
11327                            SUPPORTED_100baseT_Full |
11328                            SUPPORTED_1000baseT_Full |
11329                            SUPPORTED_2500baseX_Full |
11330                            SUPPORTED_TP |
11331                            SUPPORTED_Autoneg |
11332                            SUPPORTED_Pause |
11333                            SUPPORTED_Asym_Pause),
11334         .media_type     = ETH_PHY_BASE_T,
11335         .ver_addr       = 0,
11336         .req_flow_ctrl  = 0,
11337         .req_line_speed = 0,
11338         .speed_cap_mask = 0,
11339         .req_duplex     = 0,
11340         .rsrv           = 0,
11341         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11342         .read_status    = (read_status_t)bnx2x_link_settings_status,
11343         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11344         .config_loopback = (config_loopback_t)NULL,
11345         .format_fw_ver  = (format_fw_ver_t)NULL,
11346         .hw_reset       = (hw_reset_t)NULL,
11347         .set_link_led   = (set_link_led_t)NULL,
11348         .phy_specific_func = (phy_specific_func_t)NULL
11349 };
11350
11351 static const struct bnx2x_phy phy_xgxs = {
11352         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11353         .addr           = 0xff,
11354         .def_md_devad   = 0,
11355         .flags          = 0,
11356         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11357         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11358         .mdio_ctrl      = 0,
11359         .supported      = (SUPPORTED_10baseT_Half |
11360                            SUPPORTED_10baseT_Full |
11361                            SUPPORTED_100baseT_Half |
11362                            SUPPORTED_100baseT_Full |
11363                            SUPPORTED_1000baseT_Full |
11364                            SUPPORTED_2500baseX_Full |
11365                            SUPPORTED_10000baseT_Full |
11366                            SUPPORTED_FIBRE |
11367                            SUPPORTED_Autoneg |
11368                            SUPPORTED_Pause |
11369                            SUPPORTED_Asym_Pause),
11370         .media_type     = ETH_PHY_CX4,
11371         .ver_addr       = 0,
11372         .req_flow_ctrl  = 0,
11373         .req_line_speed = 0,
11374         .speed_cap_mask = 0,
11375         .req_duplex     = 0,
11376         .rsrv           = 0,
11377         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11378         .read_status    = (read_status_t)bnx2x_link_settings_status,
11379         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11380         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11381         .format_fw_ver  = (format_fw_ver_t)NULL,
11382         .hw_reset       = (hw_reset_t)NULL,
11383         .set_link_led   = (set_link_led_t)NULL,
11384         .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11385 };
11386 static const struct bnx2x_phy phy_warpcore = {
11387         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11388         .addr           = 0xff,
11389         .def_md_devad   = 0,
11390         .flags          = FLAGS_TX_ERROR_CHECK,
11391         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11392         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11393         .mdio_ctrl      = 0,
11394         .supported      = (SUPPORTED_10baseT_Half |
11395                            SUPPORTED_10baseT_Full |
11396                            SUPPORTED_100baseT_Half |
11397                            SUPPORTED_100baseT_Full |
11398                            SUPPORTED_1000baseT_Full |
11399                            SUPPORTED_10000baseT_Full |
11400                            SUPPORTED_20000baseKR2_Full |
11401                            SUPPORTED_20000baseMLD2_Full |
11402                            SUPPORTED_FIBRE |
11403                            SUPPORTED_Autoneg |
11404                            SUPPORTED_Pause |
11405                            SUPPORTED_Asym_Pause),
11406         .media_type     = ETH_PHY_UNSPECIFIED,
11407         .ver_addr       = 0,
11408         .req_flow_ctrl  = 0,
11409         .req_line_speed = 0,
11410         .speed_cap_mask = 0,
11411         /* req_duplex = */0,
11412         /* rsrv = */0,
11413         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11414         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11415         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11416         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11417         .format_fw_ver  = (format_fw_ver_t)NULL,
11418         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11419         .set_link_led   = (set_link_led_t)NULL,
11420         .phy_specific_func = (phy_specific_func_t)NULL
11421 };
11422
11423
11424 static const struct bnx2x_phy phy_7101 = {
11425         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11426         .addr           = 0xff,
11427         .def_md_devad   = 0,
11428         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11429         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11430         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11431         .mdio_ctrl      = 0,
11432         .supported      = (SUPPORTED_10000baseT_Full |
11433                            SUPPORTED_TP |
11434                            SUPPORTED_Autoneg |
11435                            SUPPORTED_Pause |
11436                            SUPPORTED_Asym_Pause),
11437         .media_type     = ETH_PHY_BASE_T,
11438         .ver_addr       = 0,
11439         .req_flow_ctrl  = 0,
11440         .req_line_speed = 0,
11441         .speed_cap_mask = 0,
11442         .req_duplex     = 0,
11443         .rsrv           = 0,
11444         .config_init    = (config_init_t)bnx2x_7101_config_init,
11445         .read_status    = (read_status_t)bnx2x_7101_read_status,
11446         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11447         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11448         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11449         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11450         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11451         .phy_specific_func = (phy_specific_func_t)NULL
11452 };
11453 static const struct bnx2x_phy phy_8073 = {
11454         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11455         .addr           = 0xff,
11456         .def_md_devad   = 0,
11457         .flags          = 0,
11458         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11459         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11460         .mdio_ctrl      = 0,
11461         .supported      = (SUPPORTED_10000baseT_Full |
11462                            SUPPORTED_2500baseX_Full |
11463                            SUPPORTED_1000baseT_Full |
11464                            SUPPORTED_FIBRE |
11465                            SUPPORTED_Autoneg |
11466                            SUPPORTED_Pause |
11467                            SUPPORTED_Asym_Pause),
11468         .media_type     = ETH_PHY_KR,
11469         .ver_addr       = 0,
11470         .req_flow_ctrl  = 0,
11471         .req_line_speed = 0,
11472         .speed_cap_mask = 0,
11473         .req_duplex     = 0,
11474         .rsrv           = 0,
11475         .config_init    = (config_init_t)bnx2x_8073_config_init,
11476         .read_status    = (read_status_t)bnx2x_8073_read_status,
11477         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11478         .config_loopback = (config_loopback_t)NULL,
11479         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11480         .hw_reset       = (hw_reset_t)NULL,
11481         .set_link_led   = (set_link_led_t)NULL,
11482         .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11483 };
11484 static const struct bnx2x_phy phy_8705 = {
11485         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11486         .addr           = 0xff,
11487         .def_md_devad   = 0,
11488         .flags          = FLAGS_INIT_XGXS_FIRST,
11489         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11490         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11491         .mdio_ctrl      = 0,
11492         .supported      = (SUPPORTED_10000baseT_Full |
11493                            SUPPORTED_FIBRE |
11494                            SUPPORTED_Pause |
11495                            SUPPORTED_Asym_Pause),
11496         .media_type     = ETH_PHY_XFP_FIBER,
11497         .ver_addr       = 0,
11498         .req_flow_ctrl  = 0,
11499         .req_line_speed = 0,
11500         .speed_cap_mask = 0,
11501         .req_duplex     = 0,
11502         .rsrv           = 0,
11503         .config_init    = (config_init_t)bnx2x_8705_config_init,
11504         .read_status    = (read_status_t)bnx2x_8705_read_status,
11505         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11506         .config_loopback = (config_loopback_t)NULL,
11507         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11508         .hw_reset       = (hw_reset_t)NULL,
11509         .set_link_led   = (set_link_led_t)NULL,
11510         .phy_specific_func = (phy_specific_func_t)NULL
11511 };
11512 static const struct bnx2x_phy phy_8706 = {
11513         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11514         .addr           = 0xff,
11515         .def_md_devad   = 0,
11516         .flags          = FLAGS_INIT_XGXS_FIRST,
11517         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11518         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11519         .mdio_ctrl      = 0,
11520         .supported      = (SUPPORTED_10000baseT_Full |
11521                            SUPPORTED_1000baseT_Full |
11522                            SUPPORTED_FIBRE |
11523                            SUPPORTED_Pause |
11524                            SUPPORTED_Asym_Pause),
11525         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11526         .ver_addr       = 0,
11527         .req_flow_ctrl  = 0,
11528         .req_line_speed = 0,
11529         .speed_cap_mask = 0,
11530         .req_duplex     = 0,
11531         .rsrv           = 0,
11532         .config_init    = (config_init_t)bnx2x_8706_config_init,
11533         .read_status    = (read_status_t)bnx2x_8706_read_status,
11534         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11535         .config_loopback = (config_loopback_t)NULL,
11536         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11537         .hw_reset       = (hw_reset_t)NULL,
11538         .set_link_led   = (set_link_led_t)NULL,
11539         .phy_specific_func = (phy_specific_func_t)NULL
11540 };
11541
11542 static const struct bnx2x_phy phy_8726 = {
11543         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11544         .addr           = 0xff,
11545         .def_md_devad   = 0,
11546         .flags          = (FLAGS_INIT_XGXS_FIRST |
11547                            FLAGS_TX_ERROR_CHECK),
11548         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11549         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11550         .mdio_ctrl      = 0,
11551         .supported      = (SUPPORTED_10000baseT_Full |
11552                            SUPPORTED_1000baseT_Full |
11553                            SUPPORTED_Autoneg |
11554                            SUPPORTED_FIBRE |
11555                            SUPPORTED_Pause |
11556                            SUPPORTED_Asym_Pause),
11557         .media_type     = ETH_PHY_NOT_PRESENT,
11558         .ver_addr       = 0,
11559         .req_flow_ctrl  = 0,
11560         .req_line_speed = 0,
11561         .speed_cap_mask = 0,
11562         .req_duplex     = 0,
11563         .rsrv           = 0,
11564         .config_init    = (config_init_t)bnx2x_8726_config_init,
11565         .read_status    = (read_status_t)bnx2x_8726_read_status,
11566         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11567         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11568         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11569         .hw_reset       = (hw_reset_t)NULL,
11570         .set_link_led   = (set_link_led_t)NULL,
11571         .phy_specific_func = (phy_specific_func_t)NULL
11572 };
11573
11574 static const struct bnx2x_phy phy_8727 = {
11575         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11576         .addr           = 0xff,
11577         .def_md_devad   = 0,
11578         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11579                            FLAGS_TX_ERROR_CHECK),
11580         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11581         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11582         .mdio_ctrl      = 0,
11583         .supported      = (SUPPORTED_10000baseT_Full |
11584                            SUPPORTED_1000baseT_Full |
11585                            SUPPORTED_FIBRE |
11586                            SUPPORTED_Pause |
11587                            SUPPORTED_Asym_Pause),
11588         .media_type     = ETH_PHY_NOT_PRESENT,
11589         .ver_addr       = 0,
11590         .req_flow_ctrl  = 0,
11591         .req_line_speed = 0,
11592         .speed_cap_mask = 0,
11593         .req_duplex     = 0,
11594         .rsrv           = 0,
11595         .config_init    = (config_init_t)bnx2x_8727_config_init,
11596         .read_status    = (read_status_t)bnx2x_8727_read_status,
11597         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11598         .config_loopback = (config_loopback_t)NULL,
11599         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11600         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11601         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11602         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11603 };
11604 static const struct bnx2x_phy phy_8481 = {
11605         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11606         .addr           = 0xff,
11607         .def_md_devad   = 0,
11608         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11609                           FLAGS_REARM_LATCH_SIGNAL,
11610         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11611         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11612         .mdio_ctrl      = 0,
11613         .supported      = (SUPPORTED_10baseT_Half |
11614                            SUPPORTED_10baseT_Full |
11615                            SUPPORTED_100baseT_Half |
11616                            SUPPORTED_100baseT_Full |
11617                            SUPPORTED_1000baseT_Full |
11618                            SUPPORTED_10000baseT_Full |
11619                            SUPPORTED_TP |
11620                            SUPPORTED_Autoneg |
11621                            SUPPORTED_Pause |
11622                            SUPPORTED_Asym_Pause),
11623         .media_type     = ETH_PHY_BASE_T,
11624         .ver_addr       = 0,
11625         .req_flow_ctrl  = 0,
11626         .req_line_speed = 0,
11627         .speed_cap_mask = 0,
11628         .req_duplex     = 0,
11629         .rsrv           = 0,
11630         .config_init    = (config_init_t)bnx2x_8481_config_init,
11631         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11632         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11633         .config_loopback = (config_loopback_t)NULL,
11634         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11635         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11636         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11637         .phy_specific_func = (phy_specific_func_t)NULL
11638 };
11639
11640 static const struct bnx2x_phy phy_84823 = {
11641         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11642         .addr           = 0xff,
11643         .def_md_devad   = 0,
11644         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11645                            FLAGS_REARM_LATCH_SIGNAL |
11646                            FLAGS_TX_ERROR_CHECK),
11647         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11648         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11649         .mdio_ctrl      = 0,
11650         .supported      = (SUPPORTED_10baseT_Half |
11651                            SUPPORTED_10baseT_Full |
11652                            SUPPORTED_100baseT_Half |
11653                            SUPPORTED_100baseT_Full |
11654                            SUPPORTED_1000baseT_Full |
11655                            SUPPORTED_10000baseT_Full |
11656                            SUPPORTED_TP |
11657                            SUPPORTED_Autoneg |
11658                            SUPPORTED_Pause |
11659                            SUPPORTED_Asym_Pause),
11660         .media_type     = ETH_PHY_BASE_T,
11661         .ver_addr       = 0,
11662         .req_flow_ctrl  = 0,
11663         .req_line_speed = 0,
11664         .speed_cap_mask = 0,
11665         .req_duplex     = 0,
11666         .rsrv           = 0,
11667         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11668         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11669         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11670         .config_loopback = (config_loopback_t)NULL,
11671         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11672         .hw_reset       = (hw_reset_t)NULL,
11673         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11674         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11675 };
11676
11677 static const struct bnx2x_phy phy_84833 = {
11678         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11679         .addr           = 0xff,
11680         .def_md_devad   = 0,
11681         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11682                            FLAGS_REARM_LATCH_SIGNAL |
11683                            FLAGS_TX_ERROR_CHECK),
11684         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11685         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11686         .mdio_ctrl      = 0,
11687         .supported      = (SUPPORTED_100baseT_Half |
11688                            SUPPORTED_100baseT_Full |
11689                            SUPPORTED_1000baseT_Full |
11690                            SUPPORTED_10000baseT_Full |
11691                            SUPPORTED_TP |
11692                            SUPPORTED_Autoneg |
11693                            SUPPORTED_Pause |
11694                            SUPPORTED_Asym_Pause),
11695         .media_type     = ETH_PHY_BASE_T,
11696         .ver_addr       = 0,
11697         .req_flow_ctrl  = 0,
11698         .req_line_speed = 0,
11699         .speed_cap_mask = 0,
11700         .req_duplex     = 0,
11701         .rsrv           = 0,
11702         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11703         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11704         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11705         .config_loopback = (config_loopback_t)NULL,
11706         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11707         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11708         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11709         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11710 };
11711
11712 static const struct bnx2x_phy phy_84834 = {
11713         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11714         .addr           = 0xff,
11715         .def_md_devad   = 0,
11716         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11717                             FLAGS_REARM_LATCH_SIGNAL,
11718         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11719         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11720         .mdio_ctrl      = 0,
11721         .supported      = (SUPPORTED_100baseT_Half |
11722                            SUPPORTED_100baseT_Full |
11723                            SUPPORTED_1000baseT_Full |
11724                            SUPPORTED_10000baseT_Full |
11725                            SUPPORTED_TP |
11726                            SUPPORTED_Autoneg |
11727                            SUPPORTED_Pause |
11728                            SUPPORTED_Asym_Pause),
11729         .media_type     = ETH_PHY_BASE_T,
11730         .ver_addr       = 0,
11731         .req_flow_ctrl  = 0,
11732         .req_line_speed = 0,
11733         .speed_cap_mask = 0,
11734         .req_duplex     = 0,
11735         .rsrv           = 0,
11736         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11737         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11738         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11739         .config_loopback = (config_loopback_t)NULL,
11740         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11741         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11742         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11743         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11744 };
11745
11746 static const struct bnx2x_phy phy_54618se = {
11747         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11748         .addr           = 0xff,
11749         .def_md_devad   = 0,
11750         .flags          = FLAGS_INIT_XGXS_FIRST,
11751         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11752         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11753         .mdio_ctrl      = 0,
11754         .supported      = (SUPPORTED_10baseT_Half |
11755                            SUPPORTED_10baseT_Full |
11756                            SUPPORTED_100baseT_Half |
11757                            SUPPORTED_100baseT_Full |
11758                            SUPPORTED_1000baseT_Full |
11759                            SUPPORTED_TP |
11760                            SUPPORTED_Autoneg |
11761                            SUPPORTED_Pause |
11762                            SUPPORTED_Asym_Pause),
11763         .media_type     = ETH_PHY_BASE_T,
11764         .ver_addr       = 0,
11765         .req_flow_ctrl  = 0,
11766         .req_line_speed = 0,
11767         .speed_cap_mask = 0,
11768         /* req_duplex = */0,
11769         /* rsrv = */0,
11770         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11771         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11772         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11773         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11774         .format_fw_ver  = (format_fw_ver_t)NULL,
11775         .hw_reset       = (hw_reset_t)NULL,
11776         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11777         .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11778 };
11779 /*****************************************************************/
11780 /*                                                               */
11781 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11782 /*                                                               */
11783 /*****************************************************************/
11784
11785 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11786                                      struct bnx2x_phy *phy, u8 port,
11787                                      u8 phy_index)
11788 {
11789         /* Get the 4 lanes xgxs config rx and tx */
11790         u32 rx = 0, tx = 0, i;
11791         for (i = 0; i < 2; i++) {
11792                 /* INT_PHY and EXT_PHY1 share the same value location in
11793                  * the shmem. When num_phys is greater than 1, than this value
11794                  * applies only to EXT_PHY1
11795                  */
11796                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11797                         rx = REG_RD(bp, shmem_base +
11798                                     offsetof(struct shmem_region,
11799                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11800
11801                         tx = REG_RD(bp, shmem_base +
11802                                     offsetof(struct shmem_region,
11803                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11804                 } else {
11805                         rx = REG_RD(bp, shmem_base +
11806                                     offsetof(struct shmem_region,
11807                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11808
11809                         tx = REG_RD(bp, shmem_base +
11810                                     offsetof(struct shmem_region,
11811                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11812                 }
11813
11814                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11815                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11816
11817                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11818                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11819         }
11820 }
11821
11822 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11823                                     u8 phy_index, u8 port)
11824 {
11825         u32 ext_phy_config = 0;
11826         switch (phy_index) {
11827         case EXT_PHY1:
11828                 ext_phy_config = REG_RD(bp, shmem_base +
11829                                               offsetof(struct shmem_region,
11830                         dev_info.port_hw_config[port].external_phy_config));
11831                 break;
11832         case EXT_PHY2:
11833                 ext_phy_config = REG_RD(bp, shmem_base +
11834                                               offsetof(struct shmem_region,
11835                         dev_info.port_hw_config[port].external_phy_config2));
11836                 break;
11837         default:
11838                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11839                 return -EINVAL;
11840         }
11841
11842         return ext_phy_config;
11843 }
11844 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11845                                   struct bnx2x_phy *phy)
11846 {
11847         u32 phy_addr;
11848         u32 chip_id;
11849         u32 switch_cfg = (REG_RD(bp, shmem_base +
11850                                        offsetof(struct shmem_region,
11851                         dev_info.port_feature_config[port].link_config)) &
11852                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11853         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11854                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11855
11856         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11857         if (USES_WARPCORE(bp)) {
11858                 u32 serdes_net_if;
11859                 phy_addr = REG_RD(bp,
11860                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11861                 *phy = phy_warpcore;
11862                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11863                         phy->flags |= FLAGS_4_PORT_MODE;
11864                 else
11865                         phy->flags &= ~FLAGS_4_PORT_MODE;
11866                         /* Check Dual mode */
11867                 serdes_net_if = (REG_RD(bp, shmem_base +
11868                                         offsetof(struct shmem_region, dev_info.
11869                                         port_hw_config[port].default_cfg)) &
11870                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11871                 /* Set the appropriate supported and flags indications per
11872                  * interface type of the chip
11873                  */
11874                 switch (serdes_net_if) {
11875                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11876                         phy->supported &= (SUPPORTED_10baseT_Half |
11877                                            SUPPORTED_10baseT_Full |
11878                                            SUPPORTED_100baseT_Half |
11879                                            SUPPORTED_100baseT_Full |
11880                                            SUPPORTED_1000baseT_Full |
11881                                            SUPPORTED_FIBRE |
11882                                            SUPPORTED_Autoneg |
11883                                            SUPPORTED_Pause |
11884                                            SUPPORTED_Asym_Pause);
11885                         phy->media_type = ETH_PHY_BASE_T;
11886                         break;
11887                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11888                         phy->supported &= (SUPPORTED_1000baseT_Full |
11889                                            SUPPORTED_10000baseT_Full |
11890                                            SUPPORTED_FIBRE |
11891                                            SUPPORTED_Pause |
11892                                            SUPPORTED_Asym_Pause);
11893                         phy->media_type = ETH_PHY_XFP_FIBER;
11894                         break;
11895                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11896                         phy->supported &= (SUPPORTED_1000baseT_Full |
11897                                            SUPPORTED_10000baseT_Full |
11898                                            SUPPORTED_FIBRE |
11899                                            SUPPORTED_Pause |
11900                                            SUPPORTED_Asym_Pause);
11901                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11902                         break;
11903                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11904                         phy->media_type = ETH_PHY_KR;
11905                         phy->supported &= (SUPPORTED_1000baseT_Full |
11906                                            SUPPORTED_10000baseT_Full |
11907                                            SUPPORTED_FIBRE |
11908                                            SUPPORTED_Autoneg |
11909                                            SUPPORTED_Pause |
11910                                            SUPPORTED_Asym_Pause);
11911                         break;
11912                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11913                         phy->media_type = ETH_PHY_KR;
11914                         phy->flags |= FLAGS_WC_DUAL_MODE;
11915                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11916                                            SUPPORTED_FIBRE |
11917                                            SUPPORTED_Pause |
11918                                            SUPPORTED_Asym_Pause);
11919                         break;
11920                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11921                         phy->media_type = ETH_PHY_KR;
11922                         phy->flags |= FLAGS_WC_DUAL_MODE;
11923                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11924                                            SUPPORTED_10000baseT_Full |
11925                                            SUPPORTED_1000baseT_Full |
11926                                            SUPPORTED_Autoneg |
11927                                            SUPPORTED_FIBRE |
11928                                            SUPPORTED_Pause |
11929                                            SUPPORTED_Asym_Pause);
11930                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11931                         break;
11932                 default:
11933                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11934                                        serdes_net_if);
11935                         break;
11936                 }
11937
11938                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11939                  * was not set as expected. For B0, ECO will be enabled so there
11940                  * won't be an issue there
11941                  */
11942                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11943                         phy->flags |= FLAGS_MDC_MDIO_WA;
11944                 else
11945                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11946         } else {
11947                 switch (switch_cfg) {
11948                 case SWITCH_CFG_1G:
11949                         phy_addr = REG_RD(bp,
11950                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11951                                           port * 0x10);
11952                         *phy = phy_serdes;
11953                         break;
11954                 case SWITCH_CFG_10G:
11955                         phy_addr = REG_RD(bp,
11956                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11957                                           port * 0x18);
11958                         *phy = phy_xgxs;
11959                         break;
11960                 default:
11961                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11962                         return -EINVAL;
11963                 }
11964         }
11965         phy->addr = (u8)phy_addr;
11966         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11967                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11968                                             port);
11969         if (CHIP_IS_E2(bp))
11970                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11971         else
11972                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11973
11974         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11975                    port, phy->addr, phy->mdio_ctrl);
11976
11977         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11978         return 0;
11979 }
11980
11981 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11982                                   u8 phy_index,
11983                                   u32 shmem_base,
11984                                   u32 shmem2_base,
11985                                   u8 port,
11986                                   struct bnx2x_phy *phy)
11987 {
11988         u32 ext_phy_config, phy_type, config2;
11989         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11990         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11991                                                   phy_index, port);
11992         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11993         /* Select the phy type */
11994         switch (phy_type) {
11995         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11996                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11997                 *phy = phy_8073;
11998                 break;
11999         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12000                 *phy = phy_8705;
12001                 break;
12002         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12003                 *phy = phy_8706;
12004                 break;
12005         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12006                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12007                 *phy = phy_8726;
12008                 break;
12009         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12010                 /* BCM8727_NOC => BCM8727 no over current */
12011                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12012                 *phy = phy_8727;
12013                 phy->flags |= FLAGS_NOC;
12014                 break;
12015         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12016         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12017                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12018                 *phy = phy_8727;
12019                 break;
12020         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12021                 *phy = phy_8481;
12022                 break;
12023         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12024                 *phy = phy_84823;
12025                 break;
12026         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12027                 *phy = phy_84833;
12028                 break;
12029         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12030                 *phy = phy_84834;
12031                 break;
12032         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12033         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12034                 *phy = phy_54618se;
12035                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12036                         phy->flags |= FLAGS_EEE;
12037                 break;
12038         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12039                 *phy = phy_7101;
12040                 break;
12041         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12042                 *phy = phy_null;
12043                 return -EINVAL;
12044         default:
12045                 *phy = phy_null;
12046                 /* In case external PHY wasn't found */
12047                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12048                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12049                         return -EINVAL;
12050                 return 0;
12051         }
12052
12053         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12054         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12055
12056         /* The shmem address of the phy version is located on different
12057          * structures. In case this structure is too old, do not set
12058          * the address
12059          */
12060         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12061                                         dev_info.shared_hw_config.config2));
12062         if (phy_index == EXT_PHY1) {
12063                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12064                                 port_mb[port].ext_phy_fw_version);
12065
12066                 /* Check specific mdc mdio settings */
12067                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12068                         mdc_mdio_access = config2 &
12069                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12070         } else {
12071                 u32 size = REG_RD(bp, shmem2_base);
12072
12073                 if (size >
12074                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12075                         phy->ver_addr = shmem2_base +
12076                             offsetof(struct shmem2_region,
12077                                      ext_phy_fw_version2[port]);
12078                 }
12079                 /* Check specific mdc mdio settings */
12080                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12081                         mdc_mdio_access = (config2 &
12082                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12083                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12084                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12085         }
12086         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12087
12088         if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12089              (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12090             (phy->ver_addr)) {
12091                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12092                  * version lower than or equal to 1.39
12093                  */
12094                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12095                 if (((raw_ver & 0x7F) <= 39) &&
12096                     (((raw_ver & 0xF80) >> 7) <= 1))
12097                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12098                                             SUPPORTED_100baseT_Full);
12099         }
12100
12101         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12102                    phy_type, port, phy_index);
12103         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12104                    phy->addr, phy->mdio_ctrl);
12105         return 0;
12106 }
12107
12108 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12109                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12110 {
12111         int status = 0;
12112         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12113         if (phy_index == INT_PHY)
12114                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12115         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12116                                         port, phy);
12117         return status;
12118 }
12119
12120 static void bnx2x_phy_def_cfg(struct link_params *params,
12121                               struct bnx2x_phy *phy,
12122                               u8 phy_index)
12123 {
12124         struct bnx2x *bp = params->bp;
12125         u32 link_config;
12126         /* Populate the default phy configuration for MF mode */
12127         if (phy_index == EXT_PHY2) {
12128                 link_config = REG_RD(bp, params->shmem_base +
12129                                      offsetof(struct shmem_region, dev_info.
12130                         port_feature_config[params->port].link_config2));
12131                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12132                                              offsetof(struct shmem_region,
12133                                                       dev_info.
12134                         port_hw_config[params->port].speed_capability_mask2));
12135         } else {
12136                 link_config = REG_RD(bp, params->shmem_base +
12137                                      offsetof(struct shmem_region, dev_info.
12138                                 port_feature_config[params->port].link_config));
12139                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12140                                              offsetof(struct shmem_region,
12141                                                       dev_info.
12142                         port_hw_config[params->port].speed_capability_mask));
12143         }
12144         DP(NETIF_MSG_LINK,
12145            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12146            phy_index, link_config, phy->speed_cap_mask);
12147
12148         phy->req_duplex = DUPLEX_FULL;
12149         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12150         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12151                 phy->req_duplex = DUPLEX_HALF;
12152         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12153                 phy->req_line_speed = SPEED_10;
12154                 break;
12155         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12156                 phy->req_duplex = DUPLEX_HALF;
12157         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12158                 phy->req_line_speed = SPEED_100;
12159                 break;
12160         case PORT_FEATURE_LINK_SPEED_1G:
12161                 phy->req_line_speed = SPEED_1000;
12162                 break;
12163         case PORT_FEATURE_LINK_SPEED_2_5G:
12164                 phy->req_line_speed = SPEED_2500;
12165                 break;
12166         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12167                 phy->req_line_speed = SPEED_10000;
12168                 break;
12169         default:
12170                 phy->req_line_speed = SPEED_AUTO_NEG;
12171                 break;
12172         }
12173
12174         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12175         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12176                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12177                 break;
12178         case PORT_FEATURE_FLOW_CONTROL_TX:
12179                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12180                 break;
12181         case PORT_FEATURE_FLOW_CONTROL_RX:
12182                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12183                 break;
12184         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12185                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12186                 break;
12187         default:
12188                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12189                 break;
12190         }
12191 }
12192
12193 u32 bnx2x_phy_selection(struct link_params *params)
12194 {
12195         u32 phy_config_swapped, prio_cfg;
12196         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12197
12198         phy_config_swapped = params->multi_phy_config &
12199                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12200
12201         prio_cfg = params->multi_phy_config &
12202                         PORT_HW_CFG_PHY_SELECTION_MASK;
12203
12204         if (phy_config_swapped) {
12205                 switch (prio_cfg) {
12206                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12207                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12208                      break;
12209                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12210                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12211                      break;
12212                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12213                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12214                      break;
12215                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12216                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12217                      break;
12218                 }
12219         } else
12220                 return_cfg = prio_cfg;
12221
12222         return return_cfg;
12223 }
12224
12225 int bnx2x_phy_probe(struct link_params *params)
12226 {
12227         u8 phy_index, actual_phy_idx;
12228         u32 phy_config_swapped, sync_offset, media_types;
12229         struct bnx2x *bp = params->bp;
12230         struct bnx2x_phy *phy;
12231         params->num_phys = 0;
12232         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12233         phy_config_swapped = params->multi_phy_config &
12234                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12235
12236         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12237               phy_index++) {
12238                 actual_phy_idx = phy_index;
12239                 if (phy_config_swapped) {
12240                         if (phy_index == EXT_PHY1)
12241                                 actual_phy_idx = EXT_PHY2;
12242                         else if (phy_index == EXT_PHY2)
12243                                 actual_phy_idx = EXT_PHY1;
12244                 }
12245                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12246                                " actual_phy_idx %x\n", phy_config_swapped,
12247                            phy_index, actual_phy_idx);
12248                 phy = &params->phy[actual_phy_idx];
12249                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12250                                        params->shmem2_base, params->port,
12251                                        phy) != 0) {
12252                         params->num_phys = 0;
12253                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12254                                    phy_index);
12255                         for (phy_index = INT_PHY;
12256                               phy_index < MAX_PHYS;
12257                               phy_index++)
12258                                 *phy = phy_null;
12259                         return -EINVAL;
12260                 }
12261                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12262                         break;
12263
12264                 if (params->feature_config_flags &
12265                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12266                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12267
12268                 if (!(params->feature_config_flags &
12269                       FEATURE_CONFIG_MT_SUPPORT))
12270                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12271
12272                 sync_offset = params->shmem_base +
12273                         offsetof(struct shmem_region,
12274                         dev_info.port_hw_config[params->port].media_type);
12275                 media_types = REG_RD(bp, sync_offset);
12276
12277                 /* Update media type for non-PMF sync only for the first time
12278                  * In case the media type changes afterwards, it will be updated
12279                  * using the update_status function
12280                  */
12281                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12282                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12283                                      actual_phy_idx))) == 0) {
12284                         media_types |= ((phy->media_type &
12285                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12286                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12287                                  actual_phy_idx));
12288                 }
12289                 REG_WR(bp, sync_offset, media_types);
12290
12291                 bnx2x_phy_def_cfg(params, phy, phy_index);
12292                 params->num_phys++;
12293         }
12294
12295         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12296         return 0;
12297 }
12298
12299 static void bnx2x_init_bmac_loopback(struct link_params *params,
12300                                      struct link_vars *vars)
12301 {
12302         struct bnx2x *bp = params->bp;
12303                 vars->link_up = 1;
12304                 vars->line_speed = SPEED_10000;
12305                 vars->duplex = DUPLEX_FULL;
12306                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12307                 vars->mac_type = MAC_TYPE_BMAC;
12308
12309                 vars->phy_flags = PHY_XGXS_FLAG;
12310
12311                 bnx2x_xgxs_deassert(params);
12312
12313                 /* Set bmac loopback */
12314                 bnx2x_bmac_enable(params, vars, 1, 1);
12315
12316                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12317 }
12318
12319 static void bnx2x_init_emac_loopback(struct link_params *params,
12320                                      struct link_vars *vars)
12321 {
12322         struct bnx2x *bp = params->bp;
12323                 vars->link_up = 1;
12324                 vars->line_speed = SPEED_1000;
12325                 vars->duplex = DUPLEX_FULL;
12326                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12327                 vars->mac_type = MAC_TYPE_EMAC;
12328
12329                 vars->phy_flags = PHY_XGXS_FLAG;
12330
12331                 bnx2x_xgxs_deassert(params);
12332                 /* Set bmac loopback */
12333                 bnx2x_emac_enable(params, vars, 1);
12334                 bnx2x_emac_program(params, vars);
12335                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12336 }
12337
12338 static void bnx2x_init_xmac_loopback(struct link_params *params,
12339                                      struct link_vars *vars)
12340 {
12341         struct bnx2x *bp = params->bp;
12342         vars->link_up = 1;
12343         if (!params->req_line_speed[0])
12344                 vars->line_speed = SPEED_10000;
12345         else
12346                 vars->line_speed = params->req_line_speed[0];
12347         vars->duplex = DUPLEX_FULL;
12348         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12349         vars->mac_type = MAC_TYPE_XMAC;
12350         vars->phy_flags = PHY_XGXS_FLAG;
12351         /* Set WC to loopback mode since link is required to provide clock
12352          * to the XMAC in 20G mode
12353          */
12354         bnx2x_set_aer_mmd(params, &params->phy[0]);
12355         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12356         params->phy[INT_PHY].config_loopback(
12357                         &params->phy[INT_PHY],
12358                         params);
12359
12360         bnx2x_xmac_enable(params, vars, 1);
12361         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12362 }
12363
12364 static void bnx2x_init_umac_loopback(struct link_params *params,
12365                                      struct link_vars *vars)
12366 {
12367         struct bnx2x *bp = params->bp;
12368         vars->link_up = 1;
12369         vars->line_speed = SPEED_1000;
12370         vars->duplex = DUPLEX_FULL;
12371         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12372         vars->mac_type = MAC_TYPE_UMAC;
12373         vars->phy_flags = PHY_XGXS_FLAG;
12374         bnx2x_umac_enable(params, vars, 1);
12375
12376         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12377 }
12378
12379 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12380                                      struct link_vars *vars)
12381 {
12382         struct bnx2x *bp = params->bp;
12383         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12384         vars->link_up = 1;
12385         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12386         vars->duplex = DUPLEX_FULL;
12387         if (params->req_line_speed[0] == SPEED_1000)
12388                 vars->line_speed = SPEED_1000;
12389         else if ((params->req_line_speed[0] == SPEED_20000) ||
12390                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12391                 vars->line_speed = SPEED_20000;
12392         else
12393                 vars->line_speed = SPEED_10000;
12394
12395         if (!USES_WARPCORE(bp))
12396                 bnx2x_xgxs_deassert(params);
12397         bnx2x_link_initialize(params, vars);
12398
12399         if (params->req_line_speed[0] == SPEED_1000) {
12400                 if (USES_WARPCORE(bp))
12401                         bnx2x_umac_enable(params, vars, 0);
12402                 else {
12403                         bnx2x_emac_program(params, vars);
12404                         bnx2x_emac_enable(params, vars, 0);
12405                 }
12406         } else {
12407                 if (USES_WARPCORE(bp))
12408                         bnx2x_xmac_enable(params, vars, 0);
12409                 else
12410                         bnx2x_bmac_enable(params, vars, 0, 1);
12411         }
12412
12413         if (params->loopback_mode == LOOPBACK_XGXS) {
12414                 /* Set 10G XGXS loopback */
12415                 int_phy->config_loopback(int_phy, params);
12416         } else {
12417                 /* Set external phy loopback */
12418                 u8 phy_index;
12419                 for (phy_index = EXT_PHY1;
12420                       phy_index < params->num_phys; phy_index++)
12421                         if (params->phy[phy_index].config_loopback)
12422                                 params->phy[phy_index].config_loopback(
12423                                         &params->phy[phy_index],
12424                                         params);
12425         }
12426         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12427
12428         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12429 }
12430
12431 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12432 {
12433         struct bnx2x *bp = params->bp;
12434         u8 val = en * 0x1F;
12435
12436         /* Open / close the gate between the NIG and the BRB */
12437         if (!CHIP_IS_E1x(bp))
12438                 val |= en * 0x20;
12439         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12440
12441         if (!CHIP_IS_E1(bp)) {
12442                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12443                        en*0x3);
12444         }
12445
12446         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12447                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12448 }
12449 static int bnx2x_avoid_link_flap(struct link_params *params,
12450                                             struct link_vars *vars)
12451 {
12452         u32 phy_idx;
12453         u32 dont_clear_stat, lfa_sts;
12454         struct bnx2x *bp = params->bp;
12455
12456         /* Sync the link parameters */
12457         bnx2x_link_status_update(params, vars);
12458
12459         /*
12460          * The module verification was already done by previous link owner,
12461          * so this call is meant only to get warning message
12462          */
12463
12464         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12465                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12466                 if (phy->phy_specific_func) {
12467                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12468                         phy->phy_specific_func(phy, params, PHY_INIT);
12469                 }
12470                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12471                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12472                     (phy->media_type == ETH_PHY_DA_TWINAX))
12473                         bnx2x_verify_sfp_module(phy, params);
12474         }
12475         lfa_sts = REG_RD(bp, params->lfa_base +
12476                          offsetof(struct shmem_lfa,
12477                                   lfa_sts));
12478
12479         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12480
12481         /* Re-enable the NIG/MAC */
12482         if (CHIP_IS_E3(bp)) {
12483                 if (!dont_clear_stat) {
12484                         REG_WR(bp, GRCBASE_MISC +
12485                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12486                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12487                                 params->port));
12488                         REG_WR(bp, GRCBASE_MISC +
12489                                MISC_REGISTERS_RESET_REG_2_SET,
12490                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12491                                 params->port));
12492                 }
12493                 if (vars->line_speed < SPEED_10000)
12494                         bnx2x_umac_enable(params, vars, 0);
12495                 else
12496                         bnx2x_xmac_enable(params, vars, 0);
12497         } else {
12498                 if (vars->line_speed < SPEED_10000)
12499                         bnx2x_emac_enable(params, vars, 0);
12500                 else
12501                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12502         }
12503
12504         /* Increment LFA count */
12505         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12506                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12507                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12508                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12509         /* Clear link flap reason */
12510         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12511
12512         REG_WR(bp, params->lfa_base +
12513                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12514
12515         /* Disable NIG DRAIN */
12516         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12517
12518         /* Enable interrupts */
12519         bnx2x_link_int_enable(params);
12520         return 0;
12521 }
12522
12523 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12524                                          struct link_vars *vars,
12525                                          int lfa_status)
12526 {
12527         u32 lfa_sts, cfg_idx, tmp_val;
12528         struct bnx2x *bp = params->bp;
12529
12530         bnx2x_link_reset(params, vars, 1);
12531
12532         if (!params->lfa_base)
12533                 return;
12534         /* Store the new link parameters */
12535         REG_WR(bp, params->lfa_base +
12536                offsetof(struct shmem_lfa, req_duplex),
12537                params->req_duplex[0] | (params->req_duplex[1] << 16));
12538
12539         REG_WR(bp, params->lfa_base +
12540                offsetof(struct shmem_lfa, req_flow_ctrl),
12541                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12542
12543         REG_WR(bp, params->lfa_base +
12544                offsetof(struct shmem_lfa, req_line_speed),
12545                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12546
12547         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12548                 REG_WR(bp, params->lfa_base +
12549                        offsetof(struct shmem_lfa,
12550                                 speed_cap_mask[cfg_idx]),
12551                        params->speed_cap_mask[cfg_idx]);
12552         }
12553
12554         tmp_val = REG_RD(bp, params->lfa_base +
12555                          offsetof(struct shmem_lfa, additional_config));
12556         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12557         tmp_val |= params->req_fc_auto_adv;
12558
12559         REG_WR(bp, params->lfa_base +
12560                offsetof(struct shmem_lfa, additional_config), tmp_val);
12561
12562         lfa_sts = REG_RD(bp, params->lfa_base +
12563                          offsetof(struct shmem_lfa, lfa_sts));
12564
12565         /* Clear the "Don't Clear Statistics" bit, and set reason */
12566         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12567
12568         /* Set link flap reason */
12569         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12570         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12571                     LFA_LINK_FLAP_REASON_OFFSET);
12572
12573         /* Increment link flap counter */
12574         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12575                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12576                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12577                     << LINK_FLAP_COUNT_OFFSET));
12578         REG_WR(bp, params->lfa_base +
12579                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12580         /* Proceed with regular link initialization */
12581 }
12582
12583 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12584 {
12585         int lfa_status;
12586         struct bnx2x *bp = params->bp;
12587         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12588         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12589                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12590         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12591                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12592         DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12593         vars->link_status = 0;
12594         vars->phy_link_up = 0;
12595         vars->link_up = 0;
12596         vars->line_speed = 0;
12597         vars->duplex = DUPLEX_FULL;
12598         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12599         vars->mac_type = MAC_TYPE_NONE;
12600         vars->phy_flags = 0;
12601         vars->check_kr2_recovery_cnt = 0;
12602         params->link_flags = PHY_INITIALIZED;
12603         /* Driver opens NIG-BRB filters */
12604         bnx2x_set_rx_filter(params, 1);
12605         /* Check if link flap can be avoided */
12606         lfa_status = bnx2x_check_lfa(params);
12607
12608         if (lfa_status == 0) {
12609                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12610                 return bnx2x_avoid_link_flap(params, vars);
12611         }
12612
12613         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12614                        lfa_status);
12615         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12616
12617         /* Disable attentions */
12618         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12619                        (NIG_MASK_XGXS0_LINK_STATUS |
12620                         NIG_MASK_XGXS0_LINK10G |
12621                         NIG_MASK_SERDES0_LINK_STATUS |
12622                         NIG_MASK_MI_INT));
12623
12624         bnx2x_emac_init(params, vars);
12625
12626         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12627                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12628
12629         if (params->num_phys == 0) {
12630                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12631                 return -EINVAL;
12632         }
12633         set_phy_vars(params, vars);
12634
12635         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12636         switch (params->loopback_mode) {
12637         case LOOPBACK_BMAC:
12638                 bnx2x_init_bmac_loopback(params, vars);
12639                 break;
12640         case LOOPBACK_EMAC:
12641                 bnx2x_init_emac_loopback(params, vars);
12642                 break;
12643         case LOOPBACK_XMAC:
12644                 bnx2x_init_xmac_loopback(params, vars);
12645                 break;
12646         case LOOPBACK_UMAC:
12647                 bnx2x_init_umac_loopback(params, vars);
12648                 break;
12649         case LOOPBACK_XGXS:
12650         case LOOPBACK_EXT_PHY:
12651                 bnx2x_init_xgxs_loopback(params, vars);
12652                 break;
12653         default:
12654                 if (!CHIP_IS_E3(bp)) {
12655                         if (params->switch_cfg == SWITCH_CFG_10G)
12656                                 bnx2x_xgxs_deassert(params);
12657                         else
12658                                 bnx2x_serdes_deassert(bp, params->port);
12659                 }
12660                 bnx2x_link_initialize(params, vars);
12661                 msleep(30);
12662                 bnx2x_link_int_enable(params);
12663                 break;
12664         }
12665         bnx2x_update_mng(params, vars->link_status);
12666
12667         bnx2x_update_mng_eee(params, vars->eee_status);
12668         return 0;
12669 }
12670
12671 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12672                      u8 reset_ext_phy)
12673 {
12674         struct bnx2x *bp = params->bp;
12675         u8 phy_index, port = params->port, clear_latch_ind = 0;
12676         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12677         /* Disable attentions */
12678         vars->link_status = 0;
12679         bnx2x_update_mng(params, vars->link_status);
12680         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12681                               SHMEM_EEE_ACTIVE_BIT);
12682         bnx2x_update_mng_eee(params, vars->eee_status);
12683         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12684                        (NIG_MASK_XGXS0_LINK_STATUS |
12685                         NIG_MASK_XGXS0_LINK10G |
12686                         NIG_MASK_SERDES0_LINK_STATUS |
12687                         NIG_MASK_MI_INT));
12688
12689         /* Activate nig drain */
12690         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12691
12692         /* Disable nig egress interface */
12693         if (!CHIP_IS_E3(bp)) {
12694                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12695                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12696         }
12697
12698                 if (!CHIP_IS_E3(bp)) {
12699                         bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12700                 } else {
12701                         bnx2x_set_xmac_rxtx(params, 0);
12702                         bnx2x_set_umac_rxtx(params, 0);
12703                 }
12704         /* Disable emac */
12705         if (!CHIP_IS_E3(bp))
12706                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12707
12708         usleep_range(10000, 20000);
12709         /* The PHY reset is controlled by GPIO 1
12710          * Hold it as vars low
12711          */
12712          /* Clear link led */
12713         bnx2x_set_mdio_emac_per_phy(bp, params);
12714         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12715
12716         if (reset_ext_phy) {
12717                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12718                       phy_index++) {
12719                         if (params->phy[phy_index].link_reset) {
12720                                 bnx2x_set_aer_mmd(params,
12721                                                   &params->phy[phy_index]);
12722                                 params->phy[phy_index].link_reset(
12723                                         &params->phy[phy_index],
12724                                         params);
12725                         }
12726                         if (params->phy[phy_index].flags &
12727                             FLAGS_REARM_LATCH_SIGNAL)
12728                                 clear_latch_ind = 1;
12729                 }
12730         }
12731
12732         if (clear_latch_ind) {
12733                 /* Clear latching indication */
12734                 bnx2x_rearm_latch_signal(bp, port, 0);
12735                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12736                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12737         }
12738         if (params->phy[INT_PHY].link_reset)
12739                 params->phy[INT_PHY].link_reset(
12740                         &params->phy[INT_PHY], params);
12741
12742         /* Disable nig ingress interface */
12743         if (!CHIP_IS_E3(bp)) {
12744                 /* Reset BigMac */
12745                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12746                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12747                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12748                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12749         } else {
12750                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12751                 bnx2x_set_xumac_nig(params, 0, 0);
12752                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12753                     MISC_REGISTERS_RESET_REG_2_XMAC)
12754                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12755                                XMAC_CTRL_REG_SOFT_RESET);
12756         }
12757         vars->link_up = 0;
12758         vars->phy_flags = 0;
12759         return 0;
12760 }
12761 int bnx2x_lfa_reset(struct link_params *params,
12762                                struct link_vars *vars)
12763 {
12764         struct bnx2x *bp = params->bp;
12765         vars->link_up = 0;
12766         vars->phy_flags = 0;
12767         params->link_flags &= ~PHY_INITIALIZED;
12768         if (!params->lfa_base)
12769                 return bnx2x_link_reset(params, vars, 1);
12770         /*
12771          * Activate NIG drain so that during this time the device won't send
12772          * anything while it is unable to response.
12773          */
12774         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12775
12776         /*
12777          * Close gracefully the gate from BMAC to NIG such that no half packets
12778          * are passed.
12779          */
12780         if (!CHIP_IS_E3(bp))
12781                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12782
12783         if (CHIP_IS_E3(bp)) {
12784                 bnx2x_set_xmac_rxtx(params, 0);
12785                 bnx2x_set_umac_rxtx(params, 0);
12786         }
12787         /* Wait 10ms for the pipe to clean up*/
12788         usleep_range(10000, 20000);
12789
12790         /* Clean the NIG-BRB using the network filters in a way that will
12791          * not cut a packet in the middle.
12792          */
12793         bnx2x_set_rx_filter(params, 0);
12794
12795         /*
12796          * Re-open the gate between the BMAC and the NIG, after verifying the
12797          * gate to the BRB is closed, otherwise packets may arrive to the
12798          * firmware before driver had initialized it. The target is to achieve
12799          * minimum management protocol down time.
12800          */
12801         if (!CHIP_IS_E3(bp))
12802                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12803
12804         if (CHIP_IS_E3(bp)) {
12805                 bnx2x_set_xmac_rxtx(params, 1);
12806                 bnx2x_set_umac_rxtx(params, 1);
12807         }
12808         /* Disable NIG drain */
12809         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12810         return 0;
12811 }
12812
12813 /****************************************************************************/
12814 /*                              Common function                             */
12815 /****************************************************************************/
12816 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12817                                       u32 shmem_base_path[],
12818                                       u32 shmem2_base_path[], u8 phy_index,
12819                                       u32 chip_id)
12820 {
12821         struct bnx2x_phy phy[PORT_MAX];
12822         struct bnx2x_phy *phy_blk[PORT_MAX];
12823         u16 val;
12824         s8 port = 0;
12825         s8 port_of_path = 0;
12826         u32 swap_val, swap_override;
12827         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12828         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12829         port ^= (swap_val && swap_override);
12830         bnx2x_ext_phy_hw_reset(bp, port);
12831         /* PART1 - Reset both phys */
12832         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12833                 u32 shmem_base, shmem2_base;
12834                 /* In E2, same phy is using for port0 of the two paths */
12835                 if (CHIP_IS_E1x(bp)) {
12836                         shmem_base = shmem_base_path[0];
12837                         shmem2_base = shmem2_base_path[0];
12838                         port_of_path = port;
12839                 } else {
12840                         shmem_base = shmem_base_path[port];
12841                         shmem2_base = shmem2_base_path[port];
12842                         port_of_path = 0;
12843                 }
12844
12845                 /* Extract the ext phy address for the port */
12846                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12847                                        port_of_path, &phy[port]) !=
12848                     0) {
12849                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12850                         return -EINVAL;
12851                 }
12852                 /* Disable attentions */
12853                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12854                                port_of_path*4,
12855                                (NIG_MASK_XGXS0_LINK_STATUS |
12856                                 NIG_MASK_XGXS0_LINK10G |
12857                                 NIG_MASK_SERDES0_LINK_STATUS |
12858                                 NIG_MASK_MI_INT));
12859
12860                 /* Need to take the phy out of low power mode in order
12861                  * to write to access its registers
12862                  */
12863                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12864                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12865                                port);
12866
12867                 /* Reset the phy */
12868                 bnx2x_cl45_write(bp, &phy[port],
12869                                  MDIO_PMA_DEVAD,
12870                                  MDIO_PMA_REG_CTRL,
12871                                  1<<15);
12872         }
12873
12874         /* Add delay of 150ms after reset */
12875         msleep(150);
12876
12877         if (phy[PORT_0].addr & 0x1) {
12878                 phy_blk[PORT_0] = &(phy[PORT_1]);
12879                 phy_blk[PORT_1] = &(phy[PORT_0]);
12880         } else {
12881                 phy_blk[PORT_0] = &(phy[PORT_0]);
12882                 phy_blk[PORT_1] = &(phy[PORT_1]);
12883         }
12884
12885         /* PART2 - Download firmware to both phys */
12886         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12887                 if (CHIP_IS_E1x(bp))
12888                         port_of_path = port;
12889                 else
12890                         port_of_path = 0;
12891
12892                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12893                            phy_blk[port]->addr);
12894                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12895                                                       port_of_path))
12896                         return -EINVAL;
12897
12898                 /* Only set bit 10 = 1 (Tx power down) */
12899                 bnx2x_cl45_read(bp, phy_blk[port],
12900                                 MDIO_PMA_DEVAD,
12901                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12902
12903                 /* Phase1 of TX_POWER_DOWN reset */
12904                 bnx2x_cl45_write(bp, phy_blk[port],
12905                                  MDIO_PMA_DEVAD,
12906                                  MDIO_PMA_REG_TX_POWER_DOWN,
12907                                  (val | 1<<10));
12908         }
12909
12910         /* Toggle Transmitter: Power down and then up with 600ms delay
12911          * between
12912          */
12913         msleep(600);
12914
12915         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12916         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12917                 /* Phase2 of POWER_DOWN_RESET */
12918                 /* Release bit 10 (Release Tx power down) */
12919                 bnx2x_cl45_read(bp, phy_blk[port],
12920                                 MDIO_PMA_DEVAD,
12921                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12922
12923                 bnx2x_cl45_write(bp, phy_blk[port],
12924                                 MDIO_PMA_DEVAD,
12925                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12926                 usleep_range(15000, 30000);
12927
12928                 /* Read modify write the SPI-ROM version select register */
12929                 bnx2x_cl45_read(bp, phy_blk[port],
12930                                 MDIO_PMA_DEVAD,
12931                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12932                 bnx2x_cl45_write(bp, phy_blk[port],
12933                                  MDIO_PMA_DEVAD,
12934                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12935
12936                 /* set GPIO2 back to LOW */
12937                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12938                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12939         }
12940         return 0;
12941 }
12942 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12943                                       u32 shmem_base_path[],
12944                                       u32 shmem2_base_path[], u8 phy_index,
12945                                       u32 chip_id)
12946 {
12947         u32 val;
12948         s8 port;
12949         struct bnx2x_phy phy;
12950         /* Use port1 because of the static port-swap */
12951         /* Enable the module detection interrupt */
12952         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12953         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12954                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12955         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12956
12957         bnx2x_ext_phy_hw_reset(bp, 0);
12958         usleep_range(5000, 10000);
12959         for (port = 0; port < PORT_MAX; port++) {
12960                 u32 shmem_base, shmem2_base;
12961
12962                 /* In E2, same phy is using for port0 of the two paths */
12963                 if (CHIP_IS_E1x(bp)) {
12964                         shmem_base = shmem_base_path[0];
12965                         shmem2_base = shmem2_base_path[0];
12966                 } else {
12967                         shmem_base = shmem_base_path[port];
12968                         shmem2_base = shmem2_base_path[port];
12969                 }
12970                 /* Extract the ext phy address for the port */
12971                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12972                                        port, &phy) !=
12973                     0) {
12974                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12975                         return -EINVAL;
12976                 }
12977
12978                 /* Reset phy*/
12979                 bnx2x_cl45_write(bp, &phy,
12980                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12981
12982
12983                 /* Set fault module detected LED on */
12984                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12985                                MISC_REGISTERS_GPIO_HIGH,
12986                                port);
12987         }
12988
12989         return 0;
12990 }
12991 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12992                                          u8 *io_gpio, u8 *io_port)
12993 {
12994
12995         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12996                                           offsetof(struct shmem_region,
12997                                 dev_info.port_hw_config[PORT_0].default_cfg));
12998         switch (phy_gpio_reset) {
12999         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13000                 *io_gpio = 0;
13001                 *io_port = 0;
13002                 break;
13003         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13004                 *io_gpio = 1;
13005                 *io_port = 0;
13006                 break;
13007         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13008                 *io_gpio = 2;
13009                 *io_port = 0;
13010                 break;
13011         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13012                 *io_gpio = 3;
13013                 *io_port = 0;
13014                 break;
13015         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13016                 *io_gpio = 0;
13017                 *io_port = 1;
13018                 break;
13019         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13020                 *io_gpio = 1;
13021                 *io_port = 1;
13022                 break;
13023         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13024                 *io_gpio = 2;
13025                 *io_port = 1;
13026                 break;
13027         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13028                 *io_gpio = 3;
13029                 *io_port = 1;
13030                 break;
13031         default:
13032                 /* Don't override the io_gpio and io_port */
13033                 break;
13034         }
13035 }
13036
13037 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13038                                       u32 shmem_base_path[],
13039                                       u32 shmem2_base_path[], u8 phy_index,
13040                                       u32 chip_id)
13041 {
13042         s8 port, reset_gpio;
13043         u32 swap_val, swap_override;
13044         struct bnx2x_phy phy[PORT_MAX];
13045         struct bnx2x_phy *phy_blk[PORT_MAX];
13046         s8 port_of_path;
13047         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13048         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13049
13050         reset_gpio = MISC_REGISTERS_GPIO_1;
13051         port = 1;
13052
13053         /* Retrieve the reset gpio/port which control the reset.
13054          * Default is GPIO1, PORT1
13055          */
13056         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13057                                      (u8 *)&reset_gpio, (u8 *)&port);
13058
13059         /* Calculate the port based on port swap */
13060         port ^= (swap_val && swap_override);
13061
13062         /* Initiate PHY reset*/
13063         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13064                        port);
13065         usleep_range(1000, 2000);
13066         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13067                        port);
13068
13069         usleep_range(5000, 10000);
13070
13071         /* PART1 - Reset both phys */
13072         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13073                 u32 shmem_base, shmem2_base;
13074
13075                 /* In E2, same phy is using for port0 of the two paths */
13076                 if (CHIP_IS_E1x(bp)) {
13077                         shmem_base = shmem_base_path[0];
13078                         shmem2_base = shmem2_base_path[0];
13079                         port_of_path = port;
13080                 } else {
13081                         shmem_base = shmem_base_path[port];
13082                         shmem2_base = shmem2_base_path[port];
13083                         port_of_path = 0;
13084                 }
13085
13086                 /* Extract the ext phy address for the port */
13087                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13088                                        port_of_path, &phy[port]) !=
13089                                        0) {
13090                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13091                         return -EINVAL;
13092                 }
13093                 /* disable attentions */
13094                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13095                                port_of_path*4,
13096                                (NIG_MASK_XGXS0_LINK_STATUS |
13097                                 NIG_MASK_XGXS0_LINK10G |
13098                                 NIG_MASK_SERDES0_LINK_STATUS |
13099                                 NIG_MASK_MI_INT));
13100
13101
13102                 /* Reset the phy */
13103                 bnx2x_cl45_write(bp, &phy[port],
13104                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13105         }
13106
13107         /* Add delay of 150ms after reset */
13108         msleep(150);
13109         if (phy[PORT_0].addr & 0x1) {
13110                 phy_blk[PORT_0] = &(phy[PORT_1]);
13111                 phy_blk[PORT_1] = &(phy[PORT_0]);
13112         } else {
13113                 phy_blk[PORT_0] = &(phy[PORT_0]);
13114                 phy_blk[PORT_1] = &(phy[PORT_1]);
13115         }
13116         /* PART2 - Download firmware to both phys */
13117         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13118                 if (CHIP_IS_E1x(bp))
13119                         port_of_path = port;
13120                 else
13121                         port_of_path = 0;
13122                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13123                            phy_blk[port]->addr);
13124                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13125                                                       port_of_path))
13126                         return -EINVAL;
13127                 /* Disable PHY transmitter output */
13128                 bnx2x_cl45_write(bp, phy_blk[port],
13129                                  MDIO_PMA_DEVAD,
13130                                  MDIO_PMA_REG_TX_DISABLE, 1);
13131
13132         }
13133         return 0;
13134 }
13135
13136 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13137                                                 u32 shmem_base_path[],
13138                                                 u32 shmem2_base_path[],
13139                                                 u8 phy_index,
13140                                                 u32 chip_id)
13141 {
13142         u8 reset_gpios;
13143         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13144         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13145         udelay(10);
13146         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13147         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13148                 reset_gpios);
13149         return 0;
13150 }
13151
13152 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13153                                      u32 shmem2_base_path[], u8 phy_index,
13154                                      u32 ext_phy_type, u32 chip_id)
13155 {
13156         int rc = 0;
13157
13158         switch (ext_phy_type) {
13159         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13160                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13161                                                 shmem2_base_path,
13162                                                 phy_index, chip_id);
13163                 break;
13164         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13165         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13166         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13167                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13168                                                 shmem2_base_path,
13169                                                 phy_index, chip_id);
13170                 break;
13171
13172         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13173                 /* GPIO1 affects both ports, so there's need to pull
13174                  * it for single port alone
13175                  */
13176                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13177                                                 shmem2_base_path,
13178                                                 phy_index, chip_id);
13179                 break;
13180         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13181         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13182                 /* GPIO3's are linked, and so both need to be toggled
13183                  * to obtain required 2us pulse.
13184                  */
13185                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13186                                                 shmem2_base_path,
13187                                                 phy_index, chip_id);
13188                 break;
13189         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13190                 rc = -EINVAL;
13191                 break;
13192         default:
13193                 DP(NETIF_MSG_LINK,
13194                            "ext_phy 0x%x common init not required\n",
13195                            ext_phy_type);
13196                 break;
13197         }
13198
13199         if (rc)
13200                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13201                                       " Port %d\n",
13202                          0);
13203         return rc;
13204 }
13205
13206 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13207                           u32 shmem2_base_path[], u32 chip_id)
13208 {
13209         int rc = 0;
13210         u32 phy_ver, val;
13211         u8 phy_index = 0;
13212         u32 ext_phy_type, ext_phy_config;
13213
13214         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13215         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13216         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13217         if (CHIP_IS_E3(bp)) {
13218                 /* Enable EPIO */
13219                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13220                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13221         }
13222         /* Check if common init was already done */
13223         phy_ver = REG_RD(bp, shmem_base_path[0] +
13224                          offsetof(struct shmem_region,
13225                                   port_mb[PORT_0].ext_phy_fw_version));
13226         if (phy_ver) {
13227                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13228                                phy_ver);
13229                 return 0;
13230         }
13231
13232         /* Read the ext_phy_type for arbitrary port(0) */
13233         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13234               phy_index++) {
13235                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13236                                                           shmem_base_path[0],
13237                                                           phy_index, 0);
13238                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13239                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13240                                                 shmem2_base_path,
13241                                                 phy_index, ext_phy_type,
13242                                                 chip_id);
13243         }
13244         return rc;
13245 }
13246
13247 static void bnx2x_check_over_curr(struct link_params *params,
13248                                   struct link_vars *vars)
13249 {
13250         struct bnx2x *bp = params->bp;
13251         u32 cfg_pin;
13252         u8 port = params->port;
13253         u32 pin_val;
13254
13255         cfg_pin = (REG_RD(bp, params->shmem_base +
13256                           offsetof(struct shmem_region,
13257                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13258                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13259                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13260
13261         /* Ignore check if no external input PIN available */
13262         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13263                 return;
13264
13265         if (!pin_val) {
13266                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13267                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13268                                             " been detected and the power to "
13269                                             "that SFP+ module has been removed"
13270                                             " to prevent failure of the card."
13271                                             " Please remove the SFP+ module and"
13272                                             " restart the system to clear this"
13273                                             " error.\n",
13274                          params->port);
13275                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13276                         bnx2x_warpcore_power_module(params, 0);
13277                 }
13278         } else
13279                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13280 }
13281
13282 /* Returns 0 if no change occured since last check; 1 otherwise. */
13283 static u8 bnx2x_analyze_link_error(struct link_params *params,
13284                                     struct link_vars *vars, u32 status,
13285                                     u32 phy_flag, u32 link_flag, u8 notify)
13286 {
13287         struct bnx2x *bp = params->bp;
13288         /* Compare new value with previous value */
13289         u8 led_mode;
13290         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13291
13292         if ((status ^ old_status) == 0)
13293                 return 0;
13294
13295         /* If values differ */
13296         switch (phy_flag) {
13297         case PHY_HALF_OPEN_CONN_FLAG:
13298                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13299                 break;
13300         case PHY_SFP_TX_FAULT_FLAG:
13301                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13302                 break;
13303         default:
13304                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13305         }
13306         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13307            old_status, status);
13308
13309         /* a. Update shmem->link_status accordingly
13310          * b. Update link_vars->link_up
13311          */
13312         if (status) {
13313                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13314                 vars->link_status |= link_flag;
13315                 vars->link_up = 0;
13316                 vars->phy_flags |= phy_flag;
13317
13318                 /* activate nig drain */
13319                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13320                 /* Set LED mode to off since the PHY doesn't know about these
13321                  * errors
13322                  */
13323                 led_mode = LED_MODE_OFF;
13324         } else {
13325                 vars->link_status |= LINK_STATUS_LINK_UP;
13326                 vars->link_status &= ~link_flag;
13327                 vars->link_up = 1;
13328                 vars->phy_flags &= ~phy_flag;
13329                 led_mode = LED_MODE_OPER;
13330
13331                 /* Clear nig drain */
13332                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13333         }
13334         bnx2x_sync_link(params, vars);
13335         /* Update the LED according to the link state */
13336         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13337
13338         /* Update link status in the shared memory */
13339         bnx2x_update_mng(params, vars->link_status);
13340
13341         /* C. Trigger General Attention */
13342         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13343         if (notify)
13344                 bnx2x_notify_link_changed(bp);
13345
13346         return 1;
13347 }
13348
13349 /******************************************************************************
13350 * Description:
13351 *       This function checks for half opened connection change indication.
13352 *       When such change occurs, it calls the bnx2x_analyze_link_error
13353 *       to check if Remote Fault is set or cleared. Reception of remote fault
13354 *       status message in the MAC indicates that the peer's MAC has detected
13355 *       a fault, for example, due to break in the TX side of fiber.
13356 *
13357 ******************************************************************************/
13358 int bnx2x_check_half_open_conn(struct link_params *params,
13359                                 struct link_vars *vars,
13360                                 u8 notify)
13361 {
13362         struct bnx2x *bp = params->bp;
13363         u32 lss_status = 0;
13364         u32 mac_base;
13365         /* In case link status is physically up @ 10G do */
13366         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13367             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13368                 return 0;
13369
13370         if (CHIP_IS_E3(bp) &&
13371             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13372               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13373                 /* Check E3 XMAC */
13374                 /* Note that link speed cannot be queried here, since it may be
13375                  * zero while link is down. In case UMAC is active, LSS will
13376                  * simply not be set
13377                  */
13378                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13379
13380                 /* Clear stick bits (Requires rising edge) */
13381                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13382                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13383                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13384                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13385                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13386                         lss_status = 1;
13387
13388                 bnx2x_analyze_link_error(params, vars, lss_status,
13389                                          PHY_HALF_OPEN_CONN_FLAG,
13390                                          LINK_STATUS_NONE, notify);
13391         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13392                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13393                 /* Check E1X / E2 BMAC */
13394                 u32 lss_status_reg;
13395                 u32 wb_data[2];
13396                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13397                         NIG_REG_INGRESS_BMAC0_MEM;
13398                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13399                 if (CHIP_IS_E2(bp))
13400                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13401                 else
13402                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13403
13404                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13405                 lss_status = (wb_data[0] > 0);
13406
13407                 bnx2x_analyze_link_error(params, vars, lss_status,
13408                                          PHY_HALF_OPEN_CONN_FLAG,
13409                                          LINK_STATUS_NONE, notify);
13410         }
13411         return 0;
13412 }
13413 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13414                                          struct link_params *params,
13415                                          struct link_vars *vars)
13416 {
13417         struct bnx2x *bp = params->bp;
13418         u32 cfg_pin, value = 0;
13419         u8 led_change, port = params->port;
13420
13421         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13422         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13423                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13424                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13425                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13426
13427         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13428                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13429                 return;
13430         }
13431
13432         led_change = bnx2x_analyze_link_error(params, vars, value,
13433                                               PHY_SFP_TX_FAULT_FLAG,
13434                                               LINK_STATUS_SFP_TX_FAULT, 1);
13435
13436         if (led_change) {
13437                 /* Change TX_Fault led, set link status for further syncs */
13438                 u8 led_mode;
13439
13440                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13441                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13442                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13443                 } else {
13444                         led_mode = MISC_REGISTERS_GPIO_LOW;
13445                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13446                 }
13447
13448                 /* If module is unapproved, led should be on regardless */
13449                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13450                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13451                            led_mode);
13452                         bnx2x_set_e3_module_fault_led(params, led_mode);
13453                 }
13454         }
13455 }
13456 static void bnx2x_kr2_recovery(struct link_params *params,
13457                                struct link_vars *vars,
13458                                struct bnx2x_phy *phy)
13459 {
13460         struct bnx2x *bp = params->bp;
13461         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13462         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13463         bnx2x_warpcore_restart_AN_KR(phy, params);
13464 }
13465
13466 static void bnx2x_check_kr2_wa(struct link_params *params,
13467                                struct link_vars *vars,
13468                                struct bnx2x_phy *phy)
13469 {
13470         struct bnx2x *bp = params->bp;
13471         u16 base_page, next_page, not_kr2_device, lane;
13472         int sigdet;
13473
13474         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13475          * Since some switches tend to reinit the AN process and clear the
13476          * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13477          * and recovered many times
13478          */
13479         if (vars->check_kr2_recovery_cnt > 0) {
13480                 vars->check_kr2_recovery_cnt--;
13481                 return;
13482         }
13483
13484         sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13485         if (!sigdet) {
13486                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13487                         bnx2x_kr2_recovery(params, vars, phy);
13488                         DP(NETIF_MSG_LINK, "No sigdet\n");
13489                 }
13490                 return;
13491         }
13492
13493         lane = bnx2x_get_warpcore_lane(phy, params);
13494         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13495                           MDIO_AER_BLOCK_AER_REG, lane);
13496         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13497                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13498         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13499                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13500         bnx2x_set_aer_mmd(params, phy);
13501
13502         /* CL73 has not begun yet */
13503         if (base_page == 0) {
13504                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13505                         bnx2x_kr2_recovery(params, vars, phy);
13506                         DP(NETIF_MSG_LINK, "No BP\n");
13507                 }
13508                 return;
13509         }
13510
13511         /* In case NP bit is not set in the BasePage, or it is set,
13512          * but only KX is advertised, declare this link partner as non-KR2
13513          * device.
13514          */
13515         not_kr2_device = (((base_page & 0x8000) == 0) ||
13516                           (((base_page & 0x8000) &&
13517                             ((next_page & 0xe0) == 0x2))));
13518
13519         /* In case KR2 is already disabled, check if we need to re-enable it */
13520         if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13521                 if (!not_kr2_device) {
13522                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13523                            next_page);
13524                         bnx2x_kr2_recovery(params, vars, phy);
13525                 }
13526                 return;
13527         }
13528         /* KR2 is enabled, but not KR2 device */
13529         if (not_kr2_device) {
13530                 /* Disable KR2 on both lanes */
13531                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13532                 bnx2x_disable_kr2(params, vars, phy);
13533                 /* Restart AN on leading lane */
13534                 bnx2x_warpcore_restart_AN_KR(phy, params);
13535                 return;
13536         }
13537 }
13538
13539 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13540 {
13541         u16 phy_idx;
13542         struct bnx2x *bp = params->bp;
13543         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13544                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13545                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13546                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13547                             0)
13548                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13549                         break;
13550                 }
13551         }
13552
13553         if (CHIP_IS_E3(bp)) {
13554                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13555                 bnx2x_set_aer_mmd(params, phy);
13556                 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13557                     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13558                         bnx2x_check_kr2_wa(params, vars, phy);
13559                 bnx2x_check_over_curr(params, vars);
13560                 if (vars->rx_tx_asic_rst)
13561                         bnx2x_warpcore_config_runtime(phy, params, vars);
13562
13563                 if ((REG_RD(bp, params->shmem_base +
13564                             offsetof(struct shmem_region, dev_info.
13565                                 port_hw_config[params->port].default_cfg))
13566                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13567                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13568                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13569                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13570                         } else if (vars->link_status &
13571                                 LINK_STATUS_SFP_TX_FAULT) {
13572                                 /* Clean trail, interrupt corrects the leds */
13573                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13574                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13575                                 /* Update link status in the shared memory */
13576                                 bnx2x_update_mng(params, vars->link_status);
13577                         }
13578                 }
13579         }
13580 }
13581
13582 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13583                              u32 shmem_base,
13584                              u32 shmem2_base,
13585                              u8 port)
13586 {
13587         u8 phy_index, fan_failure_det_req = 0;
13588         struct bnx2x_phy phy;
13589         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13590               phy_index++) {
13591                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13592                                        port, &phy)
13593                     != 0) {
13594                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13595                         return 0;
13596                 }
13597                 fan_failure_det_req |= (phy.flags &
13598                                         FLAGS_FAN_FAILURE_DET_REQ);
13599         }
13600         return fan_failure_det_req;
13601 }
13602
13603 void bnx2x_hw_reset_phy(struct link_params *params)
13604 {
13605         u8 phy_index;
13606         struct bnx2x *bp = params->bp;
13607         bnx2x_update_mng(params, 0);
13608         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13609                        (NIG_MASK_XGXS0_LINK_STATUS |
13610                         NIG_MASK_XGXS0_LINK10G |
13611                         NIG_MASK_SERDES0_LINK_STATUS |
13612                         NIG_MASK_MI_INT));
13613
13614         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13615               phy_index++) {
13616                 if (params->phy[phy_index].hw_reset) {
13617                         params->phy[phy_index].hw_reset(
13618                                 &params->phy[phy_index],
13619                                 params);
13620                         params->phy[phy_index] = phy_null;
13621                 }
13622         }
13623 }
13624
13625 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13626                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13627                             u8 port)
13628 {
13629         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13630         u32 val;
13631         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13632         if (CHIP_IS_E3(bp)) {
13633                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13634                                               shmem_base,
13635                                               port,
13636                                               &gpio_num,
13637                                               &gpio_port) != 0)
13638                         return;
13639         } else {
13640                 struct bnx2x_phy phy;
13641                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13642                       phy_index++) {
13643                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13644                                                shmem2_base, port, &phy)
13645                             != 0) {
13646                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
13647                                 return;
13648                         }
13649                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13650                                 gpio_num = MISC_REGISTERS_GPIO_3;
13651                                 gpio_port = port;
13652                                 break;
13653                         }
13654                 }
13655         }
13656
13657         if (gpio_num == 0xff)
13658                 return;
13659
13660         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13661         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13662
13663         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13664         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13665         gpio_port ^= (swap_val && swap_override);
13666
13667         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13668                 (gpio_num + (gpio_port << 2));
13669
13670         sync_offset = shmem_base +
13671                 offsetof(struct shmem_region,
13672                          dev_info.port_hw_config[port].aeu_int_mask);
13673         REG_WR(bp, sync_offset, vars->aeu_int_mask);
13674
13675         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13676                        gpio_num, gpio_port, vars->aeu_int_mask);
13677
13678         if (port == 0)
13679                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13680         else
13681                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13682
13683         /* Open appropriate AEU for interrupts */
13684         aeu_mask = REG_RD(bp, offset);
13685         aeu_mask |= vars->aeu_int_mask;
13686         REG_WR(bp, offset, aeu_mask);
13687
13688         /* Enable the GPIO to trigger interrupt */
13689         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13690         val |= 1 << (gpio_num + (gpio_port << 2));
13691         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13692 }