1 /* bnx2x_cmn.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
20 #include <linux/types.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
26 #include "bnx2x_sriov.h"
28 /* This is used as a replacement for an MCP if it's not present */
29 extern int bnx2x_load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
30 extern int bnx2x_num_queues;
32 /************************ Macros ********************************/
33 #define BNX2X_PCI_FREE(x, y, size) \
36 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
42 #define BNX2X_FREE(x) \
50 #define BNX2X_PCI_ALLOC(x, y, size) \
52 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
55 DP(NETIF_MSG_HW, "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \
56 (unsigned long long)(*y), x); \
59 #define BNX2X_PCI_FALLOC(x, y, size) \
61 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
64 memset((void *)x, 0xFFFFFFFF, size); \
65 DP(NETIF_MSG_HW, "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n",\
66 (unsigned long long)(*y), x); \
69 #define BNX2X_ALLOC(x, size) \
71 x = kzalloc(size, GFP_KERNEL); \
76 /*********************** Interfaces ****************************
77 * Functions that need to be implemented by each driver version
82 * bnx2x_send_unload_req - request unload mode from the MCP.
85 * @unload_mode: requested function's unload mode
87 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
89 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
92 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
95 * @keep_link: true iff link should be kept up
97 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link);
100 * bnx2x_config_rss_pf - configure RSS parameters in a PF.
103 * @rss_obj: RSS object to use
104 * @ind_table: indirection table to configure
105 * @config_hash: re-configure RSS hash keys configuration
106 * @enable: enabled or disabled configuration
108 int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
109 bool config_hash, bool enable);
112 * bnx2x__init_func_obj - init function object
116 * Initializes the Function Object with the appropriate
117 * parameters which include a function slow path driver
120 void bnx2x__init_func_obj(struct bnx2x *bp);
123 * bnx2x_setup_queue - setup eth queue.
126 * @fp: pointer to the fastpath structure
130 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
134 * bnx2x_setup_leading - bring up a leading eth queue.
138 int bnx2x_setup_leading(struct bnx2x *bp);
141 * bnx2x_fw_command - send the MCP a request
145 * @param: request's parameter
147 * block until there is a reply
149 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
152 * bnx2x_initial_phy_init - initialize link parameters structure variables.
155 * @load_mode: current mode
157 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
160 * bnx2x_link_set - configure hw according to link parameters structure.
164 void bnx2x_link_set(struct bnx2x *bp);
167 * bnx2x_force_link_reset - Forces link reset, and put the PHY
172 void bnx2x_force_link_reset(struct bnx2x *bp);
175 * bnx2x_link_test - query link status.
180 * Returns 0 if link is UP.
182 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
185 * bnx2x_drv_pulse - write driver pulse to shmem
189 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
192 void bnx2x_drv_pulse(struct bnx2x *bp);
195 * bnx2x_igu_ack_sb - update IGU with current SB value
199 * @segment: SB segment
202 * @update: is HW update required
204 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
205 u16 index, u8 op, u8 update);
207 /* Disable transactions from chip to host */
208 void bnx2x_pf_disable(struct bnx2x *bp);
209 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
212 * bnx2x__link_status_update - handles link status change.
216 void bnx2x__link_status_update(struct bnx2x *bp);
219 * bnx2x_link_report - report link status to upper layer.
223 void bnx2x_link_report(struct bnx2x *bp);
225 /* None-atomic version of bnx2x_link_report() */
226 void __bnx2x_link_report(struct bnx2x *bp);
229 * bnx2x_get_mf_speed - calculate MF speed.
233 * Takes into account current linespeed and MF configuration.
235 u16 bnx2x_get_mf_speed(struct bnx2x *bp);
238 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
241 * @dev_instance: private instance
243 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
246 * bnx2x_interrupt - non MSI-X interrupt handler
249 * @dev_instance: private instance
251 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
254 * bnx2x_cnic_notify - send command to cnic driver
259 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
262 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
266 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
269 * bnx2x_setup_cnic_info - provides cnic with updated info
273 void bnx2x_setup_cnic_info(struct bnx2x *bp);
276 * bnx2x_int_enable - enable HW interrupts.
280 void bnx2x_int_enable(struct bnx2x *bp);
283 * bnx2x_int_disable_sync - disable interrupts.
286 * @disable_hw: true, disable HW interrupts.
288 * This function ensures that there are no
289 * ISRs or SP DPCs (sp_task) are running after it returns.
291 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
294 * bnx2x_nic_init_cnic - init driver internals for cnic.
297 * @load_code: COMMON, PORT or FUNCTION
304 void bnx2x_nic_init_cnic(struct bnx2x *bp);
307 * bnx2x_preirq_nic_init - init driver internals.
316 void bnx2x_pre_irq_nic_init(struct bnx2x *bp);
319 * bnx2x_postirq_nic_init - init driver internals.
322 * @load_code: COMMON, PORT or FUNCTION
329 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code);
331 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic.
335 int bnx2x_alloc_mem_cnic(struct bnx2x *bp);
337 * bnx2x_alloc_mem - allocate driver's memory.
341 int bnx2x_alloc_mem(struct bnx2x *bp);
344 * bnx2x_free_mem_cnic - release driver's memory for cnic.
348 void bnx2x_free_mem_cnic(struct bnx2x *bp);
350 * bnx2x_free_mem - release driver's memory.
354 void bnx2x_free_mem(struct bnx2x *bp);
357 * bnx2x_set_num_queues - set number of queues according to mode.
361 void bnx2x_set_num_queues(struct bnx2x *bp);
364 * bnx2x_chip_cleanup - cleanup chip internals.
367 * @unload_mode: COMMON, PORT, FUNCTION
368 * @keep_link: true iff link should be kept up.
370 * - Cleanup MAC configuration.
374 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link);
377 * bnx2x_acquire_hw_lock - acquire HW lock.
380 * @resource: resource bit which was locked
382 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
385 * bnx2x_release_hw_lock - release HW lock.
388 * @resource: resource bit which was locked
390 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
393 * bnx2x_release_leader_lock - release recovery leader lock
397 int bnx2x_release_leader_lock(struct bnx2x *bp);
400 * bnx2x_set_eth_mac - configure eth MAC address in the HW
405 * Configures according to the value in netdev->dev_addr.
407 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
410 * bnx2x_set_rx_mode - set MAC filtering configurations.
414 * called with netif_tx_lock from dev_mcast.c
415 * If bp->state is OPEN, should be called with
416 * netif_addr_lock_bh()
418 void bnx2x_set_rx_mode_inner(struct bnx2x *bp);
420 /* Parity errors related */
421 void bnx2x_set_pf_load(struct bnx2x *bp);
422 bool bnx2x_clear_pf_load(struct bnx2x *bp);
423 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
424 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
425 void bnx2x_set_reset_in_progress(struct bnx2x *bp);
426 void bnx2x_set_reset_global(struct bnx2x *bp);
427 void bnx2x_disable_close_the_gate(struct bnx2x *bp);
428 int bnx2x_init_hw_func_cnic(struct bnx2x *bp);
431 * bnx2x_sp_event - handle ramrods completion.
433 * @fp: fastpath handle for the event
434 * @rr_cqe: eth_rx_cqe
436 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
439 * bnx2x_ilt_set_info - prepare ILT configurations.
443 void bnx2x_ilt_set_info(struct bnx2x *bp);
446 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC
451 void bnx2x_ilt_set_info_cnic(struct bnx2x *bp);
454 * bnx2x_dcbx_init - initialize dcbx protocol.
458 void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem);
461 * bnx2x_set_power_state - set power state to the requested value.
464 * @state: required state D0 or D3hot
466 * Currently only D0 and D3hot are supported.
468 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
471 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
476 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
478 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
480 /* dev_close main block */
481 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link);
483 /* dev_open main block */
484 int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
486 /* hard_xmit callback */
487 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
489 /* setup_tc callback */
490 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
492 int bnx2x_get_vf_config(struct net_device *dev, int vf,
493 struct ifla_vf_info *ivi);
494 int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac);
495 int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos);
497 /* select_queue callback */
498 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
500 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
501 struct bnx2x_fastpath *fp,
502 u16 bd_prod, u16 rx_comp_prod,
505 struct ustorm_eth_rx_producers rx_prods = {0};
508 /* Update producers */
509 rx_prods.bd_prod = bd_prod;
510 rx_prods.cqe_prod = rx_comp_prod;
511 rx_prods.sge_prod = rx_sge_prod;
513 /* Make sure that the BD and SGE data is updated before updating the
514 * producers since FW might read the BD/SGE right after the producer
516 * This is only applicable for weak-ordered memory model archs such
517 * as IA-64. The following barrier is also mandatory since FW will
518 * assumes BDs must have buffers.
522 for (i = 0; i < sizeof(rx_prods)/4; i++)
523 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4,
524 ((u32 *)&rx_prods)[i]);
526 mmiowb(); /* keep prod updates ordered */
528 DP(NETIF_MSG_RX_STATUS,
529 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
530 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
534 int bnx2x_reload_if_running(struct net_device *dev);
536 int bnx2x_change_mac_addr(struct net_device *dev, void *p);
538 /* NAPI poll Tx part */
539 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
541 /* suspend/resume callbacks */
542 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
543 int bnx2x_resume(struct pci_dev *pdev);
545 /* Release IRQ vectors */
546 void bnx2x_free_irq(struct bnx2x *bp);
548 void bnx2x_free_fp_mem(struct bnx2x *bp);
549 void bnx2x_init_rx_rings(struct bnx2x *bp);
550 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp);
551 void bnx2x_free_skbs(struct bnx2x *bp);
552 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
553 void bnx2x_netif_start(struct bnx2x *bp);
554 int bnx2x_load_cnic(struct bnx2x *bp);
557 * bnx2x_enable_msix - set msix configuration.
561 * fills msix_table, requests vectors, updates num_queues
562 * according to number of available vectors.
564 int bnx2x_enable_msix(struct bnx2x *bp);
567 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
571 int bnx2x_enable_msi(struct bnx2x *bp);
574 * bnx2x_low_latency_recv - LL callback
576 * @napi: napi structure
578 int bnx2x_low_latency_recv(struct napi_struct *napi);
581 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
585 int bnx2x_alloc_mem_bp(struct bnx2x *bp);
588 * bnx2x_free_mem_bp - release memories outsize main driver structure
592 void bnx2x_free_mem_bp(struct bnx2x *bp);
595 * bnx2x_change_mtu - change mtu netdev callback
598 * @new_mtu: requested mtu
601 int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
603 #ifdef NETDEV_FCOE_WWNN
605 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
608 * @wwn: output buffer
609 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
612 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
615 netdev_features_t bnx2x_fix_features(struct net_device *dev,
616 netdev_features_t features);
617 int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
620 * bnx2x_tx_timeout - tx timeout netdev callback
624 void bnx2x_tx_timeout(struct net_device *dev);
626 /*********************** Inlines **********************************/
627 /*********************** Fast path ********************************/
628 static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
630 barrier(); /* status block is written to by the chip */
631 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
634 static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
635 u8 segment, u16 index, u8 op,
636 u8 update, u32 igu_addr)
638 struct igu_regular cmd_data = {0};
640 cmd_data.sb_id_and_flags =
641 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
642 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
643 (update << IGU_REGULAR_BUPDATE_SHIFT) |
644 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
646 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
647 cmd_data.sb_id_and_flags, igu_addr);
648 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
650 /* Make sure that ACK is written */
655 static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
656 u8 storm, u16 index, u8 op, u8 update)
658 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
659 COMMAND_REG_INT_ACK);
660 struct igu_ack_register igu_ack;
662 igu_ack.status_block_index = index;
663 igu_ack.sb_id_and_flags =
664 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
665 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
666 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
667 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
669 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
671 /* Make sure that ACK is written */
676 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
677 u16 index, u8 op, u8 update)
679 if (bp->common.int_block == INT_BLOCK_HC)
680 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
684 if (CHIP_INT_MODE_IS_BC(bp))
686 else if (igu_sb_id != bp->igu_dsb_id)
687 segment = IGU_SEG_ACCESS_DEF;
688 else if (storm == ATTENTION_ID)
689 segment = IGU_SEG_ACCESS_ATTN;
691 segment = IGU_SEG_ACCESS_DEF;
692 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
696 static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
698 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
699 COMMAND_REG_SIMD_MASK);
700 u32 result = REG_RD(bp, hc_addr);
706 static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
708 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
709 u32 result = REG_RD(bp, igu_addr);
711 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
718 static inline u16 bnx2x_ack_int(struct bnx2x *bp)
721 if (bp->common.int_block == INT_BLOCK_HC)
722 return bnx2x_hc_ack_int(bp);
724 return bnx2x_igu_ack_int(bp);
727 static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
729 /* Tell compiler that consumer and producer can change */
731 return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
734 static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
735 struct bnx2x_fp_txdata *txdata)
741 prod = txdata->tx_bd_prod;
742 cons = txdata->tx_bd_cons;
744 used = SUB_S16(prod, cons);
746 #ifdef BNX2X_STOP_ON_ERROR
748 WARN_ON(used > txdata->tx_ring_size);
749 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL);
752 return (s16)(txdata->tx_ring_size) - used;
755 static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
759 /* Tell compiler that status block fields can change */
761 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
762 return hw_cons != txdata->tx_pkt_cons;
765 static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
768 for_each_cos_in_tx_queue(fp, cos)
769 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
774 #define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0)
775 #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF)
776 static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
779 union eth_rx_cqe *cqe;
780 struct eth_fast_path_rx_cqe *cqe_fp;
782 cons = RCQ_BD(fp->rx_comp_cons);
783 cqe = &fp->rx_comp_ring[cons];
784 cqe_fp = &cqe->fast_path_cqe;
785 return BNX2X_IS_CQE_COMPLETED(cqe_fp);
789 * bnx2x_tx_disable - disables tx from stack point of view
793 static inline void bnx2x_tx_disable(struct bnx2x *bp)
795 netif_tx_disable(bp->dev);
796 netif_carrier_off(bp->dev);
799 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
800 struct bnx2x_fastpath *fp, u16 index)
802 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
803 struct page *page = sw_buf->page;
804 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
806 /* Skip "next page" elements */
810 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
811 SGE_PAGES, DMA_FROM_DEVICE);
812 __free_pages(page, PAGES_PER_SGE_SHIFT);
819 static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp)
823 for_each_rx_queue_cnic(bp, i) {
824 napi_hash_del(&bnx2x_fp(bp, i, napi));
825 netif_napi_del(&bnx2x_fp(bp, i, napi));
829 static inline void bnx2x_del_all_napi(struct bnx2x *bp)
833 for_each_eth_queue(bp, i) {
834 napi_hash_del(&bnx2x_fp(bp, i, napi));
835 netif_napi_del(&bnx2x_fp(bp, i, napi));
839 int bnx2x_set_int_mode(struct bnx2x *bp);
841 static inline void bnx2x_disable_msi(struct bnx2x *bp)
843 if (bp->flags & USING_MSIX_FLAG) {
844 pci_disable_msix(bp->pdev);
845 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG);
846 } else if (bp->flags & USING_MSI_FLAG) {
847 pci_disable_msi(bp->pdev);
848 bp->flags &= ~USING_MSI_FLAG;
852 static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
856 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
857 int idx = RX_SGE_CNT * i - 1;
859 for (j = 0; j < 2; j++) {
860 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
866 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
868 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
869 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
871 /* Clear the two last indices in the page to 1:
872 these are the indices that correspond to the "next" element,
873 hence will never be indicated and should be removed from
875 bnx2x_clear_sge_mask_next_elems(fp);
878 /* note that we are not allocating a new buffer,
879 * we are just moving one from cons to prod
880 * we are not creating a new mapping,
881 * so there is no need to check for dma_mapping_error().
883 static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
886 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
887 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
888 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
889 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
891 dma_unmap_addr_set(prod_rx_buf, mapping,
892 dma_unmap_addr(cons_rx_buf, mapping));
893 prod_rx_buf->data = cons_rx_buf->data;
897 /************************* Init ******************************************/
899 /* returns func by VN for current port */
900 static inline int func_by_vn(struct bnx2x *bp, int vn)
902 return 2 * vn + BP_PORT(bp);
905 static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash)
907 return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true);
911 * bnx2x_func_start - init function
915 * Must be called before sending CLIENT_SETUP for the first client.
917 static inline int bnx2x_func_start(struct bnx2x *bp)
919 struct bnx2x_func_state_params func_params = {NULL};
920 struct bnx2x_func_start_params *start_params =
921 &func_params.params.start;
923 /* Prepare parameters for function state transitions */
924 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
926 func_params.f_obj = &bp->func_obj;
927 func_params.cmd = BNX2X_F_CMD_START;
929 /* Function parameters */
930 start_params->mf_mode = bp->mf_mode;
931 start_params->sd_vlan_tag = bp->mf_ov;
933 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
934 start_params->network_cos_mode = STATIC_COS;
935 else /* CHIP_IS_E1X */
936 start_params->network_cos_mode = FW_WRR;
938 start_params->gre_tunnel_mode = IPGRE_TUNNEL;
939 start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS;
941 return bnx2x_func_state_change(bp, &func_params);
945 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
947 * @fw_hi: pointer to upper part
948 * @fw_mid: pointer to middle part
949 * @fw_lo: pointer to lower part
950 * @mac: pointer to MAC address
952 static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid,
953 __le16 *fw_lo, u8 *mac)
955 ((u8 *)fw_hi)[0] = mac[1];
956 ((u8 *)fw_hi)[1] = mac[0];
957 ((u8 *)fw_mid)[0] = mac[3];
958 ((u8 *)fw_mid)[1] = mac[2];
959 ((u8 *)fw_lo)[0] = mac[5];
960 ((u8 *)fw_lo)[1] = mac[4];
963 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
964 struct bnx2x_fastpath *fp, int last)
971 for (i = 0; i < last; i++)
972 bnx2x_free_rx_sge(bp, fp, i);
975 static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
979 for (i = 1; i <= NUM_RX_RINGS; i++) {
980 struct eth_rx_bd *rx_bd;
982 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
984 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
985 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
987 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
988 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
992 /* Statistics ID are global per chip/path, while Client IDs for E1x are per
995 static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
997 struct bnx2x *bp = fp->bp;
998 if (!CHIP_IS_E1x(bp)) {
999 /* there are special statistics counters for FCoE 136..140 */
1001 return bp->cnic_base_cl_id + (bp->pf_num >> 1);
1004 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x;
1007 static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
1008 bnx2x_obj_type obj_type)
1010 struct bnx2x *bp = fp->bp;
1012 /* Configure classification DBs */
1013 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id,
1014 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
1015 bnx2x_sp_mapping(bp, mac_rdata),
1016 BNX2X_FILTER_MAC_PENDING,
1017 &bp->sp_state, obj_type,
1022 * bnx2x_get_path_func_num - get number of active functions
1024 * @bp: driver handle
1026 * Calculates the number of active (not hidden) functions on the
1029 static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
1033 /* 57710 has only one function per-port */
1037 /* Calculate a number of functions enabled on the current
1040 if (CHIP_REV_IS_SLOW(bp)) {
1046 for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
1049 func_mf_config[BP_PORT(bp) + 2 * i].
1052 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
1061 static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
1063 /* RX_MODE controlling object */
1064 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
1066 /* multicast configuration controlling object */
1067 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
1068 BP_FUNC(bp), BP_FUNC(bp),
1069 bnx2x_sp(bp, mcast_rdata),
1070 bnx2x_sp_mapping(bp, mcast_rdata),
1071 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
1074 /* Setup CAM credit pools */
1075 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
1076 bnx2x_get_path_func_num(bp));
1078 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1,
1079 bnx2x_get_path_func_num(bp));
1081 /* RSS configuration object */
1082 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
1083 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
1084 bnx2x_sp(bp, rss_rdata),
1085 bnx2x_sp_mapping(bp, rss_rdata),
1086 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
1090 static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
1092 if (CHIP_IS_E1x(fp->bp))
1093 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
1098 static inline void bnx2x_init_txdata(struct bnx2x *bp,
1099 struct bnx2x_fp_txdata *txdata, u32 cid,
1100 int txq_index, __le16 *tx_cons_sb,
1101 struct bnx2x_fastpath *fp)
1104 txdata->txq_index = txq_index;
1105 txdata->tx_cons_sb = tx_cons_sb;
1106 txdata->parent_fp = fp;
1107 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size;
1109 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1110 txdata->cid, txdata->txq_index);
1113 static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
1115 return bp->cnic_base_cl_id + cl_idx +
1116 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
1119 static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
1121 /* the 'first' id is allocated for the cnic */
1122 return bp->base_fw_ndsb;
1125 static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
1127 return bp->igu_base_sb;
1130 static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1131 struct bnx2x_fp_txdata *txdata)
1135 while (bnx2x_has_tx_work_unload(txdata)) {
1137 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1138 txdata->txq_index, txdata->tx_pkt_prod,
1139 txdata->tx_pkt_cons);
1140 #ifdef BNX2X_STOP_ON_ERROR
1148 usleep_range(1000, 2000);
1154 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1156 static inline void __storm_memset_struct(struct bnx2x *bp,
1157 u32 addr, size_t size, u32 *data)
1160 for (i = 0; i < size/4; i++)
1161 REG_WR(bp, addr + (i * 4), data[i]);
1165 * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
1167 * @bp: driver handle
1168 * @mask: bits that need to be cleared
1170 static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1172 int tout = 5000; /* Wait for 5 secs tops */
1176 netif_addr_lock_bh(bp->dev);
1177 if (!(bp->sp_state & mask)) {
1178 netif_addr_unlock_bh(bp->dev);
1181 netif_addr_unlock_bh(bp->dev);
1183 usleep_range(1000, 2000);
1188 netif_addr_lock_bh(bp->dev);
1189 if (bp->sp_state & mask) {
1190 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1191 bp->sp_state, mask);
1192 netif_addr_unlock_bh(bp->dev);
1195 netif_addr_unlock_bh(bp->dev);
1201 * bnx2x_set_ctx_validation - set CDU context validation values
1203 * @bp: driver handle
1204 * @cxt: context of the connection on the host memory
1205 * @cid: SW CID of the connection to be configured
1207 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
1210 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
1211 u8 sb_index, u8 disable, u16 usec);
1212 void bnx2x_acquire_phy_lock(struct bnx2x *bp);
1213 void bnx2x_release_phy_lock(struct bnx2x *bp);
1216 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
1218 * @bp: driver handle
1219 * @mf_cfg: MF configuration
1222 static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1224 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1225 FUNC_MF_CFG_MAX_BW_SHIFT;
1227 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1228 "Max BW configured to 0 - using 100 instead\n");
1234 /* checks if HW supports GRO for given MTU */
1235 static inline bool bnx2x_mtu_allows_gro(int mtu)
1237 /* gro frags per page */
1238 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE);
1241 * 1. Number of frags should not grow above MAX_SKB_FRAGS
1242 * 2. Frag must fit the page
1244 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
1248 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
1250 * @bp: driver handle
1253 void bnx2x_get_iscsi_info(struct bnx2x *bp);
1256 * bnx2x_link_sync_notify - send notification to other functions.
1258 * @bp: driver handle
1261 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
1266 /* Set the attention towards other drivers on the same port */
1267 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
1268 if (vn == BP_VN(bp))
1271 func = func_by_vn(bp, vn);
1272 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
1273 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
1278 * bnx2x_update_drv_flags - update flags in shmem
1280 * @bp: driver handle
1281 * @flags: flags to update
1282 * @set: set or clear
1285 static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
1287 if (SHMEM2_HAS(bp, drv_flags)) {
1289 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1290 drv_flags = SHMEM2_RD(bp, drv_flags);
1293 SET_FLAGS(drv_flags, flags);
1295 RESET_FLAGS(drv_flags, flags);
1297 SHMEM2_WR(bp, drv_flags, drv_flags);
1298 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1299 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1303 static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr)
1305 if (is_valid_ether_addr(addr) ||
1306 (is_zero_ether_addr(addr) &&
1307 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))))
1314 * bnx2x_fill_fw_str - Fill buffer with FW version string
1316 * @bp: driver handle
1317 * @buf: character buffer to fill with the fw name
1318 * @buf_len: length of the above buffer
1321 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len);
1323 int bnx2x_drain_tx_queues(struct bnx2x *bp);
1324 void bnx2x_squeeze_objects(struct bnx2x *bp);
1326 #endif /* BNX2X_CMN_H */