2 * Copyright (c) 2013 Johannes Berg <johannes@sipsolutions.net>
4 * This file is free software: you may copy, redistribute and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation, either version 2 of the License, or (at your
7 * option) any later version.
9 * This file is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 * This file incorporates work covered by the following copyright and
20 * Copyright (c) 2012 Qualcomm Atheros, Inc.
22 * Permission to use, copy, modify, and/or distribute this software for any
23 * purpose with or without fee is hereby granted, provided that the above
24 * copyright notice and this permission notice appear in all copies.
26 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
27 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
28 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
29 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
30 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
31 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
32 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
37 #include <linux/types.h>
38 #include <linux/mdio.h>
39 #include <linux/pci.h>
42 /* Transmit Packet Descriptor, contains 4 32-bit words.
45 * +----------------+----------------+
46 * | vlan-tag | buf length |
47 * +----------------+----------------+
49 * +----------------+----------------+
50 * | Word 2: buf addr lo |
51 * +----------------+----------------+
52 * | Word 3: buf addr hi |
53 * +----------------+----------------+
55 * Word 2 and 3 combine to form a 64-bit buffer address
57 * Word 1 has three forms, depending on the state of bit 8/12/13:
58 * if bit8 =='1', the definition is just for custom checksum offload.
59 * if bit8 == '0' && bit12 == '1' && bit13 == '1', the *FIRST* descriptor
60 * for the skb is special for LSO V2, Word 2 become total skb length ,
61 * Word 3 is meaningless.
62 * other condition, the definition is for general skb or ip/tcp/udp
63 * checksum or LSO(TSO) offload.
65 * Here is the depiction:
70 * 3 | Payload offset 3 | L4 header offset
75 * 8 Custom csum enable = 1 8 Custom csum enable = 0
76 * 9 General IPv4 checksum 9 General IPv4 checksum
77 * 10 General TCP checksum 10 General TCP checksum
78 * 11 General UDP checksum 11 General UDP checksum
79 * 12 Large Send Segment enable 12 Large Send Segment enable
80 * 13 Large Send Segment type 13 Large Send Segment type
81 * 14 VLAN tagged 14 VLAN tagged
82 * 15 Insert VLAN tag 15 Insert VLAN tag
83 * 16 IPv4 packet 16 IPv4 packet
84 * 17 Ethernet frame type 17 Ethernet frame type
88 * 21 | Custom csum offset 21 |
90 * 23 | 23 | MSS (30:18)
98 * 31 End of packet 31 End of packet
114 #define TPD_CXSUMSTART_MASK 0x00FF
115 #define TPD_CXSUMSTART_SHIFT 0
116 #define TPD_L4HDROFFSET_MASK 0x00FF
117 #define TPD_L4HDROFFSET_SHIFT 0
118 #define TPD_CXSUM_EN_MASK 0x0001
119 #define TPD_CXSUM_EN_SHIFT 8
120 #define TPD_IP_XSUM_MASK 0x0001
121 #define TPD_IP_XSUM_SHIFT 9
122 #define TPD_TCP_XSUM_MASK 0x0001
123 #define TPD_TCP_XSUM_SHIFT 10
124 #define TPD_UDP_XSUM_MASK 0x0001
125 #define TPD_UDP_XSUM_SHIFT 11
126 #define TPD_LSO_EN_MASK 0x0001
127 #define TPD_LSO_EN_SHIFT 12
128 #define TPD_LSO_V2_MASK 0x0001
129 #define TPD_LSO_V2_SHIFT 13
130 #define TPD_VLTAGGED_MASK 0x0001
131 #define TPD_VLTAGGED_SHIFT 14
132 #define TPD_INS_VLTAG_MASK 0x0001
133 #define TPD_INS_VLTAG_SHIFT 15
134 #define TPD_IPV4_MASK 0x0001
135 #define TPD_IPV4_SHIFT 16
136 #define TPD_ETHTYPE_MASK 0x0001
137 #define TPD_ETHTYPE_SHIFT 17
138 #define TPD_CXSUMOFFSET_MASK 0x00FF
139 #define TPD_CXSUMOFFSET_SHIFT 18
140 #define TPD_MSS_MASK 0x1FFF
141 #define TPD_MSS_SHIFT 18
142 #define TPD_EOP_MASK 0x0001
143 #define TPD_EOP_SHIFT 31
145 #define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK)
147 /* Receive Free Descriptor */
149 __le64 addr; /* data buffer address, length is
150 * declared in register --- every
151 * buffer has the same size
155 /* Receive Return Descriptor, contains 4 32-bit words.
158 * +----------------+----------------+
160 * +----------------+----------------+
161 * | Word 1: RSS Hash value |
162 * +----------------+----------------+
164 * +----------------+----------------+
166 * +----------------+----------------+
168 * Word 0 depiction & Word 2 depiction:
177 * 7 | IP payload checksum 7 | VLAN tag
178 * 8 | (15:0) 8 | (15:0)
187 * 17 | Number of RFDs 17 |
189 * 19-+ 19 | Protocol ID
195 * 25 | Start index of RFD-ring 25-+
196 * 26 | (31:20) 26 | RSS Q-num (27:25)
199 * 29 | 29 | RSS Hash algorithm
212 * 7 | Packet length (include FCS)
219 * 14 L4 Header checksum error
220 * 15 IPv4 checksum error
223 * 18 | Protocol ID (19:17)
225 * 20 Receive error summary
227 * 22 Frame alignment error
228 * 23 Truncated packet
230 * 25 Incomplete packet due to insufficient rx-desc
231 * 26 Broadcast packet
232 * 27 Multicast packet
233 * 28 Ethernet type (EII or 802.3)
235 * 30 Length error (for 802.3, length field mismatch with actual len)
236 * 31 Updated, indicate to driver that this RRD is refreshed.
246 #define RRD_XSUM_MASK 0xFFFF
247 #define RRD_XSUM_SHIFT 0
248 #define RRD_NOR_MASK 0x000F
249 #define RRD_NOR_SHIFT 16
250 #define RRD_SI_MASK 0x0FFF
251 #define RRD_SI_SHIFT 20
254 #define RRD_VLTAG_MASK 0xFFFF
255 #define RRD_VLTAG_SHIFT 0
256 #define RRD_PID_MASK 0x00FF
257 #define RRD_PID_SHIFT 16
259 #define RRD_PID_NONIP 0
261 #define RRD_PID_IPV4 1
263 #define RRD_PID_IPV6TCP 2
265 #define RRD_PID_IPV4TCP 3
267 #define RRD_PID_IPV6UDP 4
269 #define RRD_PID_IPV4UDP 5
271 #define RRD_PID_IPV6 6
273 #define RRD_PID_LLDP 7
275 #define RRD_PID_1588 8
276 #define RRD_RSSQ_MASK 0x0007
277 #define RRD_RSSQ_SHIFT 25
278 #define RRD_RSSALG_MASK 0x000F
279 #define RRD_RSSALG_SHIFT 28
280 #define RRD_RSSALG_TCPV6 0x1
281 #define RRD_RSSALG_IPV6 0x2
282 #define RRD_RSSALG_TCPV4 0x4
283 #define RRD_RSSALG_IPV4 0x8
286 #define RRD_PKTLEN_MASK 0x3FFF
287 #define RRD_PKTLEN_SHIFT 0
288 #define RRD_ERR_L4_MASK 0x0001
289 #define RRD_ERR_L4_SHIFT 14
290 #define RRD_ERR_IPV4_MASK 0x0001
291 #define RRD_ERR_IPV4_SHIFT 15
292 #define RRD_VLTAGGED_MASK 0x0001
293 #define RRD_VLTAGGED_SHIFT 16
294 #define RRD_OLD_PID_MASK 0x0007
295 #define RRD_OLD_PID_SHIFT 17
296 #define RRD_ERR_RES_MASK 0x0001
297 #define RRD_ERR_RES_SHIFT 20
298 #define RRD_ERR_FCS_MASK 0x0001
299 #define RRD_ERR_FCS_SHIFT 21
300 #define RRD_ERR_FAE_MASK 0x0001
301 #define RRD_ERR_FAE_SHIFT 22
302 #define RRD_ERR_TRUNC_MASK 0x0001
303 #define RRD_ERR_TRUNC_SHIFT 23
304 #define RRD_ERR_RUNT_MASK 0x0001
305 #define RRD_ERR_RUNT_SHIFT 24
306 #define RRD_ERR_ICMP_MASK 0x0001
307 #define RRD_ERR_ICMP_SHIFT 25
308 #define RRD_BCAST_MASK 0x0001
309 #define RRD_BCAST_SHIFT 26
310 #define RRD_MCAST_MASK 0x0001
311 #define RRD_MCAST_SHIFT 27
312 #define RRD_ETHTYPE_MASK 0x0001
313 #define RRD_ETHTYPE_SHIFT 28
314 #define RRD_ERR_FIFOV_MASK 0x0001
315 #define RRD_ERR_FIFOV_SHIFT 29
316 #define RRD_ERR_LEN_MASK 0x0001
317 #define RRD_ERR_LEN_SHIFT 30
318 #define RRD_UPDATED_MASK 0x0001
319 #define RRD_UPDATED_SHIFT 31
322 #define ALX_MAX_SETUP_LNK_CYCLE 50
324 /* for FlowControl */
325 #define ALX_FC_RX 0x01
326 #define ALX_FC_TX 0x02
327 #define ALX_FC_ANEG 0x04
329 /* for sleep control */
330 #define ALX_SLEEP_WOL_PHY 0x00000001
331 #define ALX_SLEEP_WOL_MAGIC 0x00000002
332 #define ALX_SLEEP_CIFS 0x00000004
333 #define ALX_SLEEP_ACTIVE (ALX_SLEEP_WOL_PHY | \
334 ALX_SLEEP_WOL_MAGIC | \
337 /* for RSS hash type */
338 #define ALX_RSS_HASH_TYPE_IPV4 0x1
339 #define ALX_RSS_HASH_TYPE_IPV4_TCP 0x2
340 #define ALX_RSS_HASH_TYPE_IPV6 0x4
341 #define ALX_RSS_HASH_TYPE_IPV6_TCP 0x8
342 #define ALX_RSS_HASH_TYPE_ALL (ALX_RSS_HASH_TYPE_IPV4 | \
343 ALX_RSS_HASH_TYPE_IPV4_TCP | \
344 ALX_RSS_HASH_TYPE_IPV6 | \
345 ALX_RSS_HASH_TYPE_IPV6_TCP)
346 #define ALX_DEF_RXBUF_SIZE 1536
347 #define ALX_MAX_JUMBO_PKT_SIZE (9*1024)
348 #define ALX_MAX_TSO_PKT_SIZE (7*1024)
349 #define ALX_MAX_FRAME_SIZE ALX_MAX_JUMBO_PKT_SIZE
350 #define ALX_MIN_FRAME_SIZE 68
351 #define ALX_RAW_MTU(_mtu) (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
353 #define ALX_MAX_RX_QUEUES 8
354 #define ALX_MAX_TX_QUEUES 4
355 #define ALX_MAX_HANDLED_INTRS 5
357 #define ALX_ISR_MISC (ALX_ISR_PCIE_LNKDOWN | \
364 #define ALX_ISR_FATAL (ALX_ISR_PCIE_LNKDOWN | \
365 ALX_ISR_DMAW | ALX_ISR_DMAR)
367 #define ALX_ISR_ALERT (ALX_ISR_RXF_OV | \
371 #define ALX_ISR_ALL_QUEUES (ALX_ISR_TX_Q0 | \
384 /* maximum interrupt vectors for msix */
385 #define ALX_MAX_MSIX_INTRS 16
387 #define ALX_GET_FIELD(_data, _field) \
388 (((_data) >> _field ## _SHIFT) & _field ## _MASK)
390 #define ALX_SET_FIELD(_data, _field, _value) do { \
391 (_data) &= ~(_field ## _MASK << _field ## _SHIFT); \
392 (_data) |= ((_value) & _field ## _MASK) << _field ## _SHIFT;\
396 struct pci_dev *pdev;
399 /* current & permanent mac addr */
400 u8 mac_addr[ETH_ALEN];
401 u8 perm_addr[ETH_ALEN];
407 /* tpd threshold to trig INT */
413 /* SPEED_* + DUPLEX_*, SPEED_UNKNOWN if link is down */
417 /* auto-neg advertisement or force mode config */
421 spinlock_t mdio_lock;
422 struct mdio_if_info mdio;
425 /* PHY link patch flag */
429 static inline int alx_hw_revision(struct alx_hw *hw)
431 return hw->pdev->revision >> ALX_PCI_REVID_SHIFT;
434 static inline bool alx_hw_with_cr(struct alx_hw *hw)
436 return hw->pdev->revision & 1;
439 static inline bool alx_hw_giga(struct alx_hw *hw)
441 return hw->pdev->device & 1;
444 static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val)
446 writeb(val, hw->hw_addr + reg);
449 static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val)
451 writew(val, hw->hw_addr + reg);
454 static inline u16 alx_read_mem16(struct alx_hw *hw, u32 reg)
456 return readw(hw->hw_addr + reg);
459 static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val)
461 writel(val, hw->hw_addr + reg);
464 static inline u32 alx_read_mem32(struct alx_hw *hw, u32 reg)
466 return readl(hw->hw_addr + reg);
469 static inline void alx_post_write(struct alx_hw *hw)
474 int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr);
475 void alx_reset_phy(struct alx_hw *hw);
476 void alx_reset_pcie(struct alx_hw *hw);
477 void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
478 int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
479 void alx_post_phy_link(struct alx_hw *hw);
480 int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
481 int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
482 int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
483 int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
484 int alx_read_phy_link(struct alx_hw *hw);
485 int alx_clear_phy_intr(struct alx_hw *hw);
486 void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
487 void alx_start_mac(struct alx_hw *hw);
488 int alx_reset_mac(struct alx_hw *hw);
489 void alx_set_macaddr(struct alx_hw *hw, const u8 *addr);
490 bool alx_phy_configured(struct alx_hw *hw);
491 void alx_configure_basic(struct alx_hw *hw);
492 void alx_disable_rss(struct alx_hw *hw);
493 bool alx_get_phy_info(struct alx_hw *hw);
495 static inline u32 alx_speed_to_ethadv(int speed, u8 duplex)
497 if (speed == SPEED_1000 && duplex == DUPLEX_FULL)
498 return ADVERTISED_1000baseT_Full;
499 if (speed == SPEED_100 && duplex == DUPLEX_FULL)
500 return ADVERTISED_100baseT_Full;
501 if (speed == SPEED_100 && duplex== DUPLEX_HALF)
502 return ADVERTISED_100baseT_Half;
503 if (speed == SPEED_10 && duplex == DUPLEX_FULL)
504 return ADVERTISED_10baseT_Full;
505 if (speed == SPEED_10 && duplex == DUPLEX_HALF)
506 return ADVERTISED_10baseT_Half;