1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
3 Written 1998-2000 by Donald Becker.
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
16 The information below comes from Donald Becker's original driver:
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
29 #define DRV_NAME "starfire"
30 #define DRV_VERSION "2.1"
31 #define DRV_RELDATE "July 6, 2008"
33 #include <linux/interrupt.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/crc32.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/if_vlan.h>
46 #include <linux/firmware.h>
47 #include <asm/processor.h> /* Processor type for cache alignment. */
48 #include <asm/uaccess.h>
52 * The current frame processor firmware fails to checksum a fragment
53 * of length 1. If and when this is fixed, the #define below can be removed.
55 #define HAS_BROKEN_FIRMWARE
58 * If using the broken firmware, data must be padded to the next 32-bit boundary.
60 #ifdef HAS_BROKEN_FIRMWARE
61 #define PADDING_MASK 3
65 * Define this if using the driver with the zero-copy patch
69 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
73 /* The user-configurable values.
74 These may be modified when a driver module is loaded.*/
76 /* Used for tuning interrupt latency vs. overhead. */
77 static int intr_latency;
78 static int small_frames;
80 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
81 static int max_interrupt_work = 20;
83 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
84 The Starfire has a 512 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 512;
86 /* Whether to do TCP/UDP checksums in hardware */
87 static int enable_hw_cksum = 1;
89 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
91 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
92 * Setting to > 1518 effectively disables this feature.
95 * The ia64 doesn't allow for unaligned loads even of integers being
96 * misaligned on a 2 byte boundary. Thus always force copying of
97 * packets as the starfire doesn't allow for misaligned DMAs ;-(
100 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
101 * at least, having unaligned frames leads to a rather serious performance
104 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
105 static int rx_copybreak = PKT_BUF_SZ;
107 static int rx_copybreak /* = 0 */;
110 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
112 #define DMA_BURST_SIZE 64
114 #define DMA_BURST_SIZE 128
117 /* Used to pass the media type, etc.
118 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
119 The media type is usually passed in 'options[]'.
120 These variables are deprecated, use ethtool instead. -Ion
122 #define MAX_UNITS 8 /* More are supported, limit only on options */
123 static int options[MAX_UNITS] = {0, };
124 static int full_duplex[MAX_UNITS] = {0, };
126 /* Operational parameters that are set at compile time. */
128 /* The "native" ring sizes are either 256 or 2048.
129 However in some modes a descriptor may be marked to wrap the ring earlier.
131 #define RX_RING_SIZE 256
132 #define TX_RING_SIZE 32
133 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
134 #define DONE_Q_SIZE 1024
135 /* All queues must be aligned on a 256-byte boundary */
136 #define QUEUE_ALIGN 256
138 #if RX_RING_SIZE > 256
139 #define RX_Q_ENTRIES Rx2048QEntries
141 #define RX_Q_ENTRIES Rx256QEntries
144 /* Operational parameters that usually are not changed. */
145 /* Time in jiffies before concluding the transmitter is hung. */
146 #define TX_TIMEOUT (2 * HZ)
148 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
149 /* 64-bit dma_addr_t */
150 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
151 #define netdrv_addr_t __le64
152 #define cpu_to_dma(x) cpu_to_le64(x)
153 #define dma_to_cpu(x) le64_to_cpu(x)
154 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
155 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
156 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
157 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
158 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
159 #else /* 32-bit dma_addr_t */
160 #define netdrv_addr_t __le32
161 #define cpu_to_dma(x) cpu_to_le32(x)
162 #define dma_to_cpu(x) le32_to_cpu(x)
163 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
164 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
165 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
166 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
167 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
170 #define skb_first_frag_len(skb) skb_headlen(skb)
171 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
174 #define FIRMWARE_RX "adaptec/starfire_rx.bin"
175 #define FIRMWARE_TX "adaptec/starfire_tx.bin"
177 /* These identify the driver base version and may not be removed. */
178 static const char version[] __devinitconst =
179 KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
180 " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
182 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
183 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
184 MODULE_LICENSE("GPL");
185 MODULE_VERSION(DRV_VERSION);
186 MODULE_FIRMWARE(FIRMWARE_RX);
187 MODULE_FIRMWARE(FIRMWARE_TX);
189 module_param(max_interrupt_work, int, 0);
190 module_param(mtu, int, 0);
191 module_param(debug, int, 0);
192 module_param(rx_copybreak, int, 0);
193 module_param(intr_latency, int, 0);
194 module_param(small_frames, int, 0);
195 module_param_array(options, int, NULL, 0);
196 module_param_array(full_duplex, int, NULL, 0);
197 module_param(enable_hw_cksum, int, 0);
198 MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
199 MODULE_PARM_DESC(mtu, "MTU (all boards)");
200 MODULE_PARM_DESC(debug, "Debug level (0-6)");
201 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
202 MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
203 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
204 MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
205 MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
206 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
211 I. Board Compatibility
213 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
215 II. Board-specific settings
217 III. Driver operation
221 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
222 ring sizes are set fixed by the hardware, but may optionally be wrapped
223 earlier by the END bit in the descriptor.
224 This driver uses that hardware queue size for the Rx ring, where a large
225 number of entries has no ill effect beyond increases the potential backlog.
226 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
227 disables the queue layer priority ordering and we have no mechanism to
228 utilize the hardware two-level priority queue. When modifying the
229 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
232 IIIb/c. Transmit/Receive Structure
234 See the Adaptec manual for the many possible structures, and options for
235 each structure. There are far too many to document all of them here.
237 For transmit this driver uses type 0/1 transmit descriptors (depending
238 on the 32/64 bitness of the architecture), and relies on automatic
239 minimum-length padding. It does not use the completion queue
240 consumer index, but instead checks for non-zero status entries.
242 For receive this driver uses type 2/3 receive descriptors. The driver
243 allocates full frame size skbuffs for the Rx ring buffers, so all frames
244 should fit in a single descriptor. The driver does not use the completion
245 queue consumer index, but instead checks for non-zero status entries.
247 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
248 is allocated and the frame is copied to the new skbuff. When the incoming
249 frame is larger, the skbuff is passed directly up the protocol stack.
250 Buffers consumed this way are replaced by newly allocated skbuffs in a later
253 A notable aspect of operation is that unaligned buffers are not permitted by
254 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
255 isn't longword aligned, which may cause problems on some machine
256 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
257 the frame into a new skbuff unconditionally. Copied frames are put into the
258 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
260 IIId. Synchronization
262 The driver runs as two independent, single-threaded flows of control. One
263 is the send-packet routine, which enforces single-threaded use by the
264 dev->tbusy flag. The other thread is the interrupt handler, which is single
265 threaded by the hardware and interrupt handling software.
267 The send packet thread has partial control over the Tx ring and the netif_queue
268 status. If the number of free Tx slots in the ring falls below a certain number
269 (currently hardcoded to 4), it signals the upper layer to stop the queue.
271 The interrupt handler has exclusive control over the Rx ring and records stats
272 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
273 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
274 number of free Tx slow is above the threshold, it signals the upper layer to
281 The Adaptec Starfire manuals, available only from Adaptec.
282 http://www.scyld.com/expert/100mbps.html
283 http://www.scyld.com/expert/NWay.html
287 - StopOnPerr is broken, don't enable
288 - Hardware ethernet padding exposes random data, perform software padding
289 instead (unverified -- works correctly for all the hardware I have)
295 enum chip_capability_flags {CanHaveMII=1, };
301 static DEFINE_PCI_DEVICE_TABLE(starfire_pci_tbl) = {
302 { PCI_VDEVICE(ADAPTEC, 0x6915), CH_6915 },
305 MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
307 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
308 static const struct chip_info {
311 } netdrv_tbl[] __devinitdata = {
312 { "Adaptec Starfire 6915", CanHaveMII },
316 /* Offsets to the device registers.
317 Unlike software-only systems, device drivers interact with complex hardware.
318 It's not useful to define symbolic names for every register bit in the
319 device. The name can only partially document the semantics and make
320 the driver longer and more difficult to read.
321 In general, only the important configuration values or bits changed
322 multiple times should be defined symbolically.
324 enum register_offsets {
325 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
326 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
327 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
328 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
329 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
330 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
331 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
333 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
334 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
335 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
336 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
337 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
338 TxMode=0x55000, VlanType=0x55064,
339 PerfFilterTable=0x56000, HashTable=0x56100,
340 TxGfpMem=0x58000, RxGfpMem=0x5a000,
344 * Bits in the interrupt status/mask registers.
345 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
346 * enables all the interrupt sources that are or'ed into those status bits.
348 enum intr_status_bits {
349 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
350 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
351 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
352 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
353 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
354 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
355 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
356 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
357 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
358 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
359 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
360 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
361 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
362 IntrTxGfp=0x02, IntrPCIPad=0x01,
364 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
365 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
366 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
369 /* Bits in the RxFilterMode register. */
371 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
372 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
373 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
377 /* Bits in the TxMode register */
379 MiiSoftReset=0x8000, MIILoopback=0x4000,
380 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
381 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
384 /* Bits in the TxDescCtrl register. */
386 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
387 TxDescSpace128=0x30, TxDescSpace256=0x40,
388 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
389 TxDescType3=0x03, TxDescType4=0x04,
390 TxNoDMACompletion=0x08,
391 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
392 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
393 TxDMABurstSizeShift=8,
396 /* Bits in the RxDescQCtrl register. */
398 RxBufferLenShift=16, RxMinDescrThreshShift=0,
399 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
400 Rx2048QEntries=0x4000, Rx256QEntries=0,
401 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
402 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
403 RxDescSpace4=0x000, RxDescSpace8=0x100,
404 RxDescSpace16=0x200, RxDescSpace32=0x300,
405 RxDescSpace64=0x400, RxDescSpace128=0x500,
409 /* Bits in the RxDMACtrl register. */
410 enum rx_dmactrl_bits {
411 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
412 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
413 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
414 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
415 RxChecksumRejectTCPOnly=0x01000000,
416 RxCompletionQ2Enable=0x800000,
417 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
418 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
419 RxDMAQ2NonIP=0x400000,
420 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
421 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
425 /* Bits in the RxCompletionAddr register */
427 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
428 RxComplProducerWrEn=0x40,
429 RxComplType0=0x00, RxComplType1=0x10,
430 RxComplType2=0x20, RxComplType3=0x30,
431 RxComplThreshShift=0,
434 /* Bits in the TxCompletionAddr register */
436 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
437 TxComplProducerWrEn=0x40,
438 TxComplIntrStatus=0x20,
439 CommonQueueMode=0x10,
440 TxComplThreshShift=0,
443 /* Bits in the GenCtrl register */
445 RxEnable=0x05, TxEnable=0x0a,
446 RxGFPEnable=0x10, TxGFPEnable=0x20,
449 /* Bits in the IntrTimerCtrl register */
450 enum intr_ctrl_bits {
451 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
452 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
453 IntrLatencyMask=0x1f,
456 /* The Rx and Tx buffer descriptors. */
457 struct starfire_rx_desc {
458 netdrv_addr_t rxaddr;
461 RxDescValid=1, RxDescEndRing=2,
464 /* Completion queue entry. */
465 struct short_rx_done_desc {
466 __le32 status; /* Low 16 bits is length. */
468 struct basic_rx_done_desc {
469 __le32 status; /* Low 16 bits is length. */
473 struct csum_rx_done_desc {
474 __le32 status; /* Low 16 bits is length. */
475 __le16 csum; /* Partial checksum */
478 struct full_rx_done_desc {
479 __le32 status; /* Low 16 bits is length. */
483 __le16 csum; /* partial checksum */
486 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
488 typedef struct full_rx_done_desc rx_done_desc;
489 #define RxComplType RxComplType3
490 #else /* not VLAN_SUPPORT */
491 typedef struct csum_rx_done_desc rx_done_desc;
492 #define RxComplType RxComplType2
493 #endif /* not VLAN_SUPPORT */
496 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
499 /* Type 1 Tx descriptor. */
500 struct starfire_tx_desc_1 {
501 __le32 status; /* Upper bits are status, lower 16 length. */
505 /* Type 2 Tx descriptor. */
506 struct starfire_tx_desc_2 {
507 __le32 status; /* Upper bits are status, lower 16 length. */
513 typedef struct starfire_tx_desc_2 starfire_tx_desc;
514 #define TX_DESC_TYPE TxDescType2
515 #else /* not ADDR_64BITS */
516 typedef struct starfire_tx_desc_1 starfire_tx_desc;
517 #define TX_DESC_TYPE TxDescType1
518 #endif /* not ADDR_64BITS */
519 #define TX_DESC_SPACING TxDescSpaceUnlim
523 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
524 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
526 struct tx_done_desc {
527 __le32 status; /* timestamp, index. */
529 __le32 intrstatus; /* interrupt status */
533 struct rx_ring_info {
537 struct tx_ring_info {
540 unsigned int used_slots;
544 struct netdev_private {
545 /* Descriptor rings first for alignment. */
546 struct starfire_rx_desc *rx_ring;
547 starfire_tx_desc *tx_ring;
548 dma_addr_t rx_ring_dma;
549 dma_addr_t tx_ring_dma;
550 /* The addresses of rx/tx-in-place skbuffs. */
551 struct rx_ring_info rx_info[RX_RING_SIZE];
552 struct tx_ring_info tx_info[TX_RING_SIZE];
553 /* Pointers to completion queues (full pages). */
554 rx_done_desc *rx_done_q;
555 dma_addr_t rx_done_q_dma;
556 unsigned int rx_done;
557 struct tx_done_desc *tx_done_q;
558 dma_addr_t tx_done_q_dma;
559 unsigned int tx_done;
560 struct napi_struct napi;
561 struct net_device *dev;
562 struct pci_dev *pci_dev;
564 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
567 dma_addr_t queue_mem_dma;
568 size_t queue_mem_size;
570 /* Frequently used values: keep some adjacent for cache effect. */
572 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
573 unsigned int cur_tx, dirty_tx, reap_tx;
574 unsigned int rx_buf_sz; /* Based on MTU+slack. */
575 /* These values keep track of the transceiver/media in use. */
576 int speed100; /* Set if speed == 100MBit. */
580 /* MII transceiver section. */
581 struct mii_if_info mii_if; /* MII lib hooks/info */
582 int phy_cnt; /* MII device addresses. */
583 unsigned char phys[PHY_CNT]; /* MII device addresses. */
588 static int mdio_read(struct net_device *dev, int phy_id, int location);
589 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
590 static int netdev_open(struct net_device *dev);
591 static void check_duplex(struct net_device *dev);
592 static void tx_timeout(struct net_device *dev);
593 static void init_ring(struct net_device *dev);
594 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
595 static irqreturn_t intr_handler(int irq, void *dev_instance);
596 static void netdev_error(struct net_device *dev, int intr_status);
597 static int __netdev_rx(struct net_device *dev, int *quota);
598 static int netdev_poll(struct napi_struct *napi, int budget);
599 static void refill_rx_ring(struct net_device *dev);
600 static void netdev_error(struct net_device *dev, int intr_status);
601 static void set_rx_mode(struct net_device *dev);
602 static struct net_device_stats *get_stats(struct net_device *dev);
603 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
604 static int netdev_close(struct net_device *dev);
605 static void netdev_media_change(struct net_device *dev);
606 static const struct ethtool_ops ethtool_ops;
610 static int netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
612 struct netdev_private *np = netdev_priv(dev);
614 spin_lock(&np->lock);
616 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
617 set_bit(vid, np->active_vlans);
619 spin_unlock(&np->lock);
624 static int netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
626 struct netdev_private *np = netdev_priv(dev);
628 spin_lock(&np->lock);
630 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
631 clear_bit(vid, np->active_vlans);
633 spin_unlock(&np->lock);
637 #endif /* VLAN_SUPPORT */
640 static const struct net_device_ops netdev_ops = {
641 .ndo_open = netdev_open,
642 .ndo_stop = netdev_close,
643 .ndo_start_xmit = start_tx,
644 .ndo_tx_timeout = tx_timeout,
645 .ndo_get_stats = get_stats,
646 .ndo_set_rx_mode = set_rx_mode,
647 .ndo_do_ioctl = netdev_ioctl,
648 .ndo_change_mtu = eth_change_mtu,
649 .ndo_set_mac_address = eth_mac_addr,
650 .ndo_validate_addr = eth_validate_addr,
652 .ndo_vlan_rx_add_vid = netdev_vlan_rx_add_vid,
653 .ndo_vlan_rx_kill_vid = netdev_vlan_rx_kill_vid,
657 static int __devinit starfire_init_one(struct pci_dev *pdev,
658 const struct pci_device_id *ent)
660 struct netdev_private *np;
661 int i, irq, option, chip_idx = ent->driver_data;
662 struct net_device *dev;
663 static int card_idx = -1;
666 int drv_flags, io_size;
669 /* when built into the kernel, we only print version if device is found */
671 static int printed_version;
672 if (!printed_version++)
678 if (pci_enable_device (pdev))
681 ioaddr = pci_resource_start(pdev, 0);
682 io_size = pci_resource_len(pdev, 0);
683 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
684 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
688 dev = alloc_etherdev(sizeof(*np));
692 SET_NETDEV_DEV(dev, &pdev->dev);
696 if (pci_request_regions (pdev, DRV_NAME)) {
697 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
698 goto err_out_free_netdev;
701 base = ioremap(ioaddr, io_size);
703 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
704 card_idx, io_size, ioaddr);
705 goto err_out_free_res;
708 pci_set_master(pdev);
710 /* enable MWI -- it vastly improves Rx performance on sparc64 */
711 pci_try_set_mwi(pdev);
714 /* Starfire can do TCP/UDP checksumming */
716 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
717 #endif /* ZEROCOPY */
720 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
721 #endif /* VLAN_RX_KILL_VID */
723 dev->features |= NETIF_F_HIGHDMA;
724 #endif /* ADDR_64BITS */
726 /* Serial EEPROM reads are hidden by the hardware. */
727 for (i = 0; i < 6; i++)
728 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
730 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
732 for (i = 0; i < 0x20; i++)
734 (unsigned int)readb(base + EEPROMCtrl + i),
735 i % 16 != 15 ? " " : "\n");
738 /* Issue soft reset */
739 writel(MiiSoftReset, base + TxMode);
741 writel(0, base + TxMode);
743 /* Reset the chip to erase previous misconfiguration. */
744 writel(1, base + PCIDeviceConfig);
746 while (--boguscnt > 0) {
748 if ((readl(base + PCIDeviceConfig) & 1) == 0)
752 printk("%s: chipset reset never completed!\n", dev->name);
753 /* wait a little longer */
756 dev->base_addr = (unsigned long)base;
759 np = netdev_priv(dev);
762 spin_lock_init(&np->lock);
763 pci_set_drvdata(pdev, dev);
767 np->mii_if.dev = dev;
768 np->mii_if.mdio_read = mdio_read;
769 np->mii_if.mdio_write = mdio_write;
770 np->mii_if.phy_id_mask = 0x1f;
771 np->mii_if.reg_num_mask = 0x1f;
773 drv_flags = netdrv_tbl[chip_idx].drv_flags;
775 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
777 option = dev->mem_start;
779 /* The lower four bits are the media type. */
781 np->mii_if.full_duplex = 1;
783 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
784 np->mii_if.full_duplex = 1;
786 if (np->mii_if.full_duplex)
787 np->mii_if.force_media = 1;
789 np->mii_if.force_media = 0;
792 /* timer resolution is 128 * 0.8us */
793 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
794 Timer10X | EnableIntrMasking;
796 if (small_frames > 0) {
797 np->intr_timer_ctrl |= SmallFrameBypass;
798 switch (small_frames) {
800 np->intr_timer_ctrl |= SmallFrame64;
803 np->intr_timer_ctrl |= SmallFrame128;
806 np->intr_timer_ctrl |= SmallFrame256;
809 np->intr_timer_ctrl |= SmallFrame512;
810 if (small_frames > 512)
811 printk("Adjusting small_frames down to 512\n");
816 dev->netdev_ops = &netdev_ops;
817 dev->watchdog_timeo = TX_TIMEOUT;
818 SET_ETHTOOL_OPS(dev, ðtool_ops);
820 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
825 if (register_netdev(dev))
826 goto err_out_cleardev;
828 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
829 dev->name, netdrv_tbl[chip_idx].name, base,
832 if (drv_flags & CanHaveMII) {
833 int phy, phy_idx = 0;
835 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
836 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
839 while (--boguscnt > 0)
840 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
843 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
846 mii_status = mdio_read(dev, phy, MII_BMSR);
847 if (mii_status != 0) {
848 np->phys[phy_idx++] = phy;
849 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
850 printk(KERN_INFO "%s: MII PHY found at address %d, status "
851 "%#4.4x advertising %#4.4x.\n",
852 dev->name, phy, mii_status, np->mii_if.advertising);
853 /* there can be only one PHY on-board */
857 np->phy_cnt = phy_idx;
859 np->mii_if.phy_id = np->phys[0];
861 memset(&np->mii_if, 0, sizeof(np->mii_if));
864 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
865 dev->name, enable_hw_cksum ? "enabled" : "disabled");
869 pci_set_drvdata(pdev, NULL);
872 pci_release_regions (pdev);
879 /* Read the MII Management Data I/O (MDIO) interfaces. */
880 static int mdio_read(struct net_device *dev, int phy_id, int location)
882 struct netdev_private *np = netdev_priv(dev);
883 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
884 int result, boguscnt=1000;
885 /* ??? Should we add a busy-wait here? */
887 result = readl(mdio_addr);
888 } while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
891 if ((result & 0xffff) == 0xffff)
893 return result & 0xffff;
897 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
899 struct netdev_private *np = netdev_priv(dev);
900 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
901 writel(value, mdio_addr);
902 /* The busy-wait will occur before a read. */
906 static int netdev_open(struct net_device *dev)
908 const struct firmware *fw_rx, *fw_tx;
909 const __be32 *fw_rx_data, *fw_tx_data;
910 struct netdev_private *np = netdev_priv(dev);
911 void __iomem *ioaddr = np->base;
913 size_t tx_size, rx_size;
914 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
916 /* Do we ever need to reset the chip??? */
918 retval = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
922 /* Disable the Rx and Tx, and reset the chip. */
923 writel(0, ioaddr + GenCtrl);
924 writel(1, ioaddr + PCIDeviceConfig);
926 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
927 dev->name, dev->irq);
929 /* Allocate the various queues. */
930 if (!np->queue_mem) {
931 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
932 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
933 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
934 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
935 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
936 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
937 if (np->queue_mem == NULL) {
938 free_irq(dev->irq, dev);
942 np->tx_done_q = np->queue_mem;
943 np->tx_done_q_dma = np->queue_mem_dma;
944 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
945 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
946 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
947 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
948 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
949 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
952 /* Start with no carrier, it gets adjusted later */
953 netif_carrier_off(dev);
955 /* Set the size of the Rx buffers. */
956 writel((np->rx_buf_sz << RxBufferLenShift) |
957 (0 << RxMinDescrThreshShift) |
958 RxPrefetchMode | RxVariableQ |
960 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
962 ioaddr + RxDescQCtrl);
964 /* Set up the Rx DMA controller. */
965 writel(RxChecksumIgnore |
966 (0 << RxEarlyIntThreshShift) |
967 (6 << RxHighPrioThreshShift) |
968 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
971 /* Set Tx descriptor */
972 writel((2 << TxHiPriFIFOThreshShift) |
973 (0 << TxPadLenShift) |
974 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
975 TX_DESC_Q_ADDR_SIZE |
976 TX_DESC_SPACING | TX_DESC_TYPE,
977 ioaddr + TxDescCtrl);
979 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
980 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
981 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
982 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
983 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
985 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
986 writel(np->rx_done_q_dma |
988 (0 << RxComplThreshShift),
989 ioaddr + RxCompletionAddr);
992 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
994 /* Fill both the Tx SA register and the Rx perfect filter. */
995 for (i = 0; i < 6; i++)
996 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
997 /* The first entry is special because it bypasses the VLAN filter.
999 writew(0, ioaddr + PerfFilterTable);
1000 writew(0, ioaddr + PerfFilterTable + 4);
1001 writew(0, ioaddr + PerfFilterTable + 8);
1002 for (i = 1; i < 16; i++) {
1003 __be16 *eaddrs = (__be16 *)dev->dev_addr;
1004 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
1005 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1006 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1007 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
1010 /* Initialize other registers. */
1011 /* Configure the PCI bus bursts and FIFO thresholds. */
1012 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
1013 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1015 writel(np->tx_mode, ioaddr + TxMode);
1016 np->tx_threshold = 4;
1017 writel(np->tx_threshold, ioaddr + TxThreshold);
1019 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1021 napi_enable(&np->napi);
1023 netif_start_queue(dev);
1026 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1029 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1032 /* Enable GPIO interrupts on link change */
1033 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1035 /* Set the interrupt mask */
1036 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1037 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1038 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1039 ioaddr + IntrEnable);
1040 /* Enable PCI interrupts. */
1041 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1042 ioaddr + PCIDeviceConfig);
1045 /* Set VLAN type to 802.1q */
1046 writel(ETH_P_8021Q, ioaddr + VlanType);
1047 #endif /* VLAN_SUPPORT */
1049 retval = request_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev);
1051 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1055 if (fw_rx->size % 4) {
1056 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1057 fw_rx->size, FIRMWARE_RX);
1061 retval = request_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev);
1063 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1067 if (fw_tx->size % 4) {
1068 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1069 fw_tx->size, FIRMWARE_TX);
1073 fw_rx_data = (const __be32 *)&fw_rx->data[0];
1074 fw_tx_data = (const __be32 *)&fw_tx->data[0];
1075 rx_size = fw_rx->size / 4;
1076 tx_size = fw_tx->size / 4;
1078 /* Load Rx/Tx firmware into the frame processors */
1079 for (i = 0; i < rx_size; i++)
1080 writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4);
1081 for (i = 0; i < tx_size; i++)
1082 writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4);
1083 if (enable_hw_cksum)
1084 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1085 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1087 /* Enable the Rx and Tx units only. */
1088 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1091 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1095 release_firmware(fw_tx);
1097 release_firmware(fw_rx);
1105 static void check_duplex(struct net_device *dev)
1107 struct netdev_private *np = netdev_priv(dev);
1109 int silly_count = 1000;
1111 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1112 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1114 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1117 printk("%s: MII reset failed!\n", dev->name);
1121 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1123 if (!np->mii_if.force_media) {
1124 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1126 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1128 reg0 |= BMCR_SPEED100;
1129 if (np->mii_if.full_duplex)
1130 reg0 |= BMCR_FULLDPLX;
1131 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1133 np->speed100 ? "100" : "10",
1134 np->mii_if.full_duplex ? "full" : "half");
1136 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1140 static void tx_timeout(struct net_device *dev)
1142 struct netdev_private *np = netdev_priv(dev);
1143 void __iomem *ioaddr = np->base;
1146 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1147 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1149 /* Perhaps we should reinitialize the hardware here. */
1152 * Stop and restart the interface.
1153 * Cheat and increase the debug level temporarily.
1161 /* Trigger an immediate transmit demand. */
1163 dev->trans_start = jiffies; /* prevent tx timeout */
1164 dev->stats.tx_errors++;
1165 netif_wake_queue(dev);
1169 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1170 static void init_ring(struct net_device *dev)
1172 struct netdev_private *np = netdev_priv(dev);
1175 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1176 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1178 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1180 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1181 for (i = 0; i < RX_RING_SIZE; i++) {
1182 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1183 np->rx_info[i].skb = skb;
1186 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1187 skb->dev = dev; /* Mark as being used by this device. */
1188 /* Grrr, we cannot offset to correctly align the IP header. */
1189 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1191 writew(i - 1, np->base + RxDescQIdx);
1192 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1194 /* Clear the remainder of the Rx buffer ring. */
1195 for ( ; i < RX_RING_SIZE; i++) {
1196 np->rx_ring[i].rxaddr = 0;
1197 np->rx_info[i].skb = NULL;
1198 np->rx_info[i].mapping = 0;
1200 /* Mark the last entry as wrapping the ring. */
1201 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1203 /* Clear the completion rings. */
1204 for (i = 0; i < DONE_Q_SIZE; i++) {
1205 np->rx_done_q[i].status = 0;
1206 np->tx_done_q[i].status = 0;
1209 for (i = 0; i < TX_RING_SIZE; i++)
1210 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1214 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1216 struct netdev_private *np = netdev_priv(dev);
1222 * be cautious here, wrapping the queue has weird semantics
1223 * and we may not have enough slots even when it seems we do.
1225 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1226 netif_stop_queue(dev);
1227 return NETDEV_TX_BUSY;
1230 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1231 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1232 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1233 return NETDEV_TX_OK;
1235 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1237 entry = np->cur_tx % TX_RING_SIZE;
1238 for (i = 0; i < skb_num_frags(skb); i++) {
1243 np->tx_info[entry].skb = skb;
1245 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1246 status |= TxRingWrap;
1250 status |= TxDescIntr;
1253 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1255 dev->stats.tx_compressed++;
1257 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1259 np->tx_info[entry].mapping =
1260 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1262 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1263 status |= skb_frag_size(this_frag);
1264 np->tx_info[entry].mapping =
1265 pci_map_single(np->pci_dev,
1266 skb_frag_address(this_frag),
1267 skb_frag_size(this_frag),
1271 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1272 np->tx_ring[entry].status = cpu_to_le32(status);
1274 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1275 dev->name, np->cur_tx, np->dirty_tx,
1278 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1279 np->cur_tx += np->tx_info[entry].used_slots;
1282 np->tx_info[entry].used_slots = 1;
1283 np->cur_tx += np->tx_info[entry].used_slots;
1286 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1287 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1291 /* Non-x86: explicitly flush descriptor cache lines here. */
1292 /* Ensure all descriptors are written back before the transmit is
1296 /* Update the producer index. */
1297 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1299 /* 4 is arbitrary, but should be ok */
1300 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1301 netif_stop_queue(dev);
1303 return NETDEV_TX_OK;
1307 /* The interrupt handler does all of the Rx thread work and cleans up
1308 after the Tx thread. */
1309 static irqreturn_t intr_handler(int irq, void *dev_instance)
1311 struct net_device *dev = dev_instance;
1312 struct netdev_private *np = netdev_priv(dev);
1313 void __iomem *ioaddr = np->base;
1314 int boguscnt = max_interrupt_work;
1320 u32 intr_status = readl(ioaddr + IntrClear);
1323 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1324 dev->name, intr_status);
1326 if (intr_status == 0 || intr_status == (u32) -1)
1331 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1334 if (likely(napi_schedule_prep(&np->napi))) {
1335 __napi_schedule(&np->napi);
1336 enable = readl(ioaddr + IntrEnable);
1337 enable &= ~(IntrRxDone | IntrRxEmpty);
1338 writel(enable, ioaddr + IntrEnable);
1339 /* flush PCI posting buffers */
1340 readl(ioaddr + IntrEnable);
1342 /* Paranoia check */
1343 enable = readl(ioaddr + IntrEnable);
1344 if (enable & (IntrRxDone | IntrRxEmpty)) {
1346 "%s: interrupt while in poll!\n",
1348 enable &= ~(IntrRxDone | IntrRxEmpty);
1349 writel(enable, ioaddr + IntrEnable);
1354 /* Scavenge the skbuff list based on the Tx-done queue.
1355 There are redundant checks here that may be cleaned up
1356 after the driver has proven to be reliable. */
1357 consumer = readl(ioaddr + TxConsumerIdx);
1359 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1360 dev->name, consumer);
1362 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1364 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1365 dev->name, np->dirty_tx, np->tx_done, tx_status);
1366 if ((tx_status & 0xe0000000) == 0xa0000000) {
1367 dev->stats.tx_packets++;
1368 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1369 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1370 struct sk_buff *skb = np->tx_info[entry].skb;
1371 np->tx_info[entry].skb = NULL;
1372 pci_unmap_single(np->pci_dev,
1373 np->tx_info[entry].mapping,
1374 skb_first_frag_len(skb),
1376 np->tx_info[entry].mapping = 0;
1377 np->dirty_tx += np->tx_info[entry].used_slots;
1378 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1381 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1382 pci_unmap_single(np->pci_dev,
1383 np->tx_info[entry].mapping,
1384 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1391 dev_kfree_skb_irq(skb);
1393 np->tx_done_q[np->tx_done].status = 0;
1394 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1396 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1398 if (netif_queue_stopped(dev) &&
1399 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1400 /* The ring is no longer full, wake the queue. */
1401 netif_wake_queue(dev);
1404 /* Stats overflow */
1405 if (intr_status & IntrStatsMax)
1408 /* Media change interrupt. */
1409 if (intr_status & IntrLinkChange)
1410 netdev_media_change(dev);
1412 /* Abnormal error summary/uncommon events handlers. */
1413 if (intr_status & IntrAbnormalSummary)
1414 netdev_error(dev, intr_status);
1416 if (--boguscnt < 0) {
1418 printk(KERN_WARNING "%s: Too much work at interrupt, "
1420 dev->name, intr_status);
1426 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1427 dev->name, (int) readl(ioaddr + IntrStatus));
1428 return IRQ_RETVAL(handled);
1433 * This routine is logically part of the interrupt/poll handler, but separated
1434 * for clarity and better register allocation.
1436 static int __netdev_rx(struct net_device *dev, int *quota)
1438 struct netdev_private *np = netdev_priv(dev);
1442 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1443 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1444 struct sk_buff *skb;
1447 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1450 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1451 if (!(desc_status & RxOK)) {
1452 /* There was an error. */
1454 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1455 dev->stats.rx_errors++;
1456 if (desc_status & RxFIFOErr)
1457 dev->stats.rx_fifo_errors++;
1461 if (*quota <= 0) { /* out of rx quota */
1467 pkt_len = desc_status; /* Implicitly Truncate */
1468 entry = (desc_status >> 16) & 0x7ff;
1471 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1472 /* Check if the packet is long enough to accept without copying
1473 to a minimally-sized skbuff. */
1474 if (pkt_len < rx_copybreak &&
1475 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1476 skb_reserve(skb, 2); /* 16 byte align the IP header */
1477 pci_dma_sync_single_for_cpu(np->pci_dev,
1478 np->rx_info[entry].mapping,
1479 pkt_len, PCI_DMA_FROMDEVICE);
1480 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1481 pci_dma_sync_single_for_device(np->pci_dev,
1482 np->rx_info[entry].mapping,
1483 pkt_len, PCI_DMA_FROMDEVICE);
1484 skb_put(skb, pkt_len);
1486 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1487 skb = np->rx_info[entry].skb;
1488 skb_put(skb, pkt_len);
1489 np->rx_info[entry].skb = NULL;
1490 np->rx_info[entry].mapping = 0;
1492 #ifndef final_version /* Remove after testing. */
1493 /* You will want this info for the initial debug. */
1495 printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n",
1496 skb->data, skb->data + 6,
1497 skb->data[12], skb->data[13]);
1501 skb->protocol = eth_type_trans(skb, dev);
1504 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1506 if (le16_to_cpu(desc->status2) & 0x0100) {
1507 skb->ip_summed = CHECKSUM_UNNECESSARY;
1508 dev->stats.rx_compressed++;
1511 * This feature doesn't seem to be working, at least
1512 * with the two firmware versions I have. If the GFP sees
1513 * an IP fragment, it either ignores it completely, or reports
1514 * "bad checksum" on it.
1516 * Maybe I missed something -- corrections are welcome.
1517 * Until then, the printk stays. :-) -Ion
1519 else if (le16_to_cpu(desc->status2) & 0x0040) {
1520 skb->ip_summed = CHECKSUM_COMPLETE;
1521 skb->csum = le16_to_cpu(desc->csum);
1522 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1525 if (le16_to_cpu(desc->status2) & 0x0200) {
1526 u16 vlid = le16_to_cpu(desc->vlanid);
1529 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1532 __vlan_hwaccel_put_tag(skb, vlid);
1534 #endif /* VLAN_SUPPORT */
1535 netif_receive_skb(skb);
1536 dev->stats.rx_packets++;
1541 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1544 if (*quota == 0) { /* out of rx quota */
1548 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1551 refill_rx_ring(dev);
1553 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1554 retcode, np->rx_done, desc_status);
1558 static int netdev_poll(struct napi_struct *napi, int budget)
1560 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1561 struct net_device *dev = np->dev;
1563 void __iomem *ioaddr = np->base;
1567 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1569 if (__netdev_rx(dev, "a))
1572 intr_status = readl(ioaddr + IntrStatus);
1573 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1575 napi_complete(napi);
1576 intr_status = readl(ioaddr + IntrEnable);
1577 intr_status |= IntrRxDone | IntrRxEmpty;
1578 writel(intr_status, ioaddr + IntrEnable);
1582 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1585 /* Restart Rx engine if stopped. */
1586 return budget - quota;
1589 static void refill_rx_ring(struct net_device *dev)
1591 struct netdev_private *np = netdev_priv(dev);
1592 struct sk_buff *skb;
1595 /* Refill the Rx ring buffers. */
1596 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1597 entry = np->dirty_rx % RX_RING_SIZE;
1598 if (np->rx_info[entry].skb == NULL) {
1599 skb = dev_alloc_skb(np->rx_buf_sz);
1600 np->rx_info[entry].skb = skb;
1602 break; /* Better luck next round. */
1603 np->rx_info[entry].mapping =
1604 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1605 skb->dev = dev; /* Mark as being used by this device. */
1606 np->rx_ring[entry].rxaddr =
1607 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1609 if (entry == RX_RING_SIZE - 1)
1610 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1613 writew(entry, np->base + RxDescQIdx);
1617 static void netdev_media_change(struct net_device *dev)
1619 struct netdev_private *np = netdev_priv(dev);
1620 void __iomem *ioaddr = np->base;
1621 u16 reg0, reg1, reg4, reg5;
1623 u32 new_intr_timer_ctrl;
1625 /* reset status first */
1626 mdio_read(dev, np->phys[0], MII_BMCR);
1627 mdio_read(dev, np->phys[0], MII_BMSR);
1629 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1630 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1632 if (reg1 & BMSR_LSTATUS) {
1634 if (reg0 & BMCR_ANENABLE) {
1635 /* autonegotiation is enabled */
1636 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1637 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1638 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1640 np->mii_if.full_duplex = 1;
1641 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1643 np->mii_if.full_duplex = 0;
1644 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1646 np->mii_if.full_duplex = 1;
1649 np->mii_if.full_duplex = 0;
1652 /* autonegotiation is disabled */
1653 if (reg0 & BMCR_SPEED100)
1657 if (reg0 & BMCR_FULLDPLX)
1658 np->mii_if.full_duplex = 1;
1660 np->mii_if.full_duplex = 0;
1662 netif_carrier_on(dev);
1663 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1665 np->speed100 ? "100" : "10",
1666 np->mii_if.full_duplex ? "full" : "half");
1668 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1669 if (np->mii_if.full_duplex)
1670 new_tx_mode |= FullDuplex;
1671 if (np->tx_mode != new_tx_mode) {
1672 np->tx_mode = new_tx_mode;
1673 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1675 writel(np->tx_mode, ioaddr + TxMode);
1678 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1680 new_intr_timer_ctrl |= Timer10X;
1681 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1682 np->intr_timer_ctrl = new_intr_timer_ctrl;
1683 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1686 netif_carrier_off(dev);
1687 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1692 static void netdev_error(struct net_device *dev, int intr_status)
1694 struct netdev_private *np = netdev_priv(dev);
1696 /* Came close to underrunning the Tx FIFO, increase threshold. */
1697 if (intr_status & IntrTxDataLow) {
1698 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1699 writel(++np->tx_threshold, np->base + TxThreshold);
1700 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1701 dev->name, np->tx_threshold * 16);
1703 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1705 if (intr_status & IntrRxGFPDead) {
1706 dev->stats.rx_fifo_errors++;
1707 dev->stats.rx_errors++;
1709 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1710 dev->stats.tx_fifo_errors++;
1711 dev->stats.tx_errors++;
1713 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1714 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1715 dev->name, intr_status);
1719 static struct net_device_stats *get_stats(struct net_device *dev)
1721 struct netdev_private *np = netdev_priv(dev);
1722 void __iomem *ioaddr = np->base;
1724 /* This adapter architecture needs no SMP locks. */
1725 dev->stats.tx_bytes = readl(ioaddr + 0x57010);
1726 dev->stats.rx_bytes = readl(ioaddr + 0x57044);
1727 dev->stats.tx_packets = readl(ioaddr + 0x57000);
1728 dev->stats.tx_aborted_errors =
1729 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1730 dev->stats.tx_window_errors = readl(ioaddr + 0x57018);
1731 dev->stats.collisions =
1732 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1734 /* The chip only need report frame silently dropped. */
1735 dev->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1736 writew(0, ioaddr + RxDMAStatus);
1737 dev->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1738 dev->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1739 dev->stats.rx_length_errors = readl(ioaddr + 0x57058);
1740 dev->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1746 static u32 set_vlan_mode(struct netdev_private *np)
1750 void __iomem *filter_addr = np->base + HashTable + 8;
1753 for_each_set_bit(vid, np->active_vlans, VLAN_N_VID) {
1754 if (vlan_count == 32)
1756 writew(vid, filter_addr);
1760 if (vlan_count == 32) {
1761 ret |= PerfectFilterVlan;
1762 while (vlan_count < 32) {
1763 writew(0, filter_addr);
1770 #endif /* VLAN_SUPPORT */
1772 static void set_rx_mode(struct net_device *dev)
1774 struct netdev_private *np = netdev_priv(dev);
1775 void __iomem *ioaddr = np->base;
1776 u32 rx_mode = MinVLANPrio;
1777 struct netdev_hw_addr *ha;
1781 rx_mode |= set_vlan_mode(np);
1782 #endif /* VLAN_SUPPORT */
1784 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1785 rx_mode |= AcceptAll;
1786 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1787 (dev->flags & IFF_ALLMULTI)) {
1788 /* Too many to match, or accept all multicasts. */
1789 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1790 } else if (netdev_mc_count(dev) <= 14) {
1791 /* Use the 16 element perfect filter, skip first two entries. */
1792 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1794 netdev_for_each_mc_addr(ha, dev) {
1795 eaddrs = (__be16 *) ha->addr;
1796 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1797 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1798 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1800 eaddrs = (__be16 *)dev->dev_addr;
1801 i = netdev_mc_count(dev) + 2;
1803 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1804 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1805 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1807 rx_mode |= AcceptBroadcast|PerfectFilter;
1809 /* Must use a multicast hash table. */
1810 void __iomem *filter_addr;
1812 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1814 memset(mc_filter, 0, sizeof(mc_filter));
1815 netdev_for_each_mc_addr(ha, dev) {
1816 /* The chip uses the upper 9 CRC bits
1817 as index into the hash table */
1818 int bit_nr = ether_crc_le(ETH_ALEN, ha->addr) >> 23;
1819 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1821 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1823 /* Clear the perfect filter list, skip first two entries. */
1824 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1825 eaddrs = (__be16 *)dev->dev_addr;
1826 for (i = 2; i < 16; i++) {
1827 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1828 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1829 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1831 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1832 writew(mc_filter[i], filter_addr);
1833 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1835 writel(rx_mode, ioaddr + RxFilterMode);
1838 static int check_if_running(struct net_device *dev)
1840 if (!netif_running(dev))
1845 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1847 struct netdev_private *np = netdev_priv(dev);
1848 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1849 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1850 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
1853 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1855 struct netdev_private *np = netdev_priv(dev);
1856 spin_lock_irq(&np->lock);
1857 mii_ethtool_gset(&np->mii_if, ecmd);
1858 spin_unlock_irq(&np->lock);
1862 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1864 struct netdev_private *np = netdev_priv(dev);
1866 spin_lock_irq(&np->lock);
1867 res = mii_ethtool_sset(&np->mii_if, ecmd);
1868 spin_unlock_irq(&np->lock);
1873 static int nway_reset(struct net_device *dev)
1875 struct netdev_private *np = netdev_priv(dev);
1876 return mii_nway_restart(&np->mii_if);
1879 static u32 get_link(struct net_device *dev)
1881 struct netdev_private *np = netdev_priv(dev);
1882 return mii_link_ok(&np->mii_if);
1885 static u32 get_msglevel(struct net_device *dev)
1890 static void set_msglevel(struct net_device *dev, u32 val)
1895 static const struct ethtool_ops ethtool_ops = {
1896 .begin = check_if_running,
1897 .get_drvinfo = get_drvinfo,
1898 .get_settings = get_settings,
1899 .set_settings = set_settings,
1900 .nway_reset = nway_reset,
1901 .get_link = get_link,
1902 .get_msglevel = get_msglevel,
1903 .set_msglevel = set_msglevel,
1906 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1908 struct netdev_private *np = netdev_priv(dev);
1909 struct mii_ioctl_data *data = if_mii(rq);
1912 if (!netif_running(dev))
1915 spin_lock_irq(&np->lock);
1916 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1917 spin_unlock_irq(&np->lock);
1919 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1925 static int netdev_close(struct net_device *dev)
1927 struct netdev_private *np = netdev_priv(dev);
1928 void __iomem *ioaddr = np->base;
1931 netif_stop_queue(dev);
1933 napi_disable(&np->napi);
1936 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1937 dev->name, (int) readl(ioaddr + IntrStatus));
1938 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1939 dev->name, np->cur_tx, np->dirty_tx,
1940 np->cur_rx, np->dirty_rx);
1943 /* Disable interrupts by clearing the interrupt mask. */
1944 writel(0, ioaddr + IntrEnable);
1946 /* Stop the chip's Tx and Rx processes. */
1947 writel(0, ioaddr + GenCtrl);
1948 readl(ioaddr + GenCtrl);
1951 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1952 (long long) np->tx_ring_dma);
1953 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1954 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1955 i, le32_to_cpu(np->tx_ring[i].status),
1956 (long long) dma_to_cpu(np->tx_ring[i].addr),
1957 le32_to_cpu(np->tx_done_q[i].status));
1958 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1959 (long long) np->rx_ring_dma, np->rx_done_q);
1961 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1962 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1963 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1967 free_irq(dev->irq, dev);
1969 /* Free all the skbuffs in the Rx queue. */
1970 for (i = 0; i < RX_RING_SIZE; i++) {
1971 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1972 if (np->rx_info[i].skb != NULL) {
1973 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1974 dev_kfree_skb(np->rx_info[i].skb);
1976 np->rx_info[i].skb = NULL;
1977 np->rx_info[i].mapping = 0;
1979 for (i = 0; i < TX_RING_SIZE; i++) {
1980 struct sk_buff *skb = np->tx_info[i].skb;
1983 pci_unmap_single(np->pci_dev,
1984 np->tx_info[i].mapping,
1985 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1986 np->tx_info[i].mapping = 0;
1988 np->tx_info[i].skb = NULL;
1995 static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
1997 struct net_device *dev = pci_get_drvdata(pdev);
1999 if (netif_running(dev)) {
2000 netif_device_detach(dev);
2004 pci_save_state(pdev);
2005 pci_set_power_state(pdev, pci_choose_state(pdev,state));
2010 static int starfire_resume(struct pci_dev *pdev)
2012 struct net_device *dev = pci_get_drvdata(pdev);
2014 pci_set_power_state(pdev, PCI_D0);
2015 pci_restore_state(pdev);
2017 if (netif_running(dev)) {
2019 netif_device_attach(dev);
2024 #endif /* CONFIG_PM */
2027 static void __devexit starfire_remove_one (struct pci_dev *pdev)
2029 struct net_device *dev = pci_get_drvdata(pdev);
2030 struct netdev_private *np = netdev_priv(dev);
2034 unregister_netdev(dev);
2037 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
2040 /* XXX: add wakeup code -- requires firmware for MagicPacket */
2041 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
2042 pci_disable_device(pdev);
2045 pci_release_regions(pdev);
2047 pci_set_drvdata(pdev, NULL);
2048 free_netdev(dev); /* Will also free np!! */
2052 static struct pci_driver starfire_driver = {
2054 .probe = starfire_init_one,
2055 .remove = __devexit_p(starfire_remove_one),
2057 .suspend = starfire_suspend,
2058 .resume = starfire_resume,
2059 #endif /* CONFIG_PM */
2060 .id_table = starfire_pci_tbl,
2064 static int __init starfire_init (void)
2066 /* when a module, this is printed whether or not devices are found in probe */
2070 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2073 BUILD_BUG_ON(sizeof(dma_addr_t) != sizeof(netdrv_addr_t));
2075 return pci_register_driver(&starfire_driver);
2079 static void __exit starfire_cleanup (void)
2081 pci_unregister_driver (&starfire_driver);
2085 module_init(starfire_init);
2086 module_exit(starfire_cleanup);