Pileus Git - ~andy/linux/blob - drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  */
  56
  57 #include <linux/netdevice.h>
  58 #include <linux/ethtool.h>
  59 #include <linux/delay.h>
  60 #include <linux/pci.h>
  61
  62 #include "e1000.h"
  63
  64 #define ICH_FLASH_GFPREG                0x0000
  65 #define ICH_FLASH_HSFSTS                0x0004
  66 #define ICH_FLASH_HSFCTL                0x0006
  67 #define ICH_FLASH_FADDR                 0x0008
  68 #define ICH_FLASH_FDATA0                0x0010
  69 #define ICH_FLASH_PR0                   0x0074
  70
  71 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  72 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  73 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  74 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  75 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  76
  77 #define ICH_CYCLE_READ                  0
  78 #define ICH_CYCLE_WRITE                 2
  79 #define ICH_CYCLE_ERASE                 3
  80
  81 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  82 #define FLASH_SECTOR_ADDR_SHIFT         12
  83
  84 #define ICH_FLASH_SEG_SIZE_256          256
  85 #define ICH_FLASH_SEG_SIZE_4K           4096
  86 #define ICH_FLASH_SEG_SIZE_8K           8192
  87 #define ICH_FLASH_SEG_SIZE_64K          65536
  88
  89
  90 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  91
  92 #define E1000_ICH_MNG_IAMT_MODE         0x2
  93
  94 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  95                                  (ID_LED_DEF1_OFF2 <<  8) | \
  96                                  (ID_LED_DEF1_ON2  <<  4) | \
  97                                  (ID_LED_DEF1_DEF2))
  98
  99 #define E1000_ICH_NVM_SIG_WORD          0x13
 100 #define E1000_ICH_NVM_SIG_MASK          0xC000
 101 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 102 #define E1000_ICH_NVM_SIG_VALUE         0x80
 103
 104 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 105
 106 #define E1000_FEXTNVM_SW_CONFIG         1
 107 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 108
 109 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 110
 111 #define E1000_ICH_RAR_ENTRIES           7
 112
 113 #define PHY_PAGE_SHIFT 5
 114 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 115                            ((reg) & MAX_PHY_REG_ADDRESS))
 116 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 117 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 118
 119 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 120 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 121 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 122
 123 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 124
 125 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 126 /* Offset 04h HSFSTS */
 127 union ich8_hws_flash_status {
 128         struct ich8_hsfsts {
 129                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 130                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 131                 u16 dael       :1; /* bit 2 Direct Access error Log */
 132                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 133                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 134                 u16 reserved1  :2; /* bit 13:6 Reserved */
 135                 u16 reserved2  :6; /* bit 13:6 Reserved */
 136                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 137                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 138         } hsf_status;
 139         u16 regval;
 140 };
 141
 142 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 143 /* Offset 06h FLCTL */
 144 union ich8_hws_flash_ctrl {
 145         struct ich8_hsflctl {
 146                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 147                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 148                 u16 reserved   :5;   /* 7:3 Reserved  */
 149                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 150                 u16 flockdn    :6;   /* 15:10 Reserved */
 151         } hsf_ctrl;
 152         u16 regval;
 153 };
 154
 155 /* ICH Flash Region Access Permissions */
 156 union ich8_hws_flash_regacc {
 157         struct ich8_flracc {
 158                 u32 grra      :8; /* 0:7 GbE region Read Access */
 159                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 160                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 161                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 162         } hsf_flregacc;
 163         u16 regval;
 164 };
 165
 166 /* ICH Flash Protected Region */
 167 union ich8_flash_protected_range {
 168         struct ich8_pr {
 169                 u32 base:13;     /* 0:12 Protected Range Base */
 170                 u32 reserved1:2; /* 13:14 Reserved */
 171                 u32 rpe:1;       /* 15 Read Protection Enable */
 172                 u32 limit:13;    /* 16:28 Protected Range Limit */
 173                 u32 reserved2:2; /* 29:30 Reserved */
 174                 u32 wpe:1;       /* 31 Write Protection Enable */
 175         } range;
 176         u32 regval;
 177 };
 178
 179 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 180 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 181 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 182 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 183 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 184 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 185                                                 u32 offset, u8 byte);
 186 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 187                                          u8 *data);
 188 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 189                                          u16 *data);
 190 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 191                                          u8 size, u16 *data);
 192 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 193 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 194 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 195 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 196 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 197 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 198 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 199 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 200 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 201 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 202 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 203
 204 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 205 {
 206         return readw(hw->flash_address + reg);
 207 }
 208
 209 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 210 {
 211         return readl(hw->flash_address + reg);
 212 }
 213
 214 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 215 {
 216         writew(val, hw->flash_address + reg);
 217 }
 218
 219 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 220 {
 221         writel(val, hw->flash_address + reg);
 222 }
 223
 224 #define er16flash(reg)          __er16flash(hw, (reg))
 225 #define er32flash(reg)          __er32flash(hw, (reg))
 226 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 227 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 228
 229 /**
 230  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 231  *  @hw: pointer to the HW structure
 232  *
 233  *  Initialize family-specific PHY parameters and function pointers.
 234  **/
 235 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 236 {
 237         struct e1000_phy_info *phy = &hw->phy;
 238         s32 ret_val = 0;
 239
 240         phy->addr                     = 1;
 241         phy->reset_delay_us           = 100;
 242
 243         phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;
 244         phy->ops.read_phy_reg         = e1000_read_phy_reg_hv;
 245         phy->ops.write_phy_reg        = e1000_write_phy_reg_hv;
 246         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 247
 248         phy->id = e1000_phy_unknown;
 249         e1000e_get_phy_id(hw);
 250         phy->type = e1000e_get_phy_type_from_id(phy->id);
 251
 252         if (phy->type == e1000_phy_82577) {
 253                 phy->ops.check_polarity = e1000_check_polarity_82577;
 254                 phy->ops.force_speed_duplex =
 255                         e1000_phy_force_speed_duplex_82577;
 256                 phy->ops.get_cable_length   = e1000_get_cable_length_82577;
 257                 phy->ops.get_phy_info = e1000_get_phy_info_82577;
 258                 phy->ops.commit_phy = e1000e_phy_sw_reset;
 259         }
 260
 261         return ret_val;
 262 }
 263
 264 /**
 265  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 266  *  @hw: pointer to the HW structure
 267  *
 268  *  Initialize family-specific PHY parameters and function pointers.
 269  **/
 270 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 271 {
 272         struct e1000_phy_info *phy = &hw->phy;
 273         s32 ret_val;
 274         u16 i = 0;
 275
 276         phy->addr                       = 1;
 277         phy->reset_delay_us             = 100;
 278
 279         /*
 280          * We may need to do this twice - once for IGP and if that fails,
 281          * we'll set BM func pointers and try again
 282          */
 283         ret_val = e1000e_determine_phy_address(hw);
 284         if (ret_val) {
 285                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 286                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 287                 ret_val = e1000e_determine_phy_address(hw);
 288                 if (ret_val)
 289                         return ret_val;
 290         }
 291
 292         phy->id = 0;
 293         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 294                (i++ < 100)) {
 295                 msleep(1);
 296                 ret_val = e1000e_get_phy_id(hw);
 297                 if (ret_val)
 298                         return ret_val;
 299         }
 300
 301         /* Verify phy id */
 302         switch (phy->id) {
 303         case IGP03E1000_E_PHY_ID:
 304                 phy->type = e1000_phy_igp_3;
 305                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 306                 break;
 307         case IFE_E_PHY_ID:
 308         case IFE_PLUS_E_PHY_ID:
 309         case IFE_C_E_PHY_ID:
 310                 phy->type = e1000_phy_ife;
 311                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 312                 break;
 313         case BME1000_E_PHY_ID:
 314                 phy->type = e1000_phy_bm;
 315                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 316                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 317                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 318                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 319                 break;
 320         default:
 321                 return -E1000_ERR_PHY;
 322                 break;
 323         }
 324
 325         phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
 326
 327         return 0;
 328 }
 329
 330 /**
 331  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 332  *  @hw: pointer to the HW structure
 333  *
 334  *  Initialize family-specific NVM parameters and function
 335  *  pointers.
 336  **/
 337 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 338 {
 339         struct e1000_nvm_info *nvm = &hw->nvm;
 340         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 341         u32 gfpreg;
 342         u32 sector_base_addr;
 343         u32 sector_end_addr;
 344         u16 i;
 345
 346         /* Can't read flash registers if the register set isn't mapped. */
 347         if (!hw->flash_address) {
 348                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 349                 return -E1000_ERR_CONFIG;
 350         }
 351
 352         nvm->type = e1000_nvm_flash_sw;
 353
 354         gfpreg = er32flash(ICH_FLASH_GFPREG);
 355
 356         /*
 357          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 358          * Add 1 to sector_end_addr since this sector is included in
 359          * the overall size.
 360          */
 361         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 362         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 363
 364         /* flash_base_addr is byte-aligned */
 365         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 366
 367         /*
 368          * find total size of the NVM, then cut in half since the total
 369          * size represents two separate NVM banks.
 370          */
 371         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 372                                 << FLASH_SECTOR_ADDR_SHIFT;
 373         nvm->flash_bank_size /= 2;
 374         /* Adjust to word count */
 375         nvm->flash_bank_size /= sizeof(u16);
 376
 377         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 378
 379         /* Clear shadow ram */
 380         for (i = 0; i < nvm->word_size; i++) {
 381                 dev_spec->shadow_ram[i].modified = 0;
 382                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 383         }
 384
 385         return 0;
 386 }
 387
 388 /**
 389  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 390  *  @hw: pointer to the HW structure
 391  *
 392  *  Initialize family-specific MAC parameters and function
 393  *  pointers.
 394  **/
 395 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 396 {
 397         struct e1000_hw *hw = &adapter->hw;
 398         struct e1000_mac_info *mac = &hw->mac;
 399
 400         /* Set media type function pointer */
 401         hw->phy.media_type = e1000_media_type_copper;
 402
 403         /* Set mta register count */
 404         mac->mta_reg_count = 32;
 405         /* Set rar entry count */
 406         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 407         if (mac->type == e1000_ich8lan)
 408                 mac->rar_entry_count--;
 409         /* Set if manageability features are enabled. */
 410         mac->arc_subsystem_valid = 1;
 411
 412         /* LED operations */
 413         switch (mac->type) {
 414         case e1000_ich8lan:
 415         case e1000_ich9lan:
 416         case e1000_ich10lan:
 417                 /* ID LED init */
 418                 mac->ops.id_led_init = e1000e_id_led_init;
 419                 /* setup LED */
 420                 mac->ops.setup_led = e1000e_setup_led_generic;
 421                 /* cleanup LED */
 422                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 423                 /* turn on/off LED */
 424                 mac->ops.led_on = e1000_led_on_ich8lan;
 425                 mac->ops.led_off = e1000_led_off_ich8lan;
 426                 break;
 427         case e1000_pchlan:
 428                 /* ID LED init */
 429                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 430                 /* setup LED */
 431                 mac->ops.setup_led = e1000_setup_led_pchlan;
 432                 /* cleanup LED */
 433                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 434                 /* turn on/off LED */
 435                 mac->ops.led_on = e1000_led_on_pchlan;
 436                 mac->ops.led_off = e1000_led_off_pchlan;
 437                 break;
 438         default:
 439                 break;
 440         }
 441
 442         /* Enable PCS Lock-loss workaround for ICH8 */
 443         if (mac->type == e1000_ich8lan)
 444                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 445
 446         return 0;
 447 }
 448
 449 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 450 {
 451         struct e1000_hw *hw = &adapter->hw;
 452         s32 rc;
 453
 454         rc = e1000_init_mac_params_ich8lan(adapter);
 455         if (rc)
 456                 return rc;
 457
 458         rc = e1000_init_nvm_params_ich8lan(hw);
 459         if (rc)
 460                 return rc;
 461
 462         if (hw->mac.type == e1000_pchlan)
 463                 rc = e1000_init_phy_params_pchlan(hw);
 464         else
 465                 rc = e1000_init_phy_params_ich8lan(hw);
 466         if (rc)
 467                 return rc;
 468
 469         if (adapter->hw.phy.type == e1000_phy_ife) {
 470                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 471                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 472         }
 473
 474         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 475             (adapter->hw.phy.type == e1000_phy_igp_3))
 476                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 477
 478         return 0;
 479 }
 480
 481 static DEFINE_MUTEX(nvm_mutex);
 482
 483 /**
 484  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 485  *  @hw: pointer to the HW structure
 486  *
 487  *  Acquires the software control flag for performing NVM and PHY
 488  *  operations.  This is a function pointer entry point only called by
 489  *  read/write routines for the PHY and NVM parts.
 490  **/
 491 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 492 {
 493         u32 extcnf_ctrl;
 494         u32 timeout = PHY_CFG_TIMEOUT;
 495
 496         might_sleep();
 497
 498         mutex_lock(&nvm_mutex);
 499
 500         while (timeout) {
 501                 extcnf_ctrl = er32(EXTCNF_CTRL);
 502
 503                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) {
 504                         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 505                         ew32(EXTCNF_CTRL, extcnf_ctrl);
 506
 507                         extcnf_ctrl = er32(EXTCNF_CTRL);
 508                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 509                                 break;
 510                 }
 511                 mdelay(1);
 512                 timeout--;
 513         }
 514
 515         if (!timeout) {
 516                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
 517                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 518                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 519                 mutex_unlock(&nvm_mutex);
 520                 return -E1000_ERR_CONFIG;
 521         }
 522
 523         return 0;
 524 }
 525
 526 /**
 527  *  e1000_release_swflag_ich8lan - Release software control flag
 528  *  @hw: pointer to the HW structure
 529  *
 530  *  Releases the software control flag for performing NVM and PHY operations.
 531  *  This is a function pointer entry point only called by read/write
 532  *  routines for the PHY and NVM parts.
 533  **/
 534 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 535 {
 536         u32 extcnf_ctrl;
 537
 538         extcnf_ctrl = er32(EXTCNF_CTRL);
 539         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 540         ew32(EXTCNF_CTRL, extcnf_ctrl);
 541
 542         mutex_unlock(&nvm_mutex);
 543 }
 544
 545 /**
 546  *  e1000_check_mng_mode_ich8lan - Checks management mode
 547  *  @hw: pointer to the HW structure
 548  *
 549  *  This checks if the adapter has manageability enabled.
 550  *  This is a function pointer entry point only called by read/write
 551  *  routines for the PHY and NVM parts.
 552  **/
 553 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 554 {
 555         u32 fwsm = er32(FWSM);
 556
 557         return (fwsm & E1000_FWSM_MODE_MASK) ==
 558                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 559 }
 560
 561 /**
 562  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 563  *  @hw: pointer to the HW structure
 564  *
 565  *  Checks if firmware is blocking the reset of the PHY.
 566  *  This is a function pointer entry point only called by
 567  *  reset routines.
 568  **/
 569 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 570 {
 571         u32 fwsm;
 572
 573         fwsm = er32(FWSM);
 574
 575         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 576 }
 577
 578 /**
 579  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 580  *  @hw: pointer to the HW structure
 581  *
 582  *  Forces the speed and duplex settings of the PHY.
 583  *  This is a function pointer entry point only called by
 584  *  PHY setup routines.
 585  **/
 586 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 587 {
 588         struct e1000_phy_info *phy = &hw->phy;
 589         s32 ret_val;
 590         u16 data;
 591         bool link;
 592
 593         if (phy->type != e1000_phy_ife) {
 594                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 595                 return ret_val;
 596         }
 597
 598         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 599         if (ret_val)
 600                 return ret_val;
 601
 602         e1000e_phy_force_speed_duplex_setup(hw, &data);
 603
 604         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 605         if (ret_val)
 606                 return ret_val;
 607
 608         /* Disable MDI-X support for 10/100 */
 609         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 610         if (ret_val)
 611                 return ret_val;
 612
 613         data &= ~IFE_PMC_AUTO_MDIX;
 614         data &= ~IFE_PMC_FORCE_MDIX;
 615
 616         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 617         if (ret_val)
 618                 return ret_val;
 619
 620         hw_dbg(hw, "IFE PMC: %X\n", data);
 621
 622         udelay(1);
 623
 624         if (phy->autoneg_wait_to_complete) {
 625                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 626
 627                 ret_val = e1000e_phy_has_link_generic(hw,
 628                                                      PHY_FORCE_LIMIT,
 629                                                      100000,
 630                                                      &link);
 631                 if (ret_val)
 632                         return ret_val;
 633
 634                 if (!link)
 635                         hw_dbg(hw, "Link taking longer than expected.\n");
 636
 637                 /* Try once more */
 638                 ret_val = e1000e_phy_has_link_generic(hw,
 639                                                      PHY_FORCE_LIMIT,
 640                                                      100000,
 641                                                      &link);
 642                 if (ret_val)
 643                         return ret_val;
 644         }
 645
 646         return 0;
 647 }
 648
 649 /**
 650  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
 651  *  done after every PHY reset.
 652  **/
 653 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 654 {
 655         s32 ret_val = 0;
 656
 657         if (hw->mac.type != e1000_pchlan)
 658                 return ret_val;
 659
 660         if (((hw->phy.type == e1000_phy_82577) &&
 661              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
 662             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
 663                 /* Disable generation of early preamble */
 664                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
 665                 if (ret_val)
 666                         return ret_val;
 667
 668                 /* Preamble tuning for SSC */
 669                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
 670                 if (ret_val)
 671                         return ret_val;
 672         }
 673
 674         if (hw->phy.type == e1000_phy_82578) {
 675                 /*
 676                  * Return registers to default by doing a soft reset then
 677                  * writing 0x3140 to the control register.
 678                  */
 679                 if (hw->phy.revision < 2) {
 680                         e1000e_phy_sw_reset(hw);
 681                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
 682                 }
 683         }
 684
 685         /* Select page 0 */
 686         ret_val = hw->phy.ops.acquire_phy(hw);
 687         if (ret_val)
 688                 return ret_val;
 689         hw->phy.addr = 1;
 690         e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
 691         hw->phy.ops.release_phy(hw);
 692
 693         return ret_val;
 694 }
 695
 696 /**
 697  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
 698  *  @hw: pointer to the HW structure
 699  *
 700  *  Check the appropriate indication the MAC has finished configuring the
 701  *  PHY after a software reset.
 702  **/
 703 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
 704 {
 705         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 706
 707         /* Wait for basic configuration completes before proceeding */
 708         do {
 709                 data = er32(STATUS);
 710                 data &= E1000_STATUS_LAN_INIT_DONE;
 711                 udelay(100);
 712         } while ((!data) && --loop);
 713
 714         /*
 715          * If basic configuration is incomplete before the above loop
 716          * count reaches 0, loading the configuration from NVM will
 717          * leave the PHY in a bad state possibly resulting in no link.
 718          */
 719         if (loop == 0)
 720                 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
 721
 722         /* Clear the Init Done bit for the next init event */
 723         data = er32(STATUS);
 724         data &= ~E1000_STATUS_LAN_INIT_DONE;
 725         ew32(STATUS, data);
 726 }
 727
 728 /**
 729  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 730  *  @hw: pointer to the HW structure
 731  *
 732  *  Resets the PHY
 733  *  This is a function pointer entry point called by drivers
 734  *  or other shared routines.
 735  **/
 736 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 737 {
 738         struct e1000_phy_info *phy = &hw->phy;
 739         u32 i;
 740         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
 741         s32 ret_val;
 742         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 743
 744         ret_val = e1000e_phy_hw_reset_generic(hw);
 745         if (ret_val)
 746                 return ret_val;
 747
 748         /* Allow time for h/w to get to a quiescent state after reset */
 749         mdelay(10);
 750
 751         if (hw->mac.type == e1000_pchlan) {
 752                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
 753                 if (ret_val)
 754                         return ret_val;
 755         }
 756
 757         /*
 758          * Initialize the PHY from the NVM on ICH platforms.  This
 759          * is needed due to an issue where the NVM configuration is
 760          * not properly autoloaded after power transitions.
 761          * Therefore, after each PHY reset, we will load the
 762          * configuration data out of the NVM manually.
 763          */
 764         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 765                 struct e1000_adapter *adapter = hw->adapter;
 766
 767                 /* Check if SW needs configure the PHY */
 768                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 769                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
 770                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 771                 else
 772                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 773
 774                 data = er32(FEXTNVM);
 775                 if (!(data & sw_cfg_mask))
 776                         return 0;
 777
 778                 /* Wait for basic configuration completes before proceeding */
 779                 e1000_lan_init_done_ich8lan(hw);
 780
 781                 /*
 782                  * Make sure HW does not configure LCD from PHY
 783                  * extended configuration before SW configuration
 784                  */
 785                 data = er32(EXTCNF_CTRL);
 786                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 787                         return 0;
 788
 789                 cnf_size = er32(EXTCNF_SIZE);
 790                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 791                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 792                 if (!cnf_size)
 793                         return 0;
 794
 795                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 796                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 797
 798                 /* Configure LCD from extended configuration region. */
 799
 800                 /* cnf_base_addr is in DWORD */
 801                 word_addr = (u16)(cnf_base_addr << 1);
 802
 803                 for (i = 0; i < cnf_size; i++) {
 804                         ret_val = e1000_read_nvm(hw,
 805                                                 (word_addr + i * 2),
 806                                                 1,
 807                                                 &reg_data);
 808                         if (ret_val)
 809                                 return ret_val;
 810
 811                         ret_val = e1000_read_nvm(hw,
 812                                                 (word_addr + i * 2 + 1),
 813                                                 1,
 814                                                 &reg_addr);
 815                         if (ret_val)
 816                                 return ret_val;
 817
 818                         /* Save off the PHY page for future writes. */
 819                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 820                                 phy_page = reg_data;
 821                                 continue;
 822                         }
 823
 824                         reg_addr |= phy_page;
 825
 826                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
 827                         if (ret_val)
 828                                 return ret_val;
 829                 }
 830         }
 831
 832         return 0;
 833 }
 834
 835 /**
 836  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 837  *  @hw: pointer to the HW structure
 838  *
 839  *  Populates "phy" structure with various feature states.
 840  *  This function is only called by other family-specific
 841  *  routines.
 842  **/
 843 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 844 {
 845         struct e1000_phy_info *phy = &hw->phy;
 846         s32 ret_val;
 847         u16 data;
 848         bool link;
 849
 850         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 851         if (ret_val)
 852                 return ret_val;
 853
 854         if (!link) {
 855                 hw_dbg(hw, "Phy info is only valid if link is up\n");
 856                 return -E1000_ERR_CONFIG;
 857         }
 858
 859         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
 860         if (ret_val)
 861                 return ret_val;
 862         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
 863
 864         if (phy->polarity_correction) {
 865                 ret_val = phy->ops.check_polarity(hw);
 866                 if (ret_val)
 867                         return ret_val;
 868         } else {
 869                 /* Polarity is forced */
 870                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
 871                                       ? e1000_rev_polarity_reversed
 872                                       : e1000_rev_polarity_normal;
 873         }
 874
 875         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 876         if (ret_val)
 877                 return ret_val;
 878
 879         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
 880
 881         /* The following parameters are undefined for 10/100 operation. */
 882         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 883         phy->local_rx = e1000_1000t_rx_status_undefined;
 884         phy->remote_rx = e1000_1000t_rx_status_undefined;
 885
 886         return 0;
 887 }
 888
 889 /**
 890  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
 891  *  @hw: pointer to the HW structure
 892  *
 893  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
 894  *  This is a function pointer entry point called by drivers
 895  *  or other shared routines.
 896  **/
 897 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
 898 {
 899         switch (hw->phy.type) {
 900         case e1000_phy_ife:
 901                 return e1000_get_phy_info_ife_ich8lan(hw);
 902                 break;
 903         case e1000_phy_igp_3:
 904         case e1000_phy_bm:
 905         case e1000_phy_82578:
 906         case e1000_phy_82577:
 907                 return e1000e_get_phy_info_igp(hw);
 908                 break;
 909         default:
 910                 break;
 911         }
 912
 913         return -E1000_ERR_PHY_TYPE;
 914 }
 915
 916 /**
 917  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
 918  *  @hw: pointer to the HW structure
 919  *
 920  *  Polarity is determined on the polarity reversal feature being enabled.
 921  *  This function is only called by other family-specific
 922  *  routines.
 923  **/
 924 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
 925 {
 926         struct e1000_phy_info *phy = &hw->phy;
 927         s32 ret_val;
 928         u16 phy_data, offset, mask;
 929
 930         /*
 931          * Polarity is determined based on the reversal feature being enabled.
 932          */
 933         if (phy->polarity_correction) {
 934                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
 935                 mask    = IFE_PESC_POLARITY_REVERSED;
 936         } else {
 937                 offset  = IFE_PHY_SPECIAL_CONTROL;
 938                 mask    = IFE_PSC_FORCE_POLARITY;
 939         }
 940
 941         ret_val = e1e_rphy(hw, offset, &phy_data);
 942
 943         if (!ret_val)
 944                 phy->cable_polarity = (phy_data & mask)
 945                                       ? e1000_rev_polarity_reversed
 946                                       : e1000_rev_polarity_normal;
 947
 948         return ret_val;
 949 }
 950
 951 /**
 952  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
 953  *  @hw: pointer to the HW structure
 954  *  @active: TRUE to enable LPLU, FALSE to disable
 955  *
 956  *  Sets the LPLU D0 state according to the active flag.  When
 957  *  activating LPLU this function also disables smart speed
 958  *  and vice versa.  LPLU will not be activated unless the
 959  *  device autonegotiation advertisement meets standards of
 960  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 961  *  This is a function pointer entry point only called by
 962  *  PHY setup routines.
 963  **/
 964 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 965 {
 966         struct e1000_phy_info *phy = &hw->phy;
 967         u32 phy_ctrl;
 968         s32 ret_val = 0;
 969         u16 data;
 970
 971         if (phy->type == e1000_phy_ife)
 972                 return ret_val;
 973
 974         phy_ctrl = er32(PHY_CTRL);
 975
 976         if (active) {
 977                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
 978                 ew32(PHY_CTRL, phy_ctrl);
 979
 980                 /*
 981                  * Call gig speed drop workaround on LPLU before accessing
 982                  * any PHY registers
 983                  */
 984                 if ((hw->mac.type == e1000_ich8lan) &&
 985                     (hw->phy.type == e1000_phy_igp_3))
 986                         e1000e_gig_downshift_workaround_ich8lan(hw);
 987
 988                 /* When LPLU is enabled, we should disable SmartSpeed */
 989                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 990                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 991                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 992                 if (ret_val)
 993                         return ret_val;
 994         } else {
 995                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
 996                 ew32(PHY_CTRL, phy_ctrl);
 997
 998                 /*
 999                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1000                  * during Dx states where the power conservation is most
1001                  * important.  During driver activity we should enable
1002                  * SmartSpeed, so performance is maintained.
1003                  */
1004                 if (phy->smart_speed == e1000_smart_speed_on) {
1005                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1006                                            &data);
1007                         if (ret_val)
1008                                 return ret_val;
1009
1010                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1011                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1012                                            data);
1013                         if (ret_val)
1014                                 return ret_val;
1015                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1016                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1017                                            &data);
1018                         if (ret_val)
1019                                 return ret_val;
1020
1021                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1022                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1023                                            data);
1024                         if (ret_val)
1025                                 return ret_val;
1026                 }
1027         }
1028
1029         return 0;
1030 }
1031
1032 /**
1033  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1034  *  @hw: pointer to the HW structure
1035  *  @active: TRUE to enable LPLU, FALSE to disable
1036  *
1037  *  Sets the LPLU D3 state according to the active flag.  When
1038  *  activating LPLU this function also disables smart speed
1039  *  and vice versa.  LPLU will not be activated unless the
1040  *  device autonegotiation advertisement meets standards of
1041  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1042  *  This is a function pointer entry point only called by
1043  *  PHY setup routines.
1044  **/
1045 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1046 {
1047         struct e1000_phy_info *phy = &hw->phy;
1048         u32 phy_ctrl;
1049         s32 ret_val;
1050         u16 data;
1051
1052         phy_ctrl = er32(PHY_CTRL);
1053
1054         if (!active) {
1055                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1056                 ew32(PHY_CTRL, phy_ctrl);
1057                 /*
1058                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1059                  * during Dx states where the power conservation is most
1060                  * important.  During driver activity we should enable
1061                  * SmartSpeed, so performance is maintained.
1062                  */
1063                 if (phy->smart_speed == e1000_smart_speed_on) {
1064                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1065                                            &data);
1066                         if (ret_val)
1067                                 return ret_val;
1068
1069                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1070                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1071                                            data);
1072                         if (ret_val)
1073                                 return ret_val;
1074                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1075                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1076                                            &data);
1077                         if (ret_val)
1078                                 return ret_val;
1079
1080                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1081                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1082                                            data);
1083                         if (ret_val)
1084                                 return ret_val;
1085                 }
1086         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1087                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1088                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1089                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1090                 ew32(PHY_CTRL, phy_ctrl);
1091
1092                 /*
1093                  * Call gig speed drop workaround on LPLU before accessing
1094                  * any PHY registers
1095                  */
1096                 if ((hw->mac.type == e1000_ich8lan) &&
1097                     (hw->phy.type == e1000_phy_igp_3))
1098                         e1000e_gig_downshift_workaround_ich8lan(hw);
1099
1100                 /* When LPLU is enabled, we should disable SmartSpeed */
1101                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1102                 if (ret_val)
1103                         return ret_val;
1104
1105                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1106                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1107         }
1108
1109         return 0;
1110 }
1111
1112 /**
1113  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1114  *  @hw: pointer to the HW structure
1115  *  @bank:  pointer to the variable that returns the active bank
1116  *
1117  *  Reads signature byte from the NVM using the flash access registers.
1118  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1119  **/
1120 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1121 {
1122         u32 eecd;
1123         struct e1000_nvm_info *nvm = &hw->nvm;
1124         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1125         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1126         u8 sig_byte = 0;
1127         s32 ret_val = 0;
1128
1129         switch (hw->mac.type) {
1130         case e1000_ich8lan:
1131         case e1000_ich9lan:
1132                 eecd = er32(EECD);
1133                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1134                     E1000_EECD_SEC1VAL_VALID_MASK) {
1135                         if (eecd & E1000_EECD_SEC1VAL)
1136                                 *bank = 1;
1137                         else
1138                                 *bank = 0;
1139
1140                         return 0;
1141                 }
1142                 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
1143                        "reading flash signature\n");
1144                 /* fall-thru */
1145         default:
1146                 /* set bank to 0 in case flash read fails */
1147                 *bank = 0;
1148
1149                 /* Check bank 0 */
1150                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1151                                                         &sig_byte);
1152                 if (ret_val)
1153                         return ret_val;
1154                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1155                     E1000_ICH_NVM_SIG_VALUE) {
1156                         *bank = 0;
1157                         return 0;
1158                 }
1159
1160                 /* Check bank 1 */
1161                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1162                                                         bank1_offset,
1163                                                         &sig_byte);
1164                 if (ret_val)
1165                         return ret_val;
1166                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1167                     E1000_ICH_NVM_SIG_VALUE) {
1168                         *bank = 1;
1169                         return 0;
1170                 }
1171
1172                 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1173                 return -E1000_ERR_NVM;
1174         }
1175
1176         return 0;
1177 }
1178
1179 /**
1180  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1181  *  @hw: pointer to the HW structure
1182  *  @offset: The offset (in bytes) of the word(s) to read.
1183  *  @words: Size of data to read in words
1184  *  @data: Pointer to the word(s) to read at offset.
1185  *
1186  *  Reads a word(s) from the NVM using the flash access registers.
1187  **/
1188 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1189                                   u16 *data)
1190 {
1191         struct e1000_nvm_info *nvm = &hw->nvm;
1192         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1193         u32 act_offset;
1194         s32 ret_val;
1195         u32 bank = 0;
1196         u16 i, word;
1197
1198         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1199             (words == 0)) {
1200                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1201                 return -E1000_ERR_NVM;
1202         }
1203
1204         ret_val = e1000_acquire_swflag_ich8lan(hw);
1205         if (ret_val)
1206                 goto out;
1207
1208         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1209         if (ret_val)
1210                 goto release;
1211
1212         act_offset = (bank) ? nvm->flash_bank_size : 0;
1213         act_offset += offset;
1214
1215         for (i = 0; i < words; i++) {
1216                 if ((dev_spec->shadow_ram) &&
1217                     (dev_spec->shadow_ram[offset+i].modified)) {
1218                         data[i] = dev_spec->shadow_ram[offset+i].value;
1219                 } else {
1220                         ret_val = e1000_read_flash_word_ich8lan(hw,
1221                                                                 act_offset + i,
1222                                                                 &word);
1223                         if (ret_val)
1224                                 break;
1225                         data[i] = word;
1226                 }
1227         }
1228
1229 release:
1230         e1000_release_swflag_ich8lan(hw);
1231
1232 out:
1233         if (ret_val)
1234                 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1235
1236         return ret_val;
1237 }
1238
1239 /**
1240  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1241  *  @hw: pointer to the HW structure
1242  *
1243  *  This function does initial flash setup so that a new read/write/erase cycle
1244  *  can be started.
1245  **/
1246 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1247 {
1248         union ich8_hws_flash_status hsfsts;
1249         s32 ret_val = -E1000_ERR_NVM;
1250         s32 i = 0;
1251
1252         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1253
1254         /* Check if the flash descriptor is valid */
1255         if (hsfsts.hsf_status.fldesvalid == 0) {
1256                 hw_dbg(hw, "Flash descriptor invalid.  "
1257                          "SW Sequencing must be used.");
1258                 return -E1000_ERR_NVM;
1259         }
1260
1261         /* Clear FCERR and DAEL in hw status by writing 1 */
1262         hsfsts.hsf_status.flcerr = 1;
1263         hsfsts.hsf_status.dael = 1;
1264
1265         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1266
1267         /*
1268          * Either we should have a hardware SPI cycle in progress
1269          * bit to check against, in order to start a new cycle or
1270          * FDONE bit should be changed in the hardware so that it
1271          * is 1 after hardware reset, which can then be used as an
1272          * indication whether a cycle is in progress or has been
1273          * completed.
1274          */
1275
1276         if (hsfsts.hsf_status.flcinprog == 0) {
1277                 /*
1278                  * There is no cycle running at present,
1279                  * so we can start a cycle
1280                  * Begin by setting Flash Cycle Done.
1281                  */
1282                 hsfsts.hsf_status.flcdone = 1;
1283                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1284                 ret_val = 0;
1285         } else {
1286                 /*
1287                  * otherwise poll for sometime so the current
1288                  * cycle has a chance to end before giving up.
1289                  */
1290                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1291                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1292                         if (hsfsts.hsf_status.flcinprog == 0) {
1293                                 ret_val = 0;
1294                                 break;
1295                         }
1296                         udelay(1);
1297                 }
1298                 if (ret_val == 0) {
1299                         /*
1300                          * Successful in waiting for previous cycle to timeout,
1301                          * now set the Flash Cycle Done.
1302                          */
1303                         hsfsts.hsf_status.flcdone = 1;
1304                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1305                 } else {
1306                         hw_dbg(hw, "Flash controller busy, cannot get access");
1307                 }
1308         }
1309
1310         return ret_val;
1311 }
1312
1313 /**
1314  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1315  *  @hw: pointer to the HW structure
1316  *  @timeout: maximum time to wait for completion
1317  *
1318  *  This function starts a flash cycle and waits for its completion.
1319  **/
1320 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1321 {
1322         union ich8_hws_flash_ctrl hsflctl;
1323         union ich8_hws_flash_status hsfsts;
1324         s32 ret_val = -E1000_ERR_NVM;
1325         u32 i = 0;
1326
1327         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1328         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1329         hsflctl.hsf_ctrl.flcgo = 1;
1330         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1331
1332         /* wait till FDONE bit is set to 1 */
1333         do {
1334                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1335                 if (hsfsts.hsf_status.flcdone == 1)
1336                         break;
1337                 udelay(1);
1338         } while (i++ < timeout);
1339
1340         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1341                 return 0;
1342
1343         return ret_val;
1344 }
1345
1346 /**
1347  *  e1000_read_flash_word_ich8lan - Read word from flash
1348  *  @hw: pointer to the HW structure
1349  *  @offset: offset to data location
1350  *  @data: pointer to the location for storing the data
1351  *
1352  *  Reads the flash word at offset into data.  Offset is converted
1353  *  to bytes before read.
1354  **/
1355 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1356                                          u16 *data)
1357 {
1358         /* Must convert offset into bytes. */
1359         offset <<= 1;
1360
1361         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1362 }
1363
1364 /**
1365  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1366  *  @hw: pointer to the HW structure
1367  *  @offset: The offset of the byte to read.
1368  *  @data: Pointer to a byte to store the value read.
1369  *
1370  *  Reads a single byte from the NVM using the flash access registers.
1371  **/
1372 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1373                                          u8 *data)
1374 {
1375         s32 ret_val;
1376         u16 word = 0;
1377
1378         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1379         if (ret_val)
1380                 return ret_val;
1381
1382         *data = (u8)word;
1383
1384         return 0;
1385 }
1386
1387 /**
1388  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1389  *  @hw: pointer to the HW structure
1390  *  @offset: The offset (in bytes) of the byte or word to read.
1391  *  @size: Size of data to read, 1=byte 2=word
1392  *  @data: Pointer to the word to store the value read.
1393  *
1394  *  Reads a byte or word from the NVM using the flash access registers.
1395  **/
1396 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1397                                          u8 size, u16 *data)
1398 {
1399         union ich8_hws_flash_status hsfsts;
1400         union ich8_hws_flash_ctrl hsflctl;
1401         u32 flash_linear_addr;
1402         u32 flash_data = 0;
1403         s32 ret_val = -E1000_ERR_NVM;
1404         u8 count = 0;
1405
1406         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1407                 return -E1000_ERR_NVM;
1408
1409         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1410                             hw->nvm.flash_base_addr;
1411
1412         do {
1413                 udelay(1);
1414                 /* Steps */
1415                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1416                 if (ret_val != 0)
1417                         break;
1418
1419                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1420                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1421                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1422                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1423                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1424
1425                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1426
1427                 ret_val = e1000_flash_cycle_ich8lan(hw,
1428                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1429
1430                 /*
1431                  * Check if FCERR is set to 1, if set to 1, clear it
1432                  * and try the whole sequence a few more times, else
1433                  * read in (shift in) the Flash Data0, the order is
1434                  * least significant byte first msb to lsb
1435                  */
1436                 if (ret_val == 0) {
1437                         flash_data = er32flash(ICH_FLASH_FDATA0);
1438                         if (size == 1) {
1439                                 *data = (u8)(flash_data & 0x000000FF);
1440                         } else if (size == 2) {
1441                                 *data = (u16)(flash_data & 0x0000FFFF);
1442                         }
1443                         break;
1444                 } else {
1445                         /*
1446                          * If we've gotten here, then things are probably
1447                          * completely hosed, but if the error condition is
1448                          * detected, it won't hurt to give it another try...
1449                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1450                          */
1451                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1452                         if (hsfsts.hsf_status.flcerr == 1) {
1453                                 /* Repeat for some time before giving up. */
1454                                 continue;
1455                         } else if (hsfsts.hsf_status.flcdone == 0) {
1456                                 hw_dbg(hw, "Timeout error - flash cycle "
1457                                          "did not complete.");
1458                                 break;
1459                         }
1460                 }
1461         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1462
1463         return ret_val;
1464 }
1465
1466 /**
1467  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1468  *  @hw: pointer to the HW structure
1469  *  @offset: The offset (in bytes) of the word(s) to write.
1470  *  @words: Size of data to write in words
1471  *  @data: Pointer to the word(s) to write at offset.
1472  *
1473  *  Writes a byte or word to the NVM using the flash access registers.
1474  **/
1475 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1476                                    u16 *data)
1477 {
1478         struct e1000_nvm_info *nvm = &hw->nvm;
1479         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1480         s32 ret_val;
1481         u16 i;
1482
1483         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1484             (words == 0)) {
1485                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1486                 return -E1000_ERR_NVM;
1487         }
1488
1489         ret_val = e1000_acquire_swflag_ich8lan(hw);
1490         if (ret_val)
1491                 return ret_val;
1492
1493         for (i = 0; i < words; i++) {
1494                 dev_spec->shadow_ram[offset+i].modified = 1;
1495                 dev_spec->shadow_ram[offset+i].value = data[i];
1496         }
1497
1498         e1000_release_swflag_ich8lan(hw);
1499
1500         return 0;
1501 }
1502
1503 /**
1504  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1505  *  @hw: pointer to the HW structure
1506  *
1507  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1508  *  which writes the checksum to the shadow ram.  The changes in the shadow
1509  *  ram are then committed to the EEPROM by processing each bank at a time
1510  *  checking for the modified bit and writing only the pending changes.
1511  *  After a successful commit, the shadow ram is cleared and is ready for
1512  *  future writes.
1513  **/
1514 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1515 {
1516         struct e1000_nvm_info *nvm = &hw->nvm;
1517         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1518         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1519         s32 ret_val;
1520         u16 data;
1521
1522         ret_val = e1000e_update_nvm_checksum_generic(hw);
1523         if (ret_val)
1524                 goto out;
1525
1526         if (nvm->type != e1000_nvm_flash_sw)
1527                 goto out;
1528
1529         ret_val = e1000_acquire_swflag_ich8lan(hw);
1530         if (ret_val)
1531                 goto out;
1532
1533         /*
1534          * We're writing to the opposite bank so if we're on bank 1,
1535          * write to bank 0 etc.  We also need to erase the segment that
1536          * is going to be written
1537          */
1538         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1539         if (ret_val) {
1540                 e1000_release_swflag_ich8lan(hw);
1541                 goto out;
1542         }
1543
1544         if (bank == 0) {
1545                 new_bank_offset = nvm->flash_bank_size;
1546                 old_bank_offset = 0;
1547                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1548                 if (ret_val) {
1549                         e1000_release_swflag_ich8lan(hw);
1550                         goto out;
1551                 }
1552         } else {
1553                 old_bank_offset = nvm->flash_bank_size;
1554                 new_bank_offset = 0;
1555                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1556                 if (ret_val) {
1557                         e1000_release_swflag_ich8lan(hw);
1558                         goto out;
1559                 }
1560         }
1561
1562         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1563                 /*
1564                  * Determine whether to write the value stored
1565                  * in the other NVM bank or a modified value stored
1566                  * in the shadow RAM
1567                  */
1568                 if (dev_spec->shadow_ram[i].modified) {
1569                         data = dev_spec->shadow_ram[i].value;
1570                 } else {
1571                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
1572                                                                 old_bank_offset,
1573                                                                 &data);
1574                         if (ret_val)
1575                                 break;
1576                 }
1577
1578                 /*
1579                  * If the word is 0x13, then make sure the signature bits
1580                  * (15:14) are 11b until the commit has completed.
1581                  * This will allow us to write 10b which indicates the
1582                  * signature is valid.  We want to do this after the write
1583                  * has completed so that we don't mark the segment valid
1584                  * while the write is still in progress
1585                  */
1586                 if (i == E1000_ICH_NVM_SIG_WORD)
1587                         data |= E1000_ICH_NVM_SIG_MASK;
1588
1589                 /* Convert offset to bytes. */
1590                 act_offset = (i + new_bank_offset) << 1;
1591
1592                 udelay(100);
1593                 /* Write the bytes to the new bank. */
1594                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1595                                                                act_offset,
1596                                                                (u8)data);
1597                 if (ret_val)
1598                         break;
1599
1600                 udelay(100);
1601                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1602                                                           act_offset + 1,
1603                                                           (u8)(data >> 8));
1604                 if (ret_val)
1605                         break;
1606         }
1607
1608         /*
1609          * Don't bother writing the segment valid bits if sector
1610          * programming failed.
1611          */
1612         if (ret_val) {
1613                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1614                 hw_dbg(hw, "Flash commit failed.\n");
1615                 e1000_release_swflag_ich8lan(hw);
1616                 goto out;
1617         }
1618
1619         /*
1620          * Finally validate the new segment by setting bit 15:14
1621          * to 10b in word 0x13 , this can be done without an
1622          * erase as well since these bits are 11 to start with
1623          * and we need to change bit 14 to 0b
1624          */
1625         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1626         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1627         if (ret_val) {
1628                 e1000_release_swflag_ich8lan(hw);
1629                 goto out;
1630         }
1631         data &= 0xBFFF;
1632         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1633                                                        act_offset * 2 + 1,
1634                                                        (u8)(data >> 8));
1635         if (ret_val) {
1636                 e1000_release_swflag_ich8lan(hw);
1637                 goto out;
1638         }
1639
1640         /*
1641          * And invalidate the previously valid segment by setting
1642          * its signature word (0x13) high_byte to 0b. This can be
1643          * done without an erase because flash erase sets all bits
1644          * to 1's. We can write 1's to 0's without an erase
1645          */
1646         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1647         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1648         if (ret_val) {
1649                 e1000_release_swflag_ich8lan(hw);
1650                 goto out;
1651         }
1652
1653         /* Great!  Everything worked, we can now clear the cached entries. */
1654         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1655                 dev_spec->shadow_ram[i].modified = 0;
1656                 dev_spec->shadow_ram[i].value = 0xFFFF;
1657         }
1658
1659         e1000_release_swflag_ich8lan(hw);
1660
1661         /*
1662          * Reload the EEPROM, or else modifications will not appear
1663          * until after the next adapter reset.
1664          */
1665         e1000e_reload_nvm(hw);
1666         msleep(10);
1667
1668 out:
1669         if (ret_val)
1670                 hw_dbg(hw, "NVM update error: %d\n", ret_val);
1671
1672         return ret_val;
1673 }
1674
1675 /**
1676  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1677  *  @hw: pointer to the HW structure
1678  *
1679  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1680  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1681  *  calculated, in which case we need to calculate the checksum and set bit 6.
1682  **/
1683 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1684 {
1685         s32 ret_val;
1686         u16 data;
1687
1688         /*
1689          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1690          * needs to be fixed.  This bit is an indication that the NVM
1691          * was prepared by OEM software and did not calculate the
1692          * checksum...a likely scenario.
1693          */
1694         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1695         if (ret_val)
1696                 return ret_val;
1697
1698         if ((data & 0x40) == 0) {
1699                 data |= 0x40;
1700                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1701                 if (ret_val)
1702                         return ret_val;
1703                 ret_val = e1000e_update_nvm_checksum(hw);
1704                 if (ret_val)
1705                         return ret_val;
1706         }
1707
1708         return e1000e_validate_nvm_checksum_generic(hw);
1709 }
1710
1711 /**
1712  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1713  *  @hw: pointer to the HW structure
1714  *
1715  *  To prevent malicious write/erase of the NVM, set it to be read-only
1716  *  so that the hardware ignores all write/erase cycles of the NVM via
1717  *  the flash control registers.  The shadow-ram copy of the NVM will
1718  *  still be updated, however any updates to this copy will not stick
1719  *  across driver reloads.
1720  **/
1721 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1722 {
1723         union ich8_flash_protected_range pr0;
1724         union ich8_hws_flash_status hsfsts;
1725         u32 gfpreg;
1726         s32 ret_val;
1727
1728         ret_val = e1000_acquire_swflag_ich8lan(hw);
1729         if (ret_val)
1730                 return;
1731
1732         gfpreg = er32flash(ICH_FLASH_GFPREG);
1733
1734         /* Write-protect GbE Sector of NVM */
1735         pr0.regval = er32flash(ICH_FLASH_PR0);
1736         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1737         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1738         pr0.range.wpe = true;
1739         ew32flash(ICH_FLASH_PR0, pr0.regval);
1740
1741         /*
1742          * Lock down a subset of GbE Flash Control Registers, e.g.
1743          * PR0 to prevent the write-protection from being lifted.
1744          * Once FLOCKDN is set, the registers protected by it cannot
1745          * be written until FLOCKDN is cleared by a hardware reset.
1746          */
1747         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1748         hsfsts.hsf_status.flockdn = true;
1749         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1750
1751         e1000_release_swflag_ich8lan(hw);
1752 }
1753
1754 /**
1755  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1756  *  @hw: pointer to the HW structure
1757  *  @offset: The offset (in bytes) of the byte/word to read.
1758  *  @size: Size of data to read, 1=byte 2=word
1759  *  @data: The byte(s) to write to the NVM.
1760  *
1761  *  Writes one/two bytes to the NVM using the flash access registers.
1762  **/
1763 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1764                                           u8 size, u16 data)
1765 {
1766         union ich8_hws_flash_status hsfsts;
1767         union ich8_hws_flash_ctrl hsflctl;
1768         u32 flash_linear_addr;
1769         u32 flash_data = 0;
1770         s32 ret_val;
1771         u8 count = 0;
1772
1773         if (size < 1 || size > 2 || data > size * 0xff ||
1774             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1775                 return -E1000_ERR_NVM;
1776
1777         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1778                             hw->nvm.flash_base_addr;
1779
1780         do {
1781                 udelay(1);
1782                 /* Steps */
1783                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1784                 if (ret_val)
1785                         break;
1786
1787                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1788                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1789                 hsflctl.hsf_ctrl.fldbcount = size -1;
1790                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1791                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1792
1793                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1794
1795                 if (size == 1)
1796                         flash_data = (u32)data & 0x00FF;
1797                 else
1798                         flash_data = (u32)data;
1799
1800                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1801
1802                 /*
1803                  * check if FCERR is set to 1 , if set to 1, clear it
1804                  * and try the whole sequence a few more times else done
1805                  */
1806                 ret_val = e1000_flash_cycle_ich8lan(hw,
1807                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1808                 if (!ret_val)
1809                         break;
1810
1811                 /*
1812                  * If we're here, then things are most likely
1813                  * completely hosed, but if the error condition
1814                  * is detected, it won't hurt to give it another
1815                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1816                  */
1817                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1818                 if (hsfsts.hsf_status.flcerr == 1)
1819                         /* Repeat for some time before giving up. */
1820                         continue;
1821                 if (hsfsts.hsf_status.flcdone == 0) {
1822                         hw_dbg(hw, "Timeout error - flash cycle "
1823                                  "did not complete.");
1824                         break;
1825                 }
1826         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1827
1828         return ret_val;
1829 }
1830
1831 /**
1832  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1833  *  @hw: pointer to the HW structure
1834  *  @offset: The index of the byte to read.
1835  *  @data: The byte to write to the NVM.
1836  *
1837  *  Writes a single byte to the NVM using the flash access registers.
1838  **/
1839 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1840                                           u8 data)
1841 {
1842         u16 word = (u16)data;
1843
1844         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1845 }
1846
1847 /**
1848  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1849  *  @hw: pointer to the HW structure
1850  *  @offset: The offset of the byte to write.
1851  *  @byte: The byte to write to the NVM.
1852  *
1853  *  Writes a single byte to the NVM using the flash access registers.
1854  *  Goes through a retry algorithm before giving up.
1855  **/
1856 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1857                                                 u32 offset, u8 byte)
1858 {
1859         s32 ret_val;
1860         u16 program_retries;
1861
1862         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1863         if (!ret_val)
1864                 return ret_val;
1865
1866         for (program_retries = 0; program_retries < 100; program_retries++) {
1867                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1868                 udelay(100);
1869                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1870                 if (!ret_val)
1871                         break;
1872         }
1873         if (program_retries == 100)
1874                 return -E1000_ERR_NVM;
1875
1876         return 0;
1877 }
1878
1879 /**
1880  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1881  *  @hw: pointer to the HW structure
1882  *  @bank: 0 for first bank, 1 for second bank, etc.
1883  *
1884  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1885  *  bank N is 4096 * N + flash_reg_addr.
1886  **/
1887 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1888 {
1889         struct e1000_nvm_info *nvm = &hw->nvm;
1890         union ich8_hws_flash_status hsfsts;
1891         union ich8_hws_flash_ctrl hsflctl;
1892         u32 flash_linear_addr;
1893         /* bank size is in 16bit words - adjust to bytes */
1894         u32 flash_bank_size = nvm->flash_bank_size * 2;
1895         s32 ret_val;
1896         s32 count = 0;
1897         s32 iteration;
1898         s32 sector_size;
1899         s32 j;
1900
1901         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1902
1903         /*
1904          * Determine HW Sector size: Read BERASE bits of hw flash status
1905          * register
1906          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1907          *     consecutive sectors.  The start index for the nth Hw sector
1908          *     can be calculated as = bank * 4096 + n * 256
1909          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1910          *     The start index for the nth Hw sector can be calculated
1911          *     as = bank * 4096
1912          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1913          *     (ich9 only, otherwise error condition)
1914          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1915          */
1916         switch (hsfsts.hsf_status.berasesz) {
1917         case 0:
1918                 /* Hw sector size 256 */
1919                 sector_size = ICH_FLASH_SEG_SIZE_256;
1920                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1921                 break;
1922         case 1:
1923                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1924                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1925                 break;
1926         case 2:
1927                 if (hw->mac.type == e1000_ich9lan) {
1928                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1929                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1930                 } else {
1931                         return -E1000_ERR_NVM;
1932                 }
1933                 break;
1934         case 3:
1935                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1936                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1937                 break;
1938         default:
1939                 return -E1000_ERR_NVM;
1940         }
1941
1942         /* Start with the base address, then add the sector offset. */
1943         flash_linear_addr = hw->nvm.flash_base_addr;
1944         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1945
1946         for (j = 0; j < iteration ; j++) {
1947                 do {
1948                         /* Steps */
1949                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1950                         if (ret_val)
1951                                 return ret_val;
1952
1953                         /*
1954                          * Write a value 11 (block Erase) in Flash
1955                          * Cycle field in hw flash control
1956                          */
1957                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1958                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1959                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1960
1961                         /*
1962                          * Write the last 24 bits of an index within the
1963                          * block into Flash Linear address field in Flash
1964                          * Address.
1965                          */
1966                         flash_linear_addr += (j * sector_size);
1967                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1968
1969                         ret_val = e1000_flash_cycle_ich8lan(hw,
1970                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1971                         if (ret_val == 0)
1972                                 break;
1973
1974                         /*
1975                          * Check if FCERR is set to 1.  If 1,
1976                          * clear it and try the whole sequence
1977                          * a few more times else Done
1978                          */
1979                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1980                         if (hsfsts.hsf_status.flcerr == 1)
1981                                 /* repeat for some time before giving up */
1982                                 continue;
1983                         else if (hsfsts.hsf_status.flcdone == 0)
1984                                 return ret_val;
1985                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1986         }
1987
1988         return 0;
1989 }
1990
1991 /**
1992  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1993  *  @hw: pointer to the HW structure
1994  *  @data: Pointer to the LED settings
1995  *
1996  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1997  *  settings is all 0's or F's, set the LED default to a valid LED default
1998  *  setting.
1999  **/
2000 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2001 {
2002         s32 ret_val;
2003
2004         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2005         if (ret_val) {
2006                 hw_dbg(hw, "NVM Read Error\n");
2007                 return ret_val;
2008         }
2009
2010         if (*data == ID_LED_RESERVED_0000 ||
2011             *data == ID_LED_RESERVED_FFFF)
2012                 *data = ID_LED_DEFAULT_ICH8LAN;
2013
2014         return 0;
2015 }
2016
2017 /**
2018  *  e1000_id_led_init_pchlan - store LED configurations
2019  *  @hw: pointer to the HW structure
2020  *
2021  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2022  *  the PHY LED configuration register.
2023  *
2024  *  PCH also does not have an "always on" or "always off" mode which
2025  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2026  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2027  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2028  *  link based on logic in e1000_led_[on|off]_pchlan().
2029  **/
2030 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2031 {
2032         struct e1000_mac_info *mac = &hw->mac;
2033         s32 ret_val;
2034         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2035         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2036         u16 data, i, temp, shift;
2037
2038         /* Get default ID LED modes */
2039         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2040         if (ret_val)
2041                 goto out;
2042
2043         mac->ledctl_default = er32(LEDCTL);
2044         mac->ledctl_mode1 = mac->ledctl_default;
2045         mac->ledctl_mode2 = mac->ledctl_default;
2046
2047         for (i = 0; i < 4; i++) {
2048                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2049                 shift = (i * 5);
2050                 switch (temp) {
2051                 case ID_LED_ON1_DEF2:
2052                 case ID_LED_ON1_ON2:
2053                 case ID_LED_ON1_OFF2:
2054                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2055                         mac->ledctl_mode1 |= (ledctl_on << shift);
2056                         break;
2057                 case ID_LED_OFF1_DEF2:
2058                 case ID_LED_OFF1_ON2:
2059                 case ID_LED_OFF1_OFF2:
2060                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2061                         mac->ledctl_mode1 |= (ledctl_off << shift);
2062                         break;
2063                 default:
2064                         /* Do nothing */
2065                         break;
2066                 }
2067                 switch (temp) {
2068                 case ID_LED_DEF1_ON2:
2069                 case ID_LED_ON1_ON2:
2070                 case ID_LED_OFF1_ON2:
2071                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2072                         mac->ledctl_mode2 |= (ledctl_on << shift);
2073                         break;
2074                 case ID_LED_DEF1_OFF2:
2075                 case ID_LED_ON1_OFF2:
2076                 case ID_LED_OFF1_OFF2:
2077                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2078                         mac->ledctl_mode2 |= (ledctl_off << shift);
2079                         break;
2080                 default:
2081                         /* Do nothing */
2082                         break;
2083                 }
2084         }
2085
2086 out:
2087         return ret_val;
2088 }
2089
2090 /**
2091  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2092  *  @hw: pointer to the HW structure
2093  *
2094  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2095  *  register, so the the bus width is hard coded.
2096  **/
2097 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2098 {
2099         struct e1000_bus_info *bus = &hw->bus;
2100         s32 ret_val;
2101
2102         ret_val = e1000e_get_bus_info_pcie(hw);
2103
2104         /*
2105          * ICH devices are "PCI Express"-ish.  They have
2106          * a configuration space, but do not contain
2107          * PCI Express Capability registers, so bus width
2108          * must be hardcoded.
2109          */
2110         if (bus->width == e1000_bus_width_unknown)
2111                 bus->width = e1000_bus_width_pcie_x1;
2112
2113         return ret_val;
2114 }
2115
2116 /**
2117  *  e1000_reset_hw_ich8lan - Reset the hardware
2118  *  @hw: pointer to the HW structure
2119  *
2120  *  Does a full reset of the hardware which includes a reset of the PHY and
2121  *  MAC.
2122  **/
2123 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2124 {
2125         u32 ctrl, icr, kab;
2126         s32 ret_val;
2127
2128         /*
2129          * Prevent the PCI-E bus from sticking if there is no TLP connection
2130          * on the last TLP read/write transaction when MAC is reset.
2131          */
2132         ret_val = e1000e_disable_pcie_master(hw);
2133         if (ret_val) {
2134                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
2135         }
2136
2137         hw_dbg(hw, "Masking off all interrupts\n");
2138         ew32(IMC, 0xffffffff);
2139
2140         /*
2141          * Disable the Transmit and Receive units.  Then delay to allow
2142          * any pending transactions to complete before we hit the MAC
2143          * with the global reset.
2144          */
2145         ew32(RCTL, 0);
2146         ew32(TCTL, E1000_TCTL_PSP);
2147         e1e_flush();
2148
2149         msleep(10);
2150
2151         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2152         if (hw->mac.type == e1000_ich8lan) {
2153                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2154                 ew32(PBA, E1000_PBA_8K);
2155                 /* Set Packet Buffer Size to 16k. */
2156                 ew32(PBS, E1000_PBS_16K);
2157         }
2158
2159         ctrl = er32(CTRL);
2160
2161         if (!e1000_check_reset_block(hw)) {
2162                 /* Clear PHY Reset Asserted bit */
2163                 if (hw->mac.type >= e1000_pchlan) {
2164                         u32 status = er32(STATUS);
2165                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2166                 }
2167
2168                 /*
2169                  * PHY HW reset requires MAC CORE reset at the same
2170                  * time to make sure the interface between MAC and the
2171                  * external PHY is reset.
2172                  */
2173                 ctrl |= E1000_CTRL_PHY_RST;
2174         }
2175         ret_val = e1000_acquire_swflag_ich8lan(hw);
2176         /* Whether or not the swflag was acquired, we need to reset the part */
2177         hw_dbg(hw, "Issuing a global reset to ich8lan\n");
2178         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2179         msleep(20);
2180
2181         if (!ret_val)
2182                 e1000_release_swflag_ich8lan(hw);
2183
2184         if (ctrl & E1000_CTRL_PHY_RST)
2185                 ret_val = hw->phy.ops.get_cfg_done(hw);
2186
2187         if (hw->mac.type >= e1000_ich10lan) {
2188                 e1000_lan_init_done_ich8lan(hw);
2189         } else {
2190                 ret_val = e1000e_get_auto_rd_done(hw);
2191                 if (ret_val) {
2192                         /*
2193                          * When auto config read does not complete, do not
2194                          * return with an error. This can happen in situations
2195                          * where there is no eeprom and prevents getting link.
2196                          */
2197                         hw_dbg(hw, "Auto Read Done did not complete\n");
2198                 }
2199         }
2200
2201         ew32(IMC, 0xffffffff);
2202         icr = er32(ICR);
2203
2204         kab = er32(KABGTXD);
2205         kab |= E1000_KABGTXD_BGSQLBIAS;
2206         ew32(KABGTXD, kab);
2207
2208         if (hw->mac.type == e1000_pchlan)
2209                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2210
2211         return ret_val;
2212 }
2213
2214 /**
2215  *  e1000_init_hw_ich8lan - Initialize the hardware
2216  *  @hw: pointer to the HW structure
2217  *
2218  *  Prepares the hardware for transmit and receive by doing the following:
2219  *   - initialize hardware bits
2220  *   - initialize LED identification
2221  *   - setup receive address registers
2222  *   - setup flow control
2223  *   - setup transmit descriptors
2224  *   - clear statistics
2225  **/
2226 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2227 {
2228         struct e1000_mac_info *mac = &hw->mac;
2229         u32 ctrl_ext, txdctl, snoop;
2230         s32 ret_val;
2231         u16 i;
2232
2233         e1000_initialize_hw_bits_ich8lan(hw);
2234
2235         /* Initialize identification LED */
2236         ret_val = mac->ops.id_led_init(hw);
2237         if (ret_val) {
2238                 hw_dbg(hw, "Error initializing identification LED\n");
2239                 return ret_val;
2240         }
2241
2242         /* Setup the receive address. */
2243         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2244
2245         /* Zero out the Multicast HASH table */
2246         hw_dbg(hw, "Zeroing the MTA\n");
2247         for (i = 0; i < mac->mta_reg_count; i++)
2248                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2249
2250         /*
2251          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2252          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2253          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2254          */
2255         if (hw->phy.type == e1000_phy_82578) {
2256                 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2257                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2258                 if (ret_val)
2259                         return ret_val;
2260         }
2261
2262         /* Setup link and flow control */
2263         ret_val = e1000_setup_link_ich8lan(hw);
2264
2265         /* Set the transmit descriptor write-back policy for both queues */
2266         txdctl = er32(TXDCTL(0));
2267         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2268                  E1000_TXDCTL_FULL_TX_DESC_WB;
2269         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2270                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2271         ew32(TXDCTL(0), txdctl);
2272         txdctl = er32(TXDCTL(1));
2273         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2274                  E1000_TXDCTL_FULL_TX_DESC_WB;
2275         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2276                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2277         ew32(TXDCTL(1), txdctl);
2278
2279         /*
2280          * ICH8 has opposite polarity of no_snoop bits.
2281          * By default, we should use snoop behavior.
2282          */
2283         if (mac->type == e1000_ich8lan)
2284                 snoop = PCIE_ICH8_SNOOP_ALL;
2285         else
2286                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2287         e1000e_set_pcie_no_snoop(hw, snoop);
2288
2289         ctrl_ext = er32(CTRL_EXT);
2290         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2291         ew32(CTRL_EXT, ctrl_ext);
2292
2293         /*
2294          * Clear all of the statistics registers (clear on read).  It is
2295          * important that we do this after we have tried to establish link
2296          * because the symbol error count will increment wildly if there
2297          * is no link.
2298          */
2299         e1000_clear_hw_cntrs_ich8lan(hw);
2300
2301         return 0;
2302 }
2303 /**
2304  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2305  *  @hw: pointer to the HW structure
2306  *
2307  *  Sets/Clears required hardware bits necessary for correctly setting up the
2308  *  hardware for transmit and receive.
2309  **/
2310 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2311 {
2312         u32 reg;
2313
2314         /* Extended Device Control */
2315         reg = er32(CTRL_EXT);
2316         reg |= (1 << 22);
2317         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2318         if (hw->mac.type >= e1000_pchlan)
2319                 reg |= E1000_CTRL_EXT_PHYPDEN;
2320         ew32(CTRL_EXT, reg);
2321
2322         /* Transmit Descriptor Control 0 */
2323         reg = er32(TXDCTL(0));
2324         reg |= (1 << 22);
2325         ew32(TXDCTL(0), reg);
2326
2327         /* Transmit Descriptor Control 1 */
2328         reg = er32(TXDCTL(1));
2329         reg |= (1 << 22);
2330         ew32(TXDCTL(1), reg);
2331
2332         /* Transmit Arbitration Control 0 */
2333         reg = er32(TARC(0));
2334         if (hw->mac.type == e1000_ich8lan)
2335                 reg |= (1 << 28) | (1 << 29);
2336         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2337         ew32(TARC(0), reg);
2338
2339         /* Transmit Arbitration Control 1 */
2340         reg = er32(TARC(1));
2341         if (er32(TCTL) & E1000_TCTL_MULR)
2342                 reg &= ~(1 << 28);
2343         else
2344                 reg |= (1 << 28);
2345         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2346         ew32(TARC(1), reg);
2347
2348         /* Device Status */
2349         if (hw->mac.type == e1000_ich8lan) {
2350                 reg = er32(STATUS);
2351                 reg &= ~(1 << 31);
2352                 ew32(STATUS, reg);
2353         }
2354 }
2355
2356 /**
2357  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2358  *  @hw: pointer to the HW structure
2359  *
2360  *  Determines which flow control settings to use, then configures flow
2361  *  control.  Calls the appropriate media-specific link configuration
2362  *  function.  Assuming the adapter has a valid link partner, a valid link
2363  *  should be established.  Assumes the hardware has previously been reset
2364  *  and the transmitter and receiver are not enabled.
2365  **/
2366 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2367 {
2368         s32 ret_val;
2369
2370         if (e1000_check_reset_block(hw))
2371                 return 0;
2372
2373         /*
2374          * ICH parts do not have a word in the NVM to determine
2375          * the default flow control setting, so we explicitly
2376          * set it to full.
2377          */
2378         if (hw->fc.requested_mode == e1000_fc_default) {
2379                 /* Workaround h/w hang when Tx flow control enabled */
2380                 if (hw->mac.type == e1000_pchlan)
2381                         hw->fc.requested_mode = e1000_fc_rx_pause;
2382                 else
2383                         hw->fc.requested_mode = e1000_fc_full;
2384         }
2385
2386         /*
2387          * Save off the requested flow control mode for use later.  Depending
2388          * on the link partner's capabilities, we may or may not use this mode.
2389          */
2390         hw->fc.current_mode = hw->fc.requested_mode;
2391
2392         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2393                 hw->fc.current_mode);
2394
2395         /* Continue to configure the copper link. */
2396         ret_val = e1000_setup_copper_link_ich8lan(hw);
2397         if (ret_val)
2398                 return ret_val;
2399
2400         ew32(FCTTV, hw->fc.pause_time);
2401         if ((hw->phy.type == e1000_phy_82578) ||
2402             (hw->phy.type == e1000_phy_82577)) {
2403                 ret_val = hw->phy.ops.write_phy_reg(hw,
2404                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2405                                              hw->fc.pause_time);
2406                 if (ret_val)
2407                         return ret_val;
2408         }
2409
2410         return e1000e_set_fc_watermarks(hw);
2411 }
2412
2413 /**
2414  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2415  *  @hw: pointer to the HW structure
2416  *
2417  *  Configures the kumeran interface to the PHY to wait the appropriate time
2418  *  when polling the PHY, then call the generic setup_copper_link to finish
2419  *  configuring the copper link.
2420  **/
2421 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2422 {
2423         u32 ctrl;
2424         s32 ret_val;
2425         u16 reg_data;
2426
2427         ctrl = er32(CTRL);
2428         ctrl |= E1000_CTRL_SLU;
2429         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2430         ew32(CTRL, ctrl);
2431
2432         /*
2433          * Set the mac to wait the maximum time between each iteration
2434          * and increase the max iterations when polling the phy;
2435          * this fixes erroneous timeouts at 10Mbps.
2436          */
2437         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2438         if (ret_val)
2439                 return ret_val;
2440         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2441         if (ret_val)
2442                 return ret_val;
2443         reg_data |= 0x3F;
2444         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2445         if (ret_val)
2446                 return ret_val;
2447
2448         switch (hw->phy.type) {
2449         case e1000_phy_igp_3:
2450                 ret_val = e1000e_copper_link_setup_igp(hw);
2451                 if (ret_val)
2452                         return ret_val;
2453                 break;
2454         case e1000_phy_bm:
2455         case e1000_phy_82578:
2456                 ret_val = e1000e_copper_link_setup_m88(hw);
2457                 if (ret_val)
2458                         return ret_val;
2459                 break;
2460         case e1000_phy_82577:
2461                 ret_val = e1000_copper_link_setup_82577(hw);
2462                 if (ret_val)
2463                         return ret_val;
2464                 break;
2465         case e1000_phy_ife:
2466                 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2467                                                &reg_data);
2468                 if (ret_val)
2469                         return ret_val;
2470
2471                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2472
2473                 switch (hw->phy.mdix) {
2474                 case 1:
2475                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2476                         break;
2477                 case 2:
2478                         reg_data |= IFE_PMC_FORCE_MDIX;
2479                         break;
2480                 case 0:
2481                 default:
2482                         reg_data |= IFE_PMC_AUTO_MDIX;
2483                         break;
2484                 }
2485                 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2486                                                 reg_data);
2487                 if (ret_val)
2488                         return ret_val;
2489                 break;
2490         default:
2491                 break;
2492         }
2493         return e1000e_setup_copper_link(hw);
2494 }
2495
2496 /**
2497  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2498  *  @hw: pointer to the HW structure
2499  *  @speed: pointer to store current link speed
2500  *  @duplex: pointer to store the current link duplex
2501  *
2502  *  Calls the generic get_speed_and_duplex to retrieve the current link
2503  *  information and then calls the Kumeran lock loss workaround for links at
2504  *  gigabit speeds.
2505  **/
2506 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2507                                           u16 *duplex)
2508 {
2509         s32 ret_val;
2510
2511         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2512         if (ret_val)
2513                 return ret_val;
2514
2515         if ((hw->mac.type == e1000_ich8lan) &&
2516             (hw->phy.type == e1000_phy_igp_3) &&
2517             (*speed == SPEED_1000)) {
2518                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2519         }
2520
2521         return ret_val;
2522 }
2523
2524 /**
2525  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2526  *  @hw: pointer to the HW structure
2527  *
2528  *  Work-around for 82566 Kumeran PCS lock loss:
2529  *  On link status change (i.e. PCI reset, speed change) and link is up and
2530  *  speed is gigabit-
2531  *    0) if workaround is optionally disabled do nothing
2532  *    1) wait 1ms for Kumeran link to come up
2533  *    2) check Kumeran Diagnostic register PCS lock loss bit
2534  *    3) if not set the link is locked (all is good), otherwise...
2535  *    4) reset the PHY
2536  *    5) repeat up to 10 times
2537  *  Note: this is only called for IGP3 copper when speed is 1gb.
2538  **/
2539 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2540 {
2541         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2542         u32 phy_ctrl;
2543         s32 ret_val;
2544         u16 i, data;
2545         bool link;
2546
2547         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2548                 return 0;
2549
2550         /*
2551          * Make sure link is up before proceeding.  If not just return.
2552          * Attempting this while link is negotiating fouled up link
2553          * stability
2554          */
2555         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2556         if (!link)
2557                 return 0;
2558
2559         for (i = 0; i < 10; i++) {
2560                 /* read once to clear */
2561                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2562                 if (ret_val)
2563                         return ret_val;
2564                 /* and again to get new status */
2565                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2566                 if (ret_val)
2567                         return ret_val;
2568
2569                 /* check for PCS lock */
2570                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2571                         return 0;
2572
2573                 /* Issue PHY reset */
2574                 e1000_phy_hw_reset(hw);
2575                 mdelay(5);
2576         }
2577         /* Disable GigE link negotiation */
2578         phy_ctrl = er32(PHY_CTRL);
2579         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2580                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2581         ew32(PHY_CTRL, phy_ctrl);
2582
2583         /*
2584          * Call gig speed drop workaround on Gig disable before accessing
2585          * any PHY registers
2586          */
2587         e1000e_gig_downshift_workaround_ich8lan(hw);
2588
2589         /* unable to acquire PCS lock */
2590         return -E1000_ERR_PHY;
2591 }
2592
2593 /**
2594  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2595  *  @hw: pointer to the HW structure
2596  *  @state: boolean value used to set the current Kumeran workaround state
2597  *
2598  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2599  *  /disabled - FALSE).
2600  **/
2601 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2602                                                  bool state)
2603 {
2604         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2605
2606         if (hw->mac.type != e1000_ich8lan) {
2607                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2608                 return;
2609         }
2610
2611         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2612 }
2613
2614 /**
2615  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2616  *  @hw: pointer to the HW structure
2617  *
2618  *  Workaround for 82566 power-down on D3 entry:
2619  *    1) disable gigabit link
2620  *    2) write VR power-down enable
2621  *    3) read it back
2622  *  Continue if successful, else issue LCD reset and repeat
2623  **/
2624 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2625 {
2626         u32 reg;
2627         u16 data;
2628         u8  retry = 0;
2629
2630         if (hw->phy.type != e1000_phy_igp_3)
2631                 return;
2632
2633         /* Try the workaround twice (if needed) */
2634         do {
2635                 /* Disable link */
2636                 reg = er32(PHY_CTRL);
2637                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2638                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2639                 ew32(PHY_CTRL, reg);
2640
2641                 /*
2642                  * Call gig speed drop workaround on Gig disable before
2643                  * accessing any PHY registers
2644                  */
2645                 if (hw->mac.type == e1000_ich8lan)
2646                         e1000e_gig_downshift_workaround_ich8lan(hw);
2647
2648                 /* Write VR power-down enable */
2649                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2650                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2651                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2652
2653                 /* Read it back and test */
2654                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2655                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2656                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2657                         break;
2658
2659                 /* Issue PHY reset and repeat at most one more time */
2660                 reg = er32(CTRL);
2661                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2662                 retry++;
2663         } while (retry);
2664 }
2665
2666 /**
2667  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2668  *  @hw: pointer to the HW structure
2669  *
2670  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2671  *  LPLU, Gig disable, MDIC PHY reset):
2672  *    1) Set Kumeran Near-end loopback
2673  *    2) Clear Kumeran Near-end loopback
2674  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2675  **/
2676 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2677 {
2678         s32 ret_val;
2679         u16 reg_data;
2680
2681         if ((hw->mac.type != e1000_ich8lan) ||
2682             (hw->phy.type != e1000_phy_igp_3))
2683                 return;
2684
2685         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2686                                       &reg_data);
2687         if (ret_val)
2688                 return;
2689         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2690         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2691                                        reg_data);
2692         if (ret_val)
2693                 return;
2694         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2695         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2696                                        reg_data);
2697 }
2698
2699 /**
2700  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2701  *  @hw: pointer to the HW structure
2702  *
2703  *  During S0 to Sx transition, it is possible the link remains at gig
2704  *  instead of negotiating to a lower speed.  Before going to Sx, set
2705  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2706  *  to a lower speed.
2707  *
2708  *  Should only be called for applicable parts.
2709  **/
2710 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2711 {
2712         u32 phy_ctrl;
2713
2714         switch (hw->mac.type) {
2715         case e1000_ich9lan:
2716         case e1000_ich10lan:
2717         case e1000_pchlan:
2718                 phy_ctrl = er32(PHY_CTRL);
2719                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2720                             E1000_PHY_CTRL_GBE_DISABLE;
2721                 ew32(PHY_CTRL, phy_ctrl);
2722
2723                 /* Workaround SWFLAG unexpectedly set during S0->Sx */
2724                 if (hw->mac.type == e1000_pchlan)
2725                         udelay(500);
2726         default:
2727                 break;
2728         }
2729
2730         return;
2731 }
2732
2733 /**
2734  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2735  *  @hw: pointer to the HW structure
2736  *
2737  *  Return the LED back to the default configuration.
2738  **/
2739 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2740 {
2741         if (hw->phy.type == e1000_phy_ife)
2742                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2743
2744         ew32(LEDCTL, hw->mac.ledctl_default);
2745         return 0;
2746 }
2747
2748 /**
2749  *  e1000_led_on_ich8lan - Turn LEDs on
2750  *  @hw: pointer to the HW structure
2751  *
2752  *  Turn on the LEDs.
2753  **/
2754 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2755 {
2756         if (hw->phy.type == e1000_phy_ife)
2757                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2758                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2759
2760         ew32(LEDCTL, hw->mac.ledctl_mode2);
2761         return 0;
2762 }
2763
2764 /**
2765  *  e1000_led_off_ich8lan - Turn LEDs off
2766  *  @hw: pointer to the HW structure
2767  *
2768  *  Turn off the LEDs.
2769  **/
2770 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2771 {
2772         if (hw->phy.type == e1000_phy_ife)
2773                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2774                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2775
2776         ew32(LEDCTL, hw->mac.ledctl_mode1);
2777         return 0;
2778 }
2779
2780 /**
2781  *  e1000_setup_led_pchlan - Configures SW controllable LED
2782  *  @hw: pointer to the HW structure
2783  *
2784  *  This prepares the SW controllable LED for use.
2785  **/
2786 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
2787 {
2788         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2789                                         (u16)hw->mac.ledctl_mode1);
2790 }
2791
2792 /**
2793  *  e1000_cleanup_led_pchlan - Restore the default LED operation
2794  *  @hw: pointer to the HW structure
2795  *
2796  *  Return the LED back to the default configuration.
2797  **/
2798 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
2799 {
2800         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2801                                         (u16)hw->mac.ledctl_default);
2802 }
2803
2804 /**
2805  *  e1000_led_on_pchlan - Turn LEDs on
2806  *  @hw: pointer to the HW structure
2807  *
2808  *  Turn on the LEDs.
2809  **/
2810 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
2811 {
2812         u16 data = (u16)hw->mac.ledctl_mode2;
2813         u32 i, led;
2814
2815         /*
2816          * If no link, then turn LED on by setting the invert bit
2817          * for each LED that's mode is "link_up" in ledctl_mode2.
2818          */
2819         if (!(er32(STATUS) & E1000_STATUS_LU)) {
2820                 for (i = 0; i < 3; i++) {
2821                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2822                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
2823                             E1000_LEDCTL_MODE_LINK_UP)
2824                                 continue;
2825                         if (led & E1000_PHY_LED0_IVRT)
2826                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2827                         else
2828                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2829                 }
2830         }
2831
2832         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
2833 }
2834
2835 /**
2836  *  e1000_led_off_pchlan - Turn LEDs off
2837  *  @hw: pointer to the HW structure
2838  *
2839  *  Turn off the LEDs.
2840  **/
2841 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
2842 {
2843         u16 data = (u16)hw->mac.ledctl_mode1;
2844         u32 i, led;
2845
2846         /*
2847          * If no link, then turn LED off by clearing the invert bit
2848          * for each LED that's mode is "link_up" in ledctl_mode1.
2849          */
2850         if (!(er32(STATUS) & E1000_STATUS_LU)) {
2851                 for (i = 0; i < 3; i++) {
2852                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2853                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
2854                             E1000_LEDCTL_MODE_LINK_UP)
2855                                 continue;
2856                         if (led & E1000_PHY_LED0_IVRT)
2857                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2858                         else
2859                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2860                 }
2861         }
2862
2863         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
2864 }
2865
2866 /**
2867  *  e1000_get_cfg_done_ich8lan - Read config done bit
2868  *  @hw: pointer to the HW structure
2869  *
2870  *  Read the management control register for the config done bit for
2871  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
2872  *  to read the config done bit, so an error is *ONLY* logged and returns
2873  *  0.  If we were to return with error, EEPROM-less silicon
2874  *  would not be able to be reset or change link.
2875  **/
2876 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2877 {
2878         u32 bank = 0;
2879
2880         if (hw->mac.type >= e1000_pchlan) {
2881                 u32 status = er32(STATUS);
2882
2883                 if (status & E1000_STATUS_PHYRA)
2884                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2885                 else
2886                         hw_dbg(hw,
2887                                "PHY Reset Asserted not set - needs delay\n");
2888         }
2889
2890         e1000e_get_cfg_done(hw);
2891
2892         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2893         if ((hw->mac.type != e1000_ich10lan) &&
2894             (hw->mac.type != e1000_pchlan)) {
2895                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
2896                     (hw->phy.type == e1000_phy_igp_3)) {
2897                         e1000e_phy_init_script_igp3(hw);
2898                 }
2899         } else {
2900                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2901                         /* Maybe we should do a basic PHY config */
2902                         hw_dbg(hw, "EEPROM not present\n");
2903                         return -E1000_ERR_CONFIG;
2904                 }
2905         }
2906
2907         return 0;
2908 }
2909
2910 /**
2911  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2912  *  @hw: pointer to the HW structure
2913  *
2914  *  Clears hardware counters specific to the silicon family and calls
2915  *  clear_hw_cntrs_generic to clear all general purpose counters.
2916  **/
2917 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2918 {
2919         u32 temp;
2920         u16 phy_data;
2921
2922         e1000e_clear_hw_cntrs_base(hw);
2923
2924         temp = er32(ALGNERRC);
2925         temp = er32(RXERRC);
2926         temp = er32(TNCRS);
2927         temp = er32(CEXTERR);
2928         temp = er32(TSCTC);
2929         temp = er32(TSCTFC);
2930
2931         temp = er32(MGTPRC);
2932         temp = er32(MGTPDC);
2933         temp = er32(MGTPTC);
2934
2935         temp = er32(IAC);
2936         temp = er32(ICRXOC);
2937
2938         /* Clear PHY statistics registers */
2939         if ((hw->phy.type == e1000_phy_82578) ||
2940             (hw->phy.type == e1000_phy_82577)) {
2941                 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
2942                 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
2943                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
2944                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
2945                 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
2946                 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
2947                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
2948                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
2949                 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
2950                 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
2951                 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
2952                 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
2953                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
2954                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
2955         }
2956 }
2957
2958 static struct e1000_mac_operations ich8_mac_ops = {
2959         .id_led_init            = e1000e_id_led_init,
2960         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
2961         .check_for_link         = e1000e_check_for_copper_link,
2962         /* cleanup_led dependent on mac type */
2963         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
2964         .get_bus_info           = e1000_get_bus_info_ich8lan,
2965         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
2966         /* led_on dependent on mac type */
2967         /* led_off dependent on mac type */
2968         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
2969         .reset_hw               = e1000_reset_hw_ich8lan,
2970         .init_hw                = e1000_init_hw_ich8lan,
2971         .setup_link             = e1000_setup_link_ich8lan,
2972         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2973         /* id_led_init dependent on mac type */
2974 };
2975
2976 static struct e1000_phy_operations ich8_phy_ops = {
2977         .acquire_phy            = e1000_acquire_swflag_ich8lan,
2978         .check_reset_block      = e1000_check_reset_block_ich8lan,
2979         .commit_phy             = NULL,
2980         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
2981         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
2982         .get_cable_length       = e1000e_get_cable_length_igp_2,
2983         .get_phy_info           = e1000_get_phy_info_ich8lan,
2984         .read_phy_reg           = e1000e_read_phy_reg_igp,
2985         .release_phy            = e1000_release_swflag_ich8lan,
2986         .reset_phy              = e1000_phy_hw_reset_ich8lan,
2987         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
2988         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
2989         .write_phy_reg          = e1000e_write_phy_reg_igp,
2990 };
2991
2992 static struct e1000_nvm_operations ich8_nvm_ops = {
2993         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
2994         .read_nvm               = e1000_read_nvm_ich8lan,
2995         .release_nvm            = e1000_release_swflag_ich8lan,
2996         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
2997         .valid_led_default      = e1000_valid_led_default_ich8lan,
2998         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
2999         .write_nvm              = e1000_write_nvm_ich8lan,
3000 };
3001
3002 struct e1000_info e1000_ich8_info = {
3003         .mac                    = e1000_ich8lan,
3004         .flags                  = FLAG_HAS_WOL
3005                                   | FLAG_IS_ICH
3006                                   | FLAG_RX_CSUM_ENABLED
3007                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3008                                   | FLAG_HAS_AMT
3009                                   | FLAG_HAS_FLASH
3010                                   | FLAG_APME_IN_WUC,
3011         .pba                    = 8,
3012         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3013         .get_variants           = e1000_get_variants_ich8lan,
3014         .mac_ops                = &ich8_mac_ops,
3015         .phy_ops                = &ich8_phy_ops,
3016         .nvm_ops                = &ich8_nvm_ops,
3017 };
3018
3019 struct e1000_info e1000_ich9_info = {
3020         .mac                    = e1000_ich9lan,
3021         .flags                  = FLAG_HAS_JUMBO_FRAMES
3022                                   | FLAG_IS_ICH
3023                                   | FLAG_HAS_WOL
3024                                   | FLAG_RX_CSUM_ENABLED
3025                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3026                                   | FLAG_HAS_AMT
3027                                   | FLAG_HAS_ERT
3028                                   | FLAG_HAS_FLASH
3029                                   | FLAG_APME_IN_WUC,
3030         .pba                    = 10,
3031         .max_hw_frame_size      = DEFAULT_JUMBO,
3032         .get_variants           = e1000_get_variants_ich8lan,
3033         .mac_ops                = &ich8_mac_ops,
3034         .phy_ops                = &ich8_phy_ops,
3035         .nvm_ops                = &ich8_nvm_ops,
3036 };
3037
3038 struct e1000_info e1000_ich10_info = {
3039         .mac                    = e1000_ich10lan,
3040         .flags                  = FLAG_HAS_JUMBO_FRAMES
3041                                   | FLAG_IS_ICH
3042                                   | FLAG_HAS_WOL
3043                                   | FLAG_RX_CSUM_ENABLED
3044                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3045                                   | FLAG_HAS_AMT
3046                                   | FLAG_HAS_ERT
3047                                   | FLAG_HAS_FLASH
3048                                   | FLAG_APME_IN_WUC,
3049         .pba                    = 10,
3050         .max_hw_frame_size      = DEFAULT_JUMBO,
3051         .get_variants           = e1000_get_variants_ich8lan,
3052         .mac_ops                = &ich8_mac_ops,
3053         .phy_ops                = &ich8_phy_ops,
3054         .nvm_ops                = &ich8_nvm_ops,
3055 };
3056
3057 struct e1000_info e1000_pch_info = {
3058         .mac                    = e1000_pchlan,
3059         .flags                  = FLAG_IS_ICH
3060                                   | FLAG_HAS_WOL
3061                                   | FLAG_RX_CSUM_ENABLED
3062                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3063                                   | FLAG_HAS_AMT
3064                                   | FLAG_HAS_FLASH
3065                                   | FLAG_HAS_JUMBO_FRAMES
3066                                   | FLAG_APME_IN_WUC,
3067         .pba                    = 26,
3068         .max_hw_frame_size      = 4096,
3069         .get_variants           = e1000_get_variants_ich8lan,
3070         .mac_ops                = &ich8_mac_ops,
3071         .phy_ops                = &ich8_phy_ops,
3072         .nvm_ops                = &ich8_nvm_ops,
3073 };