Pileus Git - ~andy/linux/blob - drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  */
  52
  53 #include <linux/netdevice.h>
  54 #include <linux/ethtool.h>
  55 #include <linux/delay.h>
  56 #include <linux/pci.h>
  57
  58 #include "e1000.h"
  59
  60 #define ICH_FLASH_GFPREG                0x0000
  61 #define ICH_FLASH_HSFSTS                0x0004
  62 #define ICH_FLASH_HSFCTL                0x0006
  63 #define ICH_FLASH_FADDR                 0x0008
  64 #define ICH_FLASH_FDATA0                0x0010
  65 #define ICH_FLASH_PR0                   0x0074
  66
  67 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  70 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  71 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  72
  73 #define ICH_CYCLE_READ                  0
  74 #define ICH_CYCLE_WRITE                 2
  75 #define ICH_CYCLE_ERASE                 3
  76
  77 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  78 #define FLASH_SECTOR_ADDR_SHIFT         12
  79
  80 #define ICH_FLASH_SEG_SIZE_256          256
  81 #define ICH_FLASH_SEG_SIZE_4K           4096
  82 #define ICH_FLASH_SEG_SIZE_8K           8192
  83 #define ICH_FLASH_SEG_SIZE_64K          65536
  84
  85
  86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  87
  88 #define E1000_ICH_MNG_IAMT_MODE         0x2
  89
  90 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  91                                  (ID_LED_DEF1_OFF2 <<  8) | \
  92                                  (ID_LED_DEF1_ON2  <<  4) | \
  93                                  (ID_LED_DEF1_DEF2))
  94
  95 #define E1000_ICH_NVM_SIG_WORD          0x13
  96 #define E1000_ICH_NVM_SIG_MASK          0xC000
  97 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
  98 #define E1000_ICH_NVM_SIG_VALUE         0x80
  99
 100 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 101
 102 #define E1000_FEXTNVM_SW_CONFIG         1
 103 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 104
 105 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 106
 107 #define E1000_ICH_RAR_ENTRIES           7
 108
 109 #define PHY_PAGE_SHIFT 5
 110 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 111                            ((reg) & MAX_PHY_REG_ADDRESS))
 112 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 113 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 114
 115 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 116 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 117 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 118
 119 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 120 /* Offset 04h HSFSTS */
 121 union ich8_hws_flash_status {
 122         struct ich8_hsfsts {
 123                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 124                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 125                 u16 dael       :1; /* bit 2 Direct Access error Log */
 126                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 127                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 128                 u16 reserved1  :2; /* bit 13:6 Reserved */
 129                 u16 reserved2  :6; /* bit 13:6 Reserved */
 130                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 131                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 132         } hsf_status;
 133         u16 regval;
 134 };
 135
 136 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 137 /* Offset 06h FLCTL */
 138 union ich8_hws_flash_ctrl {
 139         struct ich8_hsflctl {
 140                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 141                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 142                 u16 reserved   :5;   /* 7:3 Reserved  */
 143                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 144                 u16 flockdn    :6;   /* 15:10 Reserved */
 145         } hsf_ctrl;
 146         u16 regval;
 147 };
 148
 149 /* ICH Flash Region Access Permissions */
 150 union ich8_hws_flash_regacc {
 151         struct ich8_flracc {
 152                 u32 grra      :8; /* 0:7 GbE region Read Access */
 153                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 154                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 155                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 156         } hsf_flregacc;
 157         u16 regval;
 158 };
 159
 160 /* ICH Flash Protected Region */
 161 union ich8_flash_protected_range {
 162         struct ich8_pr {
 163                 u32 base:13;     /* 0:12 Protected Range Base */
 164                 u32 reserved1:2; /* 13:14 Reserved */
 165                 u32 rpe:1;       /* 15 Read Protection Enable */
 166                 u32 limit:13;    /* 16:28 Protected Range Limit */
 167                 u32 reserved2:2; /* 29:30 Reserved */
 168                 u32 wpe:1;       /* 31 Write Protection Enable */
 169         } range;
 170         u32 regval;
 171 };
 172
 173 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 174 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 175 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 176 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 177 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 178 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 179                                                 u32 offset, u8 byte);
 180 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 181                                          u8 *data);
 182 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 183                                          u16 *data);
 184 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 185                                          u8 size, u16 *data);
 186 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 187 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 188 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 189
 190 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 191 {
 192         return readw(hw->flash_address + reg);
 193 }
 194
 195 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 196 {
 197         return readl(hw->flash_address + reg);
 198 }
 199
 200 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 201 {
 202         writew(val, hw->flash_address + reg);
 203 }
 204
 205 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 206 {
 207         writel(val, hw->flash_address + reg);
 208 }
 209
 210 #define er16flash(reg)          __er16flash(hw, (reg))
 211 #define er32flash(reg)          __er32flash(hw, (reg))
 212 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 213 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 214
 215 /**
 216  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 217  *  @hw: pointer to the HW structure
 218  *
 219  *  Initialize family-specific PHY parameters and function pointers.
 220  **/
 221 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 222 {
 223         struct e1000_phy_info *phy = &hw->phy;
 224         s32 ret_val;
 225         u16 i = 0;
 226
 227         phy->addr                       = 1;
 228         phy->reset_delay_us             = 100;
 229
 230         /*
 231          * We may need to do this twice - once for IGP and if that fails,
 232          * we'll set BM func pointers and try again
 233          */
 234         ret_val = e1000e_determine_phy_address(hw);
 235         if (ret_val) {
 236                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 237                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 238                 ret_val = e1000e_determine_phy_address(hw);
 239                 if (ret_val)
 240                         return ret_val;
 241         }
 242
 243         phy->id = 0;
 244         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 245                (i++ < 100)) {
 246                 msleep(1);
 247                 ret_val = e1000e_get_phy_id(hw);
 248                 if (ret_val)
 249                         return ret_val;
 250         }
 251
 252         /* Verify phy id */
 253         switch (phy->id) {
 254         case IGP03E1000_E_PHY_ID:
 255                 phy->type = e1000_phy_igp_3;
 256                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 257                 break;
 258         case IFE_E_PHY_ID:
 259         case IFE_PLUS_E_PHY_ID:
 260         case IFE_C_E_PHY_ID:
 261                 phy->type = e1000_phy_ife;
 262                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 263                 break;
 264         case BME1000_E_PHY_ID:
 265                 phy->type = e1000_phy_bm;
 266                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 267                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 268                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 269                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 270                 break;
 271         default:
 272                 return -E1000_ERR_PHY;
 273                 break;
 274         }
 275
 276         return 0;
 277 }
 278
 279 /**
 280  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 281  *  @hw: pointer to the HW structure
 282  *
 283  *  Initialize family-specific NVM parameters and function
 284  *  pointers.
 285  **/
 286 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 287 {
 288         struct e1000_nvm_info *nvm = &hw->nvm;
 289         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 290         u32 gfpreg;
 291         u32 sector_base_addr;
 292         u32 sector_end_addr;
 293         u16 i;
 294
 295         /* Can't read flash registers if the register set isn't mapped. */
 296         if (!hw->flash_address) {
 297                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 298                 return -E1000_ERR_CONFIG;
 299         }
 300
 301         nvm->type = e1000_nvm_flash_sw;
 302
 303         gfpreg = er32flash(ICH_FLASH_GFPREG);
 304
 305         /*
 306          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 307          * Add 1 to sector_end_addr since this sector is included in
 308          * the overall size.
 309          */
 310         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 311         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 312
 313         /* flash_base_addr is byte-aligned */
 314         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 315
 316         /*
 317          * find total size of the NVM, then cut in half since the total
 318          * size represents two separate NVM banks.
 319          */
 320         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 321                                 << FLASH_SECTOR_ADDR_SHIFT;
 322         nvm->flash_bank_size /= 2;
 323         /* Adjust to word count */
 324         nvm->flash_bank_size /= sizeof(u16);
 325
 326         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 327
 328         /* Clear shadow ram */
 329         for (i = 0; i < nvm->word_size; i++) {
 330                 dev_spec->shadow_ram[i].modified = 0;
 331                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 332         }
 333
 334         return 0;
 335 }
 336
 337 /**
 338  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 339  *  @hw: pointer to the HW structure
 340  *
 341  *  Initialize family-specific MAC parameters and function
 342  *  pointers.
 343  **/
 344 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 345 {
 346         struct e1000_hw *hw = &adapter->hw;
 347         struct e1000_mac_info *mac = &hw->mac;
 348
 349         /* Set media type function pointer */
 350         hw->phy.media_type = e1000_media_type_copper;
 351
 352         /* Set mta register count */
 353         mac->mta_reg_count = 32;
 354         /* Set rar entry count */
 355         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 356         if (mac->type == e1000_ich8lan)
 357                 mac->rar_entry_count--;
 358         /* Set if manageability features are enabled. */
 359         mac->arc_subsystem_valid = 1;
 360
 361         /* Enable PCS Lock-loss workaround for ICH8 */
 362         if (mac->type == e1000_ich8lan)
 363                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 364
 365         return 0;
 366 }
 367
 368 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 369 {
 370         struct e1000_hw *hw = &adapter->hw;
 371         s32 rc;
 372
 373         rc = e1000_init_mac_params_ich8lan(adapter);
 374         if (rc)
 375                 return rc;
 376
 377         rc = e1000_init_nvm_params_ich8lan(hw);
 378         if (rc)
 379                 return rc;
 380
 381         rc = e1000_init_phy_params_ich8lan(hw);
 382         if (rc)
 383                 return rc;
 384
 385         if (adapter->hw.phy.type == e1000_phy_ife) {
 386                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 387                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 388         }
 389
 390         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 391             (adapter->hw.phy.type == e1000_phy_igp_3))
 392                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 393
 394         return 0;
 395 }
 396
 397 static DEFINE_MUTEX(nvm_mutex);
 398
 399 /**
 400  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 401  *  @hw: pointer to the HW structure
 402  *
 403  *  Acquires the software control flag for performing NVM and PHY
 404  *  operations.  This is a function pointer entry point only called by
 405  *  read/write routines for the PHY and NVM parts.
 406  **/
 407 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 408 {
 409         u32 extcnf_ctrl;
 410         u32 timeout = PHY_CFG_TIMEOUT;
 411
 412         might_sleep();
 413
 414         mutex_lock(&nvm_mutex);
 415
 416         while (timeout) {
 417                 extcnf_ctrl = er32(EXTCNF_CTRL);
 418                 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 419                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 420
 421                 extcnf_ctrl = er32(EXTCNF_CTRL);
 422                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 423                         break;
 424                 mdelay(1);
 425                 timeout--;
 426         }
 427
 428         if (!timeout) {
 429                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
 430                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 431                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 432                 mutex_unlock(&nvm_mutex);
 433                 return -E1000_ERR_CONFIG;
 434         }
 435
 436         return 0;
 437 }
 438
 439 /**
 440  *  e1000_release_swflag_ich8lan - Release software control flag
 441  *  @hw: pointer to the HW structure
 442  *
 443  *  Releases the software control flag for performing NVM and PHY operations.
 444  *  This is a function pointer entry point only called by read/write
 445  *  routines for the PHY and NVM parts.
 446  **/
 447 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 448 {
 449         u32 extcnf_ctrl;
 450
 451         extcnf_ctrl = er32(EXTCNF_CTRL);
 452         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 453         ew32(EXTCNF_CTRL, extcnf_ctrl);
 454
 455         mutex_unlock(&nvm_mutex);
 456 }
 457
 458 /**
 459  *  e1000_check_mng_mode_ich8lan - Checks management mode
 460  *  @hw: pointer to the HW structure
 461  *
 462  *  This checks if the adapter has manageability enabled.
 463  *  This is a function pointer entry point only called by read/write
 464  *  routines for the PHY and NVM parts.
 465  **/
 466 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 467 {
 468         u32 fwsm = er32(FWSM);
 469
 470         return (fwsm & E1000_FWSM_MODE_MASK) ==
 471                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 472 }
 473
 474 /**
 475  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 476  *  @hw: pointer to the HW structure
 477  *
 478  *  Checks if firmware is blocking the reset of the PHY.
 479  *  This is a function pointer entry point only called by
 480  *  reset routines.
 481  **/
 482 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 483 {
 484         u32 fwsm;
 485
 486         fwsm = er32(FWSM);
 487
 488         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 489 }
 490
 491 /**
 492  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 493  *  @hw: pointer to the HW structure
 494  *
 495  *  Forces the speed and duplex settings of the PHY.
 496  *  This is a function pointer entry point only called by
 497  *  PHY setup routines.
 498  **/
 499 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 500 {
 501         struct e1000_phy_info *phy = &hw->phy;
 502         s32 ret_val;
 503         u16 data;
 504         bool link;
 505
 506         if (phy->type != e1000_phy_ife) {
 507                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 508                 return ret_val;
 509         }
 510
 511         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 512         if (ret_val)
 513                 return ret_val;
 514
 515         e1000e_phy_force_speed_duplex_setup(hw, &data);
 516
 517         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 518         if (ret_val)
 519                 return ret_val;
 520
 521         /* Disable MDI-X support for 10/100 */
 522         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 523         if (ret_val)
 524                 return ret_val;
 525
 526         data &= ~IFE_PMC_AUTO_MDIX;
 527         data &= ~IFE_PMC_FORCE_MDIX;
 528
 529         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 530         if (ret_val)
 531                 return ret_val;
 532
 533         hw_dbg(hw, "IFE PMC: %X\n", data);
 534
 535         udelay(1);
 536
 537         if (phy->autoneg_wait_to_complete) {
 538                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 539
 540                 ret_val = e1000e_phy_has_link_generic(hw,
 541                                                      PHY_FORCE_LIMIT,
 542                                                      100000,
 543                                                      &link);
 544                 if (ret_val)
 545                         return ret_val;
 546
 547                 if (!link)
 548                         hw_dbg(hw, "Link taking longer than expected.\n");
 549
 550                 /* Try once more */
 551                 ret_val = e1000e_phy_has_link_generic(hw,
 552                                                      PHY_FORCE_LIMIT,
 553                                                      100000,
 554                                                      &link);
 555                 if (ret_val)
 556                         return ret_val;
 557         }
 558
 559         return 0;
 560 }
 561
 562 /**
 563  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 564  *  @hw: pointer to the HW structure
 565  *
 566  *  Resets the PHY
 567  *  This is a function pointer entry point called by drivers
 568  *  or other shared routines.
 569  **/
 570 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 571 {
 572         struct e1000_phy_info *phy = &hw->phy;
 573         u32 i;
 574         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
 575         s32 ret_val;
 576         u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 577         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 578
 579         ret_val = e1000e_phy_hw_reset_generic(hw);
 580         if (ret_val)
 581                 return ret_val;
 582
 583         /*
 584          * Initialize the PHY from the NVM on ICH platforms.  This
 585          * is needed due to an issue where the NVM configuration is
 586          * not properly autoloaded after power transitions.
 587          * Therefore, after each PHY reset, we will load the
 588          * configuration data out of the NVM manually.
 589          */
 590         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 591                 struct e1000_adapter *adapter = hw->adapter;
 592
 593                 /* Check if SW needs configure the PHY */
 594                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 595                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
 596                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 597                 else
 598                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 599
 600                 data = er32(FEXTNVM);
 601                 if (!(data & sw_cfg_mask))
 602                         return 0;
 603
 604                 /* Wait for basic configuration completes before proceeding*/
 605                 do {
 606                         data = er32(STATUS);
 607                         data &= E1000_STATUS_LAN_INIT_DONE;
 608                         udelay(100);
 609                 } while ((!data) && --loop);
 610
 611                 /*
 612                  * If basic configuration is incomplete before the above loop
 613                  * count reaches 0, loading the configuration from NVM will
 614                  * leave the PHY in a bad state possibly resulting in no link.
 615                  */
 616                 if (loop == 0) {
 617                         hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
 618                 }
 619
 620                 /* Clear the Init Done bit for the next init event */
 621                 data = er32(STATUS);
 622                 data &= ~E1000_STATUS_LAN_INIT_DONE;
 623                 ew32(STATUS, data);
 624
 625                 /*
 626                  * Make sure HW does not configure LCD from PHY
 627                  * extended configuration before SW configuration
 628                  */
 629                 data = er32(EXTCNF_CTRL);
 630                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 631                         return 0;
 632
 633                 cnf_size = er32(EXTCNF_SIZE);
 634                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 635                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 636                 if (!cnf_size)
 637                         return 0;
 638
 639                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 640                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 641
 642                 /* Configure LCD from extended configuration region. */
 643
 644                 /* cnf_base_addr is in DWORD */
 645                 word_addr = (u16)(cnf_base_addr << 1);
 646
 647                 for (i = 0; i < cnf_size; i++) {
 648                         ret_val = e1000_read_nvm(hw,
 649                                                 (word_addr + i * 2),
 650                                                 1,
 651                                                 &reg_data);
 652                         if (ret_val)
 653                                 return ret_val;
 654
 655                         ret_val = e1000_read_nvm(hw,
 656                                                 (word_addr + i * 2 + 1),
 657                                                 1,
 658                                                 &reg_addr);
 659                         if (ret_val)
 660                                 return ret_val;
 661
 662                         /* Save off the PHY page for future writes. */
 663                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 664                                 phy_page = reg_data;
 665                                 continue;
 666                         }
 667
 668                         reg_addr |= phy_page;
 669
 670                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
 671                         if (ret_val)
 672                                 return ret_val;
 673                 }
 674         }
 675
 676         return 0;
 677 }
 678
 679 /**
 680  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 681  *  @hw: pointer to the HW structure
 682  *
 683  *  Populates "phy" structure with various feature states.
 684  *  This function is only called by other family-specific
 685  *  routines.
 686  **/
 687 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 688 {
 689         struct e1000_phy_info *phy = &hw->phy;
 690         s32 ret_val;
 691         u16 data;
 692         bool link;
 693
 694         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 695         if (ret_val)
 696                 return ret_val;
 697
 698         if (!link) {
 699                 hw_dbg(hw, "Phy info is only valid if link is up\n");
 700                 return -E1000_ERR_CONFIG;
 701         }
 702
 703         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
 704         if (ret_val)
 705                 return ret_val;
 706         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
 707
 708         if (phy->polarity_correction) {
 709                 ret_val = e1000_check_polarity_ife_ich8lan(hw);
 710                 if (ret_val)
 711                         return ret_val;
 712         } else {
 713                 /* Polarity is forced */
 714                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
 715                                       ? e1000_rev_polarity_reversed
 716                                       : e1000_rev_polarity_normal;
 717         }
 718
 719         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 720         if (ret_val)
 721                 return ret_val;
 722
 723         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
 724
 725         /* The following parameters are undefined for 10/100 operation. */
 726         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 727         phy->local_rx = e1000_1000t_rx_status_undefined;
 728         phy->remote_rx = e1000_1000t_rx_status_undefined;
 729
 730         return 0;
 731 }
 732
 733 /**
 734  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
 735  *  @hw: pointer to the HW structure
 736  *
 737  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
 738  *  This is a function pointer entry point called by drivers
 739  *  or other shared routines.
 740  **/
 741 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
 742 {
 743         switch (hw->phy.type) {
 744         case e1000_phy_ife:
 745                 return e1000_get_phy_info_ife_ich8lan(hw);
 746                 break;
 747         case e1000_phy_igp_3:
 748         case e1000_phy_bm:
 749                 return e1000e_get_phy_info_igp(hw);
 750                 break;
 751         default:
 752                 break;
 753         }
 754
 755         return -E1000_ERR_PHY_TYPE;
 756 }
 757
 758 /**
 759  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
 760  *  @hw: pointer to the HW structure
 761  *
 762  *  Polarity is determined on the polarity reversal feature being enabled.
 763  *  This function is only called by other family-specific
 764  *  routines.
 765  **/
 766 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
 767 {
 768         struct e1000_phy_info *phy = &hw->phy;
 769         s32 ret_val;
 770         u16 phy_data, offset, mask;
 771
 772         /*
 773          * Polarity is determined based on the reversal feature being enabled.
 774          */
 775         if (phy->polarity_correction) {
 776                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
 777                 mask    = IFE_PESC_POLARITY_REVERSED;
 778         } else {
 779                 offset  = IFE_PHY_SPECIAL_CONTROL;
 780                 mask    = IFE_PSC_FORCE_POLARITY;
 781         }
 782
 783         ret_val = e1e_rphy(hw, offset, &phy_data);
 784
 785         if (!ret_val)
 786                 phy->cable_polarity = (phy_data & mask)
 787                                       ? e1000_rev_polarity_reversed
 788                                       : e1000_rev_polarity_normal;
 789
 790         return ret_val;
 791 }
 792
 793 /**
 794  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
 795  *  @hw: pointer to the HW structure
 796  *  @active: TRUE to enable LPLU, FALSE to disable
 797  *
 798  *  Sets the LPLU D0 state according to the active flag.  When
 799  *  activating LPLU this function also disables smart speed
 800  *  and vice versa.  LPLU will not be activated unless the
 801  *  device autonegotiation advertisement meets standards of
 802  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 803  *  This is a function pointer entry point only called by
 804  *  PHY setup routines.
 805  **/
 806 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 807 {
 808         struct e1000_phy_info *phy = &hw->phy;
 809         u32 phy_ctrl;
 810         s32 ret_val = 0;
 811         u16 data;
 812
 813         if (phy->type == e1000_phy_ife)
 814                 return ret_val;
 815
 816         phy_ctrl = er32(PHY_CTRL);
 817
 818         if (active) {
 819                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
 820                 ew32(PHY_CTRL, phy_ctrl);
 821
 822                 /*
 823                  * Call gig speed drop workaround on LPLU before accessing
 824                  * any PHY registers
 825                  */
 826                 if ((hw->mac.type == e1000_ich8lan) &&
 827                     (hw->phy.type == e1000_phy_igp_3))
 828                         e1000e_gig_downshift_workaround_ich8lan(hw);
 829
 830                 /* When LPLU is enabled, we should disable SmartSpeed */
 831                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 832                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 833                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 834                 if (ret_val)
 835                         return ret_val;
 836         } else {
 837                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
 838                 ew32(PHY_CTRL, phy_ctrl);
 839
 840                 /*
 841                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 842                  * during Dx states where the power conservation is most
 843                  * important.  During driver activity we should enable
 844                  * SmartSpeed, so performance is maintained.
 845                  */
 846                 if (phy->smart_speed == e1000_smart_speed_on) {
 847                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 848                                            &data);
 849                         if (ret_val)
 850                                 return ret_val;
 851
 852                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 853                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 854                                            data);
 855                         if (ret_val)
 856                                 return ret_val;
 857                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 858                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 859                                            &data);
 860                         if (ret_val)
 861                                 return ret_val;
 862
 863                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 864                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 865                                            data);
 866                         if (ret_val)
 867                                 return ret_val;
 868                 }
 869         }
 870
 871         return 0;
 872 }
 873
 874 /**
 875  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
 876  *  @hw: pointer to the HW structure
 877  *  @active: TRUE to enable LPLU, FALSE to disable
 878  *
 879  *  Sets the LPLU D3 state according to the active flag.  When
 880  *  activating LPLU this function also disables smart speed
 881  *  and vice versa.  LPLU will not be activated unless the
 882  *  device autonegotiation advertisement meets standards of
 883  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 884  *  This is a function pointer entry point only called by
 885  *  PHY setup routines.
 886  **/
 887 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 888 {
 889         struct e1000_phy_info *phy = &hw->phy;
 890         u32 phy_ctrl;
 891         s32 ret_val;
 892         u16 data;
 893
 894         phy_ctrl = er32(PHY_CTRL);
 895
 896         if (!active) {
 897                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 898                 ew32(PHY_CTRL, phy_ctrl);
 899                 /*
 900                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 901                  * during Dx states where the power conservation is most
 902                  * important.  During driver activity we should enable
 903                  * SmartSpeed, so performance is maintained.
 904                  */
 905                 if (phy->smart_speed == e1000_smart_speed_on) {
 906                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 907                                            &data);
 908                         if (ret_val)
 909                                 return ret_val;
 910
 911                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 912                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 913                                            data);
 914                         if (ret_val)
 915                                 return ret_val;
 916                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 917                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 918                                            &data);
 919                         if (ret_val)
 920                                 return ret_val;
 921
 922                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 923                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 924                                            data);
 925                         if (ret_val)
 926                                 return ret_val;
 927                 }
 928         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 929                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 930                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 931                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
 932                 ew32(PHY_CTRL, phy_ctrl);
 933
 934                 /*
 935                  * Call gig speed drop workaround on LPLU before accessing
 936                  * any PHY registers
 937                  */
 938                 if ((hw->mac.type == e1000_ich8lan) &&
 939                     (hw->phy.type == e1000_phy_igp_3))
 940                         e1000e_gig_downshift_workaround_ich8lan(hw);
 941
 942                 /* When LPLU is enabled, we should disable SmartSpeed */
 943                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 944                 if (ret_val)
 945                         return ret_val;
 946
 947                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 948                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 949         }
 950
 951         return 0;
 952 }
 953
 954 /**
 955  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
 956  *  @hw: pointer to the HW structure
 957  *  @bank:  pointer to the variable that returns the active bank
 958  *
 959  *  Reads signature byte from the NVM using the flash access registers.
 960  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
 961  **/
 962 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 963 {
 964         u32 eecd;
 965         struct e1000_nvm_info *nvm = &hw->nvm;
 966         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
 967         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
 968         u8 sig_byte = 0;
 969         s32 ret_val = 0;
 970
 971         switch (hw->mac.type) {
 972         case e1000_ich8lan:
 973         case e1000_ich9lan:
 974                 eecd = er32(EECD);
 975                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
 976                     E1000_EECD_SEC1VAL_VALID_MASK) {
 977                         if (eecd & E1000_EECD_SEC1VAL)
 978                                 *bank = 1;
 979                         else
 980                                 *bank = 0;
 981
 982                         return 0;
 983                 }
 984                 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
 985                        "reading flash signature\n");
 986                 /* fall-thru */
 987         default:
 988                 /* set bank to 0 in case flash read fails */
 989                 *bank = 0;
 990
 991                 /* Check bank 0 */
 992                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
 993                                                         &sig_byte);
 994                 if (ret_val)
 995                         return ret_val;
 996                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
 997                     E1000_ICH_NVM_SIG_VALUE) {
 998                         *bank = 0;
 999                         return 0;
1000                 }
1001
1002                 /* Check bank 1 */
1003                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1004                                                         bank1_offset,
1005                                                         &sig_byte);
1006                 if (ret_val)
1007                         return ret_val;
1008                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1009                     E1000_ICH_NVM_SIG_VALUE) {
1010                         *bank = 1;
1011                         return 0;
1012                 }
1013
1014                 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1015                 return -E1000_ERR_NVM;
1016         }
1017
1018         return 0;
1019 }
1020
1021 /**
1022  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1023  *  @hw: pointer to the HW structure
1024  *  @offset: The offset (in bytes) of the word(s) to read.
1025  *  @words: Size of data to read in words
1026  *  @data: Pointer to the word(s) to read at offset.
1027  *
1028  *  Reads a word(s) from the NVM using the flash access registers.
1029  **/
1030 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1031                                   u16 *data)
1032 {
1033         struct e1000_nvm_info *nvm = &hw->nvm;
1034         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1035         u32 act_offset;
1036         s32 ret_val;
1037         u32 bank = 0;
1038         u16 i, word;
1039
1040         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1041             (words == 0)) {
1042                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1043                 return -E1000_ERR_NVM;
1044         }
1045
1046         ret_val = e1000_acquire_swflag_ich8lan(hw);
1047         if (ret_val)
1048                 goto out;
1049
1050         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1051         if (ret_val)
1052                 goto release;
1053
1054         act_offset = (bank) ? nvm->flash_bank_size : 0;
1055         act_offset += offset;
1056
1057         for (i = 0; i < words; i++) {
1058                 if ((dev_spec->shadow_ram) &&
1059                     (dev_spec->shadow_ram[offset+i].modified)) {
1060                         data[i] = dev_spec->shadow_ram[offset+i].value;
1061                 } else {
1062                         ret_val = e1000_read_flash_word_ich8lan(hw,
1063                                                                 act_offset + i,
1064                                                                 &word);
1065                         if (ret_val)
1066                                 break;
1067                         data[i] = word;
1068                 }
1069         }
1070
1071 release:
1072         e1000_release_swflag_ich8lan(hw);
1073
1074 out:
1075         if (ret_val)
1076                 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1077
1078         return ret_val;
1079 }
1080
1081 /**
1082  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1083  *  @hw: pointer to the HW structure
1084  *
1085  *  This function does initial flash setup so that a new read/write/erase cycle
1086  *  can be started.
1087  **/
1088 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1089 {
1090         union ich8_hws_flash_status hsfsts;
1091         s32 ret_val = -E1000_ERR_NVM;
1092         s32 i = 0;
1093
1094         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1095
1096         /* Check if the flash descriptor is valid */
1097         if (hsfsts.hsf_status.fldesvalid == 0) {
1098                 hw_dbg(hw, "Flash descriptor invalid.  "
1099                          "SW Sequencing must be used.");
1100                 return -E1000_ERR_NVM;
1101         }
1102
1103         /* Clear FCERR and DAEL in hw status by writing 1 */
1104         hsfsts.hsf_status.flcerr = 1;
1105         hsfsts.hsf_status.dael = 1;
1106
1107         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1108
1109         /*
1110          * Either we should have a hardware SPI cycle in progress
1111          * bit to check against, in order to start a new cycle or
1112          * FDONE bit should be changed in the hardware so that it
1113          * is 1 after hardware reset, which can then be used as an
1114          * indication whether a cycle is in progress or has been
1115          * completed.
1116          */
1117
1118         if (hsfsts.hsf_status.flcinprog == 0) {
1119                 /*
1120                  * There is no cycle running at present,
1121                  * so we can start a cycle
1122                  * Begin by setting Flash Cycle Done.
1123                  */
1124                 hsfsts.hsf_status.flcdone = 1;
1125                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1126                 ret_val = 0;
1127         } else {
1128                 /*
1129                  * otherwise poll for sometime so the current
1130                  * cycle has a chance to end before giving up.
1131                  */
1132                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1133                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1134                         if (hsfsts.hsf_status.flcinprog == 0) {
1135                                 ret_val = 0;
1136                                 break;
1137                         }
1138                         udelay(1);
1139                 }
1140                 if (ret_val == 0) {
1141                         /*
1142                          * Successful in waiting for previous cycle to timeout,
1143                          * now set the Flash Cycle Done.
1144                          */
1145                         hsfsts.hsf_status.flcdone = 1;
1146                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1147                 } else {
1148                         hw_dbg(hw, "Flash controller busy, cannot get access");
1149                 }
1150         }
1151
1152         return ret_val;
1153 }
1154
1155 /**
1156  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1157  *  @hw: pointer to the HW structure
1158  *  @timeout: maximum time to wait for completion
1159  *
1160  *  This function starts a flash cycle and waits for its completion.
1161  **/
1162 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1163 {
1164         union ich8_hws_flash_ctrl hsflctl;
1165         union ich8_hws_flash_status hsfsts;
1166         s32 ret_val = -E1000_ERR_NVM;
1167         u32 i = 0;
1168
1169         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1170         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1171         hsflctl.hsf_ctrl.flcgo = 1;
1172         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1173
1174         /* wait till FDONE bit is set to 1 */
1175         do {
1176                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1177                 if (hsfsts.hsf_status.flcdone == 1)
1178                         break;
1179                 udelay(1);
1180         } while (i++ < timeout);
1181
1182         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1183                 return 0;
1184
1185         return ret_val;
1186 }
1187
1188 /**
1189  *  e1000_read_flash_word_ich8lan - Read word from flash
1190  *  @hw: pointer to the HW structure
1191  *  @offset: offset to data location
1192  *  @data: pointer to the location for storing the data
1193  *
1194  *  Reads the flash word at offset into data.  Offset is converted
1195  *  to bytes before read.
1196  **/
1197 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1198                                          u16 *data)
1199 {
1200         /* Must convert offset into bytes. */
1201         offset <<= 1;
1202
1203         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1204 }
1205
1206 /**
1207  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1208  *  @hw: pointer to the HW structure
1209  *  @offset: The offset of the byte to read.
1210  *  @data: Pointer to a byte to store the value read.
1211  *
1212  *  Reads a single byte from the NVM using the flash access registers.
1213  **/
1214 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1215                                          u8 *data)
1216 {
1217         s32 ret_val;
1218         u16 word = 0;
1219
1220         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1221         if (ret_val)
1222                 return ret_val;
1223
1224         *data = (u8)word;
1225
1226         return 0;
1227 }
1228
1229 /**
1230  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1231  *  @hw: pointer to the HW structure
1232  *  @offset: The offset (in bytes) of the byte or word to read.
1233  *  @size: Size of data to read, 1=byte 2=word
1234  *  @data: Pointer to the word to store the value read.
1235  *
1236  *  Reads a byte or word from the NVM using the flash access registers.
1237  **/
1238 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1239                                          u8 size, u16 *data)
1240 {
1241         union ich8_hws_flash_status hsfsts;
1242         union ich8_hws_flash_ctrl hsflctl;
1243         u32 flash_linear_addr;
1244         u32 flash_data = 0;
1245         s32 ret_val = -E1000_ERR_NVM;
1246         u8 count = 0;
1247
1248         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1249                 return -E1000_ERR_NVM;
1250
1251         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1252                             hw->nvm.flash_base_addr;
1253
1254         do {
1255                 udelay(1);
1256                 /* Steps */
1257                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1258                 if (ret_val != 0)
1259                         break;
1260
1261                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1262                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1263                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1264                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1265                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1266
1267                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1268
1269                 ret_val = e1000_flash_cycle_ich8lan(hw,
1270                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1271
1272                 /*
1273                  * Check if FCERR is set to 1, if set to 1, clear it
1274                  * and try the whole sequence a few more times, else
1275                  * read in (shift in) the Flash Data0, the order is
1276                  * least significant byte first msb to lsb
1277                  */
1278                 if (ret_val == 0) {
1279                         flash_data = er32flash(ICH_FLASH_FDATA0);
1280                         if (size == 1) {
1281                                 *data = (u8)(flash_data & 0x000000FF);
1282                         } else if (size == 2) {
1283                                 *data = (u16)(flash_data & 0x0000FFFF);
1284                         }
1285                         break;
1286                 } else {
1287                         /*
1288                          * If we've gotten here, then things are probably
1289                          * completely hosed, but if the error condition is
1290                          * detected, it won't hurt to give it another try...
1291                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1292                          */
1293                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1294                         if (hsfsts.hsf_status.flcerr == 1) {
1295                                 /* Repeat for some time before giving up. */
1296                                 continue;
1297                         } else if (hsfsts.hsf_status.flcdone == 0) {
1298                                 hw_dbg(hw, "Timeout error - flash cycle "
1299                                          "did not complete.");
1300                                 break;
1301                         }
1302                 }
1303         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1304
1305         return ret_val;
1306 }
1307
1308 /**
1309  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1310  *  @hw: pointer to the HW structure
1311  *  @offset: The offset (in bytes) of the word(s) to write.
1312  *  @words: Size of data to write in words
1313  *  @data: Pointer to the word(s) to write at offset.
1314  *
1315  *  Writes a byte or word to the NVM using the flash access registers.
1316  **/
1317 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1318                                    u16 *data)
1319 {
1320         struct e1000_nvm_info *nvm = &hw->nvm;
1321         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1322         s32 ret_val;
1323         u16 i;
1324
1325         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1326             (words == 0)) {
1327                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1328                 return -E1000_ERR_NVM;
1329         }
1330
1331         ret_val = e1000_acquire_swflag_ich8lan(hw);
1332         if (ret_val)
1333                 return ret_val;
1334
1335         for (i = 0; i < words; i++) {
1336                 dev_spec->shadow_ram[offset+i].modified = 1;
1337                 dev_spec->shadow_ram[offset+i].value = data[i];
1338         }
1339
1340         e1000_release_swflag_ich8lan(hw);
1341
1342         return 0;
1343 }
1344
1345 /**
1346  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1347  *  @hw: pointer to the HW structure
1348  *
1349  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1350  *  which writes the checksum to the shadow ram.  The changes in the shadow
1351  *  ram are then committed to the EEPROM by processing each bank at a time
1352  *  checking for the modified bit and writing only the pending changes.
1353  *  After a successful commit, the shadow ram is cleared and is ready for
1354  *  future writes.
1355  **/
1356 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1357 {
1358         struct e1000_nvm_info *nvm = &hw->nvm;
1359         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1360         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1361         s32 ret_val;
1362         u16 data;
1363
1364         ret_val = e1000e_update_nvm_checksum_generic(hw);
1365         if (ret_val)
1366                 goto out;
1367
1368         if (nvm->type != e1000_nvm_flash_sw)
1369                 goto out;
1370
1371         ret_val = e1000_acquire_swflag_ich8lan(hw);
1372         if (ret_val)
1373                 goto out;
1374
1375         /*
1376          * We're writing to the opposite bank so if we're on bank 1,
1377          * write to bank 0 etc.  We also need to erase the segment that
1378          * is going to be written
1379          */
1380         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1381         if (ret_val) {
1382                 e1000_release_swflag_ich8lan(hw);
1383                 goto out;
1384         }
1385
1386         if (bank == 0) {
1387                 new_bank_offset = nvm->flash_bank_size;
1388                 old_bank_offset = 0;
1389                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1390                 if (ret_val) {
1391                         e1000_release_swflag_ich8lan(hw);
1392                         goto out;
1393                 }
1394         } else {
1395                 old_bank_offset = nvm->flash_bank_size;
1396                 new_bank_offset = 0;
1397                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1398                 if (ret_val) {
1399                         e1000_release_swflag_ich8lan(hw);
1400                         goto out;
1401                 }
1402         }
1403
1404         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1405                 /*
1406                  * Determine whether to write the value stored
1407                  * in the other NVM bank or a modified value stored
1408                  * in the shadow RAM
1409                  */
1410                 if (dev_spec->shadow_ram[i].modified) {
1411                         data = dev_spec->shadow_ram[i].value;
1412                 } else {
1413                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
1414                                                                 old_bank_offset,
1415                                                                 &data);
1416                         if (ret_val)
1417                                 break;
1418                 }
1419
1420                 /*
1421                  * If the word is 0x13, then make sure the signature bits
1422                  * (15:14) are 11b until the commit has completed.
1423                  * This will allow us to write 10b which indicates the
1424                  * signature is valid.  We want to do this after the write
1425                  * has completed so that we don't mark the segment valid
1426                  * while the write is still in progress
1427                  */
1428                 if (i == E1000_ICH_NVM_SIG_WORD)
1429                         data |= E1000_ICH_NVM_SIG_MASK;
1430
1431                 /* Convert offset to bytes. */
1432                 act_offset = (i + new_bank_offset) << 1;
1433
1434                 udelay(100);
1435                 /* Write the bytes to the new bank. */
1436                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1437                                                                act_offset,
1438                                                                (u8)data);
1439                 if (ret_val)
1440                         break;
1441
1442                 udelay(100);
1443                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1444                                                           act_offset + 1,
1445                                                           (u8)(data >> 8));
1446                 if (ret_val)
1447                         break;
1448         }
1449
1450         /*
1451          * Don't bother writing the segment valid bits if sector
1452          * programming failed.
1453          */
1454         if (ret_val) {
1455                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1456                 hw_dbg(hw, "Flash commit failed.\n");
1457                 e1000_release_swflag_ich8lan(hw);
1458                 goto out;
1459         }
1460
1461         /*
1462          * Finally validate the new segment by setting bit 15:14
1463          * to 10b in word 0x13 , this can be done without an
1464          * erase as well since these bits are 11 to start with
1465          * and we need to change bit 14 to 0b
1466          */
1467         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1468         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1469         if (ret_val) {
1470                 e1000_release_swflag_ich8lan(hw);
1471                 goto out;
1472         }
1473         data &= 0xBFFF;
1474         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1475                                                        act_offset * 2 + 1,
1476                                                        (u8)(data >> 8));
1477         if (ret_val) {
1478                 e1000_release_swflag_ich8lan(hw);
1479                 goto out;
1480         }
1481
1482         /*
1483          * And invalidate the previously valid segment by setting
1484          * its signature word (0x13) high_byte to 0b. This can be
1485          * done without an erase because flash erase sets all bits
1486          * to 1's. We can write 1's to 0's without an erase
1487          */
1488         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1489         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1490         if (ret_val) {
1491                 e1000_release_swflag_ich8lan(hw);
1492                 goto out;
1493         }
1494
1495         /* Great!  Everything worked, we can now clear the cached entries. */
1496         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1497                 dev_spec->shadow_ram[i].modified = 0;
1498                 dev_spec->shadow_ram[i].value = 0xFFFF;
1499         }
1500
1501         e1000_release_swflag_ich8lan(hw);
1502
1503         /*
1504          * Reload the EEPROM, or else modifications will not appear
1505          * until after the next adapter reset.
1506          */
1507         e1000e_reload_nvm(hw);
1508         msleep(10);
1509
1510 out:
1511         if (ret_val)
1512                 hw_dbg(hw, "NVM update error: %d\n", ret_val);
1513
1514         return ret_val;
1515 }
1516
1517 /**
1518  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1519  *  @hw: pointer to the HW structure
1520  *
1521  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1522  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1523  *  calculated, in which case we need to calculate the checksum and set bit 6.
1524  **/
1525 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1526 {
1527         s32 ret_val;
1528         u16 data;
1529
1530         /*
1531          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1532          * needs to be fixed.  This bit is an indication that the NVM
1533          * was prepared by OEM software and did not calculate the
1534          * checksum...a likely scenario.
1535          */
1536         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1537         if (ret_val)
1538                 return ret_val;
1539
1540         if ((data & 0x40) == 0) {
1541                 data |= 0x40;
1542                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1543                 if (ret_val)
1544                         return ret_val;
1545                 ret_val = e1000e_update_nvm_checksum(hw);
1546                 if (ret_val)
1547                         return ret_val;
1548         }
1549
1550         return e1000e_validate_nvm_checksum_generic(hw);
1551 }
1552
1553 /**
1554  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1555  *  @hw: pointer to the HW structure
1556  *
1557  *  To prevent malicious write/erase of the NVM, set it to be read-only
1558  *  so that the hardware ignores all write/erase cycles of the NVM via
1559  *  the flash control registers.  The shadow-ram copy of the NVM will
1560  *  still be updated, however any updates to this copy will not stick
1561  *  across driver reloads.
1562  **/
1563 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1564 {
1565         union ich8_flash_protected_range pr0;
1566         union ich8_hws_flash_status hsfsts;
1567         u32 gfpreg;
1568         s32 ret_val;
1569
1570         ret_val = e1000_acquire_swflag_ich8lan(hw);
1571         if (ret_val)
1572                 return;
1573
1574         gfpreg = er32flash(ICH_FLASH_GFPREG);
1575
1576         /* Write-protect GbE Sector of NVM */
1577         pr0.regval = er32flash(ICH_FLASH_PR0);
1578         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1579         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1580         pr0.range.wpe = true;
1581         ew32flash(ICH_FLASH_PR0, pr0.regval);
1582
1583         /*
1584          * Lock down a subset of GbE Flash Control Registers, e.g.
1585          * PR0 to prevent the write-protection from being lifted.
1586          * Once FLOCKDN is set, the registers protected by it cannot
1587          * be written until FLOCKDN is cleared by a hardware reset.
1588          */
1589         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1590         hsfsts.hsf_status.flockdn = true;
1591         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1592
1593         e1000_release_swflag_ich8lan(hw);
1594 }
1595
1596 /**
1597  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1598  *  @hw: pointer to the HW structure
1599  *  @offset: The offset (in bytes) of the byte/word to read.
1600  *  @size: Size of data to read, 1=byte 2=word
1601  *  @data: The byte(s) to write to the NVM.
1602  *
1603  *  Writes one/two bytes to the NVM using the flash access registers.
1604  **/
1605 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1606                                           u8 size, u16 data)
1607 {
1608         union ich8_hws_flash_status hsfsts;
1609         union ich8_hws_flash_ctrl hsflctl;
1610         u32 flash_linear_addr;
1611         u32 flash_data = 0;
1612         s32 ret_val;
1613         u8 count = 0;
1614
1615         if (size < 1 || size > 2 || data > size * 0xff ||
1616             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1617                 return -E1000_ERR_NVM;
1618
1619         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1620                             hw->nvm.flash_base_addr;
1621
1622         do {
1623                 udelay(1);
1624                 /* Steps */
1625                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1626                 if (ret_val)
1627                         break;
1628
1629                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1630                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1631                 hsflctl.hsf_ctrl.fldbcount = size -1;
1632                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1633                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1634
1635                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1636
1637                 if (size == 1)
1638                         flash_data = (u32)data & 0x00FF;
1639                 else
1640                         flash_data = (u32)data;
1641
1642                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1643
1644                 /*
1645                  * check if FCERR is set to 1 , if set to 1, clear it
1646                  * and try the whole sequence a few more times else done
1647                  */
1648                 ret_val = e1000_flash_cycle_ich8lan(hw,
1649                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1650                 if (!ret_val)
1651                         break;
1652
1653                 /*
1654                  * If we're here, then things are most likely
1655                  * completely hosed, but if the error condition
1656                  * is detected, it won't hurt to give it another
1657                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1658                  */
1659                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1660                 if (hsfsts.hsf_status.flcerr == 1)
1661                         /* Repeat for some time before giving up. */
1662                         continue;
1663                 if (hsfsts.hsf_status.flcdone == 0) {
1664                         hw_dbg(hw, "Timeout error - flash cycle "
1665                                  "did not complete.");
1666                         break;
1667                 }
1668         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1669
1670         return ret_val;
1671 }
1672
1673 /**
1674  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1675  *  @hw: pointer to the HW structure
1676  *  @offset: The index of the byte to read.
1677  *  @data: The byte to write to the NVM.
1678  *
1679  *  Writes a single byte to the NVM using the flash access registers.
1680  **/
1681 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1682                                           u8 data)
1683 {
1684         u16 word = (u16)data;
1685
1686         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1687 }
1688
1689 /**
1690  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1691  *  @hw: pointer to the HW structure
1692  *  @offset: The offset of the byte to write.
1693  *  @byte: The byte to write to the NVM.
1694  *
1695  *  Writes a single byte to the NVM using the flash access registers.
1696  *  Goes through a retry algorithm before giving up.
1697  **/
1698 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1699                                                 u32 offset, u8 byte)
1700 {
1701         s32 ret_val;
1702         u16 program_retries;
1703
1704         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1705         if (!ret_val)
1706                 return ret_val;
1707
1708         for (program_retries = 0; program_retries < 100; program_retries++) {
1709                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1710                 udelay(100);
1711                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1712                 if (!ret_val)
1713                         break;
1714         }
1715         if (program_retries == 100)
1716                 return -E1000_ERR_NVM;
1717
1718         return 0;
1719 }
1720
1721 /**
1722  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1723  *  @hw: pointer to the HW structure
1724  *  @bank: 0 for first bank, 1 for second bank, etc.
1725  *
1726  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1727  *  bank N is 4096 * N + flash_reg_addr.
1728  **/
1729 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1730 {
1731         struct e1000_nvm_info *nvm = &hw->nvm;
1732         union ich8_hws_flash_status hsfsts;
1733         union ich8_hws_flash_ctrl hsflctl;
1734         u32 flash_linear_addr;
1735         /* bank size is in 16bit words - adjust to bytes */
1736         u32 flash_bank_size = nvm->flash_bank_size * 2;
1737         s32 ret_val;
1738         s32 count = 0;
1739         s32 iteration;
1740         s32 sector_size;
1741         s32 j;
1742
1743         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1744
1745         /*
1746          * Determine HW Sector size: Read BERASE bits of hw flash status
1747          * register
1748          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1749          *     consecutive sectors.  The start index for the nth Hw sector
1750          *     can be calculated as = bank * 4096 + n * 256
1751          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1752          *     The start index for the nth Hw sector can be calculated
1753          *     as = bank * 4096
1754          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1755          *     (ich9 only, otherwise error condition)
1756          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1757          */
1758         switch (hsfsts.hsf_status.berasesz) {
1759         case 0:
1760                 /* Hw sector size 256 */
1761                 sector_size = ICH_FLASH_SEG_SIZE_256;
1762                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1763                 break;
1764         case 1:
1765                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1766                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1767                 break;
1768         case 2:
1769                 if (hw->mac.type == e1000_ich9lan) {
1770                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1771                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1772                 } else {
1773                         return -E1000_ERR_NVM;
1774                 }
1775                 break;
1776         case 3:
1777                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1778                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1779                 break;
1780         default:
1781                 return -E1000_ERR_NVM;
1782         }
1783
1784         /* Start with the base address, then add the sector offset. */
1785         flash_linear_addr = hw->nvm.flash_base_addr;
1786         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1787
1788         for (j = 0; j < iteration ; j++) {
1789                 do {
1790                         /* Steps */
1791                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1792                         if (ret_val)
1793                                 return ret_val;
1794
1795                         /*
1796                          * Write a value 11 (block Erase) in Flash
1797                          * Cycle field in hw flash control
1798                          */
1799                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1800                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1801                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1802
1803                         /*
1804                          * Write the last 24 bits of an index within the
1805                          * block into Flash Linear address field in Flash
1806                          * Address.
1807                          */
1808                         flash_linear_addr += (j * sector_size);
1809                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1810
1811                         ret_val = e1000_flash_cycle_ich8lan(hw,
1812                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1813                         if (ret_val == 0)
1814                                 break;
1815
1816                         /*
1817                          * Check if FCERR is set to 1.  If 1,
1818                          * clear it and try the whole sequence
1819                          * a few more times else Done
1820                          */
1821                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1822                         if (hsfsts.hsf_status.flcerr == 1)
1823                                 /* repeat for some time before giving up */
1824                                 continue;
1825                         else if (hsfsts.hsf_status.flcdone == 0)
1826                                 return ret_val;
1827                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1828         }
1829
1830         return 0;
1831 }
1832
1833 /**
1834  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1835  *  @hw: pointer to the HW structure
1836  *  @data: Pointer to the LED settings
1837  *
1838  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1839  *  settings is all 0's or F's, set the LED default to a valid LED default
1840  *  setting.
1841  **/
1842 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1843 {
1844         s32 ret_val;
1845
1846         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1847         if (ret_val) {
1848                 hw_dbg(hw, "NVM Read Error\n");
1849                 return ret_val;
1850         }
1851
1852         if (*data == ID_LED_RESERVED_0000 ||
1853             *data == ID_LED_RESERVED_FFFF)
1854                 *data = ID_LED_DEFAULT_ICH8LAN;
1855
1856         return 0;
1857 }
1858
1859 /**
1860  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1861  *  @hw: pointer to the HW structure
1862  *
1863  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1864  *  register, so the the bus width is hard coded.
1865  **/
1866 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1867 {
1868         struct e1000_bus_info *bus = &hw->bus;
1869         s32 ret_val;
1870
1871         ret_val = e1000e_get_bus_info_pcie(hw);
1872
1873         /*
1874          * ICH devices are "PCI Express"-ish.  They have
1875          * a configuration space, but do not contain
1876          * PCI Express Capability registers, so bus width
1877          * must be hardcoded.
1878          */
1879         if (bus->width == e1000_bus_width_unknown)
1880                 bus->width = e1000_bus_width_pcie_x1;
1881
1882         return ret_val;
1883 }
1884
1885 /**
1886  *  e1000_reset_hw_ich8lan - Reset the hardware
1887  *  @hw: pointer to the HW structure
1888  *
1889  *  Does a full reset of the hardware which includes a reset of the PHY and
1890  *  MAC.
1891  **/
1892 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1893 {
1894         u32 ctrl, icr, kab;
1895         s32 ret_val;
1896
1897         /*
1898          * Prevent the PCI-E bus from sticking if there is no TLP connection
1899          * on the last TLP read/write transaction when MAC is reset.
1900          */
1901         ret_val = e1000e_disable_pcie_master(hw);
1902         if (ret_val) {
1903                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1904         }
1905
1906         hw_dbg(hw, "Masking off all interrupts\n");
1907         ew32(IMC, 0xffffffff);
1908
1909         /*
1910          * Disable the Transmit and Receive units.  Then delay to allow
1911          * any pending transactions to complete before we hit the MAC
1912          * with the global reset.
1913          */
1914         ew32(RCTL, 0);
1915         ew32(TCTL, E1000_TCTL_PSP);
1916         e1e_flush();
1917
1918         msleep(10);
1919
1920         /* Workaround for ICH8 bit corruption issue in FIFO memory */
1921         if (hw->mac.type == e1000_ich8lan) {
1922                 /* Set Tx and Rx buffer allocation to 8k apiece. */
1923                 ew32(PBA, E1000_PBA_8K);
1924                 /* Set Packet Buffer Size to 16k. */
1925                 ew32(PBS, E1000_PBS_16K);
1926         }
1927
1928         ctrl = er32(CTRL);
1929
1930         if (!e1000_check_reset_block(hw)) {
1931                 /*
1932                  * PHY HW reset requires MAC CORE reset at the same
1933                  * time to make sure the interface between MAC and the
1934                  * external PHY is reset.
1935                  */
1936                 ctrl |= E1000_CTRL_PHY_RST;
1937         }
1938         ret_val = e1000_acquire_swflag_ich8lan(hw);
1939         /* Whether or not the swflag was acquired, we need to reset the part */
1940         hw_dbg(hw, "Issuing a global reset to ich8lan\n");
1941         ew32(CTRL, (ctrl | E1000_CTRL_RST));
1942         msleep(20);
1943
1944         if (!ret_val) {
1945                 /* release the swflag because it is not reset by
1946                  * hardware reset
1947                  */
1948                 e1000_release_swflag_ich8lan(hw);
1949         }
1950
1951         ret_val = e1000e_get_auto_rd_done(hw);
1952         if (ret_val) {
1953                 /*
1954                  * When auto config read does not complete, do not
1955                  * return with an error. This can happen in situations
1956                  * where there is no eeprom and prevents getting link.
1957                  */
1958                 hw_dbg(hw, "Auto Read Done did not complete\n");
1959         }
1960
1961         ew32(IMC, 0xffffffff);
1962         icr = er32(ICR);
1963
1964         kab = er32(KABGTXD);
1965         kab |= E1000_KABGTXD_BGSQLBIAS;
1966         ew32(KABGTXD, kab);
1967
1968         return ret_val;
1969 }
1970
1971 /**
1972  *  e1000_init_hw_ich8lan - Initialize the hardware
1973  *  @hw: pointer to the HW structure
1974  *
1975  *  Prepares the hardware for transmit and receive by doing the following:
1976  *   - initialize hardware bits
1977  *   - initialize LED identification
1978  *   - setup receive address registers
1979  *   - setup flow control
1980  *   - setup transmit descriptors
1981  *   - clear statistics
1982  **/
1983 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1984 {
1985         struct e1000_mac_info *mac = &hw->mac;
1986         u32 ctrl_ext, txdctl, snoop;
1987         s32 ret_val;
1988         u16 i;
1989
1990         e1000_initialize_hw_bits_ich8lan(hw);
1991
1992         /* Initialize identification LED */
1993         ret_val = e1000e_id_led_init(hw);
1994         if (ret_val) {
1995                 hw_dbg(hw, "Error initializing identification LED\n");
1996                 return ret_val;
1997         }
1998
1999         /* Setup the receive address. */
2000         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2001
2002         /* Zero out the Multicast HASH table */
2003         hw_dbg(hw, "Zeroing the MTA\n");
2004         for (i = 0; i < mac->mta_reg_count; i++)
2005                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2006
2007         /* Setup link and flow control */
2008         ret_val = e1000_setup_link_ich8lan(hw);
2009
2010         /* Set the transmit descriptor write-back policy for both queues */
2011         txdctl = er32(TXDCTL(0));
2012         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2013                  E1000_TXDCTL_FULL_TX_DESC_WB;
2014         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2015                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2016         ew32(TXDCTL(0), txdctl);
2017         txdctl = er32(TXDCTL(1));
2018         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2019                  E1000_TXDCTL_FULL_TX_DESC_WB;
2020         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2021                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2022         ew32(TXDCTL(1), txdctl);
2023
2024         /*
2025          * ICH8 has opposite polarity of no_snoop bits.
2026          * By default, we should use snoop behavior.
2027          */
2028         if (mac->type == e1000_ich8lan)
2029                 snoop = PCIE_ICH8_SNOOP_ALL;
2030         else
2031                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2032         e1000e_set_pcie_no_snoop(hw, snoop);
2033
2034         ctrl_ext = er32(CTRL_EXT);
2035         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2036         ew32(CTRL_EXT, ctrl_ext);
2037
2038         /*
2039          * Clear all of the statistics registers (clear on read).  It is
2040          * important that we do this after we have tried to establish link
2041          * because the symbol error count will increment wildly if there
2042          * is no link.
2043          */
2044         e1000_clear_hw_cntrs_ich8lan(hw);
2045
2046         return 0;
2047 }
2048 /**
2049  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2050  *  @hw: pointer to the HW structure
2051  *
2052  *  Sets/Clears required hardware bits necessary for correctly setting up the
2053  *  hardware for transmit and receive.
2054  **/
2055 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2056 {
2057         u32 reg;
2058
2059         /* Extended Device Control */
2060         reg = er32(CTRL_EXT);
2061         reg |= (1 << 22);
2062         ew32(CTRL_EXT, reg);
2063
2064         /* Transmit Descriptor Control 0 */
2065         reg = er32(TXDCTL(0));
2066         reg |= (1 << 22);
2067         ew32(TXDCTL(0), reg);
2068
2069         /* Transmit Descriptor Control 1 */
2070         reg = er32(TXDCTL(1));
2071         reg |= (1 << 22);
2072         ew32(TXDCTL(1), reg);
2073
2074         /* Transmit Arbitration Control 0 */
2075         reg = er32(TARC(0));
2076         if (hw->mac.type == e1000_ich8lan)
2077                 reg |= (1 << 28) | (1 << 29);
2078         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2079         ew32(TARC(0), reg);
2080
2081         /* Transmit Arbitration Control 1 */
2082         reg = er32(TARC(1));
2083         if (er32(TCTL) & E1000_TCTL_MULR)
2084                 reg &= ~(1 << 28);
2085         else
2086                 reg |= (1 << 28);
2087         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2088         ew32(TARC(1), reg);
2089
2090         /* Device Status */
2091         if (hw->mac.type == e1000_ich8lan) {
2092                 reg = er32(STATUS);
2093                 reg &= ~(1 << 31);
2094                 ew32(STATUS, reg);
2095         }
2096 }
2097
2098 /**
2099  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2100  *  @hw: pointer to the HW structure
2101  *
2102  *  Determines which flow control settings to use, then configures flow
2103  *  control.  Calls the appropriate media-specific link configuration
2104  *  function.  Assuming the adapter has a valid link partner, a valid link
2105  *  should be established.  Assumes the hardware has previously been reset
2106  *  and the transmitter and receiver are not enabled.
2107  **/
2108 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2109 {
2110         s32 ret_val;
2111
2112         if (e1000_check_reset_block(hw))
2113                 return 0;
2114
2115         /*
2116          * ICH parts do not have a word in the NVM to determine
2117          * the default flow control setting, so we explicitly
2118          * set it to full.
2119          */
2120         if (hw->fc.requested_mode == e1000_fc_default)
2121                 hw->fc.requested_mode = e1000_fc_full;
2122
2123         /*
2124          * Save off the requested flow control mode for use later.  Depending
2125          * on the link partner's capabilities, we may or may not use this mode.
2126          */
2127         hw->fc.current_mode = hw->fc.requested_mode;
2128
2129         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2130                 hw->fc.current_mode);
2131
2132         /* Continue to configure the copper link. */
2133         ret_val = e1000_setup_copper_link_ich8lan(hw);
2134         if (ret_val)
2135                 return ret_val;
2136
2137         ew32(FCTTV, hw->fc.pause_time);
2138
2139         return e1000e_set_fc_watermarks(hw);
2140 }
2141
2142 /**
2143  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2144  *  @hw: pointer to the HW structure
2145  *
2146  *  Configures the kumeran interface to the PHY to wait the appropriate time
2147  *  when polling the PHY, then call the generic setup_copper_link to finish
2148  *  configuring the copper link.
2149  **/
2150 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2151 {
2152         u32 ctrl;
2153         s32 ret_val;
2154         u16 reg_data;
2155
2156         ctrl = er32(CTRL);
2157         ctrl |= E1000_CTRL_SLU;
2158         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2159         ew32(CTRL, ctrl);
2160
2161         /*
2162          * Set the mac to wait the maximum time between each iteration
2163          * and increase the max iterations when polling the phy;
2164          * this fixes erroneous timeouts at 10Mbps.
2165          */
2166         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2167         if (ret_val)
2168                 return ret_val;
2169         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2170         if (ret_val)
2171                 return ret_val;
2172         reg_data |= 0x3F;
2173         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2174         if (ret_val)
2175                 return ret_val;
2176
2177         if (hw->phy.type == e1000_phy_igp_3) {
2178                 ret_val = e1000e_copper_link_setup_igp(hw);
2179                 if (ret_val)
2180                         return ret_val;
2181         } else if (hw->phy.type == e1000_phy_bm) {
2182                 ret_val = e1000e_copper_link_setup_m88(hw);
2183                 if (ret_val)
2184                         return ret_val;
2185         }
2186
2187         if (hw->phy.type == e1000_phy_ife) {
2188                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
2189                 if (ret_val)
2190                         return ret_val;
2191
2192                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2193
2194                 switch (hw->phy.mdix) {
2195                 case 1:
2196                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2197                         break;
2198                 case 2:
2199                         reg_data |= IFE_PMC_FORCE_MDIX;
2200                         break;
2201                 case 0:
2202                 default:
2203                         reg_data |= IFE_PMC_AUTO_MDIX;
2204                         break;
2205                 }
2206                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2207                 if (ret_val)
2208                         return ret_val;
2209         }
2210         return e1000e_setup_copper_link(hw);
2211 }
2212
2213 /**
2214  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2215  *  @hw: pointer to the HW structure
2216  *  @speed: pointer to store current link speed
2217  *  @duplex: pointer to store the current link duplex
2218  *
2219  *  Calls the generic get_speed_and_duplex to retrieve the current link
2220  *  information and then calls the Kumeran lock loss workaround for links at
2221  *  gigabit speeds.
2222  **/
2223 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2224                                           u16 *duplex)
2225 {
2226         s32 ret_val;
2227
2228         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2229         if (ret_val)
2230                 return ret_val;
2231
2232         if ((hw->mac.type == e1000_ich8lan) &&
2233             (hw->phy.type == e1000_phy_igp_3) &&
2234             (*speed == SPEED_1000)) {
2235                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2236         }
2237
2238         return ret_val;
2239 }
2240
2241 /**
2242  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2243  *  @hw: pointer to the HW structure
2244  *
2245  *  Work-around for 82566 Kumeran PCS lock loss:
2246  *  On link status change (i.e. PCI reset, speed change) and link is up and
2247  *  speed is gigabit-
2248  *    0) if workaround is optionally disabled do nothing
2249  *    1) wait 1ms for Kumeran link to come up
2250  *    2) check Kumeran Diagnostic register PCS lock loss bit
2251  *    3) if not set the link is locked (all is good), otherwise...
2252  *    4) reset the PHY
2253  *    5) repeat up to 10 times
2254  *  Note: this is only called for IGP3 copper when speed is 1gb.
2255  **/
2256 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2257 {
2258         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2259         u32 phy_ctrl;
2260         s32 ret_val;
2261         u16 i, data;
2262         bool link;
2263
2264         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2265                 return 0;
2266
2267         /*
2268          * Make sure link is up before proceeding.  If not just return.
2269          * Attempting this while link is negotiating fouled up link
2270          * stability
2271          */
2272         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2273         if (!link)
2274                 return 0;
2275
2276         for (i = 0; i < 10; i++) {
2277                 /* read once to clear */
2278                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2279                 if (ret_val)
2280                         return ret_val;
2281                 /* and again to get new status */
2282                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2283                 if (ret_val)
2284                         return ret_val;
2285
2286                 /* check for PCS lock */
2287                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2288                         return 0;
2289
2290                 /* Issue PHY reset */
2291                 e1000_phy_hw_reset(hw);
2292                 mdelay(5);
2293         }
2294         /* Disable GigE link negotiation */
2295         phy_ctrl = er32(PHY_CTRL);
2296         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2297                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2298         ew32(PHY_CTRL, phy_ctrl);
2299
2300         /*
2301          * Call gig speed drop workaround on Gig disable before accessing
2302          * any PHY registers
2303          */
2304         e1000e_gig_downshift_workaround_ich8lan(hw);
2305
2306         /* unable to acquire PCS lock */
2307         return -E1000_ERR_PHY;
2308 }
2309
2310 /**
2311  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2312  *  @hw: pointer to the HW structure
2313  *  @state: boolean value used to set the current Kumeran workaround state
2314  *
2315  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2316  *  /disabled - FALSE).
2317  **/
2318 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2319                                                  bool state)
2320 {
2321         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2322
2323         if (hw->mac.type != e1000_ich8lan) {
2324                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2325                 return;
2326         }
2327
2328         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2329 }
2330
2331 /**
2332  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2333  *  @hw: pointer to the HW structure
2334  *
2335  *  Workaround for 82566 power-down on D3 entry:
2336  *    1) disable gigabit link
2337  *    2) write VR power-down enable
2338  *    3) read it back
2339  *  Continue if successful, else issue LCD reset and repeat
2340  **/
2341 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2342 {
2343         u32 reg;
2344         u16 data;
2345         u8  retry = 0;
2346
2347         if (hw->phy.type != e1000_phy_igp_3)
2348                 return;
2349
2350         /* Try the workaround twice (if needed) */
2351         do {
2352                 /* Disable link */
2353                 reg = er32(PHY_CTRL);
2354                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2355                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2356                 ew32(PHY_CTRL, reg);
2357
2358                 /*
2359                  * Call gig speed drop workaround on Gig disable before
2360                  * accessing any PHY registers
2361                  */
2362                 if (hw->mac.type == e1000_ich8lan)
2363                         e1000e_gig_downshift_workaround_ich8lan(hw);
2364
2365                 /* Write VR power-down enable */
2366                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2367                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2368                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2369
2370                 /* Read it back and test */
2371                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2372                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2373                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2374                         break;
2375
2376                 /* Issue PHY reset and repeat at most one more time */
2377                 reg = er32(CTRL);
2378                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2379                 retry++;
2380         } while (retry);
2381 }
2382
2383 /**
2384  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2385  *  @hw: pointer to the HW structure
2386  *
2387  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2388  *  LPLU, Gig disable, MDIC PHY reset):
2389  *    1) Set Kumeran Near-end loopback
2390  *    2) Clear Kumeran Near-end loopback
2391  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2392  **/
2393 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2394 {
2395         s32 ret_val;
2396         u16 reg_data;
2397
2398         if ((hw->mac.type != e1000_ich8lan) ||
2399             (hw->phy.type != e1000_phy_igp_3))
2400                 return;
2401
2402         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2403                                       &reg_data);
2404         if (ret_val)
2405                 return;
2406         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2407         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2408                                        reg_data);
2409         if (ret_val)
2410                 return;
2411         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2412         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2413                                        reg_data);
2414 }
2415
2416 /**
2417  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2418  *  @hw: pointer to the HW structure
2419  *
2420  *  During S0 to Sx transition, it is possible the link remains at gig
2421  *  instead of negotiating to a lower speed.  Before going to Sx, set
2422  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2423  *  to a lower speed.
2424  *
2425  *  Should only be called for ICH9 and ICH10 devices.
2426  **/
2427 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2428 {
2429         u32 phy_ctrl;
2430
2431         if ((hw->mac.type == e1000_ich10lan) ||
2432             (hw->mac.type == e1000_ich9lan)) {
2433                 phy_ctrl = er32(PHY_CTRL);
2434                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2435                             E1000_PHY_CTRL_GBE_DISABLE;
2436                 ew32(PHY_CTRL, phy_ctrl);
2437         }
2438
2439         return;
2440 }
2441
2442 /**
2443  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2444  *  @hw: pointer to the HW structure
2445  *
2446  *  Return the LED back to the default configuration.
2447  **/
2448 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2449 {
2450         if (hw->phy.type == e1000_phy_ife)
2451                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2452
2453         ew32(LEDCTL, hw->mac.ledctl_default);
2454         return 0;
2455 }
2456
2457 /**
2458  *  e1000_led_on_ich8lan - Turn LEDs on
2459  *  @hw: pointer to the HW structure
2460  *
2461  *  Turn on the LEDs.
2462  **/
2463 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2464 {
2465         if (hw->phy.type == e1000_phy_ife)
2466                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2467                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2468
2469         ew32(LEDCTL, hw->mac.ledctl_mode2);
2470         return 0;
2471 }
2472
2473 /**
2474  *  e1000_led_off_ich8lan - Turn LEDs off
2475  *  @hw: pointer to the HW structure
2476  *
2477  *  Turn off the LEDs.
2478  **/
2479 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2480 {
2481         if (hw->phy.type == e1000_phy_ife)
2482                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2483                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2484
2485         ew32(LEDCTL, hw->mac.ledctl_mode1);
2486         return 0;
2487 }
2488
2489 /**
2490  *  e1000_get_cfg_done_ich8lan - Read config done bit
2491  *  @hw: pointer to the HW structure
2492  *
2493  *  Read the management control register for the config done bit for
2494  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
2495  *  to read the config done bit, so an error is *ONLY* logged and returns
2496  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
2497  *  would not be able to be reset or change link.
2498  **/
2499 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2500 {
2501         u32 bank = 0;
2502
2503         e1000e_get_cfg_done(hw);
2504
2505         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2506         if (hw->mac.type != e1000_ich10lan) {
2507                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
2508                     (hw->phy.type == e1000_phy_igp_3)) {
2509                         e1000e_phy_init_script_igp3(hw);
2510                 }
2511         } else {
2512                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2513                         /* Maybe we should do a basic PHY config */
2514                         hw_dbg(hw, "EEPROM not present\n");
2515                         return -E1000_ERR_CONFIG;
2516                 }
2517         }
2518
2519         return 0;
2520 }
2521
2522 /**
2523  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2524  *  @hw: pointer to the HW structure
2525  *
2526  *  Clears hardware counters specific to the silicon family and calls
2527  *  clear_hw_cntrs_generic to clear all general purpose counters.
2528  **/
2529 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2530 {
2531         u32 temp;
2532
2533         e1000e_clear_hw_cntrs_base(hw);
2534
2535         temp = er32(ALGNERRC);
2536         temp = er32(RXERRC);
2537         temp = er32(TNCRS);
2538         temp = er32(CEXTERR);
2539         temp = er32(TSCTC);
2540         temp = er32(TSCTFC);
2541
2542         temp = er32(MGTPRC);
2543         temp = er32(MGTPDC);
2544         temp = er32(MGTPTC);
2545
2546         temp = er32(IAC);
2547         temp = er32(ICRXOC);
2548
2549 }
2550
2551 static struct e1000_mac_operations ich8_mac_ops = {
2552         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
2553         .check_for_link         = e1000e_check_for_copper_link,
2554         .cleanup_led            = e1000_cleanup_led_ich8lan,
2555         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
2556         .get_bus_info           = e1000_get_bus_info_ich8lan,
2557         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
2558         .led_on                 = e1000_led_on_ich8lan,
2559         .led_off                = e1000_led_off_ich8lan,
2560         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
2561         .reset_hw               = e1000_reset_hw_ich8lan,
2562         .init_hw                = e1000_init_hw_ich8lan,
2563         .setup_link             = e1000_setup_link_ich8lan,
2564         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2565 };
2566
2567 static struct e1000_phy_operations ich8_phy_ops = {
2568         .acquire_phy            = e1000_acquire_swflag_ich8lan,
2569         .check_reset_block      = e1000_check_reset_block_ich8lan,
2570         .commit_phy             = NULL,
2571         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
2572         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
2573         .get_cable_length       = e1000e_get_cable_length_igp_2,
2574         .get_phy_info           = e1000_get_phy_info_ich8lan,
2575         .read_phy_reg           = e1000e_read_phy_reg_igp,
2576         .release_phy            = e1000_release_swflag_ich8lan,
2577         .reset_phy              = e1000_phy_hw_reset_ich8lan,
2578         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
2579         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
2580         .write_phy_reg          = e1000e_write_phy_reg_igp,
2581 };
2582
2583 static struct e1000_nvm_operations ich8_nvm_ops = {
2584         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
2585         .read_nvm               = e1000_read_nvm_ich8lan,
2586         .release_nvm            = e1000_release_swflag_ich8lan,
2587         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
2588         .valid_led_default      = e1000_valid_led_default_ich8lan,
2589         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
2590         .write_nvm              = e1000_write_nvm_ich8lan,
2591 };
2592
2593 struct e1000_info e1000_ich8_info = {
2594         .mac                    = e1000_ich8lan,
2595         .flags                  = FLAG_HAS_WOL
2596                                   | FLAG_IS_ICH
2597                                   | FLAG_RX_CSUM_ENABLED
2598                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2599                                   | FLAG_HAS_AMT
2600                                   | FLAG_HAS_FLASH
2601                                   | FLAG_APME_IN_WUC,
2602         .pba                    = 8,
2603         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
2604         .get_variants           = e1000_get_variants_ich8lan,
2605         .mac_ops                = &ich8_mac_ops,
2606         .phy_ops                = &ich8_phy_ops,
2607         .nvm_ops                = &ich8_nvm_ops,
2608 };
2609
2610 struct e1000_info e1000_ich9_info = {
2611         .mac                    = e1000_ich9lan,
2612         .flags                  = FLAG_HAS_JUMBO_FRAMES
2613                                   | FLAG_IS_ICH
2614                                   | FLAG_HAS_WOL
2615                                   | FLAG_RX_CSUM_ENABLED
2616                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2617                                   | FLAG_HAS_AMT
2618                                   | FLAG_HAS_ERT
2619                                   | FLAG_HAS_FLASH
2620                                   | FLAG_APME_IN_WUC,
2621         .pba                    = 10,
2622         .max_hw_frame_size      = DEFAULT_JUMBO,
2623         .get_variants           = e1000_get_variants_ich8lan,
2624         .mac_ops                = &ich8_mac_ops,
2625         .phy_ops                = &ich8_phy_ops,
2626         .nvm_ops                = &ich8_nvm_ops,
2627 };
2628
2629 struct e1000_info e1000_ich10_info = {
2630         .mac                    = e1000_ich10lan,
2631         .flags                  = FLAG_HAS_JUMBO_FRAMES
2632                                   | FLAG_IS_ICH
2633                                   | FLAG_HAS_WOL
2634                                   | FLAG_RX_CSUM_ENABLED
2635                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2636                                   | FLAG_HAS_AMT
2637                                   | FLAG_HAS_ERT
2638                                   | FLAG_HAS_FLASH
2639                                   | FLAG_APME_IN_WUC,
2640         .pba                    = 10,
2641         .max_hw_frame_size      = DEFAULT_JUMBO,
2642         .get_variants           = e1000_get_variants_ich8lan,
2643         .mac_ops                = &ich8_mac_ops,
2644         .phy_ops                = &ich8_phy_ops,
2645         .nvm_ops                = &ich8_nvm_ops,
2646 };