Pileus Git - ~andy/linux/blob - drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  */
  56
  57 #include "e1000.h"
  58
  59 #define ICH_FLASH_GFPREG                0x0000
  60 #define ICH_FLASH_HSFSTS                0x0004
  61 #define ICH_FLASH_HSFCTL                0x0006
  62 #define ICH_FLASH_FADDR                 0x0008
  63 #define ICH_FLASH_FDATA0                0x0010
  64 #define ICH_FLASH_PR0                   0x0074
  65
  66 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  69 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  70 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  71
  72 #define ICH_CYCLE_READ                  0
  73 #define ICH_CYCLE_WRITE                 2
  74 #define ICH_CYCLE_ERASE                 3
  75
  76 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  77 #define FLASH_SECTOR_ADDR_SHIFT         12
  78
  79 #define ICH_FLASH_SEG_SIZE_256          256
  80 #define ICH_FLASH_SEG_SIZE_4K           4096
  81 #define ICH_FLASH_SEG_SIZE_8K           8192
  82 #define ICH_FLASH_SEG_SIZE_64K          65536
  83
  84
  85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  86
  87 #define E1000_ICH_MNG_IAMT_MODE         0x2
  88
  89 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  90                                  (ID_LED_DEF1_OFF2 <<  8) | \
  91                                  (ID_LED_DEF1_ON2  <<  4) | \
  92                                  (ID_LED_DEF1_DEF2))
  93
  94 #define E1000_ICH_NVM_SIG_WORD          0x13
  95 #define E1000_ICH_NVM_SIG_MASK          0xC000
  96 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
  97 #define E1000_ICH_NVM_SIG_VALUE         0x80
  98
  99 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 100
 101 #define E1000_FEXTNVM_SW_CONFIG         1
 102 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 103
 104 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 105
 106 #define E1000_ICH_RAR_ENTRIES           7
 107
 108 #define PHY_PAGE_SHIFT 5
 109 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 110                            ((reg) & MAX_PHY_REG_ADDRESS))
 111 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 112 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 113
 114 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 115 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 116 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 117
 118 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 119
 120 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 121
 122 /* SMBus Address Phy Register */
 123 #define HV_SMB_ADDR            PHY_REG(768, 26)
 124 #define HV_SMB_ADDR_PEC_EN     0x0200
 125 #define HV_SMB_ADDR_VALID      0x0080
 126
 127 /* Strapping Option Register - RO */
 128 #define E1000_STRAP                     0x0000C
 129 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 130 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 131
 132 /* OEM Bits Phy Register */
 133 #define HV_OEM_BITS            PHY_REG(768, 25)
 134 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 135 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 136 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 137
 138 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 139 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 140
 141 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 142 /* Offset 04h HSFSTS */
 143 union ich8_hws_flash_status {
 144         struct ich8_hsfsts {
 145                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 146                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 147                 u16 dael       :1; /* bit 2 Direct Access error Log */
 148                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 149                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 150                 u16 reserved1  :2; /* bit 13:6 Reserved */
 151                 u16 reserved2  :6; /* bit 13:6 Reserved */
 152                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 153                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 154         } hsf_status;
 155         u16 regval;
 156 };
 157
 158 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 159 /* Offset 06h FLCTL */
 160 union ich8_hws_flash_ctrl {
 161         struct ich8_hsflctl {
 162                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 163                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 164                 u16 reserved   :5;   /* 7:3 Reserved  */
 165                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 166                 u16 flockdn    :6;   /* 15:10 Reserved */
 167         } hsf_ctrl;
 168         u16 regval;
 169 };
 170
 171 /* ICH Flash Region Access Permissions */
 172 union ich8_hws_flash_regacc {
 173         struct ich8_flracc {
 174                 u32 grra      :8; /* 0:7 GbE region Read Access */
 175                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 176                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 177                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 178         } hsf_flregacc;
 179         u16 regval;
 180 };
 181
 182 /* ICH Flash Protected Region */
 183 union ich8_flash_protected_range {
 184         struct ich8_pr {
 185                 u32 base:13;     /* 0:12 Protected Range Base */
 186                 u32 reserved1:2; /* 13:14 Reserved */
 187                 u32 rpe:1;       /* 15 Read Protection Enable */
 188                 u32 limit:13;    /* 16:28 Protected Range Limit */
 189                 u32 reserved2:2; /* 29:30 Reserved */
 190                 u32 wpe:1;       /* 31 Write Protection Enable */
 191         } range;
 192         u32 regval;
 193 };
 194
 195 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 196 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 197 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 198 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 199 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 200 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 201                                                 u32 offset, u8 byte);
 202 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 203                                          u8 *data);
 204 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 205                                          u16 *data);
 206 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 207                                          u8 size, u16 *data);
 208 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 209 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 210 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 211 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 212 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 213 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 214 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 215 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 216 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 217 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 218 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 219 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 220 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 221 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 222
 223 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 224 {
 225         return readw(hw->flash_address + reg);
 226 }
 227
 228 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 229 {
 230         return readl(hw->flash_address + reg);
 231 }
 232
 233 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 234 {
 235         writew(val, hw->flash_address + reg);
 236 }
 237
 238 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 239 {
 240         writel(val, hw->flash_address + reg);
 241 }
 242
 243 #define er16flash(reg)          __er16flash(hw, (reg))
 244 #define er32flash(reg)          __er32flash(hw, (reg))
 245 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 246 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 247
 248 /**
 249  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 250  *  @hw: pointer to the HW structure
 251  *
 252  *  Initialize family-specific PHY parameters and function pointers.
 253  **/
 254 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 255 {
 256         struct e1000_phy_info *phy = &hw->phy;
 257         s32 ret_val = 0;
 258
 259         phy->addr                     = 1;
 260         phy->reset_delay_us           = 100;
 261
 262         phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;
 263         phy->ops.read_phy_reg         = e1000_read_phy_reg_hv;
 264         phy->ops.read_phy_reg_locked  = e1000_read_phy_reg_hv_locked;
 265         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 266         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 267         phy->ops.write_phy_reg        = e1000_write_phy_reg_hv;
 268         phy->ops.write_phy_reg_locked = e1000_write_phy_reg_hv_locked;
 269         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 270
 271         phy->id = e1000_phy_unknown;
 272         e1000e_get_phy_id(hw);
 273         phy->type = e1000e_get_phy_type_from_id(phy->id);
 274
 275         if (phy->type == e1000_phy_82577) {
 276                 phy->ops.check_polarity = e1000_check_polarity_82577;
 277                 phy->ops.force_speed_duplex =
 278                         e1000_phy_force_speed_duplex_82577;
 279                 phy->ops.get_cable_length   = e1000_get_cable_length_82577;
 280                 phy->ops.get_phy_info = e1000_get_phy_info_82577;
 281                 phy->ops.commit_phy = e1000e_phy_sw_reset;
 282         }
 283
 284         return ret_val;
 285 }
 286
 287 /**
 288  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 289  *  @hw: pointer to the HW structure
 290  *
 291  *  Initialize family-specific PHY parameters and function pointers.
 292  **/
 293 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 294 {
 295         struct e1000_phy_info *phy = &hw->phy;
 296         s32 ret_val;
 297         u16 i = 0;
 298
 299         phy->addr                       = 1;
 300         phy->reset_delay_us             = 100;
 301
 302         /*
 303          * We may need to do this twice - once for IGP and if that fails,
 304          * we'll set BM func pointers and try again
 305          */
 306         ret_val = e1000e_determine_phy_address(hw);
 307         if (ret_val) {
 308                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 309                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 310                 ret_val = e1000e_determine_phy_address(hw);
 311                 if (ret_val)
 312                         return ret_val;
 313         }
 314
 315         phy->id = 0;
 316         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 317                (i++ < 100)) {
 318                 msleep(1);
 319                 ret_val = e1000e_get_phy_id(hw);
 320                 if (ret_val)
 321                         return ret_val;
 322         }
 323
 324         /* Verify phy id */
 325         switch (phy->id) {
 326         case IGP03E1000_E_PHY_ID:
 327                 phy->type = e1000_phy_igp_3;
 328                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 329                 phy->ops.read_phy_reg_locked = e1000e_read_phy_reg_igp_locked;
 330                 phy->ops.write_phy_reg_locked = e1000e_write_phy_reg_igp_locked;
 331                 break;
 332         case IFE_E_PHY_ID:
 333         case IFE_PLUS_E_PHY_ID:
 334         case IFE_C_E_PHY_ID:
 335                 phy->type = e1000_phy_ife;
 336                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 337                 break;
 338         case BME1000_E_PHY_ID:
 339                 phy->type = e1000_phy_bm;
 340                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 341                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 342                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 343                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 344                 break;
 345         default:
 346                 return -E1000_ERR_PHY;
 347                 break;
 348         }
 349
 350         phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
 351
 352         return 0;
 353 }
 354
 355 /**
 356  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 357  *  @hw: pointer to the HW structure
 358  *
 359  *  Initialize family-specific NVM parameters and function
 360  *  pointers.
 361  **/
 362 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 363 {
 364         struct e1000_nvm_info *nvm = &hw->nvm;
 365         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 366         u32 gfpreg, sector_base_addr, sector_end_addr;
 367         u16 i;
 368
 369         /* Can't read flash registers if the register set isn't mapped. */
 370         if (!hw->flash_address) {
 371                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 372                 return -E1000_ERR_CONFIG;
 373         }
 374
 375         nvm->type = e1000_nvm_flash_sw;
 376
 377         gfpreg = er32flash(ICH_FLASH_GFPREG);
 378
 379         /*
 380          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 381          * Add 1 to sector_end_addr since this sector is included in
 382          * the overall size.
 383          */
 384         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 385         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 386
 387         /* flash_base_addr is byte-aligned */
 388         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 389
 390         /*
 391          * find total size of the NVM, then cut in half since the total
 392          * size represents two separate NVM banks.
 393          */
 394         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 395                                 << FLASH_SECTOR_ADDR_SHIFT;
 396         nvm->flash_bank_size /= 2;
 397         /* Adjust to word count */
 398         nvm->flash_bank_size /= sizeof(u16);
 399
 400         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 401
 402         /* Clear shadow ram */
 403         for (i = 0; i < nvm->word_size; i++) {
 404                 dev_spec->shadow_ram[i].modified = 0;
 405                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 406         }
 407
 408         return 0;
 409 }
 410
 411 /**
 412  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 413  *  @hw: pointer to the HW structure
 414  *
 415  *  Initialize family-specific MAC parameters and function
 416  *  pointers.
 417  **/
 418 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 419 {
 420         struct e1000_hw *hw = &adapter->hw;
 421         struct e1000_mac_info *mac = &hw->mac;
 422
 423         /* Set media type function pointer */
 424         hw->phy.media_type = e1000_media_type_copper;
 425
 426         /* Set mta register count */
 427         mac->mta_reg_count = 32;
 428         /* Set rar entry count */
 429         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 430         if (mac->type == e1000_ich8lan)
 431                 mac->rar_entry_count--;
 432         /* Set if manageability features are enabled. */
 433         mac->arc_subsystem_valid = 1;
 434
 435         /* LED operations */
 436         switch (mac->type) {
 437         case e1000_ich8lan:
 438         case e1000_ich9lan:
 439         case e1000_ich10lan:
 440                 /* ID LED init */
 441                 mac->ops.id_led_init = e1000e_id_led_init;
 442                 /* setup LED */
 443                 mac->ops.setup_led = e1000e_setup_led_generic;
 444                 /* cleanup LED */
 445                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 446                 /* turn on/off LED */
 447                 mac->ops.led_on = e1000_led_on_ich8lan;
 448                 mac->ops.led_off = e1000_led_off_ich8lan;
 449                 break;
 450         case e1000_pchlan:
 451                 /* ID LED init */
 452                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 453                 /* setup LED */
 454                 mac->ops.setup_led = e1000_setup_led_pchlan;
 455                 /* cleanup LED */
 456                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 457                 /* turn on/off LED */
 458                 mac->ops.led_on = e1000_led_on_pchlan;
 459                 mac->ops.led_off = e1000_led_off_pchlan;
 460                 break;
 461         default:
 462                 break;
 463         }
 464
 465         /* Enable PCS Lock-loss workaround for ICH8 */
 466         if (mac->type == e1000_ich8lan)
 467                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 468
 469         return 0;
 470 }
 471
 472 /**
 473  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 474  *  @hw: pointer to the HW structure
 475  *
 476  *  Checks to see of the link status of the hardware has changed.  If a
 477  *  change in link status has been detected, then we read the PHY registers
 478  *  to get the current speed/duplex if link exists.
 479  **/
 480 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 481 {
 482         struct e1000_mac_info *mac = &hw->mac;
 483         s32 ret_val;
 484         bool link;
 485
 486         /*
 487          * We only want to go out to the PHY registers to see if Auto-Neg
 488          * has completed and/or if our link status has changed.  The
 489          * get_link_status flag is set upon receiving a Link Status
 490          * Change or Rx Sequence Error interrupt.
 491          */
 492         if (!mac->get_link_status) {
 493                 ret_val = 0;
 494                 goto out;
 495         }
 496
 497         /*
 498          * First we want to see if the MII Status Register reports
 499          * link.  If so, then we want to get the current speed/duplex
 500          * of the PHY.
 501          */
 502         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 503         if (ret_val)
 504                 goto out;
 505
 506         if (hw->mac.type == e1000_pchlan) {
 507                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 508                 if (ret_val)
 509                         goto out;
 510         }
 511
 512         if (!link)
 513                 goto out; /* No link detected */
 514
 515         mac->get_link_status = false;
 516
 517         if (hw->phy.type == e1000_phy_82578) {
 518                 ret_val = e1000_link_stall_workaround_hv(hw);
 519                 if (ret_val)
 520                         goto out;
 521         }
 522
 523         /*
 524          * Check if there was DownShift, must be checked
 525          * immediately after link-up
 526          */
 527         e1000e_check_downshift(hw);
 528
 529         /*
 530          * If we are forcing speed/duplex, then we simply return since
 531          * we have already determined whether we have link or not.
 532          */
 533         if (!mac->autoneg) {
 534                 ret_val = -E1000_ERR_CONFIG;
 535                 goto out;
 536         }
 537
 538         /*
 539          * Auto-Neg is enabled.  Auto Speed Detection takes care
 540          * of MAC speed/duplex configuration.  So we only need to
 541          * configure Collision Distance in the MAC.
 542          */
 543         e1000e_config_collision_dist(hw);
 544
 545         /*
 546          * Configure Flow Control now that Auto-Neg has completed.
 547          * First, we need to restore the desired flow control
 548          * settings because we may have had to re-autoneg with a
 549          * different link partner.
 550          */
 551         ret_val = e1000e_config_fc_after_link_up(hw);
 552         if (ret_val)
 553                 hw_dbg(hw, "Error configuring flow control\n");
 554
 555 out:
 556         return ret_val;
 557 }
 558
 559 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 560 {
 561         struct e1000_hw *hw = &adapter->hw;
 562         s32 rc;
 563
 564         rc = e1000_init_mac_params_ich8lan(adapter);
 565         if (rc)
 566                 return rc;
 567
 568         rc = e1000_init_nvm_params_ich8lan(hw);
 569         if (rc)
 570                 return rc;
 571
 572         if (hw->mac.type == e1000_pchlan)
 573                 rc = e1000_init_phy_params_pchlan(hw);
 574         else
 575                 rc = e1000_init_phy_params_ich8lan(hw);
 576         if (rc)
 577                 return rc;
 578
 579         if (adapter->hw.phy.type == e1000_phy_ife) {
 580                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 581                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 582         }
 583
 584         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 585             (adapter->hw.phy.type == e1000_phy_igp_3))
 586                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 587
 588         return 0;
 589 }
 590
 591 static DEFINE_MUTEX(nvm_mutex);
 592
 593 /**
 594  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 595  *  @hw: pointer to the HW structure
 596  *
 597  *  Acquires the mutex for performing NVM operations.
 598  **/
 599 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 600 {
 601         mutex_lock(&nvm_mutex);
 602
 603         return 0;
 604 }
 605
 606 /**
 607  *  e1000_release_nvm_ich8lan - Release NVM mutex
 608  *  @hw: pointer to the HW structure
 609  *
 610  *  Releases the mutex used while performing NVM operations.
 611  **/
 612 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 613 {
 614         mutex_unlock(&nvm_mutex);
 615
 616         return;
 617 }
 618
 619 static DEFINE_MUTEX(swflag_mutex);
 620
 621 /**
 622  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 623  *  @hw: pointer to the HW structure
 624  *
 625  *  Acquires the software control flag for performing PHY and select
 626  *  MAC CSR accesses.
 627  **/
 628 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 629 {
 630         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 631         s32 ret_val = 0;
 632
 633         might_sleep();
 634
 635         mutex_lock(&swflag_mutex);
 636
 637         while (timeout) {
 638                 extcnf_ctrl = er32(EXTCNF_CTRL);
 639                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 640                         break;
 641
 642                 mdelay(1);
 643                 timeout--;
 644         }
 645
 646         if (!timeout) {
 647                 hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n");
 648                 ret_val = -E1000_ERR_CONFIG;
 649                 goto out;
 650         }
 651
 652         timeout = SW_FLAG_TIMEOUT;
 653
 654         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 655         ew32(EXTCNF_CTRL, extcnf_ctrl);
 656
 657         while (timeout) {
 658                 extcnf_ctrl = er32(EXTCNF_CTRL);
 659                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 660                         break;
 661
 662                 mdelay(1);
 663                 timeout--;
 664         }
 665
 666         if (!timeout) {
 667                 hw_dbg(hw, "Failed to acquire the semaphore.\n");
 668                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 669                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 670                 ret_val = -E1000_ERR_CONFIG;
 671                 goto out;
 672         }
 673
 674 out:
 675         if (ret_val)
 676                 mutex_unlock(&swflag_mutex);
 677
 678         return ret_val;
 679 }
 680
 681 /**
 682  *  e1000_release_swflag_ich8lan - Release software control flag
 683  *  @hw: pointer to the HW structure
 684  *
 685  *  Releases the software control flag for performing PHY and select
 686  *  MAC CSR accesses.
 687  **/
 688 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 689 {
 690         u32 extcnf_ctrl;
 691
 692         extcnf_ctrl = er32(EXTCNF_CTRL);
 693         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 694         ew32(EXTCNF_CTRL, extcnf_ctrl);
 695
 696         mutex_unlock(&swflag_mutex);
 697
 698         return;
 699 }
 700
 701 /**
 702  *  e1000_check_mng_mode_ich8lan - Checks management mode
 703  *  @hw: pointer to the HW structure
 704  *
 705  *  This checks if the adapter has manageability enabled.
 706  *  This is a function pointer entry point only called by read/write
 707  *  routines for the PHY and NVM parts.
 708  **/
 709 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 710 {
 711         u32 fwsm = er32(FWSM);
 712
 713         return (fwsm & E1000_FWSM_MODE_MASK) ==
 714                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 715 }
 716
 717 /**
 718  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 719  *  @hw: pointer to the HW structure
 720  *
 721  *  Checks if firmware is blocking the reset of the PHY.
 722  *  This is a function pointer entry point only called by
 723  *  reset routines.
 724  **/
 725 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 726 {
 727         u32 fwsm;
 728
 729         fwsm = er32(FWSM);
 730
 731         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 732 }
 733
 734 /**
 735  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 736  *  @hw: pointer to the HW structure
 737  *
 738  *  Forces the speed and duplex settings of the PHY.
 739  *  This is a function pointer entry point only called by
 740  *  PHY setup routines.
 741  **/
 742 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 743 {
 744         struct e1000_phy_info *phy = &hw->phy;
 745         s32 ret_val;
 746         u16 data;
 747         bool link;
 748
 749         if (phy->type != e1000_phy_ife) {
 750                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 751                 return ret_val;
 752         }
 753
 754         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 755         if (ret_val)
 756                 return ret_val;
 757
 758         e1000e_phy_force_speed_duplex_setup(hw, &data);
 759
 760         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 761         if (ret_val)
 762                 return ret_val;
 763
 764         /* Disable MDI-X support for 10/100 */
 765         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 766         if (ret_val)
 767                 return ret_val;
 768
 769         data &= ~IFE_PMC_AUTO_MDIX;
 770         data &= ~IFE_PMC_FORCE_MDIX;
 771
 772         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 773         if (ret_val)
 774                 return ret_val;
 775
 776         hw_dbg(hw, "IFE PMC: %X\n", data);
 777
 778         udelay(1);
 779
 780         if (phy->autoneg_wait_to_complete) {
 781                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 782
 783                 ret_val = e1000e_phy_has_link_generic(hw,
 784                                                      PHY_FORCE_LIMIT,
 785                                                      100000,
 786                                                      &link);
 787                 if (ret_val)
 788                         return ret_val;
 789
 790                 if (!link)
 791                         hw_dbg(hw, "Link taking longer than expected.\n");
 792
 793                 /* Try once more */
 794                 ret_val = e1000e_phy_has_link_generic(hw,
 795                                                      PHY_FORCE_LIMIT,
 796                                                      100000,
 797                                                      &link);
 798                 if (ret_val)
 799                         return ret_val;
 800         }
 801
 802         return 0;
 803 }
 804
 805 /**
 806  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 807  *  @hw:   pointer to the HW structure
 808  *
 809  *  SW should configure the LCD from the NVM extended configuration region
 810  *  as a workaround for certain parts.
 811  **/
 812 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 813 {
 814         struct e1000_phy_info *phy = &hw->phy;
 815         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 816         s32 ret_val;
 817         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 818
 819         ret_val = hw->phy.ops.acquire_phy(hw);
 820         if (ret_val)
 821                 return ret_val;
 822
 823         /*
 824          * Initialize the PHY from the NVM on ICH platforms.  This
 825          * is needed due to an issue where the NVM configuration is
 826          * not properly autoloaded after power transitions.
 827          * Therefore, after each PHY reset, we will load the
 828          * configuration data out of the NVM manually.
 829          */
 830         if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
 831                 (hw->mac.type == e1000_pchlan)) {
 832                 struct e1000_adapter *adapter = hw->adapter;
 833
 834                 /* Check if SW needs to configure the PHY */
 835                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 836                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
 837                     (hw->mac.type == e1000_pchlan))
 838                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 839                 else
 840                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 841
 842                 data = er32(FEXTNVM);
 843                 if (!(data & sw_cfg_mask))
 844                         goto out;
 845
 846                 /* Wait for basic configuration completes before proceeding */
 847                 e1000_lan_init_done_ich8lan(hw);
 848
 849                 /*
 850                  * Make sure HW does not configure LCD from PHY
 851                  * extended configuration before SW configuration
 852                  */
 853                 data = er32(EXTCNF_CTRL);
 854                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 855                         goto out;
 856
 857                 cnf_size = er32(EXTCNF_SIZE);
 858                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 859                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 860                 if (!cnf_size)
 861                         goto out;
 862
 863                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 864                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 865
 866                 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
 867                     (hw->mac.type == e1000_pchlan)) {
 868                         /*
 869                          * HW configures the SMBus address and LEDs when the
 870                          * OEM and LCD Write Enable bits are set in the NVM.
 871                          * When both NVM bits are cleared, SW will configure
 872                          * them instead.
 873                          */
 874                         data = er32(STRAP);
 875                         data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 876                         reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
 877                         reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 878                         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
 879                                                                 reg_data);
 880                         if (ret_val)
 881                                 goto out;
 882
 883                         data = er32(LEDCTL);
 884                         ret_val = e1000_write_phy_reg_hv_locked(hw,
 885                                                                 HV_LED_CONFIG,
 886                                                                 (u16)data);
 887                         if (ret_val)
 888                                 goto out;
 889                 }
 890                 /* Configure LCD from extended configuration region. */
 891
 892                 /* cnf_base_addr is in DWORD */
 893                 word_addr = (u16)(cnf_base_addr << 1);
 894
 895                 for (i = 0; i < cnf_size; i++) {
 896                         ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
 897                                                    &reg_data);
 898                         if (ret_val)
 899                                 goto out;
 900
 901                         ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
 902                                                    1, &reg_addr);
 903                         if (ret_val)
 904                                 goto out;
 905
 906                         /* Save off the PHY page for future writes. */
 907                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 908                                 phy_page = reg_data;
 909                                 continue;
 910                         }
 911
 912                         reg_addr &= PHY_REG_MASK;
 913                         reg_addr |= phy_page;
 914
 915                         ret_val = phy->ops.write_phy_reg_locked(hw,
 916                                                             (u32)reg_addr,
 917                                                             reg_data);
 918                         if (ret_val)
 919                                 goto out;
 920                 }
 921         }
 922
 923 out:
 924         hw->phy.ops.release_phy(hw);
 925         return ret_val;
 926 }
 927
 928 /**
 929  *  e1000_k1_gig_workaround_hv - K1 Si workaround
 930  *  @hw:   pointer to the HW structure
 931  *  @link: link up bool flag
 932  *
 933  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
 934  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
 935  *  If link is down, the function will restore the default K1 setting located
 936  *  in the NVM.
 937  **/
 938 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
 939 {
 940         s32 ret_val = 0;
 941         u16 status_reg = 0;
 942         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
 943
 944         if (hw->mac.type != e1000_pchlan)
 945                 goto out;
 946
 947         /* Wrap the whole flow with the sw flag */
 948         ret_val = hw->phy.ops.acquire_phy(hw);
 949         if (ret_val)
 950                 goto out;
 951
 952         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
 953         if (link) {
 954                 if (hw->phy.type == e1000_phy_82578) {
 955                         ret_val = hw->phy.ops.read_phy_reg_locked(hw,
 956                                                                   BM_CS_STATUS,
 957                                                                   &status_reg);
 958                         if (ret_val)
 959                                 goto release;
 960
 961                         status_reg &= BM_CS_STATUS_LINK_UP |
 962                                       BM_CS_STATUS_RESOLVED |
 963                                       BM_CS_STATUS_SPEED_MASK;
 964
 965                         if (status_reg == (BM_CS_STATUS_LINK_UP |
 966                                            BM_CS_STATUS_RESOLVED |
 967                                            BM_CS_STATUS_SPEED_1000))
 968                                 k1_enable = false;
 969                 }
 970
 971                 if (hw->phy.type == e1000_phy_82577) {
 972                         ret_val = hw->phy.ops.read_phy_reg_locked(hw,
 973                                                                   HV_M_STATUS,
 974                                                                   &status_reg);
 975                         if (ret_val)
 976                                 goto release;
 977
 978                         status_reg &= HV_M_STATUS_LINK_UP |
 979                                       HV_M_STATUS_AUTONEG_COMPLETE |
 980                                       HV_M_STATUS_SPEED_MASK;
 981
 982                         if (status_reg == (HV_M_STATUS_LINK_UP |
 983                                            HV_M_STATUS_AUTONEG_COMPLETE |
 984                                            HV_M_STATUS_SPEED_1000))
 985                                 k1_enable = false;
 986                 }
 987
 988                 /* Link stall fix for link up */
 989                 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
 990                                                            0x0100);
 991                 if (ret_val)
 992                         goto release;
 993
 994         } else {
 995                 /* Link stall fix for link down */
 996                 ret_val = hw->phy.ops.write_phy_reg_locked(hw, PHY_REG(770, 19),
 997                                                            0x4100);
 998                 if (ret_val)
 999                         goto release;
1000         }
1001
1002         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1003
1004 release:
1005         hw->phy.ops.release_phy(hw);
1006 out:
1007         return ret_val;
1008 }
1009
1010 /**
1011  *  e1000_configure_k1_ich8lan - Configure K1 power state
1012  *  @hw: pointer to the HW structure
1013  *  @enable: K1 state to configure
1014  *
1015  *  Configure the K1 power state based on the provided parameter.
1016  *  Assumes semaphore already acquired.
1017  *
1018  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1019  **/
1020 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1021 {
1022         s32 ret_val = 0;
1023         u32 ctrl_reg = 0;
1024         u32 ctrl_ext = 0;
1025         u32 reg = 0;
1026         u16 kmrn_reg = 0;
1027
1028         ret_val = e1000e_read_kmrn_reg_locked(hw,
1029                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1030                                              &kmrn_reg);
1031         if (ret_val)
1032                 goto out;
1033
1034         if (k1_enable)
1035                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1036         else
1037                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1038
1039         ret_val = e1000e_write_kmrn_reg_locked(hw,
1040                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1041                                               kmrn_reg);
1042         if (ret_val)
1043                 goto out;
1044
1045         udelay(20);
1046         ctrl_ext = er32(CTRL_EXT);
1047         ctrl_reg = er32(CTRL);
1048
1049         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1050         reg |= E1000_CTRL_FRCSPD;
1051         ew32(CTRL, reg);
1052
1053         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1054         udelay(20);
1055         ew32(CTRL, ctrl_reg);
1056         ew32(CTRL_EXT, ctrl_ext);
1057         udelay(20);
1058
1059 out:
1060         return ret_val;
1061 }
1062
1063 /**
1064  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1065  *  @hw:       pointer to the HW structure
1066  *  @d0_state: boolean if entering d0 or d3 device state
1067  *
1068  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1069  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1070  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1071  **/
1072 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1073 {
1074         s32 ret_val = 0;
1075         u32 mac_reg;
1076         u16 oem_reg;
1077
1078         if (hw->mac.type != e1000_pchlan)
1079                 return ret_val;
1080
1081         ret_val = hw->phy.ops.acquire_phy(hw);
1082         if (ret_val)
1083                 return ret_val;
1084
1085         mac_reg = er32(EXTCNF_CTRL);
1086         if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1087                 goto out;
1088
1089         mac_reg = er32(FEXTNVM);
1090         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1091                 goto out;
1092
1093         mac_reg = er32(PHY_CTRL);
1094
1095         ret_val = hw->phy.ops.read_phy_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1096         if (ret_val)
1097                 goto out;
1098
1099         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1100
1101         if (d0_state) {
1102                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1103                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1104
1105                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1106                         oem_reg |= HV_OEM_BITS_LPLU;
1107         } else {
1108                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1109                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1110
1111                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1112                         oem_reg |= HV_OEM_BITS_LPLU;
1113         }
1114         /* Restart auto-neg to activate the bits */
1115         oem_reg |= HV_OEM_BITS_RESTART_AN;
1116         ret_val = hw->phy.ops.write_phy_reg_locked(hw, HV_OEM_BITS, oem_reg);
1117
1118 out:
1119         hw->phy.ops.release_phy(hw);
1120
1121         return ret_val;
1122 }
1123
1124
1125 /**
1126  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1127  *  done after every PHY reset.
1128  **/
1129 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1130 {
1131         s32 ret_val = 0;
1132
1133         if (hw->mac.type != e1000_pchlan)
1134                 return ret_val;
1135
1136         if (((hw->phy.type == e1000_phy_82577) &&
1137              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1138             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1139                 /* Disable generation of early preamble */
1140                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1141                 if (ret_val)
1142                         return ret_val;
1143
1144                 /* Preamble tuning for SSC */
1145                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1146                 if (ret_val)
1147                         return ret_val;
1148         }
1149
1150         if (hw->phy.type == e1000_phy_82578) {
1151                 /*
1152                  * Return registers to default by doing a soft reset then
1153                  * writing 0x3140 to the control register.
1154                  */
1155                 if (hw->phy.revision < 2) {
1156                         e1000e_phy_sw_reset(hw);
1157                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1158                 }
1159         }
1160
1161         /* Select page 0 */
1162         ret_val = hw->phy.ops.acquire_phy(hw);
1163         if (ret_val)
1164                 return ret_val;
1165
1166         hw->phy.addr = 1;
1167         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1168         if (ret_val)
1169                 goto out;
1170         hw->phy.ops.release_phy(hw);
1171
1172         /*
1173          * Configure the K1 Si workaround during phy reset assuming there is
1174          * link so that it disables K1 if link is in 1Gbps.
1175          */
1176         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1177
1178 out:
1179         return ret_val;
1180 }
1181
1182 /**
1183  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1184  *  @hw: pointer to the HW structure
1185  *
1186  *  Check the appropriate indication the MAC has finished configuring the
1187  *  PHY after a software reset.
1188  **/
1189 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1190 {
1191         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1192
1193         /* Wait for basic configuration completes before proceeding */
1194         do {
1195                 data = er32(STATUS);
1196                 data &= E1000_STATUS_LAN_INIT_DONE;
1197                 udelay(100);
1198         } while ((!data) && --loop);
1199
1200         /*
1201          * If basic configuration is incomplete before the above loop
1202          * count reaches 0, loading the configuration from NVM will
1203          * leave the PHY in a bad state possibly resulting in no link.
1204          */
1205         if (loop == 0)
1206                 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
1207
1208         /* Clear the Init Done bit for the next init event */
1209         data = er32(STATUS);
1210         data &= ~E1000_STATUS_LAN_INIT_DONE;
1211         ew32(STATUS, data);
1212 }
1213
1214 /**
1215  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1216  *  @hw: pointer to the HW structure
1217  *
1218  *  Resets the PHY
1219  *  This is a function pointer entry point called by drivers
1220  *  or other shared routines.
1221  **/
1222 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1223 {
1224         s32 ret_val = 0;
1225         u16 reg;
1226
1227         ret_val = e1000e_phy_hw_reset_generic(hw);
1228         if (ret_val)
1229                 return ret_val;
1230
1231         /* Allow time for h/w to get to a quiescent state after reset */
1232         mdelay(10);
1233
1234         if (hw->mac.type == e1000_pchlan) {
1235                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1236                 if (ret_val)
1237                         return ret_val;
1238         }
1239
1240         /* Dummy read to clear the phy wakeup bit after lcd reset */
1241         if (hw->mac.type == e1000_pchlan)
1242                 e1e_rphy(hw, BM_WUC, &reg);
1243
1244         /* Configure the LCD with the extended configuration region in NVM */
1245         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1246         if (ret_val)
1247                 goto out;
1248
1249         /* Configure the LCD with the OEM bits in NVM */
1250         if (hw->mac.type == e1000_pchlan)
1251                 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1252
1253 out:
1254         return 0;
1255 }
1256
1257 /**
1258  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
1259  *  @hw: pointer to the HW structure
1260  *
1261  *  Populates "phy" structure with various feature states.
1262  *  This function is only called by other family-specific
1263  *  routines.
1264  **/
1265 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
1266 {
1267         struct e1000_phy_info *phy = &hw->phy;
1268         s32 ret_val;
1269         u16 data;
1270         bool link;
1271
1272         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1273         if (ret_val)
1274                 return ret_val;
1275
1276         if (!link) {
1277                 hw_dbg(hw, "Phy info is only valid if link is up\n");
1278                 return -E1000_ERR_CONFIG;
1279         }
1280
1281         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
1282         if (ret_val)
1283                 return ret_val;
1284         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
1285
1286         if (phy->polarity_correction) {
1287                 ret_val = phy->ops.check_polarity(hw);
1288                 if (ret_val)
1289                         return ret_val;
1290         } else {
1291                 /* Polarity is forced */
1292                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
1293                                       ? e1000_rev_polarity_reversed
1294                                       : e1000_rev_polarity_normal;
1295         }
1296
1297         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1298         if (ret_val)
1299                 return ret_val;
1300
1301         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
1302
1303         /* The following parameters are undefined for 10/100 operation. */
1304         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1305         phy->local_rx = e1000_1000t_rx_status_undefined;
1306         phy->remote_rx = e1000_1000t_rx_status_undefined;
1307
1308         return 0;
1309 }
1310
1311 /**
1312  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1313  *  @hw: pointer to the HW structure
1314  *
1315  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
1316  *  This is a function pointer entry point called by drivers
1317  *  or other shared routines.
1318  **/
1319 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1320 {
1321         switch (hw->phy.type) {
1322         case e1000_phy_ife:
1323                 return e1000_get_phy_info_ife_ich8lan(hw);
1324                 break;
1325         case e1000_phy_igp_3:
1326         case e1000_phy_bm:
1327         case e1000_phy_82578:
1328         case e1000_phy_82577:
1329                 return e1000e_get_phy_info_igp(hw);
1330                 break;
1331         default:
1332                 break;
1333         }
1334
1335         return -E1000_ERR_PHY_TYPE;
1336 }
1337
1338 /**
1339  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1340  *  @hw: pointer to the HW structure
1341  *
1342  *  Polarity is determined on the polarity reversal feature being enabled.
1343  *  This function is only called by other family-specific
1344  *  routines.
1345  **/
1346 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1347 {
1348         struct e1000_phy_info *phy = &hw->phy;
1349         s32 ret_val;
1350         u16 phy_data, offset, mask;
1351
1352         /*
1353          * Polarity is determined based on the reversal feature being enabled.
1354          */
1355         if (phy->polarity_correction) {
1356                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
1357                 mask    = IFE_PESC_POLARITY_REVERSED;
1358         } else {
1359                 offset  = IFE_PHY_SPECIAL_CONTROL;
1360                 mask    = IFE_PSC_FORCE_POLARITY;
1361         }
1362
1363         ret_val = e1e_rphy(hw, offset, &phy_data);
1364
1365         if (!ret_val)
1366                 phy->cable_polarity = (phy_data & mask)
1367                                       ? e1000_rev_polarity_reversed
1368                                       : e1000_rev_polarity_normal;
1369
1370         return ret_val;
1371 }
1372
1373 /**
1374  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1375  *  @hw: pointer to the HW structure
1376  *  @active: true to enable LPLU, false to disable
1377  *
1378  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1379  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1380  *  the phy speed. This function will manually set the LPLU bit and restart
1381  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1382  *  since it configures the same bit.
1383  **/
1384 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1385 {
1386         s32 ret_val = 0;
1387         u16 oem_reg;
1388
1389         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1390         if (ret_val)
1391                 goto out;
1392
1393         if (active)
1394                 oem_reg |= HV_OEM_BITS_LPLU;
1395         else
1396                 oem_reg &= ~HV_OEM_BITS_LPLU;
1397
1398         oem_reg |= HV_OEM_BITS_RESTART_AN;
1399         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1400
1401 out:
1402         return ret_val;
1403 }
1404
1405 /**
1406  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1407  *  @hw: pointer to the HW structure
1408  *  @active: TRUE to enable LPLU, FALSE to disable
1409  *
1410  *  Sets the LPLU D0 state according to the active flag.  When
1411  *  activating LPLU this function also disables smart speed
1412  *  and vice versa.  LPLU will not be activated unless the
1413  *  device autonegotiation advertisement meets standards of
1414  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1415  *  This is a function pointer entry point only called by
1416  *  PHY setup routines.
1417  **/
1418 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1419 {
1420         struct e1000_phy_info *phy = &hw->phy;
1421         u32 phy_ctrl;
1422         s32 ret_val = 0;
1423         u16 data;
1424
1425         if (phy->type == e1000_phy_ife)
1426                 return ret_val;
1427
1428         phy_ctrl = er32(PHY_CTRL);
1429
1430         if (active) {
1431                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1432                 ew32(PHY_CTRL, phy_ctrl);
1433
1434                 if (phy->type != e1000_phy_igp_3)
1435                         return 0;
1436
1437                 /*
1438                  * Call gig speed drop workaround on LPLU before accessing
1439                  * any PHY registers
1440                  */
1441                 if (hw->mac.type == e1000_ich8lan)
1442                         e1000e_gig_downshift_workaround_ich8lan(hw);
1443
1444                 /* When LPLU is enabled, we should disable SmartSpeed */
1445                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1446                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1447                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1448                 if (ret_val)
1449                         return ret_val;
1450         } else {
1451                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1452                 ew32(PHY_CTRL, phy_ctrl);
1453
1454                 if (phy->type != e1000_phy_igp_3)
1455                         return 0;
1456
1457                 /*
1458                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1459                  * during Dx states where the power conservation is most
1460                  * important.  During driver activity we should enable
1461                  * SmartSpeed, so performance is maintained.
1462                  */
1463                 if (phy->smart_speed == e1000_smart_speed_on) {
1464                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1465                                            &data);
1466                         if (ret_val)
1467                                 return ret_val;
1468
1469                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1470                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1471                                            data);
1472                         if (ret_val)
1473                                 return ret_val;
1474                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1475                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1476                                            &data);
1477                         if (ret_val)
1478                                 return ret_val;
1479
1480                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1481                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1482                                            data);
1483                         if (ret_val)
1484                                 return ret_val;
1485                 }
1486         }
1487
1488         return 0;
1489 }
1490
1491 /**
1492  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1493  *  @hw: pointer to the HW structure
1494  *  @active: TRUE to enable LPLU, FALSE to disable
1495  *
1496  *  Sets the LPLU D3 state according to the active flag.  When
1497  *  activating LPLU this function also disables smart speed
1498  *  and vice versa.  LPLU will not be activated unless the
1499  *  device autonegotiation advertisement meets standards of
1500  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1501  *  This is a function pointer entry point only called by
1502  *  PHY setup routines.
1503  **/
1504 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1505 {
1506         struct e1000_phy_info *phy = &hw->phy;
1507         u32 phy_ctrl;
1508         s32 ret_val;
1509         u16 data;
1510
1511         phy_ctrl = er32(PHY_CTRL);
1512
1513         if (!active) {
1514                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1515                 ew32(PHY_CTRL, phy_ctrl);
1516
1517                 if (phy->type != e1000_phy_igp_3)
1518                         return 0;
1519
1520                 /*
1521                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1522                  * during Dx states where the power conservation is most
1523                  * important.  During driver activity we should enable
1524                  * SmartSpeed, so performance is maintained.
1525                  */
1526                 if (phy->smart_speed == e1000_smart_speed_on) {
1527                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1528                                            &data);
1529                         if (ret_val)
1530                                 return ret_val;
1531
1532                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1533                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1534                                            data);
1535                         if (ret_val)
1536                                 return ret_val;
1537                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1538                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1539                                            &data);
1540                         if (ret_val)
1541                                 return ret_val;
1542
1543                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1544                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1545                                            data);
1546                         if (ret_val)
1547                                 return ret_val;
1548                 }
1549         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1550                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1551                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1552                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1553                 ew32(PHY_CTRL, phy_ctrl);
1554
1555                 if (phy->type != e1000_phy_igp_3)
1556                         return 0;
1557
1558                 /*
1559                  * Call gig speed drop workaround on LPLU before accessing
1560                  * any PHY registers
1561                  */
1562                 if (hw->mac.type == e1000_ich8lan)
1563                         e1000e_gig_downshift_workaround_ich8lan(hw);
1564
1565                 /* When LPLU is enabled, we should disable SmartSpeed */
1566                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1567                 if (ret_val)
1568                         return ret_val;
1569
1570                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1571                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1572         }
1573
1574         return 0;
1575 }
1576
1577 /**
1578  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1579  *  @hw: pointer to the HW structure
1580  *  @bank:  pointer to the variable that returns the active bank
1581  *
1582  *  Reads signature byte from the NVM using the flash access registers.
1583  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1584  **/
1585 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1586 {
1587         u32 eecd;
1588         struct e1000_nvm_info *nvm = &hw->nvm;
1589         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1590         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1591         u8 sig_byte = 0;
1592         s32 ret_val = 0;
1593
1594         switch (hw->mac.type) {
1595         case e1000_ich8lan:
1596         case e1000_ich9lan:
1597                 eecd = er32(EECD);
1598                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1599                     E1000_EECD_SEC1VAL_VALID_MASK) {
1600                         if (eecd & E1000_EECD_SEC1VAL)
1601                                 *bank = 1;
1602                         else
1603                                 *bank = 0;
1604
1605                         return 0;
1606                 }
1607                 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
1608                        "reading flash signature\n");
1609                 /* fall-thru */
1610         default:
1611                 /* set bank to 0 in case flash read fails */
1612                 *bank = 0;
1613
1614                 /* Check bank 0 */
1615                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1616                                                         &sig_byte);
1617                 if (ret_val)
1618                         return ret_val;
1619                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1620                     E1000_ICH_NVM_SIG_VALUE) {
1621                         *bank = 0;
1622                         return 0;
1623                 }
1624
1625                 /* Check bank 1 */
1626                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1627                                                         bank1_offset,
1628                                                         &sig_byte);
1629                 if (ret_val)
1630                         return ret_val;
1631                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1632                     E1000_ICH_NVM_SIG_VALUE) {
1633                         *bank = 1;
1634                         return 0;
1635                 }
1636
1637                 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1638                 return -E1000_ERR_NVM;
1639         }
1640
1641         return 0;
1642 }
1643
1644 /**
1645  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1646  *  @hw: pointer to the HW structure
1647  *  @offset: The offset (in bytes) of the word(s) to read.
1648  *  @words: Size of data to read in words
1649  *  @data: Pointer to the word(s) to read at offset.
1650  *
1651  *  Reads a word(s) from the NVM using the flash access registers.
1652  **/
1653 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1654                                   u16 *data)
1655 {
1656         struct e1000_nvm_info *nvm = &hw->nvm;
1657         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1658         u32 act_offset;
1659         s32 ret_val = 0;
1660         u32 bank = 0;
1661         u16 i, word;
1662
1663         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1664             (words == 0)) {
1665                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1666                 ret_val = -E1000_ERR_NVM;
1667                 goto out;
1668         }
1669
1670         nvm->ops.acquire_nvm(hw);
1671
1672         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1673         if (ret_val) {
1674                 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
1675                 bank = 0;
1676         }
1677
1678         act_offset = (bank) ? nvm->flash_bank_size : 0;
1679         act_offset += offset;
1680
1681         ret_val = 0;
1682         for (i = 0; i < words; i++) {
1683                 if ((dev_spec->shadow_ram) &&
1684                     (dev_spec->shadow_ram[offset+i].modified)) {
1685                         data[i] = dev_spec->shadow_ram[offset+i].value;
1686                 } else {
1687                         ret_val = e1000_read_flash_word_ich8lan(hw,
1688                                                                 act_offset + i,
1689                                                                 &word);
1690                         if (ret_val)
1691                                 break;
1692                         data[i] = word;
1693                 }
1694         }
1695
1696         nvm->ops.release_nvm(hw);
1697
1698 out:
1699         if (ret_val)
1700                 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1701
1702         return ret_val;
1703 }
1704
1705 /**
1706  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1707  *  @hw: pointer to the HW structure
1708  *
1709  *  This function does initial flash setup so that a new read/write/erase cycle
1710  *  can be started.
1711  **/
1712 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1713 {
1714         union ich8_hws_flash_status hsfsts;
1715         s32 ret_val = -E1000_ERR_NVM;
1716         s32 i = 0;
1717
1718         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1719
1720         /* Check if the flash descriptor is valid */
1721         if (hsfsts.hsf_status.fldesvalid == 0) {
1722                 hw_dbg(hw, "Flash descriptor invalid.  "
1723                          "SW Sequencing must be used.");
1724                 return -E1000_ERR_NVM;
1725         }
1726
1727         /* Clear FCERR and DAEL in hw status by writing 1 */
1728         hsfsts.hsf_status.flcerr = 1;
1729         hsfsts.hsf_status.dael = 1;
1730
1731         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1732
1733         /*
1734          * Either we should have a hardware SPI cycle in progress
1735          * bit to check against, in order to start a new cycle or
1736          * FDONE bit should be changed in the hardware so that it
1737          * is 1 after hardware reset, which can then be used as an
1738          * indication whether a cycle is in progress or has been
1739          * completed.
1740          */
1741
1742         if (hsfsts.hsf_status.flcinprog == 0) {
1743                 /*
1744                  * There is no cycle running at present,
1745                  * so we can start a cycle
1746                  * Begin by setting Flash Cycle Done.
1747                  */
1748                 hsfsts.hsf_status.flcdone = 1;
1749                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1750                 ret_val = 0;
1751         } else {
1752                 /*
1753                  * otherwise poll for sometime so the current
1754                  * cycle has a chance to end before giving up.
1755                  */
1756                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1757                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1758                         if (hsfsts.hsf_status.flcinprog == 0) {
1759                                 ret_val = 0;
1760                                 break;
1761                         }
1762                         udelay(1);
1763                 }
1764                 if (ret_val == 0) {
1765                         /*
1766                          * Successful in waiting for previous cycle to timeout,
1767                          * now set the Flash Cycle Done.
1768                          */
1769                         hsfsts.hsf_status.flcdone = 1;
1770                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1771                 } else {
1772                         hw_dbg(hw, "Flash controller busy, cannot get access");
1773                 }
1774         }
1775
1776         return ret_val;
1777 }
1778
1779 /**
1780  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1781  *  @hw: pointer to the HW structure
1782  *  @timeout: maximum time to wait for completion
1783  *
1784  *  This function starts a flash cycle and waits for its completion.
1785  **/
1786 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1787 {
1788         union ich8_hws_flash_ctrl hsflctl;
1789         union ich8_hws_flash_status hsfsts;
1790         s32 ret_val = -E1000_ERR_NVM;
1791         u32 i = 0;
1792
1793         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1794         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1795         hsflctl.hsf_ctrl.flcgo = 1;
1796         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1797
1798         /* wait till FDONE bit is set to 1 */
1799         do {
1800                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1801                 if (hsfsts.hsf_status.flcdone == 1)
1802                         break;
1803                 udelay(1);
1804         } while (i++ < timeout);
1805
1806         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1807                 return 0;
1808
1809         return ret_val;
1810 }
1811
1812 /**
1813  *  e1000_read_flash_word_ich8lan - Read word from flash
1814  *  @hw: pointer to the HW structure
1815  *  @offset: offset to data location
1816  *  @data: pointer to the location for storing the data
1817  *
1818  *  Reads the flash word at offset into data.  Offset is converted
1819  *  to bytes before read.
1820  **/
1821 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1822                                          u16 *data)
1823 {
1824         /* Must convert offset into bytes. */
1825         offset <<= 1;
1826
1827         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1828 }
1829
1830 /**
1831  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1832  *  @hw: pointer to the HW structure
1833  *  @offset: The offset of the byte to read.
1834  *  @data: Pointer to a byte to store the value read.
1835  *
1836  *  Reads a single byte from the NVM using the flash access registers.
1837  **/
1838 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1839                                          u8 *data)
1840 {
1841         s32 ret_val;
1842         u16 word = 0;
1843
1844         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1845         if (ret_val)
1846                 return ret_val;
1847
1848         *data = (u8)word;
1849
1850         return 0;
1851 }
1852
1853 /**
1854  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1855  *  @hw: pointer to the HW structure
1856  *  @offset: The offset (in bytes) of the byte or word to read.
1857  *  @size: Size of data to read, 1=byte 2=word
1858  *  @data: Pointer to the word to store the value read.
1859  *
1860  *  Reads a byte or word from the NVM using the flash access registers.
1861  **/
1862 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1863                                          u8 size, u16 *data)
1864 {
1865         union ich8_hws_flash_status hsfsts;
1866         union ich8_hws_flash_ctrl hsflctl;
1867         u32 flash_linear_addr;
1868         u32 flash_data = 0;
1869         s32 ret_val = -E1000_ERR_NVM;
1870         u8 count = 0;
1871
1872         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1873                 return -E1000_ERR_NVM;
1874
1875         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1876                             hw->nvm.flash_base_addr;
1877
1878         do {
1879                 udelay(1);
1880                 /* Steps */
1881                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1882                 if (ret_val != 0)
1883                         break;
1884
1885                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1886                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1887                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1888                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1889                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1890
1891                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1892
1893                 ret_val = e1000_flash_cycle_ich8lan(hw,
1894                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1895
1896                 /*
1897                  * Check if FCERR is set to 1, if set to 1, clear it
1898                  * and try the whole sequence a few more times, else
1899                  * read in (shift in) the Flash Data0, the order is
1900                  * least significant byte first msb to lsb
1901                  */
1902                 if (ret_val == 0) {
1903                         flash_data = er32flash(ICH_FLASH_FDATA0);
1904                         if (size == 1) {
1905                                 *data = (u8)(flash_data & 0x000000FF);
1906                         } else if (size == 2) {
1907                                 *data = (u16)(flash_data & 0x0000FFFF);
1908                         }
1909                         break;
1910                 } else {
1911                         /*
1912                          * If we've gotten here, then things are probably
1913                          * completely hosed, but if the error condition is
1914                          * detected, it won't hurt to give it another try...
1915                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1916                          */
1917                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1918                         if (hsfsts.hsf_status.flcerr == 1) {
1919                                 /* Repeat for some time before giving up. */
1920                                 continue;
1921                         } else if (hsfsts.hsf_status.flcdone == 0) {
1922                                 hw_dbg(hw, "Timeout error - flash cycle "
1923                                          "did not complete.");
1924                                 break;
1925                         }
1926                 }
1927         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1928
1929         return ret_val;
1930 }
1931
1932 /**
1933  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1934  *  @hw: pointer to the HW structure
1935  *  @offset: The offset (in bytes) of the word(s) to write.
1936  *  @words: Size of data to write in words
1937  *  @data: Pointer to the word(s) to write at offset.
1938  *
1939  *  Writes a byte or word to the NVM using the flash access registers.
1940  **/
1941 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1942                                    u16 *data)
1943 {
1944         struct e1000_nvm_info *nvm = &hw->nvm;
1945         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1946         u16 i;
1947
1948         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1949             (words == 0)) {
1950                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1951                 return -E1000_ERR_NVM;
1952         }
1953
1954         nvm->ops.acquire_nvm(hw);
1955
1956         for (i = 0; i < words; i++) {
1957                 dev_spec->shadow_ram[offset+i].modified = 1;
1958                 dev_spec->shadow_ram[offset+i].value = data[i];
1959         }
1960
1961         nvm->ops.release_nvm(hw);
1962
1963         return 0;
1964 }
1965
1966 /**
1967  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1968  *  @hw: pointer to the HW structure
1969  *
1970  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1971  *  which writes the checksum to the shadow ram.  The changes in the shadow
1972  *  ram are then committed to the EEPROM by processing each bank at a time
1973  *  checking for the modified bit and writing only the pending changes.
1974  *  After a successful commit, the shadow ram is cleared and is ready for
1975  *  future writes.
1976  **/
1977 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1978 {
1979         struct e1000_nvm_info *nvm = &hw->nvm;
1980         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1981         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1982         s32 ret_val;
1983         u16 data;
1984
1985         ret_val = e1000e_update_nvm_checksum_generic(hw);
1986         if (ret_val)
1987                 goto out;
1988
1989         if (nvm->type != e1000_nvm_flash_sw)
1990                 goto out;
1991
1992         nvm->ops.acquire_nvm(hw);
1993
1994         /*
1995          * We're writing to the opposite bank so if we're on bank 1,
1996          * write to bank 0 etc.  We also need to erase the segment that
1997          * is going to be written
1998          */
1999         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2000         if (ret_val) {
2001                 hw_dbg(hw, "Could not detect valid bank, assuming bank 0\n");
2002                 bank = 0;
2003         }
2004
2005         if (bank == 0) {
2006                 new_bank_offset = nvm->flash_bank_size;
2007                 old_bank_offset = 0;
2008                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2009                 if (ret_val) {
2010                         nvm->ops.release_nvm(hw);
2011                         goto out;
2012                 }
2013         } else {
2014                 old_bank_offset = nvm->flash_bank_size;
2015                 new_bank_offset = 0;
2016                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2017                 if (ret_val) {
2018                         nvm->ops.release_nvm(hw);
2019                         goto out;
2020                 }
2021         }
2022
2023         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2024                 /*
2025                  * Determine whether to write the value stored
2026                  * in the other NVM bank or a modified value stored
2027                  * in the shadow RAM
2028                  */
2029                 if (dev_spec->shadow_ram[i].modified) {
2030                         data = dev_spec->shadow_ram[i].value;
2031                 } else {
2032                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2033                                                                 old_bank_offset,
2034                                                                 &data);
2035                         if (ret_val)
2036                                 break;
2037                 }
2038
2039                 /*
2040                  * If the word is 0x13, then make sure the signature bits
2041                  * (15:14) are 11b until the commit has completed.
2042                  * This will allow us to write 10b which indicates the
2043                  * signature is valid.  We want to do this after the write
2044                  * has completed so that we don't mark the segment valid
2045                  * while the write is still in progress
2046                  */
2047                 if (i == E1000_ICH_NVM_SIG_WORD)
2048                         data |= E1000_ICH_NVM_SIG_MASK;
2049
2050                 /* Convert offset to bytes. */
2051                 act_offset = (i + new_bank_offset) << 1;
2052
2053                 udelay(100);
2054                 /* Write the bytes to the new bank. */
2055                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2056                                                                act_offset,
2057                                                                (u8)data);
2058                 if (ret_val)
2059                         break;
2060
2061                 udelay(100);
2062                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2063                                                           act_offset + 1,
2064                                                           (u8)(data >> 8));
2065                 if (ret_val)
2066                         break;
2067         }
2068
2069         /*
2070          * Don't bother writing the segment valid bits if sector
2071          * programming failed.
2072          */
2073         if (ret_val) {
2074                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2075                 hw_dbg(hw, "Flash commit failed.\n");
2076                 nvm->ops.release_nvm(hw);
2077                 goto out;
2078         }
2079
2080         /*
2081          * Finally validate the new segment by setting bit 15:14
2082          * to 10b in word 0x13 , this can be done without an
2083          * erase as well since these bits are 11 to start with
2084          * and we need to change bit 14 to 0b
2085          */
2086         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2087         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2088         if (ret_val) {
2089                 nvm->ops.release_nvm(hw);
2090                 goto out;
2091         }
2092         data &= 0xBFFF;
2093         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2094                                                        act_offset * 2 + 1,
2095                                                        (u8)(data >> 8));
2096         if (ret_val) {
2097                 nvm->ops.release_nvm(hw);
2098                 goto out;
2099         }
2100
2101         /*
2102          * And invalidate the previously valid segment by setting
2103          * its signature word (0x13) high_byte to 0b. This can be
2104          * done without an erase because flash erase sets all bits
2105          * to 1's. We can write 1's to 0's without an erase
2106          */
2107         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2108         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2109         if (ret_val) {
2110                 nvm->ops.release_nvm(hw);
2111                 goto out;
2112         }
2113
2114         /* Great!  Everything worked, we can now clear the cached entries. */
2115         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2116                 dev_spec->shadow_ram[i].modified = 0;
2117                 dev_spec->shadow_ram[i].value = 0xFFFF;
2118         }
2119
2120         nvm->ops.release_nvm(hw);
2121
2122         /*
2123          * Reload the EEPROM, or else modifications will not appear
2124          * until after the next adapter reset.
2125          */
2126         e1000e_reload_nvm(hw);
2127         msleep(10);
2128
2129 out:
2130         if (ret_val)
2131                 hw_dbg(hw, "NVM update error: %d\n", ret_val);
2132
2133         return ret_val;
2134 }
2135
2136 /**
2137  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2138  *  @hw: pointer to the HW structure
2139  *
2140  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2141  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2142  *  calculated, in which case we need to calculate the checksum and set bit 6.
2143  **/
2144 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2145 {
2146         s32 ret_val;
2147         u16 data;
2148
2149         /*
2150          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2151          * needs to be fixed.  This bit is an indication that the NVM
2152          * was prepared by OEM software and did not calculate the
2153          * checksum...a likely scenario.
2154          */
2155         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2156         if (ret_val)
2157                 return ret_val;
2158
2159         if ((data & 0x40) == 0) {
2160                 data |= 0x40;
2161                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2162                 if (ret_val)
2163                         return ret_val;
2164                 ret_val = e1000e_update_nvm_checksum(hw);
2165                 if (ret_val)
2166                         return ret_val;
2167         }
2168
2169         return e1000e_validate_nvm_checksum_generic(hw);
2170 }
2171
2172 /**
2173  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2174  *  @hw: pointer to the HW structure
2175  *
2176  *  To prevent malicious write/erase of the NVM, set it to be read-only
2177  *  so that the hardware ignores all write/erase cycles of the NVM via
2178  *  the flash control registers.  The shadow-ram copy of the NVM will
2179  *  still be updated, however any updates to this copy will not stick
2180  *  across driver reloads.
2181  **/
2182 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2183 {
2184         struct e1000_nvm_info *nvm = &hw->nvm;
2185         union ich8_flash_protected_range pr0;
2186         union ich8_hws_flash_status hsfsts;
2187         u32 gfpreg;
2188
2189         nvm->ops.acquire_nvm(hw);
2190
2191         gfpreg = er32flash(ICH_FLASH_GFPREG);
2192
2193         /* Write-protect GbE Sector of NVM */
2194         pr0.regval = er32flash(ICH_FLASH_PR0);
2195         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2196         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2197         pr0.range.wpe = true;
2198         ew32flash(ICH_FLASH_PR0, pr0.regval);
2199
2200         /*
2201          * Lock down a subset of GbE Flash Control Registers, e.g.
2202          * PR0 to prevent the write-protection from being lifted.
2203          * Once FLOCKDN is set, the registers protected by it cannot
2204          * be written until FLOCKDN is cleared by a hardware reset.
2205          */
2206         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2207         hsfsts.hsf_status.flockdn = true;
2208         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2209
2210         nvm->ops.release_nvm(hw);
2211 }
2212
2213 /**
2214  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2215  *  @hw: pointer to the HW structure
2216  *  @offset: The offset (in bytes) of the byte/word to read.
2217  *  @size: Size of data to read, 1=byte 2=word
2218  *  @data: The byte(s) to write to the NVM.
2219  *
2220  *  Writes one/two bytes to the NVM using the flash access registers.
2221  **/
2222 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2223                                           u8 size, u16 data)
2224 {
2225         union ich8_hws_flash_status hsfsts;
2226         union ich8_hws_flash_ctrl hsflctl;
2227         u32 flash_linear_addr;
2228         u32 flash_data = 0;
2229         s32 ret_val;
2230         u8 count = 0;
2231
2232         if (size < 1 || size > 2 || data > size * 0xff ||
2233             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2234                 return -E1000_ERR_NVM;
2235
2236         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2237                             hw->nvm.flash_base_addr;
2238
2239         do {
2240                 udelay(1);
2241                 /* Steps */
2242                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2243                 if (ret_val)
2244                         break;
2245
2246                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2247                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2248                 hsflctl.hsf_ctrl.fldbcount = size -1;
2249                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2250                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2251
2252                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2253
2254                 if (size == 1)
2255                         flash_data = (u32)data & 0x00FF;
2256                 else
2257                         flash_data = (u32)data;
2258
2259                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2260
2261                 /*
2262                  * check if FCERR is set to 1 , if set to 1, clear it
2263                  * and try the whole sequence a few more times else done
2264                  */
2265                 ret_val = e1000_flash_cycle_ich8lan(hw,
2266                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2267                 if (!ret_val)
2268                         break;
2269
2270                 /*
2271                  * If we're here, then things are most likely
2272                  * completely hosed, but if the error condition
2273                  * is detected, it won't hurt to give it another
2274                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2275                  */
2276                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2277                 if (hsfsts.hsf_status.flcerr == 1)
2278                         /* Repeat for some time before giving up. */
2279                         continue;
2280                 if (hsfsts.hsf_status.flcdone == 0) {
2281                         hw_dbg(hw, "Timeout error - flash cycle "
2282                                  "did not complete.");
2283                         break;
2284                 }
2285         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2286
2287         return ret_val;
2288 }
2289
2290 /**
2291  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2292  *  @hw: pointer to the HW structure
2293  *  @offset: The index of the byte to read.
2294  *  @data: The byte to write to the NVM.
2295  *
2296  *  Writes a single byte to the NVM using the flash access registers.
2297  **/
2298 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2299                                           u8 data)
2300 {
2301         u16 word = (u16)data;
2302
2303         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2304 }
2305
2306 /**
2307  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2308  *  @hw: pointer to the HW structure
2309  *  @offset: The offset of the byte to write.
2310  *  @byte: The byte to write to the NVM.
2311  *
2312  *  Writes a single byte to the NVM using the flash access registers.
2313  *  Goes through a retry algorithm before giving up.
2314  **/
2315 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2316                                                 u32 offset, u8 byte)
2317 {
2318         s32 ret_val;
2319         u16 program_retries;
2320
2321         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2322         if (!ret_val)
2323                 return ret_val;
2324
2325         for (program_retries = 0; program_retries < 100; program_retries++) {
2326                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
2327                 udelay(100);
2328                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2329                 if (!ret_val)
2330                         break;
2331         }
2332         if (program_retries == 100)
2333                 return -E1000_ERR_NVM;
2334
2335         return 0;
2336 }
2337
2338 /**
2339  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2340  *  @hw: pointer to the HW structure
2341  *  @bank: 0 for first bank, 1 for second bank, etc.
2342  *
2343  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2344  *  bank N is 4096 * N + flash_reg_addr.
2345  **/
2346 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2347 {
2348         struct e1000_nvm_info *nvm = &hw->nvm;
2349         union ich8_hws_flash_status hsfsts;
2350         union ich8_hws_flash_ctrl hsflctl;
2351         u32 flash_linear_addr;
2352         /* bank size is in 16bit words - adjust to bytes */
2353         u32 flash_bank_size = nvm->flash_bank_size * 2;
2354         s32 ret_val;
2355         s32 count = 0;
2356         s32 iteration;
2357         s32 sector_size;
2358         s32 j;
2359
2360         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2361
2362         /*
2363          * Determine HW Sector size: Read BERASE bits of hw flash status
2364          * register
2365          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2366          *     consecutive sectors.  The start index for the nth Hw sector
2367          *     can be calculated as = bank * 4096 + n * 256
2368          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2369          *     The start index for the nth Hw sector can be calculated
2370          *     as = bank * 4096
2371          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2372          *     (ich9 only, otherwise error condition)
2373          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2374          */
2375         switch (hsfsts.hsf_status.berasesz) {
2376         case 0:
2377                 /* Hw sector size 256 */
2378                 sector_size = ICH_FLASH_SEG_SIZE_256;
2379                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2380                 break;
2381         case 1:
2382                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2383                 iteration = 1;
2384                 break;
2385         case 2:
2386                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2387                 iteration = 1;
2388                 break;
2389         case 3:
2390                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2391                 iteration = 1;
2392                 break;
2393         default:
2394                 return -E1000_ERR_NVM;
2395         }
2396
2397         /* Start with the base address, then add the sector offset. */
2398         flash_linear_addr = hw->nvm.flash_base_addr;
2399         flash_linear_addr += (bank) ? flash_bank_size : 0;
2400
2401         for (j = 0; j < iteration ; j++) {
2402                 do {
2403                         /* Steps */
2404                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2405                         if (ret_val)
2406                                 return ret_val;
2407
2408                         /*
2409                          * Write a value 11 (block Erase) in Flash
2410                          * Cycle field in hw flash control
2411                          */
2412                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2413                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2414                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2415
2416                         /*
2417                          * Write the last 24 bits of an index within the
2418                          * block into Flash Linear address field in Flash
2419                          * Address.
2420                          */
2421                         flash_linear_addr += (j * sector_size);
2422                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2423
2424                         ret_val = e1000_flash_cycle_ich8lan(hw,
2425                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2426                         if (ret_val == 0)
2427                                 break;
2428
2429                         /*
2430                          * Check if FCERR is set to 1.  If 1,
2431                          * clear it and try the whole sequence
2432                          * a few more times else Done
2433                          */
2434                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2435                         if (hsfsts.hsf_status.flcerr == 1)
2436                                 /* repeat for some time before giving up */
2437                                 continue;
2438                         else if (hsfsts.hsf_status.flcdone == 0)
2439                                 return ret_val;
2440                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2441         }
2442
2443         return 0;
2444 }
2445
2446 /**
2447  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2448  *  @hw: pointer to the HW structure
2449  *  @data: Pointer to the LED settings
2450  *
2451  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2452  *  settings is all 0's or F's, set the LED default to a valid LED default
2453  *  setting.
2454  **/
2455 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2456 {
2457         s32 ret_val;
2458
2459         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2460         if (ret_val) {
2461                 hw_dbg(hw, "NVM Read Error\n");
2462                 return ret_val;
2463         }
2464
2465         if (*data == ID_LED_RESERVED_0000 ||
2466             *data == ID_LED_RESERVED_FFFF)
2467                 *data = ID_LED_DEFAULT_ICH8LAN;
2468
2469         return 0;
2470 }
2471
2472 /**
2473  *  e1000_id_led_init_pchlan - store LED configurations
2474  *  @hw: pointer to the HW structure
2475  *
2476  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2477  *  the PHY LED configuration register.
2478  *
2479  *  PCH also does not have an "always on" or "always off" mode which
2480  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2481  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2482  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2483  *  link based on logic in e1000_led_[on|off]_pchlan().
2484  **/
2485 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2486 {
2487         struct e1000_mac_info *mac = &hw->mac;
2488         s32 ret_val;
2489         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2490         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2491         u16 data, i, temp, shift;
2492
2493         /* Get default ID LED modes */
2494         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2495         if (ret_val)
2496                 goto out;
2497
2498         mac->ledctl_default = er32(LEDCTL);
2499         mac->ledctl_mode1 = mac->ledctl_default;
2500         mac->ledctl_mode2 = mac->ledctl_default;
2501
2502         for (i = 0; i < 4; i++) {
2503                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2504                 shift = (i * 5);
2505                 switch (temp) {
2506                 case ID_LED_ON1_DEF2:
2507                 case ID_LED_ON1_ON2:
2508                 case ID_LED_ON1_OFF2:
2509                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2510                         mac->ledctl_mode1 |= (ledctl_on << shift);
2511                         break;
2512                 case ID_LED_OFF1_DEF2:
2513                 case ID_LED_OFF1_ON2:
2514                 case ID_LED_OFF1_OFF2:
2515                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2516                         mac->ledctl_mode1 |= (ledctl_off << shift);
2517                         break;
2518                 default:
2519                         /* Do nothing */
2520                         break;
2521                 }
2522                 switch (temp) {
2523                 case ID_LED_DEF1_ON2:
2524                 case ID_LED_ON1_ON2:
2525                 case ID_LED_OFF1_ON2:
2526                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2527                         mac->ledctl_mode2 |= (ledctl_on << shift);
2528                         break;
2529                 case ID_LED_DEF1_OFF2:
2530                 case ID_LED_ON1_OFF2:
2531                 case ID_LED_OFF1_OFF2:
2532                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2533                         mac->ledctl_mode2 |= (ledctl_off << shift);
2534                         break;
2535                 default:
2536                         /* Do nothing */
2537                         break;
2538                 }
2539         }
2540
2541 out:
2542         return ret_val;
2543 }
2544
2545 /**
2546  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2547  *  @hw: pointer to the HW structure
2548  *
2549  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2550  *  register, so the the bus width is hard coded.
2551  **/
2552 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2553 {
2554         struct e1000_bus_info *bus = &hw->bus;
2555         s32 ret_val;
2556
2557         ret_val = e1000e_get_bus_info_pcie(hw);
2558
2559         /*
2560          * ICH devices are "PCI Express"-ish.  They have
2561          * a configuration space, but do not contain
2562          * PCI Express Capability registers, so bus width
2563          * must be hardcoded.
2564          */
2565         if (bus->width == e1000_bus_width_unknown)
2566                 bus->width = e1000_bus_width_pcie_x1;
2567
2568         return ret_val;
2569 }
2570
2571 /**
2572  *  e1000_reset_hw_ich8lan - Reset the hardware
2573  *  @hw: pointer to the HW structure
2574  *
2575  *  Does a full reset of the hardware which includes a reset of the PHY and
2576  *  MAC.
2577  **/
2578 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2579 {
2580         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2581         u16 reg;
2582         u32 ctrl, icr, kab;
2583         s32 ret_val;
2584
2585         /*
2586          * Prevent the PCI-E bus from sticking if there is no TLP connection
2587          * on the last TLP read/write transaction when MAC is reset.
2588          */
2589         ret_val = e1000e_disable_pcie_master(hw);
2590         if (ret_val) {
2591                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
2592         }
2593
2594         hw_dbg(hw, "Masking off all interrupts\n");
2595         ew32(IMC, 0xffffffff);
2596
2597         /*
2598          * Disable the Transmit and Receive units.  Then delay to allow
2599          * any pending transactions to complete before we hit the MAC
2600          * with the global reset.
2601          */
2602         ew32(RCTL, 0);
2603         ew32(TCTL, E1000_TCTL_PSP);
2604         e1e_flush();
2605
2606         msleep(10);
2607
2608         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2609         if (hw->mac.type == e1000_ich8lan) {
2610                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2611                 ew32(PBA, E1000_PBA_8K);
2612                 /* Set Packet Buffer Size to 16k. */
2613                 ew32(PBS, E1000_PBS_16K);
2614         }
2615
2616         if (hw->mac.type == e1000_pchlan) {
2617                 /* Save the NVM K1 bit setting*/
2618                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2619                 if (ret_val)
2620                         return ret_val;
2621
2622                 if (reg & E1000_NVM_K1_ENABLE)
2623                         dev_spec->nvm_k1_enabled = true;
2624                 else
2625                         dev_spec->nvm_k1_enabled = false;
2626         }
2627
2628         ctrl = er32(CTRL);
2629
2630         if (!e1000_check_reset_block(hw)) {
2631                 /* Clear PHY Reset Asserted bit */
2632                 if (hw->mac.type >= e1000_pchlan) {
2633                         u32 status = er32(STATUS);
2634                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2635                 }
2636
2637                 /*
2638                  * PHY HW reset requires MAC CORE reset at the same
2639                  * time to make sure the interface between MAC and the
2640                  * external PHY is reset.
2641                  */
2642                 ctrl |= E1000_CTRL_PHY_RST;
2643         }
2644         ret_val = e1000_acquire_swflag_ich8lan(hw);
2645         /* Whether or not the swflag was acquired, we need to reset the part */
2646         hw_dbg(hw, "Issuing a global reset to ich8lan\n");
2647         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2648         msleep(20);
2649
2650         if (!ret_val)
2651                 e1000_release_swflag_ich8lan(hw);
2652
2653         if (ctrl & E1000_CTRL_PHY_RST)
2654                 ret_val = hw->phy.ops.get_cfg_done(hw);
2655
2656         if (hw->mac.type >= e1000_ich10lan) {
2657                 e1000_lan_init_done_ich8lan(hw);
2658         } else {
2659                 ret_val = e1000e_get_auto_rd_done(hw);
2660                 if (ret_val) {
2661                         /*
2662                          * When auto config read does not complete, do not
2663                          * return with an error. This can happen in situations
2664                          * where there is no eeprom and prevents getting link.
2665                          */
2666                         hw_dbg(hw, "Auto Read Done did not complete\n");
2667                 }
2668         }
2669         /* Dummy read to clear the phy wakeup bit after lcd reset */
2670         if (hw->mac.type == e1000_pchlan)
2671                 e1e_rphy(hw, BM_WUC, &reg);
2672
2673         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2674         if (ret_val)
2675                 goto out;
2676
2677         if (hw->mac.type == e1000_pchlan) {
2678                 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2679                 if (ret_val)
2680                         goto out;
2681         }
2682         /*
2683          * For PCH, this write will make sure that any noise
2684          * will be detected as a CRC error and be dropped rather than show up
2685          * as a bad packet to the DMA engine.
2686          */
2687         if (hw->mac.type == e1000_pchlan)
2688                 ew32(CRC_OFFSET, 0x65656565);
2689
2690         ew32(IMC, 0xffffffff);
2691         icr = er32(ICR);
2692
2693         kab = er32(KABGTXD);
2694         kab |= E1000_KABGTXD_BGSQLBIAS;
2695         ew32(KABGTXD, kab);
2696
2697         if (hw->mac.type == e1000_pchlan)
2698                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2699
2700 out:
2701         return ret_val;
2702 }
2703
2704 /**
2705  *  e1000_init_hw_ich8lan - Initialize the hardware
2706  *  @hw: pointer to the HW structure
2707  *
2708  *  Prepares the hardware for transmit and receive by doing the following:
2709  *   - initialize hardware bits
2710  *   - initialize LED identification
2711  *   - setup receive address registers
2712  *   - setup flow control
2713  *   - setup transmit descriptors
2714  *   - clear statistics
2715  **/
2716 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2717 {
2718         struct e1000_mac_info *mac = &hw->mac;
2719         u32 ctrl_ext, txdctl, snoop;
2720         s32 ret_val;
2721         u16 i;
2722
2723         e1000_initialize_hw_bits_ich8lan(hw);
2724
2725         /* Initialize identification LED */
2726         ret_val = mac->ops.id_led_init(hw);
2727         if (ret_val) {
2728                 hw_dbg(hw, "Error initializing identification LED\n");
2729                 return ret_val;
2730         }
2731
2732         /* Setup the receive address. */
2733         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2734
2735         /* Zero out the Multicast HASH table */
2736         hw_dbg(hw, "Zeroing the MTA\n");
2737         for (i = 0; i < mac->mta_reg_count; i++)
2738                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2739
2740         /*
2741          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2742          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2743          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2744          */
2745         if (hw->phy.type == e1000_phy_82578) {
2746                 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2747                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2748                 if (ret_val)
2749                         return ret_val;
2750         }
2751
2752         /* Setup link and flow control */
2753         ret_val = e1000_setup_link_ich8lan(hw);
2754
2755         /* Set the transmit descriptor write-back policy for both queues */
2756         txdctl = er32(TXDCTL(0));
2757         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2758                  E1000_TXDCTL_FULL_TX_DESC_WB;
2759         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2760                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2761         ew32(TXDCTL(0), txdctl);
2762         txdctl = er32(TXDCTL(1));
2763         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2764                  E1000_TXDCTL_FULL_TX_DESC_WB;
2765         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2766                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2767         ew32(TXDCTL(1), txdctl);
2768
2769         /*
2770          * ICH8 has opposite polarity of no_snoop bits.
2771          * By default, we should use snoop behavior.
2772          */
2773         if (mac->type == e1000_ich8lan)
2774                 snoop = PCIE_ICH8_SNOOP_ALL;
2775         else
2776                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2777         e1000e_set_pcie_no_snoop(hw, snoop);
2778
2779         ctrl_ext = er32(CTRL_EXT);
2780         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2781         ew32(CTRL_EXT, ctrl_ext);
2782
2783         /*
2784          * Clear all of the statistics registers (clear on read).  It is
2785          * important that we do this after we have tried to establish link
2786          * because the symbol error count will increment wildly if there
2787          * is no link.
2788          */
2789         e1000_clear_hw_cntrs_ich8lan(hw);
2790
2791         return 0;
2792 }
2793 /**
2794  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2795  *  @hw: pointer to the HW structure
2796  *
2797  *  Sets/Clears required hardware bits necessary for correctly setting up the
2798  *  hardware for transmit and receive.
2799  **/
2800 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2801 {
2802         u32 reg;
2803
2804         /* Extended Device Control */
2805         reg = er32(CTRL_EXT);
2806         reg |= (1 << 22);
2807         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2808         if (hw->mac.type >= e1000_pchlan)
2809                 reg |= E1000_CTRL_EXT_PHYPDEN;
2810         ew32(CTRL_EXT, reg);
2811
2812         /* Transmit Descriptor Control 0 */
2813         reg = er32(TXDCTL(0));
2814         reg |= (1 << 22);
2815         ew32(TXDCTL(0), reg);
2816
2817         /* Transmit Descriptor Control 1 */
2818         reg = er32(TXDCTL(1));
2819         reg |= (1 << 22);
2820         ew32(TXDCTL(1), reg);
2821
2822         /* Transmit Arbitration Control 0 */
2823         reg = er32(TARC(0));
2824         if (hw->mac.type == e1000_ich8lan)
2825                 reg |= (1 << 28) | (1 << 29);
2826         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2827         ew32(TARC(0), reg);
2828
2829         /* Transmit Arbitration Control 1 */
2830         reg = er32(TARC(1));
2831         if (er32(TCTL) & E1000_TCTL_MULR)
2832                 reg &= ~(1 << 28);
2833         else
2834                 reg |= (1 << 28);
2835         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2836         ew32(TARC(1), reg);
2837
2838         /* Device Status */
2839         if (hw->mac.type == e1000_ich8lan) {
2840                 reg = er32(STATUS);
2841                 reg &= ~(1 << 31);
2842                 ew32(STATUS, reg);
2843         }
2844 }
2845
2846 /**
2847  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2848  *  @hw: pointer to the HW structure
2849  *
2850  *  Determines which flow control settings to use, then configures flow
2851  *  control.  Calls the appropriate media-specific link configuration
2852  *  function.  Assuming the adapter has a valid link partner, a valid link
2853  *  should be established.  Assumes the hardware has previously been reset
2854  *  and the transmitter and receiver are not enabled.
2855  **/
2856 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2857 {
2858         s32 ret_val;
2859
2860         if (e1000_check_reset_block(hw))
2861                 return 0;
2862
2863         /*
2864          * ICH parts do not have a word in the NVM to determine
2865          * the default flow control setting, so we explicitly
2866          * set it to full.
2867          */
2868         if (hw->fc.requested_mode == e1000_fc_default) {
2869                 /* Workaround h/w hang when Tx flow control enabled */
2870                 if (hw->mac.type == e1000_pchlan)
2871                         hw->fc.requested_mode = e1000_fc_rx_pause;
2872                 else
2873                         hw->fc.requested_mode = e1000_fc_full;
2874         }
2875
2876         /*
2877          * Save off the requested flow control mode for use later.  Depending
2878          * on the link partner's capabilities, we may or may not use this mode.
2879          */
2880         hw->fc.current_mode = hw->fc.requested_mode;
2881
2882         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2883                 hw->fc.current_mode);
2884
2885         /* Continue to configure the copper link. */
2886         ret_val = e1000_setup_copper_link_ich8lan(hw);
2887         if (ret_val)
2888                 return ret_val;
2889
2890         ew32(FCTTV, hw->fc.pause_time);
2891         if ((hw->phy.type == e1000_phy_82578) ||
2892             (hw->phy.type == e1000_phy_82577)) {
2893                 ret_val = hw->phy.ops.write_phy_reg(hw,
2894                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2895                                              hw->fc.pause_time);
2896                 if (ret_val)
2897                         return ret_val;
2898         }
2899
2900         return e1000e_set_fc_watermarks(hw);
2901 }
2902
2903 /**
2904  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2905  *  @hw: pointer to the HW structure
2906  *
2907  *  Configures the kumeran interface to the PHY to wait the appropriate time
2908  *  when polling the PHY, then call the generic setup_copper_link to finish
2909  *  configuring the copper link.
2910  **/
2911 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2912 {
2913         u32 ctrl;
2914         s32 ret_val;
2915         u16 reg_data;
2916
2917         ctrl = er32(CTRL);
2918         ctrl |= E1000_CTRL_SLU;
2919         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2920         ew32(CTRL, ctrl);
2921
2922         /*
2923          * Set the mac to wait the maximum time between each iteration
2924          * and increase the max iterations when polling the phy;
2925          * this fixes erroneous timeouts at 10Mbps.
2926          */
2927         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2928         if (ret_val)
2929                 return ret_val;
2930         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2931         if (ret_val)
2932                 return ret_val;
2933         reg_data |= 0x3F;
2934         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2935         if (ret_val)
2936                 return ret_val;
2937
2938         switch (hw->phy.type) {
2939         case e1000_phy_igp_3:
2940                 ret_val = e1000e_copper_link_setup_igp(hw);
2941                 if (ret_val)
2942                         return ret_val;
2943                 break;
2944         case e1000_phy_bm:
2945         case e1000_phy_82578:
2946                 ret_val = e1000e_copper_link_setup_m88(hw);
2947                 if (ret_val)
2948                         return ret_val;
2949                 break;
2950         case e1000_phy_82577:
2951                 ret_val = e1000_copper_link_setup_82577(hw);
2952                 if (ret_val)
2953                         return ret_val;
2954                 break;
2955         case e1000_phy_ife:
2956                 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2957                                                &reg_data);
2958                 if (ret_val)
2959                         return ret_val;
2960
2961                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2962
2963                 switch (hw->phy.mdix) {
2964                 case 1:
2965                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2966                         break;
2967                 case 2:
2968                         reg_data |= IFE_PMC_FORCE_MDIX;
2969                         break;
2970                 case 0:
2971                 default:
2972                         reg_data |= IFE_PMC_AUTO_MDIX;
2973                         break;
2974                 }
2975                 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2976                                                 reg_data);
2977                 if (ret_val)
2978                         return ret_val;
2979                 break;
2980         default:
2981                 break;
2982         }
2983         return e1000e_setup_copper_link(hw);
2984 }
2985
2986 /**
2987  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2988  *  @hw: pointer to the HW structure
2989  *  @speed: pointer to store current link speed
2990  *  @duplex: pointer to store the current link duplex
2991  *
2992  *  Calls the generic get_speed_and_duplex to retrieve the current link
2993  *  information and then calls the Kumeran lock loss workaround for links at
2994  *  gigabit speeds.
2995  **/
2996 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2997                                           u16 *duplex)
2998 {
2999         s32 ret_val;
3000
3001         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3002         if (ret_val)
3003                 return ret_val;
3004
3005         if ((hw->mac.type == e1000_ich8lan) &&
3006             (hw->phy.type == e1000_phy_igp_3) &&
3007             (*speed == SPEED_1000)) {
3008                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3009         }
3010
3011         return ret_val;
3012 }
3013
3014 /**
3015  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3016  *  @hw: pointer to the HW structure
3017  *
3018  *  Work-around for 82566 Kumeran PCS lock loss:
3019  *  On link status change (i.e. PCI reset, speed change) and link is up and
3020  *  speed is gigabit-
3021  *    0) if workaround is optionally disabled do nothing
3022  *    1) wait 1ms for Kumeran link to come up
3023  *    2) check Kumeran Diagnostic register PCS lock loss bit
3024  *    3) if not set the link is locked (all is good), otherwise...
3025  *    4) reset the PHY
3026  *    5) repeat up to 10 times
3027  *  Note: this is only called for IGP3 copper when speed is 1gb.
3028  **/
3029 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3030 {
3031         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3032         u32 phy_ctrl;
3033         s32 ret_val;
3034         u16 i, data;
3035         bool link;
3036
3037         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3038                 return 0;
3039
3040         /*
3041          * Make sure link is up before proceeding.  If not just return.
3042          * Attempting this while link is negotiating fouled up link
3043          * stability
3044          */
3045         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3046         if (!link)
3047                 return 0;
3048
3049         for (i = 0; i < 10; i++) {
3050                 /* read once to clear */
3051                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3052                 if (ret_val)
3053                         return ret_val;
3054                 /* and again to get new status */
3055                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3056                 if (ret_val)
3057                         return ret_val;
3058
3059                 /* check for PCS lock */
3060                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3061                         return 0;
3062
3063                 /* Issue PHY reset */
3064                 e1000_phy_hw_reset(hw);
3065                 mdelay(5);
3066         }
3067         /* Disable GigE link negotiation */
3068         phy_ctrl = er32(PHY_CTRL);
3069         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3070                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3071         ew32(PHY_CTRL, phy_ctrl);
3072
3073         /*
3074          * Call gig speed drop workaround on Gig disable before accessing
3075          * any PHY registers
3076          */
3077         e1000e_gig_downshift_workaround_ich8lan(hw);
3078
3079         /* unable to acquire PCS lock */
3080         return -E1000_ERR_PHY;
3081 }
3082
3083 /**
3084  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3085  *  @hw: pointer to the HW structure
3086  *  @state: boolean value used to set the current Kumeran workaround state
3087  *
3088  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
3089  *  /disabled - FALSE).
3090  **/
3091 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3092                                                  bool state)
3093 {
3094         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3095
3096         if (hw->mac.type != e1000_ich8lan) {
3097                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
3098                 return;
3099         }
3100
3101         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3102 }
3103
3104 /**
3105  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3106  *  @hw: pointer to the HW structure
3107  *
3108  *  Workaround for 82566 power-down on D3 entry:
3109  *    1) disable gigabit link
3110  *    2) write VR power-down enable
3111  *    3) read it back
3112  *  Continue if successful, else issue LCD reset and repeat
3113  **/
3114 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3115 {
3116         u32 reg;
3117         u16 data;
3118         u8  retry = 0;
3119
3120         if (hw->phy.type != e1000_phy_igp_3)
3121                 return;
3122
3123         /* Try the workaround twice (if needed) */
3124         do {
3125                 /* Disable link */
3126                 reg = er32(PHY_CTRL);
3127                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3128                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3129                 ew32(PHY_CTRL, reg);
3130
3131                 /*
3132                  * Call gig speed drop workaround on Gig disable before
3133                  * accessing any PHY registers
3134                  */
3135                 if (hw->mac.type == e1000_ich8lan)
3136                         e1000e_gig_downshift_workaround_ich8lan(hw);
3137
3138                 /* Write VR power-down enable */
3139                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3140                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3141                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3142
3143                 /* Read it back and test */
3144                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3145                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3146                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3147                         break;
3148
3149                 /* Issue PHY reset and repeat at most one more time */
3150                 reg = er32(CTRL);
3151                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3152                 retry++;
3153         } while (retry);
3154 }
3155
3156 /**
3157  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3158  *  @hw: pointer to the HW structure
3159  *
3160  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3161  *  LPLU, Gig disable, MDIC PHY reset):
3162  *    1) Set Kumeran Near-end loopback
3163  *    2) Clear Kumeran Near-end loopback
3164  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3165  **/
3166 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3167 {
3168         s32 ret_val;
3169         u16 reg_data;
3170
3171         if ((hw->mac.type != e1000_ich8lan) ||
3172             (hw->phy.type != e1000_phy_igp_3))
3173                 return;
3174
3175         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3176                                       &reg_data);
3177         if (ret_val)
3178                 return;
3179         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3180         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3181                                        reg_data);
3182         if (ret_val)
3183                 return;
3184         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3185         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3186                                        reg_data);
3187 }
3188
3189 /**
3190  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3191  *  @hw: pointer to the HW structure
3192  *
3193  *  During S0 to Sx transition, it is possible the link remains at gig
3194  *  instead of negotiating to a lower speed.  Before going to Sx, set
3195  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3196  *  to a lower speed.
3197  *
3198  *  Should only be called for applicable parts.
3199  **/
3200 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3201 {
3202         u32 phy_ctrl;
3203
3204         switch (hw->mac.type) {
3205         case e1000_ich9lan:
3206         case e1000_ich10lan:
3207         case e1000_pchlan:
3208                 phy_ctrl = er32(PHY_CTRL);
3209                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3210                             E1000_PHY_CTRL_GBE_DISABLE;
3211                 ew32(PHY_CTRL, phy_ctrl);
3212
3213                 if (hw->mac.type == e1000_pchlan)
3214                         e1000_phy_hw_reset_ich8lan(hw);
3215         default:
3216                 break;
3217         }
3218
3219         return;
3220 }
3221
3222 /**
3223  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3224  *  @hw: pointer to the HW structure
3225  *
3226  *  Return the LED back to the default configuration.
3227  **/
3228 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3229 {
3230         if (hw->phy.type == e1000_phy_ife)
3231                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3232
3233         ew32(LEDCTL, hw->mac.ledctl_default);
3234         return 0;
3235 }
3236
3237 /**
3238  *  e1000_led_on_ich8lan - Turn LEDs on
3239  *  @hw: pointer to the HW structure
3240  *
3241  *  Turn on the LEDs.
3242  **/
3243 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3244 {
3245         if (hw->phy.type == e1000_phy_ife)
3246                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3247                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3248
3249         ew32(LEDCTL, hw->mac.ledctl_mode2);
3250         return 0;
3251 }
3252
3253 /**
3254  *  e1000_led_off_ich8lan - Turn LEDs off
3255  *  @hw: pointer to the HW structure
3256  *
3257  *  Turn off the LEDs.
3258  **/
3259 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3260 {
3261         if (hw->phy.type == e1000_phy_ife)
3262                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3263                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3264
3265         ew32(LEDCTL, hw->mac.ledctl_mode1);
3266         return 0;
3267 }
3268
3269 /**
3270  *  e1000_setup_led_pchlan - Configures SW controllable LED
3271  *  @hw: pointer to the HW structure
3272  *
3273  *  This prepares the SW controllable LED for use.
3274  **/
3275 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3276 {
3277         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
3278                                         (u16)hw->mac.ledctl_mode1);
3279 }
3280
3281 /**
3282  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3283  *  @hw: pointer to the HW structure
3284  *
3285  *  Return the LED back to the default configuration.
3286  **/
3287 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3288 {
3289         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
3290                                         (u16)hw->mac.ledctl_default);
3291 }
3292
3293 /**
3294  *  e1000_led_on_pchlan - Turn LEDs on
3295  *  @hw: pointer to the HW structure
3296  *
3297  *  Turn on the LEDs.
3298  **/
3299 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3300 {
3301         u16 data = (u16)hw->mac.ledctl_mode2;
3302         u32 i, led;
3303
3304         /*
3305          * If no link, then turn LED on by setting the invert bit
3306          * for each LED that's mode is "link_up" in ledctl_mode2.
3307          */
3308         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3309                 for (i = 0; i < 3; i++) {
3310                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3311                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3312                             E1000_LEDCTL_MODE_LINK_UP)
3313                                 continue;
3314                         if (led & E1000_PHY_LED0_IVRT)
3315                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3316                         else
3317                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3318                 }
3319         }
3320
3321         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3322 }
3323
3324 /**
3325  *  e1000_led_off_pchlan - Turn LEDs off
3326  *  @hw: pointer to the HW structure
3327  *
3328  *  Turn off the LEDs.
3329  **/
3330 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3331 {
3332         u16 data = (u16)hw->mac.ledctl_mode1;
3333         u32 i, led;
3334
3335         /*
3336          * If no link, then turn LED off by clearing the invert bit
3337          * for each LED that's mode is "link_up" in ledctl_mode1.
3338          */
3339         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3340                 for (i = 0; i < 3; i++) {
3341                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3342                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3343                             E1000_LEDCTL_MODE_LINK_UP)
3344                                 continue;
3345                         if (led & E1000_PHY_LED0_IVRT)
3346                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3347                         else
3348                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3349                 }
3350         }
3351
3352         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3353 }
3354
3355 /**
3356  *  e1000_get_cfg_done_ich8lan - Read config done bit
3357  *  @hw: pointer to the HW structure
3358  *
3359  *  Read the management control register for the config done bit for
3360  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
3361  *  to read the config done bit, so an error is *ONLY* logged and returns
3362  *  0.  If we were to return with error, EEPROM-less silicon
3363  *  would not be able to be reset or change link.
3364  **/
3365 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3366 {
3367         u32 bank = 0;
3368
3369         if (hw->mac.type >= e1000_pchlan) {
3370                 u32 status = er32(STATUS);
3371
3372                 if (status & E1000_STATUS_PHYRA)
3373                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3374                 else
3375                         hw_dbg(hw,
3376                                "PHY Reset Asserted not set - needs delay\n");
3377         }
3378
3379         e1000e_get_cfg_done(hw);
3380
3381         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3382         if ((hw->mac.type != e1000_ich10lan) &&
3383             (hw->mac.type != e1000_pchlan)) {
3384                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3385                     (hw->phy.type == e1000_phy_igp_3)) {
3386                         e1000e_phy_init_script_igp3(hw);
3387                 }
3388         } else {
3389                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3390                         /* Maybe we should do a basic PHY config */
3391                         hw_dbg(hw, "EEPROM not present\n");
3392                         return -E1000_ERR_CONFIG;
3393                 }
3394         }
3395
3396         return 0;
3397 }
3398
3399 /**
3400  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3401  *  @hw: pointer to the HW structure
3402  *
3403  *  Clears hardware counters specific to the silicon family and calls
3404  *  clear_hw_cntrs_generic to clear all general purpose counters.
3405  **/
3406 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3407 {
3408         u32 temp;
3409         u16 phy_data;
3410
3411         e1000e_clear_hw_cntrs_base(hw);
3412
3413         temp = er32(ALGNERRC);
3414         temp = er32(RXERRC);
3415         temp = er32(TNCRS);
3416         temp = er32(CEXTERR);
3417         temp = er32(TSCTC);
3418         temp = er32(TSCTFC);
3419
3420         temp = er32(MGTPRC);
3421         temp = er32(MGTPDC);
3422         temp = er32(MGTPTC);
3423
3424         temp = er32(IAC);
3425         temp = er32(ICRXOC);
3426
3427         /* Clear PHY statistics registers */
3428         if ((hw->phy.type == e1000_phy_82578) ||
3429             (hw->phy.type == e1000_phy_82577)) {
3430                 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
3431                 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
3432                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
3433                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
3434                 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
3435                 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
3436                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
3437                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
3438                 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
3439                 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
3440                 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
3441                 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
3442                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
3443                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
3444         }
3445 }
3446
3447 static struct e1000_mac_operations ich8_mac_ops = {
3448         .id_led_init            = e1000e_id_led_init,
3449         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
3450         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3451         /* cleanup_led dependent on mac type */
3452         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3453         .get_bus_info           = e1000_get_bus_info_ich8lan,
3454         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3455         /* led_on dependent on mac type */
3456         /* led_off dependent on mac type */
3457         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3458         .reset_hw               = e1000_reset_hw_ich8lan,
3459         .init_hw                = e1000_init_hw_ich8lan,
3460         .setup_link             = e1000_setup_link_ich8lan,
3461         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3462         /* id_led_init dependent on mac type */
3463 };
3464
3465 static struct e1000_phy_operations ich8_phy_ops = {
3466         .acquire_phy            = e1000_acquire_swflag_ich8lan,
3467         .check_reset_block      = e1000_check_reset_block_ich8lan,
3468         .commit_phy             = NULL,
3469         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
3470         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3471         .get_cable_length       = e1000e_get_cable_length_igp_2,
3472         .get_phy_info           = e1000_get_phy_info_ich8lan,
3473         .read_phy_reg           = e1000e_read_phy_reg_igp,
3474         .release_phy            = e1000_release_swflag_ich8lan,
3475         .reset_phy              = e1000_phy_hw_reset_ich8lan,
3476         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3477         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3478         .write_phy_reg          = e1000e_write_phy_reg_igp,
3479 };
3480
3481 static struct e1000_nvm_operations ich8_nvm_ops = {
3482         .acquire_nvm            = e1000_acquire_nvm_ich8lan,
3483         .read_nvm               = e1000_read_nvm_ich8lan,
3484         .release_nvm            = e1000_release_nvm_ich8lan,
3485         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
3486         .valid_led_default      = e1000_valid_led_default_ich8lan,
3487         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
3488         .write_nvm              = e1000_write_nvm_ich8lan,
3489 };
3490
3491 struct e1000_info e1000_ich8_info = {
3492         .mac                    = e1000_ich8lan,
3493         .flags                  = FLAG_HAS_WOL
3494                                   | FLAG_IS_ICH
3495                                   | FLAG_RX_CSUM_ENABLED
3496                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3497                                   | FLAG_HAS_AMT
3498                                   | FLAG_HAS_FLASH
3499                                   | FLAG_APME_IN_WUC,
3500         .pba                    = 8,
3501         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3502         .get_variants           = e1000_get_variants_ich8lan,
3503         .mac_ops                = &ich8_mac_ops,
3504         .phy_ops                = &ich8_phy_ops,
3505         .nvm_ops                = &ich8_nvm_ops,
3506 };
3507
3508 struct e1000_info e1000_ich9_info = {
3509         .mac                    = e1000_ich9lan,
3510         .flags                  = FLAG_HAS_JUMBO_FRAMES
3511                                   | FLAG_IS_ICH
3512                                   | FLAG_HAS_WOL
3513                                   | FLAG_RX_CSUM_ENABLED
3514                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3515                                   | FLAG_HAS_AMT
3516                                   | FLAG_HAS_ERT
3517                                   | FLAG_HAS_FLASH
3518                                   | FLAG_APME_IN_WUC,
3519         .pba                    = 10,
3520         .max_hw_frame_size      = DEFAULT_JUMBO,
3521         .get_variants           = e1000_get_variants_ich8lan,
3522         .mac_ops                = &ich8_mac_ops,
3523         .phy_ops                = &ich8_phy_ops,
3524         .nvm_ops                = &ich8_nvm_ops,
3525 };
3526
3527 struct e1000_info e1000_ich10_info = {
3528         .mac                    = e1000_ich10lan,
3529         .flags                  = FLAG_HAS_JUMBO_FRAMES
3530                                   | FLAG_IS_ICH
3531                                   | FLAG_HAS_WOL
3532                                   | FLAG_RX_CSUM_ENABLED
3533                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3534                                   | FLAG_HAS_AMT
3535                                   | FLAG_HAS_ERT
3536                                   | FLAG_HAS_FLASH
3537                                   | FLAG_APME_IN_WUC,
3538         .pba                    = 10,
3539         .max_hw_frame_size      = DEFAULT_JUMBO,
3540         .get_variants           = e1000_get_variants_ich8lan,
3541         .mac_ops                = &ich8_mac_ops,
3542         .phy_ops                = &ich8_phy_ops,
3543         .nvm_ops                = &ich8_nvm_ops,
3544 };
3545
3546 struct e1000_info e1000_pch_info = {
3547         .mac                    = e1000_pchlan,
3548         .flags                  = FLAG_IS_ICH
3549                                   | FLAG_HAS_WOL
3550                                   | FLAG_RX_CSUM_ENABLED
3551                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3552                                   | FLAG_HAS_AMT
3553                                   | FLAG_HAS_FLASH
3554                                   | FLAG_HAS_JUMBO_FRAMES
3555                                   | FLAG_APME_IN_WUC,
3556         .pba                    = 26,
3557         .max_hw_frame_size      = 4096,
3558         .get_variants           = e1000_get_variants_ich8lan,
3559         .mac_ops                = &ich8_mac_ops,
3560         .phy_ops                = &ich8_phy_ops,
3561         .nvm_ops                = &ich8_nvm_ops,
3562 };