Pileus Git - ~andy/linux/blob - drivers/net/e1000e/es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  32  */
  33
  34 #include "e1000.h"
  35
  36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
  37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
  38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
  39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
  40
  41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
  42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
  43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
  44
  45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
  47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
  48
  49 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  50 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
  51
  52 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
  53 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
  54
  55 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  56 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
  57 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
  58 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
  59 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
  60 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
  61
  62 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  63 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
  64                                                 /* 1=Reverse Auto-Negotiation */
  65
  66 /* MAC Specific Control Register (Page 2, Register 21) */
  67 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  68 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
  69 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
  70 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
  71 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
  72
  73 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
  74
  75 /* DSP Distance Register (Page 5, Register 26) */
  76 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
  77                                                            1 = 50-80M
  78                                                            2 = 80-110M
  79                                                            3 = 110-140M
  80                                                            4 = >140M */
  81
  82 /* Kumeran Mode Control Register (Page 193, Register 16) */
  83 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
  84
  85 /* Max number of times Kumeran read/write should be validated */
  86 #define GG82563_MAX_KMRN_RETRY  0x5
  87
  88 /* Power Management Control Register (Page 193, Register 20) */
  89 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
  90                                            /* 1=Enable SERDES Electrical Idle */
  91
  92 /* In-Band Control Register (Page 194, Register 18) */
  93 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
  94
  95 /*
  96  * A table for the GG82563 cable length where the range is defined
  97  * with a lower bound at "index" and the upper bound at
  98  * "index + 5".
  99  */
 100 static const u16 e1000_gg82563_cable_length_table[] =
 101          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 102
 103 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
 104 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 105 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 106 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 107 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
 108 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 109 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 110 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
 111 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 112                                             u16 *data);
 113 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 114                                              u16 data);
 115
 116 /**
 117  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
 118  *  @hw: pointer to the HW structure
 119  *
 120  *  This is a function pointer entry point called by the api module.
 121  **/
 122 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 123 {
 124         struct e1000_phy_info *phy = &hw->phy;
 125         s32 ret_val;
 126
 127         if (hw->phy.media_type != e1000_media_type_copper) {
 128                 phy->type       = e1000_phy_none;
 129                 return 0;
 130         }
 131
 132         phy->addr               = 1;
 133         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 134         phy->reset_delay_us      = 100;
 135         phy->type               = e1000_phy_gg82563;
 136
 137         /* This can only be done after all function pointers are setup. */
 138         ret_val = e1000e_get_phy_id(hw);
 139
 140         /* Verify phy id */
 141         if (phy->id != GG82563_E_PHY_ID)
 142                 return -E1000_ERR_PHY;
 143
 144         return ret_val;
 145 }
 146
 147 /**
 148  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 149  *  @hw: pointer to the HW structure
 150  *
 151  *  This is a function pointer entry point called by the api module.
 152  **/
 153 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 154 {
 155         struct e1000_nvm_info *nvm = &hw->nvm;
 156         u32 eecd = er32(EECD);
 157         u16 size;
 158
 159         nvm->opcode_bits        = 8;
 160         nvm->delay_usec  = 1;
 161         switch (nvm->override) {
 162         case e1000_nvm_override_spi_large:
 163                 nvm->page_size    = 32;
 164                 nvm->address_bits = 16;
 165                 break;
 166         case e1000_nvm_override_spi_small:
 167                 nvm->page_size    = 8;
 168                 nvm->address_bits = 8;
 169                 break;
 170         default:
 171                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 172                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 173                 break;
 174         }
 175
 176         nvm->type = e1000_nvm_eeprom_spi;
 177
 178         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 179                           E1000_EECD_SIZE_EX_SHIFT);
 180
 181         /*
 182          * Added to a constant, "size" becomes the left-shift value
 183          * for setting word_size.
 184          */
 185         size += NVM_WORD_SIZE_BASE_SHIFT;
 186
 187         /* EEPROM access above 16k is unsupported */
 188         if (size > 14)
 189                 size = 14;
 190         nvm->word_size  = 1 << size;
 191
 192         return 0;
 193 }
 194
 195 /**
 196  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 197  *  @hw: pointer to the HW structure
 198  *
 199  *  This is a function pointer entry point called by the api module.
 200  **/
 201 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
 202 {
 203         struct e1000_hw *hw = &adapter->hw;
 204         struct e1000_mac_info *mac = &hw->mac;
 205         struct e1000_mac_operations *func = &mac->ops;
 206
 207         /* Set media type */
 208         switch (adapter->pdev->device) {
 209         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 210                 hw->phy.media_type = e1000_media_type_internal_serdes;
 211                 break;
 212         default:
 213                 hw->phy.media_type = e1000_media_type_copper;
 214                 break;
 215         }
 216
 217         /* Set mta register count */
 218         mac->mta_reg_count = 128;
 219         /* Set rar entry count */
 220         mac->rar_entry_count = E1000_RAR_ENTRIES;
 221         /* Set if manageability features are enabled. */
 222         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
 223
 224         /* check for link */
 225         switch (hw->phy.media_type) {
 226         case e1000_media_type_copper:
 227                 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
 228                 func->check_for_link = e1000e_check_for_copper_link;
 229                 break;
 230         case e1000_media_type_fiber:
 231                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 232                 func->check_for_link = e1000e_check_for_fiber_link;
 233                 break;
 234         case e1000_media_type_internal_serdes:
 235                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 236                 func->check_for_link = e1000e_check_for_serdes_link;
 237                 break;
 238         default:
 239                 return -E1000_ERR_CONFIG;
 240                 break;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 247 {
 248         struct e1000_hw *hw = &adapter->hw;
 249         s32 rc;
 250
 251         rc = e1000_init_mac_params_80003es2lan(adapter);
 252         if (rc)
 253                 return rc;
 254
 255         rc = e1000_init_nvm_params_80003es2lan(hw);
 256         if (rc)
 257                 return rc;
 258
 259         rc = e1000_init_phy_params_80003es2lan(hw);
 260         if (rc)
 261                 return rc;
 262
 263         return 0;
 264 }
 265
 266 /**
 267  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 268  *  @hw: pointer to the HW structure
 269  *
 270  *  A wrapper to acquire access rights to the correct PHY.  This is a
 271  *  function pointer entry point called by the api module.
 272  **/
 273 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 274 {
 275         u16 mask;
 276
 277         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 278         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 279 }
 280
 281 /**
 282  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  A wrapper to release access rights to the correct PHY.  This is a
 286  *  function pointer entry point called by the api module.
 287  **/
 288 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 289 {
 290         u16 mask;
 291
 292         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 293         e1000_release_swfw_sync_80003es2lan(hw, mask);
 294 }
 295
 296 /**
 297  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
 298  *  @hw: pointer to the HW structure
 299  *
 300  *  Acquire the semaphore to access the Kumeran interface.
 301  *
 302  **/
 303 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 304 {
 305         u16 mask;
 306
 307         mask = E1000_SWFW_CSR_SM;
 308
 309         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 310 }
 311
 312 /**
 313  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
 314  *  @hw: pointer to the HW structure
 315  *
 316  *  Release the semaphore used to access the Kumeran interface
 317  **/
 318 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 319 {
 320         u16 mask;
 321
 322         mask = E1000_SWFW_CSR_SM;
 323
 324         e1000_release_swfw_sync_80003es2lan(hw, mask);
 325 }
 326
 327 /**
 328  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 329  *  @hw: pointer to the HW structure
 330  *
 331  *  Acquire the semaphore to access the EEPROM.  This is a function
 332  *  pointer entry point called by the api module.
 333  **/
 334 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 335 {
 336         s32 ret_val;
 337
 338         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 339         if (ret_val)
 340                 return ret_val;
 341
 342         ret_val = e1000e_acquire_nvm(hw);
 343
 344         if (ret_val)
 345                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 346
 347         return ret_val;
 348 }
 349
 350 /**
 351  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 352  *  @hw: pointer to the HW structure
 353  *
 354  *  Release the semaphore used to access the EEPROM.  This is a
 355  *  function pointer entry point called by the api module.
 356  **/
 357 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 358 {
 359         e1000e_release_nvm(hw);
 360         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 361 }
 362
 363 /**
 364  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 365  *  @hw: pointer to the HW structure
 366  *  @mask: specifies which semaphore to acquire
 367  *
 368  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 369  *  will also specify which port we're acquiring the lock for.
 370  **/
 371 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 372 {
 373         u32 swfw_sync;
 374         u32 swmask = mask;
 375         u32 fwmask = mask << 16;
 376         s32 i = 0;
 377         s32 timeout = 50;
 378
 379         while (i < timeout) {
 380                 if (e1000e_get_hw_semaphore(hw))
 381                         return -E1000_ERR_SWFW_SYNC;
 382
 383                 swfw_sync = er32(SW_FW_SYNC);
 384                 if (!(swfw_sync & (fwmask | swmask)))
 385                         break;
 386
 387                 /*
 388                  * Firmware currently using resource (fwmask)
 389                  * or other software thread using resource (swmask)
 390                  */
 391                 e1000e_put_hw_semaphore(hw);
 392                 mdelay(5);
 393                 i++;
 394         }
 395
 396         if (i == timeout) {
 397                 hw_dbg(hw,
 398                        "Driver can't access resource, SW_FW_SYNC timeout.\n");
 399                 return -E1000_ERR_SWFW_SYNC;
 400         }
 401
 402         swfw_sync |= swmask;
 403         ew32(SW_FW_SYNC, swfw_sync);
 404
 405         e1000e_put_hw_semaphore(hw);
 406
 407         return 0;
 408 }
 409
 410 /**
 411  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 412  *  @hw: pointer to the HW structure
 413  *  @mask: specifies which semaphore to acquire
 414  *
 415  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 416  *  will also specify which port we're releasing the lock for.
 417  **/
 418 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 419 {
 420         u32 swfw_sync;
 421
 422         while (e1000e_get_hw_semaphore(hw) != 0);
 423         /* Empty */
 424
 425         swfw_sync = er32(SW_FW_SYNC);
 426         swfw_sync &= ~mask;
 427         ew32(SW_FW_SYNC, swfw_sync);
 428
 429         e1000e_put_hw_semaphore(hw);
 430 }
 431
 432 /**
 433  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 434  *  @hw: pointer to the HW structure
 435  *  @offset: offset of the register to read
 436  *  @data: pointer to the data returned from the operation
 437  *
 438  *  Read the GG82563 PHY register.  This is a function pointer entry
 439  *  point called by the api module.
 440  **/
 441 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 442                                                   u32 offset, u16 *data)
 443 {
 444         s32 ret_val;
 445         u32 page_select;
 446         u16 temp;
 447
 448         ret_val = e1000_acquire_phy_80003es2lan(hw);
 449         if (ret_val)
 450                 return ret_val;
 451
 452         /* Select Configuration Page */
 453         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 454                 page_select = GG82563_PHY_PAGE_SELECT;
 455         } else {
 456                 /*
 457                  * Use Alternative Page Select register to access
 458                  * registers 30 and 31
 459                  */
 460                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 461         }
 462
 463         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 464         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 465         if (ret_val) {
 466                 e1000_release_phy_80003es2lan(hw);
 467                 return ret_val;
 468         }
 469
 470         /*
 471          * The "ready" bit in the MDIC register may be incorrectly set
 472          * before the device has completed the "Page Select" MDI
 473          * transaction.  So we wait 200us after each MDI command...
 474          */
 475         udelay(200);
 476
 477         /* ...and verify the command was successful. */
 478         ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 479
 480         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 481                 ret_val = -E1000_ERR_PHY;
 482                 e1000_release_phy_80003es2lan(hw);
 483                 return ret_val;
 484         }
 485
 486         udelay(200);
 487
 488         ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
 489                                            data);
 490
 491         udelay(200);
 492         e1000_release_phy_80003es2lan(hw);
 493
 494         return ret_val;
 495 }
 496
 497 /**
 498  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 499  *  @hw: pointer to the HW structure
 500  *  @offset: offset of the register to read
 501  *  @data: value to write to the register
 502  *
 503  *  Write to the GG82563 PHY register.  This is a function pointer entry
 504  *  point called by the api module.
 505  **/
 506 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 507                                                    u32 offset, u16 data)
 508 {
 509         s32 ret_val;
 510         u32 page_select;
 511         u16 temp;
 512
 513         ret_val = e1000_acquire_phy_80003es2lan(hw);
 514         if (ret_val)
 515                 return ret_val;
 516
 517         /* Select Configuration Page */
 518         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 519                 page_select = GG82563_PHY_PAGE_SELECT;
 520         } else {
 521                 /*
 522                  * Use Alternative Page Select register to access
 523                  * registers 30 and 31
 524                  */
 525                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 526         }
 527
 528         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 529         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 530         if (ret_val) {
 531                 e1000_release_phy_80003es2lan(hw);
 532                 return ret_val;
 533         }
 534
 535
 536         /*
 537          * The "ready" bit in the MDIC register may be incorrectly set
 538          * before the device has completed the "Page Select" MDI
 539          * transaction.  So we wait 200us after each MDI command...
 540          */
 541         udelay(200);
 542
 543         /* ...and verify the command was successful. */
 544         ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 545
 546         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 547                 e1000_release_phy_80003es2lan(hw);
 548                 return -E1000_ERR_PHY;
 549         }
 550
 551         udelay(200);
 552
 553         ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
 554                                             data);
 555
 556         udelay(200);
 557         e1000_release_phy_80003es2lan(hw);
 558
 559         return ret_val;
 560 }
 561
 562 /**
 563  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 564  *  @hw: pointer to the HW structure
 565  *  @offset: offset of the register to read
 566  *  @words: number of words to write
 567  *  @data: buffer of data to write to the NVM
 568  *
 569  *  Write "words" of data to the ESB2 NVM.  This is a function
 570  *  pointer entry point called by the api module.
 571  **/
 572 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 573                                        u16 words, u16 *data)
 574 {
 575         return e1000e_write_nvm_spi(hw, offset, words, data);
 576 }
 577
 578 /**
 579  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 580  *  @hw: pointer to the HW structure
 581  *
 582  *  Wait a specific amount of time for manageability processes to complete.
 583  *  This is a function pointer entry point called by the phy module.
 584  **/
 585 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 586 {
 587         s32 timeout = PHY_CFG_TIMEOUT;
 588         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 589
 590         if (hw->bus.func == 1)
 591                 mask = E1000_NVM_CFG_DONE_PORT_1;
 592
 593         while (timeout) {
 594                 if (er32(EEMNGCTL) & mask)
 595                         break;
 596                 msleep(1);
 597                 timeout--;
 598         }
 599         if (!timeout) {
 600                 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
 601                 return -E1000_ERR_RESET;
 602         }
 603
 604         return 0;
 605 }
 606
 607 /**
 608  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 609  *  @hw: pointer to the HW structure
 610  *
 611  *  Force the speed and duplex settings onto the PHY.  This is a
 612  *  function pointer entry point called by the phy module.
 613  **/
 614 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 615 {
 616         s32 ret_val;
 617         u16 phy_data;
 618         bool link;
 619
 620         /*
 621          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 622          * forced whenever speed and duplex are forced.
 623          */
 624         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 625         if (ret_val)
 626                 return ret_val;
 627
 628         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 629         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 630         if (ret_val)
 631                 return ret_val;
 632
 633         hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data);
 634
 635         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
 636         if (ret_val)
 637                 return ret_val;
 638
 639         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 640
 641         /* Reset the phy to commit changes. */
 642         phy_data |= MII_CR_RESET;
 643
 644         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
 645         if (ret_val)
 646                 return ret_val;
 647
 648         udelay(1);
 649
 650         if (hw->phy.autoneg_wait_to_complete) {
 651                 hw_dbg(hw, "Waiting for forced speed/duplex link "
 652                          "on GG82563 phy.\n");
 653
 654                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 655                                                      100000, &link);
 656                 if (ret_val)
 657                         return ret_val;
 658
 659                 if (!link) {
 660                         /*
 661                          * We didn't get link.
 662                          * Reset the DSP and cross our fingers.
 663                          */
 664                         ret_val = e1000e_phy_reset_dsp(hw);
 665                         if (ret_val)
 666                                 return ret_val;
 667                 }
 668
 669                 /* Try once more */
 670                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 671                                                      100000, &link);
 672                 if (ret_val)
 673                         return ret_val;
 674         }
 675
 676         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 677         if (ret_val)
 678                 return ret_val;
 679
 680         /*
 681          * Resetting the phy means we need to verify the TX_CLK corresponds
 682          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 683          */
 684         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 685         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 686                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 687         else
 688                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 689
 690         /*
 691          * In addition, we must re-enable CRS on Tx for both half and full
 692          * duplex.
 693          */
 694         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 695         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 696
 697         return ret_val;
 698 }
 699
 700 /**
 701  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 702  *  @hw: pointer to the HW structure
 703  *
 704  *  Find the approximate cable length as measured by the GG82563 PHY.
 705  *  This is a function pointer entry point called by the phy module.
 706  **/
 707 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 708 {
 709         struct e1000_phy_info *phy = &hw->phy;
 710         s32 ret_val;
 711         u16 phy_data;
 712         u16 index;
 713
 714         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 715         if (ret_val)
 716                 return ret_val;
 717
 718         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 719         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 720         phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
 721
 722         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 723
 724         return 0;
 725 }
 726
 727 /**
 728  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 729  *  @hw: pointer to the HW structure
 730  *  @speed: pointer to speed buffer
 731  *  @duplex: pointer to duplex buffer
 732  *
 733  *  Retrieve the current speed and duplex configuration.
 734  *  This is a function pointer entry point called by the api module.
 735  **/
 736 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 737                                               u16 *duplex)
 738 {
 739         s32 ret_val;
 740
 741         if (hw->phy.media_type == e1000_media_type_copper) {
 742                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
 743                                                                     speed,
 744                                                                     duplex);
 745                 hw->phy.ops.cfg_on_link_up(hw);
 746         } else {
 747                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 748                                                                   speed,
 749                                                                   duplex);
 750         }
 751
 752         return ret_val;
 753 }
 754
 755 /**
 756  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 757  *  @hw: pointer to the HW structure
 758  *
 759  *  Perform a global reset to the ESB2 controller.
 760  *  This is a function pointer entry point called by the api module.
 761  **/
 762 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 763 {
 764         u32 ctrl;
 765         u32 icr;
 766         s32 ret_val;
 767
 768         /*
 769          * Prevent the PCI-E bus from sticking if there is no TLP connection
 770          * on the last TLP read/write transaction when MAC is reset.
 771          */
 772         ret_val = e1000e_disable_pcie_master(hw);
 773         if (ret_val)
 774                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 775
 776         hw_dbg(hw, "Masking off all interrupts\n");
 777         ew32(IMC, 0xffffffff);
 778
 779         ew32(RCTL, 0);
 780         ew32(TCTL, E1000_TCTL_PSP);
 781         e1e_flush();
 782
 783         msleep(10);
 784
 785         ctrl = er32(CTRL);
 786
 787         ret_val = e1000_acquire_phy_80003es2lan(hw);
 788         hw_dbg(hw, "Issuing a global reset to MAC\n");
 789         ew32(CTRL, ctrl | E1000_CTRL_RST);
 790         e1000_release_phy_80003es2lan(hw);
 791
 792         ret_val = e1000e_get_auto_rd_done(hw);
 793         if (ret_val)
 794                 /* We don't want to continue accessing MAC registers. */
 795                 return ret_val;
 796
 797         /* Clear any pending interrupt events. */
 798         ew32(IMC, 0xffffffff);
 799         icr = er32(ICR);
 800
 801         return 0;
 802 }
 803
 804 /**
 805  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 806  *  @hw: pointer to the HW structure
 807  *
 808  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 809  *  This is a function pointer entry point called by the api module.
 810  **/
 811 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 812 {
 813         struct e1000_mac_info *mac = &hw->mac;
 814         u32 reg_data;
 815         s32 ret_val;
 816         u16 i;
 817
 818         e1000_initialize_hw_bits_80003es2lan(hw);
 819
 820         /* Initialize identification LED */
 821         ret_val = e1000e_id_led_init(hw);
 822         if (ret_val) {
 823                 hw_dbg(hw, "Error initializing identification LED\n");
 824                 return ret_val;
 825         }
 826
 827         /* Disabling VLAN filtering */
 828         hw_dbg(hw, "Initializing the IEEE VLAN\n");
 829         e1000e_clear_vfta(hw);
 830
 831         /* Setup the receive address. */
 832         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 833
 834         /* Zero out the Multicast HASH table */
 835         hw_dbg(hw, "Zeroing the MTA\n");
 836         for (i = 0; i < mac->mta_reg_count; i++)
 837                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 838
 839         /* Setup link and flow control */
 840         ret_val = e1000e_setup_link(hw);
 841
 842         /* Set the transmit descriptor write-back policy */
 843         reg_data = er32(TXDCTL(0));
 844         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 845                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 846         ew32(TXDCTL(0), reg_data);
 847
 848         /* ...for both queues. */
 849         reg_data = er32(TXDCTL(1));
 850         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 851                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 852         ew32(TXDCTL(1), reg_data);
 853
 854         /* Enable retransmit on late collisions */
 855         reg_data = er32(TCTL);
 856         reg_data |= E1000_TCTL_RTLC;
 857         ew32(TCTL, reg_data);
 858
 859         /* Configure Gigabit Carry Extend Padding */
 860         reg_data = er32(TCTL_EXT);
 861         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 862         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 863         ew32(TCTL_EXT, reg_data);
 864
 865         /* Configure Transmit Inter-Packet Gap */
 866         reg_data = er32(TIPG);
 867         reg_data &= ~E1000_TIPG_IPGT_MASK;
 868         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 869         ew32(TIPG, reg_data);
 870
 871         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 872         reg_data &= ~0x00100000;
 873         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 874
 875         /*
 876          * Clear all of the statistics registers (clear on read).  It is
 877          * important that we do this after we have tried to establish link
 878          * because the symbol error count will increment wildly if there
 879          * is no link.
 880          */
 881         e1000_clear_hw_cntrs_80003es2lan(hw);
 882
 883         return ret_val;
 884 }
 885
 886 /**
 887  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 888  *  @hw: pointer to the HW structure
 889  *
 890  *  Initializes required hardware-dependent bits needed for normal operation.
 891  **/
 892 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 893 {
 894         u32 reg;
 895
 896         /* Transmit Descriptor Control 0 */
 897         reg = er32(TXDCTL(0));
 898         reg |= (1 << 22);
 899         ew32(TXDCTL(0), reg);
 900
 901         /* Transmit Descriptor Control 1 */
 902         reg = er32(TXDCTL(1));
 903         reg |= (1 << 22);
 904         ew32(TXDCTL(1), reg);
 905
 906         /* Transmit Arbitration Control 0 */
 907         reg = er32(TARC(0));
 908         reg &= ~(0xF << 27); /* 30:27 */
 909         if (hw->phy.media_type != e1000_media_type_copper)
 910                 reg &= ~(1 << 20);
 911         ew32(TARC(0), reg);
 912
 913         /* Transmit Arbitration Control 1 */
 914         reg = er32(TARC(1));
 915         if (er32(TCTL) & E1000_TCTL_MULR)
 916                 reg &= ~(1 << 28);
 917         else
 918                 reg |= (1 << 28);
 919         ew32(TARC(1), reg);
 920 }
 921
 922 /**
 923  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 924  *  @hw: pointer to the HW structure
 925  *
 926  *  Setup some GG82563 PHY registers for obtaining link
 927  **/
 928 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 929 {
 930         struct e1000_phy_info *phy = &hw->phy;
 931         s32 ret_val;
 932         u32 ctrl_ext;
 933         u16 data;
 934
 935         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 936         if (ret_val)
 937                 return ret_val;
 938
 939         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 940         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 941         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 942
 943         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 944         if (ret_val)
 945                 return ret_val;
 946
 947         /*
 948          * Options:
 949          *   MDI/MDI-X = 0 (default)
 950          *   0 - Auto for all speeds
 951          *   1 - MDI mode
 952          *   2 - MDI-X mode
 953          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 954          */
 955         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 956         if (ret_val)
 957                 return ret_val;
 958
 959         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 960
 961         switch (phy->mdix) {
 962         case 1:
 963                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 964                 break;
 965         case 2:
 966                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 967                 break;
 968         case 0:
 969         default:
 970                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 971                 break;
 972         }
 973
 974         /*
 975          * Options:
 976          *   disable_polarity_correction = 0 (default)
 977          *       Automatic Correction for Reversed Cable Polarity
 978          *   0 - Disabled
 979          *   1 - Enabled
 980          */
 981         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 982         if (phy->disable_polarity_correction)
 983                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 984
 985         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
 986         if (ret_val)
 987                 return ret_val;
 988
 989         /* SW Reset the PHY so all changes take effect */
 990         ret_val = e1000e_commit_phy(hw);
 991         if (ret_val) {
 992                 hw_dbg(hw, "Error Resetting the PHY\n");
 993                 return ret_val;
 994         }
 995
 996         /* Bypass Rx and Tx FIFO's */
 997         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
 998                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
 999                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1000                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1001         if (ret_val)
1002                 return ret_val;
1003
1004         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1005                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1006                                        &data);
1007         if (ret_val)
1008                 return ret_val;
1009         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1010         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1011                                         E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1012                                         data);
1013         if (ret_val)
1014                 return ret_val;
1015
1016         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1017         if (ret_val)
1018                 return ret_val;
1019
1020         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1021         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1022         if (ret_val)
1023                 return ret_val;
1024
1025         ctrl_ext = er32(CTRL_EXT);
1026         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1027         ew32(CTRL_EXT, ctrl_ext);
1028
1029         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1030         if (ret_val)
1031                 return ret_val;
1032
1033         /*
1034          * Do not init these registers when the HW is in IAMT mode, since the
1035          * firmware will have already initialized them.  We only initialize
1036          * them if the HW is not in IAMT mode.
1037          */
1038         if (!e1000e_check_mng_mode(hw)) {
1039                 /* Enable Electrical Idle on the PHY */
1040                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1041                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1042                 if (ret_val)
1043                         return ret_val;
1044
1045                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1046                 if (ret_val)
1047                         return ret_val;
1048
1049                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1050                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1051                 if (ret_val)
1052                         return ret_val;
1053         }
1054
1055         /*
1056          * Workaround: Disable padding in Kumeran interface in the MAC
1057          * and in the PHY to avoid CRC errors.
1058          */
1059         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1060         if (ret_val)
1061                 return ret_val;
1062
1063         data |= GG82563_ICR_DIS_PADDING;
1064         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1065         if (ret_val)
1066                 return ret_val;
1067
1068         return 0;
1069 }
1070
1071 /**
1072  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1073  *  @hw: pointer to the HW structure
1074  *
1075  *  Essentially a wrapper for setting up all things "copper" related.
1076  *  This is a function pointer entry point called by the mac module.
1077  **/
1078 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1079 {
1080         u32 ctrl;
1081         s32 ret_val;
1082         u16 reg_data;
1083
1084         ctrl = er32(CTRL);
1085         ctrl |= E1000_CTRL_SLU;
1086         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1087         ew32(CTRL, ctrl);
1088
1089         /*
1090          * Set the mac to wait the maximum time between each
1091          * iteration and increase the max iterations when
1092          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1093          */
1094         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1095                                                    0xFFFF);
1096         if (ret_val)
1097                 return ret_val;
1098         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1099                                                   &reg_data);
1100         if (ret_val)
1101                 return ret_val;
1102         reg_data |= 0x3F;
1103         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1104                                                    reg_data);
1105         if (ret_val)
1106                 return ret_val;
1107         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1108                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1109                                       &reg_data);
1110         if (ret_val)
1111                 return ret_val;
1112         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1113         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1114                                         E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1115                                         reg_data);
1116         if (ret_val)
1117                 return ret_val;
1118
1119         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1120         if (ret_val)
1121                 return ret_val;
1122
1123         ret_val = e1000e_setup_copper_link(hw);
1124
1125         return 0;
1126 }
1127
1128 /**
1129  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1130  *  @hw: pointer to the HW structure
1131  *  @duplex: current duplex setting
1132  *
1133  *  Configure the KMRN interface by applying last minute quirks for
1134  *  10/100 operation.
1135  **/
1136 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1137 {
1138         s32 ret_val = 0;
1139         u16 speed;
1140         u16 duplex;
1141
1142         if (hw->phy.media_type == e1000_media_type_copper) {
1143                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1144                                                              &duplex);
1145                 if (ret_val)
1146                         return ret_val;
1147
1148                 if (speed == SPEED_1000)
1149                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1150                 else
1151                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1152         }
1153
1154         return ret_val;
1155 }
1156
1157 /**
1158  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1159  *  @hw: pointer to the HW structure
1160  *  @duplex: current duplex setting
1161  *
1162  *  Configure the KMRN interface by applying last minute quirks for
1163  *  10/100 operation.
1164  **/
1165 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1166 {
1167         s32 ret_val;
1168         u32 tipg;
1169         u32 i = 0;
1170         u16 reg_data, reg_data2;
1171
1172         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1173         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1174                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1175                                        reg_data);
1176         if (ret_val)
1177                 return ret_val;
1178
1179         /* Configure Transmit Inter-Packet Gap */
1180         tipg = er32(TIPG);
1181         tipg &= ~E1000_TIPG_IPGT_MASK;
1182         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1183         ew32(TIPG, tipg);
1184
1185         do {
1186                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1187                 if (ret_val)
1188                         return ret_val;
1189
1190                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1191                 if (ret_val)
1192                         return ret_val;
1193                 i++;
1194         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1195
1196         if (duplex == HALF_DUPLEX)
1197                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1198         else
1199                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1200
1201         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1202
1203         return 0;
1204 }
1205
1206 /**
1207  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1208  *  @hw: pointer to the HW structure
1209  *
1210  *  Configure the KMRN interface by applying last minute quirks for
1211  *  gigabit operation.
1212  **/
1213 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1214 {
1215         s32 ret_val;
1216         u16 reg_data, reg_data2;
1217         u32 tipg;
1218         u32 i = 0;
1219
1220         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1221         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1222                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1223                                        reg_data);
1224         if (ret_val)
1225                 return ret_val;
1226
1227         /* Configure Transmit Inter-Packet Gap */
1228         tipg = er32(TIPG);
1229         tipg &= ~E1000_TIPG_IPGT_MASK;
1230         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1231         ew32(TIPG, tipg);
1232
1233         do {
1234                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1235                 if (ret_val)
1236                         return ret_val;
1237
1238                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1239                 if (ret_val)
1240                         return ret_val;
1241                 i++;
1242         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1243
1244         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1245         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1246
1247         return ret_val;
1248 }
1249
1250 /**
1251  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1252  *  @hw: pointer to the HW structure
1253  *  @offset: register offset to be read
1254  *  @data: pointer to the read data
1255  *
1256  *  Acquire semaphore, then read the PHY register at offset
1257  *  using the kumeran interface.  The information retrieved is stored in data.
1258  *  Release the semaphore before exiting.
1259  **/
1260 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1261                                            u16 *data)
1262 {
1263         u32 kmrnctrlsta;
1264         s32 ret_val = 0;
1265
1266         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1267         if (ret_val)
1268                 return ret_val;
1269
1270         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1271                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1272         ew32(KMRNCTRLSTA, kmrnctrlsta);
1273
1274         udelay(2);
1275
1276         kmrnctrlsta = er32(KMRNCTRLSTA);
1277         *data = (u16)kmrnctrlsta;
1278
1279         e1000_release_mac_csr_80003es2lan(hw);
1280
1281         return ret_val;
1282 }
1283
1284 /**
1285  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1286  *  @hw: pointer to the HW structure
1287  *  @offset: register offset to write to
1288  *  @data: data to write at register offset
1289  *
1290  *  Acquire semaphore, then write the data to PHY register
1291  *  at the offset using the kumeran interface.  Release semaphore
1292  *  before exiting.
1293  **/
1294 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1295                                             u16 data)
1296 {
1297         u32 kmrnctrlsta;
1298         s32 ret_val = 0;
1299
1300         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1301         if (ret_val)
1302                 return ret_val;
1303
1304         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1305                        E1000_KMRNCTRLSTA_OFFSET) | data;
1306         ew32(KMRNCTRLSTA, kmrnctrlsta);
1307
1308         udelay(2);
1309
1310         e1000_release_mac_csr_80003es2lan(hw);
1311
1312         return ret_val;
1313 }
1314
1315 /**
1316  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1317  *  @hw: pointer to the HW structure
1318  *
1319  *  Clears the hardware counters by reading the counter registers.
1320  **/
1321 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1322 {
1323         u32 temp;
1324
1325         e1000e_clear_hw_cntrs_base(hw);
1326
1327         temp = er32(PRC64);
1328         temp = er32(PRC127);
1329         temp = er32(PRC255);
1330         temp = er32(PRC511);
1331         temp = er32(PRC1023);
1332         temp = er32(PRC1522);
1333         temp = er32(PTC64);
1334         temp = er32(PTC127);
1335         temp = er32(PTC255);
1336         temp = er32(PTC511);
1337         temp = er32(PTC1023);
1338         temp = er32(PTC1522);
1339
1340         temp = er32(ALGNERRC);
1341         temp = er32(RXERRC);
1342         temp = er32(TNCRS);
1343         temp = er32(CEXTERR);
1344         temp = er32(TSCTC);
1345         temp = er32(TSCTFC);
1346
1347         temp = er32(MGTPRC);
1348         temp = er32(MGTPDC);
1349         temp = er32(MGTPTC);
1350
1351         temp = er32(IAC);
1352         temp = er32(ICRXOC);
1353
1354         temp = er32(ICRXPTC);
1355         temp = er32(ICRXATC);
1356         temp = er32(ICTXPTC);
1357         temp = er32(ICTXATC);
1358         temp = er32(ICTXQEC);
1359         temp = er32(ICTXQMTC);
1360         temp = er32(ICRXDMTC);
1361 }
1362
1363 static struct e1000_mac_operations es2_mac_ops = {
1364         .id_led_init            = e1000e_id_led_init,
1365         .check_mng_mode         = e1000e_check_mng_mode_generic,
1366         /* check_for_link dependent on media type */
1367         .cleanup_led            = e1000e_cleanup_led_generic,
1368         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1369         .get_bus_info           = e1000e_get_bus_info_pcie,
1370         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1371         .led_on                 = e1000e_led_on_generic,
1372         .led_off                = e1000e_led_off_generic,
1373         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1374         .reset_hw               = e1000_reset_hw_80003es2lan,
1375         .init_hw                = e1000_init_hw_80003es2lan,
1376         .setup_link             = e1000e_setup_link,
1377         /* setup_physical_interface dependent on media type */
1378         .setup_led              = e1000e_setup_led_generic,
1379 };
1380
1381 static struct e1000_phy_operations es2_phy_ops = {
1382         .acquire_phy            = e1000_acquire_phy_80003es2lan,
1383         .check_reset_block      = e1000e_check_reset_block_generic,
1384         .commit_phy             = e1000e_phy_sw_reset,
1385         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1386         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1387         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1388         .get_phy_info           = e1000e_get_phy_info_m88,
1389         .read_phy_reg           = e1000_read_phy_reg_gg82563_80003es2lan,
1390         .release_phy            = e1000_release_phy_80003es2lan,
1391         .reset_phy              = e1000e_phy_hw_reset_generic,
1392         .set_d0_lplu_state      = NULL,
1393         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1394         .write_phy_reg          = e1000_write_phy_reg_gg82563_80003es2lan,
1395         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1396 };
1397
1398 static struct e1000_nvm_operations es2_nvm_ops = {
1399         .acquire_nvm            = e1000_acquire_nvm_80003es2lan,
1400         .read_nvm               = e1000e_read_nvm_eerd,
1401         .release_nvm            = e1000_release_nvm_80003es2lan,
1402         .update_nvm             = e1000e_update_nvm_checksum_generic,
1403         .valid_led_default      = e1000e_valid_led_default,
1404         .validate_nvm           = e1000e_validate_nvm_checksum_generic,
1405         .write_nvm              = e1000_write_nvm_80003es2lan,
1406 };
1407
1408 struct e1000_info e1000_es2_info = {
1409         .mac                    = e1000_80003es2lan,
1410         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1411                                   | FLAG_HAS_JUMBO_FRAMES
1412                                   | FLAG_HAS_WOL
1413                                   | FLAG_APME_IN_CTRL3
1414                                   | FLAG_RX_CSUM_ENABLED
1415                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1416                                   | FLAG_RX_NEEDS_RESTART /* errata */
1417                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1418                                   | FLAG_APME_CHECK_PORT_B
1419                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1420                                   | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1421         .pba                    = 38,
1422         .max_hw_frame_size      = DEFAULT_JUMBO,
1423         .get_variants           = e1000_get_variants_80003es2lan,
1424         .mac_ops                = &es2_mac_ops,
1425         .phy_ops                = &es2_phy_ops,
1426         .nvm_ops                = &es2_nvm_ops,
1427 };
1428