1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #ifndef _E1000_DEFINES_H_
30 #define _E1000_DEFINES_H_
32 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
33 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
34 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
35 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
36 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
37 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
38 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
39 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
40 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
41 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
42 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
43 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
44 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
45 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
46 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
47 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
48 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
49 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
51 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
52 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
53 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
55 /* Definitions for power management and wakeup registers */
57 #define E1000_WUC_APME 0x00000001 /* APM Enable */
58 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
59 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
61 /* Wake Up Filter Control */
62 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
63 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
64 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
65 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
66 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
67 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
70 #define E1000_WUS_LNKC E1000_WUFC_LNKC
71 #define E1000_WUS_MAG E1000_WUFC_MAG
72 #define E1000_WUS_EX E1000_WUFC_EX
73 #define E1000_WUS_MC E1000_WUFC_MC
74 #define E1000_WUS_BC E1000_WUFC_BC
76 /* Extended Device Control */
77 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */
78 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
79 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
80 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
81 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
82 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
83 #define E1000_CTRL_EXT_EIAME 0x01000000
84 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
85 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
86 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
87 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
88 #define E1000_CTRL_EXT_PHYPDEN 0x00100000
90 /* Receive Descriptor bit definitions */
91 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
92 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
93 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
94 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
95 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
96 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
97 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
98 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
99 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
100 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
101 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
102 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
103 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
105 #define E1000_RXDEXT_STATERR_CE 0x01000000
106 #define E1000_RXDEXT_STATERR_SE 0x02000000
107 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
108 #define E1000_RXDEXT_STATERR_CXE 0x10000000
109 #define E1000_RXDEXT_STATERR_RXE 0x80000000
111 /* mask to determine if packets should be dropped due to frame errors */
112 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
115 E1000_RXD_ERR_SEQ | \
116 E1000_RXD_ERR_CXE | \
119 /* Same mask, but for extended and packet split descriptors */
120 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
121 E1000_RXDEXT_STATERR_CE | \
122 E1000_RXDEXT_STATERR_SE | \
123 E1000_RXDEXT_STATERR_SEQ | \
124 E1000_RXDEXT_STATERR_CXE | \
125 E1000_RXDEXT_STATERR_RXE)
127 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
129 /* Management Control */
130 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
131 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
132 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
133 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
134 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
135 /* Enable MAC address filtering */
136 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
137 /* Enable MNG packets to host memory */
138 #define E1000_MANC_EN_MNG2HOST 0x00200000
140 /* Receive Control */
141 #define E1000_RCTL_EN 0x00000002 /* enable */
142 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
143 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
144 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
145 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
146 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
147 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
148 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
149 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
150 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */
151 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
152 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
153 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
154 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
155 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
156 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
157 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
158 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
159 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
160 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
161 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
162 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
163 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
164 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
165 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
166 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
167 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
168 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
171 * Use byte values for the following shift parameters
173 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
174 * E1000_PSRCTL_BSIZE0_MASK) |
175 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
176 * E1000_PSRCTL_BSIZE1_MASK) |
177 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
178 * E1000_PSRCTL_BSIZE2_MASK) |
179 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
180 * E1000_PSRCTL_BSIZE3_MASK))
181 * where value0 = [128..16256], default=256
182 * value1 = [1024..64512], default=4096
183 * value2 = [0..64512], default=4096
184 * value3 = [0..64512], default=0
187 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
188 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
189 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
190 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
192 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
193 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
194 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
195 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
197 /* SWFW_SYNC Definitions */
198 #define E1000_SWFW_EEP_SM 0x1
199 #define E1000_SWFW_PHY0_SM 0x2
200 #define E1000_SWFW_PHY1_SM 0x4
201 #define E1000_SWFW_CSR_SM 0x8
204 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
205 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
206 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
207 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
208 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
209 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
210 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
211 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
212 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
213 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
214 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
215 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
216 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
217 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
218 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
219 #define E1000_CTRL_RST 0x04000000 /* Global reset */
220 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
221 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
222 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
223 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
226 * Bit definitions for the Management Data IO (MDIO) and Management Data
227 * Clock (MDC) pins in the Device Control Register.
231 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
232 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
233 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
234 #define E1000_STATUS_FUNC_SHIFT 2
235 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
236 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
237 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
238 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
239 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
240 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
241 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
243 /* Constants used to interpret the masked PCI-X bus speed. */
245 #define HALF_DUPLEX 1
246 #define FULL_DUPLEX 2
249 #define ADVERTISE_10_HALF 0x0001
250 #define ADVERTISE_10_FULL 0x0002
251 #define ADVERTISE_100_HALF 0x0004
252 #define ADVERTISE_100_FULL 0x0008
253 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
254 #define ADVERTISE_1000_FULL 0x0020
256 /* 1000/H is not supported, nor spec-compliant. */
257 #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
258 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
260 #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
261 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
262 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
263 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
264 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
266 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
269 #define E1000_PHY_LED0_MODE_MASK 0x00000007
270 #define E1000_PHY_LED0_IVRT 0x00000008
271 #define E1000_PHY_LED0_MASK 0x0000001F
273 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
274 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
275 #define E1000_LEDCTL_LED0_IVRT 0x00000040
276 #define E1000_LEDCTL_LED0_BLINK 0x00000080
278 #define E1000_LEDCTL_MODE_LINK_UP 0x2
279 #define E1000_LEDCTL_MODE_LED_ON 0xE
280 #define E1000_LEDCTL_MODE_LED_OFF 0xF
282 /* Transmit Descriptor bit definitions */
283 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
284 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
285 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
286 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
287 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
288 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
289 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
290 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
291 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
292 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
293 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
294 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
295 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
296 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
297 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
298 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
299 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
300 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
301 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
303 /* Transmit Control */
304 #define E1000_TCTL_EN 0x00000002 /* enable Tx */
305 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
306 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
307 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
308 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
309 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
311 /* Transmit Arbitration Count */
314 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
316 /* Receive Checksum Control */
317 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
318 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
320 /* Header split receive */
321 #define E1000_RFCTL_ACK_DIS 0x00001000
322 #define E1000_RFCTL_EXTEN 0x00008000
323 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
324 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
326 /* Collision related configuration parameters */
327 #define E1000_COLLISION_THRESHOLD 15
328 #define E1000_CT_SHIFT 4
329 #define E1000_COLLISION_DISTANCE 63
330 #define E1000_COLD_SHIFT 12
332 /* Default values for the transmit IPG register */
333 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
335 #define E1000_TIPG_IPGT_MASK 0x000003FF
337 #define DEFAULT_82543_TIPG_IPGR1 8
338 #define E1000_TIPG_IPGR1_SHIFT 10
340 #define DEFAULT_82543_TIPG_IPGR2 6
341 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
342 #define E1000_TIPG_IPGR2_SHIFT 20
344 #define MAX_JUMBO_FRAME_SIZE 0x3F00
346 /* Extended Configuration Control and Size */
347 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
348 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
349 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
350 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
351 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
352 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
353 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
355 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
356 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
357 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
358 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
360 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
363 #define E1000_PBA_8K 0x0008 /* 8KB */
364 #define E1000_PBA_16K 0x0010 /* 16KB */
366 #define E1000_PBS_16K E1000_PBA_16K
372 #define MIN_NUM_XMITS 1000
374 /* SW Semaphore Register */
375 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
376 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
377 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
379 /* Interrupt Cause Read */
380 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
381 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
382 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
383 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
384 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
385 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
386 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
387 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
388 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
389 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
390 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
392 /* PBA ECC Register */
393 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
394 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
395 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */
396 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
397 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */
400 * This defines the bits that are set in the Interrupt Mask
401 * Set/Read Register. Each bit is documented below:
402 * o RXT0 = Receiver Timer Interrupt (ring 0)
403 * o TXDW = Transmit Descriptor Written Back
404 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
405 * o RXSEQ = Receive Sequence Error
406 * o LSC = Link Status Change
408 #define IMS_ENABLE_MASK ( \
415 /* Interrupt Mask Set */
416 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
417 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
418 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
419 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
420 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
421 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
422 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
423 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
424 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
425 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */
427 /* Interrupt Cause Set */
428 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
429 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
430 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
432 /* Transmit Descriptor Control */
433 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
434 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
435 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
436 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
437 /* Enable the counting of desc. still to be processed. */
438 #define E1000_TXDCTL_COUNT_DESC 0x00400000
440 /* Flow Control Constants */
441 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
442 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
443 #define FLOW_CONTROL_TYPE 0x8808
445 /* 802.1q VLAN Packet Size */
446 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
448 /* Receive Address */
450 * Number of high/low register pairs in the RAR. The RAR (Receive Address
451 * Registers) holds the directed and multicast addresses that we monitor.
452 * Technically, we have 16 spots. However, we reserve one of these spots
453 * (RAR[15]) for our directed address used by controllers with
454 * manageability enabled, allowing us room for 15 multicast addresses.
456 #define E1000_RAR_ENTRIES 15
457 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
460 #define E1000_ERR_NVM 1
461 #define E1000_ERR_PHY 2
462 #define E1000_ERR_CONFIG 3
463 #define E1000_ERR_PARAM 4
464 #define E1000_ERR_MAC_INIT 5
465 #define E1000_ERR_PHY_TYPE 6
466 #define E1000_ERR_RESET 9
467 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
468 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
469 #define E1000_BLK_PHY_RESET 12
470 #define E1000_ERR_SWFW_SYNC 13
471 #define E1000_NOT_IMPLEMENTED 14
473 /* Loop limit on how long we wait for auto-negotiation to complete */
474 #define FIBER_LINK_UP_LIMIT 50
475 #define COPPER_LINK_UP_LIMIT 10
476 #define PHY_AUTO_NEG_LIMIT 45
477 #define PHY_FORCE_LIMIT 20
478 /* Number of 100 microseconds we wait for PCI Express master disable */
479 #define MASTER_DISABLE_TIMEOUT 800
480 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
481 #define PHY_CFG_TIMEOUT 100
482 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
483 #define MDIO_OWNERSHIP_TIMEOUT 10
484 /* Number of milliseconds for NVM auto read done after MAC reset. */
485 #define AUTO_READ_DONE_TIMEOUT 10
488 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
489 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
490 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
492 /* Transmit Configuration Word */
493 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
494 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
495 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
496 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
497 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
499 /* Receive Configuration Word */
500 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
501 #define E1000_RXCW_C 0x20000000 /* Receive config */
502 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
504 /* PCI Express Control */
505 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
506 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
507 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
508 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
509 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
510 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
512 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
513 E1000_GCR_RXDSCW_NO_SNOOP | \
514 E1000_GCR_RXDSCR_NO_SNOOP | \
515 E1000_GCR_TXD_NO_SNOOP | \
516 E1000_GCR_TXDSCW_NO_SNOOP | \
517 E1000_GCR_TXDSCR_NO_SNOOP)
519 /* PHY Control Register */
520 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
521 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
522 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
523 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
524 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
525 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
526 #define MII_CR_SPEED_1000 0x0040
527 #define MII_CR_SPEED_100 0x2000
528 #define MII_CR_SPEED_10 0x0000
530 /* PHY Status Register */
531 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
532 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
534 /* Autoneg Advertisement Register */
535 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
536 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
537 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
538 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
539 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
540 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
542 /* Link Partner Ability Register (Base Page) */
543 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
544 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
546 /* Autoneg Expansion Register */
547 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
549 /* 1000BASE-T Control Register */
550 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
551 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
553 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
554 /* 0=Configure PHY as Slave */
555 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
556 /* 0=Automatic Master/Slave config */
558 /* 1000BASE-T Status Register */
559 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
560 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
563 /* PHY 1000 MII Register/Bit Definitions */
564 /* PHY Registers defined by IEEE */
565 #define PHY_CONTROL 0x00 /* Control Register */
566 #define PHY_STATUS 0x01 /* Status Register */
567 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
568 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
569 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
570 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
571 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
572 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
573 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
574 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
577 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
578 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
579 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
580 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
581 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
582 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
583 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
584 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
585 /* NVM Addressing bits based on type (0-small, 1-large) */
586 #define E1000_EECD_ADDR_BITS 0x00000400
587 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
588 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
589 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
590 #define E1000_EECD_SIZE_EX_SHIFT 11
591 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
592 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
593 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
594 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
596 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */
597 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
598 #define E1000_NVM_RW_REG_START 1 /* Start operation */
599 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
600 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
601 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
602 #define E1000_FLASH_UPDATES 2000
604 /* NVM Word Offsets */
605 #define NVM_ID_LED_SETTINGS 0x0004
606 #define NVM_INIT_CONTROL2_REG 0x000F
607 #define NVM_INIT_CONTROL3_PORT_B 0x0014
608 #define NVM_INIT_3GIO_3 0x001A
609 #define NVM_INIT_CONTROL3_PORT_A 0x0024
610 #define NVM_CFG 0x0012
611 #define NVM_ALT_MAC_ADDR_PTR 0x0037
612 #define NVM_CHECKSUM_REG 0x003F
614 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
615 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
617 /* Mask bits for fields in Word 0x0f of the NVM */
618 #define NVM_WORD0F_PAUSE_MASK 0x3000
619 #define NVM_WORD0F_PAUSE 0x1000
620 #define NVM_WORD0F_ASM_DIR 0x2000
622 /* Mask bits for fields in Word 0x1a of the NVM */
623 #define NVM_WORD1A_ASPM_MASK 0x000C
625 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
626 #define NVM_SUM 0xBABA
628 /* PBA (printed board assembly) number words */
629 #define NVM_PBA_OFFSET_0 8
630 #define NVM_PBA_OFFSET_1 9
632 #define NVM_WORD_SIZE_BASE_SHIFT 6
634 /* NVM Commands - SPI */
635 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
636 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
637 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
638 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
639 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
640 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
642 /* SPI NVM Status Register */
643 #define NVM_STATUS_RDY_SPI 0x01
645 /* Word definitions for ID LED Settings */
646 #define ID_LED_RESERVED_0000 0x0000
647 #define ID_LED_RESERVED_FFFF 0xFFFF
648 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
649 (ID_LED_OFF1_OFF2 << 8) | \
650 (ID_LED_DEF1_DEF2 << 4) | \
652 #define ID_LED_DEF1_DEF2 0x1
653 #define ID_LED_DEF1_ON2 0x2
654 #define ID_LED_DEF1_OFF2 0x3
655 #define ID_LED_ON1_DEF2 0x4
656 #define ID_LED_ON1_ON2 0x5
657 #define ID_LED_ON1_OFF2 0x6
658 #define ID_LED_OFF1_DEF2 0x7
659 #define ID_LED_OFF1_ON2 0x8
660 #define ID_LED_OFF1_OFF2 0x9
662 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
663 #define IGP_ACTIVITY_LED_ENABLE 0x0300
664 #define IGP_LED3_MODE 0x07000000
666 /* PCI/PCI-X/PCI-EX Config space */
667 #define PCI_HEADER_TYPE_REGISTER 0x0E
668 #define PCIE_LINK_STATUS 0x12
670 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
671 #define PCIE_LINK_WIDTH_MASK 0x3F0
672 #define PCIE_LINK_WIDTH_SHIFT 4
674 #define PHY_REVISION_MASK 0xFFFFFFF0
675 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
676 #define MAX_PHY_MULTI_PAGE_REG 0xF
678 /* Bit definitions for valid PHY IDs. */
683 #define M88E1000_E_PHY_ID 0x01410C50
684 #define M88E1000_I_PHY_ID 0x01410C30
685 #define M88E1011_I_PHY_ID 0x01410C20
686 #define IGP01E1000_I_PHY_ID 0x02A80380
687 #define M88E1111_I_PHY_ID 0x01410CC0
688 #define GG82563_E_PHY_ID 0x01410CA0
689 #define IGP03E1000_E_PHY_ID 0x02A80390
690 #define IFE_E_PHY_ID 0x02A80330
691 #define IFE_PLUS_E_PHY_ID 0x02A80320
692 #define IFE_C_E_PHY_ID 0x02A80310
693 #define BME1000_E_PHY_ID 0x01410CB0
694 #define BME1000_E_PHY_ID_R2 0x01410CB1
695 #define I82577_E_PHY_ID 0x01540050
696 #define I82578_E_PHY_ID 0x004DD040
698 /* M88E1000 Specific Registers */
699 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
700 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
701 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
703 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
704 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
706 /* M88E1000 PHY Specific Control Register */
707 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
708 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
709 /* Manual MDI configuration */
710 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
711 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
712 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
713 /* Auto crossover enabled all speeds */
714 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
716 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)
717 * 0=Normal 10BASE-T Rx Threshold
719 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
721 /* M88E1000 PHY Specific Status Register */
722 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
723 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
724 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
725 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
726 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
727 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
728 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
730 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
733 * Number of times we will attempt to autonegotiate before downshifting if we
736 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
737 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
739 * Number of times we will attempt to autonegotiate before downshifting if we
742 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
743 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
744 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
746 /* M88EC018 Rev 2 specific DownShift settings */
747 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
748 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
750 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
751 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
753 /* BME1000 PHY Specific Control Register */
754 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
757 #define PHY_PAGE_SHIFT 5
758 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
759 ((reg) & MAX_PHY_REG_ADDRESS))
764 * 4-0: register offset
766 #define GG82563_PAGE_SHIFT 5
767 #define GG82563_REG(page, reg) \
768 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
769 #define GG82563_MIN_ALT_REG 30
771 /* GG82563 Specific Registers */
772 #define GG82563_PHY_SPEC_CTRL \
773 GG82563_REG(0, 16) /* PHY Specific Control */
774 #define GG82563_PHY_PAGE_SELECT \
775 GG82563_REG(0, 22) /* Page Select */
776 #define GG82563_PHY_SPEC_CTRL_2 \
777 GG82563_REG(0, 26) /* PHY Specific Control 2 */
778 #define GG82563_PHY_PAGE_SELECT_ALT \
779 GG82563_REG(0, 29) /* Alternate Page Select */
781 #define GG82563_PHY_MAC_SPEC_CTRL \
782 GG82563_REG(2, 21) /* MAC Specific Control Register */
784 #define GG82563_PHY_DSP_DISTANCE \
785 GG82563_REG(5, 26) /* DSP Distance */
787 /* Page 193 - Port Control Registers */
788 #define GG82563_PHY_KMRN_MODE_CTRL \
789 GG82563_REG(193, 16) /* Kumeran Mode Control */
790 #define GG82563_PHY_PWR_MGMT_CTRL \
791 GG82563_REG(193, 20) /* Power Management Control */
793 /* Page 194 - KMRN Registers */
794 #define GG82563_PHY_INBAND_CTRL \
795 GG82563_REG(194, 18) /* Inband Control */
798 #define E1000_MDIC_REG_SHIFT 16
799 #define E1000_MDIC_PHY_SHIFT 21
800 #define E1000_MDIC_OP_WRITE 0x04000000
801 #define E1000_MDIC_OP_READ 0x08000000
802 #define E1000_MDIC_READY 0x10000000
803 #define E1000_MDIC_ERROR 0x40000000
806 #define E1000_GEN_POLL_TIMEOUT 640
808 #endif /* _E1000_DEFINES_H_ */
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