2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
38 #define FW_T4VF_SGE_BASE_ADDR 0x0000
39 #define FW_T4VF_MPS_BASE_ADDR 0x0100
40 #define FW_T4VF_PL_BASE_ADDR 0x0200
41 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
42 #define FW_T4VF_CIM_BASE_ADDR 0x0300
48 FW_ETH_TX_PKT_WR = 0x08,
50 FW_OFLD_TX_DATA_WR = 0x0b,
52 FW_ETH_TX_PKT_VM_WR = 0x11,
55 FW_RI_RDMA_WRITE_WR = 0x14,
57 FW_RI_RDMA_READ_WR = 0x16,
59 FW_RI_BIND_MW_WR = 0x18,
60 FW_RI_FR_NSMR_WR = 0x19,
61 FW_RI_INV_LSTAG_WR = 0x1a,
70 #define FW_WR_OP(x) ((x) << 24)
71 #define FW_WR_ATOMIC(x) ((x) << 23)
72 #define FW_WR_FLUSH(x) ((x) << 22)
73 #define FW_WR_COMPL(x) ((x) << 21)
74 #define FW_WR_IMMDLEN(x) ((x) << 0)
76 #define FW_WR_EQUIQ (1U << 31)
77 #define FW_WR_EQUEQ (1U << 30)
78 #define FW_WR_FLOWID(x) ((x) << 8)
79 #define FW_WR_LEN16(x) ((x) << 0)
93 struct fw_eth_tx_pkt_wr {
95 __be32 equiq_to_len16;
100 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
104 FW_FLOWC_MNEM_SNDNXT,
105 FW_FLOWC_MNEM_RCVNXT,
106 FW_FLOWC_MNEM_SNDBUF,
110 struct fw_flowc_mnemval {
117 __be32 op_to_nparams;
118 #define FW_FLOWC_WR_NPARAMS(x) ((x) << 0)
120 struct fw_flowc_mnemval mnemval[0];
123 struct fw_ofld_tx_data_wr {
124 __be32 op_to_immdlen;
127 __be32 tunnel_to_proxy;
128 #define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19)
129 #define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18)
130 #define FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << 17)
131 #define FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << 16)
132 #define FW_OFLD_TX_DATA_WR_MORE(x) ((x) << 15)
133 #define FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << 14)
134 #define FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << 10)
135 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6)
140 #define FW_CMD_WR_DMA (1U << 17)
145 struct fw_eth_tx_pkt_vm_wr {
147 __be32 equiq_to_len16;
155 #define FW_CMD_MAX_TIMEOUT 3000
157 enum fw_cmd_opcodes {
162 FW_INITIALIZE_CMD = 0x06,
163 FW_CAPS_CONFIG_CMD = 0x07,
164 FW_PARAMS_CMD = 0x08,
167 FW_EQ_MNGT_CMD = 0x11,
168 FW_EQ_ETH_CMD = 0x12,
169 FW_EQ_CTRL_CMD = 0x13,
170 FW_EQ_OFLD_CMD = 0x21,
172 FW_VI_MAC_CMD = 0x15,
173 FW_VI_RXMODE_CMD = 0x16,
174 FW_VI_ENABLE_CMD = 0x17,
175 FW_ACL_MAC_CMD = 0x18,
176 FW_ACL_VLAN_CMD = 0x19,
177 FW_VI_STATS_CMD = 0x1a,
179 FW_PORT_STATS_CMD = 0x1c,
180 FW_PORT_LB_STATS_CMD = 0x1d,
181 FW_PORT_TRACE_CMD = 0x1e,
182 FW_PORT_TRACE_MMAP_CMD = 0x1f,
183 FW_RSS_IND_TBL_CMD = 0x20,
184 FW_RSS_GLB_CONFIG_CMD = 0x22,
185 FW_RSS_VI_CONFIG_CMD = 0x23,
186 FW_LASTC2E_CMD = 0x40,
192 FW_CMD_CAP_PF = 0x01,
193 FW_CMD_CAP_DMAQ = 0x02,
194 FW_CMD_CAP_PORT = 0x04,
195 FW_CMD_CAP_PORTPROMISC = 0x08,
196 FW_CMD_CAP_PORTSTATS = 0x10,
197 FW_CMD_CAP_VF = 0x80,
201 * Generic command header flit0
208 #define FW_CMD_OP(x) ((x) << 24)
209 #define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff)
210 #define FW_CMD_REQUEST (1U << 23)
211 #define FW_CMD_READ (1U << 22)
212 #define FW_CMD_WRITE (1U << 21)
213 #define FW_CMD_EXEC (1U << 20)
214 #define FW_CMD_RAMASK(x) ((x) << 20)
215 #define FW_CMD_RETVAL(x) ((x) << 8)
216 #define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff)
217 #define FW_CMD_LEN16(x) ((x) << 0)
219 enum fw_ldst_addrspc {
220 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
221 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
222 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
223 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
224 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
225 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
226 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
227 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
228 FW_LDST_ADDRSPC_MDIO = 0x0018,
229 FW_LDST_ADDRSPC_MPS = 0x0020,
230 FW_LDST_ADDRSPC_FUNC = 0x0028
233 enum fw_ldst_mps_fid {
238 enum fw_ldst_func_access_ctl {
239 FW_LDST_FUNC_ACC_CTL_VIID,
240 FW_LDST_FUNC_ACC_CTL_FID
243 enum fw_ldst_func_mod_index {
248 __be32 op_to_addrspace;
249 #define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0)
250 __be32 cycles_to_len16;
252 struct fw_ldst_addrval {
256 struct fw_ldst_idctxt {
268 struct fw_ldst_mdio {
284 struct fw_ldst_func {
295 #define FW_LDST_CMD_MSG(x) ((x) << 31)
296 #define FW_LDST_CMD_PADDR(x) ((x) << 8)
297 #define FW_LDST_CMD_MMD(x) ((x) << 0)
298 #define FW_LDST_CMD_FID(x) ((x) << 15)
299 #define FW_LDST_CMD_CTL(x) ((x) << 0)
300 #define FW_LDST_CMD_RPLCPF(x) ((x) << 0)
302 struct fw_reset_cmd {
309 struct fw_hello_cmd {
312 __be32 err_to_mbasyncnot;
313 #define FW_HELLO_CMD_ERR (1U << 31)
314 #define FW_HELLO_CMD_INIT (1U << 30)
315 #define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29)
316 #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
317 #define FW_HELLO_CMD_MBMASTER(x) ((x) << 24)
318 #define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20)
328 struct fw_initialize_cmd {
334 enum fw_caps_config_hm {
335 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
336 FW_CAPS_CONFIG_HM_PL = 0x00000002,
337 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
338 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
339 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
340 FW_CAPS_CONFIG_HM_TP = 0x00000020,
341 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
342 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
343 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
344 FW_CAPS_CONFIG_HM_MC = 0x00000200,
345 FW_CAPS_CONFIG_HM_LE = 0x00000400,
346 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
347 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
348 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
349 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
350 FW_CAPS_CONFIG_HM_MI = 0x00008000,
351 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
352 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
353 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
354 FW_CAPS_CONFIG_HM_MA = 0x00080000,
355 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
356 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
357 FW_CAPS_CONFIG_HM_UART = 0x00400000,
358 FW_CAPS_CONFIG_HM_SF = 0x00800000,
361 enum fw_caps_config_nbm {
362 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
363 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
366 enum fw_caps_config_link {
367 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
368 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
369 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
372 enum fw_caps_config_switch {
373 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
374 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
377 enum fw_caps_config_nic {
378 FW_CAPS_CONFIG_NIC = 0x00000001,
379 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
382 enum fw_caps_config_ofld {
383 FW_CAPS_CONFIG_OFLD = 0x00000001,
386 enum fw_caps_config_rdma {
387 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
388 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
391 enum fw_caps_config_iscsi {
392 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
393 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
394 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
395 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
398 enum fw_caps_config_fcoe {
399 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
400 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
403 struct fw_caps_config_cmd {
423 * params command mnemonics
425 enum fw_params_mnem {
426 FW_PARAMS_MNEM_DEV = 1, /* device params */
427 FW_PARAMS_MNEM_PFVF = 2, /* function params */
428 FW_PARAMS_MNEM_REG = 3, /* limited register access */
429 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
436 enum fw_params_param_dev {
437 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
438 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
439 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
440 * allocated by the device's
443 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
444 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
445 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
446 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
447 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
448 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
449 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
450 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A
454 * physical and virtual function parameters
456 enum fw_params_param_pfvf {
457 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
458 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
459 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
460 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
461 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
462 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
463 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
464 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
465 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
466 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
467 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
468 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
469 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
470 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
471 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
472 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
473 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
474 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
475 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
476 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
477 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
478 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
479 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
480 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
481 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
482 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
483 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
484 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
488 * dma queue parameters
490 enum fw_params_param_dmaq {
491 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
492 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
493 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
494 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
495 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
498 #define FW_PARAMS_MNEM(x) ((x) << 24)
499 #define FW_PARAMS_PARAM_X(x) ((x) << 16)
500 #define FW_PARAMS_PARAM_Y(x) ((x) << 8)
501 #define FW_PARAMS_PARAM_Z(x) ((x) << 0)
502 #define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
503 #define FW_PARAMS_PARAM_YZ(x) ((x) << 0)
505 struct fw_params_cmd {
508 struct fw_params_param {
514 #define FW_PARAMS_CMD_PFN(x) ((x) << 8)
515 #define FW_PARAMS_CMD_VFN(x) ((x) << 0)
522 __be32 tc_to_nexactf;
523 __be32 r_caps_to_nethctrl;
529 #define FW_PFVF_CMD_PFN(x) ((x) << 8)
530 #define FW_PFVF_CMD_VFN(x) ((x) << 0)
532 #define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20)
533 #define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff)
535 #define FW_PFVF_CMD_NIQ(x) ((x) << 0)
536 #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff)
538 #define FW_PFVF_CMD_CMASK(x) ((x) << 24)
539 #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & 0xf)
541 #define FW_PFVF_CMD_PMASK(x) ((x) << 20)
542 #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & 0xf)
544 #define FW_PFVF_CMD_NEQ(x) ((x) << 0)
545 #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff)
547 #define FW_PFVF_CMD_TC(x) ((x) << 24)
548 #define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff)
550 #define FW_PFVF_CMD_NVI(x) ((x) << 16)
551 #define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff)
553 #define FW_PFVF_CMD_NEXACTF(x) ((x) << 0)
554 #define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff)
556 #define FW_PFVF_CMD_R_CAPS(x) ((x) << 24)
557 #define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff)
559 #define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16)
560 #define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff)
562 #define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0)
563 #define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff)
566 FW_IQ_TYPE_FL_INT_CAP,
567 FW_IQ_TYPE_NO_FL_INT_CAP
572 __be32 alloc_to_len16;
577 __be32 type_to_iqandstindex;
578 __be16 iqdroprss_to_iqesize;
581 __be32 iqns_to_fl0congen;
582 __be16 fl0dcaen_to_fl0cidxfthresh;
585 __be32 fl1cngchmap_to_fl1congen;
586 __be16 fl1dcaen_to_fl1cidxfthresh;
591 #define FW_IQ_CMD_PFN(x) ((x) << 8)
592 #define FW_IQ_CMD_VFN(x) ((x) << 0)
594 #define FW_IQ_CMD_ALLOC (1U << 31)
595 #define FW_IQ_CMD_FREE (1U << 30)
596 #define FW_IQ_CMD_MODIFY (1U << 29)
597 #define FW_IQ_CMD_IQSTART(x) ((x) << 28)
598 #define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
600 #define FW_IQ_CMD_TYPE(x) ((x) << 29)
601 #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
602 #define FW_IQ_CMD_VIID(x) ((x) << 16)
603 #define FW_IQ_CMD_IQANDST(x) ((x) << 15)
604 #define FW_IQ_CMD_IQANUS(x) ((x) << 14)
605 #define FW_IQ_CMD_IQANUD(x) ((x) << 12)
606 #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
608 #define FW_IQ_CMD_IQDROPRSS (1U << 15)
609 #define FW_IQ_CMD_IQGTSMODE (1U << 14)
610 #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
611 #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
612 #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
613 #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
614 #define FW_IQ_CMD_IQO (1U << 3)
615 #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
616 #define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
618 #define FW_IQ_CMD_IQNS(x) ((x) << 31)
619 #define FW_IQ_CMD_IQRO(x) ((x) << 30)
620 #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
621 #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
622 #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
623 #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
624 #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
625 #define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
626 #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
627 #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
628 #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
629 #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
630 #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
631 #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
632 #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
633 #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
634 #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
635 #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
636 #define FW_IQ_CMD_FL0PADEN (1U << 2)
637 #define FW_IQ_CMD_FL0PACKEN (1U << 1)
638 #define FW_IQ_CMD_FL0CONGEN (1U << 0)
640 #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
641 #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
642 #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
643 #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
644 #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
645 #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
647 #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
648 #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
649 #define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
650 #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
651 #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
652 #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
653 #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
654 #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
655 #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
656 #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
657 #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
658 #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
659 #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
660 #define FW_IQ_CMD_FL1PADEN (1U << 2)
661 #define FW_IQ_CMD_FL1PACKEN (1U << 1)
662 #define FW_IQ_CMD_FL1CONGEN (1U << 0)
664 #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
665 #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
666 #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
667 #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
668 #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
669 #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
671 struct fw_eq_eth_cmd {
673 __be32 alloc_to_len16;
676 __be32 fetchszm_to_iqid;
677 __be32 dcaen_to_eqsize;
684 #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
685 #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
686 #define FW_EQ_ETH_CMD_ALLOC (1U << 31)
687 #define FW_EQ_ETH_CMD_FREE (1U << 30)
688 #define FW_EQ_ETH_CMD_MODIFY (1U << 29)
689 #define FW_EQ_ETH_CMD_EQSTART (1U << 28)
690 #define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
692 #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
693 #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
694 #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
696 #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
697 #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
698 #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
699 #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
700 #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
701 #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
702 #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
703 #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
704 #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
705 #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
707 #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
708 #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
709 #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
710 #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
711 #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
712 #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
713 #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
715 #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
717 struct fw_eq_ctrl_cmd {
719 __be32 alloc_to_len16;
720 __be32 cmpliqid_eqid;
722 __be32 fetchszm_to_iqid;
723 __be32 dcaen_to_eqsize;
727 #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
728 #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
730 #define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
731 #define FW_EQ_CTRL_CMD_FREE (1U << 30)
732 #define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
733 #define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
734 #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
736 #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
737 #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
738 #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
739 #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
741 #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
742 #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
743 #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
744 #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
745 #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
746 #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
747 #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
748 #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
749 #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
750 #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
752 #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
753 #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
754 #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
755 #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
756 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
757 #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
758 #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
760 struct fw_eq_ofld_cmd {
762 __be32 alloc_to_len16;
765 __be32 fetchszm_to_iqid;
766 __be32 dcaen_to_eqsize;
770 #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
771 #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
773 #define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
774 #define FW_EQ_OFLD_CMD_FREE (1U << 30)
775 #define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
776 #define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
777 #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
779 #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
780 #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
781 #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
783 #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
784 #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
785 #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
786 #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
787 #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
788 #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
789 #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
790 #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
791 #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
792 #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
794 #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
795 #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
796 #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
797 #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
798 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
799 #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
800 #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
803 * Macros for VIID parsing:
804 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
806 #define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7)
807 #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
808 #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
812 __be32 alloc_to_len16;
828 #define FW_VI_CMD_PFN(x) ((x) << 8)
829 #define FW_VI_CMD_VFN(x) ((x) << 0)
830 #define FW_VI_CMD_ALLOC (1U << 31)
831 #define FW_VI_CMD_FREE (1U << 30)
832 #define FW_VI_CMD_VIID(x) ((x) << 0)
833 #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff)
834 #define FW_VI_CMD_PORTID(x) ((x) << 4)
835 #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
837 /* Special VI_MAC command index ids */
838 #define FW_VI_MAC_ADD_MAC 0x3FF
839 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
840 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
842 enum fw_vi_mac_smac {
843 FW_VI_MAC_MPS_TCAM_ENTRY,
844 FW_VI_MAC_MPS_TCAM_ONLY,
846 FW_VI_MAC_SMT_AND_MPSTCAM
849 enum fw_vi_mac_result {
851 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
852 FW_VI_MAC_R_SMAC_FAIL,
853 FW_VI_MAC_R_F_ACL_CHECK
856 struct fw_vi_mac_cmd {
858 __be32 freemacs_to_len16;
860 struct fw_vi_mac_exact {
864 struct fw_vi_mac_hash {
870 #define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
871 #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
872 #define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
873 #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
874 #define FW_VI_MAC_CMD_VALID (1U << 15)
875 #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
876 #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
877 #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
878 #define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
879 #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
881 #define FW_RXMODE_MTU_NO_CHG 65535
883 struct fw_vi_rxmode_cmd {
886 __be32 mtu_to_vlanexen;
890 #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
891 #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
892 #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
893 #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
894 #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
895 #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
896 #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
897 #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
898 #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3
899 #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8)
901 struct fw_vi_enable_cmd {
909 #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
910 #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
911 #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
912 #define FW_VI_ENABLE_CMD_LED (1U << 29)
914 /* VI VF stats offset definitions */
915 #define VI_VF_NUM_STATS 16
916 enum fw_vi_stats_vf_index {
917 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
918 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
919 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
920 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
921 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
922 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
923 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
924 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
925 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
926 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
927 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
928 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
929 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
930 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
931 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
932 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
935 /* VI PF stats offset definitions */
936 #define VI_PF_NUM_STATS 17
937 enum fw_vi_stats_pf_index {
938 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
939 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
940 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
941 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
942 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
943 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
944 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
945 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
946 FW_VI_PF_STAT_RX_BYTES_IX,
947 FW_VI_PF_STAT_RX_FRAMES_IX,
948 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
949 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
950 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
951 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
952 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
953 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
954 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
957 struct fw_vi_stats_cmd {
961 struct fw_vi_stats_ctl {
972 struct fw_vi_stats_pf {
973 __be64 tx_bcast_bytes;
974 __be64 tx_bcast_frames;
975 __be64 tx_mcast_bytes;
976 __be64 tx_mcast_frames;
977 __be64 tx_ucast_bytes;
978 __be64 tx_ucast_frames;
979 __be64 tx_offload_bytes;
980 __be64 tx_offload_frames;
983 __be64 rx_bcast_bytes;
984 __be64 rx_bcast_frames;
985 __be64 rx_mcast_bytes;
986 __be64 rx_mcast_frames;
987 __be64 rx_ucast_bytes;
988 __be64 rx_ucast_frames;
989 __be64 rx_err_frames;
991 struct fw_vi_stats_vf {
992 __be64 tx_bcast_bytes;
993 __be64 tx_bcast_frames;
994 __be64 tx_mcast_bytes;
995 __be64 tx_mcast_frames;
996 __be64 tx_ucast_bytes;
997 __be64 tx_ucast_frames;
998 __be64 tx_drop_frames;
999 __be64 tx_offload_bytes;
1000 __be64 tx_offload_frames;
1001 __be64 rx_bcast_bytes;
1002 __be64 rx_bcast_frames;
1003 __be64 rx_mcast_bytes;
1004 __be64 rx_mcast_frames;
1005 __be64 rx_ucast_bytes;
1006 __be64 rx_ucast_frames;
1007 __be64 rx_err_frames;
1012 #define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1013 #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1014 #define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1016 struct fw_acl_mac_cmd {
1031 #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1032 #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1033 #define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1035 struct fw_acl_vlan_cmd {
1044 #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1045 #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1046 #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1047 #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1048 #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1051 FW_PORT_CAP_SPEED_100M = 0x0001,
1052 FW_PORT_CAP_SPEED_1G = 0x0002,
1053 FW_PORT_CAP_SPEED_2_5G = 0x0004,
1054 FW_PORT_CAP_SPEED_10G = 0x0008,
1055 FW_PORT_CAP_SPEED_40G = 0x0010,
1056 FW_PORT_CAP_SPEED_100G = 0x0020,
1057 FW_PORT_CAP_FC_RX = 0x0040,
1058 FW_PORT_CAP_FC_TX = 0x0080,
1059 FW_PORT_CAP_ANEG = 0x0100,
1060 FW_PORT_CAP_MDI_0 = 0x0200,
1061 FW_PORT_CAP_MDI_1 = 0x0400,
1062 FW_PORT_CAP_BEAN = 0x0800,
1063 FW_PORT_CAP_PMA_LPBK = 0x1000,
1064 FW_PORT_CAP_PCS_LPBK = 0x2000,
1065 FW_PORT_CAP_PHYXS_LPBK = 0x4000,
1066 FW_PORT_CAP_FAR_END_LPBK = 0x8000,
1070 FW_PORT_MDI_UNCHANGED,
1072 FW_PORT_MDI_F_STRAIGHT,
1073 FW_PORT_MDI_F_CROSSOVER
1076 #define FW_PORT_MDI(x) ((x) << 9)
1078 enum fw_port_action {
1079 FW_PORT_ACTION_L1_CFG = 0x0001,
1080 FW_PORT_ACTION_L2_CFG = 0x0002,
1081 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1082 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
1083 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
1084 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1085 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
1086 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
1087 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
1088 FW_PORT_ACTION_L1_LPBK = 0x0021,
1089 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
1090 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
1091 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1092 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1093 FW_PORT_ACTION_PHY_RESET = 0x0040,
1094 FW_PORT_ACTION_PMA_RESET = 0x0041,
1095 FW_PORT_ACTION_PCS_RESET = 0x0042,
1096 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
1097 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
1098 FW_PORT_ACTION_AN_RESET = 0x0045
1101 enum fw_port_l2cfg_ctlbf {
1102 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
1103 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
1104 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
1105 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
1106 FW_PORT_L2_CTLBF_IVLAN = 0x10,
1107 FW_PORT_L2_CTLBF_TXIPG = 0x20
1110 enum fw_port_dcb_cfg {
1111 FW_PORT_DCB_CFG_PG = 0x01,
1112 FW_PORT_DCB_CFG_PFC = 0x02,
1113 FW_PORT_DCB_CFG_APPL = 0x04
1116 enum fw_port_dcb_cfg_rc {
1117 FW_PORT_DCB_CFG_SUCCESS = 0x0,
1118 FW_PORT_DCB_CFG_ERROR = 0x1
1121 struct fw_port_cmd {
1122 __be32 op_to_portid;
1123 __be32 action_to_len16;
1125 struct fw_port_l1cfg {
1129 struct fw_port_l2cfg {
1130 __be16 ctlbf_to_ivlan0;
1142 struct fw_port_info {
1143 __be32 lstatus_to_modtype;
1152 struct fw_port_ppp {
1153 __be32 pppen_to_ncsich;
1156 struct fw_port_dcb {
1163 __be32 pgid0_to_pgid7;
1170 #define FW_PORT_CMD_READ (1U << 22)
1172 #define FW_PORT_CMD_PORTID(x) ((x) << 0)
1173 #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1175 #define FW_PORT_CMD_ACTION(x) ((x) << 16)
1177 #define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1178 #define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1179 #define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1180 #define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1181 #define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1182 #define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1184 #define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1186 #define FW_PORT_CMD_LSTATUS (1U << 31)
1187 #define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1188 #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1189 #define FW_PORT_CMD_TXPAUSE (1U << 23)
1190 #define FW_PORT_CMD_RXPAUSE (1U << 22)
1191 #define FW_PORT_CMD_MDIOCAP (1U << 21)
1192 #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1193 #define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1194 #define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1195 #define FW_PORT_CMD_PTYPE_MASK 0x1f
1196 #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1197 #define FW_PORT_CMD_MODTYPE_MASK 0x1f
1198 #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1200 #define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1201 #define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1202 #define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1204 #define FW_PORT_CMD_CH0(x) ((x) << 20)
1205 #define FW_PORT_CMD_CH1(x) ((x) << 16)
1206 #define FW_PORT_CMD_CH2(x) ((x) << 12)
1207 #define FW_PORT_CMD_CH3(x) ((x) << 8)
1208 #define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1211 FW_PORT_TYPE_FIBER_XFI,
1212 FW_PORT_TYPE_FIBER_XAUI,
1213 FW_PORT_TYPE_BT_SGMII,
1214 FW_PORT_TYPE_BT_XFI,
1215 FW_PORT_TYPE_BT_XAUI,
1223 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1226 enum fw_port_module_type {
1227 FW_PORT_MOD_TYPE_NA,
1228 FW_PORT_MOD_TYPE_LR,
1229 FW_PORT_MOD_TYPE_SR,
1230 FW_PORT_MOD_TYPE_ER,
1231 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
1232 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
1233 FW_PORT_MOD_TYPE_LRM,
1235 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1239 #define FW_NUM_PORT_STATS 50
1240 #define FW_NUM_PORT_TX_STATS 23
1241 #define FW_NUM_PORT_RX_STATS 27
1243 enum fw_port_stats_tx_index {
1244 FW_STAT_TX_PORT_BYTES_IX,
1245 FW_STAT_TX_PORT_FRAMES_IX,
1246 FW_STAT_TX_PORT_BCAST_IX,
1247 FW_STAT_TX_PORT_MCAST_IX,
1248 FW_STAT_TX_PORT_UCAST_IX,
1249 FW_STAT_TX_PORT_ERROR_IX,
1250 FW_STAT_TX_PORT_64B_IX,
1251 FW_STAT_TX_PORT_65B_127B_IX,
1252 FW_STAT_TX_PORT_128B_255B_IX,
1253 FW_STAT_TX_PORT_256B_511B_IX,
1254 FW_STAT_TX_PORT_512B_1023B_IX,
1255 FW_STAT_TX_PORT_1024B_1518B_IX,
1256 FW_STAT_TX_PORT_1519B_MAX_IX,
1257 FW_STAT_TX_PORT_DROP_IX,
1258 FW_STAT_TX_PORT_PAUSE_IX,
1259 FW_STAT_TX_PORT_PPP0_IX,
1260 FW_STAT_TX_PORT_PPP1_IX,
1261 FW_STAT_TX_PORT_PPP2_IX,
1262 FW_STAT_TX_PORT_PPP3_IX,
1263 FW_STAT_TX_PORT_PPP4_IX,
1264 FW_STAT_TX_PORT_PPP5_IX,
1265 FW_STAT_TX_PORT_PPP6_IX,
1266 FW_STAT_TX_PORT_PPP7_IX
1269 enum fw_port_stat_rx_index {
1270 FW_STAT_RX_PORT_BYTES_IX,
1271 FW_STAT_RX_PORT_FRAMES_IX,
1272 FW_STAT_RX_PORT_BCAST_IX,
1273 FW_STAT_RX_PORT_MCAST_IX,
1274 FW_STAT_RX_PORT_UCAST_IX,
1275 FW_STAT_RX_PORT_MTU_ERROR_IX,
1276 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1277 FW_STAT_RX_PORT_CRC_ERROR_IX,
1278 FW_STAT_RX_PORT_LEN_ERROR_IX,
1279 FW_STAT_RX_PORT_SYM_ERROR_IX,
1280 FW_STAT_RX_PORT_64B_IX,
1281 FW_STAT_RX_PORT_65B_127B_IX,
1282 FW_STAT_RX_PORT_128B_255B_IX,
1283 FW_STAT_RX_PORT_256B_511B_IX,
1284 FW_STAT_RX_PORT_512B_1023B_IX,
1285 FW_STAT_RX_PORT_1024B_1518B_IX,
1286 FW_STAT_RX_PORT_1519B_MAX_IX,
1287 FW_STAT_RX_PORT_PAUSE_IX,
1288 FW_STAT_RX_PORT_PPP0_IX,
1289 FW_STAT_RX_PORT_PPP1_IX,
1290 FW_STAT_RX_PORT_PPP2_IX,
1291 FW_STAT_RX_PORT_PPP3_IX,
1292 FW_STAT_RX_PORT_PPP4_IX,
1293 FW_STAT_RX_PORT_PPP5_IX,
1294 FW_STAT_RX_PORT_PPP6_IX,
1295 FW_STAT_RX_PORT_PPP7_IX,
1296 FW_STAT_RX_PORT_LESS_64B_IX
1299 struct fw_port_stats_cmd {
1300 __be32 op_to_portid;
1301 __be32 retval_len16;
1302 union fw_port_stats {
1303 struct fw_port_stats_ctl {
1315 struct fw_port_stats_all {
1324 __be64 tx_128b_255b;
1325 __be64 tx_256b_511b;
1326 __be64 tx_512b_1023b;
1327 __be64 tx_1024b_1518b;
1328 __be64 tx_1519b_max;
1344 __be64 rx_mtu_error;
1345 __be64 rx_mtu_crc_error;
1346 __be64 rx_crc_error;
1347 __be64 rx_len_error;
1348 __be64 rx_sym_error;
1351 __be64 rx_128b_255b;
1352 __be64 rx_256b_511b;
1353 __be64 rx_512b_1023b;
1354 __be64 rx_1024b_1518b;
1355 __be64 rx_1519b_max;
1372 #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
1373 #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
1374 #define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
1375 #define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
1377 /* port loopback stats */
1378 #define FW_NUM_LB_STATS 16
1379 enum fw_port_lb_stats_index {
1380 FW_STAT_LB_PORT_BYTES_IX,
1381 FW_STAT_LB_PORT_FRAMES_IX,
1382 FW_STAT_LB_PORT_BCAST_IX,
1383 FW_STAT_LB_PORT_MCAST_IX,
1384 FW_STAT_LB_PORT_UCAST_IX,
1385 FW_STAT_LB_PORT_ERROR_IX,
1386 FW_STAT_LB_PORT_64B_IX,
1387 FW_STAT_LB_PORT_65B_127B_IX,
1388 FW_STAT_LB_PORT_128B_255B_IX,
1389 FW_STAT_LB_PORT_256B_511B_IX,
1390 FW_STAT_LB_PORT_512B_1023B_IX,
1391 FW_STAT_LB_PORT_1024B_1518B_IX,
1392 FW_STAT_LB_PORT_1519B_MAX_IX,
1393 FW_STAT_LB_PORT_DROP_FRAMES_IX
1396 struct fw_port_lb_stats_cmd {
1397 __be32 op_to_lbport;
1398 __be32 retval_len16;
1399 union fw_port_lb_stats {
1400 struct fw_port_lb_stats_ctl {
1412 struct fw_port_lb_stats_all {
1421 __be64 tx_128b_255b;
1422 __be64 tx_256b_511b;
1423 __be64 tx_512b_1023b;
1424 __be64 tx_1024b_1518b;
1425 __be64 tx_1519b_max;
1432 #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
1433 #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
1434 #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
1435 #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
1437 struct fw_rss_ind_tbl_cmd {
1439 #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
1440 __be32 retval_len16;
1445 #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
1446 #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
1447 #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
1451 __be32 iq12_to_iq14;
1452 __be32 iq15_to_iq17;
1453 __be32 iq18_to_iq20;
1454 __be32 iq21_to_iq23;
1455 __be32 iq24_to_iq26;
1456 __be32 iq27_to_iq29;
1461 struct fw_rss_glb_config_cmd {
1463 __be32 retval_len16;
1464 union fw_rss_glb_config {
1465 struct fw_rss_glb_config_manual {
1471 struct fw_rss_glb_config_basicvirtual {
1473 __be32 synmapen_to_hashtoeplitz;
1474 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8)
1475 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
1476 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
1477 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
1478 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
1479 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3)
1480 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2)
1481 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1)
1482 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0)
1489 #define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28)
1491 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
1492 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
1494 struct fw_rss_vi_config_cmd {
1496 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
1497 __be32 retval_len16;
1498 union fw_rss_vi_config {
1499 struct fw_rss_vi_config_manual {
1504 struct fw_rss_vi_config_basicvirtual {
1506 __be32 defaultq_to_ip4udpen;
1507 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16)
1508 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
1509 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3)
1510 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
1511 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1)
1512 #define FW_RSS_VI_CONFIG_CMD_IP4UDPEN (1U << 0)
1519 enum fw_error_type {
1520 FW_ERROR_TYPE_EXCEPTION = 0x0,
1521 FW_ERROR_TYPE_HWMODULE = 0x1,
1522 FW_ERROR_TYPE_WR = 0x2,
1523 FW_ERROR_TYPE_ACL = 0x3,
1526 struct fw_error_cmd {
1530 struct fw_error_exception {
1533 struct fw_error_hwmodule {
1537 struct fw_error_wr {
1543 struct fw_error_acl {
1554 struct fw_debug_cmd {
1556 #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
1559 struct fw_debug_assert {
1565 u8 filename_8_15[8];
1568 struct fw_debug_prt {
1571 __be32 dprtstrparam0;
1572 __be32 dprtstrparam1;
1573 __be32 dprtstrparam2;
1574 __be32 dprtstrparam3;
1582 __be16 len512; /* bin length in units of 512-bytes */
1583 __be32 fw_ver; /* firmware version */
1584 __be32 tp_microcode_ver;
1589 u8 intfver_iscsipdu;
1593 __be32 reserved3[27];
1596 #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
1597 #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
1598 #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
1599 #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
1600 #endif /* _T4FW_INTERFACE_H_ */