Pileus Git - ~andy/linux/blob - drivers/net/chelsio/subr.c

   1 /*****************************************************************************
   2  *                                                                           *
   3  * File: subr.c                                                              *
   4  * $Revision: 1.27 $                                                         *
   5  * $Date: 2005/06/22 01:08:36 $                                              *
   6  * Description:                                                              *
   7  *  Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
   8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
   9  *                                                                           *
  10  * This program is free software; you can redistribute it and/or modify      *
  11  * it under the terms of the GNU General Public License, version 2, as       *
  12  * published by the Free Software Foundation.                                *
  13  *                                                                           *
  14  * You should have received a copy of the GNU General Public License along   *
  15  * with this program; if not, write to the Free Software Foundation, Inc.,   *
  16  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
  17  *                                                                           *
  18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  19  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  21  *                                                                           *
  22  * http://www.chelsio.com                                                    *
  23  *                                                                           *
  24  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  25  * All rights reserved.                                                      *
  26  *                                                                           *
  27  * Maintainers: maintainers@chelsio.com                                      *
  28  *                                                                           *
  29  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  30  *          Tina Yang               <tainay@chelsio.com>                     *
  31  *          Felix Marti             <felix@chelsio.com>                      *
  32  *          Scott Bardone           <sbardone@chelsio.com>                   *
  33  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  34  *          Frank DiMambro          <frank@chelsio.com>                      *
  35  *                                                                           *
  36  * History:                                                                  *
  37  *                                                                           *
  38  ****************************************************************************/
  39
  40 #include "common.h"
  41 #include "elmer0.h"
  42 #include "regs.h"
  43 #include "gmac.h"
  44 #include "cphy.h"
  45 #include "sge.h"
  46 #include "tp.h"
  47 #include "espi.h"
  48
  49 /**
  50  *      t1_wait_op_done - wait until an operation is completed
  51  *      @adapter: the adapter performing the operation
  52  *      @reg: the register to check for completion
  53  *      @mask: a single-bit field within @reg that indicates completion
  54  *      @polarity: the value of the field when the operation is completed
  55  *      @attempts: number of check iterations
  56  *      @delay: delay in usecs between iterations
  57  *
  58  *      Wait until an operation is completed by checking a bit in a register
  59  *      up to @attempts times.  Returns %0 if the operation completes and %1
  60  *      otherwise.
  61  */
  62 static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
  63                            int attempts, int delay)
  64 {
  65         while (1) {
  66                 u32 val = readl(adapter->regs + reg) & mask;
  67
  68                 if (!!val == polarity)
  69                         return 0;
  70                 if (--attempts == 0)
  71                         return 1;
  72                 if (delay)
  73                         udelay(delay);
  74         }
  75 }
  76
  77 #define TPI_ATTEMPTS 50
  78
  79 /*
  80  * Write a register over the TPI interface (unlocked and locked versions).
  81  */
  82 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
  83 {
  84         int tpi_busy;
  85
  86         writel(addr, adapter->regs + A_TPI_ADDR);
  87         writel(value, adapter->regs + A_TPI_WR_DATA);
  88         writel(F_TPIWR, adapter->regs + A_TPI_CSR);
  89
  90         tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
  91                                    TPI_ATTEMPTS, 3);
  92         if (tpi_busy)
  93                 CH_ALERT("%s: TPI write to 0x%x failed\n",
  94                          adapter->name, addr);
  95         return tpi_busy;
  96 }
  97
  98 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
  99 {
 100         int ret;
 101
 102         spin_lock(&adapter->tpi_lock);
 103         ret = __t1_tpi_write(adapter, addr, value);
 104         spin_unlock(&adapter->tpi_lock);
 105         return ret;
 106 }
 107
 108 /*
 109  * Read a register over the TPI interface (unlocked and locked versions).
 110  */
 111 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
 112 {
 113         int tpi_busy;
 114
 115         writel(addr, adapter->regs + A_TPI_ADDR);
 116         writel(0, adapter->regs + A_TPI_CSR);
 117
 118         tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
 119                                    TPI_ATTEMPTS, 3);
 120         if (tpi_busy)
 121                 CH_ALERT("%s: TPI read from 0x%x failed\n",
 122                          adapter->name, addr);
 123         else
 124                 *valp = readl(adapter->regs + A_TPI_RD_DATA);
 125         return tpi_busy;
 126 }
 127
 128 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
 129 {
 130         int ret;
 131
 132         spin_lock(&adapter->tpi_lock);
 133         ret = __t1_tpi_read(adapter, addr, valp);
 134         spin_unlock(&adapter->tpi_lock);
 135         return ret;
 136 }
 137
 138 /*
 139  * Set a TPI parameter.
 140  */
 141 static void t1_tpi_par(adapter_t *adapter, u32 value)
 142 {
 143         writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
 144 }
 145
 146 /*
 147  * Called when a port's link settings change to propagate the new values to the
 148  * associated PHY and MAC.  After performing the common tasks it invokes an
 149  * OS-specific handler.
 150  */
 151 void t1_link_changed(adapter_t *adapter, int port_id)
 152 {
 153         int link_ok, speed, duplex, fc;
 154         struct cphy *phy = adapter->port[port_id].phy;
 155         struct link_config *lc = &adapter->port[port_id].link_config;
 156
 157         phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
 158
 159         lc->speed = speed < 0 ? SPEED_INVALID : speed;
 160         lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
 161         if (!(lc->requested_fc & PAUSE_AUTONEG))
 162                 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
 163
 164         if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
 165                 /* Set MAC speed, duplex, and flow control to match PHY. */
 166                 struct cmac *mac = adapter->port[port_id].mac;
 167
 168                 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
 169                 lc->fc = (unsigned char)fc;
 170         }
 171         t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
 172 }
 173
 174 static int t1_pci_intr_handler(adapter_t *adapter)
 175 {
 176         u32 pcix_cause;
 177
 178         pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
 179
 180         if (pcix_cause) {
 181                 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
 182                                        pcix_cause);
 183                 t1_fatal_err(adapter);    /* PCI errors are fatal */
 184         }
 185         return 0;
 186 }
 187
 188 #ifdef CONFIG_CHELSIO_T1_COUGAR
 189 #include "cspi.h"
 190 #endif
 191 #ifdef CONFIG_CHELSIO_T1_1G
 192 #include "fpga_defs.h"
 193
 194 /*
 195  * PHY interrupt handler for FPGA boards.
 196  */
 197 static int fpga_phy_intr_handler(adapter_t *adapter)
 198 {
 199         int p;
 200         u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
 201
 202         for_each_port(adapter, p)
 203                 if (cause & (1 << p)) {
 204                         struct cphy *phy = adapter->port[p].phy;
 205                         int phy_cause = phy->ops->interrupt_handler(phy);
 206
 207                         if (phy_cause & cphy_cause_link_change)
 208                                 t1_link_changed(adapter, p);
 209                 }
 210         writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
 211         return 0;
 212 }
 213
 214 /*
 215  * Slow path interrupt handler for FPGAs.
 216  */
 217 static int fpga_slow_intr(adapter_t *adapter)
 218 {
 219         u32 cause = readl(adapter->regs + A_PL_CAUSE);
 220
 221         cause &= ~F_PL_INTR_SGE_DATA;
 222         if (cause & F_PL_INTR_SGE_ERR)
 223                 t1_sge_intr_error_handler(adapter->sge);
 224
 225         if (cause & FPGA_PCIX_INTERRUPT_GMAC)
 226                 fpga_phy_intr_handler(adapter);
 227
 228         if (cause & FPGA_PCIX_INTERRUPT_TP) {
 229                 /*
 230                  * FPGA doesn't support MC4 interrupts and it requires
 231                  * this odd layer of indirection for MC5.
 232                  */
 233                 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
 234
 235                 /* Clear TP interrupt */
 236                 writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
 237         }
 238         if (cause & FPGA_PCIX_INTERRUPT_PCIX)
 239                 t1_pci_intr_handler(adapter);
 240
 241         /* Clear the interrupts just processed. */
 242         if (cause)
 243                 writel(cause, adapter->regs + A_PL_CAUSE);
 244
 245         return cause != 0;
 246 }
 247 #endif
 248
 249 /*
 250  * Wait until Elmer's MI1 interface is ready for new operations.
 251  */
 252 static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
 253 {
 254         int attempts = 100, busy;
 255
 256         do {
 257                 u32 val;
 258
 259                 __t1_tpi_read(adapter, mi1_reg, &val);
 260                 busy = val & F_MI1_OP_BUSY;
 261                 if (busy)
 262                         udelay(10);
 263         } while (busy && --attempts);
 264         if (busy)
 265                 CH_ALERT("%s: MDIO operation timed out\n",
 266                          adapter->name);
 267         return busy;
 268 }
 269
 270 /*
 271  * MI1 MDIO initialization.
 272  */
 273 static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
 274 {
 275         u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
 276         u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
 277                 V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
 278
 279         if (!(bi->caps & SUPPORTED_10000baseT_Full))
 280                 val |= V_MI1_SOF(1);
 281         t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
 282 }
 283
 284 #if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
 285 /*
 286  * Elmer MI1 MDIO read/write operations.
 287  */
 288 static int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr,
 289                          int reg_addr, unsigned int *valp)
 290 {
 291         u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
 292
 293         if (mmd_addr)
 294                 return -EINVAL;
 295
 296         spin_lock(&adapter->tpi_lock);
 297         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
 298         __t1_tpi_write(adapter,
 299                         A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
 300         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 301         __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
 302         spin_unlock(&adapter->tpi_lock);
 303         return 0;
 304 }
 305
 306 static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
 307                           int reg_addr, unsigned int val)
 308 {
 309         u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
 310
 311         if (mmd_addr)
 312                 return -EINVAL;
 313
 314         spin_lock(&adapter->tpi_lock);
 315         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
 316         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
 317         __t1_tpi_write(adapter,
 318                         A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE);
 319         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 320         spin_unlock(&adapter->tpi_lock);
 321         return 0;
 322 }
 323
 324 #if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
 325 static struct mdio_ops mi1_mdio_ops = {
 326         mi1_mdio_init,
 327         mi1_mdio_read,
 328         mi1_mdio_write
 329 };
 330 #endif
 331
 332 #endif
 333
 334 static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
 335                              int reg_addr, unsigned int *valp)
 336 {
 337         u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
 338
 339         spin_lock(&adapter->tpi_lock);
 340
 341         /* Write the address we want. */
 342         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
 343         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
 344         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
 345                        MI1_OP_INDIRECT_ADDRESS);
 346         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 347
 348         /* Write the operation we want. */
 349         __t1_tpi_write(adapter,
 350                         A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
 351         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 352
 353         /* Read the data. */
 354         __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
 355         spin_unlock(&adapter->tpi_lock);
 356         return 0;
 357 }
 358
 359 static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
 360                               int reg_addr, unsigned int val)
 361 {
 362         u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
 363
 364         spin_lock(&adapter->tpi_lock);
 365
 366         /* Write the address we want. */
 367         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
 368         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
 369         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
 370                        MI1_OP_INDIRECT_ADDRESS);
 371         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 372
 373         /* Write the data. */
 374         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
 375         __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
 376         mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
 377         spin_unlock(&adapter->tpi_lock);
 378         return 0;
 379 }
 380
 381 static struct mdio_ops mi1_mdio_ext_ops = {
 382         mi1_mdio_init,
 383         mi1_mdio_ext_read,
 384         mi1_mdio_ext_write
 385 };
 386
 387 enum {
 388         CH_BRD_T110_1CU,
 389         CH_BRD_N110_1F,
 390         CH_BRD_N210_1F,
 391         CH_BRD_T210_1F,
 392         CH_BRD_T210_1CU,
 393         CH_BRD_N204_4CU,
 394 };
 395
 396 static struct board_info t1_board[] = {
 397
 398 { CHBT_BOARD_CHT110, 1/*ports#*/,
 399   SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T1,
 400   CHBT_MAC_PM3393, CHBT_PHY_MY3126,
 401   125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
 402   1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
 403   1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
 404   &t1_my3126_ops, &mi1_mdio_ext_ops,
 405   "Chelsio T110 1x10GBase-CX4 TOE" },
 406
 407 { CHBT_BOARD_N110, 1/*ports#*/,
 408   SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
 409   CHBT_MAC_PM3393, CHBT_PHY_88X2010,
 410   125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
 411   1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
 412   0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
 413   &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
 414   "Chelsio N110 1x10GBaseX NIC" },
 415
 416 { CHBT_BOARD_N210, 1/*ports#*/,
 417   SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T2,
 418   CHBT_MAC_PM3393, CHBT_PHY_88X2010,
 419   125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
 420   1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
 421   0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
 422   &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
 423   "Chelsio N210 1x10GBaseX NIC" },
 424
 425 { CHBT_BOARD_CHT210, 1/*ports#*/,
 426   SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
 427   CHBT_MAC_PM3393, CHBT_PHY_88X2010,
 428   125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
 429   1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
 430   0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
 431   &t1_mv88x201x_ops, &mi1_mdio_ext_ops,
 432   "Chelsio T210 1x10GBaseX TOE" },
 433
 434 { CHBT_BOARD_CHT210, 1/*ports#*/,
 435   SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
 436   CHBT_MAC_PM3393, CHBT_PHY_MY3126,
 437   125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
 438   1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
 439   1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
 440   &t1_my3126_ops, &mi1_mdio_ext_ops,
 441   "Chelsio T210 1x10GBase-CX4 TOE" },
 442
 443 #ifdef CONFIG_CHELSIO_T1_1G
 444 { CHBT_BOARD_CHN204, 4/*ports#*/,
 445   SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
 446   SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
 447   SUPPORTED_PAUSE | SUPPORTED_TP /*caps*/, CHBT_TERM_T2, CHBT_MAC_VSC7321, CHBT_PHY_88E1111,
 448   100000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/,
 449   4/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
 450   0/*mdiinv*/, 1/*mdc*/, 4/*phybaseaddr*/, &t1_vsc7326_ops,
 451   &t1_mv88e1xxx_ops, &mi1_mdio_ops,
 452   "Chelsio N204 4x100/1000BaseT NIC" },
 453 #endif
 454
 455 };
 456
 457 struct pci_device_id t1_pci_tbl[] = {
 458         CH_DEVICE(8, 0, CH_BRD_T110_1CU),
 459         CH_DEVICE(8, 1, CH_BRD_T110_1CU),
 460         CH_DEVICE(7, 0, CH_BRD_N110_1F),
 461         CH_DEVICE(10, 1, CH_BRD_N210_1F),
 462         CH_DEVICE(11, 1, CH_BRD_T210_1F),
 463         CH_DEVICE(14, 1, CH_BRD_T210_1CU),
 464         CH_DEVICE(16, 1, CH_BRD_N204_4CU),
 465         { 0 }
 466 };
 467
 468 MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
 469
 470 /*
 471  * Return the board_info structure with a given index.  Out-of-range indices
 472  * return NULL.
 473  */
 474 const struct board_info *t1_get_board_info(unsigned int board_id)
 475 {
 476         return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
 477 }
 478
 479 struct chelsio_vpd_t {
 480         u32 format_version;
 481         u8 serial_number[16];
 482         u8 mac_base_address[6];
 483         u8 pad[2];           /* make multiple-of-4 size requirement explicit */
 484 };
 485
 486 #define EEPROMSIZE        (8 * 1024)
 487 #define EEPROM_MAX_POLL   4
 488
 489 /*
 490  * Read SEEPROM. A zero is written to the flag register when the addres is
 491  * written to the Control register. The hardware device will set the flag to a
 492  * one when 4B have been transferred to the Data register.
 493  */
 494 int t1_seeprom_read(adapter_t *adapter, u32 addr, u32 *data)
 495 {
 496         int i = EEPROM_MAX_POLL;
 497         u16 val;
 498
 499         if (addr >= EEPROMSIZE || (addr & 3))
 500                 return -EINVAL;
 501
 502         pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
 503         do {
 504                 udelay(50);
 505                 pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
 506         } while (!(val & F_VPD_OP_FLAG) && --i);
 507
 508         if (!(val & F_VPD_OP_FLAG)) {
 509                 CH_ERR("%s: reading EEPROM address 0x%x failed\n",
 510                        adapter->name, addr);
 511                 return -EIO;
 512         }
 513         pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, data);
 514         *data = le32_to_cpu(*data);
 515         return 0;
 516 }
 517
 518 static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
 519 {
 520         int addr, ret = 0;
 521
 522         for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
 523                 ret = t1_seeprom_read(adapter, addr,
 524                                       (u32 *)((u8 *)vpd + addr));
 525
 526         return ret;
 527 }
 528
 529 /*
 530  * Read a port's MAC address from the VPD ROM.
 531  */
 532 static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
 533 {
 534         struct chelsio_vpd_t vpd;
 535
 536         if (t1_eeprom_vpd_get(adapter, &vpd))
 537                 return 1;
 538         memcpy(mac_addr, vpd.mac_base_address, 5);
 539         mac_addr[5] = vpd.mac_base_address[5] + index;
 540         return 0;
 541 }
 542
 543 /*
 544  * Set up the MAC/PHY according to the requested link settings.
 545  *
 546  * If the PHY can auto-negotiate first decide what to advertise, then
 547  * enable/disable auto-negotiation as desired and reset.
 548  *
 549  * If the PHY does not auto-negotiate we just reset it.
 550  *
 551  * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
 552  * otherwise do it later based on the outcome of auto-negotiation.
 553  */
 554 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
 555 {
 556         unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
 557
 558         if (lc->supported & SUPPORTED_Autoneg) {
 559                 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
 560                 if (fc) {
 561                         if (fc == ((PAUSE_RX | PAUSE_TX) &
 562                                    (mac->adapter->params.nports < 2)))
 563                                 lc->advertising |= ADVERTISED_PAUSE;
 564                         else {
 565                                 lc->advertising |= ADVERTISED_ASYM_PAUSE;
 566                                 if (fc == PAUSE_RX)
 567                                         lc->advertising |= ADVERTISED_PAUSE;
 568                         }
 569                 }
 570                 phy->ops->advertise(phy, lc->advertising);
 571
 572                 if (lc->autoneg == AUTONEG_DISABLE) {
 573                         lc->speed = lc->requested_speed;
 574                         lc->duplex = lc->requested_duplex;
 575                         lc->fc = (unsigned char)fc;
 576                         mac->ops->set_speed_duplex_fc(mac, lc->speed,
 577                                                       lc->duplex, fc);
 578                         /* Also disables autoneg */
 579                         phy->state = PHY_AUTONEG_RDY;
 580                         phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
 581                         phy->ops->reset(phy, 0);
 582                 } else {
 583                         phy->state = PHY_AUTONEG_EN;
 584                         phy->ops->autoneg_enable(phy); /* also resets PHY */
 585                 }
 586         } else {
 587                 phy->state = PHY_AUTONEG_RDY;
 588                 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
 589                 lc->fc = (unsigned char)fc;
 590                 phy->ops->reset(phy, 0);
 591         }
 592         return 0;
 593 }
 594
 595 /*
 596  * External interrupt handler for boards using elmer0.
 597  */
 598 int t1_elmer0_ext_intr_handler(adapter_t *adapter)
 599 {
 600         struct cphy *phy;
 601         int phy_cause;
 602         u32 cause;
 603
 604         t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
 605
 606         switch (board_info(adapter)->board) {
 607 #ifdef CONFIG_CHELSIO_T1_1G
 608         case CHBT_BOARD_CHT204:
 609         case CHBT_BOARD_CHT204E:
 610         case CHBT_BOARD_CHN204:
 611         case CHBT_BOARD_CHT204V: {
 612                 int i, port_bit;
 613                 for_each_port(adapter, i) {
 614                         port_bit = i + 1;
 615                         if (!(cause & (1 << port_bit)))
 616                                 continue;
 617
 618                         phy = adapter->port[i].phy;
 619                         phy_cause = phy->ops->interrupt_handler(phy);
 620                         if (phy_cause & cphy_cause_link_change)
 621                                 t1_link_changed(adapter, i);
 622                 }
 623                 break;
 624         }
 625         case CHBT_BOARD_CHT101:
 626                 if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
 627                         phy = adapter->port[0].phy;
 628                         phy_cause = phy->ops->interrupt_handler(phy);
 629                         if (phy_cause & cphy_cause_link_change)
 630                                 t1_link_changed(adapter, 0);
 631                 }
 632                 break;
 633         case CHBT_BOARD_7500: {
 634                 int p;
 635                 /*
 636                  * Elmer0's interrupt cause isn't useful here because there is
 637                  * only one bit that can be set for all 4 ports.  This means
 638                  * we are forced to check every PHY's interrupt status
 639                  * register to see who initiated the interrupt.
 640                  */
 641                 for_each_port(adapter, p) {
 642                         phy = adapter->port[p].phy;
 643                         phy_cause = phy->ops->interrupt_handler(phy);
 644                         if (phy_cause & cphy_cause_link_change)
 645                             t1_link_changed(adapter, p);
 646                 }
 647                 break;
 648         }
 649 #endif
 650         case CHBT_BOARD_CHT210:
 651         case CHBT_BOARD_N210:
 652         case CHBT_BOARD_N110:
 653                 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
 654                         phy = adapter->port[0].phy;
 655                         phy_cause = phy->ops->interrupt_handler(phy);
 656                         if (phy_cause & cphy_cause_link_change)
 657                                 t1_link_changed(adapter, 0);
 658                 }
 659                 break;
 660         case CHBT_BOARD_8000:
 661         case CHBT_BOARD_CHT110:
 662                 CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n",
 663                        cause);
 664                 if (cause & ELMER0_GP_BIT1) {        /* PMC3393 INTB */
 665                         struct cmac *mac = adapter->port[0].mac;
 666
 667                         mac->ops->interrupt_handler(mac);
 668                 }
 669                 if (cause & ELMER0_GP_BIT5) {        /* XPAK MOD_DETECT */
 670                         u32 mod_detect;
 671
 672                         t1_tpi_read(adapter,
 673                                         A_ELMER0_GPI_STAT, &mod_detect);
 674                         CH_MSG(adapter, INFO, LINK, "XPAK %s\n",
 675                                mod_detect ? "removed" : "inserted");
 676                 }
 677                 break;
 678 #ifdef CONFIG_CHELSIO_T1_COUGAR
 679         case CHBT_BOARD_COUGAR:
 680                 if (adapter->params.nports == 1) {
 681                         if (cause & ELMER0_GP_BIT1) {         /* Vitesse MAC */
 682                                 struct cmac *mac = adapter->port[0].mac;
 683                                 mac->ops->interrupt_handler(mac);
 684                         }
 685                         if (cause & ELMER0_GP_BIT5) {     /* XPAK MOD_DETECT */
 686                         }
 687                 } else {
 688                         int i, port_bit;
 689
 690                         for_each_port(adapter, i) {
 691                                 port_bit = i ? i + 1 : 0;
 692                                 if (!(cause & (1 << port_bit)))
 693                                         continue;
 694
 695                                 phy = adapter->port[i].phy;
 696                                 phy_cause = phy->ops->interrupt_handler(phy);
 697                                 if (phy_cause & cphy_cause_link_change)
 698                                         t1_link_changed(adapter, i);
 699                         }
 700                 }
 701                 break;
 702 #endif
 703         }
 704         t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
 705         return 0;
 706 }
 707
 708 /* Enables all interrupts. */
 709 void t1_interrupts_enable(adapter_t *adapter)
 710 {
 711         unsigned int i;
 712
 713         adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
 714
 715         t1_sge_intr_enable(adapter->sge);
 716         t1_tp_intr_enable(adapter->tp);
 717         if (adapter->espi) {
 718                 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
 719                 t1_espi_intr_enable(adapter->espi);
 720         }
 721
 722         /* Enable MAC/PHY interrupts for each port. */
 723         for_each_port(adapter, i) {
 724                 adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
 725                 adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
 726         }
 727
 728         /* Enable PCIX & external chip interrupts on ASIC boards. */
 729         if (t1_is_asic(adapter)) {
 730                 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
 731
 732                 /* PCI-X interrupts */
 733                 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
 734                                        0xffffffff);
 735
 736                 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
 737                 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
 738                 writel(pl_intr, adapter->regs + A_PL_ENABLE);
 739         }
 740 }
 741
 742 /* Disables all interrupts. */
 743 void t1_interrupts_disable(adapter_t* adapter)
 744 {
 745         unsigned int i;
 746
 747         t1_sge_intr_disable(adapter->sge);
 748         t1_tp_intr_disable(adapter->tp);
 749         if (adapter->espi)
 750                 t1_espi_intr_disable(adapter->espi);
 751
 752         /* Disable MAC/PHY interrupts for each port. */
 753         for_each_port(adapter, i) {
 754                 adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
 755                 adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
 756         }
 757
 758         /* Disable PCIX & external chip interrupts. */
 759         if (t1_is_asic(adapter))
 760                 writel(0, adapter->regs + A_PL_ENABLE);
 761
 762         /* PCI-X interrupts */
 763         pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
 764
 765         adapter->slow_intr_mask = 0;
 766 }
 767
 768 /* Clears all interrupts */
 769 void t1_interrupts_clear(adapter_t* adapter)
 770 {
 771         unsigned int i;
 772
 773         t1_sge_intr_clear(adapter->sge);
 774         t1_tp_intr_clear(adapter->tp);
 775         if (adapter->espi)
 776                 t1_espi_intr_clear(adapter->espi);
 777
 778         /* Clear MAC/PHY interrupts for each port. */
 779         for_each_port(adapter, i) {
 780                 adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
 781                 adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
 782         }
 783
 784         /* Enable interrupts for external devices. */
 785         if (t1_is_asic(adapter)) {
 786                 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
 787
 788                 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
 789                        adapter->regs + A_PL_CAUSE);
 790         }
 791
 792         /* PCI-X interrupts */
 793         pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
 794 }
 795
 796 /*
 797  * Slow path interrupt handler for ASICs.
 798  */
 799 static int asic_slow_intr(adapter_t *adapter)
 800 {
 801         u32 cause = readl(adapter->regs + A_PL_CAUSE);
 802
 803         cause &= adapter->slow_intr_mask;
 804         if (!cause)
 805                 return 0;
 806         if (cause & F_PL_INTR_SGE_ERR)
 807                 t1_sge_intr_error_handler(adapter->sge);
 808         if (cause & F_PL_INTR_TP)
 809                 t1_tp_intr_handler(adapter->tp);
 810         if (cause & F_PL_INTR_ESPI)
 811                 t1_espi_intr_handler(adapter->espi);
 812         if (cause & F_PL_INTR_PCIX)
 813                 t1_pci_intr_handler(adapter);
 814         if (cause & F_PL_INTR_EXT)
 815                 t1_elmer0_ext_intr_handler(adapter);
 816
 817         /* Clear the interrupts just processed. */
 818         writel(cause, adapter->regs + A_PL_CAUSE);
 819         readl(adapter->regs + A_PL_CAUSE); /* flush writes */
 820         return 1;
 821 }
 822
 823 int t1_slow_intr_handler(adapter_t *adapter)
 824 {
 825 #ifdef CONFIG_CHELSIO_T1_1G
 826         if (!t1_is_asic(adapter))
 827                 return fpga_slow_intr(adapter);
 828 #endif
 829         return asic_slow_intr(adapter);
 830 }
 831
 832 /* Power sequencing is a work-around for Intel's XPAKs. */
 833 static void power_sequence_xpak(adapter_t* adapter)
 834 {
 835         u32 mod_detect;
 836         u32 gpo;
 837
 838         /* Check for XPAK */
 839         t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
 840         if (!(ELMER0_GP_BIT5 & mod_detect)) {
 841                 /* XPAK is present */
 842                 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
 843                 gpo |= ELMER0_GP_BIT18;
 844                 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
 845         }
 846 }
 847
 848 int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
 849                                struct adapter_params *p)
 850 {
 851         p->chip_version = bi->chip_term;
 852         p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
 853         if (p->chip_version == CHBT_TERM_T1 ||
 854             p->chip_version == CHBT_TERM_T2 ||
 855             p->chip_version == CHBT_TERM_FPGA) {
 856                 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
 857
 858                 val = G_TP_PC_REV(val);
 859                 if (val == 2)
 860                         p->chip_revision = TERM_T1B;
 861                 else if (val == 3)
 862                         p->chip_revision = TERM_T2;
 863                 else
 864                         return -1;
 865         } else
 866                 return -1;
 867         return 0;
 868 }
 869
 870 /*
 871  * Enable board components other than the Chelsio chip, such as external MAC
 872  * and PHY.
 873  */
 874 static int board_init(adapter_t *adapter, const struct board_info *bi)
 875 {
 876         switch (bi->board) {
 877         case CHBT_BOARD_8000:
 878         case CHBT_BOARD_N110:
 879         case CHBT_BOARD_N210:
 880         case CHBT_BOARD_CHT210:
 881         case CHBT_BOARD_COUGAR:
 882                 t1_tpi_par(adapter, 0xf);
 883                 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
 884                 break;
 885         case CHBT_BOARD_CHT110:
 886                 t1_tpi_par(adapter, 0xf);
 887                 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
 888
 889                 /* TBD XXX Might not need.  This fixes a problem
 890                  *         described in the Intel SR XPAK errata.
 891                  */
 892                 power_sequence_xpak(adapter);
 893                 break;
 894 #ifdef CONFIG_CHELSIO_T1_1G
 895     case CHBT_BOARD_CHT204E:
 896                         /* add config space write here */
 897         case CHBT_BOARD_CHT204:
 898         case CHBT_BOARD_CHT204V:
 899         case CHBT_BOARD_CHN204:
 900                 t1_tpi_par(adapter, 0xf);
 901                 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
 902                 break;
 903         case CHBT_BOARD_CHT101:
 904         case CHBT_BOARD_7500:
 905                 t1_tpi_par(adapter, 0xf);
 906                 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
 907                 break;
 908 #endif
 909         }
 910         return 0;
 911 }
 912
 913 /*
 914  * Initialize and configure the Terminator HW modules.  Note that external
 915  * MAC and PHYs are initialized separately.
 916  */
 917 int t1_init_hw_modules(adapter_t *adapter)
 918 {
 919         int err = -EIO;
 920         const struct board_info *bi = board_info(adapter);
 921
 922         if (!bi->clock_mc4) {
 923                 u32 val = readl(adapter->regs + A_MC4_CFG);
 924
 925                 writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
 926                 writel(F_M_BUS_ENABLE | F_TCAM_RESET,
 927                        adapter->regs + A_MC5_CONFIG);
 928         }
 929
 930 #ifdef CONFIG_CHELSIO_T1_COUGAR
 931         if (adapter->cspi && t1_cspi_init(adapter->cspi))
 932                 goto out_err;
 933 #endif
 934         if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
 935                                           bi->espi_nports))
 936                 goto out_err;
 937
 938         if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
 939                 goto out_err;
 940
 941         err = t1_sge_configure(adapter->sge, &adapter->params.sge);
 942         if (err)
 943                 goto out_err;
 944
 945         err = 0;
 946  out_err:
 947         return err;
 948 }
 949
 950 /*
 951  * Determine a card's PCI mode.
 952  */
 953 static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
 954 {
 955         static const unsigned short speed_map[] = { 33, 66, 100, 133 };
 956         u32 pci_mode;
 957
 958         pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
 959         p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
 960         p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
 961         p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
 962 }
 963
 964 /*
 965  * Release the structures holding the SW per-Terminator-HW-module state.
 966  */
 967 void t1_free_sw_modules(adapter_t *adapter)
 968 {
 969         unsigned int i;
 970
 971         for_each_port(adapter, i) {
 972                 struct cmac *mac = adapter->port[i].mac;
 973                 struct cphy *phy = adapter->port[i].phy;
 974
 975                 if (mac)
 976                         mac->ops->destroy(mac);
 977                 if (phy)
 978                         phy->ops->destroy(phy);
 979         }
 980
 981         if (adapter->sge)
 982                 t1_sge_destroy(adapter->sge);
 983         if (adapter->tp)
 984                 t1_tp_destroy(adapter->tp);
 985         if (adapter->espi)
 986                 t1_espi_destroy(adapter->espi);
 987 #ifdef CONFIG_CHELSIO_T1_COUGAR
 988         if (adapter->cspi)
 989                 t1_cspi_destroy(adapter->cspi);
 990 #endif
 991 }
 992
 993 static void __devinit init_link_config(struct link_config *lc,
 994                                        const struct board_info *bi)
 995 {
 996         lc->supported = bi->caps;
 997         lc->requested_speed = lc->speed = SPEED_INVALID;
 998         lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
 999         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
1000         if (lc->supported & SUPPORTED_Autoneg) {
1001                 lc->advertising = lc->supported;
1002                 lc->autoneg = AUTONEG_ENABLE;
1003                 lc->requested_fc |= PAUSE_AUTONEG;
1004         } else {
1005                 lc->advertising = 0;
1006                 lc->autoneg = AUTONEG_DISABLE;
1007         }
1008 }
1009
1010 #ifdef CONFIG_CHELSIO_T1_COUGAR
1011         if (bi->clock_cspi && !(adapter->cspi = t1_cspi_create(adapter))) {
1012                 CH_ERR("%s: CSPI initialization failed\n",
1013                        adapter->name);
1014                 goto error;
1015         }
1016 #endif
1017
1018 /*
1019  * Allocate and initialize the data structures that hold the SW state of
1020  * the Terminator HW modules.
1021  */
1022 int __devinit t1_init_sw_modules(adapter_t *adapter,
1023                                  const struct board_info *bi)
1024 {
1025         unsigned int i;
1026
1027         adapter->params.brd_info = bi;
1028         adapter->params.nports = bi->port_number;
1029         adapter->params.stats_update_period = bi->gmac->stats_update_period;
1030
1031         adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
1032         if (!adapter->sge) {
1033                 CH_ERR("%s: SGE initialization failed\n",
1034                        adapter->name);
1035                 goto error;
1036         }
1037
1038         if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
1039                 CH_ERR("%s: ESPI initialization failed\n",
1040                        adapter->name);
1041                 goto error;
1042         }
1043
1044         adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1045         if (!adapter->tp) {
1046                 CH_ERR("%s: TP initialization failed\n",
1047                        adapter->name);
1048                 goto error;
1049         }
1050
1051         board_init(adapter, bi);
1052         bi->mdio_ops->init(adapter, bi);
1053         if (bi->gphy->reset)
1054                 bi->gphy->reset(adapter);
1055         if (bi->gmac->reset)
1056                 bi->gmac->reset(adapter);
1057
1058         for_each_port(adapter, i) {
1059                 u8 hw_addr[6];
1060                 struct cmac *mac;
1061                 int phy_addr = bi->mdio_phybaseaddr + i;
1062
1063                 adapter->port[i].phy = bi->gphy->create(adapter, phy_addr,
1064                                                         bi->mdio_ops);
1065                 if (!adapter->port[i].phy) {
1066                         CH_ERR("%s: PHY %d initialization failed\n",
1067                                adapter->name, i);
1068                         goto error;
1069                 }
1070
1071                 adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1072                 if (!mac) {
1073                         CH_ERR("%s: MAC %d initialization failed\n",
1074                                adapter->name, i);
1075                         goto error;
1076                 }
1077
1078                 /*
1079                  * Get the port's MAC addresses either from the EEPROM if one
1080                  * exists or the one hardcoded in the MAC.
1081                  */
1082                 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1083                         mac->ops->macaddress_get(mac, hw_addr);
1084                 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
1085                         CH_ERR("%s: could not read MAC address from VPD ROM\n",
1086                                adapter->port[i].dev->name);
1087                         goto error;
1088                 }
1089                 memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
1090                 init_link_config(&adapter->port[i].link_config, bi);
1091         }
1092
1093         get_pci_mode(adapter, &adapter->params.pci);
1094         t1_interrupts_clear(adapter);
1095         return 0;
1096
1097 error:
1098         t1_free_sw_modules(adapter);
1099         return -1;
1100 }