2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see <http://www.gnu.org/licenses/>.
35 * Your platform definition file should specify something like:
37 * static struct mcp251x_platform_data mcp251x_info = {
38 * .oscillator_frequency = 8000000,
41 * static struct spi_board_info spi_board_info[] = {
43 * .modalias = "mcp2510",
44 * // or "mcp2515" depending on your controller
45 * .platform_data = &mcp251x_info,
47 * .max_speed_hz = 2*1000*1000,
52 * Please see mcp251x.h for a description of the fields in
53 * struct mcp251x_platform_data.
57 #include <linux/can/core.h>
58 #include <linux/can/dev.h>
59 #include <linux/can/led.h>
60 #include <linux/can/platform/mcp251x.h>
61 #include <linux/completion.h>
62 #include <linux/delay.h>
63 #include <linux/device.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/freezer.h>
66 #include <linux/interrupt.h>
68 #include <linux/kernel.h>
69 #include <linux/module.h>
70 #include <linux/netdevice.h>
71 #include <linux/platform_device.h>
72 #include <linux/slab.h>
73 #include <linux/spi/spi.h>
74 #include <linux/uaccess.h>
75 #include <linux/regulator/consumer.h>
77 /* SPI interface instruction set */
78 #define INSTRUCTION_WRITE 0x02
79 #define INSTRUCTION_READ 0x03
80 #define INSTRUCTION_BIT_MODIFY 0x05
81 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
82 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
83 #define INSTRUCTION_RESET 0xC0
87 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
90 /* MPC251x registers */
93 # define CANCTRL_REQOP_MASK 0xe0
94 # define CANCTRL_REQOP_CONF 0x80
95 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
96 # define CANCTRL_REQOP_LOOPBACK 0x40
97 # define CANCTRL_REQOP_SLEEP 0x20
98 # define CANCTRL_REQOP_NORMAL 0x00
99 # define CANCTRL_OSM 0x08
100 # define CANCTRL_ABAT 0x10
104 # define CNF1_SJW_SHIFT 6
106 # define CNF2_BTLMODE 0x80
107 # define CNF2_SAM 0x40
108 # define CNF2_PS1_SHIFT 3
110 # define CNF3_SOF 0x08
111 # define CNF3_WAKFIL 0x04
112 # define CNF3_PHSEG2_MASK 0x07
114 # define CANINTE_MERRE 0x80
115 # define CANINTE_WAKIE 0x40
116 # define CANINTE_ERRIE 0x20
117 # define CANINTE_TX2IE 0x10
118 # define CANINTE_TX1IE 0x08
119 # define CANINTE_TX0IE 0x04
120 # define CANINTE_RX1IE 0x02
121 # define CANINTE_RX0IE 0x01
123 # define CANINTF_MERRF 0x80
124 # define CANINTF_WAKIF 0x40
125 # define CANINTF_ERRIF 0x20
126 # define CANINTF_TX2IF 0x10
127 # define CANINTF_TX1IF 0x08
128 # define CANINTF_TX0IF 0x04
129 # define CANINTF_RX1IF 0x02
130 # define CANINTF_RX0IF 0x01
131 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
132 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
133 # define CANINTF_ERR (CANINTF_ERRIF)
135 # define EFLG_EWARN 0x01
136 # define EFLG_RXWAR 0x02
137 # define EFLG_TXWAR 0x04
138 # define EFLG_RXEP 0x08
139 # define EFLG_TXEP 0x10
140 # define EFLG_TXBO 0x20
141 # define EFLG_RX0OVR 0x40
142 # define EFLG_RX1OVR 0x80
143 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
144 # define TXBCTRL_ABTF 0x40
145 # define TXBCTRL_MLOA 0x20
146 # define TXBCTRL_TXERR 0x10
147 # define TXBCTRL_TXREQ 0x08
148 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
149 # define SIDH_SHIFT 3
150 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
151 # define SIDL_SID_MASK 7
152 # define SIDL_SID_SHIFT 5
153 # define SIDL_EXIDE_SHIFT 3
154 # define SIDL_EID_SHIFT 16
155 # define SIDL_EID_MASK 3
156 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
157 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
158 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
159 # define DLC_RTR_SHIFT 6
160 #define TXBCTRL_OFF 0
161 #define TXBSIDH_OFF 1
162 #define TXBSIDL_OFF 2
163 #define TXBEID8_OFF 3
164 #define TXBEID0_OFF 4
167 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
168 # define RXBCTRL_BUKT 0x04
169 # define RXBCTRL_RXM0 0x20
170 # define RXBCTRL_RXM1 0x40
171 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
172 # define RXBSIDH_SHIFT 3
173 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
174 # define RXBSIDL_IDE 0x08
175 # define RXBSIDL_SRR 0x10
176 # define RXBSIDL_EID 3
177 # define RXBSIDL_SHIFT 5
178 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
179 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
180 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
181 # define RXBDLC_LEN_MASK 0x0f
182 # define RXBDLC_RTR 0x40
183 #define RXBCTRL_OFF 0
184 #define RXBSIDH_OFF 1
185 #define RXBSIDL_OFF 2
186 #define RXBEID8_OFF 3
187 #define RXBEID0_OFF 4
190 #define RXFSIDH(n) ((n) * 4)
191 #define RXFSIDL(n) ((n) * 4 + 1)
192 #define RXFEID8(n) ((n) * 4 + 2)
193 #define RXFEID0(n) ((n) * 4 + 3)
194 #define RXMSIDH(n) ((n) * 4 + 0x20)
195 #define RXMSIDL(n) ((n) * 4 + 0x21)
196 #define RXMEID8(n) ((n) * 4 + 0x22)
197 #define RXMEID0(n) ((n) * 4 + 0x23)
199 #define GET_BYTE(val, byte) \
200 (((val) >> ((byte) * 8)) & 0xff)
201 #define SET_BYTE(val, byte) \
202 (((val) & 0xff) << ((byte) * 8))
205 * Buffer size required for the largest SPI transfer (i.e., reading a
208 #define CAN_FRAME_MAX_DATA_LEN 8
209 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
210 #define CAN_FRAME_MAX_BITS 128
212 #define TX_ECHO_SKB_MAX 1
214 #define DEVICE_NAME "mcp251x"
216 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
217 module_param(mcp251x_enable_dma, int, S_IRUGO);
218 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
220 static const struct can_bittiming_const mcp251x_bittiming_const = {
233 CAN_MCP251X_MCP2510 = 0x2510,
234 CAN_MCP251X_MCP2515 = 0x2515,
237 struct mcp251x_priv {
239 struct net_device *net;
240 struct spi_device *spi;
241 enum mcp251x_model model;
243 struct mutex mcp_lock; /* SPI device lock */
247 dma_addr_t spi_tx_dma;
248 dma_addr_t spi_rx_dma;
250 struct sk_buff *tx_skb;
253 struct workqueue_struct *wq;
254 struct work_struct tx_work;
255 struct work_struct restart_work;
259 #define AFTER_SUSPEND_UP 1
260 #define AFTER_SUSPEND_DOWN 2
261 #define AFTER_SUSPEND_POWER 4
262 #define AFTER_SUSPEND_RESTART 8
264 struct regulator *power;
265 struct regulator *transceiver;
268 #define MCP251X_IS(_model) \
269 static inline int mcp251x_is_##_model(struct spi_device *spi) \
271 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
272 return priv->model == CAN_MCP251X_MCP##_model; \
278 static void mcp251x_clean(struct net_device *net)
280 struct mcp251x_priv *priv = netdev_priv(net);
282 if (priv->tx_skb || priv->tx_len)
283 net->stats.tx_errors++;
285 dev_kfree_skb(priv->tx_skb);
287 can_free_echo_skb(priv->net, 0);
293 * Note about handling of error return of mcp251x_spi_trans: accessing
294 * registers via SPI is not really different conceptually than using
295 * normal I/O assembler instructions, although it's much more
296 * complicated from a practical POV. So it's not advisable to always
297 * check the return value of this function. Imagine that every
298 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
299 * error();", it would be a great mess (well there are some situation
300 * when exception handling C++ like could be useful after all). So we
301 * just check that transfers are OK at the beginning of our
302 * conversation with the chip and to avoid doing really nasty things
303 * (like injecting bogus packets in the network stack).
305 static int mcp251x_spi_trans(struct spi_device *spi, int len)
307 struct mcp251x_priv *priv = spi_get_drvdata(spi);
308 struct spi_transfer t = {
309 .tx_buf = priv->spi_tx_buf,
310 .rx_buf = priv->spi_rx_buf,
314 struct spi_message m;
317 spi_message_init(&m);
319 if (mcp251x_enable_dma) {
320 t.tx_dma = priv->spi_tx_dma;
321 t.rx_dma = priv->spi_rx_dma;
325 spi_message_add_tail(&t, &m);
327 ret = spi_sync(spi, &m);
329 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
333 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
335 struct mcp251x_priv *priv = spi_get_drvdata(spi);
338 priv->spi_tx_buf[0] = INSTRUCTION_READ;
339 priv->spi_tx_buf[1] = reg;
341 mcp251x_spi_trans(spi, 3);
342 val = priv->spi_rx_buf[2];
347 static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
348 uint8_t *v1, uint8_t *v2)
350 struct mcp251x_priv *priv = spi_get_drvdata(spi);
352 priv->spi_tx_buf[0] = INSTRUCTION_READ;
353 priv->spi_tx_buf[1] = reg;
355 mcp251x_spi_trans(spi, 4);
357 *v1 = priv->spi_rx_buf[2];
358 *v2 = priv->spi_rx_buf[3];
361 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
363 struct mcp251x_priv *priv = spi_get_drvdata(spi);
365 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
366 priv->spi_tx_buf[1] = reg;
367 priv->spi_tx_buf[2] = val;
369 mcp251x_spi_trans(spi, 3);
372 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
373 u8 mask, uint8_t val)
375 struct mcp251x_priv *priv = spi_get_drvdata(spi);
377 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
378 priv->spi_tx_buf[1] = reg;
379 priv->spi_tx_buf[2] = mask;
380 priv->spi_tx_buf[3] = val;
382 mcp251x_spi_trans(spi, 4);
385 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
386 int len, int tx_buf_idx)
388 struct mcp251x_priv *priv = spi_get_drvdata(spi);
390 if (mcp251x_is_2510(spi)) {
393 for (i = 1; i < TXBDAT_OFF + len; i++)
394 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
397 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
398 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
402 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
405 struct mcp251x_priv *priv = spi_get_drvdata(spi);
406 u32 sid, eid, exide, rtr;
407 u8 buf[SPI_TRANSFER_BUF_LEN];
409 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
411 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
413 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
414 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
415 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
417 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
418 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
419 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
420 (exide << SIDL_EXIDE_SHIFT) |
421 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
422 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
423 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
424 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
425 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
426 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
428 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
429 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
430 mcp251x_spi_trans(priv->spi, 1);
433 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
436 struct mcp251x_priv *priv = spi_get_drvdata(spi);
438 if (mcp251x_is_2510(spi)) {
441 for (i = 1; i < RXBDAT_OFF; i++)
442 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
444 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
445 for (; i < (RXBDAT_OFF + len); i++)
446 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
448 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
449 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
450 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
454 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
456 struct mcp251x_priv *priv = spi_get_drvdata(spi);
458 struct can_frame *frame;
459 u8 buf[SPI_TRANSFER_BUF_LEN];
461 skb = alloc_can_skb(priv->net, &frame);
463 dev_err(&spi->dev, "cannot allocate RX skb\n");
464 priv->net->stats.rx_dropped++;
468 mcp251x_hw_rx_frame(spi, buf, buf_idx);
469 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
470 /* Extended ID format */
471 frame->can_id = CAN_EFF_FLAG;
473 /* Extended ID part */
474 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
475 SET_BYTE(buf[RXBEID8_OFF], 1) |
476 SET_BYTE(buf[RXBEID0_OFF], 0) |
477 /* Standard ID part */
478 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
479 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
480 /* Remote transmission request */
481 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
482 frame->can_id |= CAN_RTR_FLAG;
484 /* Standard ID format */
486 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
487 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
488 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
489 frame->can_id |= CAN_RTR_FLAG;
492 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
493 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
495 priv->net->stats.rx_packets++;
496 priv->net->stats.rx_bytes += frame->can_dlc;
498 can_led_event(priv->net, CAN_LED_EVENT_RX);
503 static void mcp251x_hw_sleep(struct spi_device *spi)
505 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
508 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
509 struct net_device *net)
511 struct mcp251x_priv *priv = netdev_priv(net);
512 struct spi_device *spi = priv->spi;
514 if (priv->tx_skb || priv->tx_len) {
515 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
516 return NETDEV_TX_BUSY;
519 if (can_dropped_invalid_skb(net, skb))
522 netif_stop_queue(net);
524 queue_work(priv->wq, &priv->tx_work);
529 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
531 struct mcp251x_priv *priv = netdev_priv(net);
536 /* We have to delay work since SPI I/O may sleep */
537 priv->can.state = CAN_STATE_ERROR_ACTIVE;
538 priv->restart_tx = 1;
539 if (priv->can.restart_ms == 0)
540 priv->after_suspend = AFTER_SUSPEND_RESTART;
541 queue_work(priv->wq, &priv->restart_work);
550 static int mcp251x_set_normal_mode(struct spi_device *spi)
552 struct mcp251x_priv *priv = spi_get_drvdata(spi);
553 unsigned long timeout;
555 /* Enable interrupts */
556 mcp251x_write_reg(spi, CANINTE,
557 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
558 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
560 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
561 /* Put device into loopback mode */
562 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
563 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
564 /* Put device into listen-only mode */
565 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
567 /* Put device into normal mode */
568 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
570 /* Wait for the device to enter normal mode */
571 timeout = jiffies + HZ;
572 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
574 if (time_after(jiffies, timeout)) {
575 dev_err(&spi->dev, "MCP251x didn't"
576 " enter in normal mode\n");
581 priv->can.state = CAN_STATE_ERROR_ACTIVE;
585 static int mcp251x_do_set_bittiming(struct net_device *net)
587 struct mcp251x_priv *priv = netdev_priv(net);
588 struct can_bittiming *bt = &priv->can.bittiming;
589 struct spi_device *spi = priv->spi;
591 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
593 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
594 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
596 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
598 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
599 (bt->phase_seg2 - 1));
600 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
601 mcp251x_read_reg(spi, CNF1),
602 mcp251x_read_reg(spi, CNF2),
603 mcp251x_read_reg(spi, CNF3));
608 static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
609 struct spi_device *spi)
611 mcp251x_do_set_bittiming(net);
613 mcp251x_write_reg(spi, RXBCTRL(0),
614 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
615 mcp251x_write_reg(spi, RXBCTRL(1),
616 RXBCTRL_RXM0 | RXBCTRL_RXM1);
620 static int mcp251x_hw_reset(struct spi_device *spi)
622 struct mcp251x_priv *priv = spi_get_drvdata(spi);
624 unsigned long timeout;
626 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
627 ret = spi_write(spi, priv->spi_tx_buf, 1);
629 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
633 /* Wait for reset to finish */
634 timeout = jiffies + HZ;
636 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
637 != CANCTRL_REQOP_CONF) {
639 if (time_after(jiffies, timeout)) {
640 dev_err(&spi->dev, "MCP251x didn't"
641 " enter in conf mode after reset\n");
648 static int mcp251x_hw_probe(struct spi_device *spi)
652 mcp251x_hw_reset(spi);
655 * Please note that these are "magic values" based on after
656 * reset defaults taken from data sheet which allows us to see
657 * if we really have a chip on the bus (we avoid common all
658 * zeroes or all ones situations)
660 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
661 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
663 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
665 /* Check for power up default values */
666 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
669 static int mcp251x_power_enable(struct regulator *reg, int enable)
675 return regulator_enable(reg);
677 return regulator_disable(reg);
680 static void mcp251x_open_clean(struct net_device *net)
682 struct mcp251x_priv *priv = netdev_priv(net);
683 struct spi_device *spi = priv->spi;
685 free_irq(spi->irq, priv);
686 mcp251x_hw_sleep(spi);
687 mcp251x_power_enable(priv->transceiver, 0);
691 static int mcp251x_stop(struct net_device *net)
693 struct mcp251x_priv *priv = netdev_priv(net);
694 struct spi_device *spi = priv->spi;
698 priv->force_quit = 1;
699 free_irq(spi->irq, priv);
700 destroy_workqueue(priv->wq);
703 mutex_lock(&priv->mcp_lock);
705 /* Disable and clear pending interrupts */
706 mcp251x_write_reg(spi, CANINTE, 0x00);
707 mcp251x_write_reg(spi, CANINTF, 0x00);
709 mcp251x_write_reg(spi, TXBCTRL(0), 0);
712 mcp251x_hw_sleep(spi);
714 mcp251x_power_enable(priv->transceiver, 0);
716 priv->can.state = CAN_STATE_STOPPED;
718 mutex_unlock(&priv->mcp_lock);
720 can_led_event(net, CAN_LED_EVENT_STOP);
725 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
728 struct can_frame *frame;
730 skb = alloc_can_err_skb(net, &frame);
732 frame->can_id |= can_id;
733 frame->data[1] = data1;
736 netdev_err(net, "cannot allocate error skb\n");
740 static void mcp251x_tx_work_handler(struct work_struct *ws)
742 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
744 struct spi_device *spi = priv->spi;
745 struct net_device *net = priv->net;
746 struct can_frame *frame;
748 mutex_lock(&priv->mcp_lock);
750 if (priv->can.state == CAN_STATE_BUS_OFF) {
753 frame = (struct can_frame *)priv->tx_skb->data;
755 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
756 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
757 mcp251x_hw_tx(spi, frame, 0);
758 priv->tx_len = 1 + frame->can_dlc;
759 can_put_echo_skb(priv->tx_skb, net, 0);
763 mutex_unlock(&priv->mcp_lock);
766 static void mcp251x_restart_work_handler(struct work_struct *ws)
768 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
770 struct spi_device *spi = priv->spi;
771 struct net_device *net = priv->net;
773 mutex_lock(&priv->mcp_lock);
774 if (priv->after_suspend) {
776 mcp251x_hw_reset(spi);
777 mcp251x_setup(net, priv, spi);
778 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
779 mcp251x_set_normal_mode(spi);
780 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
781 netif_device_attach(net);
783 mcp251x_set_normal_mode(spi);
784 netif_wake_queue(net);
786 mcp251x_hw_sleep(spi);
788 priv->after_suspend = 0;
789 priv->force_quit = 0;
792 if (priv->restart_tx) {
793 priv->restart_tx = 0;
794 mcp251x_write_reg(spi, TXBCTRL(0), 0);
796 netif_wake_queue(net);
797 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
799 mutex_unlock(&priv->mcp_lock);
802 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
804 struct mcp251x_priv *priv = dev_id;
805 struct spi_device *spi = priv->spi;
806 struct net_device *net = priv->net;
808 mutex_lock(&priv->mcp_lock);
809 while (!priv->force_quit) {
810 enum can_state new_state;
813 int can_id = 0, data1 = 0;
815 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
817 /* mask out flags we don't care about */
818 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
820 /* receive buffer 0 */
821 if (intf & CANINTF_RX0IF) {
822 mcp251x_hw_rx(spi, 0);
824 * Free one buffer ASAP
825 * (The MCP2515 does this automatically.)
827 if (mcp251x_is_2510(spi))
828 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
831 /* receive buffer 1 */
832 if (intf & CANINTF_RX1IF) {
833 mcp251x_hw_rx(spi, 1);
834 /* the MCP2515 does this automatically */
835 if (mcp251x_is_2510(spi))
836 clear_intf |= CANINTF_RX1IF;
839 /* any error or tx interrupt we need to clear? */
840 if (intf & (CANINTF_ERR | CANINTF_TX))
841 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
843 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
846 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
848 /* Update can state */
849 if (eflag & EFLG_TXBO) {
850 new_state = CAN_STATE_BUS_OFF;
851 can_id |= CAN_ERR_BUSOFF;
852 } else if (eflag & EFLG_TXEP) {
853 new_state = CAN_STATE_ERROR_PASSIVE;
854 can_id |= CAN_ERR_CRTL;
855 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
856 } else if (eflag & EFLG_RXEP) {
857 new_state = CAN_STATE_ERROR_PASSIVE;
858 can_id |= CAN_ERR_CRTL;
859 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
860 } else if (eflag & EFLG_TXWAR) {
861 new_state = CAN_STATE_ERROR_WARNING;
862 can_id |= CAN_ERR_CRTL;
863 data1 |= CAN_ERR_CRTL_TX_WARNING;
864 } else if (eflag & EFLG_RXWAR) {
865 new_state = CAN_STATE_ERROR_WARNING;
866 can_id |= CAN_ERR_CRTL;
867 data1 |= CAN_ERR_CRTL_RX_WARNING;
869 new_state = CAN_STATE_ERROR_ACTIVE;
872 /* Update can state statistics */
873 switch (priv->can.state) {
874 case CAN_STATE_ERROR_ACTIVE:
875 if (new_state >= CAN_STATE_ERROR_WARNING &&
876 new_state <= CAN_STATE_BUS_OFF)
877 priv->can.can_stats.error_warning++;
878 case CAN_STATE_ERROR_WARNING: /* fallthrough */
879 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
880 new_state <= CAN_STATE_BUS_OFF)
881 priv->can.can_stats.error_passive++;
886 priv->can.state = new_state;
888 if (intf & CANINTF_ERRIF) {
889 /* Handle overflow counters */
890 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
891 if (eflag & EFLG_RX0OVR) {
892 net->stats.rx_over_errors++;
893 net->stats.rx_errors++;
895 if (eflag & EFLG_RX1OVR) {
896 net->stats.rx_over_errors++;
897 net->stats.rx_errors++;
899 can_id |= CAN_ERR_CRTL;
900 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
902 mcp251x_error_skb(net, can_id, data1);
905 if (priv->can.state == CAN_STATE_BUS_OFF) {
906 if (priv->can.restart_ms == 0) {
907 priv->force_quit = 1;
909 mcp251x_hw_sleep(spi);
917 if (intf & CANINTF_TX) {
918 net->stats.tx_packets++;
919 net->stats.tx_bytes += priv->tx_len - 1;
920 can_led_event(net, CAN_LED_EVENT_TX);
922 can_get_echo_skb(net, 0);
925 netif_wake_queue(net);
929 mutex_unlock(&priv->mcp_lock);
933 static int mcp251x_open(struct net_device *net)
935 struct mcp251x_priv *priv = netdev_priv(net);
936 struct spi_device *spi = priv->spi;
937 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING;
940 ret = open_candev(net);
942 dev_err(&spi->dev, "unable to set initial baudrate!\n");
946 mutex_lock(&priv->mcp_lock);
947 mcp251x_power_enable(priv->transceiver, 1);
949 priv->force_quit = 0;
953 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
954 flags, DEVICE_NAME, priv);
956 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
957 mcp251x_power_enable(priv->transceiver, 0);
962 priv->wq = create_freezable_workqueue("mcp251x_wq");
963 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
964 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
966 ret = mcp251x_hw_reset(spi);
968 mcp251x_open_clean(net);
971 ret = mcp251x_setup(net, priv, spi);
973 mcp251x_open_clean(net);
976 ret = mcp251x_set_normal_mode(spi);
978 mcp251x_open_clean(net);
982 can_led_event(net, CAN_LED_EVENT_OPEN);
984 netif_wake_queue(net);
987 mutex_unlock(&priv->mcp_lock);
991 static const struct net_device_ops mcp251x_netdev_ops = {
992 .ndo_open = mcp251x_open,
993 .ndo_stop = mcp251x_stop,
994 .ndo_start_xmit = mcp251x_hard_start_xmit,
997 static int mcp251x_can_probe(struct spi_device *spi)
999 struct net_device *net;
1000 struct mcp251x_priv *priv;
1001 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
1005 /* Platform data is required for osc freq */
1008 /* Allocate can/net device */
1009 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1015 net->netdev_ops = &mcp251x_netdev_ops;
1016 net->flags |= IFF_ECHO;
1018 priv = netdev_priv(net);
1019 priv->can.bittiming_const = &mcp251x_bittiming_const;
1020 priv->can.do_set_mode = mcp251x_do_set_mode;
1021 priv->can.clock.freq = pdata->oscillator_frequency / 2;
1022 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1023 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1024 priv->model = spi_get_device_id(spi)->driver_data;
1027 priv->power = devm_regulator_get(&spi->dev, "vdd");
1028 priv->transceiver = devm_regulator_get(&spi->dev, "xceiver");
1029 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1030 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1031 ret = -EPROBE_DEFER;
1035 ret = mcp251x_power_enable(priv->power, 1);
1039 spi_set_drvdata(spi, priv);
1042 mutex_init(&priv->mcp_lock);
1044 /* If requested, allocate DMA buffers */
1045 if (mcp251x_enable_dma) {
1046 spi->dev.coherent_dma_mask = ~0;
1049 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1050 * that much and share it between Tx and Rx DMA buffers.
1052 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
1057 if (priv->spi_tx_buf) {
1058 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
1059 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1062 /* Fall back to non-DMA */
1063 mcp251x_enable_dma = 0;
1067 /* Allocate non-DMA buffers */
1068 if (!mcp251x_enable_dma) {
1069 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1071 if (!priv->spi_tx_buf) {
1075 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1077 if (!priv->spi_rx_buf) {
1083 SET_NETDEV_DEV(net, &spi->dev);
1085 /* Configure the SPI bus */
1086 spi->mode = spi->mode ? : SPI_MODE_0;
1087 if (mcp251x_is_2510(spi))
1088 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1090 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1091 spi->bits_per_word = 8;
1094 /* Here is OK to not lock the MCP, no one knows about it yet */
1095 if (!mcp251x_hw_probe(spi)) {
1099 mcp251x_hw_sleep(spi);
1101 ret = register_candev(net);
1105 devm_can_led_init(net);
1107 dev_info(&spi->dev, "probed\n");
1112 if (mcp251x_enable_dma)
1113 dma_free_coherent(&spi->dev, PAGE_SIZE,
1114 priv->spi_tx_buf, priv->spi_tx_dma);
1115 mcp251x_power_enable(priv->power, 0);
1119 dev_err(&spi->dev, "probe failed\n");
1124 static int mcp251x_can_remove(struct spi_device *spi)
1126 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1127 struct net_device *net = priv->net;
1129 unregister_candev(net);
1131 if (mcp251x_enable_dma) {
1132 dma_free_coherent(&spi->dev, PAGE_SIZE,
1133 priv->spi_tx_buf, priv->spi_tx_dma);
1136 mcp251x_power_enable(priv->power, 0);
1143 #ifdef CONFIG_PM_SLEEP
1145 static int mcp251x_can_suspend(struct device *dev)
1147 struct spi_device *spi = to_spi_device(dev);
1148 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1149 struct net_device *net = priv->net;
1151 priv->force_quit = 1;
1152 disable_irq(spi->irq);
1154 * Note: at this point neither IST nor workqueues are running.
1155 * open/stop cannot be called anyway so locking is not needed
1157 if (netif_running(net)) {
1158 netif_device_detach(net);
1160 mcp251x_hw_sleep(spi);
1161 mcp251x_power_enable(priv->transceiver, 0);
1162 priv->after_suspend = AFTER_SUSPEND_UP;
1164 priv->after_suspend = AFTER_SUSPEND_DOWN;
1167 if (!IS_ERR(priv->power)) {
1168 regulator_disable(priv->power);
1169 priv->after_suspend |= AFTER_SUSPEND_POWER;
1175 static int mcp251x_can_resume(struct device *dev)
1177 struct spi_device *spi = to_spi_device(dev);
1178 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1180 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1181 mcp251x_power_enable(priv->power, 1);
1182 queue_work(priv->wq, &priv->restart_work);
1184 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1185 mcp251x_power_enable(priv->transceiver, 1);
1186 queue_work(priv->wq, &priv->restart_work);
1188 priv->after_suspend = 0;
1191 priv->force_quit = 0;
1192 enable_irq(spi->irq);
1197 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1198 mcp251x_can_resume);
1200 static const struct spi_device_id mcp251x_id_table[] = {
1201 { "mcp2510", CAN_MCP251X_MCP2510 },
1202 { "mcp2515", CAN_MCP251X_MCP2515 },
1206 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1208 static struct spi_driver mcp251x_can_driver = {
1210 .name = DEVICE_NAME,
1211 .owner = THIS_MODULE,
1212 .pm = &mcp251x_can_pm_ops,
1215 .id_table = mcp251x_id_table,
1216 .probe = mcp251x_can_probe,
1217 .remove = mcp251x_can_remove,
1219 module_spi_driver(mcp251x_can_driver);
1221 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1222 "Christian Pellegrin <chripell@evolware.org>");
1223 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1224 MODULE_LICENSE("GPL v2");