Pileus Git - ~andy/linux/blob - drivers/net/benet/be_cmds.h

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 /*
  19  * The driver sends configuration and managements command requests to the
  20  * firmware in the BE. These requests are communicated to the processor
  21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22  * WRB inside a MAILBOX.
  23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24  */
  25
  26 struct be_sge {
  27         u32 pa_lo;
  28         u32 pa_hi;
  29         u32 len;
  30 };
  31
  32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35 struct be_mcc_wrb {
  36         u32 embedded;           /* dword 0 */
  37         u32 payload_length;     /* dword 1 */
  38         u32 tag0;               /* dword 2 */
  39         u32 tag1;               /* dword 3 */
  40         u32 rsvd;               /* dword 4 */
  41         union {
  42                 u8 embedded_payload[236]; /* used by embedded cmds */
  43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
  44         } payload;
  45 };
  46
  47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
  48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52 /* Completion Status */
  53 enum {
  54         MCC_STATUS_SUCCESS = 0x0,
  55 /* The client does not have sufficient privileges to execute the command */
  56         MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
  57 /* A parameter in the command was invalid. */
  58         MCC_STATUS_INVALID_PARAMETER = 0x2,
  59 /* There are insufficient chip resources to execute the command */
  60         MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
  61 /* The command is completing because the queue was getting flushed */
  62         MCC_STATUS_QUEUE_FLUSHING = 0x4,
  63 /* The command is completing with a DMA error */
  64         MCC_STATUS_DMA_FAILED = 0x5,
  65         MCC_STATUS_NOT_SUPPORTED = 66
  66 };
  67
  68 #define CQE_STATUS_COMPL_MASK           0xFFFF
  69 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  70 #define CQE_STATUS_EXTD_MASK            0xFFFF
  71 #define CQE_STATUS_EXTD_SHIFT           16      /* bits 16 - 31 */
  72
  73 struct be_mcc_compl {
  74         u32 status;             /* dword 0 */
  75         u32 tag0;               /* dword 1 */
  76         u32 tag1;               /* dword 2 */
  77         u32 flags;              /* dword 3 */
  78 };
  79
  80 /* When the async bit of mcc_compl is set, the last 4 bytes of
  81  * mcc_compl is interpreted as follows:
  82  */
  83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
  84 #define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
  85 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT  16
  86 #define ASYNC_TRAILER_EVENT_TYPE_MASK   0xFF
  87 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
  88 #define ASYNC_EVENT_CODE_GRP_5          0x5
  89 #define ASYNC_EVENT_QOS_SPEED           0x1
  90 #define ASYNC_EVENT_COS_PRIORITY        0x2
  91 #define ASYNC_EVENT_PVID_STATE          0x3
  92 struct be_async_event_trailer {
  93         u32 code;
  94 };
  95
  96 enum {
  97         ASYNC_EVENT_LINK_DOWN   = 0x0,
  98         ASYNC_EVENT_LINK_UP     = 0x1
  99 };
 100
 101 /* When the event code of an async trailer is link-state, the mcc_compl
 102  * must be interpreted as follows
 103  */
 104 struct be_async_event_link_state {
 105         u8 physical_port;
 106         u8 port_link_status;
 107         u8 port_duplex;
 108         u8 port_speed;
 109         u8 port_fault;
 110         u8 rsvd0[7];
 111         struct be_async_event_trailer trailer;
 112 } __packed;
 113
 114 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
 115  * the mcc_compl must be interpreted as follows
 116  */
 117 struct be_async_event_grp5_qos_link_speed {
 118         u8 physical_port;
 119         u8 rsvd[5];
 120         u16 qos_link_speed;
 121         u32 event_tag;
 122         struct be_async_event_trailer trailer;
 123 } __packed;
 124
 125 /* When the event code of an async trailer is GRP5 and event type is
 126  * CoS-Priority, the mcc_compl must be interpreted as follows
 127  */
 128 struct be_async_event_grp5_cos_priority {
 129         u8 physical_port;
 130         u8 available_priority_bmap;
 131         u8 reco_default_priority;
 132         u8 valid;
 133         u8 rsvd0;
 134         u8 event_tag;
 135         struct be_async_event_trailer trailer;
 136 } __packed;
 137
 138 /* When the event code of an async trailer is GRP5 and event type is
 139  * PVID state, the mcc_compl must be interpreted as follows
 140  */
 141 struct be_async_event_grp5_pvid_state {
 142         u8 enabled;
 143         u8 rsvd0;
 144         u16 tag;
 145         u32 event_tag;
 146         u32 rsvd1;
 147         struct be_async_event_trailer trailer;
 148 } __packed;
 149
 150 struct be_mcc_mailbox {
 151         struct be_mcc_wrb wrb;
 152         struct be_mcc_compl compl;
 153 };
 154
 155 #define CMD_SUBSYSTEM_COMMON    0x1
 156 #define CMD_SUBSYSTEM_ETH       0x3
 157 #define CMD_SUBSYSTEM_LOWLEVEL  0xb
 158
 159 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
 160 #define OPCODE_COMMON_NTWK_MAC_SET                      2
 161 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
 162 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
 163 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
 164 #define OPCODE_COMMON_READ_FLASHROM                     6
 165 #define OPCODE_COMMON_WRITE_FLASHROM                    7
 166 #define OPCODE_COMMON_CQ_CREATE                         12
 167 #define OPCODE_COMMON_EQ_CREATE                         13
 168 #define OPCODE_COMMON_MCC_CREATE                        21
 169 #define OPCODE_COMMON_SET_QOS                           28
 170 #define OPCODE_COMMON_MCC_CREATE_EXT                    90
 171 #define OPCODE_COMMON_SEEPROM_READ                      30
 172 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES               32
 173 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
 174 #define OPCODE_COMMON_GET_FW_VERSION                    35
 175 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
 176 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
 177 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
 178 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 179 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 180 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 181 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 182 #define OPCODE_COMMON_MCC_DESTROY                       53
 183 #define OPCODE_COMMON_CQ_DESTROY                        54
 184 #define OPCODE_COMMON_EQ_DESTROY                        55
 185 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 186 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 187 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 188 #define OPCODE_COMMON_FUNCTION_RESET                    61
 189 #define OPCODE_COMMON_MANAGE_FAT                        68
 190 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON             69
 191 #define OPCODE_COMMON_GET_BEACON_STATE                  70
 192 #define OPCODE_COMMON_READ_TRANSRECV_DATA               73
 193 #define OPCODE_COMMON_GET_PHY_DETAILS                   102
 194 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP           103
 195 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES    121
 196
 197 #define OPCODE_ETH_RSS_CONFIG                           1
 198 #define OPCODE_ETH_ACPI_CONFIG                          2
 199 #define OPCODE_ETH_PROMISCUOUS                          3
 200 #define OPCODE_ETH_GET_STATISTICS                       4
 201 #define OPCODE_ETH_TX_CREATE                            7
 202 #define OPCODE_ETH_RX_CREATE                            8
 203 #define OPCODE_ETH_TX_DESTROY                           9
 204 #define OPCODE_ETH_RX_DESTROY                           10
 205 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG                12
 206 #define OPCODE_ETH_GET_PPORT_STATS                      18
 207
 208 #define OPCODE_LOWLEVEL_HOST_DDR_DMA                    17
 209 #define OPCODE_LOWLEVEL_LOOPBACK_TEST                   18
 210 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE               19
 211
 212 struct be_cmd_req_hdr {
 213         u8 opcode;              /* dword 0 */
 214         u8 subsystem;           /* dword 0 */
 215         u8 port_number;         /* dword 0 */
 216         u8 domain;              /* dword 0 */
 217         u32 timeout;            /* dword 1 */
 218         u32 request_length;     /* dword 2 */
 219         u8 version;             /* dword 3 */
 220         u8 rsvd[3];             /* dword 3 */
 221 };
 222
 223 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 224 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 225 struct be_cmd_resp_hdr {
 226         u32 info;               /* dword 0 */
 227         u32 status;             /* dword 1 */
 228         u32 response_length;    /* dword 2 */
 229         u32 actual_resp_len;    /* dword 3 */
 230 };
 231
 232 struct phys_addr {
 233         u32 lo;
 234         u32 hi;
 235 };
 236
 237 /**************************
 238  * BE Command definitions *
 239  **************************/
 240
 241 /* Pseudo amap definition in which each bit of the actual structure is defined
 242  * as a byte: used to calculate offset/shift/mask of each field */
 243 struct amap_eq_context {
 244         u8 cidx[13];            /* dword 0*/
 245         u8 rsvd0[3];            /* dword 0*/
 246         u8 epidx[13];           /* dword 0*/
 247         u8 valid;               /* dword 0*/
 248         u8 rsvd1;               /* dword 0*/
 249         u8 size;                /* dword 0*/
 250         u8 pidx[13];            /* dword 1*/
 251         u8 rsvd2[3];            /* dword 1*/
 252         u8 pd[10];              /* dword 1*/
 253         u8 count[3];            /* dword 1*/
 254         u8 solevent;            /* dword 1*/
 255         u8 stalled;             /* dword 1*/
 256         u8 armed;               /* dword 1*/
 257         u8 rsvd3[4];            /* dword 2*/
 258         u8 func[8];             /* dword 2*/
 259         u8 rsvd4;               /* dword 2*/
 260         u8 delaymult[10];       /* dword 2*/
 261         u8 rsvd5[2];            /* dword 2*/
 262         u8 phase[2];            /* dword 2*/
 263         u8 nodelay;             /* dword 2*/
 264         u8 rsvd6[4];            /* dword 2*/
 265         u8 rsvd7[32];           /* dword 3*/
 266 } __packed;
 267
 268 struct be_cmd_req_eq_create {
 269         struct be_cmd_req_hdr hdr;
 270         u16 num_pages;          /* sword */
 271         u16 rsvd0;              /* sword */
 272         u8 context[sizeof(struct amap_eq_context) / 8];
 273         struct phys_addr pages[8];
 274 } __packed;
 275
 276 struct be_cmd_resp_eq_create {
 277         struct be_cmd_resp_hdr resp_hdr;
 278         u16 eq_id;              /* sword */
 279         u16 rsvd0;              /* sword */
 280 } __packed;
 281
 282 /******************** Mac query ***************************/
 283 enum {
 284         MAC_ADDRESS_TYPE_STORAGE = 0x0,
 285         MAC_ADDRESS_TYPE_NETWORK = 0x1,
 286         MAC_ADDRESS_TYPE_PD = 0x2,
 287         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 288 };
 289
 290 struct mac_addr {
 291         u16 size_of_struct;
 292         u8 addr[ETH_ALEN];
 293 } __packed;
 294
 295 struct be_cmd_req_mac_query {
 296         struct be_cmd_req_hdr hdr;
 297         u8 type;
 298         u8 permanent;
 299         u16 if_id;
 300 } __packed;
 301
 302 struct be_cmd_resp_mac_query {
 303         struct be_cmd_resp_hdr hdr;
 304         struct mac_addr mac;
 305 };
 306
 307 /******************** PMac Add ***************************/
 308 struct be_cmd_req_pmac_add {
 309         struct be_cmd_req_hdr hdr;
 310         u32 if_id;
 311         u8 mac_address[ETH_ALEN];
 312         u8 rsvd0[2];
 313 } __packed;
 314
 315 struct be_cmd_resp_pmac_add {
 316         struct be_cmd_resp_hdr hdr;
 317         u32 pmac_id;
 318 };
 319
 320 /******************** PMac Del ***************************/
 321 struct be_cmd_req_pmac_del {
 322         struct be_cmd_req_hdr hdr;
 323         u32 if_id;
 324         u32 pmac_id;
 325 };
 326
 327 /******************** Create CQ ***************************/
 328 /* Pseudo amap definition in which each bit of the actual structure is defined
 329  * as a byte: used to calculate offset/shift/mask of each field */
 330 struct amap_cq_context_be {
 331         u8 cidx[11];            /* dword 0*/
 332         u8 rsvd0;               /* dword 0*/
 333         u8 coalescwm[2];        /* dword 0*/
 334         u8 nodelay;             /* dword 0*/
 335         u8 epidx[11];           /* dword 0*/
 336         u8 rsvd1;               /* dword 0*/
 337         u8 count[2];            /* dword 0*/
 338         u8 valid;               /* dword 0*/
 339         u8 solevent;            /* dword 0*/
 340         u8 eventable;           /* dword 0*/
 341         u8 pidx[11];            /* dword 1*/
 342         u8 rsvd2;               /* dword 1*/
 343         u8 pd[10];              /* dword 1*/
 344         u8 eqid[8];             /* dword 1*/
 345         u8 stalled;             /* dword 1*/
 346         u8 armed;               /* dword 1*/
 347         u8 rsvd3[4];            /* dword 2*/
 348         u8 func[8];             /* dword 2*/
 349         u8 rsvd4[20];           /* dword 2*/
 350         u8 rsvd5[32];           /* dword 3*/
 351 } __packed;
 352
 353 struct amap_cq_context_lancer {
 354         u8 rsvd0[12];           /* dword 0*/
 355         u8 coalescwm[2];        /* dword 0*/
 356         u8 nodelay;             /* dword 0*/
 357         u8 rsvd1[12];           /* dword 0*/
 358         u8 count[2];            /* dword 0*/
 359         u8 valid;               /* dword 0*/
 360         u8 rsvd2;               /* dword 0*/
 361         u8 eventable;           /* dword 0*/
 362         u8 eqid[16];            /* dword 1*/
 363         u8 rsvd3[15];           /* dword 1*/
 364         u8 armed;               /* dword 1*/
 365         u8 rsvd4[32];           /* dword 2*/
 366         u8 rsvd5[32];           /* dword 3*/
 367 } __packed;
 368
 369 struct be_cmd_req_cq_create {
 370         struct be_cmd_req_hdr hdr;
 371         u16 num_pages;
 372         u8 page_size;
 373         u8 rsvd0;
 374         u8 context[sizeof(struct amap_cq_context_be) / 8];
 375         struct phys_addr pages[8];
 376 } __packed;
 377
 378
 379 struct be_cmd_resp_cq_create {
 380         struct be_cmd_resp_hdr hdr;
 381         u16 cq_id;
 382         u16 rsvd0;
 383 } __packed;
 384
 385 struct be_cmd_req_get_fat {
 386         struct be_cmd_req_hdr hdr;
 387         u32 fat_operation;
 388         u32 read_log_offset;
 389         u32 read_log_length;
 390         u32 data_buffer_size;
 391         u32 data_buffer[1];
 392 } __packed;
 393
 394 struct be_cmd_resp_get_fat {
 395         struct be_cmd_resp_hdr hdr;
 396         u32 log_size;
 397         u32 read_log_length;
 398         u32 rsvd[2];
 399         u32 data_buffer[1];
 400 } __packed;
 401
 402
 403 /******************** Create MCCQ ***************************/
 404 /* Pseudo amap definition in which each bit of the actual structure is defined
 405  * as a byte: used to calculate offset/shift/mask of each field */
 406 struct amap_mcc_context_be {
 407         u8 con_index[14];
 408         u8 rsvd0[2];
 409         u8 ring_size[4];
 410         u8 fetch_wrb;
 411         u8 fetch_r2t;
 412         u8 cq_id[10];
 413         u8 prod_index[14];
 414         u8 fid[8];
 415         u8 pdid[9];
 416         u8 valid;
 417         u8 rsvd1[32];
 418         u8 rsvd2[32];
 419 } __packed;
 420
 421 struct amap_mcc_context_lancer {
 422         u8 async_cq_id[16];
 423         u8 ring_size[4];
 424         u8 rsvd0[12];
 425         u8 rsvd1[31];
 426         u8 valid;
 427         u8 async_cq_valid[1];
 428         u8 rsvd2[31];
 429         u8 rsvd3[32];
 430 } __packed;
 431
 432 struct be_cmd_req_mcc_create {
 433         struct be_cmd_req_hdr hdr;
 434         u16 num_pages;
 435         u16 cq_id;
 436         u32 async_event_bitmap[1];
 437         u8 context[sizeof(struct amap_mcc_context_be) / 8];
 438         struct phys_addr pages[8];
 439 } __packed;
 440
 441 struct be_cmd_resp_mcc_create {
 442         struct be_cmd_resp_hdr hdr;
 443         u16 id;
 444         u16 rsvd0;
 445 } __packed;
 446
 447 /******************** Create TxQ ***************************/
 448 #define BE_ETH_TX_RING_TYPE_STANDARD            2
 449 #define BE_ULP1_NUM                             1
 450
 451 /* Pseudo amap definition in which each bit of the actual structure is defined
 452  * as a byte: used to calculate offset/shift/mask of each field */
 453 struct amap_tx_context {
 454         u8 if_id[16];           /* dword 0 */
 455         u8 tx_ring_size[4];     /* dword 0 */
 456         u8 rsvd1[26];           /* dword 0 */
 457         u8 pci_func_id[8];      /* dword 1 */
 458         u8 rsvd2[9];            /* dword 1 */
 459         u8 ctx_valid;           /* dword 1 */
 460         u8 cq_id_send[16];      /* dword 2 */
 461         u8 rsvd3[16];           /* dword 2 */
 462         u8 rsvd4[32];           /* dword 3 */
 463         u8 rsvd5[32];           /* dword 4 */
 464         u8 rsvd6[32];           /* dword 5 */
 465         u8 rsvd7[32];           /* dword 6 */
 466         u8 rsvd8[32];           /* dword 7 */
 467         u8 rsvd9[32];           /* dword 8 */
 468         u8 rsvd10[32];          /* dword 9 */
 469         u8 rsvd11[32];          /* dword 10 */
 470         u8 rsvd12[32];          /* dword 11 */
 471         u8 rsvd13[32];          /* dword 12 */
 472         u8 rsvd14[32];          /* dword 13 */
 473         u8 rsvd15[32];          /* dword 14 */
 474         u8 rsvd16[32];          /* dword 15 */
 475 } __packed;
 476
 477 struct be_cmd_req_eth_tx_create {
 478         struct be_cmd_req_hdr hdr;
 479         u8 num_pages;
 480         u8 ulp_num;
 481         u8 type;
 482         u8 bound_port;
 483         u8 context[sizeof(struct amap_tx_context) / 8];
 484         struct phys_addr pages[8];
 485 } __packed;
 486
 487 struct be_cmd_resp_eth_tx_create {
 488         struct be_cmd_resp_hdr hdr;
 489         u16 cid;
 490         u16 rsvd0;
 491 } __packed;
 492
 493 /******************** Create RxQ ***************************/
 494 struct be_cmd_req_eth_rx_create {
 495         struct be_cmd_req_hdr hdr;
 496         u16 cq_id;
 497         u8 frag_size;
 498         u8 num_pages;
 499         struct phys_addr pages[2];
 500         u32 interface_id;
 501         u16 max_frame_size;
 502         u16 rsvd0;
 503         u32 rss_queue;
 504 } __packed;
 505
 506 struct be_cmd_resp_eth_rx_create {
 507         struct be_cmd_resp_hdr hdr;
 508         u16 id;
 509         u8 rss_id;
 510         u8 rsvd0;
 511 } __packed;
 512
 513 /******************** Q Destroy  ***************************/
 514 /* Type of Queue to be destroyed */
 515 enum {
 516         QTYPE_EQ = 1,
 517         QTYPE_CQ,
 518         QTYPE_TXQ,
 519         QTYPE_RXQ,
 520         QTYPE_MCCQ
 521 };
 522
 523 struct be_cmd_req_q_destroy {
 524         struct be_cmd_req_hdr hdr;
 525         u16 id;
 526         u16 bypass_flush;       /* valid only for rx q destroy */
 527 } __packed;
 528
 529 /************ I/f Create (it's actually I/f Config Create)**********/
 530
 531 /* Capability flags for the i/f */
 532 enum be_if_flags {
 533         BE_IF_FLAGS_RSS = 0x4,
 534         BE_IF_FLAGS_PROMISCUOUS = 0x8,
 535         BE_IF_FLAGS_BROADCAST = 0x10,
 536         BE_IF_FLAGS_UNTAGGED = 0x20,
 537         BE_IF_FLAGS_ULP = 0x40,
 538         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 539         BE_IF_FLAGS_VLAN = 0x100,
 540         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 541         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 542         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
 543         BE_IF_FLAGS_MULTICAST = 0x1000
 544 };
 545
 546 /* An RX interface is an object with one or more MAC addresses and
 547  * filtering capabilities. */
 548 struct be_cmd_req_if_create {
 549         struct be_cmd_req_hdr hdr;
 550         u32 version;            /* ignore currently */
 551         u32 capability_flags;
 552         u32 enable_flags;
 553         u8 mac_addr[ETH_ALEN];
 554         u8 rsvd0;
 555         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 556         u32 vlan_tag;    /* not used currently */
 557 } __packed;
 558
 559 struct be_cmd_resp_if_create {
 560         struct be_cmd_resp_hdr hdr;
 561         u32 interface_id;
 562         u32 pmac_id;
 563 };
 564
 565 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
 566 struct be_cmd_req_if_destroy {
 567         struct be_cmd_req_hdr hdr;
 568         u32 interface_id;
 569 };
 570
 571 /*************** HW Stats Get **********************************/
 572 struct be_port_rxf_stats_v0 {
 573         u32 rx_bytes_lsd;       /* dword 0*/
 574         u32 rx_bytes_msd;       /* dword 1*/
 575         u32 rx_total_frames;    /* dword 2*/
 576         u32 rx_unicast_frames;  /* dword 3*/
 577         u32 rx_multicast_frames;        /* dword 4*/
 578         u32 rx_broadcast_frames;        /* dword 5*/
 579         u32 rx_crc_errors;      /* dword 6*/
 580         u32 rx_alignment_symbol_errors; /* dword 7*/
 581         u32 rx_pause_frames;    /* dword 8*/
 582         u32 rx_control_frames;  /* dword 9*/
 583         u32 rx_in_range_errors; /* dword 10*/
 584         u32 rx_out_range_errors;        /* dword 11*/
 585         u32 rx_frame_too_long;  /* dword 12*/
 586         u32 rx_address_match_errors;    /* dword 13*/
 587         u32 rx_vlan_mismatch;   /* dword 14*/
 588         u32 rx_dropped_too_small;       /* dword 15*/
 589         u32 rx_dropped_too_short;       /* dword 16*/
 590         u32 rx_dropped_header_too_small;        /* dword 17*/
 591         u32 rx_dropped_tcp_length;      /* dword 18*/
 592         u32 rx_dropped_runt;    /* dword 19*/
 593         u32 rx_64_byte_packets; /* dword 20*/
 594         u32 rx_65_127_byte_packets;     /* dword 21*/
 595         u32 rx_128_256_byte_packets;    /* dword 22*/
 596         u32 rx_256_511_byte_packets;    /* dword 23*/
 597         u32 rx_512_1023_byte_packets;   /* dword 24*/
 598         u32 rx_1024_1518_byte_packets;  /* dword 25*/
 599         u32 rx_1519_2047_byte_packets;  /* dword 26*/
 600         u32 rx_2048_4095_byte_packets;  /* dword 27*/
 601         u32 rx_4096_8191_byte_packets;  /* dword 28*/
 602         u32 rx_8192_9216_byte_packets;  /* dword 29*/
 603         u32 rx_ip_checksum_errs;        /* dword 30*/
 604         u32 rx_tcp_checksum_errs;       /* dword 31*/
 605         u32 rx_udp_checksum_errs;       /* dword 32*/
 606         u32 rx_non_rss_packets; /* dword 33*/
 607         u32 rx_ipv4_packets;    /* dword 34*/
 608         u32 rx_ipv6_packets;    /* dword 35*/
 609         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 610         u32 rx_ipv4_bytes_msd;  /* dword 37*/
 611         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 612         u32 rx_ipv6_bytes_msd;  /* dword 39*/
 613         u32 rx_chute1_packets;  /* dword 40*/
 614         u32 rx_chute2_packets;  /* dword 41*/
 615         u32 rx_chute3_packets;  /* dword 42*/
 616         u32 rx_management_packets;      /* dword 43*/
 617         u32 rx_switched_unicast_packets;        /* dword 44*/
 618         u32 rx_switched_multicast_packets;      /* dword 45*/
 619         u32 rx_switched_broadcast_packets;      /* dword 46*/
 620         u32 tx_bytes_lsd;       /* dword 47*/
 621         u32 tx_bytes_msd;       /* dword 48*/
 622         u32 tx_unicastframes;   /* dword 49*/
 623         u32 tx_multicastframes; /* dword 50*/
 624         u32 tx_broadcastframes; /* dword 51*/
 625         u32 tx_pauseframes;     /* dword 52*/
 626         u32 tx_controlframes;   /* dword 53*/
 627         u32 tx_64_byte_packets; /* dword 54*/
 628         u32 tx_65_127_byte_packets;     /* dword 55*/
 629         u32 tx_128_256_byte_packets;    /* dword 56*/
 630         u32 tx_256_511_byte_packets;    /* dword 57*/
 631         u32 tx_512_1023_byte_packets;   /* dword 58*/
 632         u32 tx_1024_1518_byte_packets;  /* dword 59*/
 633         u32 tx_1519_2047_byte_packets;  /* dword 60*/
 634         u32 tx_2048_4095_byte_packets;  /* dword 61*/
 635         u32 tx_4096_8191_byte_packets;  /* dword 62*/
 636         u32 tx_8192_9216_byte_packets;  /* dword 63*/
 637         u32 rx_fifo_overflow;   /* dword 64*/
 638         u32 rx_input_fifo_overflow;     /* dword 65*/
 639 };
 640
 641 struct be_rxf_stats_v0 {
 642         struct be_port_rxf_stats_v0 port[2];
 643         u32 rx_drops_no_pbuf;   /* dword 132*/
 644         u32 rx_drops_no_txpb;   /* dword 133*/
 645         u32 rx_drops_no_erx_descr;      /* dword 134*/
 646         u32 rx_drops_no_tpre_descr;     /* dword 135*/
 647         u32 management_rx_port_packets; /* dword 136*/
 648         u32 management_rx_port_bytes;   /* dword 137*/
 649         u32 management_rx_port_pause_frames;    /* dword 138*/
 650         u32 management_rx_port_errors;  /* dword 139*/
 651         u32 management_tx_port_packets; /* dword 140*/
 652         u32 management_tx_port_bytes;   /* dword 141*/
 653         u32 management_tx_port_pause;   /* dword 142*/
 654         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 655         u32 rx_drops_too_many_frags;    /* dword 144*/
 656         u32 rx_drops_invalid_ring;      /* dword 145*/
 657         u32 forwarded_packets;  /* dword 146*/
 658         u32 rx_drops_mtu;       /* dword 147*/
 659         u32 rsvd0[7];
 660         u32 port0_jabber_events;
 661         u32 port1_jabber_events;
 662         u32 rsvd1[6];
 663 };
 664
 665 struct be_erx_stats_v0 {
 666         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 667         u32 rsvd[4];
 668 };
 669
 670 struct be_pmem_stats {
 671         u32 eth_red_drops;
 672         u32 rsvd[5];
 673 };
 674
 675 struct be_hw_stats_v0 {
 676         struct be_rxf_stats_v0 rxf;
 677         u32 rsvd[48];
 678         struct be_erx_stats_v0 erx;
 679         struct be_pmem_stats pmem;
 680 };
 681
 682 struct be_cmd_req_get_stats_v0 {
 683         struct be_cmd_req_hdr hdr;
 684         u8 rsvd[sizeof(struct be_hw_stats_v0)];
 685 };
 686
 687 struct be_cmd_resp_get_stats_v0 {
 688         struct be_cmd_resp_hdr hdr;
 689         struct be_hw_stats_v0 hw_stats;
 690 };
 691
 692 #define make_64bit_val(hi_32, lo_32)    (((u64)hi_32<<32) | lo_32)
 693 struct lancer_cmd_pport_stats {
 694         u32 tx_packets_lo;
 695         u32 tx_packets_hi;
 696         u32 tx_unicast_packets_lo;
 697         u32 tx_unicast_packets_hi;
 698         u32 tx_multicast_packets_lo;
 699         u32 tx_multicast_packets_hi;
 700         u32 tx_broadcast_packets_lo;
 701         u32 tx_broadcast_packets_hi;
 702         u32 tx_bytes_lo;
 703         u32 tx_bytes_hi;
 704         u32 tx_unicast_bytes_lo;
 705         u32 tx_unicast_bytes_hi;
 706         u32 tx_multicast_bytes_lo;
 707         u32 tx_multicast_bytes_hi;
 708         u32 tx_broadcast_bytes_lo;
 709         u32 tx_broadcast_bytes_hi;
 710         u32 tx_discards_lo;
 711         u32 tx_discards_hi;
 712         u32 tx_errors_lo;
 713         u32 tx_errors_hi;
 714         u32 tx_pause_frames_lo;
 715         u32 tx_pause_frames_hi;
 716         u32 tx_pause_on_frames_lo;
 717         u32 tx_pause_on_frames_hi;
 718         u32 tx_pause_off_frames_lo;
 719         u32 tx_pause_off_frames_hi;
 720         u32 tx_internal_mac_errors_lo;
 721         u32 tx_internal_mac_errors_hi;
 722         u32 tx_control_frames_lo;
 723         u32 tx_control_frames_hi;
 724         u32 tx_packets_64_bytes_lo;
 725         u32 tx_packets_64_bytes_hi;
 726         u32 tx_packets_65_to_127_bytes_lo;
 727         u32 tx_packets_65_to_127_bytes_hi;
 728         u32 tx_packets_128_to_255_bytes_lo;
 729         u32 tx_packets_128_to_255_bytes_hi;
 730         u32 tx_packets_256_to_511_bytes_lo;
 731         u32 tx_packets_256_to_511_bytes_hi;
 732         u32 tx_packets_512_to_1023_bytes_lo;
 733         u32 tx_packets_512_to_1023_bytes_hi;
 734         u32 tx_packets_1024_to_1518_bytes_lo;
 735         u32 tx_packets_1024_to_1518_bytes_hi;
 736         u32 tx_packets_1519_to_2047_bytes_lo;
 737         u32 tx_packets_1519_to_2047_bytes_hi;
 738         u32 tx_packets_2048_to_4095_bytes_lo;
 739         u32 tx_packets_2048_to_4095_bytes_hi;
 740         u32 tx_packets_4096_to_8191_bytes_lo;
 741         u32 tx_packets_4096_to_8191_bytes_hi;
 742         u32 tx_packets_8192_to_9216_bytes_lo;
 743         u32 tx_packets_8192_to_9216_bytes_hi;
 744         u32 tx_lso_packets_lo;
 745         u32 tx_lso_packets_hi;
 746         u32 rx_packets_lo;
 747         u32 rx_packets_hi;
 748         u32 rx_unicast_packets_lo;
 749         u32 rx_unicast_packets_hi;
 750         u32 rx_multicast_packets_lo;
 751         u32 rx_multicast_packets_hi;
 752         u32 rx_broadcast_packets_lo;
 753         u32 rx_broadcast_packets_hi;
 754         u32 rx_bytes_lo;
 755         u32 rx_bytes_hi;
 756         u32 rx_unicast_bytes_lo;
 757         u32 rx_unicast_bytes_hi;
 758         u32 rx_multicast_bytes_lo;
 759         u32 rx_multicast_bytes_hi;
 760         u32 rx_broadcast_bytes_lo;
 761         u32 rx_broadcast_bytes_hi;
 762         u32 rx_unknown_protos;
 763         u32 rsvd_69; /* Word 69 is reserved */
 764         u32 rx_discards_lo;
 765         u32 rx_discards_hi;
 766         u32 rx_errors_lo;
 767         u32 rx_errors_hi;
 768         u32 rx_crc_errors_lo;
 769         u32 rx_crc_errors_hi;
 770         u32 rx_alignment_errors_lo;
 771         u32 rx_alignment_errors_hi;
 772         u32 rx_symbol_errors_lo;
 773         u32 rx_symbol_errors_hi;
 774         u32 rx_pause_frames_lo;
 775         u32 rx_pause_frames_hi;
 776         u32 rx_pause_on_frames_lo;
 777         u32 rx_pause_on_frames_hi;
 778         u32 rx_pause_off_frames_lo;
 779         u32 rx_pause_off_frames_hi;
 780         u32 rx_frames_too_long_lo;
 781         u32 rx_frames_too_long_hi;
 782         u32 rx_internal_mac_errors_lo;
 783         u32 rx_internal_mac_errors_hi;
 784         u32 rx_undersize_packets;
 785         u32 rx_oversize_packets;
 786         u32 rx_fragment_packets;
 787         u32 rx_jabbers;
 788         u32 rx_control_frames_lo;
 789         u32 rx_control_frames_hi;
 790         u32 rx_control_frames_unknown_opcode_lo;
 791         u32 rx_control_frames_unknown_opcode_hi;
 792         u32 rx_in_range_errors;
 793         u32 rx_out_of_range_errors;
 794         u32 rx_address_match_errors;
 795         u32 rx_vlan_mismatch_errors;
 796         u32 rx_dropped_too_small;
 797         u32 rx_dropped_too_short;
 798         u32 rx_dropped_header_too_small;
 799         u32 rx_dropped_invalid_tcp_length;
 800         u32 rx_dropped_runt;
 801         u32 rx_ip_checksum_errors;
 802         u32 rx_tcp_checksum_errors;
 803         u32 rx_udp_checksum_errors;
 804         u32 rx_non_rss_packets;
 805         u32 rsvd_111;
 806         u32 rx_ipv4_packets_lo;
 807         u32 rx_ipv4_packets_hi;
 808         u32 rx_ipv6_packets_lo;
 809         u32 rx_ipv6_packets_hi;
 810         u32 rx_ipv4_bytes_lo;
 811         u32 rx_ipv4_bytes_hi;
 812         u32 rx_ipv6_bytes_lo;
 813         u32 rx_ipv6_bytes_hi;
 814         u32 rx_nic_packets_lo;
 815         u32 rx_nic_packets_hi;
 816         u32 rx_tcp_packets_lo;
 817         u32 rx_tcp_packets_hi;
 818         u32 rx_iscsi_packets_lo;
 819         u32 rx_iscsi_packets_hi;
 820         u32 rx_management_packets_lo;
 821         u32 rx_management_packets_hi;
 822         u32 rx_switched_unicast_packets_lo;
 823         u32 rx_switched_unicast_packets_hi;
 824         u32 rx_switched_multicast_packets_lo;
 825         u32 rx_switched_multicast_packets_hi;
 826         u32 rx_switched_broadcast_packets_lo;
 827         u32 rx_switched_broadcast_packets_hi;
 828         u32 num_forwards_lo;
 829         u32 num_forwards_hi;
 830         u32 rx_fifo_overflow;
 831         u32 rx_input_fifo_overflow;
 832         u32 rx_drops_too_many_frags_lo;
 833         u32 rx_drops_too_many_frags_hi;
 834         u32 rx_drops_invalid_queue;
 835         u32 rsvd_141;
 836         u32 rx_drops_mtu_lo;
 837         u32 rx_drops_mtu_hi;
 838         u32 rx_packets_64_bytes_lo;
 839         u32 rx_packets_64_bytes_hi;
 840         u32 rx_packets_65_to_127_bytes_lo;
 841         u32 rx_packets_65_to_127_bytes_hi;
 842         u32 rx_packets_128_to_255_bytes_lo;
 843         u32 rx_packets_128_to_255_bytes_hi;
 844         u32 rx_packets_256_to_511_bytes_lo;
 845         u32 rx_packets_256_to_511_bytes_hi;
 846         u32 rx_packets_512_to_1023_bytes_lo;
 847         u32 rx_packets_512_to_1023_bytes_hi;
 848         u32 rx_packets_1024_to_1518_bytes_lo;
 849         u32 rx_packets_1024_to_1518_bytes_hi;
 850         u32 rx_packets_1519_to_2047_bytes_lo;
 851         u32 rx_packets_1519_to_2047_bytes_hi;
 852         u32 rx_packets_2048_to_4095_bytes_lo;
 853         u32 rx_packets_2048_to_4095_bytes_hi;
 854         u32 rx_packets_4096_to_8191_bytes_lo;
 855         u32 rx_packets_4096_to_8191_bytes_hi;
 856         u32 rx_packets_8192_to_9216_bytes_lo;
 857         u32 rx_packets_8192_to_9216_bytes_hi;
 858 };
 859
 860 struct pport_stats_params {
 861         u16 pport_num;
 862         u8 rsvd;
 863         u8 reset_stats;
 864 };
 865
 866 struct lancer_cmd_req_pport_stats {
 867         struct be_cmd_req_hdr hdr;
 868         union {
 869                 struct pport_stats_params params;
 870                 u8 rsvd[sizeof(struct lancer_cmd_pport_stats)];
 871         } cmd_params;
 872 };
 873
 874 struct lancer_cmd_resp_pport_stats {
 875         struct be_cmd_resp_hdr hdr;
 876         struct lancer_cmd_pport_stats pport_stats;
 877 };
 878
 879 static inline  struct lancer_cmd_pport_stats*
 880         pport_stats_from_cmd(struct be_adapter *adapter)
 881 {
 882         struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
 883         return &cmd->pport_stats;
 884 }
 885
 886 struct be_cmd_req_get_cntl_addnl_attribs {
 887         struct be_cmd_req_hdr hdr;
 888         u8 rsvd[8];
 889 };
 890
 891 struct be_cmd_resp_get_cntl_addnl_attribs {
 892         struct be_cmd_resp_hdr hdr;
 893         u16 ipl_file_number;
 894         u8 ipl_file_version;
 895         u8 rsvd0;
 896         u8 on_die_temperature; /* in degrees centigrade*/
 897         u8 rsvd1[3];
 898 };
 899
 900 struct be_cmd_req_vlan_config {
 901         struct be_cmd_req_hdr hdr;
 902         u8 interface_id;
 903         u8 promiscuous;
 904         u8 untagged;
 905         u8 num_vlan;
 906         u16 normal_vlan[64];
 907 } __packed;
 908
 909 /******************** Multicast MAC Config *******************/
 910 #define BE_MAX_MC               64 /* set mcast promisc if > 64 */
 911 struct macaddr {
 912         u8 byte[ETH_ALEN];
 913 };
 914
 915 struct be_cmd_req_mcast_mac_config {
 916         struct be_cmd_req_hdr hdr;
 917         u16 num_mac;
 918         u8 promiscuous;
 919         u8 interface_id;
 920         struct macaddr mac[BE_MAX_MC];
 921 } __packed;
 922
 923 /******************* RX FILTER ******************************/
 924 struct be_cmd_req_rx_filter {
 925         struct be_cmd_req_hdr hdr;
 926         u32 global_flags_mask;
 927         u32 global_flags;
 928         u32 if_flags_mask;
 929         u32 if_flags;
 930         u32 if_id;
 931         u32 multicast_num;
 932         struct macaddr mac[BE_MAX_MC];
 933 };
 934
 935
 936 /******************** Link Status Query *******************/
 937 struct be_cmd_req_link_status {
 938         struct be_cmd_req_hdr hdr;
 939         u32 rsvd;
 940 };
 941
 942 enum {
 943         PHY_LINK_DUPLEX_NONE = 0x0,
 944         PHY_LINK_DUPLEX_HALF = 0x1,
 945         PHY_LINK_DUPLEX_FULL = 0x2
 946 };
 947
 948 enum {
 949         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 950         PHY_LINK_SPEED_10MBPS = 0x1,
 951         PHY_LINK_SPEED_100MBPS = 0x2,
 952         PHY_LINK_SPEED_1GBPS = 0x3,
 953         PHY_LINK_SPEED_10GBPS = 0x4
 954 };
 955
 956 struct be_cmd_resp_link_status {
 957         struct be_cmd_resp_hdr hdr;
 958         u8 physical_port;
 959         u8 mac_duplex;
 960         u8 mac_speed;
 961         u8 mac_fault;
 962         u8 mgmt_mac_duplex;
 963         u8 mgmt_mac_speed;
 964         u16 link_speed;
 965         u32 rsvd0;
 966 } __packed;
 967
 968 /******************** Port Identification ***************************/
 969 /*    Identifies the type of port attached to NIC     */
 970 struct be_cmd_req_port_type {
 971         struct be_cmd_req_hdr hdr;
 972         u32 page_num;
 973         u32 port;
 974 };
 975
 976 enum {
 977         TR_PAGE_A0 = 0xa0,
 978         TR_PAGE_A2 = 0xa2
 979 };
 980
 981 struct be_cmd_resp_port_type {
 982         struct be_cmd_resp_hdr hdr;
 983         u32 page_num;
 984         u32 port;
 985         struct data {
 986                 u8 identifier;
 987                 u8 identifier_ext;
 988                 u8 connector;
 989                 u8 transceiver[8];
 990                 u8 rsvd0[3];
 991                 u8 length_km;
 992                 u8 length_hm;
 993                 u8 length_om1;
 994                 u8 length_om2;
 995                 u8 length_cu;
 996                 u8 length_cu_m;
 997                 u8 vendor_name[16];
 998                 u8 rsvd;
 999                 u8 vendor_oui[3];
1000                 u8 vendor_pn[16];
1001                 u8 vendor_rev[4];
1002         } data;
1003 };
1004
1005 /******************** Get FW Version *******************/
1006 struct be_cmd_req_get_fw_version {
1007         struct be_cmd_req_hdr hdr;
1008         u8 rsvd0[FW_VER_LEN];
1009         u8 rsvd1[FW_VER_LEN];
1010 } __packed;
1011
1012 struct be_cmd_resp_get_fw_version {
1013         struct be_cmd_resp_hdr hdr;
1014         u8 firmware_version_string[FW_VER_LEN];
1015         u8 fw_on_flash_version_string[FW_VER_LEN];
1016 } __packed;
1017
1018 /******************** Set Flow Contrl *******************/
1019 struct be_cmd_req_set_flow_control {
1020         struct be_cmd_req_hdr hdr;
1021         u16 tx_flow_control;
1022         u16 rx_flow_control;
1023 } __packed;
1024
1025 /******************** Get Flow Contrl *******************/
1026 struct be_cmd_req_get_flow_control {
1027         struct be_cmd_req_hdr hdr;
1028         u32 rsvd;
1029 };
1030
1031 struct be_cmd_resp_get_flow_control {
1032         struct be_cmd_resp_hdr hdr;
1033         u16 tx_flow_control;
1034         u16 rx_flow_control;
1035 } __packed;
1036
1037 /******************** Modify EQ Delay *******************/
1038 struct be_cmd_req_modify_eq_delay {
1039         struct be_cmd_req_hdr hdr;
1040         u32 num_eq;
1041         struct {
1042                 u32 eq_id;
1043                 u32 phase;
1044                 u32 delay_multiplier;
1045         } delay[8];
1046 } __packed;
1047
1048 struct be_cmd_resp_modify_eq_delay {
1049         struct be_cmd_resp_hdr hdr;
1050         u32 rsvd0;
1051 } __packed;
1052
1053 /******************** Get FW Config *******************/
1054 #define BE_FUNCTION_CAPS_RSS                    0x2
1055 struct be_cmd_req_query_fw_cfg {
1056         struct be_cmd_req_hdr hdr;
1057         u32 rsvd[31];
1058 };
1059
1060 struct be_cmd_resp_query_fw_cfg {
1061         struct be_cmd_resp_hdr hdr;
1062         u32 be_config_number;
1063         u32 asic_revision;
1064         u32 phys_port;
1065         u32 function_mode;
1066         u32 rsvd[26];
1067         u32 function_caps;
1068 };
1069
1070 /******************** RSS Config *******************/
1071 /* RSS types */
1072 #define RSS_ENABLE_NONE                         0x0
1073 #define RSS_ENABLE_IPV4                         0x1
1074 #define RSS_ENABLE_TCP_IPV4                     0x2
1075 #define RSS_ENABLE_IPV6                         0x4
1076 #define RSS_ENABLE_TCP_IPV6                     0x8
1077
1078 struct be_cmd_req_rss_config {
1079         struct be_cmd_req_hdr hdr;
1080         u32 if_id;
1081         u16 enable_rss;
1082         u16 cpu_table_size_log2;
1083         u32 hash[10];
1084         u8 cpu_table[128];
1085         u8 flush;
1086         u8 rsvd0[3];
1087 };
1088
1089 /******************** Port Beacon ***************************/
1090
1091 #define BEACON_STATE_ENABLED            0x1
1092 #define BEACON_STATE_DISABLED           0x0
1093
1094 struct be_cmd_req_enable_disable_beacon {
1095         struct be_cmd_req_hdr hdr;
1096         u8  port_num;
1097         u8  beacon_state;
1098         u8  beacon_duration;
1099         u8  status_duration;
1100 } __packed;
1101
1102 struct be_cmd_resp_enable_disable_beacon {
1103         struct be_cmd_resp_hdr resp_hdr;
1104         u32 rsvd0;
1105 } __packed;
1106
1107 struct be_cmd_req_get_beacon_state {
1108         struct be_cmd_req_hdr hdr;
1109         u8  port_num;
1110         u8  rsvd0;
1111         u16 rsvd1;
1112 } __packed;
1113
1114 struct be_cmd_resp_get_beacon_state {
1115         struct be_cmd_resp_hdr resp_hdr;
1116         u8 beacon_state;
1117         u8 rsvd0[3];
1118 } __packed;
1119
1120 /****************** Firmware Flash ******************/
1121 struct flashrom_params {
1122         u32 op_code;
1123         u32 op_type;
1124         u32 data_buf_size;
1125         u32 offset;
1126         u8 data_buf[4];
1127 };
1128
1129 struct be_cmd_write_flashrom {
1130         struct be_cmd_req_hdr hdr;
1131         struct flashrom_params params;
1132 };
1133
1134 /************************ WOL *******************************/
1135 struct be_cmd_req_acpi_wol_magic_config{
1136         struct be_cmd_req_hdr hdr;
1137         u32 rsvd0[145];
1138         u8 magic_mac[6];
1139         u8 rsvd2[2];
1140 } __packed;
1141
1142 /********************** LoopBack test *********************/
1143 struct be_cmd_req_loopback_test {
1144         struct be_cmd_req_hdr hdr;
1145         u32 loopback_type;
1146         u32 num_pkts;
1147         u64 pattern;
1148         u32 src_port;
1149         u32 dest_port;
1150         u32 pkt_size;
1151 };
1152
1153 struct be_cmd_resp_loopback_test {
1154         struct be_cmd_resp_hdr resp_hdr;
1155         u32    status;
1156         u32    num_txfer;
1157         u32    num_rx;
1158         u32    miscomp_off;
1159         u32    ticks_compl;
1160 };
1161
1162 struct be_cmd_req_set_lmode {
1163         struct be_cmd_req_hdr hdr;
1164         u8 src_port;
1165         u8 dest_port;
1166         u8 loopback_type;
1167         u8 loopback_state;
1168 };
1169
1170 struct be_cmd_resp_set_lmode {
1171         struct be_cmd_resp_hdr resp_hdr;
1172         u8 rsvd0[4];
1173 };
1174
1175 /********************** DDR DMA test *********************/
1176 struct be_cmd_req_ddrdma_test {
1177         struct be_cmd_req_hdr hdr;
1178         u64 pattern;
1179         u32 byte_count;
1180         u32 rsvd0;
1181         u8  snd_buff[4096];
1182         u8  rsvd1[4096];
1183 };
1184
1185 struct be_cmd_resp_ddrdma_test {
1186         struct be_cmd_resp_hdr hdr;
1187         u64 pattern;
1188         u32 byte_cnt;
1189         u32 snd_err;
1190         u8  rsvd0[4096];
1191         u8  rcv_buff[4096];
1192 };
1193
1194 /*********************** SEEPROM Read ***********************/
1195
1196 #define BE_READ_SEEPROM_LEN 1024
1197 struct be_cmd_req_seeprom_read {
1198         struct be_cmd_req_hdr hdr;
1199         u8 rsvd0[BE_READ_SEEPROM_LEN];
1200 };
1201
1202 struct be_cmd_resp_seeprom_read {
1203         struct be_cmd_req_hdr hdr;
1204         u8 seeprom_data[BE_READ_SEEPROM_LEN];
1205 };
1206
1207 enum {
1208         PHY_TYPE_CX4_10GB = 0,
1209         PHY_TYPE_XFP_10GB,
1210         PHY_TYPE_SFP_1GB,
1211         PHY_TYPE_SFP_PLUS_10GB,
1212         PHY_TYPE_KR_10GB,
1213         PHY_TYPE_KX4_10GB,
1214         PHY_TYPE_BASET_10GB,
1215         PHY_TYPE_BASET_1GB,
1216         PHY_TYPE_DISABLED = 255
1217 };
1218
1219 struct be_cmd_req_get_phy_info {
1220         struct be_cmd_req_hdr hdr;
1221         u8 rsvd0[24];
1222 };
1223 struct be_cmd_resp_get_phy_info {
1224         struct be_cmd_req_hdr hdr;
1225         u16 phy_type;
1226         u16 interface_type;
1227         u32 misc_params;
1228         u32 future_use[4];
1229 };
1230
1231 /*********************** Set QOS ***********************/
1232
1233 #define BE_QOS_BITS_NIC                         1
1234
1235 struct be_cmd_req_set_qos {
1236         struct be_cmd_req_hdr hdr;
1237         u32 valid_bits;
1238         u32 max_bps_nic;
1239         u32 rsvd[7];
1240 };
1241
1242 struct be_cmd_resp_set_qos {
1243         struct be_cmd_resp_hdr hdr;
1244         u32 rsvd;
1245 };
1246
1247 /*********************** Controller Attributes ***********************/
1248 struct be_cmd_req_cntl_attribs {
1249         struct be_cmd_req_hdr hdr;
1250 };
1251
1252 struct be_cmd_resp_cntl_attribs {
1253         struct be_cmd_resp_hdr hdr;
1254         struct mgmt_controller_attrib attribs;
1255 };
1256
1257 /*********************** Set driver function ***********************/
1258 #define CAPABILITY_SW_TIMESTAMPS        2
1259 #define CAPABILITY_BE3_NATIVE_ERX_API   4
1260
1261 struct be_cmd_req_set_func_cap {
1262         struct be_cmd_req_hdr hdr;
1263         u32 valid_cap_flags;
1264         u32 cap_flags;
1265         u8 rsvd[212];
1266 };
1267
1268 struct be_cmd_resp_set_func_cap {
1269         struct be_cmd_resp_hdr hdr;
1270         u32 valid_cap_flags;
1271         u32 cap_flags;
1272         u8 rsvd[212];
1273 };
1274
1275 /*************** HW Stats Get v1 **********************************/
1276 #define BE_TXP_SW_SZ                    48
1277 struct be_port_rxf_stats_v1 {
1278         u32 rsvd0[12];
1279         u32 rx_crc_errors;
1280         u32 rx_alignment_symbol_errors;
1281         u32 rx_pause_frames;
1282         u32 rx_priority_pause_frames;
1283         u32 rx_control_frames;
1284         u32 rx_in_range_errors;
1285         u32 rx_out_range_errors;
1286         u32 rx_frame_too_long;
1287         u32 rx_address_match_errors;
1288         u32 rx_dropped_too_small;
1289         u32 rx_dropped_too_short;
1290         u32 rx_dropped_header_too_small;
1291         u32 rx_dropped_tcp_length;
1292         u32 rx_dropped_runt;
1293         u32 rsvd1[10];
1294         u32 rx_ip_checksum_errs;
1295         u32 rx_tcp_checksum_errs;
1296         u32 rx_udp_checksum_errs;
1297         u32 rsvd2[7];
1298         u32 rx_switched_unicast_packets;
1299         u32 rx_switched_multicast_packets;
1300         u32 rx_switched_broadcast_packets;
1301         u32 rsvd3[3];
1302         u32 tx_pauseframes;
1303         u32 tx_priority_pauseframes;
1304         u32 tx_controlframes;
1305         u32 rsvd4[10];
1306         u32 rxpp_fifo_overflow_drop;
1307         u32 rx_input_fifo_overflow_drop;
1308         u32 pmem_fifo_overflow_drop;
1309         u32 jabber_events;
1310         u32 rsvd5[3];
1311 };
1312
1313
1314 struct be_rxf_stats_v1 {
1315         struct be_port_rxf_stats_v1 port[4];
1316         u32 rsvd0[2];
1317         u32 rx_drops_no_pbuf;
1318         u32 rx_drops_no_txpb;
1319         u32 rx_drops_no_erx_descr;
1320         u32 rx_drops_no_tpre_descr;
1321         u32 rsvd1[6];
1322         u32 rx_drops_too_many_frags;
1323         u32 rx_drops_invalid_ring;
1324         u32 forwarded_packets;
1325         u32 rx_drops_mtu;
1326         u32 rsvd2[14];
1327 };
1328
1329 struct be_erx_stats_v1 {
1330         u32 rx_drops_no_fragments[68];     /* dwordS 0 to 67*/
1331         u32 rsvd[4];
1332 };
1333
1334 struct be_hw_stats_v1 {
1335         struct be_rxf_stats_v1 rxf;
1336         u32 rsvd0[BE_TXP_SW_SZ];
1337         struct be_erx_stats_v1 erx;
1338         struct be_pmem_stats pmem;
1339         u32 rsvd1[3];
1340 };
1341
1342 struct be_cmd_req_get_stats_v1 {
1343         struct be_cmd_req_hdr hdr;
1344         u8 rsvd[sizeof(struct be_hw_stats_v1)];
1345 };
1346
1347 struct be_cmd_resp_get_stats_v1 {
1348         struct be_cmd_resp_hdr hdr;
1349         struct be_hw_stats_v1 hw_stats;
1350 };
1351
1352 static inline void *
1353 hw_stats_from_cmd(struct be_adapter *adapter)
1354 {
1355         if (adapter->generation == BE_GEN3) {
1356                 struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va;
1357
1358                 return &cmd->hw_stats;
1359         } else {
1360                 struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va;
1361
1362                 return &cmd->hw_stats;
1363         }
1364 }
1365
1366 static inline void *be_port_rxf_stats_from_cmd(struct be_adapter *adapter)
1367 {
1368         if (adapter->generation == BE_GEN3) {
1369                 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1370                 struct be_rxf_stats_v1 *rxf_stats = &hw_stats->rxf;
1371
1372                 return &rxf_stats->port[adapter->port_num];
1373         } else {
1374                 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1375                 struct be_rxf_stats_v0 *rxf_stats = &hw_stats->rxf;
1376
1377                 return &rxf_stats->port[adapter->port_num];
1378         }
1379 }
1380
1381 static inline void *be_rxf_stats_from_cmd(struct be_adapter *adapter)
1382 {
1383         if (adapter->generation == BE_GEN3) {
1384                 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1385
1386                 return &hw_stats->rxf;
1387         } else {
1388                 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1389
1390                 return &hw_stats->rxf;
1391         }
1392 }
1393
1394 static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter)
1395 {
1396         if (adapter->generation == BE_GEN3) {
1397                 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1398
1399                 return &hw_stats->erx;
1400         } else {
1401                 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1402
1403                 return &hw_stats->erx;
1404         }
1405 }
1406
1407 static inline void *be_pmem_stats_from_cmd(struct be_adapter *adapter)
1408 {
1409         if (adapter->generation == BE_GEN3) {
1410                 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1411
1412                 return &hw_stats->pmem;
1413         } else {
1414                 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1415
1416                 return &hw_stats->pmem;
1417         }
1418 }
1419
1420 extern int be_pci_fnum_get(struct be_adapter *adapter);
1421 extern int be_cmd_POST(struct be_adapter *adapter);
1422 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1423                         u8 type, bool permanent, u32 if_handle);
1424 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1425                         u32 if_id, u32 *pmac_id, u32 domain);
1426 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1427                         u32 pmac_id, u32 domain);
1428 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1429                         u32 en_flags, u8 *mac, bool pmac_invalid,
1430                         u32 *if_handle, u32 *pmac_id, u32 domain);
1431 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle,
1432                         u32 domain);
1433 extern int be_cmd_eq_create(struct be_adapter *adapter,
1434                         struct be_queue_info *eq, int eq_delay);
1435 extern int be_cmd_cq_create(struct be_adapter *adapter,
1436                         struct be_queue_info *cq, struct be_queue_info *eq,
1437                         bool sol_evts, bool no_delay,
1438                         int num_cqe_dma_coalesce);
1439 extern int be_cmd_mccq_create(struct be_adapter *adapter,
1440                         struct be_queue_info *mccq,
1441                         struct be_queue_info *cq);
1442 extern int be_cmd_txq_create(struct be_adapter *adapter,
1443                         struct be_queue_info *txq,
1444                         struct be_queue_info *cq);
1445 extern int be_cmd_rxq_create(struct be_adapter *adapter,
1446                         struct be_queue_info *rxq, u16 cq_id,
1447                         u16 frag_size, u16 max_frame_size, u32 if_id,
1448                         u32 rss, u8 *rss_id);
1449 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1450                         int type);
1451 extern int be_cmd_link_status_query(struct be_adapter *adapter,
1452                         bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom);
1453 extern int be_cmd_reset(struct be_adapter *adapter);
1454 extern int be_cmd_get_stats(struct be_adapter *adapter,
1455                         struct be_dma_mem *nonemb_cmd);
1456 extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1457                         struct be_dma_mem *nonemb_cmd);
1458 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
1459
1460 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1461 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1462                         u16 *vtag_array, u32 num, bool untagged,
1463                         bool promiscuous);
1464 extern int be_cmd_promiscuous_config(struct be_adapter *adapter, bool en);
1465 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1466                         struct net_device *netdev, struct be_dma_mem *mem);
1467 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1468                         u32 tx_fc, u32 rx_fc);
1469 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1470                         u32 *tx_fc, u32 *rx_fc);
1471 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
1472                         u32 *port_num, u32 *function_mode, u32 *function_caps);
1473 extern int be_cmd_reset_function(struct be_adapter *adapter);
1474 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1475                         u16 table_size);
1476 extern int be_process_mcc(struct be_adapter *adapter, int *status);
1477 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1478                         u8 port_num, u8 beacon, u8 status, u8 state);
1479 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1480                         u8 port_num, u32 *state);
1481 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1482                         struct be_dma_mem *cmd, u32 flash_oper,
1483                         u32 flash_opcode, u32 buf_size);
1484 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1485                                 int offset);
1486 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1487                                 struct be_dma_mem *nonemb_cmd);
1488 extern int be_cmd_fw_init(struct be_adapter *adapter);
1489 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1490 extern void be_async_mcc_enable(struct be_adapter *adapter);
1491 extern void be_async_mcc_disable(struct be_adapter *adapter);
1492 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1493                                 u32 loopback_type, u32 pkt_size,
1494                                 u32 num_pkts, u64 pattern);
1495 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1496                         u32 byte_cnt, struct be_dma_mem *cmd);
1497 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1498                                 struct be_dma_mem *nonemb_cmd);
1499 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1500                                 u8 loopback_type, u8 enable);
1501 extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1502                 struct be_dma_mem *cmd);
1503 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1504 extern void be_detect_dump_ue(struct be_adapter *adapter);
1505 extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
1506 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
1507 extern int be_cmd_check_native_mode(struct be_adapter *adapter);
1508 extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
1509 extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
1510