Pileus Git - ~andy/linux/blob - drivers/net/b44.c

   1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
   2  *
   3  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
   5  * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
   6  * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
   7  * Copyright (C) 2006 Broadcom Corporation.
   8  * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
   9  *
  10  * Distribute under GPL.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/types.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/mii.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/pci.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/ssb/ssb.h>
  28
  29 #include <asm/uaccess.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33
  34 #include "b44.h"
  35
  36 #define DRV_MODULE_NAME         "b44"
  37 #define PFX DRV_MODULE_NAME     ": "
  38 #define DRV_MODULE_VERSION      "2.0"
  39
  40 #define B44_DEF_MSG_ENABLE        \
  41         (NETIF_MSG_DRV          | \
  42          NETIF_MSG_PROBE        | \
  43          NETIF_MSG_LINK         | \
  44          NETIF_MSG_TIMER        | \
  45          NETIF_MSG_IFDOWN       | \
  46          NETIF_MSG_IFUP         | \
  47          NETIF_MSG_RX_ERR       | \
  48          NETIF_MSG_TX_ERR)
  49
  50 /* length of time before we decide the hardware is borked,
  51  * and dev->tx_timeout() should be called to fix the problem
  52  */
  53 #define B44_TX_TIMEOUT                  (5 * HZ)
  54
  55 /* hardware minimum and maximum for a single frame's data payload */
  56 #define B44_MIN_MTU                     60
  57 #define B44_MAX_MTU                     1500
  58
  59 #define B44_RX_RING_SIZE                512
  60 #define B44_DEF_RX_RING_PENDING         200
  61 #define B44_RX_RING_BYTES       (sizeof(struct dma_desc) * \
  62                                  B44_RX_RING_SIZE)
  63 #define B44_TX_RING_SIZE                512
  64 #define B44_DEF_TX_RING_PENDING         (B44_TX_RING_SIZE - 1)
  65 #define B44_TX_RING_BYTES       (sizeof(struct dma_desc) * \
  66                                  B44_TX_RING_SIZE)
  67
  68 #define TX_RING_GAP(BP) \
  69         (B44_TX_RING_SIZE - (BP)->tx_pending)
  70 #define TX_BUFFS_AVAIL(BP)                                              \
  71         (((BP)->tx_cons <= (BP)->tx_prod) ?                             \
  72           (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod :            \
  73           (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
  74 #define NEXT_TX(N)              (((N) + 1) & (B44_TX_RING_SIZE - 1))
  75
  76 #define RX_PKT_OFFSET           (RX_HEADER_LEN + 2)
  77 #define RX_PKT_BUF_SZ           (1536 + RX_PKT_OFFSET)
  78
  79 /* minimum number of free TX descriptors required to wake up TX process */
  80 #define B44_TX_WAKEUP_THRESH            (B44_TX_RING_SIZE / 4)
  81
  82 /* b44 internal pattern match filter info */
  83 #define B44_PATTERN_BASE        0x400
  84 #define B44_PATTERN_SIZE        0x80
  85 #define B44_PMASK_BASE          0x600
  86 #define B44_PMASK_SIZE          0x10
  87 #define B44_MAX_PATTERNS        16
  88 #define B44_ETHIPV6UDP_HLEN     62
  89 #define B44_ETHIPV4UDP_HLEN     42
  90
  91 static char version[] __devinitdata =
  92         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
  93
  94 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
  95 MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
  96 MODULE_LICENSE("GPL");
  97 MODULE_VERSION(DRV_MODULE_VERSION);
  98
  99 static int b44_debug = -1;      /* -1 == use B44_DEF_MSG_ENABLE as value */
 100 module_param(b44_debug, int, 0);
 101 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
 102
 103
 104 #ifdef CONFIG_B44_PCI
 105 static const struct pci_device_id b44_pci_tbl[] = {
 106         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
 107         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
 108         { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
 109         { 0 } /* terminate list with empty entry */
 110 };
 111 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
 112
 113 static struct pci_driver b44_pci_driver = {
 114         .name           = DRV_MODULE_NAME,
 115         .id_table       = b44_pci_tbl,
 116 };
 117 #endif /* CONFIG_B44_PCI */
 118
 119 static const struct ssb_device_id b44_ssb_tbl[] = {
 120         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
 121         SSB_DEVTABLE_END
 122 };
 123 MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
 124
 125 static void b44_halt(struct b44 *);
 126 static void b44_init_rings(struct b44 *);
 127
 128 #define B44_FULL_RESET          1
 129 #define B44_FULL_RESET_SKIP_PHY 2
 130 #define B44_PARTIAL_RESET       3
 131 #define B44_CHIP_RESET_FULL     4
 132 #define B44_CHIP_RESET_PARTIAL  5
 133
 134 static void b44_init_hw(struct b44 *, int);
 135
 136 static int dma_desc_align_mask;
 137 static int dma_desc_sync_size;
 138 static int instance;
 139
 140 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
 141 #define _B44(x...)      # x,
 142 B44_STAT_REG_DECLARE
 143 #undef _B44
 144 };
 145
 146 static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
 147                                                 dma_addr_t dma_base,
 148                                                 unsigned long offset,
 149                                                 enum dma_data_direction dir)
 150 {
 151         ssb_dma_sync_single_range_for_device(sdev, dma_base,
 152                                              offset & dma_desc_align_mask,
 153                                              dma_desc_sync_size, dir);
 154 }
 155
 156 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
 157                                              dma_addr_t dma_base,
 158                                              unsigned long offset,
 159                                              enum dma_data_direction dir)
 160 {
 161         ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
 162                                           offset & dma_desc_align_mask,
 163                                           dma_desc_sync_size, dir);
 164 }
 165
 166 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
 167 {
 168         return ssb_read32(bp->sdev, reg);
 169 }
 170
 171 static inline void bw32(const struct b44 *bp,
 172                         unsigned long reg, unsigned long val)
 173 {
 174         ssb_write32(bp->sdev, reg, val);
 175 }
 176
 177 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
 178                         u32 bit, unsigned long timeout, const int clear)
 179 {
 180         unsigned long i;
 181
 182         for (i = 0; i < timeout; i++) {
 183                 u32 val = br32(bp, reg);
 184
 185                 if (clear && !(val & bit))
 186                         break;
 187                 if (!clear && (val & bit))
 188                         break;
 189                 udelay(10);
 190         }
 191         if (i == timeout) {
 192                 printk(KERN_ERR PFX "%s: BUG!  Timeout waiting for bit %08x of register "
 193                        "%lx to %s.\n",
 194                        bp->dev->name,
 195                        bit, reg,
 196                        (clear ? "clear" : "set"));
 197                 return -ENODEV;
 198         }
 199         return 0;
 200 }
 201
 202 static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
 203 {
 204         u32 val;
 205
 206         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
 207                             (index << CAM_CTRL_INDEX_SHIFT)));
 208
 209         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 210
 211         val = br32(bp, B44_CAM_DATA_LO);
 212
 213         data[2] = (val >> 24) & 0xFF;
 214         data[3] = (val >> 16) & 0xFF;
 215         data[4] = (val >> 8) & 0xFF;
 216         data[5] = (val >> 0) & 0xFF;
 217
 218         val = br32(bp, B44_CAM_DATA_HI);
 219
 220         data[0] = (val >> 8) & 0xFF;
 221         data[1] = (val >> 0) & 0xFF;
 222 }
 223
 224 static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 225 {
 226         u32 val;
 227
 228         val  = ((u32) data[2]) << 24;
 229         val |= ((u32) data[3]) << 16;
 230         val |= ((u32) data[4]) <<  8;
 231         val |= ((u32) data[5]) <<  0;
 232         bw32(bp, B44_CAM_DATA_LO, val);
 233         val = (CAM_DATA_HI_VALID |
 234                (((u32) data[0]) << 8) |
 235                (((u32) data[1]) << 0));
 236         bw32(bp, B44_CAM_DATA_HI, val);
 237         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
 238                             (index << CAM_CTRL_INDEX_SHIFT)));
 239         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 240 }
 241
 242 static inline void __b44_disable_ints(struct b44 *bp)
 243 {
 244         bw32(bp, B44_IMASK, 0);
 245 }
 246
 247 static void b44_disable_ints(struct b44 *bp)
 248 {
 249         __b44_disable_ints(bp);
 250
 251         /* Flush posted writes. */
 252         br32(bp, B44_IMASK);
 253 }
 254
 255 static void b44_enable_ints(struct b44 *bp)
 256 {
 257         bw32(bp, B44_IMASK, bp->imask);
 258 }
 259
 260 static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
 261 {
 262         int err;
 263
 264         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 265         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 266                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 267                              (phy_addr << MDIO_DATA_PMD_SHIFT) |
 268                              (reg << MDIO_DATA_RA_SHIFT) |
 269                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 270         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 271         *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
 272
 273         return err;
 274 }
 275
 276 static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
 277 {
 278         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 279         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 280                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 281                              (phy_addr << MDIO_DATA_PMD_SHIFT) |
 282                              (reg << MDIO_DATA_RA_SHIFT) |
 283                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 284                              (val & MDIO_DATA_DATA)));
 285         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 286 }
 287
 288 static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
 289 {
 290         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 291                 return 0;
 292
 293         return __b44_readphy(bp, bp->phy_addr, reg, val);
 294 }
 295
 296 static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
 297 {
 298         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 299                 return 0;
 300
 301         return __b44_writephy(bp, bp->phy_addr, reg, val);
 302 }
 303
 304 /* miilib interface */
 305 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
 306 {
 307         u32 val;
 308         struct b44 *bp = netdev_priv(dev);
 309         int rc = __b44_readphy(bp, phy_id, location, &val);
 310         if (rc)
 311                 return 0xffffffff;
 312         return val;
 313 }
 314
 315 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
 316                          int val)
 317 {
 318         struct b44 *bp = netdev_priv(dev);
 319         __b44_writephy(bp, phy_id, location, val);
 320 }
 321
 322 static int b44_phy_reset(struct b44 *bp)
 323 {
 324         u32 val;
 325         int err;
 326
 327         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 328                 return 0;
 329         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 330         if (err)
 331                 return err;
 332         udelay(100);
 333         err = b44_readphy(bp, MII_BMCR, &val);
 334         if (!err) {
 335                 if (val & BMCR_RESET) {
 336                         printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
 337                                bp->dev->name);
 338                         err = -ENODEV;
 339                 }
 340         }
 341
 342         return 0;
 343 }
 344
 345 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
 346 {
 347         u32 val;
 348
 349         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
 350         bp->flags |= pause_flags;
 351
 352         val = br32(bp, B44_RXCONFIG);
 353         if (pause_flags & B44_FLAG_RX_PAUSE)
 354                 val |= RXCONFIG_FLOW;
 355         else
 356                 val &= ~RXCONFIG_FLOW;
 357         bw32(bp, B44_RXCONFIG, val);
 358
 359         val = br32(bp, B44_MAC_FLOW);
 360         if (pause_flags & B44_FLAG_TX_PAUSE)
 361                 val |= (MAC_FLOW_PAUSE_ENAB |
 362                         (0xc0 & MAC_FLOW_RX_HI_WATER));
 363         else
 364                 val &= ~MAC_FLOW_PAUSE_ENAB;
 365         bw32(bp, B44_MAC_FLOW, val);
 366 }
 367
 368 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
 369 {
 370         u32 pause_enab = 0;
 371
 372         /* The driver supports only rx pause by default because
 373            the b44 mac tx pause mechanism generates excessive
 374            pause frames.
 375            Use ethtool to turn on b44 tx pause if necessary.
 376          */
 377         if ((local & ADVERTISE_PAUSE_CAP) &&
 378             (local & ADVERTISE_PAUSE_ASYM)){
 379                 if ((remote & LPA_PAUSE_ASYM) &&
 380                     !(remote & LPA_PAUSE_CAP))
 381                         pause_enab |= B44_FLAG_RX_PAUSE;
 382         }
 383
 384         __b44_set_flow_ctrl(bp, pause_enab);
 385 }
 386
 387 #ifdef SSB_DRIVER_MIPS
 388 extern char *nvram_get(char *name);
 389 static void b44_wap54g10_workaround(struct b44 *bp)
 390 {
 391         const char *str;
 392         u32 val;
 393         int err;
 394
 395         /*
 396          * workaround for bad hardware design in Linksys WAP54G v1.0
 397          * see https://dev.openwrt.org/ticket/146
 398          * check and reset bit "isolate"
 399          */
 400         str = nvram_get("boardnum");
 401         if (!str)
 402                 return;
 403         if (simple_strtoul(str, NULL, 0) == 2) {
 404                 err = __b44_readphy(bp, 0, MII_BMCR, &val);
 405                 if (err)
 406                         goto error;
 407                 if (!(val & BMCR_ISOLATE))
 408                         return;
 409                 val &= ~BMCR_ISOLATE;
 410                 err = __b44_writephy(bp, 0, MII_BMCR, val);
 411                 if (err)
 412                         goto error;
 413         }
 414         return;
 415 error:
 416         printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
 417 }
 418 #else
 419 static inline void b44_wap54g10_workaround(struct b44 *bp)
 420 {
 421 }
 422 #endif
 423
 424 static int b44_setup_phy(struct b44 *bp)
 425 {
 426         u32 val;
 427         int err;
 428
 429         b44_wap54g10_workaround(bp);
 430
 431         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 432                 return 0;
 433         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 434                 goto out;
 435         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 436                                 val & MII_ALEDCTRL_ALLMSK)) != 0)
 437                 goto out;
 438         if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
 439                 goto out;
 440         if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
 441                                 val | MII_TLEDCTRL_ENABLE)) != 0)
 442                 goto out;
 443
 444         if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
 445                 u32 adv = ADVERTISE_CSMA;
 446
 447                 if (bp->flags & B44_FLAG_ADV_10HALF)
 448                         adv |= ADVERTISE_10HALF;
 449                 if (bp->flags & B44_FLAG_ADV_10FULL)
 450                         adv |= ADVERTISE_10FULL;
 451                 if (bp->flags & B44_FLAG_ADV_100HALF)
 452                         adv |= ADVERTISE_100HALF;
 453                 if (bp->flags & B44_FLAG_ADV_100FULL)
 454                         adv |= ADVERTISE_100FULL;
 455
 456                 if (bp->flags & B44_FLAG_PAUSE_AUTO)
 457                         adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 458
 459                 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
 460                         goto out;
 461                 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
 462                                                        BMCR_ANRESTART))) != 0)
 463                         goto out;
 464         } else {
 465                 u32 bmcr;
 466
 467                 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
 468                         goto out;
 469                 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
 470                 if (bp->flags & B44_FLAG_100_BASE_T)
 471                         bmcr |= BMCR_SPEED100;
 472                 if (bp->flags & B44_FLAG_FULL_DUPLEX)
 473                         bmcr |= BMCR_FULLDPLX;
 474                 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
 475                         goto out;
 476
 477                 /* Since we will not be negotiating there is no safe way
 478                  * to determine if the link partner supports flow control
 479                  * or not.  So just disable it completely in this case.
 480                  */
 481                 b44_set_flow_ctrl(bp, 0, 0);
 482         }
 483
 484 out:
 485         return err;
 486 }
 487
 488 static void b44_stats_update(struct b44 *bp)
 489 {
 490         unsigned long reg;
 491         u32 *val;
 492
 493         val = &bp->hw_stats.tx_good_octets;
 494         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
 495                 *val++ += br32(bp, reg);
 496         }
 497
 498         /* Pad */
 499         reg += 8*4UL;
 500
 501         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
 502                 *val++ += br32(bp, reg);
 503         }
 504 }
 505
 506 static void b44_link_report(struct b44 *bp)
 507 {
 508         if (!netif_carrier_ok(bp->dev)) {
 509                 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
 510         } else {
 511                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
 512                        bp->dev->name,
 513                        (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
 514                        (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
 515
 516                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
 517                        "%s for RX.\n",
 518                        bp->dev->name,
 519                        (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
 520                        (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
 521         }
 522 }
 523
 524 static void b44_check_phy(struct b44 *bp)
 525 {
 526         u32 bmsr, aux;
 527
 528         if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
 529                 bp->flags |= B44_FLAG_100_BASE_T;
 530                 bp->flags |= B44_FLAG_FULL_DUPLEX;
 531                 if (!netif_carrier_ok(bp->dev)) {
 532                         u32 val = br32(bp, B44_TX_CTRL);
 533                         val |= TX_CTRL_DUPLEX;
 534                         bw32(bp, B44_TX_CTRL, val);
 535                         netif_carrier_on(bp->dev);
 536                         b44_link_report(bp);
 537                 }
 538                 return;
 539         }
 540
 541         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 542             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 543             (bmsr != 0xffff)) {
 544                 if (aux & MII_AUXCTRL_SPEED)
 545                         bp->flags |= B44_FLAG_100_BASE_T;
 546                 else
 547                         bp->flags &= ~B44_FLAG_100_BASE_T;
 548                 if (aux & MII_AUXCTRL_DUPLEX)
 549                         bp->flags |= B44_FLAG_FULL_DUPLEX;
 550                 else
 551                         bp->flags &= ~B44_FLAG_FULL_DUPLEX;
 552
 553                 if (!netif_carrier_ok(bp->dev) &&
 554                     (bmsr & BMSR_LSTATUS)) {
 555                         u32 val = br32(bp, B44_TX_CTRL);
 556                         u32 local_adv, remote_adv;
 557
 558                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
 559                                 val |= TX_CTRL_DUPLEX;
 560                         else
 561                                 val &= ~TX_CTRL_DUPLEX;
 562                         bw32(bp, B44_TX_CTRL, val);
 563
 564                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
 565                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
 566                             !b44_readphy(bp, MII_LPA, &remote_adv))
 567                                 b44_set_flow_ctrl(bp, local_adv, remote_adv);
 568
 569                         /* Link now up */
 570                         netif_carrier_on(bp->dev);
 571                         b44_link_report(bp);
 572                 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
 573                         /* Link now down */
 574                         netif_carrier_off(bp->dev);
 575                         b44_link_report(bp);
 576                 }
 577
 578                 if (bmsr & BMSR_RFAULT)
 579                         printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
 580                                bp->dev->name);
 581                 if (bmsr & BMSR_JCD)
 582                         printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
 583                                bp->dev->name);
 584         }
 585 }
 586
 587 static void b44_timer(unsigned long __opaque)
 588 {
 589         struct b44 *bp = (struct b44 *) __opaque;
 590
 591         spin_lock_irq(&bp->lock);
 592
 593         b44_check_phy(bp);
 594
 595         b44_stats_update(bp);
 596
 597         spin_unlock_irq(&bp->lock);
 598
 599         mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
 600 }
 601
 602 static void b44_tx(struct b44 *bp)
 603 {
 604         u32 cur, cons;
 605
 606         cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 607         cur /= sizeof(struct dma_desc);
 608
 609         /* XXX needs updating when NETIF_F_SG is supported */
 610         for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
 611                 struct ring_info *rp = &bp->tx_buffers[cons];
 612                 struct sk_buff *skb = rp->skb;
 613
 614                 BUG_ON(skb == NULL);
 615
 616                 ssb_dma_unmap_single(bp->sdev,
 617                                      rp->mapping,
 618                                      skb->len,
 619                                      DMA_TO_DEVICE);
 620                 rp->skb = NULL;
 621                 dev_kfree_skb_irq(skb);
 622         }
 623
 624         bp->tx_cons = cons;
 625         if (netif_queue_stopped(bp->dev) &&
 626             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
 627                 netif_wake_queue(bp->dev);
 628
 629         bw32(bp, B44_GPTIMER, 0);
 630 }
 631
 632 /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 633  * before the DMA address you give it.  So we allocate 30 more bytes
 634  * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
 635  * point the chip at 30 bytes past where the rx_header will go.
 636  */
 637 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 638 {
 639         struct dma_desc *dp;
 640         struct ring_info *src_map, *map;
 641         struct rx_header *rh;
 642         struct sk_buff *skb;
 643         dma_addr_t mapping;
 644         int dest_idx;
 645         u32 ctrl;
 646
 647         src_map = NULL;
 648         if (src_idx >= 0)
 649                 src_map = &bp->rx_buffers[src_idx];
 650         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 651         map = &bp->rx_buffers[dest_idx];
 652         skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
 653         if (skb == NULL)
 654                 return -ENOMEM;
 655
 656         mapping = ssb_dma_map_single(bp->sdev, skb->data,
 657                                      RX_PKT_BUF_SZ,
 658                                      DMA_FROM_DEVICE);
 659
 660         /* Hardware bug work-around, the chip is unable to do PCI DMA
 661            to/from anything above 1GB :-( */
 662         if (ssb_dma_mapping_error(bp->sdev, mapping) ||
 663                 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
 664                 /* Sigh... */
 665                 if (!ssb_dma_mapping_error(bp->sdev, mapping))
 666                         ssb_dma_unmap_single(bp->sdev, mapping,
 667                                              RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
 668                 dev_kfree_skb_any(skb);
 669                 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
 670                 if (skb == NULL)
 671                         return -ENOMEM;
 672                 mapping = ssb_dma_map_single(bp->sdev, skb->data,
 673                                              RX_PKT_BUF_SZ,
 674                                              DMA_FROM_DEVICE);
 675                 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
 676                         mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
 677                         if (!ssb_dma_mapping_error(bp->sdev, mapping))
 678                                 ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
 679                         dev_kfree_skb_any(skb);
 680                         return -ENOMEM;
 681                 }
 682                 bp->force_copybreak = 1;
 683         }
 684
 685         rh = (struct rx_header *) skb->data;
 686
 687         rh->len = 0;
 688         rh->flags = 0;
 689
 690         map->skb = skb;
 691         map->mapping = mapping;
 692
 693         if (src_map != NULL)
 694                 src_map->skb = NULL;
 695
 696         ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
 697         if (dest_idx == (B44_RX_RING_SIZE - 1))
 698                 ctrl |= DESC_CTRL_EOT;
 699
 700         dp = &bp->rx_ring[dest_idx];
 701         dp->ctrl = cpu_to_le32(ctrl);
 702         dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
 703
 704         if (bp->flags & B44_FLAG_RX_RING_HACK)
 705                 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
 706                                             dest_idx * sizeof(*dp),
 707                                             DMA_BIDIRECTIONAL);
 708
 709         return RX_PKT_BUF_SZ;
 710 }
 711
 712 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 713 {
 714         struct dma_desc *src_desc, *dest_desc;
 715         struct ring_info *src_map, *dest_map;
 716         struct rx_header *rh;
 717         int dest_idx;
 718         __le32 ctrl;
 719
 720         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 721         dest_desc = &bp->rx_ring[dest_idx];
 722         dest_map = &bp->rx_buffers[dest_idx];
 723         src_desc = &bp->rx_ring[src_idx];
 724         src_map = &bp->rx_buffers[src_idx];
 725
 726         dest_map->skb = src_map->skb;
 727         rh = (struct rx_header *) src_map->skb->data;
 728         rh->len = 0;
 729         rh->flags = 0;
 730         dest_map->mapping = src_map->mapping;
 731
 732         if (bp->flags & B44_FLAG_RX_RING_HACK)
 733                 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
 734                                          src_idx * sizeof(*src_desc),
 735                                          DMA_BIDIRECTIONAL);
 736
 737         ctrl = src_desc->ctrl;
 738         if (dest_idx == (B44_RX_RING_SIZE - 1))
 739                 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
 740         else
 741                 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
 742
 743         dest_desc->ctrl = ctrl;
 744         dest_desc->addr = src_desc->addr;
 745
 746         src_map->skb = NULL;
 747
 748         if (bp->flags & B44_FLAG_RX_RING_HACK)
 749                 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
 750                                              dest_idx * sizeof(*dest_desc),
 751                                              DMA_BIDIRECTIONAL);
 752
 753         ssb_dma_sync_single_for_device(bp->sdev, dest_map->mapping,
 754                                        RX_PKT_BUF_SZ,
 755                                        DMA_FROM_DEVICE);
 756 }
 757
 758 static int b44_rx(struct b44 *bp, int budget)
 759 {
 760         int received;
 761         u32 cons, prod;
 762
 763         received = 0;
 764         prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 765         prod /= sizeof(struct dma_desc);
 766         cons = bp->rx_cons;
 767
 768         while (cons != prod && budget > 0) {
 769                 struct ring_info *rp = &bp->rx_buffers[cons];
 770                 struct sk_buff *skb = rp->skb;
 771                 dma_addr_t map = rp->mapping;
 772                 struct rx_header *rh;
 773                 u16 len;
 774
 775                 ssb_dma_sync_single_for_cpu(bp->sdev, map,
 776                                             RX_PKT_BUF_SZ,
 777                                             DMA_FROM_DEVICE);
 778                 rh = (struct rx_header *) skb->data;
 779                 len = le16_to_cpu(rh->len);
 780                 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
 781                     (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
 782                 drop_it:
 783                         b44_recycle_rx(bp, cons, bp->rx_prod);
 784                 drop_it_no_recycle:
 785                         bp->dev->stats.rx_dropped++;
 786                         goto next_pkt;
 787                 }
 788
 789                 if (len == 0) {
 790                         int i = 0;
 791
 792                         do {
 793                                 udelay(2);
 794                                 barrier();
 795                                 len = le16_to_cpu(rh->len);
 796                         } while (len == 0 && i++ < 5);
 797                         if (len == 0)
 798                                 goto drop_it;
 799                 }
 800
 801                 /* Omit CRC. */
 802                 len -= 4;
 803
 804                 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
 805                         int skb_size;
 806                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
 807                         if (skb_size < 0)
 808                                 goto drop_it;
 809                         ssb_dma_unmap_single(bp->sdev, map,
 810                                              skb_size, DMA_FROM_DEVICE);
 811                         /* Leave out rx_header */
 812                         skb_put(skb, len + RX_PKT_OFFSET);
 813                         skb_pull(skb, RX_PKT_OFFSET);
 814                 } else {
 815                         struct sk_buff *copy_skb;
 816
 817                         b44_recycle_rx(bp, cons, bp->rx_prod);
 818                         copy_skb = dev_alloc_skb(len + 2);
 819                         if (copy_skb == NULL)
 820                                 goto drop_it_no_recycle;
 821
 822                         skb_reserve(copy_skb, 2);
 823                         skb_put(copy_skb, len);
 824                         /* DMA sync done above, copy just the actual packet */
 825                         skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
 826                                                          copy_skb->data, len);
 827                         skb = copy_skb;
 828                 }
 829                 skb->ip_summed = CHECKSUM_NONE;
 830                 skb->protocol = eth_type_trans(skb, bp->dev);
 831                 netif_receive_skb(skb);
 832                 received++;
 833                 budget--;
 834         next_pkt:
 835                 bp->rx_prod = (bp->rx_prod + 1) &
 836                         (B44_RX_RING_SIZE - 1);
 837                 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
 838         }
 839
 840         bp->rx_cons = cons;
 841         bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 842
 843         return received;
 844 }
 845
 846 static int b44_poll(struct napi_struct *napi, int budget)
 847 {
 848         struct b44 *bp = container_of(napi, struct b44, napi);
 849         int work_done;
 850
 851         spin_lock_irq(&bp->lock);
 852
 853         if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
 854                 /* spin_lock(&bp->tx_lock); */
 855                 b44_tx(bp);
 856                 /* spin_unlock(&bp->tx_lock); */
 857         }
 858         spin_unlock_irq(&bp->lock);
 859
 860         work_done = 0;
 861         if (bp->istat & ISTAT_RX)
 862                 work_done += b44_rx(bp, budget);
 863
 864         if (bp->istat & ISTAT_ERRORS) {
 865                 unsigned long flags;
 866
 867                 spin_lock_irqsave(&bp->lock, flags);
 868                 b44_halt(bp);
 869                 b44_init_rings(bp);
 870                 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
 871                 netif_wake_queue(bp->dev);
 872                 spin_unlock_irqrestore(&bp->lock, flags);
 873                 work_done = 0;
 874         }
 875
 876         if (work_done < budget) {
 877                 napi_complete(napi);
 878                 b44_enable_ints(bp);
 879         }
 880
 881         return work_done;
 882 }
 883
 884 static irqreturn_t b44_interrupt(int irq, void *dev_id)
 885 {
 886         struct net_device *dev = dev_id;
 887         struct b44 *bp = netdev_priv(dev);
 888         u32 istat, imask;
 889         int handled = 0;
 890
 891         spin_lock(&bp->lock);
 892
 893         istat = br32(bp, B44_ISTAT);
 894         imask = br32(bp, B44_IMASK);
 895
 896         /* The interrupt mask register controls which interrupt bits
 897          * will actually raise an interrupt to the CPU when set by hw/firmware,
 898          * but doesn't mask off the bits.
 899          */
 900         istat &= imask;
 901         if (istat) {
 902                 handled = 1;
 903
 904                 if (unlikely(!netif_running(dev))) {
 905                         printk(KERN_INFO "%s: late interrupt.\n", dev->name);
 906                         goto irq_ack;
 907                 }
 908
 909                 if (napi_schedule_prep(&bp->napi)) {
 910                         /* NOTE: These writes are posted by the readback of
 911                          *       the ISTAT register below.
 912                          */
 913                         bp->istat = istat;
 914                         __b44_disable_ints(bp);
 915                         __napi_schedule(&bp->napi);
 916                 } else {
 917                         printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
 918                                dev->name);
 919                 }
 920
 921 irq_ack:
 922                 bw32(bp, B44_ISTAT, istat);
 923                 br32(bp, B44_ISTAT);
 924         }
 925         spin_unlock(&bp->lock);
 926         return IRQ_RETVAL(handled);
 927 }
 928
 929 static void b44_tx_timeout(struct net_device *dev)
 930 {
 931         struct b44 *bp = netdev_priv(dev);
 932
 933         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
 934                dev->name);
 935
 936         spin_lock_irq(&bp->lock);
 937
 938         b44_halt(bp);
 939         b44_init_rings(bp);
 940         b44_init_hw(bp, B44_FULL_RESET);
 941
 942         spin_unlock_irq(&bp->lock);
 943
 944         b44_enable_ints(bp);
 945
 946         netif_wake_queue(dev);
 947 }
 948
 949 static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
 950 {
 951         struct b44 *bp = netdev_priv(dev);
 952         int rc = NETDEV_TX_OK;
 953         dma_addr_t mapping;
 954         u32 len, entry, ctrl;
 955         unsigned long flags;
 956
 957         len = skb->len;
 958         spin_lock_irqsave(&bp->lock, flags);
 959
 960         /* This is a hard error, log it. */
 961         if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
 962                 netif_stop_queue(dev);
 963                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
 964                        dev->name);
 965                 goto err_out;
 966         }
 967
 968         mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
 969         if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
 970                 struct sk_buff *bounce_skb;
 971
 972                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
 973                 if (!ssb_dma_mapping_error(bp->sdev, mapping))
 974                         ssb_dma_unmap_single(bp->sdev, mapping, len,
 975                                              DMA_TO_DEVICE);
 976
 977                 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
 978                 if (!bounce_skb)
 979                         goto err_out;
 980
 981                 mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
 982                                              len, DMA_TO_DEVICE);
 983                 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
 984                         if (!ssb_dma_mapping_error(bp->sdev, mapping))
 985                                 ssb_dma_unmap_single(bp->sdev, mapping,
 986                                                      len, DMA_TO_DEVICE);
 987                         dev_kfree_skb_any(bounce_skb);
 988                         goto err_out;
 989                 }
 990
 991                 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
 992                 dev_kfree_skb_any(skb);
 993                 skb = bounce_skb;
 994         }
 995
 996         entry = bp->tx_prod;
 997         bp->tx_buffers[entry].skb = skb;
 998         bp->tx_buffers[entry].mapping = mapping;
 999
1000         ctrl  = (len & DESC_CTRL_LEN);
1001         ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1002         if (entry == (B44_TX_RING_SIZE - 1))
1003                 ctrl |= DESC_CTRL_EOT;
1004
1005         bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1006         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1007
1008         if (bp->flags & B44_FLAG_TX_RING_HACK)
1009                 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1010                                             entry * sizeof(bp->tx_ring[0]),
1011                                             DMA_TO_DEVICE);
1012
1013         entry = NEXT_TX(entry);
1014
1015         bp->tx_prod = entry;
1016
1017         wmb();
1018
1019         bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1020         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1021                 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1022         if (bp->flags & B44_FLAG_REORDER_BUG)
1023                 br32(bp, B44_DMATX_PTR);
1024
1025         if (TX_BUFFS_AVAIL(bp) < 1)
1026                 netif_stop_queue(dev);
1027
1028         dev->trans_start = jiffies;
1029
1030 out_unlock:
1031         spin_unlock_irqrestore(&bp->lock, flags);
1032
1033         return rc;
1034
1035 err_out:
1036         rc = NETDEV_TX_BUSY;
1037         goto out_unlock;
1038 }
1039
1040 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1041 {
1042         struct b44 *bp = netdev_priv(dev);
1043
1044         if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1045                 return -EINVAL;
1046
1047         if (!netif_running(dev)) {
1048                 /* We'll just catch it later when the
1049                  * device is up'd.
1050                  */
1051                 dev->mtu = new_mtu;
1052                 return 0;
1053         }
1054
1055         spin_lock_irq(&bp->lock);
1056         b44_halt(bp);
1057         dev->mtu = new_mtu;
1058         b44_init_rings(bp);
1059         b44_init_hw(bp, B44_FULL_RESET);
1060         spin_unlock_irq(&bp->lock);
1061
1062         b44_enable_ints(bp);
1063
1064         return 0;
1065 }
1066
1067 /* Free up pending packets in all rx/tx rings.
1068  *
1069  * The chip has been shut down and the driver detached from
1070  * the networking, so no interrupts or new tx packets will
1071  * end up in the driver.  bp->lock is not held and we are not
1072  * in an interrupt context and thus may sleep.
1073  */
1074 static void b44_free_rings(struct b44 *bp)
1075 {
1076         struct ring_info *rp;
1077         int i;
1078
1079         for (i = 0; i < B44_RX_RING_SIZE; i++) {
1080                 rp = &bp->rx_buffers[i];
1081
1082                 if (rp->skb == NULL)
1083                         continue;
1084                 ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
1085                                      DMA_FROM_DEVICE);
1086                 dev_kfree_skb_any(rp->skb);
1087                 rp->skb = NULL;
1088         }
1089
1090         /* XXX needs changes once NETIF_F_SG is set... */
1091         for (i = 0; i < B44_TX_RING_SIZE; i++) {
1092                 rp = &bp->tx_buffers[i];
1093
1094                 if (rp->skb == NULL)
1095                         continue;
1096                 ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
1097                                      DMA_TO_DEVICE);
1098                 dev_kfree_skb_any(rp->skb);
1099                 rp->skb = NULL;
1100         }
1101 }
1102
1103 /* Initialize tx/rx rings for packet processing.
1104  *
1105  * The chip has been shut down and the driver detached from
1106  * the networking, so no interrupts or new tx packets will
1107  * end up in the driver.
1108  */
1109 static void b44_init_rings(struct b44 *bp)
1110 {
1111         int i;
1112
1113         b44_free_rings(bp);
1114
1115         memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1116         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1117
1118         if (bp->flags & B44_FLAG_RX_RING_HACK)
1119                 ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
1120                                                DMA_TABLE_BYTES,
1121                                                DMA_BIDIRECTIONAL);
1122
1123         if (bp->flags & B44_FLAG_TX_RING_HACK)
1124                 ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
1125                                                DMA_TABLE_BYTES,
1126                                                DMA_TO_DEVICE);
1127
1128         for (i = 0; i < bp->rx_pending; i++) {
1129                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1130                         break;
1131         }
1132 }
1133
1134 /*
1135  * Must not be invoked with interrupt sources disabled and
1136  * the hardware shutdown down.
1137  */
1138 static void b44_free_consistent(struct b44 *bp)
1139 {
1140         kfree(bp->rx_buffers);
1141         bp->rx_buffers = NULL;
1142         kfree(bp->tx_buffers);
1143         bp->tx_buffers = NULL;
1144         if (bp->rx_ring) {
1145                 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1146                         ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
1147                                              DMA_TABLE_BYTES,
1148                                              DMA_BIDIRECTIONAL);
1149                         kfree(bp->rx_ring);
1150                 } else
1151                         ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1152                                                 bp->rx_ring, bp->rx_ring_dma,
1153                                                 GFP_KERNEL);
1154                 bp->rx_ring = NULL;
1155                 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1156         }
1157         if (bp->tx_ring) {
1158                 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1159                         ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
1160                                              DMA_TABLE_BYTES,
1161                                              DMA_TO_DEVICE);
1162                         kfree(bp->tx_ring);
1163                 } else
1164                         ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1165                                                 bp->tx_ring, bp->tx_ring_dma,
1166                                                 GFP_KERNEL);
1167                 bp->tx_ring = NULL;
1168                 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1169         }
1170 }
1171
1172 /*
1173  * Must not be invoked with interrupt sources disabled and
1174  * the hardware shutdown down.  Can sleep.
1175  */
1176 static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1177 {
1178         int size;
1179
1180         size  = B44_RX_RING_SIZE * sizeof(struct ring_info);
1181         bp->rx_buffers = kzalloc(size, gfp);
1182         if (!bp->rx_buffers)
1183                 goto out_err;
1184
1185         size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1186         bp->tx_buffers = kzalloc(size, gfp);
1187         if (!bp->tx_buffers)
1188                 goto out_err;
1189
1190         size = DMA_TABLE_BYTES;
1191         bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
1192         if (!bp->rx_ring) {
1193                 /* Allocation may have failed due to pci_alloc_consistent
1194                    insisting on use of GFP_DMA, which is more restrictive
1195                    than necessary...  */
1196                 struct dma_desc *rx_ring;
1197                 dma_addr_t rx_ring_dma;
1198
1199                 rx_ring = kzalloc(size, gfp);
1200                 if (!rx_ring)
1201                         goto out_err;
1202
1203                 rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
1204                                                  DMA_TABLE_BYTES,
1205                                                  DMA_BIDIRECTIONAL);
1206
1207                 if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
1208                         rx_ring_dma + size > DMA_BIT_MASK(30)) {
1209                         kfree(rx_ring);
1210                         goto out_err;
1211                 }
1212
1213                 bp->rx_ring = rx_ring;
1214                 bp->rx_ring_dma = rx_ring_dma;
1215                 bp->flags |= B44_FLAG_RX_RING_HACK;
1216         }
1217
1218         bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
1219         if (!bp->tx_ring) {
1220                 /* Allocation may have failed due to ssb_dma_alloc_consistent
1221                    insisting on use of GFP_DMA, which is more restrictive
1222                    than necessary...  */
1223                 struct dma_desc *tx_ring;
1224                 dma_addr_t tx_ring_dma;
1225
1226                 tx_ring = kzalloc(size, gfp);
1227                 if (!tx_ring)
1228                         goto out_err;
1229
1230                 tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
1231                                             DMA_TABLE_BYTES,
1232                                             DMA_TO_DEVICE);
1233
1234                 if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
1235                         tx_ring_dma + size > DMA_BIT_MASK(30)) {
1236                         kfree(tx_ring);
1237                         goto out_err;
1238                 }
1239
1240                 bp->tx_ring = tx_ring;
1241                 bp->tx_ring_dma = tx_ring_dma;
1242                 bp->flags |= B44_FLAG_TX_RING_HACK;
1243         }
1244
1245         return 0;
1246
1247 out_err:
1248         b44_free_consistent(bp);
1249         return -ENOMEM;
1250 }
1251
1252 /* bp->lock is held. */
1253 static void b44_clear_stats(struct b44 *bp)
1254 {
1255         unsigned long reg;
1256
1257         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1258         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1259                 br32(bp, reg);
1260         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1261                 br32(bp, reg);
1262 }
1263
1264 /* bp->lock is held. */
1265 static void b44_chip_reset(struct b44 *bp, int reset_kind)
1266 {
1267         struct ssb_device *sdev = bp->sdev;
1268         bool was_enabled;
1269
1270         was_enabled = ssb_device_is_enabled(bp->sdev);
1271
1272         ssb_device_enable(bp->sdev, 0);
1273         ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1274
1275         if (was_enabled) {
1276                 bw32(bp, B44_RCV_LAZY, 0);
1277                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1278                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1279                 bw32(bp, B44_DMATX_CTRL, 0);
1280                 bp->tx_prod = bp->tx_cons = 0;
1281                 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1282                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1283                                      100, 0);
1284                 }
1285                 bw32(bp, B44_DMARX_CTRL, 0);
1286                 bp->rx_prod = bp->rx_cons = 0;
1287         }
1288
1289         b44_clear_stats(bp);
1290
1291         /*
1292          * Don't enable PHY if we are doing a partial reset
1293          * we are probably going to power down
1294          */
1295         if (reset_kind == B44_CHIP_RESET_PARTIAL)
1296                 return;
1297
1298         switch (sdev->bus->bustype) {
1299         case SSB_BUSTYPE_SSB:
1300                 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1301                      (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
1302                                         B44_MDC_RATIO)
1303                      & MDIO_CTRL_MAXF_MASK)));
1304                 break;
1305         case SSB_BUSTYPE_PCI:
1306         case SSB_BUSTYPE_PCMCIA:
1307                 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1308                      (0x0d & MDIO_CTRL_MAXF_MASK)));
1309                 break;
1310         }
1311
1312         br32(bp, B44_MDIO_CTRL);
1313
1314         if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1315                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1316                 br32(bp, B44_ENET_CTRL);
1317                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1318         } else {
1319                 u32 val = br32(bp, B44_DEVCTRL);
1320
1321                 if (val & DEVCTRL_EPR) {
1322                         bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1323                         br32(bp, B44_DEVCTRL);
1324                         udelay(100);
1325                 }
1326                 bp->flags |= B44_FLAG_INTERNAL_PHY;
1327         }
1328 }
1329
1330 /* bp->lock is held. */
1331 static void b44_halt(struct b44 *bp)
1332 {
1333         b44_disable_ints(bp);
1334         /* reset PHY */
1335         b44_phy_reset(bp);
1336         /* power down PHY */
1337         printk(KERN_INFO PFX "%s: powering down PHY\n", bp->dev->name);
1338         bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1339         /* now reset the chip, but without enabling the MAC&PHY
1340          * part of it. This has to be done _after_ we shut down the PHY */
1341         b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1342 }
1343
1344 /* bp->lock is held. */
1345 static void __b44_set_mac_addr(struct b44 *bp)
1346 {
1347         bw32(bp, B44_CAM_CTRL, 0);
1348         if (!(bp->dev->flags & IFF_PROMISC)) {
1349                 u32 val;
1350
1351                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1352                 val = br32(bp, B44_CAM_CTRL);
1353                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1354         }
1355 }
1356
1357 static int b44_set_mac_addr(struct net_device *dev, void *p)
1358 {
1359         struct b44 *bp = netdev_priv(dev);
1360         struct sockaddr *addr = p;
1361         u32 val;
1362
1363         if (netif_running(dev))
1364                 return -EBUSY;
1365
1366         if (!is_valid_ether_addr(addr->sa_data))
1367                 return -EINVAL;
1368
1369         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1370
1371         spin_lock_irq(&bp->lock);
1372
1373         val = br32(bp, B44_RXCONFIG);
1374         if (!(val & RXCONFIG_CAM_ABSENT))
1375                 __b44_set_mac_addr(bp);
1376
1377         spin_unlock_irq(&bp->lock);
1378
1379         return 0;
1380 }
1381
1382 /* Called at device open time to get the chip ready for
1383  * packet processing.  Invoked with bp->lock held.
1384  */
1385 static void __b44_set_rx_mode(struct net_device *);
1386 static void b44_init_hw(struct b44 *bp, int reset_kind)
1387 {
1388         u32 val;
1389
1390         b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1391         if (reset_kind == B44_FULL_RESET) {
1392                 b44_phy_reset(bp);
1393                 b44_setup_phy(bp);
1394         }
1395
1396         /* Enable CRC32, set proper LED modes and power on PHY */
1397         bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1398         bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1399
1400         /* This sets the MAC address too.  */
1401         __b44_set_rx_mode(bp->dev);
1402
1403         /* MTU + eth header + possible VLAN tag + struct rx_header */
1404         bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1405         bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1406
1407         bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1408         if (reset_kind == B44_PARTIAL_RESET) {
1409                 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1410                                       (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1411         } else {
1412                 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1413                 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1414                 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1415                                       (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1416                 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1417
1418                 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1419                 bp->rx_prod = bp->rx_pending;
1420
1421                 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1422         }
1423
1424         val = br32(bp, B44_ENET_CTRL);
1425         bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1426 }
1427
1428 static int b44_open(struct net_device *dev)
1429 {
1430         struct b44 *bp = netdev_priv(dev);
1431         int err;
1432
1433         err = b44_alloc_consistent(bp, GFP_KERNEL);
1434         if (err)
1435                 goto out;
1436
1437         napi_enable(&bp->napi);
1438
1439         b44_init_rings(bp);
1440         b44_init_hw(bp, B44_FULL_RESET);
1441
1442         b44_check_phy(bp);
1443
1444         err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1445         if (unlikely(err < 0)) {
1446                 napi_disable(&bp->napi);
1447                 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1448                 b44_free_rings(bp);
1449                 b44_free_consistent(bp);
1450                 goto out;
1451         }
1452
1453         init_timer(&bp->timer);
1454         bp->timer.expires = jiffies + HZ;
1455         bp->timer.data = (unsigned long) bp;
1456         bp->timer.function = b44_timer;
1457         add_timer(&bp->timer);
1458
1459         b44_enable_ints(bp);
1460         netif_start_queue(dev);
1461 out:
1462         return err;
1463 }
1464
1465 #ifdef CONFIG_NET_POLL_CONTROLLER
1466 /*
1467  * Polling receive - used by netconsole and other diagnostic tools
1468  * to allow network i/o with interrupts disabled.
1469  */
1470 static void b44_poll_controller(struct net_device *dev)
1471 {
1472         disable_irq(dev->irq);
1473         b44_interrupt(dev->irq, dev);
1474         enable_irq(dev->irq);
1475 }
1476 #endif
1477
1478 static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1479 {
1480         u32 i;
1481         u32 *pattern = (u32 *) pp;
1482
1483         for (i = 0; i < bytes; i += sizeof(u32)) {
1484                 bw32(bp, B44_FILT_ADDR, table_offset + i);
1485                 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1486         }
1487 }
1488
1489 static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1490 {
1491         int magicsync = 6;
1492         int k, j, len = offset;
1493         int ethaddr_bytes = ETH_ALEN;
1494
1495         memset(ppattern + offset, 0xff, magicsync);
1496         for (j = 0; j < magicsync; j++)
1497                 set_bit(len++, (unsigned long *) pmask);
1498
1499         for (j = 0; j < B44_MAX_PATTERNS; j++) {
1500                 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1501                         ethaddr_bytes = ETH_ALEN;
1502                 else
1503                         ethaddr_bytes = B44_PATTERN_SIZE - len;
1504                 if (ethaddr_bytes <=0)
1505                         break;
1506                 for (k = 0; k< ethaddr_bytes; k++) {
1507                         ppattern[offset + magicsync +
1508                                 (j * ETH_ALEN) + k] = macaddr[k];
1509                         len++;
1510                         set_bit(len, (unsigned long *) pmask);
1511                 }
1512         }
1513         return len - 1;
1514 }
1515
1516 /* Setup magic packet patterns in the b44 WOL
1517  * pattern matching filter.
1518  */
1519 static void b44_setup_pseudo_magicp(struct b44 *bp)
1520 {
1521
1522         u32 val;
1523         int plen0, plen1, plen2;
1524         u8 *pwol_pattern;
1525         u8 pwol_mask[B44_PMASK_SIZE];
1526
1527         pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1528         if (!pwol_pattern) {
1529                 printk(KERN_ERR PFX "Memory not available for WOL\n");
1530                 return;
1531         }
1532
1533         /* Ipv4 magic packet pattern - pattern 0.*/
1534         memset(pwol_mask, 0, B44_PMASK_SIZE);
1535         plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1536                                   B44_ETHIPV4UDP_HLEN);
1537
1538         bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1539         bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1540
1541         /* Raw ethernet II magic packet pattern - pattern 1 */
1542         memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1543         memset(pwol_mask, 0, B44_PMASK_SIZE);
1544         plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1545                                   ETH_HLEN);
1546
1547         bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1548                        B44_PATTERN_BASE + B44_PATTERN_SIZE);
1549         bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1550                        B44_PMASK_BASE + B44_PMASK_SIZE);
1551
1552         /* Ipv6 magic packet pattern - pattern 2 */
1553         memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1554         memset(pwol_mask, 0, B44_PMASK_SIZE);
1555         plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1556                                   B44_ETHIPV6UDP_HLEN);
1557
1558         bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1559                        B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1560         bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1561                        B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1562
1563         kfree(pwol_pattern);
1564
1565         /* set these pattern's lengths: one less than each real length */
1566         val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1567         bw32(bp, B44_WKUP_LEN, val);
1568
1569         /* enable wakeup pattern matching */
1570         val = br32(bp, B44_DEVCTRL);
1571         bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1572
1573 }
1574
1575 #ifdef CONFIG_B44_PCI
1576 static void b44_setup_wol_pci(struct b44 *bp)
1577 {
1578         u16 val;
1579
1580         if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1581                 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1582                 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1583                 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1584         }
1585 }
1586 #else
1587 static inline void b44_setup_wol_pci(struct b44 *bp) { }
1588 #endif /* CONFIG_B44_PCI */
1589
1590 static void b44_setup_wol(struct b44 *bp)
1591 {
1592         u32 val;
1593
1594         bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1595
1596         if (bp->flags & B44_FLAG_B0_ANDLATER) {
1597
1598                 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1599
1600                 val = bp->dev->dev_addr[2] << 24 |
1601                         bp->dev->dev_addr[3] << 16 |
1602                         bp->dev->dev_addr[4] << 8 |
1603                         bp->dev->dev_addr[5];
1604                 bw32(bp, B44_ADDR_LO, val);
1605
1606                 val = bp->dev->dev_addr[0] << 8 |
1607                         bp->dev->dev_addr[1];
1608                 bw32(bp, B44_ADDR_HI, val);
1609
1610                 val = br32(bp, B44_DEVCTRL);
1611                 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1612
1613         } else {
1614                 b44_setup_pseudo_magicp(bp);
1615         }
1616         b44_setup_wol_pci(bp);
1617 }
1618
1619 static int b44_close(struct net_device *dev)
1620 {
1621         struct b44 *bp = netdev_priv(dev);
1622
1623         netif_stop_queue(dev);
1624
1625         napi_disable(&bp->napi);
1626
1627         del_timer_sync(&bp->timer);
1628
1629         spin_lock_irq(&bp->lock);
1630
1631         b44_halt(bp);
1632         b44_free_rings(bp);
1633         netif_carrier_off(dev);
1634
1635         spin_unlock_irq(&bp->lock);
1636
1637         free_irq(dev->irq, dev);
1638
1639         if (bp->flags & B44_FLAG_WOL_ENABLE) {
1640                 b44_init_hw(bp, B44_PARTIAL_RESET);
1641                 b44_setup_wol(bp);
1642         }
1643
1644         b44_free_consistent(bp);
1645
1646         return 0;
1647 }
1648
1649 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1650 {
1651         struct b44 *bp = netdev_priv(dev);
1652         struct net_device_stats *nstat = &dev->stats;
1653         struct b44_hw_stats *hwstat = &bp->hw_stats;
1654
1655         /* Convert HW stats into netdevice stats. */
1656         nstat->rx_packets = hwstat->rx_pkts;
1657         nstat->tx_packets = hwstat->tx_pkts;
1658         nstat->rx_bytes   = hwstat->rx_octets;
1659         nstat->tx_bytes   = hwstat->tx_octets;
1660         nstat->tx_errors  = (hwstat->tx_jabber_pkts +
1661                              hwstat->tx_oversize_pkts +
1662                              hwstat->tx_underruns +
1663                              hwstat->tx_excessive_cols +
1664                              hwstat->tx_late_cols);
1665         nstat->multicast  = hwstat->tx_multicast_pkts;
1666         nstat->collisions = hwstat->tx_total_cols;
1667
1668         nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1669                                    hwstat->rx_undersize);
1670         nstat->rx_over_errors   = hwstat->rx_missed_pkts;
1671         nstat->rx_frame_errors  = hwstat->rx_align_errs;
1672         nstat->rx_crc_errors    = hwstat->rx_crc_errs;
1673         nstat->rx_errors        = (hwstat->rx_jabber_pkts +
1674                                    hwstat->rx_oversize_pkts +
1675                                    hwstat->rx_missed_pkts +
1676                                    hwstat->rx_crc_align_errs +
1677                                    hwstat->rx_undersize +
1678                                    hwstat->rx_crc_errs +
1679                                    hwstat->rx_align_errs +
1680                                    hwstat->rx_symbol_errs);
1681
1682         nstat->tx_aborted_errors = hwstat->tx_underruns;
1683 #if 0
1684         /* Carrier lost counter seems to be broken for some devices */
1685         nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1686 #endif
1687
1688         return nstat;
1689 }
1690
1691 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1692 {
1693         struct dev_mc_list *mclist;
1694         int i, num_ents;
1695
1696         num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1697         mclist = dev->mc_list;
1698         for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1699                 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1700         }
1701         return i+1;
1702 }
1703
1704 static void __b44_set_rx_mode(struct net_device *dev)
1705 {
1706         struct b44 *bp = netdev_priv(dev);
1707         u32 val;
1708
1709         val = br32(bp, B44_RXCONFIG);
1710         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1711         if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1712                 val |= RXCONFIG_PROMISC;
1713                 bw32(bp, B44_RXCONFIG, val);
1714         } else {
1715                 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1716                 int i = 1;
1717
1718                 __b44_set_mac_addr(bp);
1719
1720                 if ((dev->flags & IFF_ALLMULTI) ||
1721                     (dev->mc_count > B44_MCAST_TABLE_SIZE))
1722                         val |= RXCONFIG_ALLMULTI;
1723                 else
1724                         i = __b44_load_mcast(bp, dev);
1725
1726                 for (; i < 64; i++)
1727                         __b44_cam_write(bp, zero, i);
1728
1729                 bw32(bp, B44_RXCONFIG, val);
1730                 val = br32(bp, B44_CAM_CTRL);
1731                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1732         }
1733 }
1734
1735 static void b44_set_rx_mode(struct net_device *dev)
1736 {
1737         struct b44 *bp = netdev_priv(dev);
1738
1739         spin_lock_irq(&bp->lock);
1740         __b44_set_rx_mode(dev);
1741         spin_unlock_irq(&bp->lock);
1742 }
1743
1744 static u32 b44_get_msglevel(struct net_device *dev)
1745 {
1746         struct b44 *bp = netdev_priv(dev);
1747         return bp->msg_enable;
1748 }
1749
1750 static void b44_set_msglevel(struct net_device *dev, u32 value)
1751 {
1752         struct b44 *bp = netdev_priv(dev);
1753         bp->msg_enable = value;
1754 }
1755
1756 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1757 {
1758         struct b44 *bp = netdev_priv(dev);
1759         struct ssb_bus *bus = bp->sdev->bus;
1760
1761         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1762         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1763         switch (bus->bustype) {
1764         case SSB_BUSTYPE_PCI:
1765                 strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1766                 break;
1767         case SSB_BUSTYPE_PCMCIA:
1768         case SSB_BUSTYPE_SSB:
1769                 strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
1770                 break;
1771         }
1772 }
1773
1774 static int b44_nway_reset(struct net_device *dev)
1775 {
1776         struct b44 *bp = netdev_priv(dev);
1777         u32 bmcr;
1778         int r;
1779
1780         spin_lock_irq(&bp->lock);
1781         b44_readphy(bp, MII_BMCR, &bmcr);
1782         b44_readphy(bp, MII_BMCR, &bmcr);
1783         r = -EINVAL;
1784         if (bmcr & BMCR_ANENABLE) {
1785                 b44_writephy(bp, MII_BMCR,
1786                              bmcr | BMCR_ANRESTART);
1787                 r = 0;
1788         }
1789         spin_unlock_irq(&bp->lock);
1790
1791         return r;
1792 }
1793
1794 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1795 {
1796         struct b44 *bp = netdev_priv(dev);
1797
1798         cmd->supported = (SUPPORTED_Autoneg);
1799         cmd->supported |= (SUPPORTED_100baseT_Half |
1800                           SUPPORTED_100baseT_Full |
1801                           SUPPORTED_10baseT_Half |
1802                           SUPPORTED_10baseT_Full |
1803                           SUPPORTED_MII);
1804
1805         cmd->advertising = 0;
1806         if (bp->flags & B44_FLAG_ADV_10HALF)
1807                 cmd->advertising |= ADVERTISED_10baseT_Half;
1808         if (bp->flags & B44_FLAG_ADV_10FULL)
1809                 cmd->advertising |= ADVERTISED_10baseT_Full;
1810         if (bp->flags & B44_FLAG_ADV_100HALF)
1811                 cmd->advertising |= ADVERTISED_100baseT_Half;
1812         if (bp->flags & B44_FLAG_ADV_100FULL)
1813                 cmd->advertising |= ADVERTISED_100baseT_Full;
1814         cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1815         cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1816                 SPEED_100 : SPEED_10;
1817         cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1818                 DUPLEX_FULL : DUPLEX_HALF;
1819         cmd->port = 0;
1820         cmd->phy_address = bp->phy_addr;
1821         cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1822                 XCVR_INTERNAL : XCVR_EXTERNAL;
1823         cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1824                 AUTONEG_DISABLE : AUTONEG_ENABLE;
1825         if (cmd->autoneg == AUTONEG_ENABLE)
1826                 cmd->advertising |= ADVERTISED_Autoneg;
1827         if (!netif_running(dev)){
1828                 cmd->speed = 0;
1829                 cmd->duplex = 0xff;
1830         }
1831         cmd->maxtxpkt = 0;
1832         cmd->maxrxpkt = 0;
1833         return 0;
1834 }
1835
1836 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1837 {
1838         struct b44 *bp = netdev_priv(dev);
1839
1840         /* We do not support gigabit. */
1841         if (cmd->autoneg == AUTONEG_ENABLE) {
1842                 if (cmd->advertising &
1843                     (ADVERTISED_1000baseT_Half |
1844                      ADVERTISED_1000baseT_Full))
1845                         return -EINVAL;
1846         } else if ((cmd->speed != SPEED_100 &&
1847                     cmd->speed != SPEED_10) ||
1848                    (cmd->duplex != DUPLEX_HALF &&
1849                     cmd->duplex != DUPLEX_FULL)) {
1850                         return -EINVAL;
1851         }
1852
1853         spin_lock_irq(&bp->lock);
1854
1855         if (cmd->autoneg == AUTONEG_ENABLE) {
1856                 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1857                                B44_FLAG_100_BASE_T |
1858                                B44_FLAG_FULL_DUPLEX |
1859                                B44_FLAG_ADV_10HALF |
1860                                B44_FLAG_ADV_10FULL |
1861                                B44_FLAG_ADV_100HALF |
1862                                B44_FLAG_ADV_100FULL);
1863                 if (cmd->advertising == 0) {
1864                         bp->flags |= (B44_FLAG_ADV_10HALF |
1865                                       B44_FLAG_ADV_10FULL |
1866                                       B44_FLAG_ADV_100HALF |
1867                                       B44_FLAG_ADV_100FULL);
1868                 } else {
1869                         if (cmd->advertising & ADVERTISED_10baseT_Half)
1870                                 bp->flags |= B44_FLAG_ADV_10HALF;
1871                         if (cmd->advertising & ADVERTISED_10baseT_Full)
1872                                 bp->flags |= B44_FLAG_ADV_10FULL;
1873                         if (cmd->advertising & ADVERTISED_100baseT_Half)
1874                                 bp->flags |= B44_FLAG_ADV_100HALF;
1875                         if (cmd->advertising & ADVERTISED_100baseT_Full)
1876                                 bp->flags |= B44_FLAG_ADV_100FULL;
1877                 }
1878         } else {
1879                 bp->flags |= B44_FLAG_FORCE_LINK;
1880                 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1881                 if (cmd->speed == SPEED_100)
1882                         bp->flags |= B44_FLAG_100_BASE_T;
1883                 if (cmd->duplex == DUPLEX_FULL)
1884                         bp->flags |= B44_FLAG_FULL_DUPLEX;
1885         }
1886
1887         if (netif_running(dev))
1888                 b44_setup_phy(bp);
1889
1890         spin_unlock_irq(&bp->lock);
1891
1892         return 0;
1893 }
1894
1895 static void b44_get_ringparam(struct net_device *dev,
1896                               struct ethtool_ringparam *ering)
1897 {
1898         struct b44 *bp = netdev_priv(dev);
1899
1900         ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1901         ering->rx_pending = bp->rx_pending;
1902
1903         /* XXX ethtool lacks a tx_max_pending, oops... */
1904 }
1905
1906 static int b44_set_ringparam(struct net_device *dev,
1907                              struct ethtool_ringparam *ering)
1908 {
1909         struct b44 *bp = netdev_priv(dev);
1910
1911         if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1912             (ering->rx_mini_pending != 0) ||
1913             (ering->rx_jumbo_pending != 0) ||
1914             (ering->tx_pending > B44_TX_RING_SIZE - 1))
1915                 return -EINVAL;
1916
1917         spin_lock_irq(&bp->lock);
1918
1919         bp->rx_pending = ering->rx_pending;
1920         bp->tx_pending = ering->tx_pending;
1921
1922         b44_halt(bp);
1923         b44_init_rings(bp);
1924         b44_init_hw(bp, B44_FULL_RESET);
1925         netif_wake_queue(bp->dev);
1926         spin_unlock_irq(&bp->lock);
1927
1928         b44_enable_ints(bp);
1929
1930         return 0;
1931 }
1932
1933 static void b44_get_pauseparam(struct net_device *dev,
1934                                 struct ethtool_pauseparam *epause)
1935 {
1936         struct b44 *bp = netdev_priv(dev);
1937
1938         epause->autoneg =
1939                 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1940         epause->rx_pause =
1941                 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1942         epause->tx_pause =
1943                 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1944 }
1945
1946 static int b44_set_pauseparam(struct net_device *dev,
1947                                 struct ethtool_pauseparam *epause)
1948 {
1949         struct b44 *bp = netdev_priv(dev);
1950
1951         spin_lock_irq(&bp->lock);
1952         if (epause->autoneg)
1953                 bp->flags |= B44_FLAG_PAUSE_AUTO;
1954         else
1955                 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1956         if (epause->rx_pause)
1957                 bp->flags |= B44_FLAG_RX_PAUSE;
1958         else
1959                 bp->flags &= ~B44_FLAG_RX_PAUSE;
1960         if (epause->tx_pause)
1961                 bp->flags |= B44_FLAG_TX_PAUSE;
1962         else
1963                 bp->flags &= ~B44_FLAG_TX_PAUSE;
1964         if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1965                 b44_halt(bp);
1966                 b44_init_rings(bp);
1967                 b44_init_hw(bp, B44_FULL_RESET);
1968         } else {
1969                 __b44_set_flow_ctrl(bp, bp->flags);
1970         }
1971         spin_unlock_irq(&bp->lock);
1972
1973         b44_enable_ints(bp);
1974
1975         return 0;
1976 }
1977
1978 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1979 {
1980         switch(stringset) {
1981         case ETH_SS_STATS:
1982                 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1983                 break;
1984         }
1985 }
1986
1987 static int b44_get_sset_count(struct net_device *dev, int sset)
1988 {
1989         switch (sset) {
1990         case ETH_SS_STATS:
1991                 return ARRAY_SIZE(b44_gstrings);
1992         default:
1993                 return -EOPNOTSUPP;
1994         }
1995 }
1996
1997 static void b44_get_ethtool_stats(struct net_device *dev,
1998                                   struct ethtool_stats *stats, u64 *data)
1999 {
2000         struct b44 *bp = netdev_priv(dev);
2001         u32 *val = &bp->hw_stats.tx_good_octets;
2002         u32 i;
2003
2004         spin_lock_irq(&bp->lock);
2005
2006         b44_stats_update(bp);
2007
2008         for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2009                 *data++ = *val++;
2010
2011         spin_unlock_irq(&bp->lock);
2012 }
2013
2014 static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2015 {
2016         struct b44 *bp = netdev_priv(dev);
2017
2018         wol->supported = WAKE_MAGIC;
2019         if (bp->flags & B44_FLAG_WOL_ENABLE)
2020                 wol->wolopts = WAKE_MAGIC;
2021         else
2022                 wol->wolopts = 0;
2023         memset(&wol->sopass, 0, sizeof(wol->sopass));
2024 }
2025
2026 static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2027 {
2028         struct b44 *bp = netdev_priv(dev);
2029
2030         spin_lock_irq(&bp->lock);
2031         if (wol->wolopts & WAKE_MAGIC)
2032                 bp->flags |= B44_FLAG_WOL_ENABLE;
2033         else
2034                 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2035         spin_unlock_irq(&bp->lock);
2036
2037         return 0;
2038 }
2039
2040 static const struct ethtool_ops b44_ethtool_ops = {
2041         .get_drvinfo            = b44_get_drvinfo,
2042         .get_settings           = b44_get_settings,
2043         .set_settings           = b44_set_settings,
2044         .nway_reset             = b44_nway_reset,
2045         .get_link               = ethtool_op_get_link,
2046         .get_wol                = b44_get_wol,
2047         .set_wol                = b44_set_wol,
2048         .get_ringparam          = b44_get_ringparam,
2049         .set_ringparam          = b44_set_ringparam,
2050         .get_pauseparam         = b44_get_pauseparam,
2051         .set_pauseparam         = b44_set_pauseparam,
2052         .get_msglevel           = b44_get_msglevel,
2053         .set_msglevel           = b44_set_msglevel,
2054         .get_strings            = b44_get_strings,
2055         .get_sset_count         = b44_get_sset_count,
2056         .get_ethtool_stats      = b44_get_ethtool_stats,
2057 };
2058
2059 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2060 {
2061         struct mii_ioctl_data *data = if_mii(ifr);
2062         struct b44 *bp = netdev_priv(dev);
2063         int err = -EINVAL;
2064
2065         if (!netif_running(dev))
2066                 goto out;
2067
2068         spin_lock_irq(&bp->lock);
2069         err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2070         spin_unlock_irq(&bp->lock);
2071 out:
2072         return err;
2073 }
2074
2075 static int __devinit b44_get_invariants(struct b44 *bp)
2076 {
2077         struct ssb_device *sdev = bp->sdev;
2078         int err = 0;
2079         u8 *addr;
2080
2081         bp->dma_offset = ssb_dma_translation(sdev);
2082
2083         if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2084             instance > 1) {
2085                 addr = sdev->bus->sprom.et1mac;
2086                 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2087         } else {
2088                 addr = sdev->bus->sprom.et0mac;
2089                 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2090         }
2091         /* Some ROMs have buggy PHY addresses with the high
2092          * bits set (sign extension?). Truncate them to a
2093          * valid PHY address. */
2094         bp->phy_addr &= 0x1F;
2095
2096         memcpy(bp->dev->dev_addr, addr, 6);
2097
2098         if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2099                 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
2100                 return -EINVAL;
2101         }
2102
2103         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
2104
2105         bp->imask = IMASK_DEF;
2106
2107         /* XXX - really required?
2108            bp->flags |= B44_FLAG_BUGGY_TXPTR;
2109         */
2110
2111         if (bp->sdev->id.revision >= 7)
2112                 bp->flags |= B44_FLAG_B0_ANDLATER;
2113
2114         return err;
2115 }
2116
2117 static const struct net_device_ops b44_netdev_ops = {
2118         .ndo_open               = b44_open,
2119         .ndo_stop               = b44_close,
2120         .ndo_start_xmit         = b44_start_xmit,
2121         .ndo_get_stats          = b44_get_stats,
2122         .ndo_set_multicast_list = b44_set_rx_mode,
2123         .ndo_set_mac_address    = b44_set_mac_addr,
2124         .ndo_validate_addr      = eth_validate_addr,
2125         .ndo_do_ioctl           = b44_ioctl,
2126         .ndo_tx_timeout         = b44_tx_timeout,
2127         .ndo_change_mtu         = b44_change_mtu,
2128 #ifdef CONFIG_NET_POLL_CONTROLLER
2129         .ndo_poll_controller    = b44_poll_controller,
2130 #endif
2131 };
2132
2133 static int __devinit b44_init_one(struct ssb_device *sdev,
2134                                   const struct ssb_device_id *ent)
2135 {
2136         static int b44_version_printed = 0;
2137         struct net_device *dev;
2138         struct b44 *bp;
2139         int err;
2140
2141         instance++;
2142
2143         if (b44_version_printed++ == 0)
2144                 printk(KERN_INFO "%s", version);
2145
2146
2147         dev = alloc_etherdev(sizeof(*bp));
2148         if (!dev) {
2149                 dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
2150                 err = -ENOMEM;
2151                 goto out;
2152         }
2153
2154         SET_NETDEV_DEV(dev, sdev->dev);
2155
2156         /* No interesting netdevice features in this card... */
2157         dev->features |= 0;
2158
2159         bp = netdev_priv(dev);
2160         bp->sdev = sdev;
2161         bp->dev = dev;
2162         bp->force_copybreak = 0;
2163
2164         bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
2165
2166         spin_lock_init(&bp->lock);
2167
2168         bp->rx_pending = B44_DEF_RX_RING_PENDING;
2169         bp->tx_pending = B44_DEF_TX_RING_PENDING;
2170
2171         dev->netdev_ops = &b44_netdev_ops;
2172         netif_napi_add(dev, &bp->napi, b44_poll, 64);
2173         dev->watchdog_timeo = B44_TX_TIMEOUT;
2174         dev->irq = sdev->irq;
2175         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2176
2177         netif_carrier_off(dev);
2178
2179         err = ssb_bus_powerup(sdev->bus, 0);
2180         if (err) {
2181                 dev_err(sdev->dev,
2182                         "Failed to powerup the bus\n");
2183                 goto err_out_free_dev;
2184         }
2185         err = ssb_dma_set_mask(sdev, DMA_BIT_MASK(30));
2186         if (err) {
2187                 dev_err(sdev->dev,
2188                         "Required 30BIT DMA mask unsupported by the system.\n");
2189                 goto err_out_powerdown;
2190         }
2191         err = b44_get_invariants(bp);
2192         if (err) {
2193                 dev_err(sdev->dev,
2194                         "Problem fetching invariants of chip, aborting.\n");
2195                 goto err_out_powerdown;
2196         }
2197
2198         bp->mii_if.dev = dev;
2199         bp->mii_if.mdio_read = b44_mii_read;
2200         bp->mii_if.mdio_write = b44_mii_write;
2201         bp->mii_if.phy_id = bp->phy_addr;
2202         bp->mii_if.phy_id_mask = 0x1f;
2203         bp->mii_if.reg_num_mask = 0x1f;
2204
2205         /* By default, advertise all speed/duplex settings. */
2206         bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2207                       B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2208
2209         /* By default, auto-negotiate PAUSE. */
2210         bp->flags |= B44_FLAG_PAUSE_AUTO;
2211
2212         err = register_netdev(dev);
2213         if (err) {
2214                 dev_err(sdev->dev, "Cannot register net device, aborting.\n");
2215                 goto err_out_powerdown;
2216         }
2217
2218         ssb_set_drvdata(sdev, dev);
2219
2220         /* Chip reset provides power to the b44 MAC & PCI cores, which
2221          * is necessary for MAC register access.
2222          */
2223         b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2224
2225         printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
2226                dev->name, dev->dev_addr);
2227
2228         return 0;
2229
2230 err_out_powerdown:
2231         ssb_bus_may_powerdown(sdev->bus);
2232
2233 err_out_free_dev:
2234         free_netdev(dev);
2235
2236 out:
2237         return err;
2238 }
2239
2240 static void __devexit b44_remove_one(struct ssb_device *sdev)
2241 {
2242         struct net_device *dev = ssb_get_drvdata(sdev);
2243
2244         unregister_netdev(dev);
2245         ssb_device_disable(sdev, 0);
2246         ssb_bus_may_powerdown(sdev->bus);
2247         free_netdev(dev);
2248         ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2249         ssb_set_drvdata(sdev, NULL);
2250 }
2251
2252 static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
2253 {
2254         struct net_device *dev = ssb_get_drvdata(sdev);
2255         struct b44 *bp = netdev_priv(dev);
2256
2257         if (!netif_running(dev))
2258                 return 0;
2259
2260         del_timer_sync(&bp->timer);
2261
2262         spin_lock_irq(&bp->lock);
2263
2264         b44_halt(bp);
2265         netif_carrier_off(bp->dev);
2266         netif_device_detach(bp->dev);
2267         b44_free_rings(bp);
2268
2269         spin_unlock_irq(&bp->lock);
2270
2271         free_irq(dev->irq, dev);
2272         if (bp->flags & B44_FLAG_WOL_ENABLE) {
2273                 b44_init_hw(bp, B44_PARTIAL_RESET);
2274                 b44_setup_wol(bp);
2275         }
2276
2277         ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2278         return 0;
2279 }
2280
2281 static int b44_resume(struct ssb_device *sdev)
2282 {
2283         struct net_device *dev = ssb_get_drvdata(sdev);
2284         struct b44 *bp = netdev_priv(dev);
2285         int rc = 0;
2286
2287         rc = ssb_bus_powerup(sdev->bus, 0);
2288         if (rc) {
2289                 dev_err(sdev->dev,
2290                         "Failed to powerup the bus\n");
2291                 return rc;
2292         }
2293
2294         if (!netif_running(dev))
2295                 return 0;
2296
2297         rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2298         if (rc) {
2299                 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2300                 return rc;
2301         }
2302
2303         spin_lock_irq(&bp->lock);
2304
2305         b44_init_rings(bp);
2306         b44_init_hw(bp, B44_FULL_RESET);
2307         netif_device_attach(bp->dev);
2308         spin_unlock_irq(&bp->lock);
2309
2310         b44_enable_ints(bp);
2311         netif_wake_queue(dev);
2312
2313         mod_timer(&bp->timer, jiffies + 1);
2314
2315         return 0;
2316 }
2317
2318 static struct ssb_driver b44_ssb_driver = {
2319         .name           = DRV_MODULE_NAME,
2320         .id_table       = b44_ssb_tbl,
2321         .probe          = b44_init_one,
2322         .remove         = __devexit_p(b44_remove_one),
2323         .suspend        = b44_suspend,
2324         .resume         = b44_resume,
2325 };
2326
2327 static inline int b44_pci_init(void)
2328 {
2329         int err = 0;
2330 #ifdef CONFIG_B44_PCI
2331         err = ssb_pcihost_register(&b44_pci_driver);
2332 #endif
2333         return err;
2334 }
2335
2336 static inline void b44_pci_exit(void)
2337 {
2338 #ifdef CONFIG_B44_PCI
2339         ssb_pcihost_unregister(&b44_pci_driver);
2340 #endif
2341 }
2342
2343 static int __init b44_init(void)
2344 {
2345         unsigned int dma_desc_align_size = dma_get_cache_alignment();
2346         int err;
2347
2348         /* Setup paramaters for syncing RX/TX DMA descriptors */
2349         dma_desc_align_mask = ~(dma_desc_align_size - 1);
2350         dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2351
2352         err = b44_pci_init();
2353         if (err)
2354                 return err;
2355         err = ssb_driver_register(&b44_ssb_driver);
2356         if (err)
2357                 b44_pci_exit();
2358         return err;
2359 }
2360
2361 static void __exit b44_cleanup(void)
2362 {
2363         ssb_driver_unregister(&b44_ssb_driver);
2364         b44_pci_exit();
2365 }
2366
2367 module_init(b44_init);
2368 module_exit(b44_cleanup);
2369