Pileus Git - ~andy/linux/blob - drivers/mtd/nand/pxa3xx_nand.c

   1 /*
   2  * drivers/mtd/nand/pxa3xx_nand.c
   3  *
   4  * Copyright © 2005 Intel Corporation
   5  * Copyright © 2006 Marvell International Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/delay.h>
  18 #include <linux/clk.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/io.h>
  23 #include <linux/irq.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27
  28 #include <mach/dma.h>
  29 #include <linux/platform_data/mtd-nand-pxa3xx.h>
  30
  31 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
  32 #define NAND_STOP_DELAY         (2 * HZ/50)
  33 #define PAGE_CHUNK_SIZE         (2048)
  34
  35 /* registers and bit definitions */
  36 #define NDCR            (0x00) /* Control register */
  37 #define NDTR0CS0        (0x04) /* Timing Parameter 0 for CS0 */
  38 #define NDTR1CS0        (0x0C) /* Timing Parameter 1 for CS0 */
  39 #define NDSR            (0x14) /* Status Register */
  40 #define NDPCR           (0x18) /* Page Count Register */
  41 #define NDBDR0          (0x1C) /* Bad Block Register 0 */
  42 #define NDBDR1          (0x20) /* Bad Block Register 1 */
  43 #define NDDB            (0x40) /* Data Buffer */
  44 #define NDCB0           (0x48) /* Command Buffer0 */
  45 #define NDCB1           (0x4C) /* Command Buffer1 */
  46 #define NDCB2           (0x50) /* Command Buffer2 */
  47
  48 #define NDCR_SPARE_EN           (0x1 << 31)
  49 #define NDCR_ECC_EN             (0x1 << 30)
  50 #define NDCR_DMA_EN             (0x1 << 29)
  51 #define NDCR_ND_RUN             (0x1 << 28)
  52 #define NDCR_DWIDTH_C           (0x1 << 27)
  53 #define NDCR_DWIDTH_M           (0x1 << 26)
  54 #define NDCR_PAGE_SZ            (0x1 << 24)
  55 #define NDCR_NCSX               (0x1 << 23)
  56 #define NDCR_ND_MODE            (0x3 << 21)
  57 #define NDCR_NAND_MODE          (0x0)
  58 #define NDCR_CLR_PG_CNT         (0x1 << 20)
  59 #define NDCR_STOP_ON_UNCOR      (0x1 << 19)
  60 #define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
  61 #define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  62
  63 #define NDCR_RA_START           (0x1 << 15)
  64 #define NDCR_PG_PER_BLK         (0x1 << 14)
  65 #define NDCR_ND_ARB_EN          (0x1 << 12)
  66 #define NDCR_INT_MASK           (0xFFF)
  67
  68 #define NDSR_MASK               (0xfff)
  69 #define NDSR_RDY                (0x1 << 12)
  70 #define NDSR_FLASH_RDY          (0x1 << 11)
  71 #define NDSR_CS0_PAGED          (0x1 << 10)
  72 #define NDSR_CS1_PAGED          (0x1 << 9)
  73 #define NDSR_CS0_CMDD           (0x1 << 8)
  74 #define NDSR_CS1_CMDD           (0x1 << 7)
  75 #define NDSR_CS0_BBD            (0x1 << 6)
  76 #define NDSR_CS1_BBD            (0x1 << 5)
  77 #define NDSR_DBERR              (0x1 << 4)
  78 #define NDSR_SBERR              (0x1 << 3)
  79 #define NDSR_WRDREQ             (0x1 << 2)
  80 #define NDSR_RDDREQ             (0x1 << 1)
  81 #define NDSR_WRCMDREQ           (0x1)
  82
  83 #define NDCB0_ST_ROW_EN         (0x1 << 26)
  84 #define NDCB0_AUTO_RS           (0x1 << 25)
  85 #define NDCB0_CSEL              (0x1 << 24)
  86 #define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
  87 #define NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  88 #define NDCB0_NC                (0x1 << 20)
  89 #define NDCB0_DBC               (0x1 << 19)
  90 #define NDCB0_ADDR_CYC_MASK     (0x7 << 16)
  91 #define NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  92 #define NDCB0_CMD2_MASK         (0xff << 8)
  93 #define NDCB0_CMD1_MASK         (0xff)
  94 #define NDCB0_ADDR_CYC_SHIFT    (16)
  95
  96 /* macros for registers read/write */
  97 #define nand_writel(info, off, val)     \
  98         __raw_writel((val), (info)->mmio_base + (off))
  99
 100 #define nand_readl(info, off)           \
 101         __raw_readl((info)->mmio_base + (off))
 102
 103 /* error code and state */
 104 enum {
 105         ERR_NONE        = 0,
 106         ERR_DMABUSERR   = -1,
 107         ERR_SENDCMD     = -2,
 108         ERR_DBERR       = -3,
 109         ERR_BBERR       = -4,
 110         ERR_SBERR       = -5,
 111 };
 112
 113 enum {
 114         STATE_IDLE = 0,
 115         STATE_PREPARED,
 116         STATE_CMD_HANDLE,
 117         STATE_DMA_READING,
 118         STATE_DMA_WRITING,
 119         STATE_DMA_DONE,
 120         STATE_PIO_READING,
 121         STATE_PIO_WRITING,
 122         STATE_CMD_DONE,
 123         STATE_READY,
 124 };
 125
 126 enum pxa3xx_nand_variant {
 127         PXA3XX_NAND_VARIANT_PXA,
 128         PXA3XX_NAND_VARIANT_ARMADA370,
 129 };
 130
 131 struct pxa3xx_nand_host {
 132         struct nand_chip        chip;
 133         struct pxa3xx_nand_cmdset *cmdset;
 134         struct mtd_info         *mtd;
 135         void                    *info_data;
 136
 137         /* page size of attached chip */
 138         unsigned int            page_size;
 139         int                     use_ecc;
 140         int                     cs;
 141
 142         /* calculated from pxa3xx_nand_flash data */
 143         unsigned int            col_addr_cycles;
 144         unsigned int            row_addr_cycles;
 145         size_t                  read_id_bytes;
 146
 147         /* cached register value */
 148         uint32_t                reg_ndcr;
 149         uint32_t                ndtr0cs0;
 150         uint32_t                ndtr1cs0;
 151 };
 152
 153 struct pxa3xx_nand_info {
 154         struct nand_hw_control  controller;
 155         struct platform_device   *pdev;
 156
 157         struct clk              *clk;
 158         void __iomem            *mmio_base;
 159         unsigned long           mmio_phys;
 160         struct completion       cmd_complete;
 161
 162         unsigned int            buf_start;
 163         unsigned int            buf_count;
 164
 165         /* DMA information */
 166         int                     drcmr_dat;
 167         int                     drcmr_cmd;
 168
 169         unsigned char           *data_buff;
 170         unsigned char           *oob_buff;
 171         dma_addr_t              data_buff_phys;
 172         int                     data_dma_ch;
 173         struct pxa_dma_desc     *data_desc;
 174         dma_addr_t              data_desc_addr;
 175
 176         struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
 177         unsigned int            state;
 178
 179         /*
 180          * This driver supports NFCv1 (as found in PXA SoC)
 181          * and NFCv2 (as found in Armada 370/XP SoC).
 182          */
 183         enum pxa3xx_nand_variant variant;
 184
 185         int                     cs;
 186         int                     use_ecc;        /* use HW ECC ? */
 187         int                     use_dma;        /* use DMA ? */
 188         int                     is_ready;
 189
 190         unsigned int            page_size;      /* page size of attached chip */
 191         unsigned int            data_size;      /* data size in FIFO */
 192         unsigned int            oob_size;
 193         int                     retcode;
 194
 195         /* generated NDCBx register values */
 196         uint32_t                ndcb0;
 197         uint32_t                ndcb1;
 198         uint32_t                ndcb2;
 199 };
 200
 201 static bool use_dma = 1;
 202 module_param(use_dma, bool, 0444);
 203 MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
 204
 205 /*
 206  * Default NAND flash controller configuration setup by the
 207  * bootloader. This configuration is used only when pdata->keep_config is set
 208  */
 209 static struct pxa3xx_nand_cmdset default_cmdset = {
 210         .read1          = 0x3000,
 211         .read2          = 0x0050,
 212         .program        = 0x1080,
 213         .read_status    = 0x0070,
 214         .read_id        = 0x0090,
 215         .erase          = 0xD060,
 216         .reset          = 0x00FF,
 217         .lock           = 0x002A,
 218         .unlock         = 0x2423,
 219         .lock_status    = 0x007A,
 220 };
 221
 222 static struct pxa3xx_nand_timing timing[] = {
 223         { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
 224         { 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 225         { 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 226         { 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
 227 };
 228
 229 static struct pxa3xx_nand_flash builtin_flash_types[] = {
 230 { "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, &timing[0] },
 231 { "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1] },
 232 { "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1] },
 233 { "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1] },
 234 { "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2] },
 235 { "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2] },
 236 { "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, &timing[2] },
 237 { "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2] },
 238 { "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3] },
 239 };
 240
 241 /* Define a default flash type setting serve as flash detecting only */
 242 #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
 243
 244 const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
 245
 246 #define NDTR0_tCH(c)    (min((c), 7) << 19)
 247 #define NDTR0_tCS(c)    (min((c), 7) << 16)
 248 #define NDTR0_tWH(c)    (min((c), 7) << 11)
 249 #define NDTR0_tWP(c)    (min((c), 7) << 8)
 250 #define NDTR0_tRH(c)    (min((c), 7) << 3)
 251 #define NDTR0_tRP(c)    (min((c), 7) << 0)
 252
 253 #define NDTR1_tR(c)     (min((c), 65535) << 16)
 254 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
 255 #define NDTR1_tAR(c)    (min((c), 15) << 0)
 256
 257 /* convert nano-seconds to nand flash controller clock cycles */
 258 #define ns2cycle(ns, clk)       (int)((ns) * (clk / 1000000) / 1000)
 259
 260 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
 261                                    const struct pxa3xx_nand_timing *t)
 262 {
 263         struct pxa3xx_nand_info *info = host->info_data;
 264         unsigned long nand_clk = clk_get_rate(info->clk);
 265         uint32_t ndtr0, ndtr1;
 266
 267         ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
 268                 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
 269                 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
 270                 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
 271                 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
 272                 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
 273
 274         ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
 275                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
 276                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
 277
 278         host->ndtr0cs0 = ndtr0;
 279         host->ndtr1cs0 = ndtr1;
 280         nand_writel(info, NDTR0CS0, ndtr0);
 281         nand_writel(info, NDTR1CS0, ndtr1);
 282 }
 283
 284 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 285 {
 286         struct pxa3xx_nand_host *host = info->host[info->cs];
 287         int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
 288
 289         info->data_size = host->page_size;
 290         if (!oob_enable) {
 291                 info->oob_size = 0;
 292                 return;
 293         }
 294
 295         switch (host->page_size) {
 296         case 2048:
 297                 info->oob_size = (info->use_ecc) ? 40 : 64;
 298                 break;
 299         case 512:
 300                 info->oob_size = (info->use_ecc) ? 8 : 16;
 301                 break;
 302         }
 303 }
 304
 305 /**
 306  * NOTE: it is a must to set ND_RUN firstly, then write
 307  * command buffer, otherwise, it does not work.
 308  * We enable all the interrupt at the same time, and
 309  * let pxa3xx_nand_irq to handle all logic.
 310  */
 311 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
 312 {
 313         struct pxa3xx_nand_host *host = info->host[info->cs];
 314         uint32_t ndcr;
 315
 316         ndcr = host->reg_ndcr;
 317         ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
 318         ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
 319         ndcr |= NDCR_ND_RUN;
 320
 321         /* clear status bits and run */
 322         nand_writel(info, NDCR, 0);
 323         nand_writel(info, NDSR, NDSR_MASK);
 324         nand_writel(info, NDCR, ndcr);
 325 }
 326
 327 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
 328 {
 329         uint32_t ndcr;
 330         int timeout = NAND_STOP_DELAY;
 331
 332         /* wait RUN bit in NDCR become 0 */
 333         ndcr = nand_readl(info, NDCR);
 334         while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
 335                 ndcr = nand_readl(info, NDCR);
 336                 udelay(1);
 337         }
 338
 339         if (timeout <= 0) {
 340                 ndcr &= ~NDCR_ND_RUN;
 341                 nand_writel(info, NDCR, ndcr);
 342         }
 343         /* clear status bits */
 344         nand_writel(info, NDSR, NDSR_MASK);
 345 }
 346
 347 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 348 {
 349         uint32_t ndcr;
 350
 351         ndcr = nand_readl(info, NDCR);
 352         nand_writel(info, NDCR, ndcr & ~int_mask);
 353 }
 354
 355 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 356 {
 357         uint32_t ndcr;
 358
 359         ndcr = nand_readl(info, NDCR);
 360         nand_writel(info, NDCR, ndcr | int_mask);
 361 }
 362
 363 static void handle_data_pio(struct pxa3xx_nand_info *info)
 364 {
 365         switch (info->state) {
 366         case STATE_PIO_WRITING:
 367                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
 368                                 DIV_ROUND_UP(info->data_size, 4));
 369                 if (info->oob_size > 0)
 370                         __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
 371                                         DIV_ROUND_UP(info->oob_size, 4));
 372                 break;
 373         case STATE_PIO_READING:
 374                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
 375                                 DIV_ROUND_UP(info->data_size, 4));
 376                 if (info->oob_size > 0)
 377                         __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
 378                                         DIV_ROUND_UP(info->oob_size, 4));
 379                 break;
 380         default:
 381                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 382                                 info->state);
 383                 BUG();
 384         }
 385 }
 386
 387 static void start_data_dma(struct pxa3xx_nand_info *info)
 388 {
 389         struct pxa_dma_desc *desc = info->data_desc;
 390         int dma_len = ALIGN(info->data_size + info->oob_size, 32);
 391
 392         desc->ddadr = DDADR_STOP;
 393         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
 394
 395         switch (info->state) {
 396         case STATE_DMA_WRITING:
 397                 desc->dsadr = info->data_buff_phys;
 398                 desc->dtadr = info->mmio_phys + NDDB;
 399                 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
 400                 break;
 401         case STATE_DMA_READING:
 402                 desc->dtadr = info->data_buff_phys;
 403                 desc->dsadr = info->mmio_phys + NDDB;
 404                 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
 405                 break;
 406         default:
 407                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 408                                 info->state);
 409                 BUG();
 410         }
 411
 412         DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
 413         DDADR(info->data_dma_ch) = info->data_desc_addr;
 414         DCSR(info->data_dma_ch) |= DCSR_RUN;
 415 }
 416
 417 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
 418 {
 419         struct pxa3xx_nand_info *info = data;
 420         uint32_t dcsr;
 421
 422         dcsr = DCSR(channel);
 423         DCSR(channel) = dcsr;
 424
 425         if (dcsr & DCSR_BUSERR) {
 426                 info->retcode = ERR_DMABUSERR;
 427         }
 428
 429         info->state = STATE_DMA_DONE;
 430         enable_int(info, NDCR_INT_MASK);
 431         nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 432 }
 433
 434 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 435 {
 436         struct pxa3xx_nand_info *info = devid;
 437         unsigned int status, is_completed = 0;
 438         unsigned int ready, cmd_done;
 439
 440         if (info->cs == 0) {
 441                 ready           = NDSR_FLASH_RDY;
 442                 cmd_done        = NDSR_CS0_CMDD;
 443         } else {
 444                 ready           = NDSR_RDY;
 445                 cmd_done        = NDSR_CS1_CMDD;
 446         }
 447
 448         status = nand_readl(info, NDSR);
 449
 450         if (status & NDSR_DBERR)
 451                 info->retcode = ERR_DBERR;
 452         if (status & NDSR_SBERR)
 453                 info->retcode = ERR_SBERR;
 454         if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
 455                 /* whether use dma to transfer data */
 456                 if (info->use_dma) {
 457                         disable_int(info, NDCR_INT_MASK);
 458                         info->state = (status & NDSR_RDDREQ) ?
 459                                       STATE_DMA_READING : STATE_DMA_WRITING;
 460                         start_data_dma(info);
 461                         goto NORMAL_IRQ_EXIT;
 462                 } else {
 463                         info->state = (status & NDSR_RDDREQ) ?
 464                                       STATE_PIO_READING : STATE_PIO_WRITING;
 465                         handle_data_pio(info);
 466                 }
 467         }
 468         if (status & cmd_done) {
 469                 info->state = STATE_CMD_DONE;
 470                 is_completed = 1;
 471         }
 472         if (status & ready) {
 473                 info->is_ready = 1;
 474                 info->state = STATE_READY;
 475         }
 476
 477         if (status & NDSR_WRCMDREQ) {
 478                 nand_writel(info, NDSR, NDSR_WRCMDREQ);
 479                 status &= ~NDSR_WRCMDREQ;
 480                 info->state = STATE_CMD_HANDLE;
 481                 nand_writel(info, NDCB0, info->ndcb0);
 482                 nand_writel(info, NDCB0, info->ndcb1);
 483                 nand_writel(info, NDCB0, info->ndcb2);
 484         }
 485
 486         /* clear NDSR to let the controller exit the IRQ */
 487         nand_writel(info, NDSR, status);
 488         if (is_completed)
 489                 complete(&info->cmd_complete);
 490 NORMAL_IRQ_EXIT:
 491         return IRQ_HANDLED;
 492 }
 493
 494 static inline int is_buf_blank(uint8_t *buf, size_t len)
 495 {
 496         for (; len > 0; len--)
 497                 if (*buf++ != 0xff)
 498                         return 0;
 499         return 1;
 500 }
 501
 502 static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
 503                 uint16_t column, int page_addr)
 504 {
 505         uint16_t cmd;
 506         int addr_cycle, exec_cmd;
 507         struct pxa3xx_nand_host *host;
 508         struct mtd_info *mtd;
 509
 510         host = info->host[info->cs];
 511         mtd = host->mtd;
 512         addr_cycle = 0;
 513         exec_cmd = 1;
 514
 515         /* reset data and oob column point to handle data */
 516         info->buf_start         = 0;
 517         info->buf_count         = 0;
 518         info->oob_size          = 0;
 519         info->use_ecc           = 0;
 520         info->use_dma           = (use_dma) ? 1 : 0;
 521         info->is_ready          = 0;
 522         info->retcode           = ERR_NONE;
 523         if (info->cs != 0)
 524                 info->ndcb0 = NDCB0_CSEL;
 525         else
 526                 info->ndcb0 = 0;
 527
 528         switch (command) {
 529         case NAND_CMD_READ0:
 530         case NAND_CMD_PAGEPROG:
 531                 info->use_ecc = 1;
 532         case NAND_CMD_READOOB:
 533                 pxa3xx_set_datasize(info);
 534                 break;
 535         case NAND_CMD_SEQIN:
 536                 exec_cmd = 0;
 537                 break;
 538         default:
 539                 info->ndcb1 = 0;
 540                 info->ndcb2 = 0;
 541                 break;
 542         }
 543
 544         addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
 545                                     + host->col_addr_cycles);
 546
 547         switch (command) {
 548         case NAND_CMD_READOOB:
 549         case NAND_CMD_READ0:
 550                 cmd = host->cmdset->read1;
 551                 if (command == NAND_CMD_READOOB)
 552                         info->buf_start = mtd->writesize + column;
 553                 else
 554                         info->buf_start = column;
 555
 556                 if (unlikely(host->page_size < PAGE_CHUNK_SIZE))
 557                         info->ndcb0 |= NDCB0_CMD_TYPE(0)
 558                                         | addr_cycle
 559                                         | (cmd & NDCB0_CMD1_MASK);
 560                 else
 561                         info->ndcb0 |= NDCB0_CMD_TYPE(0)
 562                                         | NDCB0_DBC
 563                                         | addr_cycle
 564                                         | cmd;
 565
 566         case NAND_CMD_SEQIN:
 567                 /* small page addr setting */
 568                 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
 569                         info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 570                                         | (column & 0xFF);
 571
 572                         info->ndcb2 = 0;
 573                 } else {
 574                         info->ndcb1 = ((page_addr & 0xFFFF) << 16)
 575                                         | (column & 0xFFFF);
 576
 577                         if (page_addr & 0xFF0000)
 578                                 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
 579                         else
 580                                 info->ndcb2 = 0;
 581                 }
 582
 583                 info->buf_count = mtd->writesize + mtd->oobsize;
 584                 memset(info->data_buff, 0xFF, info->buf_count);
 585
 586                 break;
 587
 588         case NAND_CMD_PAGEPROG:
 589                 if (is_buf_blank(info->data_buff,
 590                                         (mtd->writesize + mtd->oobsize))) {
 591                         exec_cmd = 0;
 592                         break;
 593                 }
 594
 595                 cmd = host->cmdset->program;
 596                 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
 597                                 | NDCB0_AUTO_RS
 598                                 | NDCB0_ST_ROW_EN
 599                                 | NDCB0_DBC
 600                                 | cmd
 601                                 | addr_cycle;
 602                 break;
 603
 604         case NAND_CMD_PARAM:
 605                 cmd = NAND_CMD_PARAM;
 606                 info->buf_count = 256;
 607                 info->ndcb0 |= NDCB0_CMD_TYPE(0)
 608                                 | NDCB0_ADDR_CYC(1)
 609                                 | cmd;
 610                 info->ndcb1 = (column & 0xFF);
 611                 info->data_size = 256;
 612                 break;
 613
 614         case NAND_CMD_READID:
 615                 cmd = host->cmdset->read_id;
 616                 info->buf_count = host->read_id_bytes;
 617                 info->ndcb0 |= NDCB0_CMD_TYPE(3)
 618                                 | NDCB0_ADDR_CYC(1)
 619                                 | cmd;
 620                 info->ndcb1 = (column & 0xFF);
 621
 622                 info->data_size = 8;
 623                 break;
 624         case NAND_CMD_STATUS:
 625                 cmd = host->cmdset->read_status;
 626                 info->buf_count = 1;
 627                 info->ndcb0 |= NDCB0_CMD_TYPE(4)
 628                                 | NDCB0_ADDR_CYC(1)
 629                                 | cmd;
 630
 631                 info->data_size = 8;
 632                 break;
 633
 634         case NAND_CMD_ERASE1:
 635                 cmd = host->cmdset->erase;
 636                 info->ndcb0 |= NDCB0_CMD_TYPE(2)
 637                                 | NDCB0_AUTO_RS
 638                                 | NDCB0_ADDR_CYC(3)
 639                                 | NDCB0_DBC
 640                                 | cmd;
 641                 info->ndcb1 = page_addr;
 642                 info->ndcb2 = 0;
 643
 644                 break;
 645         case NAND_CMD_RESET:
 646                 cmd = host->cmdset->reset;
 647                 info->ndcb0 |= NDCB0_CMD_TYPE(5)
 648                                 | cmd;
 649
 650                 break;
 651
 652         case NAND_CMD_ERASE2:
 653                 exec_cmd = 0;
 654                 break;
 655
 656         default:
 657                 exec_cmd = 0;
 658                 dev_err(&info->pdev->dev, "non-supported command %x\n",
 659                                 command);
 660                 break;
 661         }
 662
 663         return exec_cmd;
 664 }
 665
 666 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 667                                 int column, int page_addr)
 668 {
 669         struct pxa3xx_nand_host *host = mtd->priv;
 670         struct pxa3xx_nand_info *info = host->info_data;
 671         int ret, exec_cmd;
 672
 673         /*
 674          * if this is a x16 device ,then convert the input
 675          * "byte" address into a "word" address appropriate
 676          * for indexing a word-oriented device
 677          */
 678         if (host->reg_ndcr & NDCR_DWIDTH_M)
 679                 column /= 2;
 680
 681         /*
 682          * There may be different NAND chip hooked to
 683          * different chip select, so check whether
 684          * chip select has been changed, if yes, reset the timing
 685          */
 686         if (info->cs != host->cs) {
 687                 info->cs = host->cs;
 688                 nand_writel(info, NDTR0CS0, host->ndtr0cs0);
 689                 nand_writel(info, NDTR1CS0, host->ndtr1cs0);
 690         }
 691
 692         info->state = STATE_PREPARED;
 693         exec_cmd = prepare_command_pool(info, command, column, page_addr);
 694         if (exec_cmd) {
 695                 init_completion(&info->cmd_complete);
 696                 pxa3xx_nand_start(info);
 697
 698                 ret = wait_for_completion_timeout(&info->cmd_complete,
 699                                 CHIP_DELAY_TIMEOUT);
 700                 if (!ret) {
 701                         dev_err(&info->pdev->dev, "Wait time out!!!\n");
 702                         /* Stop State Machine for next command cycle */
 703                         pxa3xx_nand_stop(info);
 704                 }
 705         }
 706         info->state = STATE_IDLE;
 707 }
 708
 709 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
 710                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
 711 {
 712         chip->write_buf(mtd, buf, mtd->writesize);
 713         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 714
 715         return 0;
 716 }
 717
 718 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 719                 struct nand_chip *chip, uint8_t *buf, int oob_required,
 720                 int page)
 721 {
 722         struct pxa3xx_nand_host *host = mtd->priv;
 723         struct pxa3xx_nand_info *info = host->info_data;
 724
 725         chip->read_buf(mtd, buf, mtd->writesize);
 726         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 727
 728         if (info->retcode == ERR_SBERR) {
 729                 switch (info->use_ecc) {
 730                 case 1:
 731                         mtd->ecc_stats.corrected++;
 732                         break;
 733                 case 0:
 734                 default:
 735                         break;
 736                 }
 737         } else if (info->retcode == ERR_DBERR) {
 738                 /*
 739                  * for blank page (all 0xff), HW will calculate its ECC as
 740                  * 0, which is different from the ECC information within
 741                  * OOB, ignore such double bit errors
 742                  */
 743                 if (is_buf_blank(buf, mtd->writesize))
 744                         info->retcode = ERR_NONE;
 745                 else
 746                         mtd->ecc_stats.failed++;
 747         }
 748
 749         return 0;
 750 }
 751
 752 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 753 {
 754         struct pxa3xx_nand_host *host = mtd->priv;
 755         struct pxa3xx_nand_info *info = host->info_data;
 756         char retval = 0xFF;
 757
 758         if (info->buf_start < info->buf_count)
 759                 /* Has just send a new command? */
 760                 retval = info->data_buff[info->buf_start++];
 761
 762         return retval;
 763 }
 764
 765 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 766 {
 767         struct pxa3xx_nand_host *host = mtd->priv;
 768         struct pxa3xx_nand_info *info = host->info_data;
 769         u16 retval = 0xFFFF;
 770
 771         if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
 772                 retval = *((u16 *)(info->data_buff+info->buf_start));
 773                 info->buf_start += 2;
 774         }
 775         return retval;
 776 }
 777
 778 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 779 {
 780         struct pxa3xx_nand_host *host = mtd->priv;
 781         struct pxa3xx_nand_info *info = host->info_data;
 782         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 783
 784         memcpy(buf, info->data_buff + info->buf_start, real_len);
 785         info->buf_start += real_len;
 786 }
 787
 788 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 789                 const uint8_t *buf, int len)
 790 {
 791         struct pxa3xx_nand_host *host = mtd->priv;
 792         struct pxa3xx_nand_info *info = host->info_data;
 793         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 794
 795         memcpy(info->data_buff + info->buf_start, buf, real_len);
 796         info->buf_start += real_len;
 797 }
 798
 799 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
 800 {
 801         return;
 802 }
 803
 804 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 805 {
 806         struct pxa3xx_nand_host *host = mtd->priv;
 807         struct pxa3xx_nand_info *info = host->info_data;
 808
 809         /* pxa3xx_nand_send_command has waited for command complete */
 810         if (this->state == FL_WRITING || this->state == FL_ERASING) {
 811                 if (info->retcode == ERR_NONE)
 812                         return 0;
 813                 else {
 814                         /*
 815                          * any error make it return 0x01 which will tell
 816                          * the caller the erase and write fail
 817                          */
 818                         return 0x01;
 819                 }
 820         }
 821
 822         return 0;
 823 }
 824
 825 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 826                                     const struct pxa3xx_nand_flash *f)
 827 {
 828         struct platform_device *pdev = info->pdev;
 829         struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 830         struct pxa3xx_nand_host *host = info->host[info->cs];
 831         uint32_t ndcr = 0x0; /* enable all interrupts */
 832
 833         if (f->page_size != 2048 && f->page_size != 512) {
 834                 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
 835                 return -EINVAL;
 836         }
 837
 838         if (f->flash_width != 16 && f->flash_width != 8) {
 839                 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
 840                 return -EINVAL;
 841         }
 842
 843         /* calculate flash information */
 844         host->cmdset = &default_cmdset;
 845         host->page_size = f->page_size;
 846         host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
 847
 848         /* calculate addressing information */
 849         host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
 850
 851         if (f->num_blocks * f->page_per_block > 65536)
 852                 host->row_addr_cycles = 3;
 853         else
 854                 host->row_addr_cycles = 2;
 855
 856         ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
 857         ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 858         ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
 859         ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
 860         ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
 861         ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
 862
 863         ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
 864         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
 865
 866         host->reg_ndcr = ndcr;
 867
 868         pxa3xx_nand_set_timing(host, f->timing);
 869         return 0;
 870 }
 871
 872 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 873 {
 874         /*
 875          * We set 0 by hard coding here, for we don't support keep_config
 876          * when there is more than one chip attached to the controller
 877          */
 878         struct pxa3xx_nand_host *host = info->host[0];
 879         uint32_t ndcr = nand_readl(info, NDCR);
 880
 881         if (ndcr & NDCR_PAGE_SZ) {
 882                 host->page_size = 2048;
 883                 host->read_id_bytes = 4;
 884         } else {
 885                 host->page_size = 512;
 886                 host->read_id_bytes = 2;
 887         }
 888
 889         host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
 890         host->cmdset = &default_cmdset;
 891
 892         host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
 893         host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
 894
 895         return 0;
 896 }
 897
 898 /* the maximum possible buffer size for large page with OOB data
 899  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
 900  * data buffer and the DMA descriptor
 901  */
 902 #define MAX_BUFF_SIZE   PAGE_SIZE
 903
 904 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 905 {
 906         struct platform_device *pdev = info->pdev;
 907         int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
 908
 909         if (use_dma == 0) {
 910                 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
 911                 if (info->data_buff == NULL)
 912                         return -ENOMEM;
 913                 return 0;
 914         }
 915
 916         info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
 917                                 &info->data_buff_phys, GFP_KERNEL);
 918         if (info->data_buff == NULL) {
 919                 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
 920                 return -ENOMEM;
 921         }
 922
 923         info->data_desc = (void *)info->data_buff + data_desc_offset;
 924         info->data_desc_addr = info->data_buff_phys + data_desc_offset;
 925
 926         info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
 927                                 pxa3xx_nand_data_dma_irq, info);
 928         if (info->data_dma_ch < 0) {
 929                 dev_err(&pdev->dev, "failed to request data dma\n");
 930                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 931                                 info->data_buff, info->data_buff_phys);
 932                 return info->data_dma_ch;
 933         }
 934
 935         return 0;
 936 }
 937
 938 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
 939 {
 940         struct platform_device *pdev = info->pdev;
 941         if (use_dma) {
 942                 pxa_free_dma(info->data_dma_ch);
 943                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 944                                   info->data_buff, info->data_buff_phys);
 945         } else {
 946                 kfree(info->data_buff);
 947         }
 948 }
 949
 950 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
 951 {
 952         struct mtd_info *mtd;
 953         int ret;
 954         mtd = info->host[info->cs]->mtd;
 955         /* use the common timing to make a try */
 956         ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
 957         if (ret)
 958                 return ret;
 959
 960         pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
 961         if (info->is_ready)
 962                 return 0;
 963
 964         return -ENODEV;
 965 }
 966
 967 static int pxa3xx_nand_scan(struct mtd_info *mtd)
 968 {
 969         struct pxa3xx_nand_host *host = mtd->priv;
 970         struct pxa3xx_nand_info *info = host->info_data;
 971         struct platform_device *pdev = info->pdev;
 972         struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 973         struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
 974         const struct pxa3xx_nand_flash *f = NULL;
 975         struct nand_chip *chip = mtd->priv;
 976         uint32_t id = -1;
 977         uint64_t chipsize;
 978         int i, ret, num;
 979
 980         if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
 981                 goto KEEP_CONFIG;
 982
 983         ret = pxa3xx_nand_sensing(info);
 984         if (ret) {
 985                 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
 986                          info->cs);
 987
 988                 return ret;
 989         }
 990
 991         chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
 992         id = *((uint16_t *)(info->data_buff));
 993         if (id != 0)
 994                 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
 995         else {
 996                 dev_warn(&info->pdev->dev,
 997                          "Read out ID 0, potential timing set wrong!!\n");
 998
 999                 return -EINVAL;
1000         }
1001
1002         num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
1003         for (i = 0; i < num; i++) {
1004                 if (i < pdata->num_flash)
1005                         f = pdata->flash + i;
1006                 else
1007                         f = &builtin_flash_types[i - pdata->num_flash + 1];
1008
1009                 /* find the chip in default list */
1010                 if (f->chip_id == id)
1011                         break;
1012         }
1013
1014         if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
1015                 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
1016
1017                 return -EINVAL;
1018         }
1019
1020         ret = pxa3xx_nand_config_flash(info, f);
1021         if (ret) {
1022                 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
1023                 return ret;
1024         }
1025
1026         pxa3xx_flash_ids[0].name = f->name;
1027         pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
1028         pxa3xx_flash_ids[0].pagesize = f->page_size;
1029         chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
1030         pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1031         pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1032         if (f->flash_width == 16)
1033                 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
1034         pxa3xx_flash_ids[1].name = NULL;
1035         def = pxa3xx_flash_ids;
1036 KEEP_CONFIG:
1037         chip->ecc.mode = NAND_ECC_HW;
1038         chip->ecc.size = host->page_size;
1039         chip->ecc.strength = 1;
1040
1041         if (host->reg_ndcr & NDCR_DWIDTH_M)
1042                 chip->options |= NAND_BUSWIDTH_16;
1043
1044         if (nand_scan_ident(mtd, 1, def))
1045                 return -ENODEV;
1046         /* calculate addressing information */
1047         if (mtd->writesize >= 2048)
1048                 host->col_addr_cycles = 2;
1049         else
1050                 host->col_addr_cycles = 1;
1051
1052         info->oob_buff = info->data_buff + mtd->writesize;
1053         if ((mtd->size >> chip->page_shift) > 65536)
1054                 host->row_addr_cycles = 3;
1055         else
1056                 host->row_addr_cycles = 2;
1057
1058         mtd->name = mtd_names[0];
1059         return nand_scan_tail(mtd);
1060 }
1061
1062 static int alloc_nand_resource(struct platform_device *pdev)
1063 {
1064         struct pxa3xx_nand_platform_data *pdata;
1065         struct pxa3xx_nand_info *info;
1066         struct pxa3xx_nand_host *host;
1067         struct nand_chip *chip = NULL;
1068         struct mtd_info *mtd;
1069         struct resource *r;
1070         int ret, irq, cs;
1071
1072         pdata = dev_get_platdata(&pdev->dev);
1073         info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
1074                             sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1075         if (!info)
1076                 return -ENOMEM;
1077
1078         info->pdev = pdev;
1079         for (cs = 0; cs < pdata->num_cs; cs++) {
1080                 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1081                       (sizeof(*mtd) + sizeof(*host)) * cs);
1082                 chip = (struct nand_chip *)(&mtd[1]);
1083                 host = (struct pxa3xx_nand_host *)chip;
1084                 info->host[cs] = host;
1085                 host->mtd = mtd;
1086                 host->cs = cs;
1087                 host->info_data = info;
1088                 mtd->priv = host;
1089                 mtd->owner = THIS_MODULE;
1090
1091                 chip->ecc.read_page     = pxa3xx_nand_read_page_hwecc;
1092                 chip->ecc.write_page    = pxa3xx_nand_write_page_hwecc;
1093                 chip->controller        = &info->controller;
1094                 chip->waitfunc          = pxa3xx_nand_waitfunc;
1095                 chip->select_chip       = pxa3xx_nand_select_chip;
1096                 chip->cmdfunc           = pxa3xx_nand_cmdfunc;
1097                 chip->read_word         = pxa3xx_nand_read_word;
1098                 chip->read_byte         = pxa3xx_nand_read_byte;
1099                 chip->read_buf          = pxa3xx_nand_read_buf;
1100                 chip->write_buf         = pxa3xx_nand_write_buf;
1101         }
1102
1103         spin_lock_init(&chip->controller->lock);
1104         init_waitqueue_head(&chip->controller->wq);
1105         info->clk = devm_clk_get(&pdev->dev, NULL);
1106         if (IS_ERR(info->clk)) {
1107                 dev_err(&pdev->dev, "failed to get nand clock\n");
1108                 return PTR_ERR(info->clk);
1109         }
1110         ret = clk_prepare_enable(info->clk);
1111         if (ret < 0)
1112                 return ret;
1113
1114         /*
1115          * This is a dirty hack to make this driver work from devicetree
1116          * bindings. It can be removed once we have a prober DMA controller
1117          * framework for DT.
1118          */
1119         if (pdev->dev.of_node && of_machine_is_compatible("marvell,pxa3xx")) {
1120                 info->drcmr_dat = 97;
1121                 info->drcmr_cmd = 99;
1122         } else {
1123                 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1124                 if (r == NULL) {
1125                         dev_err(&pdev->dev, "no resource defined for data DMA\n");
1126                         ret = -ENXIO;
1127                         goto fail_disable_clk;
1128                 }
1129                 info->drcmr_dat = r->start;
1130
1131                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1132                 if (r == NULL) {
1133                         dev_err(&pdev->dev, "no resource defined for command DMA\n");
1134                         ret = -ENXIO;
1135                         goto fail_disable_clk;
1136                 }
1137                 info->drcmr_cmd = r->start;
1138         }
1139
1140         irq = platform_get_irq(pdev, 0);
1141         if (irq < 0) {
1142                 dev_err(&pdev->dev, "no IRQ resource defined\n");
1143                 ret = -ENXIO;
1144                 goto fail_disable_clk;
1145         }
1146
1147         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1148         info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
1149         if (IS_ERR(info->mmio_base)) {
1150                 ret = PTR_ERR(info->mmio_base);
1151                 goto fail_disable_clk;
1152         }
1153         info->mmio_phys = r->start;
1154
1155         ret = pxa3xx_nand_init_buff(info);
1156         if (ret)
1157                 goto fail_disable_clk;
1158
1159         /* initialize all interrupts to be disabled */
1160         disable_int(info, NDSR_MASK);
1161
1162         ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1163                           pdev->name, info);
1164         if (ret < 0) {
1165                 dev_err(&pdev->dev, "failed to request IRQ\n");
1166                 goto fail_free_buf;
1167         }
1168
1169         platform_set_drvdata(pdev, info);
1170
1171         return 0;
1172
1173 fail_free_buf:
1174         free_irq(irq, info);
1175         pxa3xx_nand_free_buff(info);
1176 fail_disable_clk:
1177         clk_disable_unprepare(info->clk);
1178         return ret;
1179 }
1180
1181 static int pxa3xx_nand_remove(struct platform_device *pdev)
1182 {
1183         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1184         struct pxa3xx_nand_platform_data *pdata;
1185         int irq, cs;
1186
1187         if (!info)
1188                 return 0;
1189
1190         pdata = dev_get_platdata(&pdev->dev);
1191
1192         irq = platform_get_irq(pdev, 0);
1193         if (irq >= 0)
1194                 free_irq(irq, info);
1195         pxa3xx_nand_free_buff(info);
1196
1197         clk_disable_unprepare(info->clk);
1198
1199         for (cs = 0; cs < pdata->num_cs; cs++)
1200                 nand_release(info->host[cs]->mtd);
1201         return 0;
1202 }
1203
1204 #ifdef CONFIG_OF
1205 static struct of_device_id pxa3xx_nand_dt_ids[] = {
1206         {
1207                 .compatible = "marvell,pxa3xx-nand",
1208                 .data       = (void *)PXA3XX_NAND_VARIANT_PXA,
1209         },
1210         {
1211                 .compatible = "marvell,armada370-nand",
1212                 .data       = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
1213         },
1214         {}
1215 };
1216 MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
1217
1218 static enum pxa3xx_nand_variant
1219 pxa3xx_nand_get_variant(struct platform_device *pdev)
1220 {
1221         const struct of_device_id *of_id =
1222                         of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1223         if (!of_id)
1224                 return PXA3XX_NAND_VARIANT_PXA;
1225         return (enum pxa3xx_nand_variant)of_id->data;
1226 }
1227
1228 static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1229 {
1230         struct pxa3xx_nand_platform_data *pdata;
1231         struct device_node *np = pdev->dev.of_node;
1232         const struct of_device_id *of_id =
1233                         of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1234
1235         if (!of_id)
1236                 return 0;
1237
1238         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1239         if (!pdata)
1240                 return -ENOMEM;
1241
1242         if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1243                 pdata->enable_arbiter = 1;
1244         if (of_get_property(np, "marvell,nand-keep-config", NULL))
1245                 pdata->keep_config = 1;
1246         of_property_read_u32(np, "num-cs", &pdata->num_cs);
1247
1248         pdev->dev.platform_data = pdata;
1249
1250         return 0;
1251 }
1252 #else
1253 static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1254 {
1255         return 0;
1256 }
1257 #endif
1258
1259 static int pxa3xx_nand_probe(struct platform_device *pdev)
1260 {
1261         struct pxa3xx_nand_platform_data *pdata;
1262         struct mtd_part_parser_data ppdata = {};
1263         struct pxa3xx_nand_info *info;
1264         int ret, cs, probe_success;
1265
1266         ret = pxa3xx_nand_probe_dt(pdev);
1267         if (ret)
1268                 return ret;
1269
1270         pdata = dev_get_platdata(&pdev->dev);
1271         if (!pdata) {
1272                 dev_err(&pdev->dev, "no platform data defined\n");
1273                 return -ENODEV;
1274         }
1275
1276         ret = alloc_nand_resource(pdev);
1277         if (ret) {
1278                 dev_err(&pdev->dev, "alloc nand resource failed\n");
1279                 return ret;
1280         }
1281
1282         info = platform_get_drvdata(pdev);
1283         info->variant = pxa3xx_nand_get_variant(pdev);
1284         probe_success = 0;
1285         for (cs = 0; cs < pdata->num_cs; cs++) {
1286                 info->cs = cs;
1287                 ret = pxa3xx_nand_scan(info->host[cs]->mtd);
1288                 if (ret) {
1289                         dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1290                                 cs);
1291                         continue;
1292                 }
1293
1294                 ppdata.of_node = pdev->dev.of_node;
1295                 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
1296                                                 &ppdata, pdata->parts[cs],
1297                                                 pdata->nr_parts[cs]);
1298                 if (!ret)
1299                         probe_success = 1;
1300         }
1301
1302         if (!probe_success) {
1303                 pxa3xx_nand_remove(pdev);
1304                 return -ENODEV;
1305         }
1306
1307         return 0;
1308 }
1309
1310 #ifdef CONFIG_PM
1311 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1312 {
1313         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1314         struct pxa3xx_nand_platform_data *pdata;
1315         struct mtd_info *mtd;
1316         int cs;
1317
1318         pdata = dev_get_platdata(&pdev->dev);
1319         if (info->state) {
1320                 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1321                 return -EAGAIN;
1322         }
1323
1324         for (cs = 0; cs < pdata->num_cs; cs++) {
1325                 mtd = info->host[cs]->mtd;
1326                 mtd_suspend(mtd);
1327         }
1328
1329         return 0;
1330 }
1331
1332 static int pxa3xx_nand_resume(struct platform_device *pdev)
1333 {
1334         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1335         struct pxa3xx_nand_platform_data *pdata;
1336         struct mtd_info *mtd;
1337         int cs;
1338
1339         pdata = dev_get_platdata(&pdev->dev);
1340         /* We don't want to handle interrupt without calling mtd routine */
1341         disable_int(info, NDCR_INT_MASK);
1342
1343         /*
1344          * Directly set the chip select to a invalid value,
1345          * then the driver would reset the timing according
1346          * to current chip select at the beginning of cmdfunc
1347          */
1348         info->cs = 0xff;
1349
1350         /*
1351          * As the spec says, the NDSR would be updated to 0x1800 when
1352          * doing the nand_clk disable/enable.
1353          * To prevent it damaging state machine of the driver, clear
1354          * all status before resume
1355          */
1356         nand_writel(info, NDSR, NDSR_MASK);
1357         for (cs = 0; cs < pdata->num_cs; cs++) {
1358                 mtd = info->host[cs]->mtd;
1359                 mtd_resume(mtd);
1360         }
1361
1362         return 0;
1363 }
1364 #else
1365 #define pxa3xx_nand_suspend     NULL
1366 #define pxa3xx_nand_resume      NULL
1367 #endif
1368
1369 static struct platform_driver pxa3xx_nand_driver = {
1370         .driver = {
1371                 .name   = "pxa3xx-nand",
1372                 .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
1373         },
1374         .probe          = pxa3xx_nand_probe,
1375         .remove         = pxa3xx_nand_remove,
1376         .suspend        = pxa3xx_nand_suspend,
1377         .resume         = pxa3xx_nand_resume,
1378 };
1379
1380 module_platform_driver(pxa3xx_nand_driver);
1381
1382 MODULE_LICENSE("GPL");
1383 MODULE_DESCRIPTION("PXA3xx NAND controller driver");