Pileus Git - ~andy/linux/blob - drivers/mmc/host/sh_mmcif.c

   1 /*
   2  * MMCIF eMMC driver.
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  *
  12  * TODO
  13  *  1. DMA
  14  *  2. Power management
  15  *  3. Handle MMC errors better
  16  *
  17  */
  18
  19 #include <linux/bitops.h>
  20 #include <linux/clk.h>
  21 #include <linux/completion.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/dmaengine.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/mmc/core.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/sdio.h>
  30 #include <linux/mmc/sh_mmcif.h>
  31 #include <linux/pagemap.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/module.h>
  36
  37 #define DRIVER_NAME     "sh_mmcif"
  38 #define DRIVER_VERSION  "2010-04-28"
  39
  40 /* CE_CMD_SET */
  41 #define CMD_MASK                0x3f000000
  42 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  43 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  44 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
  45 #define CMD_SET_RBSY            (1 << 21) /* R1b */
  46 #define CMD_SET_CCSEN           (1 << 20)
  47 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
  48 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
  49 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
  50 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
  51 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
  52 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
  53 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
  54 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
  55 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
  56 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  57 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
  58 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
  59 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
  60 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
  61 #define CMD_SET_CCSH            (1 << 5)
  62 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
  63 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
  64 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
  65
  66 /* CE_CMD_CTRL */
  67 #define CMD_CTRL_BREAK          (1 << 0)
  68
  69 /* CE_BLOCK_SET */
  70 #define BLOCK_SIZE_MASK         0x0000ffff
  71
  72 /* CE_INT */
  73 #define INT_CCSDE               (1 << 29)
  74 #define INT_CMD12DRE            (1 << 26)
  75 #define INT_CMD12RBE            (1 << 25)
  76 #define INT_CMD12CRE            (1 << 24)
  77 #define INT_DTRANE              (1 << 23)
  78 #define INT_BUFRE               (1 << 22)
  79 #define INT_BUFWEN              (1 << 21)
  80 #define INT_BUFREN              (1 << 20)
  81 #define INT_CCSRCV              (1 << 19)
  82 #define INT_RBSYE               (1 << 17)
  83 #define INT_CRSPE               (1 << 16)
  84 #define INT_CMDVIO              (1 << 15)
  85 #define INT_BUFVIO              (1 << 14)
  86 #define INT_WDATERR             (1 << 11)
  87 #define INT_RDATERR             (1 << 10)
  88 #define INT_RIDXERR             (1 << 9)
  89 #define INT_RSPERR              (1 << 8)
  90 #define INT_CCSTO               (1 << 5)
  91 #define INT_CRCSTO              (1 << 4)
  92 #define INT_WDATTO              (1 << 3)
  93 #define INT_RDATTO              (1 << 2)
  94 #define INT_RBSYTO              (1 << 1)
  95 #define INT_RSPTO               (1 << 0)
  96 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
  97                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
  98                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
  99                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 100
 101 /* CE_INT_MASK */
 102 #define MASK_ALL                0x00000000
 103 #define MASK_MCCSDE             (1 << 29)
 104 #define MASK_MCMD12DRE          (1 << 26)
 105 #define MASK_MCMD12RBE          (1 << 25)
 106 #define MASK_MCMD12CRE          (1 << 24)
 107 #define MASK_MDTRANE            (1 << 23)
 108 #define MASK_MBUFRE             (1 << 22)
 109 #define MASK_MBUFWEN            (1 << 21)
 110 #define MASK_MBUFREN            (1 << 20)
 111 #define MASK_MCCSRCV            (1 << 19)
 112 #define MASK_MRBSYE             (1 << 17)
 113 #define MASK_MCRSPE             (1 << 16)
 114 #define MASK_MCMDVIO            (1 << 15)
 115 #define MASK_MBUFVIO            (1 << 14)
 116 #define MASK_MWDATERR           (1 << 11)
 117 #define MASK_MRDATERR           (1 << 10)
 118 #define MASK_MRIDXERR           (1 << 9)
 119 #define MASK_MRSPERR            (1 << 8)
 120 #define MASK_MCCSTO             (1 << 5)
 121 #define MASK_MCRCSTO            (1 << 4)
 122 #define MASK_MWDATTO            (1 << 3)
 123 #define MASK_MRDATTO            (1 << 2)
 124 #define MASK_MRBSYTO            (1 << 1)
 125 #define MASK_MRSPTO             (1 << 0)
 126
 127 #define MASK_START_CMD          (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
 128                                  MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
 129                                  MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
 130                                  MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
 131
 132 /* CE_HOST_STS1 */
 133 #define STS1_CMDSEQ             (1 << 31)
 134
 135 /* CE_HOST_STS2 */
 136 #define STS2_CRCSTE             (1 << 31)
 137 #define STS2_CRC16E             (1 << 30)
 138 #define STS2_AC12CRCE           (1 << 29)
 139 #define STS2_RSPCRC7E           (1 << 28)
 140 #define STS2_CRCSTEBE           (1 << 27)
 141 #define STS2_RDATEBE            (1 << 26)
 142 #define STS2_AC12REBE           (1 << 25)
 143 #define STS2_RSPEBE             (1 << 24)
 144 #define STS2_AC12IDXE           (1 << 23)
 145 #define STS2_RSPIDXE            (1 << 22)
 146 #define STS2_CCSTO              (1 << 15)
 147 #define STS2_RDATTO             (1 << 14)
 148 #define STS2_DATBSYTO           (1 << 13)
 149 #define STS2_CRCSTTO            (1 << 12)
 150 #define STS2_AC12BSYTO          (1 << 11)
 151 #define STS2_RSPBSYTO           (1 << 10)
 152 #define STS2_AC12RSPTO          (1 << 9)
 153 #define STS2_RSPTO              (1 << 8)
 154 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 155                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 156 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 157                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 158                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 159                                  STS2_AC12RSPTO | STS2_RSPTO)
 160
 161 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
 162 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
 163 #define CLKDEV_INIT             400000   /* 400 KHz */
 164
 165 enum mmcif_state {
 166         STATE_IDLE,
 167         STATE_REQUEST,
 168         STATE_IOS,
 169 };
 170
 171 struct sh_mmcif_host {
 172         struct mmc_host *mmc;
 173         struct mmc_data *data;
 174         struct platform_device *pd;
 175         struct sh_dmae_slave dma_slave_tx;
 176         struct sh_dmae_slave dma_slave_rx;
 177         struct clk *hclk;
 178         unsigned int clk;
 179         int bus_width;
 180         bool sd_error;
 181         long timeout;
 182         void __iomem *addr;
 183         struct completion intr_wait;
 184         spinlock_t lock;                /* protect sh_mmcif_host::state */
 185         enum mmcif_state state;
 186         bool power;
 187         bool card_present;
 188
 189         /* DMA support */
 190         struct dma_chan         *chan_rx;
 191         struct dma_chan         *chan_tx;
 192         struct completion       dma_complete;
 193         bool                    dma_active;
 194 };
 195
 196 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
 197                                         unsigned int reg, u32 val)
 198 {
 199         writel(val | readl(host->addr + reg), host->addr + reg);
 200 }
 201
 202 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
 203                                         unsigned int reg, u32 val)
 204 {
 205         writel(~val & readl(host->addr + reg), host->addr + reg);
 206 }
 207
 208 static void mmcif_dma_complete(void *arg)
 209 {
 210         struct sh_mmcif_host *host = arg;
 211         dev_dbg(&host->pd->dev, "Command completed\n");
 212
 213         if (WARN(!host->data, "%s: NULL data in DMA completion!\n",
 214                  dev_name(&host->pd->dev)))
 215                 return;
 216
 217         if (host->data->flags & MMC_DATA_READ)
 218                 dma_unmap_sg(host->chan_rx->device->dev,
 219                              host->data->sg, host->data->sg_len,
 220                              DMA_FROM_DEVICE);
 221         else
 222                 dma_unmap_sg(host->chan_tx->device->dev,
 223                              host->data->sg, host->data->sg_len,
 224                              DMA_TO_DEVICE);
 225
 226         complete(&host->dma_complete);
 227 }
 228
 229 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
 230 {
 231         struct scatterlist *sg = host->data->sg;
 232         struct dma_async_tx_descriptor *desc = NULL;
 233         struct dma_chan *chan = host->chan_rx;
 234         dma_cookie_t cookie = -EINVAL;
 235         int ret;
 236
 237         ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
 238                          DMA_FROM_DEVICE);
 239         if (ret > 0) {
 240                 host->dma_active = true;
 241                 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
 242                         DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 243         }
 244
 245         if (desc) {
 246                 desc->callback = mmcif_dma_complete;
 247                 desc->callback_param = host;
 248                 cookie = dmaengine_submit(desc);
 249                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
 250                 dma_async_issue_pending(chan);
 251         }
 252         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 253                 __func__, host->data->sg_len, ret, cookie);
 254
 255         if (!desc) {
 256                 /* DMA failed, fall back to PIO */
 257                 if (ret >= 0)
 258                         ret = -EIO;
 259                 host->chan_rx = NULL;
 260                 host->dma_active = false;
 261                 dma_release_channel(chan);
 262                 /* Free the Tx channel too */
 263                 chan = host->chan_tx;
 264                 if (chan) {
 265                         host->chan_tx = NULL;
 266                         dma_release_channel(chan);
 267                 }
 268                 dev_warn(&host->pd->dev,
 269                          "DMA failed: %d, falling back to PIO\n", ret);
 270                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 271         }
 272
 273         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
 274                 desc, cookie, host->data->sg_len);
 275 }
 276
 277 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
 278 {
 279         struct scatterlist *sg = host->data->sg;
 280         struct dma_async_tx_descriptor *desc = NULL;
 281         struct dma_chan *chan = host->chan_tx;
 282         dma_cookie_t cookie = -EINVAL;
 283         int ret;
 284
 285         ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
 286                          DMA_TO_DEVICE);
 287         if (ret > 0) {
 288                 host->dma_active = true;
 289                 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
 290                         DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 291         }
 292
 293         if (desc) {
 294                 desc->callback = mmcif_dma_complete;
 295                 desc->callback_param = host;
 296                 cookie = dmaengine_submit(desc);
 297                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
 298                 dma_async_issue_pending(chan);
 299         }
 300         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 301                 __func__, host->data->sg_len, ret, cookie);
 302
 303         if (!desc) {
 304                 /* DMA failed, fall back to PIO */
 305                 if (ret >= 0)
 306                         ret = -EIO;
 307                 host->chan_tx = NULL;
 308                 host->dma_active = false;
 309                 dma_release_channel(chan);
 310                 /* Free the Rx channel too */
 311                 chan = host->chan_rx;
 312                 if (chan) {
 313                         host->chan_rx = NULL;
 314                         dma_release_channel(chan);
 315                 }
 316                 dev_warn(&host->pd->dev,
 317                          "DMA failed: %d, falling back to PIO\n", ret);
 318                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 319         }
 320
 321         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
 322                 desc, cookie);
 323 }
 324
 325 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
 326 {
 327         dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
 328         chan->private = arg;
 329         return true;
 330 }
 331
 332 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
 333                                  struct sh_mmcif_plat_data *pdata)
 334 {
 335         struct sh_dmae_slave *tx, *rx;
 336         host->dma_active = false;
 337
 338         /* We can only either use DMA for both Tx and Rx or not use it at all */
 339         if (pdata->dma) {
 340                 dev_warn(&host->pd->dev,
 341                          "Update your platform to use embedded DMA slave IDs\n");
 342                 tx = &pdata->dma->chan_priv_tx;
 343                 rx = &pdata->dma->chan_priv_rx;
 344         } else {
 345                 tx = &host->dma_slave_tx;
 346                 tx->slave_id = pdata->slave_id_tx;
 347                 rx = &host->dma_slave_rx;
 348                 rx->slave_id = pdata->slave_id_rx;
 349         }
 350         if (tx->slave_id > 0 && rx->slave_id > 0) {
 351                 dma_cap_mask_t mask;
 352
 353                 dma_cap_zero(mask);
 354                 dma_cap_set(DMA_SLAVE, mask);
 355
 356                 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx);
 357                 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
 358                         host->chan_tx);
 359
 360                 if (!host->chan_tx)
 361                         return;
 362
 363                 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx);
 364                 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
 365                         host->chan_rx);
 366
 367                 if (!host->chan_rx) {
 368                         dma_release_channel(host->chan_tx);
 369                         host->chan_tx = NULL;
 370                         return;
 371                 }
 372
 373                 init_completion(&host->dma_complete);
 374         }
 375 }
 376
 377 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
 378 {
 379         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 380         /* Descriptors are freed automatically */
 381         if (host->chan_tx) {
 382                 struct dma_chan *chan = host->chan_tx;
 383                 host->chan_tx = NULL;
 384                 dma_release_channel(chan);
 385         }
 386         if (host->chan_rx) {
 387                 struct dma_chan *chan = host->chan_rx;
 388                 host->chan_rx = NULL;
 389                 dma_release_channel(chan);
 390         }
 391
 392         host->dma_active = false;
 393 }
 394
 395 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 396 {
 397         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 398
 399         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 400         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
 401
 402         if (!clk)
 403                 return;
 404         if (p->sup_pclk && clk == host->clk)
 405                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
 406         else
 407                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
 408                                 ((fls(host->clk / clk) - 1) << 16));
 409
 410         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 411 }
 412
 413 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 414 {
 415         u32 tmp;
 416
 417         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
 418
 419         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
 420         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
 421         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
 422                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 423         /* byte swap on */
 424         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 425 }
 426
 427 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
 428 {
 429         u32 state1, state2;
 430         int ret, timeout;
 431
 432         host->sd_error = false;
 433
 434         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
 435         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
 436         dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
 437         dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
 438
 439         if (state1 & STS1_CMDSEQ) {
 440                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
 441                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
 442                 for (timeout = 10000000; timeout; timeout--) {
 443                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
 444                               & STS1_CMDSEQ))
 445                                 break;
 446                         mdelay(1);
 447                 }
 448                 if (!timeout) {
 449                         dev_err(&host->pd->dev,
 450                                 "Forced end of command sequence timeout err\n");
 451                         return -EIO;
 452                 }
 453                 sh_mmcif_sync_reset(host);
 454                 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
 455                 return -EIO;
 456         }
 457
 458         if (state2 & STS2_CRC_ERR) {
 459                 dev_dbg(&host->pd->dev, ": CRC error\n");
 460                 ret = -EIO;
 461         } else if (state2 & STS2_TIMEOUT_ERR) {
 462                 dev_dbg(&host->pd->dev, ": Timeout\n");
 463                 ret = -ETIMEDOUT;
 464         } else {
 465                 dev_dbg(&host->pd->dev, ": End/Index error\n");
 466                 ret = -EIO;
 467         }
 468         return ret;
 469 }
 470
 471 static int sh_mmcif_single_read(struct sh_mmcif_host *host,
 472                                         struct mmc_request *mrq)
 473 {
 474         struct mmc_data *data = mrq->data;
 475         long time;
 476         u32 blocksize, i, *p = sg_virt(data->sg);
 477
 478         /* buf read enable */
 479         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 480         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 481                         host->timeout);
 482         if (time <= 0 || host->sd_error)
 483                 return sh_mmcif_error_manage(host);
 484
 485         blocksize = (BLOCK_SIZE_MASK &
 486                         sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
 487         for (i = 0; i < blocksize / 4; i++)
 488                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 489
 490         /* buffer read end */
 491         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 492         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 493                         host->timeout);
 494         if (time <= 0 || host->sd_error)
 495                 return sh_mmcif_error_manage(host);
 496
 497         return 0;
 498 }
 499
 500 static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
 501                                         struct mmc_request *mrq)
 502 {
 503         struct mmc_data *data = mrq->data;
 504         long time;
 505         u32 blocksize, i, j, sec, *p;
 506
 507         blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
 508                                                      MMCIF_CE_BLOCK_SET);
 509         for (j = 0; j < data->sg_len; j++) {
 510                 p = sg_virt(data->sg);
 511                 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
 512                         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 513                         /* buf read enable */
 514                         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 515                                 host->timeout);
 516
 517                         if (time <= 0 || host->sd_error)
 518                                 return sh_mmcif_error_manage(host);
 519
 520                         for (i = 0; i < blocksize / 4; i++)
 521                                 *p++ = sh_mmcif_readl(host->addr,
 522                                                       MMCIF_CE_DATA);
 523                 }
 524                 if (j < data->sg_len - 1)
 525                         data->sg++;
 526         }
 527         return 0;
 528 }
 529
 530 static int sh_mmcif_single_write(struct sh_mmcif_host *host,
 531                                         struct mmc_request *mrq)
 532 {
 533         struct mmc_data *data = mrq->data;
 534         long time;
 535         u32 blocksize, i, *p = sg_virt(data->sg);
 536
 537         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 538
 539         /* buf write enable */
 540         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 541                         host->timeout);
 542         if (time <= 0 || host->sd_error)
 543                 return sh_mmcif_error_manage(host);
 544
 545         blocksize = (BLOCK_SIZE_MASK &
 546                         sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
 547         for (i = 0; i < blocksize / 4; i++)
 548                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 549
 550         /* buffer write end */
 551         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 552
 553         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 554                         host->timeout);
 555         if (time <= 0 || host->sd_error)
 556                 return sh_mmcif_error_manage(host);
 557
 558         return 0;
 559 }
 560
 561 static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
 562                                                 struct mmc_request *mrq)
 563 {
 564         struct mmc_data *data = mrq->data;
 565         long time;
 566         u32 i, sec, j, blocksize, *p;
 567
 568         blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
 569                                                      MMCIF_CE_BLOCK_SET);
 570
 571         for (j = 0; j < data->sg_len; j++) {
 572                 p = sg_virt(data->sg);
 573                 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
 574                         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 575                         /* buf write enable*/
 576                         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 577                                 host->timeout);
 578
 579                         if (time <= 0 || host->sd_error)
 580                                 return sh_mmcif_error_manage(host);
 581
 582                         for (i = 0; i < blocksize / 4; i++)
 583                                 sh_mmcif_writel(host->addr,
 584                                                 MMCIF_CE_DATA, *p++);
 585                 }
 586                 if (j < data->sg_len - 1)
 587                         data->sg++;
 588         }
 589         return 0;
 590 }
 591
 592 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
 593                                                 struct mmc_command *cmd)
 594 {
 595         if (cmd->flags & MMC_RSP_136) {
 596                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
 597                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
 598                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
 599                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 600         } else
 601                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 602 }
 603
 604 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
 605                                                 struct mmc_command *cmd)
 606 {
 607         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
 608 }
 609
 610 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
 611                 struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
 612 {
 613         u32 tmp = 0;
 614
 615         /* Response Type check */
 616         switch (mmc_resp_type(cmd)) {
 617         case MMC_RSP_NONE:
 618                 tmp |= CMD_SET_RTYP_NO;
 619                 break;
 620         case MMC_RSP_R1:
 621         case MMC_RSP_R1B:
 622         case MMC_RSP_R3:
 623                 tmp |= CMD_SET_RTYP_6B;
 624                 break;
 625         case MMC_RSP_R2:
 626                 tmp |= CMD_SET_RTYP_17B;
 627                 break;
 628         default:
 629                 dev_err(&host->pd->dev, "Unsupported response type.\n");
 630                 break;
 631         }
 632         switch (opc) {
 633         /* RBSY */
 634         case MMC_SWITCH:
 635         case MMC_STOP_TRANSMISSION:
 636         case MMC_SET_WRITE_PROT:
 637         case MMC_CLR_WRITE_PROT:
 638         case MMC_ERASE:
 639         case MMC_GEN_CMD:
 640                 tmp |= CMD_SET_RBSY;
 641                 break;
 642         }
 643         /* WDAT / DATW */
 644         if (host->data) {
 645                 tmp |= CMD_SET_WDAT;
 646                 switch (host->bus_width) {
 647                 case MMC_BUS_WIDTH_1:
 648                         tmp |= CMD_SET_DATW_1;
 649                         break;
 650                 case MMC_BUS_WIDTH_4:
 651                         tmp |= CMD_SET_DATW_4;
 652                         break;
 653                 case MMC_BUS_WIDTH_8:
 654                         tmp |= CMD_SET_DATW_8;
 655                         break;
 656                 default:
 657                         dev_err(&host->pd->dev, "Unsupported bus width.\n");
 658                         break;
 659                 }
 660         }
 661         /* DWEN */
 662         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
 663                 tmp |= CMD_SET_DWEN;
 664         /* CMLTE/CMD12EN */
 665         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
 666                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
 667                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
 668                                         mrq->data->blocks << 16);
 669         }
 670         /* RIDXC[1:0] check bits */
 671         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
 672             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 673                 tmp |= CMD_SET_RIDXC_BITS;
 674         /* RCRC7C[1:0] check bits */
 675         if (opc == MMC_SEND_OP_COND)
 676                 tmp |= CMD_SET_CRC7C_BITS;
 677         /* RCRC7C[1:0] internal CRC7 */
 678         if (opc == MMC_ALL_SEND_CID ||
 679                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 680                 tmp |= CMD_SET_CRC7C_INTERNAL;
 681
 682         return opc = ((opc << 24) | tmp);
 683 }
 684
 685 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
 686                                 struct mmc_request *mrq, u32 opc)
 687 {
 688         switch (opc) {
 689         case MMC_READ_MULTIPLE_BLOCK:
 690                 return sh_mmcif_multi_read(host, mrq);
 691         case MMC_WRITE_MULTIPLE_BLOCK:
 692                 return sh_mmcif_multi_write(host, mrq);
 693         case MMC_WRITE_BLOCK:
 694                 return sh_mmcif_single_write(host, mrq);
 695         case MMC_READ_SINGLE_BLOCK:
 696         case MMC_SEND_EXT_CSD:
 697                 return sh_mmcif_single_read(host, mrq);
 698         default:
 699                 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
 700                 return -EINVAL;
 701         }
 702 }
 703
 704 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 705                                struct mmc_request *mrq)
 706 {
 707         struct mmc_command *cmd = mrq->cmd;
 708         long time;
 709         int ret = 0;
 710         u32 mask, opc = cmd->opcode;
 711
 712         switch (opc) {
 713         /* response busy check */
 714         case MMC_SWITCH:
 715         case MMC_STOP_TRANSMISSION:
 716         case MMC_SET_WRITE_PROT:
 717         case MMC_CLR_WRITE_PROT:
 718         case MMC_ERASE:
 719         case MMC_GEN_CMD:
 720                 mask = MASK_START_CMD | MASK_MRBSYE;
 721                 break;
 722         default:
 723                 mask = MASK_START_CMD | MASK_MCRSPE;
 724                 break;
 725         }
 726
 727         if (host->data) {
 728                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
 729                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
 730                                 mrq->data->blksz);
 731         }
 732         opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
 733
 734         sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
 735         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
 736         /* set arg */
 737         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
 738         /* set cmd */
 739         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 740
 741         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 742                 host->timeout);
 743         if (time <= 0) {
 744                 cmd->error = sh_mmcif_error_manage(host);
 745                 return;
 746         }
 747         if (host->sd_error) {
 748                 switch (cmd->opcode) {
 749                 case MMC_ALL_SEND_CID:
 750                 case MMC_SELECT_CARD:
 751                 case MMC_APP_CMD:
 752                         cmd->error = -ETIMEDOUT;
 753                         break;
 754                 default:
 755                         dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n",
 756                                         cmd->opcode);
 757                         cmd->error = sh_mmcif_error_manage(host);
 758                         break;
 759                 }
 760                 host->sd_error = false;
 761                 return;
 762         }
 763         if (!(cmd->flags & MMC_RSP_PRESENT)) {
 764                 cmd->error = 0;
 765                 return;
 766         }
 767         sh_mmcif_get_response(host, cmd);
 768         if (host->data) {
 769                 if (!host->dma_active) {
 770                         ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
 771                 } else {
 772                         long time =
 773                                 wait_for_completion_interruptible_timeout(&host->dma_complete,
 774                                                                           host->timeout);
 775                         if (!time)
 776                                 ret = -ETIMEDOUT;
 777                         else if (time < 0)
 778                                 ret = time;
 779                         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
 780                                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 781                         host->dma_active = false;
 782                 }
 783                 if (ret < 0)
 784                         mrq->data->bytes_xfered = 0;
 785                 else
 786                         mrq->data->bytes_xfered =
 787                                 mrq->data->blocks * mrq->data->blksz;
 788         }
 789         cmd->error = ret;
 790 }
 791
 792 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
 793                               struct mmc_request *mrq)
 794 {
 795         struct mmc_command *cmd = mrq->stop;
 796         long time;
 797
 798         if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
 799                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 800         else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
 801                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 802         else {
 803                 dev_err(&host->pd->dev, "unsupported stop cmd\n");
 804                 cmd->error = sh_mmcif_error_manage(host);
 805                 return;
 806         }
 807
 808         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 809                         host->timeout);
 810         if (time <= 0 || host->sd_error) {
 811                 cmd->error = sh_mmcif_error_manage(host);
 812                 return;
 813         }
 814         sh_mmcif_get_cmd12response(host, cmd);
 815         cmd->error = 0;
 816 }
 817
 818 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
 819 {
 820         struct sh_mmcif_host *host = mmc_priv(mmc);
 821         unsigned long flags;
 822
 823         spin_lock_irqsave(&host->lock, flags);
 824         if (host->state != STATE_IDLE) {
 825                 spin_unlock_irqrestore(&host->lock, flags);
 826                 mrq->cmd->error = -EAGAIN;
 827                 mmc_request_done(mmc, mrq);
 828                 return;
 829         }
 830
 831         host->state = STATE_REQUEST;
 832         spin_unlock_irqrestore(&host->lock, flags);
 833
 834         switch (mrq->cmd->opcode) {
 835         /* MMCIF does not support SD/SDIO command */
 836         case SD_IO_SEND_OP_COND:
 837         case MMC_APP_CMD:
 838                 host->state = STATE_IDLE;
 839                 mrq->cmd->error = -ETIMEDOUT;
 840                 mmc_request_done(mmc, mrq);
 841                 return;
 842         case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
 843                 if (!mrq->data) {
 844                         /* send_if_cond cmd (not support) */
 845                         host->state = STATE_IDLE;
 846                         mrq->cmd->error = -ETIMEDOUT;
 847                         mmc_request_done(mmc, mrq);
 848                         return;
 849                 }
 850                 break;
 851         default:
 852                 break;
 853         }
 854         host->data = mrq->data;
 855         if (mrq->data) {
 856                 if (mrq->data->flags & MMC_DATA_READ) {
 857                         if (host->chan_rx)
 858                                 sh_mmcif_start_dma_rx(host);
 859                 } else {
 860                         if (host->chan_tx)
 861                                 sh_mmcif_start_dma_tx(host);
 862                 }
 863         }
 864         sh_mmcif_start_cmd(host, mrq);
 865         host->data = NULL;
 866
 867         if (!mrq->cmd->error && mrq->stop)
 868                 sh_mmcif_stop_cmd(host, mrq);
 869         host->state = STATE_IDLE;
 870         mmc_request_done(mmc, mrq);
 871 }
 872
 873 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 874 {
 875         struct sh_mmcif_host *host = mmc_priv(mmc);
 876         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 877         unsigned long flags;
 878
 879         spin_lock_irqsave(&host->lock, flags);
 880         if (host->state != STATE_IDLE) {
 881                 spin_unlock_irqrestore(&host->lock, flags);
 882                 return;
 883         }
 884
 885         host->state = STATE_IOS;
 886         spin_unlock_irqrestore(&host->lock, flags);
 887
 888         if (ios->power_mode == MMC_POWER_UP) {
 889                 if (!host->card_present) {
 890                         /* See if we also get DMA */
 891                         sh_mmcif_request_dma(host, host->pd->dev.platform_data);
 892                         host->card_present = true;
 893                 }
 894         } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
 895                 /* clock stop */
 896                 sh_mmcif_clock_control(host, 0);
 897                 if (ios->power_mode == MMC_POWER_OFF) {
 898                         if (host->card_present) {
 899                                 sh_mmcif_release_dma(host);
 900                                 host->card_present = false;
 901                         }
 902                 }
 903                 if (host->power) {
 904                         pm_runtime_put(&host->pd->dev);
 905                         host->power = false;
 906                         if (p->down_pwr && ios->power_mode == MMC_POWER_OFF)
 907                                 p->down_pwr(host->pd);
 908                 }
 909                 host->state = STATE_IDLE;
 910                 return;
 911         }
 912
 913         if (ios->clock) {
 914                 if (!host->power) {
 915                         if (p->set_pwr)
 916                                 p->set_pwr(host->pd, ios->power_mode);
 917                         pm_runtime_get_sync(&host->pd->dev);
 918                         host->power = true;
 919                         sh_mmcif_sync_reset(host);
 920                 }
 921                 sh_mmcif_clock_control(host, ios->clock);
 922         }
 923
 924         host->bus_width = ios->bus_width;
 925         host->state = STATE_IDLE;
 926 }
 927
 928 static int sh_mmcif_get_cd(struct mmc_host *mmc)
 929 {
 930         struct sh_mmcif_host *host = mmc_priv(mmc);
 931         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 932
 933         if (!p->get_cd)
 934                 return -ENOSYS;
 935         else
 936                 return p->get_cd(host->pd);
 937 }
 938
 939 static struct mmc_host_ops sh_mmcif_ops = {
 940         .request        = sh_mmcif_request,
 941         .set_ios        = sh_mmcif_set_ios,
 942         .get_cd         = sh_mmcif_get_cd,
 943 };
 944
 945 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
 946 {
 947         struct sh_mmcif_host *host = dev_id;
 948         u32 state;
 949         int err = 0;
 950
 951         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
 952
 953         if (state & INT_ERR_STS) {
 954                 /* error interrupts - process first */
 955                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
 956                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
 957                 err = 1;
 958         } else if (state & INT_RBSYE) {
 959                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
 960                                 ~(INT_RBSYE | INT_CRSPE));
 961                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
 962         } else if (state & INT_CRSPE) {
 963                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
 964                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
 965         } else if (state & INT_BUFREN) {
 966                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
 967                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 968         } else if (state & INT_BUFWEN) {
 969                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
 970                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 971         } else if (state & INT_CMD12DRE) {
 972                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
 973                         ~(INT_CMD12DRE | INT_CMD12RBE |
 974                           INT_CMD12CRE | INT_BUFRE));
 975                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 976         } else if (state & INT_BUFRE) {
 977                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
 978                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 979         } else if (state & INT_DTRANE) {
 980                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
 981                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 982         } else if (state & INT_CMD12RBE) {
 983                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
 984                                 ~(INT_CMD12RBE | INT_CMD12CRE));
 985                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 986         } else {
 987                 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
 988                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
 989                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
 990                 err = 1;
 991         }
 992         if (err) {
 993                 host->sd_error = true;
 994                 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
 995         }
 996         if (state & ~(INT_CMD12RBE | INT_CMD12CRE))
 997                 complete(&host->intr_wait);
 998         else
 999                 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1000
1001         return IRQ_HANDLED;
1002 }
1003
1004 static int __devinit sh_mmcif_probe(struct platform_device *pdev)
1005 {
1006         int ret = 0, irq[2];
1007         struct mmc_host *mmc;
1008         struct sh_mmcif_host *host;
1009         struct sh_mmcif_plat_data *pd;
1010         struct resource *res;
1011         void __iomem *reg;
1012         char clk_name[8];
1013
1014         irq[0] = platform_get_irq(pdev, 0);
1015         irq[1] = platform_get_irq(pdev, 1);
1016         if (irq[0] < 0 || irq[1] < 0) {
1017                 dev_err(&pdev->dev, "Get irq error\n");
1018                 return -ENXIO;
1019         }
1020         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1021         if (!res) {
1022                 dev_err(&pdev->dev, "platform_get_resource error.\n");
1023                 return -ENXIO;
1024         }
1025         reg = ioremap(res->start, resource_size(res));
1026         if (!reg) {
1027                 dev_err(&pdev->dev, "ioremap error.\n");
1028                 return -ENOMEM;
1029         }
1030         pd = pdev->dev.platform_data;
1031         if (!pd) {
1032                 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
1033                 ret = -ENXIO;
1034                 goto clean_up;
1035         }
1036         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1037         if (!mmc) {
1038                 ret = -ENOMEM;
1039                 goto clean_up;
1040         }
1041         host            = mmc_priv(mmc);
1042         host->mmc       = mmc;
1043         host->addr      = reg;
1044         host->timeout   = 1000;
1045
1046         snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1047         host->hclk = clk_get(&pdev->dev, clk_name);
1048         if (IS_ERR(host->hclk)) {
1049                 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
1050                 ret = PTR_ERR(host->hclk);
1051                 goto clean_up1;
1052         }
1053         clk_enable(host->hclk);
1054         host->clk = clk_get_rate(host->hclk);
1055         host->pd = pdev;
1056
1057         init_completion(&host->intr_wait);
1058         spin_lock_init(&host->lock);
1059
1060         mmc->ops = &sh_mmcif_ops;
1061         mmc->f_max = host->clk;
1062         /* close to 400KHz */
1063         if (mmc->f_max < 51200000)
1064                 mmc->f_min = mmc->f_max / 128;
1065         else if (mmc->f_max < 102400000)
1066                 mmc->f_min = mmc->f_max / 256;
1067         else
1068                 mmc->f_min = mmc->f_max / 512;
1069         if (pd->ocr)
1070                 mmc->ocr_avail = pd->ocr;
1071         mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1072         if (pd->caps)
1073                 mmc->caps |= pd->caps;
1074         mmc->max_segs = 32;
1075         mmc->max_blk_size = 512;
1076         mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1077         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1078         mmc->max_seg_size = mmc->max_req_size;
1079
1080         sh_mmcif_sync_reset(host);
1081         platform_set_drvdata(pdev, host);
1082
1083         pm_runtime_enable(&pdev->dev);
1084         host->power = false;
1085
1086         ret = pm_runtime_resume(&pdev->dev);
1087         if (ret < 0)
1088                 goto clean_up2;
1089
1090         mmc_add_host(mmc);
1091
1092         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1093
1094         ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
1095         if (ret) {
1096                 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
1097                 goto clean_up3;
1098         }
1099         ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
1100         if (ret) {
1101                 free_irq(irq[0], host);
1102                 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1103                 goto clean_up3;
1104         }
1105
1106         mmc_detect_change(host->mmc, 0);
1107
1108         dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1109         dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1110                 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1111         return ret;
1112
1113 clean_up3:
1114         mmc_remove_host(mmc);
1115         pm_runtime_suspend(&pdev->dev);
1116 clean_up2:
1117         pm_runtime_disable(&pdev->dev);
1118         clk_disable(host->hclk);
1119 clean_up1:
1120         mmc_free_host(mmc);
1121 clean_up:
1122         if (reg)
1123                 iounmap(reg);
1124         return ret;
1125 }
1126
1127 static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1128 {
1129         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1130         int irq[2];
1131
1132         pm_runtime_get_sync(&pdev->dev);
1133
1134         mmc_remove_host(host->mmc);
1135         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1136
1137         if (host->addr)
1138                 iounmap(host->addr);
1139
1140         irq[0] = platform_get_irq(pdev, 0);
1141         irq[1] = platform_get_irq(pdev, 1);
1142
1143         free_irq(irq[0], host);
1144         free_irq(irq[1], host);
1145
1146         platform_set_drvdata(pdev, NULL);
1147
1148         clk_disable(host->hclk);
1149         mmc_free_host(host->mmc);
1150         pm_runtime_put_sync(&pdev->dev);
1151         pm_runtime_disable(&pdev->dev);
1152
1153         return 0;
1154 }
1155
1156 #ifdef CONFIG_PM
1157 static int sh_mmcif_suspend(struct device *dev)
1158 {
1159         struct platform_device *pdev = to_platform_device(dev);
1160         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1161         int ret = mmc_suspend_host(host->mmc);
1162
1163         if (!ret) {
1164                 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1165                 clk_disable(host->hclk);
1166         }
1167
1168         return ret;
1169 }
1170
1171 static int sh_mmcif_resume(struct device *dev)
1172 {
1173         struct platform_device *pdev = to_platform_device(dev);
1174         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1175
1176         clk_enable(host->hclk);
1177
1178         return mmc_resume_host(host->mmc);
1179 }
1180 #else
1181 #define sh_mmcif_suspend        NULL
1182 #define sh_mmcif_resume         NULL
1183 #endif  /* CONFIG_PM */
1184
1185 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1186         .suspend = sh_mmcif_suspend,
1187         .resume = sh_mmcif_resume,
1188 };
1189
1190 static struct platform_driver sh_mmcif_driver = {
1191         .probe          = sh_mmcif_probe,
1192         .remove         = sh_mmcif_remove,
1193         .driver         = {
1194                 .name   = DRIVER_NAME,
1195                 .pm     = &sh_mmcif_dev_pm_ops,
1196         },
1197 };
1198
1199 module_platform_driver(sh_mmcif_driver);
1200
1201 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1202 MODULE_LICENSE("GPL");
1203 MODULE_ALIAS("platform:" DRIVER_NAME);
1204 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");