4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
15 * 3. Handle MMC errors better
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/mmc/card.h>
25 #include <linux/mmc/core.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/mmc.h>
28 #include <linux/mmc/sdio.h>
29 #include <linux/mmc/sh_mmcif.h>
30 #include <linux/pagemap.h>
31 #include <linux/platform_device.h>
33 #define DRIVER_NAME "sh_mmcif"
34 #define DRIVER_VERSION "2010-04-28"
37 #define CMD_MASK 0x3f000000
38 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
39 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
40 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
41 #define CMD_SET_RBSY (1 << 21) /* R1b */
42 #define CMD_SET_CCSEN (1 << 20)
43 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
44 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
45 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
46 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
47 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
48 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
49 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
50 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
51 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
52 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
53 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
54 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
55 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
56 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
57 #define CMD_SET_CCSH (1 << 5)
58 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
59 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
60 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
63 #define CMD_CTRL_BREAK (1 << 0)
66 #define BLOCK_SIZE_MASK 0x0000ffff
69 #define INT_CCSDE (1 << 29)
70 #define INT_CMD12DRE (1 << 26)
71 #define INT_CMD12RBE (1 << 25)
72 #define INT_CMD12CRE (1 << 24)
73 #define INT_DTRANE (1 << 23)
74 #define INT_BUFRE (1 << 22)
75 #define INT_BUFWEN (1 << 21)
76 #define INT_BUFREN (1 << 20)
77 #define INT_CCSRCV (1 << 19)
78 #define INT_RBSYE (1 << 17)
79 #define INT_CRSPE (1 << 16)
80 #define INT_CMDVIO (1 << 15)
81 #define INT_BUFVIO (1 << 14)
82 #define INT_WDATERR (1 << 11)
83 #define INT_RDATERR (1 << 10)
84 #define INT_RIDXERR (1 << 9)
85 #define INT_RSPERR (1 << 8)
86 #define INT_CCSTO (1 << 5)
87 #define INT_CRCSTO (1 << 4)
88 #define INT_WDATTO (1 << 3)
89 #define INT_RDATTO (1 << 2)
90 #define INT_RBSYTO (1 << 1)
91 #define INT_RSPTO (1 << 0)
92 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
93 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
94 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
95 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
98 #define MASK_ALL 0x00000000
99 #define MASK_MCCSDE (1 << 29)
100 #define MASK_MCMD12DRE (1 << 26)
101 #define MASK_MCMD12RBE (1 << 25)
102 #define MASK_MCMD12CRE (1 << 24)
103 #define MASK_MDTRANE (1 << 23)
104 #define MASK_MBUFRE (1 << 22)
105 #define MASK_MBUFWEN (1 << 21)
106 #define MASK_MBUFREN (1 << 20)
107 #define MASK_MCCSRCV (1 << 19)
108 #define MASK_MRBSYE (1 << 17)
109 #define MASK_MCRSPE (1 << 16)
110 #define MASK_MCMDVIO (1 << 15)
111 #define MASK_MBUFVIO (1 << 14)
112 #define MASK_MWDATERR (1 << 11)
113 #define MASK_MRDATERR (1 << 10)
114 #define MASK_MRIDXERR (1 << 9)
115 #define MASK_MRSPERR (1 << 8)
116 #define MASK_MCCSTO (1 << 5)
117 #define MASK_MCRCSTO (1 << 4)
118 #define MASK_MWDATTO (1 << 3)
119 #define MASK_MRDATTO (1 << 2)
120 #define MASK_MRBSYTO (1 << 1)
121 #define MASK_MRSPTO (1 << 0)
124 #define STS1_CMDSEQ (1 << 31)
127 #define STS2_CRCSTE (1 << 31)
128 #define STS2_CRC16E (1 << 30)
129 #define STS2_AC12CRCE (1 << 29)
130 #define STS2_RSPCRC7E (1 << 28)
131 #define STS2_CRCSTEBE (1 << 27)
132 #define STS2_RDATEBE (1 << 26)
133 #define STS2_AC12REBE (1 << 25)
134 #define STS2_RSPEBE (1 << 24)
135 #define STS2_AC12IDXE (1 << 23)
136 #define STS2_RSPIDXE (1 << 22)
137 #define STS2_CCSTO (1 << 15)
138 #define STS2_RDATTO (1 << 14)
139 #define STS2_DATBSYTO (1 << 13)
140 #define STS2_CRCSTTO (1 << 12)
141 #define STS2_AC12BSYTO (1 << 11)
142 #define STS2_RSPBSYTO (1 << 10)
143 #define STS2_AC12RSPTO (1 << 9)
144 #define STS2_RSPTO (1 << 8)
145 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
146 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
147 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
148 STS2_DATBSYTO | STS2_CRCSTTO | \
149 STS2_AC12BSYTO | STS2_RSPBSYTO | \
150 STS2_AC12RSPTO | STS2_RSPTO)
152 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
153 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
154 #define CLKDEV_INIT 400000 /* 400 KHz */
156 struct sh_mmcif_host {
157 struct mmc_host *mmc;
158 struct mmc_data *data;
159 struct platform_device *pd;
166 struct completion intr_wait;
169 struct dma_chan *chan_rx;
170 struct dma_chan *chan_tx;
171 struct completion dma_complete;
172 unsigned int dma_sglen;
175 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
176 unsigned int reg, u32 val)
178 writel(val | readl(host->addr + reg), host->addr + reg);
181 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
182 unsigned int reg, u32 val)
184 writel(~val & readl(host->addr + reg), host->addr + reg);
187 static void mmcif_dma_complete(void *arg)
189 struct sh_mmcif_host *host = arg;
190 dev_dbg(&host->pd->dev, "Command completed\n");
192 if (WARN(!host->data, "%s: NULL data in DMA completion!\n",
193 dev_name(&host->pd->dev)))
196 if (host->data->flags & MMC_DATA_READ)
197 dma_unmap_sg(host->chan_rx->device->dev,
198 host->data->sg, host->data->sg_len,
201 dma_unmap_sg(host->chan_tx->device->dev,
202 host->data->sg, host->data->sg_len,
205 complete(&host->dma_complete);
208 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
210 struct scatterlist *sg = host->data->sg;
211 struct dma_async_tx_descriptor *desc = NULL;
212 struct dma_chan *chan = host->chan_rx;
213 dma_cookie_t cookie = -EINVAL;
216 ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
219 host->dma_sglen = ret;
220 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
221 DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
225 desc->callback = mmcif_dma_complete;
226 desc->callback_param = host;
227 cookie = desc->tx_submit(desc);
232 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
233 chan->device->device_issue_pending(chan);
236 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
237 __func__, host->data->sg_len, ret, cookie);
240 /* DMA failed, fall back to PIO */
243 host->chan_rx = NULL;
245 dma_release_channel(chan);
246 /* Free the Tx channel too */
247 chan = host->chan_tx;
249 host->chan_tx = NULL;
250 dma_release_channel(chan);
252 dev_warn(&host->pd->dev,
253 "DMA failed: %d, falling back to PIO\n", ret);
254 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
257 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
258 desc, cookie, host->data->sg_len);
261 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
263 struct scatterlist *sg = host->data->sg;
264 struct dma_async_tx_descriptor *desc = NULL;
265 struct dma_chan *chan = host->chan_tx;
266 dma_cookie_t cookie = -EINVAL;
269 ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
272 host->dma_sglen = ret;
273 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
274 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
278 desc->callback = mmcif_dma_complete;
279 desc->callback_param = host;
280 cookie = desc->tx_submit(desc);
285 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
286 chan->device->device_issue_pending(chan);
289 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
290 __func__, host->data->sg_len, ret, cookie);
293 /* DMA failed, fall back to PIO */
296 host->chan_tx = NULL;
298 dma_release_channel(chan);
299 /* Free the Rx channel too */
300 chan = host->chan_rx;
302 host->chan_rx = NULL;
303 dma_release_channel(chan);
305 dev_warn(&host->pd->dev,
306 "DMA failed: %d, falling back to PIO\n", ret);
307 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
310 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
314 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
316 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
321 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
322 struct sh_mmcif_plat_data *pdata)
326 /* We can only either use DMA for both Tx and Rx or not use it at all */
331 dma_cap_set(DMA_SLAVE, mask);
333 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter,
334 &pdata->dma->chan_priv_tx);
335 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
341 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter,
342 &pdata->dma->chan_priv_rx);
343 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
346 if (!host->chan_rx) {
347 dma_release_channel(host->chan_tx);
348 host->chan_tx = NULL;
352 init_completion(&host->dma_complete);
356 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
358 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
359 /* Descriptors are freed automatically */
361 struct dma_chan *chan = host->chan_tx;
362 host->chan_tx = NULL;
363 dma_release_channel(chan);
366 struct dma_chan *chan = host->chan_rx;
367 host->chan_rx = NULL;
368 dma_release_channel(chan);
374 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
376 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
378 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
379 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
383 if (p->sup_pclk && clk == host->clk)
384 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
386 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
387 (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16));
389 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
392 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
396 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
398 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
399 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
400 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
401 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
403 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
406 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
409 int ret, timeout = 10000000;
411 host->sd_error = false;
413 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
414 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
415 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
416 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
418 if (state1 & STS1_CMDSEQ) {
419 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
420 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
424 dev_err(&host->pd->dev,
425 "Forceed end of command sequence timeout err\n");
428 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
433 sh_mmcif_sync_reset(host);
434 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
438 if (state2 & STS2_CRC_ERR) {
439 dev_dbg(&host->pd->dev, ": Happened CRC error\n");
441 } else if (state2 & STS2_TIMEOUT_ERR) {
442 dev_dbg(&host->pd->dev, ": Happened Timeout error\n");
445 dev_dbg(&host->pd->dev, ": Happened End/Index error\n");
451 static int sh_mmcif_single_read(struct sh_mmcif_host *host,
452 struct mmc_request *mrq)
454 struct mmc_data *data = mrq->data;
456 u32 blocksize, i, *p = sg_virt(data->sg);
458 /* buf read enable */
459 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
460 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
462 if (time <= 0 || host->sd_error)
463 return sh_mmcif_error_manage(host);
465 blocksize = (BLOCK_SIZE_MASK &
466 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
467 for (i = 0; i < blocksize / 4; i++)
468 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
470 /* buffer read end */
471 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
472 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
474 if (time <= 0 || host->sd_error)
475 return sh_mmcif_error_manage(host);
480 static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
481 struct mmc_request *mrq)
483 struct mmc_data *data = mrq->data;
485 u32 blocksize, i, j, sec, *p;
487 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
489 for (j = 0; j < data->sg_len; j++) {
490 p = sg_virt(data->sg);
491 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
492 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
493 /* buf read enable */
494 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
497 if (time <= 0 || host->sd_error)
498 return sh_mmcif_error_manage(host);
500 for (i = 0; i < blocksize / 4; i++)
501 *p++ = sh_mmcif_readl(host->addr,
504 if (j < data->sg_len - 1)
510 static int sh_mmcif_single_write(struct sh_mmcif_host *host,
511 struct mmc_request *mrq)
513 struct mmc_data *data = mrq->data;
515 u32 blocksize, i, *p = sg_virt(data->sg);
517 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
519 /* buf write enable */
520 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
522 if (time <= 0 || host->sd_error)
523 return sh_mmcif_error_manage(host);
525 blocksize = (BLOCK_SIZE_MASK &
526 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
527 for (i = 0; i < blocksize / 4; i++)
528 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
530 /* buffer write end */
531 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
533 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
535 if (time <= 0 || host->sd_error)
536 return sh_mmcif_error_manage(host);
541 static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
542 struct mmc_request *mrq)
544 struct mmc_data *data = mrq->data;
546 u32 i, sec, j, blocksize, *p;
548 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
551 for (j = 0; j < data->sg_len; j++) {
552 p = sg_virt(data->sg);
553 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
554 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
555 /* buf write enable*/
556 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
559 if (time <= 0 || host->sd_error)
560 return sh_mmcif_error_manage(host);
562 for (i = 0; i < blocksize / 4; i++)
563 sh_mmcif_writel(host->addr,
564 MMCIF_CE_DATA, *p++);
566 if (j < data->sg_len - 1)
572 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
573 struct mmc_command *cmd)
575 if (cmd->flags & MMC_RSP_136) {
576 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
577 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
578 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
579 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
581 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
584 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
585 struct mmc_command *cmd)
587 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
590 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
591 struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
595 /* Response Type check */
596 switch (mmc_resp_type(cmd)) {
598 tmp |= CMD_SET_RTYP_NO;
603 tmp |= CMD_SET_RTYP_6B;
606 tmp |= CMD_SET_RTYP_17B;
609 dev_err(&host->pd->dev, "Unsupported response type.\n");
615 case MMC_STOP_TRANSMISSION:
616 case MMC_SET_WRITE_PROT:
617 case MMC_CLR_WRITE_PROT:
626 switch (host->bus_width) {
627 case MMC_BUS_WIDTH_1:
628 tmp |= CMD_SET_DATW_1;
630 case MMC_BUS_WIDTH_4:
631 tmp |= CMD_SET_DATW_4;
633 case MMC_BUS_WIDTH_8:
634 tmp |= CMD_SET_DATW_8;
637 dev_err(&host->pd->dev, "Unsupported bus width.\n");
642 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
645 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
646 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
647 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
648 mrq->data->blocks << 16);
650 /* RIDXC[1:0] check bits */
651 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
652 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
653 tmp |= CMD_SET_RIDXC_BITS;
654 /* RCRC7C[1:0] check bits */
655 if (opc == MMC_SEND_OP_COND)
656 tmp |= CMD_SET_CRC7C_BITS;
657 /* RCRC7C[1:0] internal CRC7 */
658 if (opc == MMC_ALL_SEND_CID ||
659 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
660 tmp |= CMD_SET_CRC7C_INTERNAL;
662 return opc = ((opc << 24) | tmp);
665 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
666 struct mmc_request *mrq, u32 opc)
671 case MMC_READ_MULTIPLE_BLOCK:
672 ret = sh_mmcif_multi_read(host, mrq);
674 case MMC_WRITE_MULTIPLE_BLOCK:
675 ret = sh_mmcif_multi_write(host, mrq);
677 case MMC_WRITE_BLOCK:
678 ret = sh_mmcif_single_write(host, mrq);
680 case MMC_READ_SINGLE_BLOCK:
681 case MMC_SEND_EXT_CSD:
682 ret = sh_mmcif_single_read(host, mrq);
685 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
692 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
693 struct mmc_request *mrq, struct mmc_command *cmd)
696 int ret = 0, mask = 0;
697 u32 opc = cmd->opcode;
700 /* respons busy check */
702 case MMC_STOP_TRANSMISSION:
703 case MMC_SET_WRITE_PROT:
704 case MMC_CLR_WRITE_PROT:
713 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
714 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
715 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
716 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
719 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
720 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
723 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
725 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
726 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
728 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
730 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
732 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
735 cmd->error = sh_mmcif_error_manage(host);
738 if (host->sd_error) {
739 switch (cmd->opcode) {
740 case MMC_ALL_SEND_CID:
741 case MMC_SELECT_CARD:
743 cmd->error = -ETIMEDOUT;
746 dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n",
748 cmd->error = sh_mmcif_error_manage(host);
751 host->sd_error = false;
754 if (!(cmd->flags & MMC_RSP_PRESENT)) {
758 sh_mmcif_get_response(host, cmd);
760 if (!host->dma_sglen) {
761 ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
764 wait_for_completion_interruptible_timeout(&host->dma_complete,
770 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
771 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
775 mrq->data->bytes_xfered = 0;
777 mrq->data->bytes_xfered =
778 mrq->data->blocks * mrq->data->blksz;
783 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
784 struct mmc_request *mrq, struct mmc_command *cmd)
788 if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
789 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
790 else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
791 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
793 dev_err(&host->pd->dev, "unsupported stop cmd\n");
794 cmd->error = sh_mmcif_error_manage(host);
798 time = wait_for_completion_interruptible_timeout(&host->intr_wait,
800 if (time <= 0 || host->sd_error) {
801 cmd->error = sh_mmcif_error_manage(host);
804 sh_mmcif_get_cmd12response(host, cmd);
808 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
810 struct sh_mmcif_host *host = mmc_priv(mmc);
812 switch (mrq->cmd->opcode) {
813 /* MMCIF does not support SD/SDIO command */
814 case SD_IO_SEND_OP_COND:
816 mrq->cmd->error = -ETIMEDOUT;
817 mmc_request_done(mmc, mrq);
819 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
821 /* send_if_cond cmd (not support) */
822 mrq->cmd->error = -ETIMEDOUT;
823 mmc_request_done(mmc, mrq);
830 host->data = mrq->data;
832 if (mrq->data->flags & MMC_DATA_READ) {
834 sh_mmcif_start_dma_rx(host);
837 sh_mmcif_start_dma_tx(host);
840 sh_mmcif_start_cmd(host, mrq, mrq->cmd);
843 if (mrq->cmd->error != 0) {
844 mmc_request_done(mmc, mrq);
848 sh_mmcif_stop_cmd(host, mrq, mrq->stop);
849 mmc_request_done(mmc, mrq);
852 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
854 struct sh_mmcif_host *host = mmc_priv(mmc);
855 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
857 if (ios->power_mode == MMC_POWER_OFF) {
859 sh_mmcif_clock_control(host, 0);
861 p->down_pwr(host->pd);
863 } else if (ios->power_mode == MMC_POWER_UP) {
865 p->set_pwr(host->pd, ios->power_mode);
869 sh_mmcif_clock_control(host, ios->clock);
871 host->bus_width = ios->bus_width;
874 static int sh_mmcif_get_cd(struct mmc_host *mmc)
876 struct sh_mmcif_host *host = mmc_priv(mmc);
877 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
882 return p->get_cd(host->pd);
885 static struct mmc_host_ops sh_mmcif_ops = {
886 .request = sh_mmcif_request,
887 .set_ios = sh_mmcif_set_ios,
888 .get_cd = sh_mmcif_get_cd,
891 static void sh_mmcif_detect(struct mmc_host *mmc)
893 mmc_detect_change(mmc, 0);
896 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
898 struct sh_mmcif_host *host = dev_id;
902 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
904 if (state & INT_RBSYE) {
905 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
906 ~(INT_RBSYE | INT_CRSPE));
907 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
908 } else if (state & INT_CRSPE) {
909 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
910 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
911 } else if (state & INT_BUFREN) {
912 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
913 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
914 } else if (state & INT_BUFWEN) {
915 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
916 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
917 } else if (state & INT_CMD12DRE) {
918 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
919 ~(INT_CMD12DRE | INT_CMD12RBE |
920 INT_CMD12CRE | INT_BUFRE));
921 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
922 } else if (state & INT_BUFRE) {
923 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
924 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
925 } else if (state & INT_DTRANE) {
926 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
927 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
928 } else if (state & INT_CMD12RBE) {
929 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
930 ~(INT_CMD12RBE | INT_CMD12CRE));
931 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
932 } else if (state & INT_ERR_STS) {
934 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
935 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
938 dev_dbg(&host->pd->dev, "Not support int\n");
939 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
940 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
944 host->sd_error = true;
945 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
947 if (state & ~(INT_CMD12RBE | INT_CMD12CRE))
948 complete(&host->intr_wait);
950 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
955 static int __devinit sh_mmcif_probe(struct platform_device *pdev)
958 struct mmc_host *mmc;
959 struct sh_mmcif_host *host;
960 struct sh_mmcif_plat_data *pd;
961 struct resource *res;
965 irq[0] = platform_get_irq(pdev, 0);
966 irq[1] = platform_get_irq(pdev, 1);
967 if (irq[0] < 0 || irq[1] < 0) {
968 dev_err(&pdev->dev, "Get irq error\n");
971 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
973 dev_err(&pdev->dev, "platform_get_resource error.\n");
976 reg = ioremap(res->start, resource_size(res));
978 dev_err(&pdev->dev, "ioremap error.\n");
981 pd = pdev->dev.platform_data;
983 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
987 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
992 host = mmc_priv(mmc);
995 host->timeout = 1000;
997 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
998 host->hclk = clk_get(&pdev->dev, clk_name);
999 if (IS_ERR(host->hclk)) {
1000 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
1001 ret = PTR_ERR(host->hclk);
1004 clk_enable(host->hclk);
1005 host->clk = clk_get_rate(host->hclk);
1008 init_completion(&host->intr_wait);
1010 mmc->ops = &sh_mmcif_ops;
1011 mmc->f_max = host->clk;
1012 /* close to 400KHz */
1013 if (mmc->f_max < 51200000)
1014 mmc->f_min = mmc->f_max / 128;
1015 else if (mmc->f_max < 102400000)
1016 mmc->f_min = mmc->f_max / 256;
1018 mmc->f_min = mmc->f_max / 512;
1020 mmc->ocr_avail = pd->ocr;
1021 mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1023 mmc->caps |= pd->caps;
1025 mmc->max_blk_size = 512;
1026 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1027 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1028 mmc->max_seg_size = mmc->max_req_size;
1030 sh_mmcif_sync_reset(host);
1031 platform_set_drvdata(pdev, host);
1033 /* See if we also get DMA */
1034 sh_mmcif_request_dma(host, pd);
1038 ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
1040 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
1043 ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
1045 free_irq(irq[0], host);
1046 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1050 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1051 sh_mmcif_detect(host->mmc);
1053 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1054 dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1055 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1059 clk_disable(host->hclk);
1068 static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1070 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1073 mmc_remove_host(host->mmc);
1074 sh_mmcif_release_dma(host);
1077 iounmap(host->addr);
1079 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1081 irq[0] = platform_get_irq(pdev, 0);
1082 irq[1] = platform_get_irq(pdev, 1);
1084 free_irq(irq[0], host);
1085 free_irq(irq[1], host);
1087 platform_set_drvdata(pdev, NULL);
1089 clk_disable(host->hclk);
1090 mmc_free_host(host->mmc);
1095 static struct platform_driver sh_mmcif_driver = {
1096 .probe = sh_mmcif_probe,
1097 .remove = sh_mmcif_remove,
1099 .name = DRIVER_NAME,
1103 static int __init sh_mmcif_init(void)
1105 return platform_driver_register(&sh_mmcif_driver);
1108 static void __exit sh_mmcif_exit(void)
1110 platform_driver_unregister(&sh_mmcif_driver);
1113 module_init(sh_mmcif_init);
1114 module_exit(sh_mmcif_exit);
1117 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1118 MODULE_LICENSE("GPL");
1119 MODULE_ALIAS("platform:" DRIVER_NAME);
1120 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");