Pileus Git - ~andy/linux/blob - drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30
  31 #include "sdhci.h"
  32
  33 #define DRIVER_NAME "sdhci"
  34
  35 #define DBG(f, x...) \
  36         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  37
  38 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  39         defined(CONFIG_MMC_SDHCI_MODULE))
  40 #define SDHCI_USE_LEDS_CLASS
  41 #endif
  42
  43 #define MAX_TUNING_LOOP 40
  44
  45 static unsigned int debug_quirks = 0;
  46 static unsigned int debug_quirks2;
  47
  48 static void sdhci_finish_data(struct sdhci_host *);
  49
  50 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  51 static void sdhci_finish_command(struct sdhci_host *);
  52 static int sdhci_execute_tuning(struct mmc_host *mmc);
  53 static void sdhci_tuning_timer(unsigned long data);
  54
  55 #ifdef CONFIG_PM_RUNTIME
  56 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  57 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  58 #else
  59 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  60 {
  61         return 0;
  62 }
  63 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  64 {
  65         return 0;
  66 }
  67 #endif
  68
  69 static void sdhci_dumpregs(struct sdhci_host *host)
  70 {
  71         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  72                 mmc_hostname(host->mmc));
  73
  74         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  75                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  76                 sdhci_readw(host, SDHCI_HOST_VERSION));
  77         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  78                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  79                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  80         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  81                 sdhci_readl(host, SDHCI_ARGUMENT),
  82                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  83         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  84                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  85                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  86         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  87                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  88                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  89         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  90                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  91                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  92         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  93                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  94                 sdhci_readl(host, SDHCI_INT_STATUS));
  95         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  96                 sdhci_readl(host, SDHCI_INT_ENABLE),
  97                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  98         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  99                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 100                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 101         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 102                 sdhci_readl(host, SDHCI_CAPABILITIES),
 103                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 104         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 105                 sdhci_readw(host, SDHCI_COMMAND),
 106                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 107         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 108                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 109
 110         if (host->flags & SDHCI_USE_ADMA)
 111                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 112                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 113                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 114
 115         pr_debug(DRIVER_NAME ": ===========================================\n");
 116 }
 117
 118 /*****************************************************************************\
 119  *                                                                           *
 120  * Low level functions                                                       *
 121  *                                                                           *
 122 \*****************************************************************************/
 123
 124 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 125 {
 126         u32 ier;
 127
 128         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 129         ier &= ~clear;
 130         ier |= set;
 131         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 132         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 133 }
 134
 135 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 136 {
 137         sdhci_clear_set_irqs(host, 0, irqs);
 138 }
 139
 140 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 141 {
 142         sdhci_clear_set_irqs(host, irqs, 0);
 143 }
 144
 145 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 146 {
 147         u32 present, irqs;
 148
 149         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 150             (host->quirks2 & SDHCI_QUIRK2_OWN_CARD_DETECTION) ||
 151             !mmc_card_is_removable(host->mmc))
 152                 return;
 153
 154         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 155                               SDHCI_CARD_PRESENT;
 156         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 157
 158         if (enable)
 159                 sdhci_unmask_irqs(host, irqs);
 160         else
 161                 sdhci_mask_irqs(host, irqs);
 162 }
 163
 164 static void sdhci_enable_card_detection(struct sdhci_host *host)
 165 {
 166         sdhci_set_card_detection(host, true);
 167 }
 168
 169 static void sdhci_disable_card_detection(struct sdhci_host *host)
 170 {
 171         sdhci_set_card_detection(host, false);
 172 }
 173
 174 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 175 {
 176         unsigned long timeout;
 177         u32 uninitialized_var(ier);
 178
 179         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 180                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 181                         SDHCI_CARD_PRESENT))
 182                         return;
 183         }
 184
 185         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 186                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 187
 188         if (host->ops->platform_reset_enter)
 189                 host->ops->platform_reset_enter(host, mask);
 190
 191         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 192
 193         if (mask & SDHCI_RESET_ALL)
 194                 host->clock = 0;
 195
 196         /* Wait max 100 ms */
 197         timeout = 100;
 198
 199         /* hw clears the bit when it's done */
 200         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 201                 if (timeout == 0) {
 202                         pr_err("%s: Reset 0x%x never completed.\n",
 203                                 mmc_hostname(host->mmc), (int)mask);
 204                         sdhci_dumpregs(host);
 205                         return;
 206                 }
 207                 timeout--;
 208                 mdelay(1);
 209         }
 210
 211         if (host->ops->platform_reset_exit)
 212                 host->ops->platform_reset_exit(host, mask);
 213
 214         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 215                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 216 }
 217
 218 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 219
 220 static void sdhci_init(struct sdhci_host *host, int soft)
 221 {
 222         if (soft)
 223                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 224         else
 225                 sdhci_reset(host, SDHCI_RESET_ALL);
 226
 227         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 228                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 229                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 230                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 231                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 232
 233         if (soft) {
 234                 /* force clock reconfiguration */
 235                 host->clock = 0;
 236                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 237         }
 238 }
 239
 240 static void sdhci_reinit(struct sdhci_host *host)
 241 {
 242         sdhci_init(host, 0);
 243         sdhci_enable_card_detection(host);
 244 }
 245
 246 static void sdhci_activate_led(struct sdhci_host *host)
 247 {
 248         u8 ctrl;
 249
 250         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 251         ctrl |= SDHCI_CTRL_LED;
 252         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 253 }
 254
 255 static void sdhci_deactivate_led(struct sdhci_host *host)
 256 {
 257         u8 ctrl;
 258
 259         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 260         ctrl &= ~SDHCI_CTRL_LED;
 261         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 262 }
 263
 264 #ifdef SDHCI_USE_LEDS_CLASS
 265 static void sdhci_led_control(struct led_classdev *led,
 266         enum led_brightness brightness)
 267 {
 268         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 269         unsigned long flags;
 270
 271         spin_lock_irqsave(&host->lock, flags);
 272
 273         if (host->runtime_suspended)
 274                 goto out;
 275
 276         if (brightness == LED_OFF)
 277                 sdhci_deactivate_led(host);
 278         else
 279                 sdhci_activate_led(host);
 280 out:
 281         spin_unlock_irqrestore(&host->lock, flags);
 282 }
 283 #endif
 284
 285 /*****************************************************************************\
 286  *                                                                           *
 287  * Core functions                                                            *
 288  *                                                                           *
 289 \*****************************************************************************/
 290
 291 static void sdhci_read_block_pio(struct sdhci_host *host)
 292 {
 293         unsigned long flags;
 294         size_t blksize, len, chunk;
 295         u32 uninitialized_var(scratch);
 296         u8 *buf;
 297
 298         DBG("PIO reading\n");
 299
 300         blksize = host->data->blksz;
 301         chunk = 0;
 302
 303         local_irq_save(flags);
 304
 305         while (blksize) {
 306                 if (!sg_miter_next(&host->sg_miter))
 307                         BUG();
 308
 309                 len = min(host->sg_miter.length, blksize);
 310
 311                 blksize -= len;
 312                 host->sg_miter.consumed = len;
 313
 314                 buf = host->sg_miter.addr;
 315
 316                 while (len) {
 317                         if (chunk == 0) {
 318                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 319                                 chunk = 4;
 320                         }
 321
 322                         *buf = scratch & 0xFF;
 323
 324                         buf++;
 325                         scratch >>= 8;
 326                         chunk--;
 327                         len--;
 328                 }
 329         }
 330
 331         sg_miter_stop(&host->sg_miter);
 332
 333         local_irq_restore(flags);
 334 }
 335
 336 static void sdhci_write_block_pio(struct sdhci_host *host)
 337 {
 338         unsigned long flags;
 339         size_t blksize, len, chunk;
 340         u32 scratch;
 341         u8 *buf;
 342
 343         DBG("PIO writing\n");
 344
 345         blksize = host->data->blksz;
 346         chunk = 0;
 347         scratch = 0;
 348
 349         local_irq_save(flags);
 350
 351         while (blksize) {
 352                 if (!sg_miter_next(&host->sg_miter))
 353                         BUG();
 354
 355                 len = min(host->sg_miter.length, blksize);
 356
 357                 blksize -= len;
 358                 host->sg_miter.consumed = len;
 359
 360                 buf = host->sg_miter.addr;
 361
 362                 while (len) {
 363                         scratch |= (u32)*buf << (chunk * 8);
 364
 365                         buf++;
 366                         chunk++;
 367                         len--;
 368
 369                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 370                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 371                                 chunk = 0;
 372                                 scratch = 0;
 373                         }
 374                 }
 375         }
 376
 377         sg_miter_stop(&host->sg_miter);
 378
 379         local_irq_restore(flags);
 380 }
 381
 382 static void sdhci_transfer_pio(struct sdhci_host *host)
 383 {
 384         u32 mask;
 385
 386         BUG_ON(!host->data);
 387
 388         if (host->blocks == 0)
 389                 return;
 390
 391         if (host->data->flags & MMC_DATA_READ)
 392                 mask = SDHCI_DATA_AVAILABLE;
 393         else
 394                 mask = SDHCI_SPACE_AVAILABLE;
 395
 396         /*
 397          * Some controllers (JMicron JMB38x) mess up the buffer bits
 398          * for transfers < 4 bytes. As long as it is just one block,
 399          * we can ignore the bits.
 400          */
 401         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 402                 (host->data->blocks == 1))
 403                 mask = ~0;
 404
 405         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 406                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 407                         udelay(100);
 408
 409                 if (host->data->flags & MMC_DATA_READ)
 410                         sdhci_read_block_pio(host);
 411                 else
 412                         sdhci_write_block_pio(host);
 413
 414                 host->blocks--;
 415                 if (host->blocks == 0)
 416                         break;
 417         }
 418
 419         DBG("PIO transfer complete.\n");
 420 }
 421
 422 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 423 {
 424         local_irq_save(*flags);
 425         return kmap_atomic(sg_page(sg)) + sg->offset;
 426 }
 427
 428 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 429 {
 430         kunmap_atomic(buffer);
 431         local_irq_restore(*flags);
 432 }
 433
 434 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 435 {
 436         __le32 *dataddr = (__le32 __force *)(desc + 4);
 437         __le16 *cmdlen = (__le16 __force *)desc;
 438
 439         /* SDHCI specification says ADMA descriptors should be 4 byte
 440          * aligned, so using 16 or 32bit operations should be safe. */
 441
 442         cmdlen[0] = cpu_to_le16(cmd);
 443         cmdlen[1] = cpu_to_le16(len);
 444
 445         dataddr[0] = cpu_to_le32(addr);
 446 }
 447
 448 static int sdhci_adma_table_pre(struct sdhci_host *host,
 449         struct mmc_data *data)
 450 {
 451         int direction;
 452
 453         u8 *desc;
 454         u8 *align;
 455         dma_addr_t addr;
 456         dma_addr_t align_addr;
 457         int len, offset;
 458
 459         struct scatterlist *sg;
 460         int i;
 461         char *buffer;
 462         unsigned long flags;
 463
 464         /*
 465          * The spec does not specify endianness of descriptor table.
 466          * We currently guess that it is LE.
 467          */
 468
 469         if (data->flags & MMC_DATA_READ)
 470                 direction = DMA_FROM_DEVICE;
 471         else
 472                 direction = DMA_TO_DEVICE;
 473
 474         /*
 475          * The ADMA descriptor table is mapped further down as we
 476          * need to fill it with data first.
 477          */
 478
 479         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 480                 host->align_buffer, 128 * 4, direction);
 481         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 482                 goto fail;
 483         BUG_ON(host->align_addr & 0x3);
 484
 485         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 486                 data->sg, data->sg_len, direction);
 487         if (host->sg_count == 0)
 488                 goto unmap_align;
 489
 490         desc = host->adma_desc;
 491         align = host->align_buffer;
 492
 493         align_addr = host->align_addr;
 494
 495         for_each_sg(data->sg, sg, host->sg_count, i) {
 496                 addr = sg_dma_address(sg);
 497                 len = sg_dma_len(sg);
 498
 499                 /*
 500                  * The SDHCI specification states that ADMA
 501                  * addresses must be 32-bit aligned. If they
 502                  * aren't, then we use a bounce buffer for
 503                  * the (up to three) bytes that screw up the
 504                  * alignment.
 505                  */
 506                 offset = (4 - (addr & 0x3)) & 0x3;
 507                 if (offset) {
 508                         if (data->flags & MMC_DATA_WRITE) {
 509                                 buffer = sdhci_kmap_atomic(sg, &flags);
 510                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 511                                 memcpy(align, buffer, offset);
 512                                 sdhci_kunmap_atomic(buffer, &flags);
 513                         }
 514
 515                         /* tran, valid */
 516                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 517
 518                         BUG_ON(offset > 65536);
 519
 520                         align += 4;
 521                         align_addr += 4;
 522
 523                         desc += 8;
 524
 525                         addr += offset;
 526                         len -= offset;
 527                 }
 528
 529                 BUG_ON(len > 65536);
 530
 531                 /* tran, valid */
 532                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 533                 desc += 8;
 534
 535                 /*
 536                  * If this triggers then we have a calculation bug
 537                  * somewhere. :/
 538                  */
 539                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 540         }
 541
 542         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 543                 /*
 544                 * Mark the last descriptor as the terminating descriptor
 545                 */
 546                 if (desc != host->adma_desc) {
 547                         desc -= 8;
 548                         desc[0] |= 0x2; /* end */
 549                 }
 550         } else {
 551                 /*
 552                 * Add a terminating entry.
 553                 */
 554
 555                 /* nop, end, valid */
 556                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 557         }
 558
 559         /*
 560          * Resync align buffer as we might have changed it.
 561          */
 562         if (data->flags & MMC_DATA_WRITE) {
 563                 dma_sync_single_for_device(mmc_dev(host->mmc),
 564                         host->align_addr, 128 * 4, direction);
 565         }
 566
 567         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 568                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 569         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 570                 goto unmap_entries;
 571         BUG_ON(host->adma_addr & 0x3);
 572
 573         return 0;
 574
 575 unmap_entries:
 576         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 577                 data->sg_len, direction);
 578 unmap_align:
 579         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 580                 128 * 4, direction);
 581 fail:
 582         return -EINVAL;
 583 }
 584
 585 static void sdhci_adma_table_post(struct sdhci_host *host,
 586         struct mmc_data *data)
 587 {
 588         int direction;
 589
 590         struct scatterlist *sg;
 591         int i, size;
 592         u8 *align;
 593         char *buffer;
 594         unsigned long flags;
 595
 596         if (data->flags & MMC_DATA_READ)
 597                 direction = DMA_FROM_DEVICE;
 598         else
 599                 direction = DMA_TO_DEVICE;
 600
 601         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 602                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 603
 604         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 605                 128 * 4, direction);
 606
 607         if (data->flags & MMC_DATA_READ) {
 608                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 609                         data->sg_len, direction);
 610
 611                 align = host->align_buffer;
 612
 613                 for_each_sg(data->sg, sg, host->sg_count, i) {
 614                         if (sg_dma_address(sg) & 0x3) {
 615                                 size = 4 - (sg_dma_address(sg) & 0x3);
 616
 617                                 buffer = sdhci_kmap_atomic(sg, &flags);
 618                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 619                                 memcpy(buffer, align, size);
 620                                 sdhci_kunmap_atomic(buffer, &flags);
 621
 622                                 align += 4;
 623                         }
 624                 }
 625         }
 626
 627         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 628                 data->sg_len, direction);
 629 }
 630
 631 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 632 {
 633         u8 count;
 634         struct mmc_data *data = cmd->data;
 635         unsigned target_timeout, current_timeout;
 636
 637         /*
 638          * If the host controller provides us with an incorrect timeout
 639          * value, just skip the check and use 0xE.  The hardware may take
 640          * longer to time out, but that's much better than having a too-short
 641          * timeout value.
 642          */
 643         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 644                 return 0xE;
 645
 646         /* Unspecified timeout, assume max */
 647         if (!data && !cmd->cmd_timeout_ms)
 648                 return 0xE;
 649
 650         /* timeout in us */
 651         if (!data)
 652                 target_timeout = cmd->cmd_timeout_ms * 1000;
 653         else {
 654                 target_timeout = data->timeout_ns / 1000;
 655                 if (host->clock)
 656                         target_timeout += data->timeout_clks / host->clock;
 657         }
 658
 659         /*
 660          * Figure out needed cycles.
 661          * We do this in steps in order to fit inside a 32 bit int.
 662          * The first step is the minimum timeout, which will have a
 663          * minimum resolution of 6 bits:
 664          * (1) 2^13*1000 > 2^22,
 665          * (2) host->timeout_clk < 2^16
 666          *     =>
 667          *     (1) / (2) > 2^6
 668          */
 669         count = 0;
 670         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 671         while (current_timeout < target_timeout) {
 672                 count++;
 673                 current_timeout <<= 1;
 674                 if (count >= 0xF)
 675                         break;
 676         }
 677
 678         if (count >= 0xF) {
 679                 pr_warning("%s: Too large timeout requested for CMD%d!\n",
 680                        mmc_hostname(host->mmc), cmd->opcode);
 681                 count = 0xE;
 682         }
 683
 684         return count;
 685 }
 686
 687 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 688 {
 689         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 690         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 691
 692         if (host->flags & SDHCI_REQ_USE_DMA)
 693                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 694         else
 695                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 696 }
 697
 698 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 699 {
 700         u8 count;
 701         u8 ctrl;
 702         struct mmc_data *data = cmd->data;
 703         int ret;
 704
 705         WARN_ON(host->data);
 706
 707         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 708                 count = sdhci_calc_timeout(host, cmd);
 709                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 710         }
 711
 712         if (!data)
 713                 return;
 714
 715         /* Sanity checks */
 716         BUG_ON(data->blksz * data->blocks > 524288);
 717         BUG_ON(data->blksz > host->mmc->max_blk_size);
 718         BUG_ON(data->blocks > 65535);
 719
 720         host->data = data;
 721         host->data_early = 0;
 722         host->data->bytes_xfered = 0;
 723
 724         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 725                 host->flags |= SDHCI_REQ_USE_DMA;
 726
 727         /*
 728          * FIXME: This doesn't account for merging when mapping the
 729          * scatterlist.
 730          */
 731         if (host->flags & SDHCI_REQ_USE_DMA) {
 732                 int broken, i;
 733                 struct scatterlist *sg;
 734
 735                 broken = 0;
 736                 if (host->flags & SDHCI_USE_ADMA) {
 737                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 738                                 broken = 1;
 739                 } else {
 740                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 741                                 broken = 1;
 742                 }
 743
 744                 if (unlikely(broken)) {
 745                         for_each_sg(data->sg, sg, data->sg_len, i) {
 746                                 if (sg->length & 0x3) {
 747                                         DBG("Reverting to PIO because of "
 748                                                 "transfer size (%d)\n",
 749                                                 sg->length);
 750                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 751                                         break;
 752                                 }
 753                         }
 754                 }
 755         }
 756
 757         /*
 758          * The assumption here being that alignment is the same after
 759          * translation to device address space.
 760          */
 761         if (host->flags & SDHCI_REQ_USE_DMA) {
 762                 int broken, i;
 763                 struct scatterlist *sg;
 764
 765                 broken = 0;
 766                 if (host->flags & SDHCI_USE_ADMA) {
 767                         /*
 768                          * As we use 3 byte chunks to work around
 769                          * alignment problems, we need to check this
 770                          * quirk.
 771                          */
 772                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 773                                 broken = 1;
 774                 } else {
 775                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 776                                 broken = 1;
 777                 }
 778
 779                 if (unlikely(broken)) {
 780                         for_each_sg(data->sg, sg, data->sg_len, i) {
 781                                 if (sg->offset & 0x3) {
 782                                         DBG("Reverting to PIO because of "
 783                                                 "bad alignment\n");
 784                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 785                                         break;
 786                                 }
 787                         }
 788                 }
 789         }
 790
 791         if (host->flags & SDHCI_REQ_USE_DMA) {
 792                 if (host->flags & SDHCI_USE_ADMA) {
 793                         ret = sdhci_adma_table_pre(host, data);
 794                         if (ret) {
 795                                 /*
 796                                  * This only happens when someone fed
 797                                  * us an invalid request.
 798                                  */
 799                                 WARN_ON(1);
 800                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 801                         } else {
 802                                 sdhci_writel(host, host->adma_addr,
 803                                         SDHCI_ADMA_ADDRESS);
 804                         }
 805                 } else {
 806                         int sg_cnt;
 807
 808                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 809                                         data->sg, data->sg_len,
 810                                         (data->flags & MMC_DATA_READ) ?
 811                                                 DMA_FROM_DEVICE :
 812                                                 DMA_TO_DEVICE);
 813                         if (sg_cnt == 0) {
 814                                 /*
 815                                  * This only happens when someone fed
 816                                  * us an invalid request.
 817                                  */
 818                                 WARN_ON(1);
 819                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 820                         } else {
 821                                 WARN_ON(sg_cnt != 1);
 822                                 sdhci_writel(host, sg_dma_address(data->sg),
 823                                         SDHCI_DMA_ADDRESS);
 824                         }
 825                 }
 826         }
 827
 828         /*
 829          * Always adjust the DMA selection as some controllers
 830          * (e.g. JMicron) can't do PIO properly when the selection
 831          * is ADMA.
 832          */
 833         if (host->version >= SDHCI_SPEC_200) {
 834                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 835                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 836                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 837                         (host->flags & SDHCI_USE_ADMA))
 838                         ctrl |= SDHCI_CTRL_ADMA32;
 839                 else
 840                         ctrl |= SDHCI_CTRL_SDMA;
 841                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 842         }
 843
 844         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 845                 int flags;
 846
 847                 flags = SG_MITER_ATOMIC;
 848                 if (host->data->flags & MMC_DATA_READ)
 849                         flags |= SG_MITER_TO_SG;
 850                 else
 851                         flags |= SG_MITER_FROM_SG;
 852                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 853                 host->blocks = data->blocks;
 854         }
 855
 856         sdhci_set_transfer_irqs(host);
 857
 858         /* Set the DMA boundary value and block size */
 859         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 860                 data->blksz), SDHCI_BLOCK_SIZE);
 861         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 862 }
 863
 864 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 865         struct mmc_command *cmd)
 866 {
 867         u16 mode;
 868         struct mmc_data *data = cmd->data;
 869
 870         if (data == NULL)
 871                 return;
 872
 873         WARN_ON(!host->data);
 874
 875         mode = SDHCI_TRNS_BLK_CNT_EN;
 876         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 877                 mode |= SDHCI_TRNS_MULTI;
 878                 /*
 879                  * If we are sending CMD23, CMD12 never gets sent
 880                  * on successful completion (so no Auto-CMD12).
 881                  */
 882                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 883                         mode |= SDHCI_TRNS_AUTO_CMD12;
 884                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 885                         mode |= SDHCI_TRNS_AUTO_CMD23;
 886                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 887                 }
 888         }
 889
 890         if (data->flags & MMC_DATA_READ)
 891                 mode |= SDHCI_TRNS_READ;
 892         if (host->flags & SDHCI_REQ_USE_DMA)
 893                 mode |= SDHCI_TRNS_DMA;
 894
 895         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 896 }
 897
 898 static void sdhci_finish_data(struct sdhci_host *host)
 899 {
 900         struct mmc_data *data;
 901
 902         BUG_ON(!host->data);
 903
 904         data = host->data;
 905         host->data = NULL;
 906
 907         if (host->flags & SDHCI_REQ_USE_DMA) {
 908                 if (host->flags & SDHCI_USE_ADMA)
 909                         sdhci_adma_table_post(host, data);
 910                 else {
 911                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 912                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 913                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 914                 }
 915         }
 916
 917         /*
 918          * The specification states that the block count register must
 919          * be updated, but it does not specify at what point in the
 920          * data flow. That makes the register entirely useless to read
 921          * back so we have to assume that nothing made it to the card
 922          * in the event of an error.
 923          */
 924         if (data->error)
 925                 data->bytes_xfered = 0;
 926         else
 927                 data->bytes_xfered = data->blksz * data->blocks;
 928
 929         /*
 930          * Need to send CMD12 if -
 931          * a) open-ended multiblock transfer (no CMD23)
 932          * b) error in multiblock transfer
 933          */
 934         if (data->stop &&
 935             (data->error ||
 936              !host->mrq->sbc)) {
 937
 938                 /*
 939                  * The controller needs a reset of internal state machines
 940                  * upon error conditions.
 941                  */
 942                 if (data->error) {
 943                         sdhci_reset(host, SDHCI_RESET_CMD);
 944                         sdhci_reset(host, SDHCI_RESET_DATA);
 945                 }
 946
 947                 sdhci_send_command(host, data->stop);
 948         } else
 949                 tasklet_schedule(&host->finish_tasklet);
 950 }
 951
 952 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 953 {
 954         int flags;
 955         u32 mask;
 956         unsigned long timeout;
 957
 958         WARN_ON(host->cmd);
 959
 960         /* Wait max 10 ms */
 961         timeout = 10;
 962
 963         mask = SDHCI_CMD_INHIBIT;
 964         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 965                 mask |= SDHCI_DATA_INHIBIT;
 966
 967         /* We shouldn't wait for data inihibit for stop commands, even
 968            though they might use busy signaling */
 969         if (host->mrq->data && (cmd == host->mrq->data->stop))
 970                 mask &= ~SDHCI_DATA_INHIBIT;
 971
 972         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 973                 if (timeout == 0) {
 974                         pr_err("%s: Controller never released "
 975                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 976                         sdhci_dumpregs(host);
 977                         cmd->error = -EIO;
 978                         tasklet_schedule(&host->finish_tasklet);
 979                         return;
 980                 }
 981                 timeout--;
 982                 mdelay(1);
 983         }
 984
 985         mod_timer(&host->timer, jiffies + 10 * HZ);
 986
 987         host->cmd = cmd;
 988
 989         sdhci_prepare_data(host, cmd);
 990
 991         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 992
 993         sdhci_set_transfer_mode(host, cmd);
 994
 995         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 996                 pr_err("%s: Unsupported response type!\n",
 997                         mmc_hostname(host->mmc));
 998                 cmd->error = -EINVAL;
 999                 tasklet_schedule(&host->finish_tasklet);
1000                 return;
1001         }
1002
1003         if (!(cmd->flags & MMC_RSP_PRESENT))
1004                 flags = SDHCI_CMD_RESP_NONE;
1005         else if (cmd->flags & MMC_RSP_136)
1006                 flags = SDHCI_CMD_RESP_LONG;
1007         else if (cmd->flags & MMC_RSP_BUSY)
1008                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1009         else
1010                 flags = SDHCI_CMD_RESP_SHORT;
1011
1012         if (cmd->flags & MMC_RSP_CRC)
1013                 flags |= SDHCI_CMD_CRC;
1014         if (cmd->flags & MMC_RSP_OPCODE)
1015                 flags |= SDHCI_CMD_INDEX;
1016
1017         /* CMD19 is special in that the Data Present Select should be set */
1018         if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
1019                 flags |= SDHCI_CMD_DATA;
1020
1021         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1022 }
1023
1024 static void sdhci_finish_command(struct sdhci_host *host)
1025 {
1026         int i;
1027
1028         BUG_ON(host->cmd == NULL);
1029
1030         if (host->cmd->flags & MMC_RSP_PRESENT) {
1031                 if (host->cmd->flags & MMC_RSP_136) {
1032                         /* CRC is stripped so we need to do some shifting. */
1033                         for (i = 0;i < 4;i++) {
1034                                 host->cmd->resp[i] = sdhci_readl(host,
1035                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1036                                 if (i != 3)
1037                                         host->cmd->resp[i] |=
1038                                                 sdhci_readb(host,
1039                                                 SDHCI_RESPONSE + (3-i)*4-1);
1040                         }
1041                 } else {
1042                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1043                 }
1044         }
1045
1046         host->cmd->error = 0;
1047
1048         /* Finished CMD23, now send actual command. */
1049         if (host->cmd == host->mrq->sbc) {
1050                 host->cmd = NULL;
1051                 sdhci_send_command(host, host->mrq->cmd);
1052         } else {
1053
1054                 /* Processed actual command. */
1055                 if (host->data && host->data_early)
1056                         sdhci_finish_data(host);
1057
1058                 if (!host->cmd->data)
1059                         tasklet_schedule(&host->finish_tasklet);
1060
1061                 host->cmd = NULL;
1062         }
1063 }
1064
1065 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1066 {
1067         int div = 0; /* Initialized for compiler warning */
1068         int real_div = div, clk_mul = 1;
1069         u16 clk = 0;
1070         unsigned long timeout;
1071
1072         if (clock == host->clock)
1073                 return;
1074
1075         host->mmc->actual_clock = 0;
1076
1077         if (host->ops->set_clock) {
1078                 host->ops->set_clock(host, clock);
1079                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1080                         return;
1081         }
1082
1083         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1084
1085         if (clock == 0)
1086                 goto out;
1087
1088         if (host->version >= SDHCI_SPEC_300) {
1089                 /*
1090                  * Check if the Host Controller supports Programmable Clock
1091                  * Mode.
1092                  */
1093                 if (host->clk_mul) {
1094                         u16 ctrl;
1095
1096                         /*
1097                          * We need to figure out whether the Host Driver needs
1098                          * to select Programmable Clock Mode, or the value can
1099                          * be set automatically by the Host Controller based on
1100                          * the Preset Value registers.
1101                          */
1102                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1103                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1104                                 for (div = 1; div <= 1024; div++) {
1105                                         if (((host->max_clk * host->clk_mul) /
1106                                               div) <= clock)
1107                                                 break;
1108                                 }
1109                                 /*
1110                                  * Set Programmable Clock Mode in the Clock
1111                                  * Control register.
1112                                  */
1113                                 clk = SDHCI_PROG_CLOCK_MODE;
1114                                 real_div = div;
1115                                 clk_mul = host->clk_mul;
1116                                 div--;
1117                         }
1118                 } else {
1119                         /* Version 3.00 divisors must be a multiple of 2. */
1120                         if (host->max_clk <= clock)
1121                                 div = 1;
1122                         else {
1123                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1124                                      div += 2) {
1125                                         if ((host->max_clk / div) <= clock)
1126                                                 break;
1127                                 }
1128                         }
1129                         real_div = div;
1130                         div >>= 1;
1131                 }
1132         } else {
1133                 /* Version 2.00 divisors must be a power of 2. */
1134                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1135                         if ((host->max_clk / div) <= clock)
1136                                 break;
1137                 }
1138                 real_div = div;
1139                 div >>= 1;
1140         }
1141
1142         if (real_div)
1143                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1144
1145         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1146         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1147                 << SDHCI_DIVIDER_HI_SHIFT;
1148         clk |= SDHCI_CLOCK_INT_EN;
1149         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1150
1151         /* Wait max 20 ms */
1152         timeout = 20;
1153         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1154                 & SDHCI_CLOCK_INT_STABLE)) {
1155                 if (timeout == 0) {
1156                         pr_err("%s: Internal clock never "
1157                                 "stabilised.\n", mmc_hostname(host->mmc));
1158                         sdhci_dumpregs(host);
1159                         return;
1160                 }
1161                 timeout--;
1162                 mdelay(1);
1163         }
1164
1165         clk |= SDHCI_CLOCK_CARD_EN;
1166         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1167
1168 out:
1169         host->clock = clock;
1170 }
1171
1172 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1173 {
1174         u8 pwr = 0;
1175
1176         if (power != (unsigned short)-1) {
1177                 switch (1 << power) {
1178                 case MMC_VDD_165_195:
1179                         pwr = SDHCI_POWER_180;
1180                         break;
1181                 case MMC_VDD_29_30:
1182                 case MMC_VDD_30_31:
1183                         pwr = SDHCI_POWER_300;
1184                         break;
1185                 case MMC_VDD_32_33:
1186                 case MMC_VDD_33_34:
1187                         pwr = SDHCI_POWER_330;
1188                         break;
1189                 default:
1190                         BUG();
1191                 }
1192         }
1193
1194         if (host->pwr == pwr)
1195                 return -1;
1196
1197         host->pwr = pwr;
1198
1199         if (pwr == 0) {
1200                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1201                 return 0;
1202         }
1203
1204         /*
1205          * Spec says that we should clear the power reg before setting
1206          * a new value. Some controllers don't seem to like this though.
1207          */
1208         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1209                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1210
1211         /*
1212          * At least the Marvell CaFe chip gets confused if we set the voltage
1213          * and set turn on power at the same time, so set the voltage first.
1214          */
1215         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1216                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1217
1218         pwr |= SDHCI_POWER_ON;
1219
1220         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1221
1222         /*
1223          * Some controllers need an extra 10ms delay of 10ms before they
1224          * can apply clock after applying power
1225          */
1226         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1227                 mdelay(10);
1228
1229         return power;
1230 }
1231
1232 /*****************************************************************************\
1233  *                                                                           *
1234  * MMC callbacks                                                             *
1235  *                                                                           *
1236 \*****************************************************************************/
1237
1238 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1239 {
1240         struct sdhci_host *host;
1241         bool present;
1242         unsigned long flags;
1243
1244         host = mmc_priv(mmc);
1245
1246         sdhci_runtime_pm_get(host);
1247
1248         spin_lock_irqsave(&host->lock, flags);
1249
1250         WARN_ON(host->mrq != NULL);
1251
1252 #ifndef SDHCI_USE_LEDS_CLASS
1253         sdhci_activate_led(host);
1254 #endif
1255
1256         /*
1257          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1258          * requests if Auto-CMD12 is enabled.
1259          */
1260         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1261                 if (mrq->stop) {
1262                         mrq->data->stop = NULL;
1263                         mrq->stop = NULL;
1264                 }
1265         }
1266
1267         host->mrq = mrq;
1268
1269         /* If polling, assume that the card is always present. */
1270         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1271                 present = true;
1272         else
1273                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1274                                 SDHCI_CARD_PRESENT;
1275
1276         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1277                 host->mrq->cmd->error = -ENOMEDIUM;
1278                 tasklet_schedule(&host->finish_tasklet);
1279         } else {
1280                 u32 present_state;
1281
1282                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1283                 /*
1284                  * Check if the re-tuning timer has already expired and there
1285                  * is no on-going data transfer. If so, we need to execute
1286                  * tuning procedure before sending command.
1287                  */
1288                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1289                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1290                         spin_unlock_irqrestore(&host->lock, flags);
1291                         sdhci_execute_tuning(mmc);
1292                         spin_lock_irqsave(&host->lock, flags);
1293
1294                         /* Restore original mmc_request structure */
1295                         host->mrq = mrq;
1296                 }
1297
1298                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1299                         sdhci_send_command(host, mrq->sbc);
1300                 else
1301                         sdhci_send_command(host, mrq->cmd);
1302         }
1303
1304         mmiowb();
1305         spin_unlock_irqrestore(&host->lock, flags);
1306 }
1307
1308 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1309 {
1310         unsigned long flags;
1311         int vdd_bit = -1;
1312         u8 ctrl;
1313
1314         spin_lock_irqsave(&host->lock, flags);
1315
1316         if (host->flags & SDHCI_DEVICE_DEAD) {
1317                 spin_unlock_irqrestore(&host->lock, flags);
1318                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1319                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1320                 return;
1321         }
1322
1323         /*
1324          * Reset the chip on each power off.
1325          * Should clear out any weird states.
1326          */
1327         if (ios->power_mode == MMC_POWER_OFF) {
1328                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1329                 sdhci_reinit(host);
1330         }
1331
1332         sdhci_set_clock(host, ios->clock);
1333
1334         if (ios->power_mode == MMC_POWER_OFF)
1335                 vdd_bit = sdhci_set_power(host, -1);
1336         else
1337                 vdd_bit = sdhci_set_power(host, ios->vdd);
1338
1339         if (host->vmmc && vdd_bit != -1) {
1340                 spin_unlock_irqrestore(&host->lock, flags);
1341                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1342                 spin_lock_irqsave(&host->lock, flags);
1343         }
1344
1345         if (host->ops->platform_send_init_74_clocks)
1346                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1347
1348         /*
1349          * If your platform has 8-bit width support but is not a v3 controller,
1350          * or if it requires special setup code, you should implement that in
1351          * platform_8bit_width().
1352          */
1353         if (host->ops->platform_8bit_width)
1354                 host->ops->platform_8bit_width(host, ios->bus_width);
1355         else {
1356                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1357                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1358                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1359                         if (host->version >= SDHCI_SPEC_300)
1360                                 ctrl |= SDHCI_CTRL_8BITBUS;
1361                 } else {
1362                         if (host->version >= SDHCI_SPEC_300)
1363                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1364                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1365                                 ctrl |= SDHCI_CTRL_4BITBUS;
1366                         else
1367                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1368                 }
1369                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1370         }
1371
1372         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1373
1374         if ((ios->timing == MMC_TIMING_SD_HS ||
1375              ios->timing == MMC_TIMING_MMC_HS)
1376             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1377                 ctrl |= SDHCI_CTRL_HISPD;
1378         else
1379                 ctrl &= ~SDHCI_CTRL_HISPD;
1380
1381         if (host->version >= SDHCI_SPEC_300) {
1382                 u16 clk, ctrl_2;
1383                 unsigned int clock;
1384
1385                 /* In case of UHS-I modes, set High Speed Enable */
1386                 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1387                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1388                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1389                     (ios->timing == MMC_TIMING_UHS_SDR25) ||
1390                     (ios->timing == MMC_TIMING_UHS_SDR12))
1391                         ctrl |= SDHCI_CTRL_HISPD;
1392
1393                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1394                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1395                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1396                         /*
1397                          * We only need to set Driver Strength if the
1398                          * preset value enable is not set.
1399                          */
1400                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1401                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1402                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1403                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1404                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1405
1406                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1407                 } else {
1408                         /*
1409                          * According to SDHC Spec v3.00, if the Preset Value
1410                          * Enable in the Host Control 2 register is set, we
1411                          * need to reset SD Clock Enable before changing High
1412                          * Speed Enable to avoid generating clock gliches.
1413                          */
1414
1415                         /* Reset SD Clock Enable */
1416                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1417                         clk &= ~SDHCI_CLOCK_CARD_EN;
1418                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1419
1420                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1421
1422                         /* Re-enable SD Clock */
1423                         clock = host->clock;
1424                         host->clock = 0;
1425                         sdhci_set_clock(host, clock);
1426                 }
1427
1428
1429                 /* Reset SD Clock Enable */
1430                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1431                 clk &= ~SDHCI_CLOCK_CARD_EN;
1432                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1433
1434                 if (host->ops->set_uhs_signaling)
1435                         host->ops->set_uhs_signaling(host, ios->timing);
1436                 else {
1437                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1438                         /* Select Bus Speed Mode for host */
1439                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1440                         if (ios->timing == MMC_TIMING_UHS_SDR12)
1441                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1442                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1443                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1444                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1445                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1446                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1447                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1448                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1449                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1450                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1451                 }
1452
1453                 /* Re-enable SD Clock */
1454                 clock = host->clock;
1455                 host->clock = 0;
1456                 sdhci_set_clock(host, clock);
1457         } else
1458                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1459
1460         /*
1461          * Some (ENE) controllers go apeshit on some ios operation,
1462          * signalling timeout and CRC errors even on CMD0. Resetting
1463          * it on each ios seems to solve the problem.
1464          */
1465         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1466                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1467
1468         mmiowb();
1469         spin_unlock_irqrestore(&host->lock, flags);
1470 }
1471
1472 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1473 {
1474         struct sdhci_host *host = mmc_priv(mmc);
1475
1476         sdhci_runtime_pm_get(host);
1477         sdhci_do_set_ios(host, ios);
1478         sdhci_runtime_pm_put(host);
1479 }
1480
1481 static int sdhci_check_ro(struct sdhci_host *host)
1482 {
1483         unsigned long flags;
1484         int is_readonly;
1485
1486         spin_lock_irqsave(&host->lock, flags);
1487
1488         if (host->flags & SDHCI_DEVICE_DEAD)
1489                 is_readonly = 0;
1490         else if (host->ops->get_ro)
1491                 is_readonly = host->ops->get_ro(host);
1492         else
1493                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1494                                 & SDHCI_WRITE_PROTECT);
1495
1496         spin_unlock_irqrestore(&host->lock, flags);
1497
1498         /* This quirk needs to be replaced by a callback-function later */
1499         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1500                 !is_readonly : is_readonly;
1501 }
1502
1503 #define SAMPLE_COUNT    5
1504
1505 static int sdhci_do_get_ro(struct sdhci_host *host)
1506 {
1507         int i, ro_count;
1508
1509         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1510                 return sdhci_check_ro(host);
1511
1512         ro_count = 0;
1513         for (i = 0; i < SAMPLE_COUNT; i++) {
1514                 if (sdhci_check_ro(host)) {
1515                         if (++ro_count > SAMPLE_COUNT / 2)
1516                                 return 1;
1517                 }
1518                 msleep(30);
1519         }
1520         return 0;
1521 }
1522
1523 static void sdhci_hw_reset(struct mmc_host *mmc)
1524 {
1525         struct sdhci_host *host = mmc_priv(mmc);
1526
1527         if (host->ops && host->ops->hw_reset)
1528                 host->ops->hw_reset(host);
1529 }
1530
1531 static int sdhci_get_ro(struct mmc_host *mmc)
1532 {
1533         struct sdhci_host *host = mmc_priv(mmc);
1534         int ret;
1535
1536         sdhci_runtime_pm_get(host);
1537         ret = sdhci_do_get_ro(host);
1538         sdhci_runtime_pm_put(host);
1539         return ret;
1540 }
1541
1542 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1543 {
1544         if (host->flags & SDHCI_DEVICE_DEAD)
1545                 goto out;
1546
1547         if (enable)
1548                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1549         else
1550                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1551
1552         /* SDIO IRQ will be enabled as appropriate in runtime resume */
1553         if (host->runtime_suspended)
1554                 goto out;
1555
1556         if (enable)
1557                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1558         else
1559                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1560 out:
1561         mmiowb();
1562 }
1563
1564 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1565 {
1566         struct sdhci_host *host = mmc_priv(mmc);
1567         unsigned long flags;
1568
1569         spin_lock_irqsave(&host->lock, flags);
1570         sdhci_enable_sdio_irq_nolock(host, enable);
1571         spin_unlock_irqrestore(&host->lock, flags);
1572 }
1573
1574 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1575                                                 struct mmc_ios *ios)
1576 {
1577         u8 pwr;
1578         u16 clk, ctrl;
1579         u32 present_state;
1580
1581         /*
1582          * Signal Voltage Switching is only applicable for Host Controllers
1583          * v3.00 and above.
1584          */
1585         if (host->version < SDHCI_SPEC_300)
1586                 return 0;
1587
1588         /*
1589          * We first check whether the request is to set signalling voltage
1590          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1591          */
1592         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1593         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1594                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1595                 ctrl &= ~SDHCI_CTRL_VDD_180;
1596                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1597
1598                 /* Wait for 5ms */
1599                 usleep_range(5000, 5500);
1600
1601                 /* 3.3V regulator output should be stable within 5 ms */
1602                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1603                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1604                         return 0;
1605                 else {
1606                         pr_info(DRIVER_NAME ": Switching to 3.3V "
1607                                 "signalling voltage failed\n");
1608                         return -EIO;
1609                 }
1610         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1611                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1612                 /* Stop SDCLK */
1613                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1614                 clk &= ~SDHCI_CLOCK_CARD_EN;
1615                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1616
1617                 /* Check whether DAT[3:0] is 0000 */
1618                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1619                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1620                        SDHCI_DATA_LVL_SHIFT)) {
1621                         /*
1622                          * Enable 1.8V Signal Enable in the Host Control2
1623                          * register
1624                          */
1625                         ctrl |= SDHCI_CTRL_VDD_180;
1626                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1627
1628                         /* Wait for 5ms */
1629                         usleep_range(5000, 5500);
1630
1631                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1632                         if (ctrl & SDHCI_CTRL_VDD_180) {
1633                                 /* Provide SDCLK again and wait for 1ms*/
1634                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1635                                 clk |= SDHCI_CLOCK_CARD_EN;
1636                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1637                                 usleep_range(1000, 1500);
1638
1639                                 /*
1640                                  * If DAT[3:0] level is 1111b, then the card
1641                                  * was successfully switched to 1.8V signaling.
1642                                  */
1643                                 present_state = sdhci_readl(host,
1644                                                         SDHCI_PRESENT_STATE);
1645                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1646                                      SDHCI_DATA_LVL_MASK)
1647                                         return 0;
1648                         }
1649                 }
1650
1651                 /*
1652                  * If we are here, that means the switch to 1.8V signaling
1653                  * failed. We power cycle the card, and retry initialization
1654                  * sequence by setting S18R to 0.
1655                  */
1656                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1657                 pwr &= ~SDHCI_POWER_ON;
1658                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1659
1660                 /* Wait for 1ms as per the spec */
1661                 usleep_range(1000, 1500);
1662                 pwr |= SDHCI_POWER_ON;
1663                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1664
1665                 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1666                         "voltage failed, retrying with S18R set to 0\n");
1667                 return -EAGAIN;
1668         } else
1669                 /* No signal voltage switch required */
1670                 return 0;
1671 }
1672
1673 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1674         struct mmc_ios *ios)
1675 {
1676         struct sdhci_host *host = mmc_priv(mmc);
1677         int err;
1678
1679         if (host->version < SDHCI_SPEC_300)
1680                 return 0;
1681         sdhci_runtime_pm_get(host);
1682         err = sdhci_do_start_signal_voltage_switch(host, ios);
1683         sdhci_runtime_pm_put(host);
1684         return err;
1685 }
1686
1687 static int sdhci_execute_tuning(struct mmc_host *mmc)
1688 {
1689         struct sdhci_host *host;
1690         u16 ctrl;
1691         u32 ier;
1692         int tuning_loop_counter = MAX_TUNING_LOOP;
1693         unsigned long timeout;
1694         int err = 0;
1695
1696         host = mmc_priv(mmc);
1697
1698         sdhci_runtime_pm_get(host);
1699         disable_irq(host->irq);
1700         spin_lock(&host->lock);
1701
1702         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1703
1704         /*
1705          * Host Controller needs tuning only in case of SDR104 mode
1706          * and for SDR50 mode when Use Tuning for SDR50 is set in
1707          * Capabilities register.
1708          */
1709         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1710             (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1711             (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1712                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1713         else {
1714                 spin_unlock(&host->lock);
1715                 enable_irq(host->irq);
1716                 sdhci_runtime_pm_put(host);
1717                 return 0;
1718         }
1719
1720         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1721
1722         /*
1723          * As per the Host Controller spec v3.00, tuning command
1724          * generates Buffer Read Ready interrupt, so enable that.
1725          *
1726          * Note: The spec clearly says that when tuning sequence
1727          * is being performed, the controller does not generate
1728          * interrupts other than Buffer Read Ready interrupt. But
1729          * to make sure we don't hit a controller bug, we _only_
1730          * enable Buffer Read Ready interrupt here.
1731          */
1732         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1733         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1734
1735         /*
1736          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1737          * of loops reaches 40 times or a timeout of 150ms occurs.
1738          */
1739         timeout = 150;
1740         do {
1741                 struct mmc_command cmd = {0};
1742                 struct mmc_request mrq = {NULL};
1743
1744                 if (!tuning_loop_counter && !timeout)
1745                         break;
1746
1747                 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1748                 cmd.arg = 0;
1749                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1750                 cmd.retries = 0;
1751                 cmd.data = NULL;
1752                 cmd.error = 0;
1753
1754                 mrq.cmd = &cmd;
1755                 host->mrq = &mrq;
1756
1757                 /*
1758                  * In response to CMD19, the card sends 64 bytes of tuning
1759                  * block to the Host Controller. So we set the block size
1760                  * to 64 here.
1761                  */
1762                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1763
1764                 /*
1765                  * The tuning block is sent by the card to the host controller.
1766                  * So we set the TRNS_READ bit in the Transfer Mode register.
1767                  * This also takes care of setting DMA Enable and Multi Block
1768                  * Select in the same register to 0.
1769                  */
1770                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1771
1772                 sdhci_send_command(host, &cmd);
1773
1774                 host->cmd = NULL;
1775                 host->mrq = NULL;
1776
1777                 spin_unlock(&host->lock);
1778                 enable_irq(host->irq);
1779
1780                 /* Wait for Buffer Read Ready interrupt */
1781                 wait_event_interruptible_timeout(host->buf_ready_int,
1782                                         (host->tuning_done == 1),
1783                                         msecs_to_jiffies(50));
1784                 disable_irq(host->irq);
1785                 spin_lock(&host->lock);
1786
1787                 if (!host->tuning_done) {
1788                         pr_info(DRIVER_NAME ": Timeout waiting for "
1789                                 "Buffer Read Ready interrupt during tuning "
1790                                 "procedure, falling back to fixed sampling "
1791                                 "clock\n");
1792                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1793                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1794                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1795                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1796
1797                         err = -EIO;
1798                         goto out;
1799                 }
1800
1801                 host->tuning_done = 0;
1802
1803                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1804                 tuning_loop_counter--;
1805                 timeout--;
1806                 mdelay(1);
1807         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1808
1809         /*
1810          * The Host Driver has exhausted the maximum number of loops allowed,
1811          * so use fixed sampling frequency.
1812          */
1813         if (!tuning_loop_counter || !timeout) {
1814                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1815                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1816         } else {
1817                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1818                         pr_info(DRIVER_NAME ": Tuning procedure"
1819                                 " failed, falling back to fixed sampling"
1820                                 " clock\n");
1821                         err = -EIO;
1822                 }
1823         }
1824
1825 out:
1826         /*
1827          * If this is the very first time we are here, we start the retuning
1828          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1829          * flag won't be set, we check this condition before actually starting
1830          * the timer.
1831          */
1832         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1833             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1834                 mod_timer(&host->tuning_timer, jiffies +
1835                         host->tuning_count * HZ);
1836                 /* Tuning mode 1 limits the maximum data length to 4MB */
1837                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1838         } else {
1839                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1840                 /* Reload the new initial value for timer */
1841                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1842                         mod_timer(&host->tuning_timer, jiffies +
1843                                 host->tuning_count * HZ);
1844         }
1845
1846         /*
1847          * In case tuning fails, host controllers which support re-tuning can
1848          * try tuning again at a later time, when the re-tuning timer expires.
1849          * So for these controllers, we return 0. Since there might be other
1850          * controllers who do not have this capability, we return error for
1851          * them.
1852          */
1853         if (err && host->tuning_count &&
1854             host->tuning_mode == SDHCI_TUNING_MODE_1)
1855                 err = 0;
1856
1857         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1858         spin_unlock(&host->lock);
1859         enable_irq(host->irq);
1860         sdhci_runtime_pm_put(host);
1861
1862         return err;
1863 }
1864
1865 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1866 {
1867         u16 ctrl;
1868         unsigned long flags;
1869
1870         /* Host Controller v3.00 defines preset value registers */
1871         if (host->version < SDHCI_SPEC_300)
1872                 return;
1873
1874         spin_lock_irqsave(&host->lock, flags);
1875
1876         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1877
1878         /*
1879          * We only enable or disable Preset Value if they are not already
1880          * enabled or disabled respectively. Otherwise, we bail out.
1881          */
1882         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1883                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1884                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1885                 host->flags |= SDHCI_PV_ENABLED;
1886         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1887                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1888                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1889                 host->flags &= ~SDHCI_PV_ENABLED;
1890         }
1891
1892         spin_unlock_irqrestore(&host->lock, flags);
1893 }
1894
1895 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1896 {
1897         struct sdhci_host *host = mmc_priv(mmc);
1898
1899         sdhci_runtime_pm_get(host);
1900         sdhci_do_enable_preset_value(host, enable);
1901         sdhci_runtime_pm_put(host);
1902 }
1903
1904 static const struct mmc_host_ops sdhci_ops = {
1905         .request        = sdhci_request,
1906         .set_ios        = sdhci_set_ios,
1907         .get_ro         = sdhci_get_ro,
1908         .hw_reset       = sdhci_hw_reset,
1909         .enable_sdio_irq = sdhci_enable_sdio_irq,
1910         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1911         .execute_tuning                 = sdhci_execute_tuning,
1912         .enable_preset_value            = sdhci_enable_preset_value,
1913 };
1914
1915 /*****************************************************************************\
1916  *                                                                           *
1917  * Tasklets                                                                  *
1918  *                                                                           *
1919 \*****************************************************************************/
1920
1921 static void sdhci_tasklet_card(unsigned long param)
1922 {
1923         struct sdhci_host *host;
1924         unsigned long flags;
1925
1926         host = (struct sdhci_host*)param;
1927
1928         spin_lock_irqsave(&host->lock, flags);
1929
1930         /* Check host->mrq first in case we are runtime suspended */
1931         if (host->mrq &&
1932             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1933                 pr_err("%s: Card removed during transfer!\n",
1934                         mmc_hostname(host->mmc));
1935                 pr_err("%s: Resetting controller.\n",
1936                         mmc_hostname(host->mmc));
1937
1938                 sdhci_reset(host, SDHCI_RESET_CMD);
1939                 sdhci_reset(host, SDHCI_RESET_DATA);
1940
1941                 host->mrq->cmd->error = -ENOMEDIUM;
1942                 tasklet_schedule(&host->finish_tasklet);
1943         }
1944
1945         spin_unlock_irqrestore(&host->lock, flags);
1946
1947         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1948 }
1949
1950 static void sdhci_tasklet_finish(unsigned long param)
1951 {
1952         struct sdhci_host *host;
1953         unsigned long flags;
1954         struct mmc_request *mrq;
1955
1956         host = (struct sdhci_host*)param;
1957
1958         spin_lock_irqsave(&host->lock, flags);
1959
1960         /*
1961          * If this tasklet gets rescheduled while running, it will
1962          * be run again afterwards but without any active request.
1963          */
1964         if (!host->mrq) {
1965                 spin_unlock_irqrestore(&host->lock, flags);
1966                 return;
1967         }
1968
1969         del_timer(&host->timer);
1970
1971         mrq = host->mrq;
1972
1973         /*
1974          * The controller needs a reset of internal state machines
1975          * upon error conditions.
1976          */
1977         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1978             ((mrq->cmd && mrq->cmd->error) ||
1979                  (mrq->data && (mrq->data->error ||
1980                   (mrq->data->stop && mrq->data->stop->error))) ||
1981                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1982
1983                 /* Some controllers need this kick or reset won't work here */
1984                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1985                         unsigned int clock;
1986
1987                         /* This is to force an update */
1988                         clock = host->clock;
1989                         host->clock = 0;
1990                         sdhci_set_clock(host, clock);
1991                 }
1992
1993                 /* Spec says we should do both at the same time, but Ricoh
1994                    controllers do not like that. */
1995                 sdhci_reset(host, SDHCI_RESET_CMD);
1996                 sdhci_reset(host, SDHCI_RESET_DATA);
1997         }
1998
1999         host->mrq = NULL;
2000         host->cmd = NULL;
2001         host->data = NULL;
2002
2003 #ifndef SDHCI_USE_LEDS_CLASS
2004         sdhci_deactivate_led(host);
2005 #endif
2006
2007         mmiowb();
2008         spin_unlock_irqrestore(&host->lock, flags);
2009
2010         mmc_request_done(host->mmc, mrq);
2011         sdhci_runtime_pm_put(host);
2012 }
2013
2014 static void sdhci_timeout_timer(unsigned long data)
2015 {
2016         struct sdhci_host *host;
2017         unsigned long flags;
2018
2019         host = (struct sdhci_host*)data;
2020
2021         spin_lock_irqsave(&host->lock, flags);
2022
2023         if (host->mrq) {
2024                 pr_err("%s: Timeout waiting for hardware "
2025                         "interrupt.\n", mmc_hostname(host->mmc));
2026                 sdhci_dumpregs(host);
2027
2028                 if (host->data) {
2029                         host->data->error = -ETIMEDOUT;
2030                         sdhci_finish_data(host);
2031                 } else {
2032                         if (host->cmd)
2033                                 host->cmd->error = -ETIMEDOUT;
2034                         else
2035                                 host->mrq->cmd->error = -ETIMEDOUT;
2036
2037                         tasklet_schedule(&host->finish_tasklet);
2038                 }
2039         }
2040
2041         mmiowb();
2042         spin_unlock_irqrestore(&host->lock, flags);
2043 }
2044
2045 static void sdhci_tuning_timer(unsigned long data)
2046 {
2047         struct sdhci_host *host;
2048         unsigned long flags;
2049
2050         host = (struct sdhci_host *)data;
2051
2052         spin_lock_irqsave(&host->lock, flags);
2053
2054         host->flags |= SDHCI_NEEDS_RETUNING;
2055
2056         spin_unlock_irqrestore(&host->lock, flags);
2057 }
2058
2059 /*****************************************************************************\
2060  *                                                                           *
2061  * Interrupt handling                                                        *
2062  *                                                                           *
2063 \*****************************************************************************/
2064
2065 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2066 {
2067         BUG_ON(intmask == 0);
2068
2069         if (!host->cmd) {
2070                 pr_err("%s: Got command interrupt 0x%08x even "
2071                         "though no command operation was in progress.\n",
2072                         mmc_hostname(host->mmc), (unsigned)intmask);
2073                 sdhci_dumpregs(host);
2074                 return;
2075         }
2076
2077         if (intmask & SDHCI_INT_TIMEOUT)
2078                 host->cmd->error = -ETIMEDOUT;
2079         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2080                         SDHCI_INT_INDEX))
2081                 host->cmd->error = -EILSEQ;
2082
2083         if (host->cmd->error) {
2084                 tasklet_schedule(&host->finish_tasklet);
2085                 return;
2086         }
2087
2088         /*
2089          * The host can send and interrupt when the busy state has
2090          * ended, allowing us to wait without wasting CPU cycles.
2091          * Unfortunately this is overloaded on the "data complete"
2092          * interrupt, so we need to take some care when handling
2093          * it.
2094          *
2095          * Note: The 1.0 specification is a bit ambiguous about this
2096          *       feature so there might be some problems with older
2097          *       controllers.
2098          */
2099         if (host->cmd->flags & MMC_RSP_BUSY) {
2100                 if (host->cmd->data)
2101                         DBG("Cannot wait for busy signal when also "
2102                                 "doing a data transfer");
2103                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2104                         return;
2105
2106                 /* The controller does not support the end-of-busy IRQ,
2107                  * fall through and take the SDHCI_INT_RESPONSE */
2108         }
2109
2110         if (intmask & SDHCI_INT_RESPONSE)
2111                 sdhci_finish_command(host);
2112 }
2113
2114 #ifdef CONFIG_MMC_DEBUG
2115 static void sdhci_show_adma_error(struct sdhci_host *host)
2116 {
2117         const char *name = mmc_hostname(host->mmc);
2118         u8 *desc = host->adma_desc;
2119         __le32 *dma;
2120         __le16 *len;
2121         u8 attr;
2122
2123         sdhci_dumpregs(host);
2124
2125         while (true) {
2126                 dma = (__le32 *)(desc + 4);
2127                 len = (__le16 *)(desc + 2);
2128                 attr = *desc;
2129
2130                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2131                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2132
2133                 desc += 8;
2134
2135                 if (attr & 2)
2136                         break;
2137         }
2138 }
2139 #else
2140 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2141 #endif
2142
2143 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2144 {
2145         BUG_ON(intmask == 0);
2146
2147         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2148         if (intmask & SDHCI_INT_DATA_AVAIL) {
2149                 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2150                     MMC_SEND_TUNING_BLOCK) {
2151                         host->tuning_done = 1;
2152                         wake_up(&host->buf_ready_int);
2153                         return;
2154                 }
2155         }
2156
2157         if (!host->data) {
2158                 /*
2159                  * The "data complete" interrupt is also used to
2160                  * indicate that a busy state has ended. See comment
2161                  * above in sdhci_cmd_irq().
2162                  */
2163                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2164                         if (intmask & SDHCI_INT_DATA_END) {
2165                                 sdhci_finish_command(host);
2166                                 return;
2167                         }
2168                 }
2169
2170                 pr_err("%s: Got data interrupt 0x%08x even "
2171                         "though no data operation was in progress.\n",
2172                         mmc_hostname(host->mmc), (unsigned)intmask);
2173                 sdhci_dumpregs(host);
2174
2175                 return;
2176         }
2177
2178         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2179                 host->data->error = -ETIMEDOUT;
2180         else if (intmask & SDHCI_INT_DATA_END_BIT)
2181                 host->data->error = -EILSEQ;
2182         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2183                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2184                         != MMC_BUS_TEST_R)
2185                 host->data->error = -EILSEQ;
2186         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2187                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2188                 sdhci_show_adma_error(host);
2189                 host->data->error = -EIO;
2190         }
2191
2192         if (host->data->error)
2193                 sdhci_finish_data(host);
2194         else {
2195                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2196                         sdhci_transfer_pio(host);
2197
2198                 /*
2199                  * We currently don't do anything fancy with DMA
2200                  * boundaries, but as we can't disable the feature
2201                  * we need to at least restart the transfer.
2202                  *
2203                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2204                  * should return a valid address to continue from, but as
2205                  * some controllers are faulty, don't trust them.
2206                  */
2207                 if (intmask & SDHCI_INT_DMA_END) {
2208                         u32 dmastart, dmanow;
2209                         dmastart = sg_dma_address(host->data->sg);
2210                         dmanow = dmastart + host->data->bytes_xfered;
2211                         /*
2212                          * Force update to the next DMA block boundary.
2213                          */
2214                         dmanow = (dmanow &
2215                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2216                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2217                         host->data->bytes_xfered = dmanow - dmastart;
2218                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2219                                 " next 0x%08x\n",
2220                                 mmc_hostname(host->mmc), dmastart,
2221                                 host->data->bytes_xfered, dmanow);
2222                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2223                 }
2224
2225                 if (intmask & SDHCI_INT_DATA_END) {
2226                         if (host->cmd) {
2227                                 /*
2228                                  * Data managed to finish before the
2229                                  * command completed. Make sure we do
2230                                  * things in the proper order.
2231                                  */
2232                                 host->data_early = 1;
2233                         } else {
2234                                 sdhci_finish_data(host);
2235                         }
2236                 }
2237         }
2238 }
2239
2240 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2241 {
2242         irqreturn_t result;
2243         struct sdhci_host *host = dev_id;
2244         u32 intmask;
2245         int cardint = 0;
2246
2247         spin_lock(&host->lock);
2248
2249         if (host->runtime_suspended) {
2250                 spin_unlock(&host->lock);
2251                 pr_warning("%s: got irq while runtime suspended\n",
2252                        mmc_hostname(host->mmc));
2253                 return IRQ_HANDLED;
2254         }
2255
2256         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2257
2258         if (!intmask || intmask == 0xffffffff) {
2259                 result = IRQ_NONE;
2260                 goto out;
2261         }
2262
2263         DBG("*** %s got interrupt: 0x%08x\n",
2264                 mmc_hostname(host->mmc), intmask);
2265
2266         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2267                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2268                               SDHCI_CARD_PRESENT;
2269
2270                 /*
2271                  * There is a observation on i.mx esdhc.  INSERT bit will be
2272                  * immediately set again when it gets cleared, if a card is
2273                  * inserted.  We have to mask the irq to prevent interrupt
2274                  * storm which will freeze the system.  And the REMOVE gets
2275                  * the same situation.
2276                  *
2277                  * More testing are needed here to ensure it works for other
2278                  * platforms though.
2279                  */
2280                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2281                                                 SDHCI_INT_CARD_REMOVE);
2282                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2283                                                   SDHCI_INT_CARD_INSERT);
2284
2285                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2286                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2287                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2288                 tasklet_schedule(&host->card_tasklet);
2289         }
2290
2291         if (intmask & SDHCI_INT_CMD_MASK) {
2292                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2293                         SDHCI_INT_STATUS);
2294                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2295         }
2296
2297         if (intmask & SDHCI_INT_DATA_MASK) {
2298                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2299                         SDHCI_INT_STATUS);
2300                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2301         }
2302
2303         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2304
2305         intmask &= ~SDHCI_INT_ERROR;
2306
2307         if (intmask & SDHCI_INT_BUS_POWER) {
2308                 pr_err("%s: Card is consuming too much power!\n",
2309                         mmc_hostname(host->mmc));
2310                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2311         }
2312
2313         intmask &= ~SDHCI_INT_BUS_POWER;
2314
2315         if (intmask & SDHCI_INT_CARD_INT)
2316                 cardint = 1;
2317
2318         intmask &= ~SDHCI_INT_CARD_INT;
2319
2320         if (intmask) {
2321                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2322                         mmc_hostname(host->mmc), intmask);
2323                 sdhci_dumpregs(host);
2324
2325                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2326         }
2327
2328         result = IRQ_HANDLED;
2329
2330         mmiowb();
2331 out:
2332         spin_unlock(&host->lock);
2333
2334         /*
2335          * We have to delay this as it calls back into the driver.
2336          */
2337         if (cardint)
2338                 mmc_signal_sdio_irq(host->mmc);
2339
2340         return result;
2341 }
2342
2343 /*****************************************************************************\
2344  *                                                                           *
2345  * Suspend/resume                                                            *
2346  *                                                                           *
2347 \*****************************************************************************/
2348
2349 #ifdef CONFIG_PM
2350
2351 int sdhci_suspend_host(struct sdhci_host *host)
2352 {
2353         int ret;
2354
2355         sdhci_disable_card_detection(host);
2356
2357         /* Disable tuning since we are suspending */
2358         if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2359             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2360                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2361                 mod_timer(&host->tuning_timer, jiffies +
2362                         host->tuning_count * HZ);
2363         }
2364
2365         ret = mmc_suspend_host(host->mmc);
2366         if (ret)
2367                 return ret;
2368
2369         free_irq(host->irq, host);
2370
2371         return ret;
2372 }
2373
2374 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2375
2376 int sdhci_resume_host(struct sdhci_host *host)
2377 {
2378         int ret;
2379
2380         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2381                 if (host->ops->enable_dma)
2382                         host->ops->enable_dma(host);
2383         }
2384
2385         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2386                           mmc_hostname(host->mmc), host);
2387         if (ret)
2388                 return ret;
2389
2390         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2391         mmiowb();
2392
2393         ret = mmc_resume_host(host->mmc);
2394         sdhci_enable_card_detection(host);
2395
2396         /* Set the re-tuning expiration flag */
2397         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2398             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2399                 host->flags |= SDHCI_NEEDS_RETUNING;
2400
2401         return ret;
2402 }
2403
2404 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2405
2406 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2407 {
2408         u8 val;
2409         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2410         val |= SDHCI_WAKE_ON_INT;
2411         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2412 }
2413
2414 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2415
2416 #endif /* CONFIG_PM */
2417
2418 #ifdef CONFIG_PM_RUNTIME
2419
2420 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2421 {
2422         return pm_runtime_get_sync(host->mmc->parent);
2423 }
2424
2425 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2426 {
2427         pm_runtime_mark_last_busy(host->mmc->parent);
2428         return pm_runtime_put_autosuspend(host->mmc->parent);
2429 }
2430
2431 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2432 {
2433         unsigned long flags;
2434         int ret = 0;
2435
2436         /* Disable tuning since we are suspending */
2437         if (host->version >= SDHCI_SPEC_300 &&
2438             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2439                 del_timer_sync(&host->tuning_timer);
2440                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2441         }
2442
2443         spin_lock_irqsave(&host->lock, flags);
2444         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2445         spin_unlock_irqrestore(&host->lock, flags);
2446
2447         synchronize_irq(host->irq);
2448
2449         spin_lock_irqsave(&host->lock, flags);
2450         host->runtime_suspended = true;
2451         spin_unlock_irqrestore(&host->lock, flags);
2452
2453         return ret;
2454 }
2455 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2456
2457 int sdhci_runtime_resume_host(struct sdhci_host *host)
2458 {
2459         unsigned long flags;
2460         int ret = 0, host_flags = host->flags;
2461
2462         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2463                 if (host->ops->enable_dma)
2464                         host->ops->enable_dma(host);
2465         }
2466
2467         sdhci_init(host, 0);
2468
2469         /* Force clock and power re-program */
2470         host->pwr = 0;
2471         host->clock = 0;
2472         sdhci_do_set_ios(host, &host->mmc->ios);
2473
2474         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2475         if (host_flags & SDHCI_PV_ENABLED)
2476                 sdhci_do_enable_preset_value(host, true);
2477
2478         /* Set the re-tuning expiration flag */
2479         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2480             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2481                 host->flags |= SDHCI_NEEDS_RETUNING;
2482
2483         spin_lock_irqsave(&host->lock, flags);
2484
2485         host->runtime_suspended = false;
2486
2487         /* Enable SDIO IRQ */
2488         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2489                 sdhci_enable_sdio_irq_nolock(host, true);
2490
2491         /* Enable Card Detection */
2492         sdhci_enable_card_detection(host);
2493
2494         spin_unlock_irqrestore(&host->lock, flags);
2495
2496         return ret;
2497 }
2498 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2499
2500 #endif
2501
2502 /*****************************************************************************\
2503  *                                                                           *
2504  * Device allocation/registration                                            *
2505  *                                                                           *
2506 \*****************************************************************************/
2507
2508 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2509         size_t priv_size)
2510 {
2511         struct mmc_host *mmc;
2512         struct sdhci_host *host;
2513
2514         WARN_ON(dev == NULL);
2515
2516         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2517         if (!mmc)
2518                 return ERR_PTR(-ENOMEM);
2519
2520         host = mmc_priv(mmc);
2521         host->mmc = mmc;
2522
2523         return host;
2524 }
2525
2526 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2527
2528 int sdhci_add_host(struct sdhci_host *host)
2529 {
2530         struct mmc_host *mmc;
2531         u32 caps[2];
2532         u32 max_current_caps;
2533         unsigned int ocr_avail;
2534         int ret;
2535
2536         WARN_ON(host == NULL);
2537         if (host == NULL)
2538                 return -EINVAL;
2539
2540         mmc = host->mmc;
2541
2542         if (debug_quirks)
2543                 host->quirks = debug_quirks;
2544         if (debug_quirks2)
2545                 host->quirks2 = debug_quirks2;
2546
2547         sdhci_reset(host, SDHCI_RESET_ALL);
2548
2549         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2550         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2551                                 >> SDHCI_SPEC_VER_SHIFT;
2552         if (host->version > SDHCI_SPEC_300) {
2553                 pr_err("%s: Unknown controller version (%d). "
2554                         "You may experience problems.\n", mmc_hostname(mmc),
2555                         host->version);
2556         }
2557
2558         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2559                 sdhci_readl(host, SDHCI_CAPABILITIES);
2560
2561         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2562                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2563
2564         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2565                 host->flags |= SDHCI_USE_SDMA;
2566         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2567                 DBG("Controller doesn't have SDMA capability\n");
2568         else
2569                 host->flags |= SDHCI_USE_SDMA;
2570
2571         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2572                 (host->flags & SDHCI_USE_SDMA)) {
2573                 DBG("Disabling DMA as it is marked broken\n");
2574                 host->flags &= ~SDHCI_USE_SDMA;
2575         }
2576
2577         if ((host->version >= SDHCI_SPEC_200) &&
2578                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2579                 host->flags |= SDHCI_USE_ADMA;
2580
2581         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2582                 (host->flags & SDHCI_USE_ADMA)) {
2583                 DBG("Disabling ADMA as it is marked broken\n");
2584                 host->flags &= ~SDHCI_USE_ADMA;
2585         }
2586
2587         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2588                 if (host->ops->enable_dma) {
2589                         if (host->ops->enable_dma(host)) {
2590                                 pr_warning("%s: No suitable DMA "
2591                                         "available. Falling back to PIO.\n",
2592                                         mmc_hostname(mmc));
2593                                 host->flags &=
2594                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2595                         }
2596                 }
2597         }
2598
2599         if (host->flags & SDHCI_USE_ADMA) {
2600                 /*
2601                  * We need to allocate descriptors for all sg entries
2602                  * (128) and potentially one alignment transfer for
2603                  * each of those entries.
2604                  */
2605                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2606                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2607                 if (!host->adma_desc || !host->align_buffer) {
2608                         kfree(host->adma_desc);
2609                         kfree(host->align_buffer);
2610                         pr_warning("%s: Unable to allocate ADMA "
2611                                 "buffers. Falling back to standard DMA.\n",
2612                                 mmc_hostname(mmc));
2613                         host->flags &= ~SDHCI_USE_ADMA;
2614                 }
2615         }
2616
2617         /*
2618          * If we use DMA, then it's up to the caller to set the DMA
2619          * mask, but PIO does not need the hw shim so we set a new
2620          * mask here in that case.
2621          */
2622         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2623                 host->dma_mask = DMA_BIT_MASK(64);
2624                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2625         }
2626
2627         if (host->version >= SDHCI_SPEC_300)
2628                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2629                         >> SDHCI_CLOCK_BASE_SHIFT;
2630         else
2631                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2632                         >> SDHCI_CLOCK_BASE_SHIFT;
2633
2634         host->max_clk *= 1000000;
2635         if (host->max_clk == 0 || host->quirks &
2636                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2637                 if (!host->ops->get_max_clock) {
2638                         pr_err("%s: Hardware doesn't specify base clock "
2639                                "frequency.\n", mmc_hostname(mmc));
2640                         return -ENODEV;
2641                 }
2642                 host->max_clk = host->ops->get_max_clock(host);
2643         }
2644
2645         /*
2646          * In case of Host Controller v3.00, find out whether clock
2647          * multiplier is supported.
2648          */
2649         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2650                         SDHCI_CLOCK_MUL_SHIFT;
2651
2652         /*
2653          * In case the value in Clock Multiplier is 0, then programmable
2654          * clock mode is not supported, otherwise the actual clock
2655          * multiplier is one more than the value of Clock Multiplier
2656          * in the Capabilities Register.
2657          */
2658         if (host->clk_mul)
2659                 host->clk_mul += 1;
2660
2661         /*
2662          * Set host parameters.
2663          */
2664         mmc->ops = &sdhci_ops;
2665         mmc->f_max = host->max_clk;
2666         if (host->ops->get_min_clock)
2667                 mmc->f_min = host->ops->get_min_clock(host);
2668         else if (host->version >= SDHCI_SPEC_300) {
2669                 if (host->clk_mul) {
2670                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2671                         mmc->f_max = host->max_clk * host->clk_mul;
2672                 } else
2673                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2674         } else
2675                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2676
2677         host->timeout_clk =
2678                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2679         if (host->timeout_clk == 0) {
2680                 if (host->ops->get_timeout_clock) {
2681                         host->timeout_clk = host->ops->get_timeout_clock(host);
2682                 } else if (!(host->quirks &
2683                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2684                         pr_err("%s: Hardware doesn't specify timeout clock "
2685                                "frequency.\n", mmc_hostname(mmc));
2686                         return -ENODEV;
2687                 }
2688         }
2689         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2690                 host->timeout_clk *= 1000;
2691
2692         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2693                 host->timeout_clk = mmc->f_max / 1000;
2694
2695         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2696
2697         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2698
2699         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2700                 host->flags |= SDHCI_AUTO_CMD12;
2701
2702         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2703         if ((host->version >= SDHCI_SPEC_300) &&
2704             ((host->flags & SDHCI_USE_ADMA) ||
2705              !(host->flags & SDHCI_USE_SDMA))) {
2706                 host->flags |= SDHCI_AUTO_CMD23;
2707                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2708         } else {
2709                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2710         }
2711
2712         /*
2713          * A controller may support 8-bit width, but the board itself
2714          * might not have the pins brought out.  Boards that support
2715          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2716          * their platform code before calling sdhci_add_host(), and we
2717          * won't assume 8-bit width for hosts without that CAP.
2718          */
2719         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2720                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2721
2722         if (caps[0] & SDHCI_CAN_DO_HISPD)
2723                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2724
2725         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2726             mmc_card_is_removable(mmc))
2727                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2728
2729         /* UHS-I mode(s) supported by the host controller. */
2730         if (host->version >= SDHCI_SPEC_300)
2731                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2732
2733         /* SDR104 supports also implies SDR50 support */
2734         if (caps[1] & SDHCI_SUPPORT_SDR104)
2735                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2736         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2737                 mmc->caps |= MMC_CAP_UHS_SDR50;
2738
2739         if (caps[1] & SDHCI_SUPPORT_DDR50)
2740                 mmc->caps |= MMC_CAP_UHS_DDR50;
2741
2742         /* Does the host needs tuning for SDR50? */
2743         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2744                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2745
2746         /* Driver Type(s) (A, C, D) supported by the host */
2747         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2748                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2749         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2750                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2751         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2752                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2753
2754         /*
2755          * If Power Off Notify capability is enabled by the host,
2756          * set notify to short power off notify timeout value.
2757          */
2758         if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2759                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2760         else
2761                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2762
2763         /* Initial value for re-tuning timer count */
2764         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2765                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2766
2767         /*
2768          * In case Re-tuning Timer is not disabled, the actual value of
2769          * re-tuning timer will be 2 ^ (n - 1).
2770          */
2771         if (host->tuning_count)
2772                 host->tuning_count = 1 << (host->tuning_count - 1);
2773
2774         /* Re-tuning mode supported by the Host Controller */
2775         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2776                              SDHCI_RETUNING_MODE_SHIFT;
2777
2778         ocr_avail = 0;
2779         /*
2780          * According to SD Host Controller spec v3.00, if the Host System
2781          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2782          * the value is meaningful only if Voltage Support in the Capabilities
2783          * register is set. The actual current value is 4 times the register
2784          * value.
2785          */
2786         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2787
2788         if (caps[0] & SDHCI_CAN_VDD_330) {
2789                 int max_current_330;
2790
2791                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2792
2793                 max_current_330 = ((max_current_caps &
2794                                    SDHCI_MAX_CURRENT_330_MASK) >>
2795                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2796                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2797
2798                 if (max_current_330 > 150)
2799                         mmc->caps |= MMC_CAP_SET_XPC_330;
2800         }
2801         if (caps[0] & SDHCI_CAN_VDD_300) {
2802                 int max_current_300;
2803
2804                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2805
2806                 max_current_300 = ((max_current_caps &
2807                                    SDHCI_MAX_CURRENT_300_MASK) >>
2808                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2809                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2810
2811                 if (max_current_300 > 150)
2812                         mmc->caps |= MMC_CAP_SET_XPC_300;
2813         }
2814         if (caps[0] & SDHCI_CAN_VDD_180) {
2815                 int max_current_180;
2816
2817                 ocr_avail |= MMC_VDD_165_195;
2818
2819                 max_current_180 = ((max_current_caps &
2820                                    SDHCI_MAX_CURRENT_180_MASK) >>
2821                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2822                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2823
2824                 if (max_current_180 > 150)
2825                         mmc->caps |= MMC_CAP_SET_XPC_180;
2826
2827                 /* Maximum current capabilities of the host at 1.8V */
2828                 if (max_current_180 >= 800)
2829                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2830                 else if (max_current_180 >= 600)
2831                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2832                 else if (max_current_180 >= 400)
2833                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2834                 else
2835                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2836         }
2837
2838         mmc->ocr_avail = ocr_avail;
2839         mmc->ocr_avail_sdio = ocr_avail;
2840         if (host->ocr_avail_sdio)
2841                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2842         mmc->ocr_avail_sd = ocr_avail;
2843         if (host->ocr_avail_sd)
2844                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2845         else /* normal SD controllers don't support 1.8V */
2846                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2847         mmc->ocr_avail_mmc = ocr_avail;
2848         if (host->ocr_avail_mmc)
2849                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2850
2851         if (mmc->ocr_avail == 0) {
2852                 pr_err("%s: Hardware doesn't report any "
2853                         "support voltages.\n", mmc_hostname(mmc));
2854                 return -ENODEV;
2855         }
2856
2857         spin_lock_init(&host->lock);
2858
2859         /*
2860          * Maximum number of segments. Depends on if the hardware
2861          * can do scatter/gather or not.
2862          */
2863         if (host->flags & SDHCI_USE_ADMA)
2864                 mmc->max_segs = 128;
2865         else if (host->flags & SDHCI_USE_SDMA)
2866                 mmc->max_segs = 1;
2867         else /* PIO */
2868                 mmc->max_segs = 128;
2869
2870         /*
2871          * Maximum number of sectors in one transfer. Limited by DMA boundary
2872          * size (512KiB).
2873          */
2874         mmc->max_req_size = 524288;
2875
2876         /*
2877          * Maximum segment size. Could be one segment with the maximum number
2878          * of bytes. When doing hardware scatter/gather, each entry cannot
2879          * be larger than 64 KiB though.
2880          */
2881         if (host->flags & SDHCI_USE_ADMA) {
2882                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2883                         mmc->max_seg_size = 65535;
2884                 else
2885                         mmc->max_seg_size = 65536;
2886         } else {
2887                 mmc->max_seg_size = mmc->max_req_size;
2888         }
2889
2890         /*
2891          * Maximum block size. This varies from controller to controller and
2892          * is specified in the capabilities register.
2893          */
2894         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2895                 mmc->max_blk_size = 2;
2896         } else {
2897                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2898                                 SDHCI_MAX_BLOCK_SHIFT;
2899                 if (mmc->max_blk_size >= 3) {
2900                         pr_warning("%s: Invalid maximum block size, "
2901                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2902                         mmc->max_blk_size = 0;
2903                 }
2904         }
2905
2906         mmc->max_blk_size = 512 << mmc->max_blk_size;
2907
2908         /*
2909          * Maximum block count.
2910          */
2911         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2912
2913         /*
2914          * Init tasklets.
2915          */
2916         tasklet_init(&host->card_tasklet,
2917                 sdhci_tasklet_card, (unsigned long)host);
2918         tasklet_init(&host->finish_tasklet,
2919                 sdhci_tasklet_finish, (unsigned long)host);
2920
2921         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2922
2923         if (host->version >= SDHCI_SPEC_300) {
2924                 init_waitqueue_head(&host->buf_ready_int);
2925
2926                 /* Initialize re-tuning timer */
2927                 init_timer(&host->tuning_timer);
2928                 host->tuning_timer.data = (unsigned long)host;
2929                 host->tuning_timer.function = sdhci_tuning_timer;
2930         }
2931
2932         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2933                 mmc_hostname(mmc), host);
2934         if (ret)
2935                 goto untasklet;
2936
2937         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2938         if (IS_ERR(host->vmmc)) {
2939                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2940                 host->vmmc = NULL;
2941         }
2942
2943         sdhci_init(host, 0);
2944
2945 #ifdef CONFIG_MMC_DEBUG
2946         sdhci_dumpregs(host);
2947 #endif
2948
2949 #ifdef SDHCI_USE_LEDS_CLASS
2950         snprintf(host->led_name, sizeof(host->led_name),
2951                 "%s::", mmc_hostname(mmc));
2952         host->led.name = host->led_name;
2953         host->led.brightness = LED_OFF;
2954         host->led.default_trigger = mmc_hostname(mmc);
2955         host->led.brightness_set = sdhci_led_control;
2956
2957         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2958         if (ret)
2959                 goto reset;
2960 #endif
2961
2962         mmiowb();
2963
2964         mmc_add_host(mmc);
2965
2966         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
2967                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2968                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2969                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2970
2971         sdhci_enable_card_detection(host);
2972
2973         return 0;
2974
2975 #ifdef SDHCI_USE_LEDS_CLASS
2976 reset:
2977         sdhci_reset(host, SDHCI_RESET_ALL);
2978         free_irq(host->irq, host);
2979 #endif
2980 untasklet:
2981         tasklet_kill(&host->card_tasklet);
2982         tasklet_kill(&host->finish_tasklet);
2983
2984         return ret;
2985 }
2986
2987 EXPORT_SYMBOL_GPL(sdhci_add_host);
2988
2989 void sdhci_remove_host(struct sdhci_host *host, int dead)
2990 {
2991         unsigned long flags;
2992
2993         if (dead) {
2994                 spin_lock_irqsave(&host->lock, flags);
2995
2996                 host->flags |= SDHCI_DEVICE_DEAD;
2997
2998                 if (host->mrq) {
2999                         pr_err("%s: Controller removed during "
3000                                 " transfer!\n", mmc_hostname(host->mmc));
3001
3002                         host->mrq->cmd->error = -ENOMEDIUM;
3003                         tasklet_schedule(&host->finish_tasklet);
3004                 }
3005
3006                 spin_unlock_irqrestore(&host->lock, flags);
3007         }
3008
3009         sdhci_disable_card_detection(host);
3010
3011         mmc_remove_host(host->mmc);
3012
3013 #ifdef SDHCI_USE_LEDS_CLASS
3014         led_classdev_unregister(&host->led);
3015 #endif
3016
3017         if (!dead)
3018                 sdhci_reset(host, SDHCI_RESET_ALL);
3019
3020         free_irq(host->irq, host);
3021
3022         del_timer_sync(&host->timer);
3023         if (host->version >= SDHCI_SPEC_300)
3024                 del_timer_sync(&host->tuning_timer);
3025
3026         tasklet_kill(&host->card_tasklet);
3027         tasklet_kill(&host->finish_tasklet);
3028
3029         if (host->vmmc)
3030                 regulator_put(host->vmmc);
3031
3032         kfree(host->adma_desc);
3033         kfree(host->align_buffer);
3034
3035         host->adma_desc = NULL;
3036         host->align_buffer = NULL;
3037 }
3038
3039 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3040
3041 void sdhci_free_host(struct sdhci_host *host)
3042 {
3043         mmc_free_host(host->mmc);
3044 }
3045
3046 EXPORT_SYMBOL_GPL(sdhci_free_host);
3047
3048 /*****************************************************************************\
3049  *                                                                           *
3050  * Driver init/exit                                                          *
3051  *                                                                           *
3052 \*****************************************************************************/
3053
3054 static int __init sdhci_drv_init(void)
3055 {
3056         pr_info(DRIVER_NAME
3057                 ": Secure Digital Host Controller Interface driver\n");
3058         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3059
3060         return 0;
3061 }
3062
3063 static void __exit sdhci_drv_exit(void)
3064 {
3065 }
3066
3067 module_init(sdhci_drv_init);
3068 module_exit(sdhci_drv_exit);
3069
3070 module_param(debug_quirks, uint, 0444);
3071 module_param(debug_quirks2, uint, 0444);
3072
3073 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3074 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3075 MODULE_LICENSE("GPL");
3076
3077 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3078 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");