Pileus Git - ~andy/linux/blob - drivers/mmc/host/sdhci-esdhc-imx.c

   1 /*
   2  * Freescale eSDHC i.MX controller driver for the platform bus.
   3  *
   4  * derived from the OF-version.
   5  *
   6  * Copyright (c) 2010 Pengutronix e.K.
   7  *   Author: Wolfram Sang <w.sang@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/gpio.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/mmc/mmc.h>
  23 #include <linux/mmc/sdio.h>
  24 #include <linux/mmc/slot-gpio.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/platform_data/mmc-esdhc-imx.h>
  30 #include "sdhci-pltfm.h"
  31 #include "sdhci-esdhc.h"
  32
  33 #define ESDHC_CTRL_D3CD                 0x08
  34 /* VENDOR SPEC register */
  35 #define ESDHC_VENDOR_SPEC               0xc0
  36 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  37 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  38 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  39 #define ESDHC_WTMK_LVL                  0x44
  40 #define ESDHC_MIX_CTRL                  0x48
  41 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  42 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  43 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  44 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  45 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  46 /* Bits 3 and 6 are not SDHCI standard definitions */
  47 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  48
  49 /* dll control register */
  50 #define ESDHC_DLL_CTRL                  0x60
  51 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  52 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  53
  54 /* tune control register */
  55 #define ESDHC_TUNE_CTRL_STATUS          0x68
  56 #define  ESDHC_TUNE_CTRL_STEP           1
  57 #define  ESDHC_TUNE_CTRL_MIN            0
  58 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  59
  60 #define ESDHC_TUNING_CTRL               0xcc
  61 #define ESDHC_STD_TUNING_EN             (1 << 24)
  62 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  63 #define ESDHC_TUNING_START_TAP          0x1
  64
  65 #define ESDHC_TUNING_BLOCK_PATTERN_LEN  64
  66
  67 /* pinctrl state */
  68 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
  69 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
  70
  71 /*
  72  * Our interpretation of the SDHCI_HOST_CONTROL register
  73  */
  74 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
  75 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
  76 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
  77
  78 /*
  79  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
  80  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
  81  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
  82  * Define this macro DMA error INT for fsl eSDHC
  83  */
  84 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
  85
  86 /*
  87  * The CMDTYPE of the CMD register (offset 0xE) should be set to
  88  * "11" when the STOP CMD12 is issued on imx53 to abort one
  89  * open ended multi-blk IO. Otherwise the TC INT wouldn't
  90  * be generated.
  91  * In exact block transfer, the controller doesn't complete the
  92  * operations automatically as required at the end of the
  93  * transfer and remains on hold if the abort command is not sent.
  94  * As a result, the TC flag is not asserted and SW  received timeout
  95  * exeception. Bit1 of Vendor Spec registor is used to fix it.
  96  */
  97 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
  98 /*
  99  * The flag enables the workaround for ESDHC errata ENGcm07207 which
 100  * affects i.MX25 and i.MX35.
 101  */
 102 #define ESDHC_FLAG_ENGCM07207           BIT(2)
 103 /*
 104  * The flag tells that the ESDHC controller is an USDHC block that is
 105  * integrated on the i.MX6 series.
 106  */
 107 #define ESDHC_FLAG_USDHC                BIT(3)
 108 /* The IP supports manual tuning process */
 109 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 110 /* The IP supports standard tuning process */
 111 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 112 /* The IP has SDHCI_CAPABILITIES_1 register */
 113 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 114
 115 struct esdhc_soc_data {
 116         u32 flags;
 117 };
 118
 119 static struct esdhc_soc_data esdhc_imx25_data = {
 120         .flags = ESDHC_FLAG_ENGCM07207,
 121 };
 122
 123 static struct esdhc_soc_data esdhc_imx35_data = {
 124         .flags = ESDHC_FLAG_ENGCM07207,
 125 };
 126
 127 static struct esdhc_soc_data esdhc_imx51_data = {
 128         .flags = 0,
 129 };
 130
 131 static struct esdhc_soc_data esdhc_imx53_data = {
 132         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 133 };
 134
 135 static struct esdhc_soc_data usdhc_imx6q_data = {
 136         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
 137 };
 138
 139 static struct esdhc_soc_data usdhc_imx6sl_data = {
 140         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 141                         | ESDHC_FLAG_HAVE_CAP1,
 142 };
 143
 144 struct pltfm_imx_data {
 145         u32 scratchpad;
 146         struct pinctrl *pinctrl;
 147         struct pinctrl_state *pins_default;
 148         struct pinctrl_state *pins_100mhz;
 149         struct pinctrl_state *pins_200mhz;
 150         const struct esdhc_soc_data *socdata;
 151         struct esdhc_platform_data boarddata;
 152         struct clk *clk_ipg;
 153         struct clk *clk_ahb;
 154         struct clk *clk_per;
 155         enum {
 156                 NO_CMD_PENDING,      /* no multiblock command pending*/
 157                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 158                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 159         } multiblock_status;
 160         u32 uhs_mode;
 161         u32 is_ddr;
 162 };
 163
 164 static struct platform_device_id imx_esdhc_devtype[] = {
 165         {
 166                 .name = "sdhci-esdhc-imx25",
 167                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
 168         }, {
 169                 .name = "sdhci-esdhc-imx35",
 170                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
 171         }, {
 172                 .name = "sdhci-esdhc-imx51",
 173                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
 174         }, {
 175                 /* sentinel */
 176         }
 177 };
 178 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
 179
 180 static const struct of_device_id imx_esdhc_dt_ids[] = {
 181         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 182         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 183         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 184         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 185         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 186         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 187         { /* sentinel */ }
 188 };
 189 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 190
 191 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 192 {
 193         return data->socdata == &esdhc_imx25_data;
 194 }
 195
 196 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 197 {
 198         return data->socdata == &esdhc_imx53_data;
 199 }
 200
 201 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 202 {
 203         return data->socdata == &usdhc_imx6q_data;
 204 }
 205
 206 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 207 {
 208         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 209 }
 210
 211 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 212 {
 213         void __iomem *base = host->ioaddr + (reg & ~0x3);
 214         u32 shift = (reg & 0x3) * 8;
 215
 216         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 217 }
 218
 219 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 220 {
 221         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 222         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 223         u32 val = readl(host->ioaddr + reg);
 224
 225         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 226                 u32 fsl_prss = val;
 227                 /* save the least 20 bits */
 228                 val = fsl_prss & 0x000FFFFF;
 229                 /* move dat[0-3] bits */
 230                 val |= (fsl_prss & 0x0F000000) >> 4;
 231                 /* move cmd line bit */
 232                 val |= (fsl_prss & 0x00800000) << 1;
 233         }
 234
 235         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 236                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 237                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 238                         val &= 0xffff0000;
 239
 240                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 241                  * ADMA2 capability of esdhc, but this bit is messed up on
 242                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 243                  * don't actually support ADMA2). So set the BROKEN_ADMA
 244                  * uirk on MX25/35 platforms.
 245                  */
 246
 247                 if (val & SDHCI_CAN_DO_ADMA1) {
 248                         val &= ~SDHCI_CAN_DO_ADMA1;
 249                         val |= SDHCI_CAN_DO_ADMA2;
 250                 }
 251         }
 252
 253         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 254                 if (esdhc_is_usdhc(imx_data)) {
 255                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 256                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 257                         else
 258                                 /* imx6q/dl does not have cap_1 register, fake one */
 259                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 260                                         | SDHCI_SUPPORT_SDR50
 261                                         | SDHCI_USE_SDR50_TUNING;
 262                 }
 263         }
 264
 265         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 266                 val = 0;
 267                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 268                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 269                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 270         }
 271
 272         if (unlikely(reg == SDHCI_INT_STATUS)) {
 273                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 274                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 275                         val |= SDHCI_INT_ADMA_ERROR;
 276                 }
 277
 278                 /*
 279                  * mask off the interrupt we get in response to the manually
 280                  * sent CMD12
 281                  */
 282                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 283                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 284                         val &= ~SDHCI_INT_RESPONSE;
 285                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 286                                                    SDHCI_INT_STATUS);
 287                         imx_data->multiblock_status = NO_CMD_PENDING;
 288                 }
 289         }
 290
 291         return val;
 292 }
 293
 294 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 295 {
 296         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 297         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 298         u32 data;
 299
 300         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 301                 if (val & SDHCI_INT_CARD_INT) {
 302                         /*
 303                          * Clear and then set D3CD bit to avoid missing the
 304                          * card interrupt.  This is a eSDHC controller problem
 305                          * so we need to apply the following workaround: clear
 306                          * and set D3CD bit will make eSDHC re-sample the card
 307                          * interrupt. In case a card interrupt was lost,
 308                          * re-sample it by the following steps.
 309                          */
 310                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 311                         data &= ~ESDHC_CTRL_D3CD;
 312                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 313                         data |= ESDHC_CTRL_D3CD;
 314                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 315                 }
 316         }
 317
 318         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 319                                 && (reg == SDHCI_INT_STATUS)
 320                                 && (val & SDHCI_INT_DATA_END))) {
 321                         u32 v;
 322                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 323                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 324                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 325
 326                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 327                         {
 328                                 /* send a manual CMD12 with RESPTYP=none */
 329                                 data = MMC_STOP_TRANSMISSION << 24 |
 330                                        SDHCI_CMD_ABORTCMD << 16;
 331                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 332                                 imx_data->multiblock_status = WAIT_FOR_INT;
 333                         }
 334         }
 335
 336         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 337                 if (val & SDHCI_INT_ADMA_ERROR) {
 338                         val &= ~SDHCI_INT_ADMA_ERROR;
 339                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 340                 }
 341         }
 342
 343         writel(val, host->ioaddr + reg);
 344 }
 345
 346 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 347 {
 348         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 349         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 350         u16 ret = 0;
 351         u32 val;
 352
 353         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 354                 reg ^= 2;
 355                 if (esdhc_is_usdhc(imx_data)) {
 356                         /*
 357                          * The usdhc register returns a wrong host version.
 358                          * Correct it here.
 359                          */
 360                         return SDHCI_SPEC_300;
 361                 }
 362         }
 363
 364         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 365                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 366                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 367                         ret |= SDHCI_CTRL_VDD_180;
 368
 369                 if (esdhc_is_usdhc(imx_data)) {
 370                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 371                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 372                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 373                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 374                                 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 375                 }
 376
 377                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 378                         ret |= SDHCI_CTRL_EXEC_TUNING;
 379                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 380                         ret |= SDHCI_CTRL_TUNED_CLK;
 381
 382                 ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK);
 383                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 384
 385                 return ret;
 386         }
 387
 388         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 389                 if (esdhc_is_usdhc(imx_data)) {
 390                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 391                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 392                         /* Swap AC23 bit */
 393                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 394                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 395                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 396                         }
 397                 } else {
 398                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 399                 }
 400
 401                 return ret;
 402         }
 403
 404         return readw(host->ioaddr + reg);
 405 }
 406
 407 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 408 {
 409         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 410         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 411         u32 new_val = 0;
 412
 413         switch (reg) {
 414         case SDHCI_CLOCK_CONTROL:
 415                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 416                 if (val & SDHCI_CLOCK_CARD_EN)
 417                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 418                 else
 419                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 420                         writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 421                 return;
 422         case SDHCI_HOST_CONTROL2:
 423                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 424                 if (val & SDHCI_CTRL_VDD_180)
 425                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 426                 else
 427                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 428                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 429                 imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK;
 430                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 431                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 432                         if (val & SDHCI_CTRL_TUNED_CLK)
 433                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 434                         else
 435                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 436                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 437                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 438                         u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 439                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 440                         new_val = readl(host->ioaddr + ESDHC_TUNING_CTRL);
 441                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 442                                 new_val |= ESDHC_STD_TUNING_EN |
 443                                                 ESDHC_TUNING_START_TAP;
 444                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 445                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 446                         } else {
 447                                 new_val &= ~ESDHC_STD_TUNING_EN;
 448                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 449                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 450                         }
 451
 452                         if (val & SDHCI_CTRL_TUNED_CLK)
 453                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 454                         else
 455                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 456
 457                         writel(new_val, host->ioaddr + ESDHC_TUNING_CTRL);
 458                         writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
 459                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 460                 }
 461                 return;
 462         case SDHCI_TRANSFER_MODE:
 463                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 464                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 465                                 && (host->cmd->data->blocks > 1)
 466                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 467                         u32 v;
 468                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 469                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 470                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 471                 }
 472
 473                 if (esdhc_is_usdhc(imx_data)) {
 474                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 475                         /* Swap AC23 bit */
 476                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 477                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 478                                 val |= ESDHC_MIX_CTRL_AC23EN;
 479                         }
 480                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 481                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 482                 } else {
 483                         /*
 484                          * Postpone this write, we must do it together with a
 485                          * command write that is down below.
 486                          */
 487                         imx_data->scratchpad = val;
 488                 }
 489                 return;
 490         case SDHCI_COMMAND:
 491                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 492                         val |= SDHCI_CMD_ABORTCMD;
 493
 494                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 495                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 496                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 497
 498                 if (esdhc_is_usdhc(imx_data))
 499                         writel(val << 16,
 500                                host->ioaddr + SDHCI_TRANSFER_MODE);
 501                 else
 502                         writel(val << 16 | imx_data->scratchpad,
 503                                host->ioaddr + SDHCI_TRANSFER_MODE);
 504                 return;
 505         case SDHCI_BLOCK_SIZE:
 506                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 507                 break;
 508         }
 509         esdhc_clrset_le(host, 0xffff, val, reg);
 510 }
 511
 512 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 513 {
 514         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 515         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 516         u32 new_val;
 517         u32 mask;
 518
 519         switch (reg) {
 520         case SDHCI_POWER_CONTROL:
 521                 /*
 522                  * FSL put some DMA bits here
 523                  * If your board has a regulator, code should be here
 524                  */
 525                 return;
 526         case SDHCI_HOST_CONTROL:
 527                 /* FSL messed up here, so we need to manually compose it. */
 528                 new_val = val & SDHCI_CTRL_LED;
 529                 /* ensure the endianness */
 530                 new_val |= ESDHC_HOST_CONTROL_LE;
 531                 /* bits 8&9 are reserved on mx25 */
 532                 if (!is_imx25_esdhc(imx_data)) {
 533                         /* DMA mode bits are shifted */
 534                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 535                 }
 536
 537                 /*
 538                  * Do not touch buswidth bits here. This is done in
 539                  * esdhc_pltfm_bus_width.
 540                  * Do not touch the D3CD bit either which is used for the
 541                  * SDIO interrupt errata workaround.
 542                  */
 543                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 544
 545                 esdhc_clrset_le(host, mask, new_val, reg);
 546                 return;
 547         }
 548         esdhc_clrset_le(host, 0xff, val, reg);
 549
 550         /*
 551          * The esdhc has a design violation to SDHC spec which tells
 552          * that software reset should not affect card detection circuit.
 553          * But esdhc clears its SYSCTL register bits [0..2] during the
 554          * software reset.  This will stop those clocks that card detection
 555          * circuit relies on.  To work around it, we turn the clocks on back
 556          * to keep card detection circuit functional.
 557          */
 558         if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
 559                 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 560                 /*
 561                  * The reset on usdhc fails to clear MIX_CTRL register.
 562                  * Do it manually here.
 563                  */
 564                 if (esdhc_is_usdhc(imx_data)) {
 565                         writel(0, host->ioaddr + ESDHC_MIX_CTRL);
 566                         imx_data->is_ddr = 0;
 567                 }
 568         }
 569 }
 570
 571 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 572 {
 573         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 574         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 575         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 576
 577         u32 f_host = clk_get_rate(pltfm_host->clk);
 578
 579         if (boarddata->f_max && (boarddata->f_max < f_host))
 580                 return boarddata->f_max;
 581         else
 582                 return f_host;
 583 }
 584
 585 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 586 {
 587         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 588
 589         return clk_get_rate(pltfm_host->clk) / 256 / 16;
 590 }
 591
 592 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 593                                          unsigned int clock)
 594 {
 595         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 596         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 597         unsigned int host_clock = clk_get_rate(pltfm_host->clk);
 598         int pre_div = 2;
 599         int div = 1;
 600         u32 temp, val;
 601
 602         if (clock == 0) {
 603                 if (esdhc_is_usdhc(imx_data)) {
 604                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 605                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 606                                         host->ioaddr + ESDHC_VENDOR_SPEC);
 607                 }
 608                 goto out;
 609         }
 610
 611         if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
 612                 pre_div = 1;
 613
 614         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 615         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 616                 | ESDHC_CLOCK_MASK);
 617         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 618
 619         while (host_clock / pre_div / 16 > clock && pre_div < 256)
 620                 pre_div *= 2;
 621
 622         while (host_clock / pre_div / div > clock && div < 16)
 623                 div++;
 624
 625         host->mmc->actual_clock = host_clock / pre_div / div;
 626         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 627                 clock, host->mmc->actual_clock);
 628
 629         if (imx_data->is_ddr)
 630                 pre_div >>= 2;
 631         else
 632                 pre_div >>= 1;
 633         div--;
 634
 635         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 636         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 637                 | (div << ESDHC_DIVIDER_SHIFT)
 638                 | (pre_div << ESDHC_PREDIV_SHIFT));
 639         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 640
 641         if (esdhc_is_usdhc(imx_data)) {
 642                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 643                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 644                 host->ioaddr + ESDHC_VENDOR_SPEC);
 645         }
 646
 647         mdelay(1);
 648 out:
 649         host->clock = clock;
 650 }
 651
 652 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 653 {
 654         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 655         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 656         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 657
 658         switch (boarddata->wp_type) {
 659         case ESDHC_WP_GPIO:
 660                 return mmc_gpio_get_ro(host->mmc);
 661         case ESDHC_WP_CONTROLLER:
 662                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 663                                SDHCI_WRITE_PROTECT);
 664         case ESDHC_WP_NONE:
 665                 break;
 666         }
 667
 668         return -ENOSYS;
 669 }
 670
 671 static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
 672 {
 673         u32 ctrl;
 674
 675         switch (width) {
 676         case MMC_BUS_WIDTH_8:
 677                 ctrl = ESDHC_CTRL_8BITBUS;
 678                 break;
 679         case MMC_BUS_WIDTH_4:
 680                 ctrl = ESDHC_CTRL_4BITBUS;
 681                 break;
 682         default:
 683                 ctrl = 0;
 684                 break;
 685         }
 686
 687         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 688                         SDHCI_HOST_CONTROL);
 689
 690         return 0;
 691 }
 692
 693 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 694 {
 695         u32 reg;
 696
 697         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 698         mdelay(1);
 699
 700         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 701         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 702                         ESDHC_MIX_CTRL_FBCLK_SEL;
 703         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 704         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 705         dev_dbg(mmc_dev(host->mmc),
 706                 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 707                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 708 }
 709
 710 static void esdhc_request_done(struct mmc_request *mrq)
 711 {
 712         complete(&mrq->completion);
 713 }
 714
 715 static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode)
 716 {
 717         struct mmc_command cmd = {0};
 718         struct mmc_request mrq = {0};
 719         struct mmc_data data = {0};
 720         struct scatterlist sg;
 721         char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN];
 722
 723         cmd.opcode = opcode;
 724         cmd.arg = 0;
 725         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 726
 727         data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
 728         data.blocks = 1;
 729         data.flags = MMC_DATA_READ;
 730         data.sg = &sg;
 731         data.sg_len = 1;
 732
 733         sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern));
 734
 735         mrq.cmd = &cmd;
 736         mrq.cmd->mrq = &mrq;
 737         mrq.data = &data;
 738         mrq.data->mrq = &mrq;
 739         mrq.cmd->data = mrq.data;
 740
 741         mrq.done = esdhc_request_done;
 742         init_completion(&(mrq.completion));
 743
 744         disable_irq(host->irq);
 745         spin_lock(&host->lock);
 746         host->mrq = &mrq;
 747
 748         sdhci_send_command(host, mrq.cmd);
 749
 750         spin_unlock(&host->lock);
 751         enable_irq(host->irq);
 752
 753         wait_for_completion(&mrq.completion);
 754
 755         if (cmd.error)
 756                 return cmd.error;
 757         if (data.error)
 758                 return data.error;
 759
 760         return 0;
 761 }
 762
 763 static void esdhc_post_tuning(struct sdhci_host *host)
 764 {
 765         u32 reg;
 766
 767         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 768         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 769         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 770 }
 771
 772 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 773 {
 774         int min, max, avg, ret;
 775
 776         /* find the mininum delay first which can pass tuning */
 777         min = ESDHC_TUNE_CTRL_MIN;
 778         while (min < ESDHC_TUNE_CTRL_MAX) {
 779                 esdhc_prepare_tuning(host, min);
 780                 if (!esdhc_send_tuning_cmd(host, opcode))
 781                         break;
 782                 min += ESDHC_TUNE_CTRL_STEP;
 783         }
 784
 785         /* find the maxinum delay which can not pass tuning */
 786         max = min + ESDHC_TUNE_CTRL_STEP;
 787         while (max < ESDHC_TUNE_CTRL_MAX) {
 788                 esdhc_prepare_tuning(host, max);
 789                 if (esdhc_send_tuning_cmd(host, opcode)) {
 790                         max -= ESDHC_TUNE_CTRL_STEP;
 791                         break;
 792                 }
 793                 max += ESDHC_TUNE_CTRL_STEP;
 794         }
 795
 796         /* use average delay to get the best timing */
 797         avg = (min + max) / 2;
 798         esdhc_prepare_tuning(host, avg);
 799         ret = esdhc_send_tuning_cmd(host, opcode);
 800         esdhc_post_tuning(host);
 801
 802         dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
 803                 ret ? "failed" : "passed", avg, ret);
 804
 805         return ret;
 806 }
 807
 808 static int esdhc_change_pinstate(struct sdhci_host *host,
 809                                                 unsigned int uhs)
 810 {
 811         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 812         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 813         struct pinctrl_state *pinctrl;
 814
 815         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
 816
 817         if (IS_ERR(imx_data->pinctrl) ||
 818                 IS_ERR(imx_data->pins_default) ||
 819                 IS_ERR(imx_data->pins_100mhz) ||
 820                 IS_ERR(imx_data->pins_200mhz))
 821                 return -EINVAL;
 822
 823         switch (uhs) {
 824         case MMC_TIMING_UHS_SDR50:
 825                 pinctrl = imx_data->pins_100mhz;
 826                 break;
 827         case MMC_TIMING_UHS_SDR104:
 828                 pinctrl = imx_data->pins_200mhz;
 829                 break;
 830         default:
 831                 /* back to default state for other legacy timing */
 832                 pinctrl = imx_data->pins_default;
 833         }
 834
 835         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
 836 }
 837
 838 static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 839 {
 840         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 841         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 842         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 843
 844         switch (uhs) {
 845         case MMC_TIMING_UHS_SDR12:
 846                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12;
 847                 break;
 848         case MMC_TIMING_UHS_SDR25:
 849                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25;
 850                 break;
 851         case MMC_TIMING_UHS_SDR50:
 852                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50;
 853                 break;
 854         case MMC_TIMING_UHS_SDR104:
 855                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104;
 856                 break;
 857         case MMC_TIMING_UHS_DDR50:
 858                 imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50;
 859                 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
 860                                 ESDHC_MIX_CTRL_DDREN,
 861                                 host->ioaddr + ESDHC_MIX_CTRL);
 862                 imx_data->is_ddr = 1;
 863                 if (boarddata->delay_line) {
 864                         u32 v;
 865                         v = boarddata->delay_line <<
 866                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
 867                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
 868                         if (is_imx53_esdhc(imx_data))
 869                                 v <<= 1;
 870                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
 871                 }
 872                 break;
 873         }
 874
 875         return esdhc_change_pinstate(host, uhs);
 876 }
 877
 878 static struct sdhci_ops sdhci_esdhc_ops = {
 879         .read_l = esdhc_readl_le,
 880         .read_w = esdhc_readw_le,
 881         .write_l = esdhc_writel_le,
 882         .write_w = esdhc_writew_le,
 883         .write_b = esdhc_writeb_le,
 884         .set_clock = esdhc_pltfm_set_clock,
 885         .get_max_clock = esdhc_pltfm_get_max_clock,
 886         .get_min_clock = esdhc_pltfm_get_min_clock,
 887         .get_ro = esdhc_pltfm_get_ro,
 888         .platform_bus_width = esdhc_pltfm_bus_width,
 889         .set_uhs_signaling = esdhc_set_uhs_signaling,
 890 };
 891
 892 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
 893         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
 894                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 895                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
 896                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 897         .ops = &sdhci_esdhc_ops,
 898 };
 899
 900 #ifdef CONFIG_OF
 901 static int
 902 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 903                          struct esdhc_platform_data *boarddata)
 904 {
 905         struct device_node *np = pdev->dev.of_node;
 906
 907         if (!np)
 908                 return -ENODEV;
 909
 910         if (of_get_property(np, "non-removable", NULL))
 911                 boarddata->cd_type = ESDHC_CD_PERMANENT;
 912
 913         if (of_get_property(np, "fsl,cd-controller", NULL))
 914                 boarddata->cd_type = ESDHC_CD_CONTROLLER;
 915
 916         if (of_get_property(np, "fsl,wp-controller", NULL))
 917                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
 918
 919         boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
 920         if (gpio_is_valid(boarddata->cd_gpio))
 921                 boarddata->cd_type = ESDHC_CD_GPIO;
 922
 923         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
 924         if (gpio_is_valid(boarddata->wp_gpio))
 925                 boarddata->wp_type = ESDHC_WP_GPIO;
 926
 927         of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
 928
 929         of_property_read_u32(np, "max-frequency", &boarddata->f_max);
 930
 931         if (of_find_property(np, "no-1-8-v", NULL))
 932                 boarddata->support_vsel = false;
 933         else
 934                 boarddata->support_vsel = true;
 935
 936         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
 937                 boarddata->delay_line = 0;
 938
 939         return 0;
 940 }
 941 #else
 942 static inline int
 943 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 944                          struct esdhc_platform_data *boarddata)
 945 {
 946         return -ENODEV;
 947 }
 948 #endif
 949
 950 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 951 {
 952         const struct of_device_id *of_id =
 953                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
 954         struct sdhci_pltfm_host *pltfm_host;
 955         struct sdhci_host *host;
 956         struct esdhc_platform_data *boarddata;
 957         int err;
 958         struct pltfm_imx_data *imx_data;
 959
 960         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
 961         if (IS_ERR(host))
 962                 return PTR_ERR(host);
 963
 964         pltfm_host = sdhci_priv(host);
 965
 966         imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
 967         if (!imx_data) {
 968                 err = -ENOMEM;
 969                 goto free_sdhci;
 970         }
 971
 972         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
 973                                                   pdev->id_entry->driver_data;
 974         pltfm_host->priv = imx_data;
 975
 976         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 977         if (IS_ERR(imx_data->clk_ipg)) {
 978                 err = PTR_ERR(imx_data->clk_ipg);
 979                 goto free_sdhci;
 980         }
 981
 982         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
 983         if (IS_ERR(imx_data->clk_ahb)) {
 984                 err = PTR_ERR(imx_data->clk_ahb);
 985                 goto free_sdhci;
 986         }
 987
 988         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
 989         if (IS_ERR(imx_data->clk_per)) {
 990                 err = PTR_ERR(imx_data->clk_per);
 991                 goto free_sdhci;
 992         }
 993
 994         pltfm_host->clk = imx_data->clk_per;
 995
 996         clk_prepare_enable(imx_data->clk_per);
 997         clk_prepare_enable(imx_data->clk_ipg);
 998         clk_prepare_enable(imx_data->clk_ahb);
 999
1000         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1001         if (IS_ERR(imx_data->pinctrl)) {
1002                 err = PTR_ERR(imx_data->pinctrl);
1003                 goto disable_clk;
1004         }
1005
1006         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1007                                                 PINCTRL_STATE_DEFAULT);
1008         if (IS_ERR(imx_data->pins_default)) {
1009                 err = PTR_ERR(imx_data->pins_default);
1010                 dev_err(mmc_dev(host->mmc), "could not get default state\n");
1011                 goto disable_clk;
1012         }
1013
1014         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1015
1016         if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1017                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1018                 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1019                         | SDHCI_QUIRK_BROKEN_ADMA;
1020
1021         /*
1022          * The imx6q ROM code will change the default watermark level setting
1023          * to something insane.  Change it back here.
1024          */
1025         if (esdhc_is_usdhc(imx_data)) {
1026                 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
1027                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1028         }
1029
1030         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1031                 sdhci_esdhc_ops.platform_execute_tuning =
1032                                         esdhc_executing_tuning;
1033         boarddata = &imx_data->boarddata;
1034         if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
1035                 if (!host->mmc->parent->platform_data) {
1036                         dev_err(mmc_dev(host->mmc), "no board data!\n");
1037                         err = -EINVAL;
1038                         goto disable_clk;
1039                 }
1040                 imx_data->boarddata = *((struct esdhc_platform_data *)
1041                                         host->mmc->parent->platform_data);
1042         }
1043
1044         /* write_protect */
1045         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1046                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1047                 if (err) {
1048                         dev_err(mmc_dev(host->mmc),
1049                                 "failed to request write-protect gpio!\n");
1050                         goto disable_clk;
1051                 }
1052                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1053         }
1054
1055         /* card_detect */
1056         switch (boarddata->cd_type) {
1057         case ESDHC_CD_GPIO:
1058                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1059                 if (err) {
1060                         dev_err(mmc_dev(host->mmc),
1061                                 "failed to request card-detect gpio!\n");
1062                         goto disable_clk;
1063                 }
1064                 /* fall through */
1065
1066         case ESDHC_CD_CONTROLLER:
1067                 /* we have a working card_detect back */
1068                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1069                 break;
1070
1071         case ESDHC_CD_PERMANENT:
1072                 host->mmc->caps = MMC_CAP_NONREMOVABLE;
1073                 break;
1074
1075         case ESDHC_CD_NONE:
1076                 break;
1077         }
1078
1079         switch (boarddata->max_bus_width) {
1080         case 8:
1081                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1082                 break;
1083         case 4:
1084                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1085                 break;
1086         case 1:
1087         default:
1088                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1089                 break;
1090         }
1091
1092         /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1093         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {
1094                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1095                                                 ESDHC_PINCTRL_STATE_100MHZ);
1096                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1097                                                 ESDHC_PINCTRL_STATE_200MHZ);
1098                 if (IS_ERR(imx_data->pins_100mhz) ||
1099                                 IS_ERR(imx_data->pins_200mhz)) {
1100                         dev_warn(mmc_dev(host->mmc),
1101                                 "could not get ultra high speed state, work on normal mode\n");
1102                         /* fall back to not support uhs by specify no 1.8v quirk */
1103                         host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1104                 }
1105         } else {
1106                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1107         }
1108
1109         err = sdhci_add_host(host);
1110         if (err)
1111                 goto disable_clk;
1112
1113         return 0;
1114
1115 disable_clk:
1116         clk_disable_unprepare(imx_data->clk_per);
1117         clk_disable_unprepare(imx_data->clk_ipg);
1118         clk_disable_unprepare(imx_data->clk_ahb);
1119 free_sdhci:
1120         sdhci_pltfm_free(pdev);
1121         return err;
1122 }
1123
1124 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1125 {
1126         struct sdhci_host *host = platform_get_drvdata(pdev);
1127         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1128         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1129         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1130
1131         sdhci_remove_host(host, dead);
1132
1133         clk_disable_unprepare(imx_data->clk_per);
1134         clk_disable_unprepare(imx_data->clk_ipg);
1135         clk_disable_unprepare(imx_data->clk_ahb);
1136
1137         sdhci_pltfm_free(pdev);
1138
1139         return 0;
1140 }
1141
1142 static struct platform_driver sdhci_esdhc_imx_driver = {
1143         .driver         = {
1144                 .name   = "sdhci-esdhc-imx",
1145                 .owner  = THIS_MODULE,
1146                 .of_match_table = imx_esdhc_dt_ids,
1147                 .pm     = SDHCI_PLTFM_PMOPS,
1148         },
1149         .id_table       = imx_esdhc_devtype,
1150         .probe          = sdhci_esdhc_imx_probe,
1151         .remove         = sdhci_esdhc_imx_remove,
1152 };
1153
1154 module_platform_driver(sdhci_esdhc_imx_driver);
1155
1156 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1157 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
1158 MODULE_LICENSE("GPL v2");