2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 * derived from pxamci.c by Russell King
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
38 #include <asm/sizes.h>
41 #ifdef CONFIG_ARCH_MX2
42 #include <mach/dma-mx1-mx2.h>
46 #define DRIVER_NAME "mxc-mmc"
48 #define MMC_REG_STR_STP_CLK 0x00
49 #define MMC_REG_STATUS 0x04
50 #define MMC_REG_CLK_RATE 0x08
51 #define MMC_REG_CMD_DAT_CONT 0x0C
52 #define MMC_REG_RES_TO 0x10
53 #define MMC_REG_READ_TO 0x14
54 #define MMC_REG_BLK_LEN 0x18
55 #define MMC_REG_NOB 0x1C
56 #define MMC_REG_REV_NO 0x20
57 #define MMC_REG_INT_CNTR 0x24
58 #define MMC_REG_CMD 0x28
59 #define MMC_REG_ARG 0x2C
60 #define MMC_REG_RES_FIFO 0x34
61 #define MMC_REG_BUFFER_ACCESS 0x38
63 #define STR_STP_CLK_RESET (1 << 3)
64 #define STR_STP_CLK_START_CLK (1 << 1)
65 #define STR_STP_CLK_STOP_CLK (1 << 0)
67 #define STATUS_CARD_INSERTION (1 << 31)
68 #define STATUS_CARD_REMOVAL (1 << 30)
69 #define STATUS_YBUF_EMPTY (1 << 29)
70 #define STATUS_XBUF_EMPTY (1 << 28)
71 #define STATUS_YBUF_FULL (1 << 27)
72 #define STATUS_XBUF_FULL (1 << 26)
73 #define STATUS_BUF_UND_RUN (1 << 25)
74 #define STATUS_BUF_OVFL (1 << 24)
75 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
76 #define STATUS_END_CMD_RESP (1 << 13)
77 #define STATUS_WRITE_OP_DONE (1 << 12)
78 #define STATUS_DATA_TRANS_DONE (1 << 11)
79 #define STATUS_READ_OP_DONE (1 << 11)
80 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
81 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
82 #define STATUS_BUF_READ_RDY (1 << 7)
83 #define STATUS_BUF_WRITE_RDY (1 << 6)
84 #define STATUS_RESP_CRC_ERR (1 << 5)
85 #define STATUS_CRC_READ_ERR (1 << 3)
86 #define STATUS_CRC_WRITE_ERR (1 << 2)
87 #define STATUS_TIME_OUT_RESP (1 << 1)
88 #define STATUS_TIME_OUT_READ (1 << 0)
89 #define STATUS_ERR_MASK 0x2f
91 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
92 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
93 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
94 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
95 #define CMD_DAT_CONT_INIT (1 << 7)
96 #define CMD_DAT_CONT_WRITE (1 << 4)
97 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
98 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
99 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
100 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
102 #define INT_SDIO_INT_WKP_EN (1 << 18)
103 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
104 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
105 #define INT_CARD_INSERTION_EN (1 << 15)
106 #define INT_CARD_REMOVAL_EN (1 << 14)
107 #define INT_SDIO_IRQ_EN (1 << 13)
108 #define INT_DAT0_EN (1 << 12)
109 #define INT_BUF_READ_EN (1 << 4)
110 #define INT_BUF_WRITE_EN (1 << 3)
111 #define INT_END_CMD_RES_EN (1 << 2)
112 #define INT_WRITE_OP_DONE_EN (1 << 1)
113 #define INT_READ_OP_EN (1 << 0)
116 struct mmc_host *mmc;
117 struct resource *res;
123 int default_irq_mask;
125 unsigned int power_mode;
126 struct imxmmc_platform_data *pdata;
128 struct mmc_request *req;
129 struct mmc_command *cmd;
130 struct mmc_data *data;
132 unsigned int dma_nents;
133 unsigned int datasize;
134 unsigned int dma_dir;
143 struct work_struct datawork;
146 struct regulator *vcc;
149 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
151 static inline void mxcmci_init_ocr(struct mxcmci_host *host)
153 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
155 if (IS_ERR(host->vcc)) {
158 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
159 if (host->pdata && host->pdata->ocr_avail)
160 dev_warn(mmc_dev(host->mmc),
161 "pdata->ocr_avail will not be used\n");
164 if (host->vcc == NULL) {
165 /* fall-back to platform data */
166 if (host->pdata && host->pdata->ocr_avail)
167 host->mmc->ocr_avail = host->pdata->ocr_avail;
169 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
173 static inline void mxcmci_set_power(struct mxcmci_host *host,
174 unsigned char power_mode,
178 if (power_mode == MMC_POWER_UP)
179 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
180 else if (power_mode == MMC_POWER_OFF)
181 mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
184 if (host->pdata && host->pdata->setpower)
185 host->pdata->setpower(mmc_dev(host->mmc), vdd);
188 static inline int mxcmci_use_dma(struct mxcmci_host *host)
193 static void mxcmci_softreset(struct mxcmci_host *host)
197 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
200 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
201 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
202 host->base + MMC_REG_STR_STP_CLK);
204 for (i = 0; i < 8; i++)
205 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
207 writew(0xff, host->base + MMC_REG_RES_TO);
210 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
212 unsigned int nob = data->blocks;
213 unsigned int blksz = data->blksz;
214 unsigned int datasize = nob * blksz;
216 struct scatterlist *sg;
220 if (data->flags & MMC_DATA_STREAM)
224 data->bytes_xfered = 0;
226 writew(nob, host->base + MMC_REG_NOB);
227 writew(blksz, host->base + MMC_REG_BLK_LEN);
228 host->datasize = datasize;
231 for_each_sg(data->sg, sg, data->sg_len, i) {
232 if (sg->offset & 3 || sg->length & 3) {
238 if (data->flags & MMC_DATA_READ) {
239 host->dma_dir = DMA_FROM_DEVICE;
240 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
241 data->sg_len, host->dma_dir);
243 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
245 host->res->start + MMC_REG_BUFFER_ACCESS,
248 host->dma_dir = DMA_TO_DEVICE;
249 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
250 data->sg_len, host->dma_dir);
252 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
254 host->res->start + MMC_REG_BUFFER_ACCESS,
259 dev_err(mmc_dev(host->mmc), "failed to setup DMA : %d\n", ret);
264 imx_dma_enable(host->dma);
269 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
272 u32 int_cntr = host->default_irq_mask;
275 WARN_ON(host->cmd != NULL);
278 switch (mmc_resp_type(cmd)) {
279 case MMC_RSP_R1: /* short CRC, OPCODE */
280 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
281 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
283 case MMC_RSP_R2: /* long 136 bit + CRC */
284 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
286 case MMC_RSP_R3: /* short */
287 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
292 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
294 cmd->error = -EINVAL;
298 int_cntr = INT_END_CMD_RES_EN;
300 if (mxcmci_use_dma(host))
301 int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN;
303 spin_lock_irqsave(&host->lock, flags);
305 int_cntr |= INT_SDIO_IRQ_EN;
306 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
307 spin_unlock_irqrestore(&host->lock, flags);
309 writew(cmd->opcode, host->base + MMC_REG_CMD);
310 writel(cmd->arg, host->base + MMC_REG_ARG);
311 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
316 static void mxcmci_finish_request(struct mxcmci_host *host,
317 struct mmc_request *req)
319 u32 int_cntr = host->default_irq_mask;
322 spin_lock_irqsave(&host->lock, flags);
324 int_cntr |= INT_SDIO_IRQ_EN;
325 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
326 spin_unlock_irqrestore(&host->lock, flags);
332 mmc_request_done(host->mmc, req);
335 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
337 struct mmc_data *data = host->data;
341 if (mxcmci_use_dma(host)) {
342 imx_dma_disable(host->dma);
343 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
348 if (stat & STATUS_ERR_MASK) {
349 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
351 if (stat & STATUS_CRC_READ_ERR) {
352 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
353 data->error = -EILSEQ;
354 } else if (stat & STATUS_CRC_WRITE_ERR) {
355 u32 err_code = (stat >> 9) & 0x3;
356 if (err_code == 2) { /* No CRC response */
357 dev_err(mmc_dev(host->mmc),
358 "%s: No CRC -ETIMEDOUT\n", __func__);
359 data->error = -ETIMEDOUT;
361 dev_err(mmc_dev(host->mmc),
362 "%s: -EILSEQ\n", __func__);
363 data->error = -EILSEQ;
365 } else if (stat & STATUS_TIME_OUT_READ) {
366 dev_err(mmc_dev(host->mmc),
367 "%s: read -ETIMEDOUT\n", __func__);
368 data->error = -ETIMEDOUT;
370 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
374 data->bytes_xfered = host->datasize;
377 data_error = data->error;
384 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
386 struct mmc_command *cmd = host->cmd;
393 if (stat & STATUS_TIME_OUT_RESP) {
394 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
395 cmd->error = -ETIMEDOUT;
396 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
397 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
398 cmd->error = -EILSEQ;
401 if (cmd->flags & MMC_RSP_PRESENT) {
402 if (cmd->flags & MMC_RSP_136) {
403 for (i = 0; i < 4; i++) {
404 a = readw(host->base + MMC_REG_RES_FIFO);
405 b = readw(host->base + MMC_REG_RES_FIFO);
406 cmd->resp[i] = a << 16 | b;
409 a = readw(host->base + MMC_REG_RES_FIFO);
410 b = readw(host->base + MMC_REG_RES_FIFO);
411 c = readw(host->base + MMC_REG_RES_FIFO);
412 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
417 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
420 unsigned long timeout = jiffies + HZ;
423 stat = readl(host->base + MMC_REG_STATUS);
424 if (stat & STATUS_ERR_MASK)
426 if (time_after(jiffies, timeout)) {
427 mxcmci_softreset(host);
428 mxcmci_set_clk_rate(host, host->clock);
429 return STATUS_TIME_OUT_READ;
437 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
443 stat = mxcmci_poll_status(host,
444 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
447 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
455 stat = mxcmci_poll_status(host,
456 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
459 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
460 memcpy(b, &tmp, bytes);
466 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
472 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
475 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
483 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
487 memcpy(&tmp, b, bytes);
488 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
491 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
498 static int mxcmci_transfer_data(struct mxcmci_host *host)
500 struct mmc_data *data = host->req->data;
501 struct scatterlist *sg;
507 if (data->flags & MMC_DATA_READ) {
508 for_each_sg(data->sg, sg, data->sg_len, i) {
509 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
512 host->datasize += sg->length;
515 for_each_sg(data->sg, sg, data->sg_len, i) {
516 stat = mxcmci_push(host, sg_virt(sg), sg->length);
519 host->datasize += sg->length;
521 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
528 static void mxcmci_datawork(struct work_struct *work)
530 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
532 int datastat = mxcmci_transfer_data(host);
534 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
535 host->base + MMC_REG_STATUS);
536 mxcmci_finish_data(host, datastat);
538 if (host->req->stop) {
539 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
540 mxcmci_finish_request(host, host->req);
544 mxcmci_finish_request(host, host->req);
549 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
551 struct mmc_data *data = host->data;
557 data_error = mxcmci_finish_data(host, stat);
559 mxcmci_read_response(host, stat);
562 if (host->req->stop) {
563 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
564 mxcmci_finish_request(host, host->req);
568 mxcmci_finish_request(host, host->req);
573 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
575 mxcmci_read_response(host, stat);
578 if (!host->data && host->req) {
579 mxcmci_finish_request(host, host->req);
583 /* For the DMA case the DMA engine handles the data transfer
584 * automatically. For non DMA we have to do it ourselves.
585 * Don't do it in interrupt context though.
587 if (!mxcmci_use_dma(host) && host->data)
588 schedule_work(&host->datawork);
592 static irqreturn_t mxcmci_irq(int irq, void *devid)
594 struct mxcmci_host *host = devid;
599 stat = readl(host->base + MMC_REG_STATUS);
600 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
601 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS);
603 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
605 spin_lock_irqsave(&host->lock, flags);
606 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
607 spin_unlock_irqrestore(&host->lock, flags);
610 if (mxcmci_use_dma(host) &&
611 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
612 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
613 host->base + MMC_REG_STATUS);
617 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
618 mmc_signal_sdio_irq(host->mmc);
621 if (stat & STATUS_END_CMD_RESP)
622 mxcmci_cmd_done(host, stat);
625 if (mxcmci_use_dma(host) &&
626 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
627 mxcmci_data_done(host, stat);
629 if (host->default_irq_mask &&
630 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
631 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
635 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
637 struct mxcmci_host *host = mmc_priv(mmc);
638 unsigned int cmdat = host->cmdat;
641 WARN_ON(host->req != NULL);
644 host->cmdat &= ~CMD_DAT_CONT_INIT;
649 error = mxcmci_setup_data(host, req->data);
651 req->cmd->error = error;
656 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
658 if (req->data->flags & MMC_DATA_WRITE)
659 cmdat |= CMD_DAT_CONT_WRITE;
662 error = mxcmci_start_cmd(host, req->cmd, cmdat);
665 mxcmci_finish_request(host, req);
668 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
670 unsigned int divider;
672 unsigned int clk_in = clk_get_rate(host->clk);
674 while (prescaler <= 0x800) {
675 for (divider = 1; divider <= 0xF; divider++) {
678 x = (clk_in / (divider + 1));
681 x /= (prescaler * 2);
695 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
697 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
698 prescaler, divider, clk_in, clk_ios);
701 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
703 struct mxcmci_host *host = mmc_priv(mmc);
707 * use burstlen of 64 in 4 bit mode (--> reg value 0)
708 * use burstlen of 16 in 1 bit mode (--> reg value 16)
710 if (ios->bus_width == MMC_BUS_WIDTH_4)
715 imx_dma_config_burstlen(host->dma, blen);
717 if (ios->bus_width == MMC_BUS_WIDTH_4)
718 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
720 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
722 if (host->power_mode != ios->power_mode) {
723 mxcmci_set_power(host, ios->power_mode, ios->vdd);
724 host->power_mode = ios->power_mode;
726 if (ios->power_mode == MMC_POWER_ON)
727 host->cmdat |= CMD_DAT_CONT_INIT;
731 mxcmci_set_clk_rate(host, ios->clock);
732 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
734 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
737 host->clock = ios->clock;
740 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
742 struct mmc_host *mmc = data;
744 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
746 mmc_detect_change(mmc, msecs_to_jiffies(250));
750 static int mxcmci_get_ro(struct mmc_host *mmc)
752 struct mxcmci_host *host = mmc_priv(mmc);
754 if (host->pdata && host->pdata->get_ro)
755 return !!host->pdata->get_ro(mmc_dev(mmc));
757 * Board doesn't support read only detection; let the mmc core
763 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
765 struct mxcmci_host *host = mmc_priv(mmc);
769 spin_lock_irqsave(&host->lock, flags);
770 host->use_sdio = enable;
771 int_cntr = readl(host->base + MMC_REG_INT_CNTR);
774 int_cntr |= INT_SDIO_IRQ_EN;
776 int_cntr &= ~INT_SDIO_IRQ_EN;
778 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
779 spin_unlock_irqrestore(&host->lock, flags);
782 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
785 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
786 * multi-block transfers when connected SDIO peripheral doesn't
787 * drive the BUSY line as required by the specs.
788 * One way to prevent this is to only allow 1-bit transfers.
791 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO)
792 host->caps &= ~MMC_CAP_4_BIT_DATA;
794 host->caps |= MMC_CAP_4_BIT_DATA;
797 static const struct mmc_host_ops mxcmci_ops = {
798 .request = mxcmci_request,
799 .set_ios = mxcmci_set_ios,
800 .get_ro = mxcmci_get_ro,
801 .enable_sdio_irq = mxcmci_enable_sdio_irq,
802 .init_card = mxcmci_init_card,
805 static int mxcmci_probe(struct platform_device *pdev)
807 struct mmc_host *mmc;
808 struct mxcmci_host *host = NULL;
809 struct resource *iores, *r;
812 printk(KERN_INFO "i.MX SDHC driver\n");
814 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
815 irq = platform_get_irq(pdev, 0);
816 if (!iores || irq < 0)
819 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
823 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
826 goto out_release_mem;
829 mmc->ops = &mxcmci_ops;
830 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
832 /* MMC core transfer sizes tunable parameters */
834 mmc->max_blk_size = 2048;
835 mmc->max_blk_count = 65535;
836 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
837 mmc->max_seg_size = mmc->max_req_size;
839 host = mmc_priv(mmc);
840 host->base = ioremap(r->start, resource_size(r));
847 host->pdata = pdev->dev.platform_data;
848 spin_lock_init(&host->lock);
850 mxcmci_init_ocr(host);
852 if (host->pdata && host->pdata->dat3_card_detect)
853 host->default_irq_mask =
854 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
856 host->default_irq_mask = 0;
861 host->clk = clk_get(&pdev->dev, NULL);
862 if (IS_ERR(host->clk)) {
863 ret = PTR_ERR(host->clk);
866 clk_enable(host->clk);
868 mxcmci_softreset(host);
870 host->rev_no = readw(host->base + MMC_REG_REV_NO);
871 if (host->rev_no != 0x400) {
873 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
878 mmc->f_min = clk_get_rate(host->clk) >> 16;
879 mmc->f_max = clk_get_rate(host->clk) >> 1;
881 /* recommended in data sheet */
882 writew(0x2db4, host->base + MMC_REG_READ_TO);
884 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR);
887 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
889 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
894 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
900 ret = imx_dma_config_channel(host->dma,
901 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
902 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
905 dev_err(mmc_dev(host->mmc), "failed to config DMA channel\n");
909 INIT_WORK(&host->datawork, mxcmci_datawork);
911 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
915 platform_set_drvdata(pdev, mmc);
917 if (host->pdata && host->pdata->init) {
918 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
929 free_irq(host->irq, host);
932 imx_dma_free(host->dma);
935 clk_disable(host->clk);
942 release_mem_region(iores->start, resource_size(iores));
946 static int mxcmci_remove(struct platform_device *pdev)
948 struct mmc_host *mmc = platform_get_drvdata(pdev);
949 struct mxcmci_host *host = mmc_priv(mmc);
951 platform_set_drvdata(pdev, NULL);
953 mmc_remove_host(mmc);
956 regulator_put(host->vcc);
958 if (host->pdata && host->pdata->exit)
959 host->pdata->exit(&pdev->dev, mmc);
961 free_irq(host->irq, host);
964 imx_dma_free(host->dma);
966 clk_disable(host->clk);
969 release_mem_region(host->res->start, resource_size(host->res));
977 static int mxcmci_suspend(struct device *dev)
979 struct mmc_host *mmc = dev_get_drvdata(dev);
980 struct mxcmci_host *host = mmc_priv(mmc);
984 ret = mmc_suspend_host(mmc);
985 clk_disable(host->clk);
990 static int mxcmci_resume(struct device *dev)
992 struct mmc_host *mmc = dev_get_drvdata(dev);
993 struct mxcmci_host *host = mmc_priv(mmc);
996 clk_enable(host->clk);
998 ret = mmc_resume_host(mmc);
1003 static const struct dev_pm_ops mxcmci_pm_ops = {
1004 .suspend = mxcmci_suspend,
1005 .resume = mxcmci_resume,
1009 static struct platform_driver mxcmci_driver = {
1010 .probe = mxcmci_probe,
1011 .remove = mxcmci_remove,
1013 .name = DRIVER_NAME,
1014 .owner = THIS_MODULE,
1016 .pm = &mxcmci_pm_ops,
1021 static int __init mxcmci_init(void)
1023 return platform_driver_register(&mxcmci_driver);
1026 static void __exit mxcmci_exit(void)
1028 platform_driver_unregister(&mxcmci_driver);
1031 module_init(mxcmci_init);
1032 module_exit(mxcmci_exit);
1034 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1035 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1036 MODULE_LICENSE("GPL");
1037 MODULE_ALIAS("platform:imx-mmc");