Pileus Git - ~andy/linux/blob - drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/scatterlist.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/slab.h>
  28 #include <linux/stat.h>
  29 #include <linux/delay.h>
  30 #include <linux/irq.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/dw_mmc.h>
  34 #include <linux/bitops.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/workqueue.h>
  37
  38 #include "dw_mmc.h"
  39
  40 /* Common flag combinations */
  41 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
  42                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  43                                  SDMMC_INT_EBE)
  44 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  45                                  SDMMC_INT_RESP_ERR)
  46 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  47                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  48 #define DW_MCI_SEND_STATUS      1
  49 #define DW_MCI_RECV_STATUS      2
  50 #define DW_MCI_DMA_THRESHOLD    16
  51
  52 #ifdef CONFIG_MMC_DW_IDMAC
  53 struct idmac_desc {
  54         u32             des0;   /* Control Descriptor */
  55 #define IDMAC_DES0_DIC  BIT(1)
  56 #define IDMAC_DES0_LD   BIT(2)
  57 #define IDMAC_DES0_FD   BIT(3)
  58 #define IDMAC_DES0_CH   BIT(4)
  59 #define IDMAC_DES0_ER   BIT(5)
  60 #define IDMAC_DES0_CES  BIT(30)
  61 #define IDMAC_DES0_OWN  BIT(31)
  62
  63         u32             des1;   /* Buffer sizes */
  64 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  65         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  66
  67         u32             des2;   /* buffer 1 physical address */
  68
  69         u32             des3;   /* buffer 2 physical address */
  70 };
  71 #endif /* CONFIG_MMC_DW_IDMAC */
  72
  73 /**
  74  * struct dw_mci_slot - MMC slot state
  75  * @mmc: The mmc_host representing this slot.
  76  * @host: The MMC controller this slot is using.
  77  * @ctype: Card type for this slot.
  78  * @mrq: mmc_request currently being processed or waiting to be
  79  *      processed, or NULL when the slot is idle.
  80  * @queue_node: List node for placing this node in the @queue list of
  81  *      &struct dw_mci.
  82  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  83  * @flags: Random state bits associated with the slot.
  84  * @id: Number of this slot.
  85  * @last_detect_state: Most recently observed card detect state.
  86  */
  87 struct dw_mci_slot {
  88         struct mmc_host         *mmc;
  89         struct dw_mci           *host;
  90
  91         u32                     ctype;
  92
  93         struct mmc_request      *mrq;
  94         struct list_head        queue_node;
  95
  96         unsigned int            clock;
  97         unsigned long           flags;
  98 #define DW_MMC_CARD_PRESENT     0
  99 #define DW_MMC_CARD_NEED_INIT   1
 100         int                     id;
 101         int                     last_detect_state;
 102 };
 103
 104 static struct workqueue_struct *dw_mci_card_workqueue;
 105
 106 #if defined(CONFIG_DEBUG_FS)
 107 static int dw_mci_req_show(struct seq_file *s, void *v)
 108 {
 109         struct dw_mci_slot *slot = s->private;
 110         struct mmc_request *mrq;
 111         struct mmc_command *cmd;
 112         struct mmc_command *stop;
 113         struct mmc_data *data;
 114
 115         /* Make sure we get a consistent snapshot */
 116         spin_lock_bh(&slot->host->lock);
 117         mrq = slot->mrq;
 118
 119         if (mrq) {
 120                 cmd = mrq->cmd;
 121                 data = mrq->data;
 122                 stop = mrq->stop;
 123
 124                 if (cmd)
 125                         seq_printf(s,
 126                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 127                                    cmd->opcode, cmd->arg, cmd->flags,
 128                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 129                                    cmd->resp[2], cmd->error);
 130                 if (data)
 131                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 132                                    data->bytes_xfered, data->blocks,
 133                                    data->blksz, data->flags, data->error);
 134                 if (stop)
 135                         seq_printf(s,
 136                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 137                                    stop->opcode, stop->arg, stop->flags,
 138                                    stop->resp[0], stop->resp[1], stop->resp[2],
 139                                    stop->resp[2], stop->error);
 140         }
 141
 142         spin_unlock_bh(&slot->host->lock);
 143
 144         return 0;
 145 }
 146
 147 static int dw_mci_req_open(struct inode *inode, struct file *file)
 148 {
 149         return single_open(file, dw_mci_req_show, inode->i_private);
 150 }
 151
 152 static const struct file_operations dw_mci_req_fops = {
 153         .owner          = THIS_MODULE,
 154         .open           = dw_mci_req_open,
 155         .read           = seq_read,
 156         .llseek         = seq_lseek,
 157         .release        = single_release,
 158 };
 159
 160 static int dw_mci_regs_show(struct seq_file *s, void *v)
 161 {
 162         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 163         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 164         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 165         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 166         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 167         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 168
 169         return 0;
 170 }
 171
 172 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 173 {
 174         return single_open(file, dw_mci_regs_show, inode->i_private);
 175 }
 176
 177 static const struct file_operations dw_mci_regs_fops = {
 178         .owner          = THIS_MODULE,
 179         .open           = dw_mci_regs_open,
 180         .read           = seq_read,
 181         .llseek         = seq_lseek,
 182         .release        = single_release,
 183 };
 184
 185 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 186 {
 187         struct mmc_host *mmc = slot->mmc;
 188         struct dw_mci *host = slot->host;
 189         struct dentry *root;
 190         struct dentry *node;
 191
 192         root = mmc->debugfs_root;
 193         if (!root)
 194                 return;
 195
 196         node = debugfs_create_file("regs", S_IRUSR, root, host,
 197                                    &dw_mci_regs_fops);
 198         if (!node)
 199                 goto err;
 200
 201         node = debugfs_create_file("req", S_IRUSR, root, slot,
 202                                    &dw_mci_req_fops);
 203         if (!node)
 204                 goto err;
 205
 206         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 207         if (!node)
 208                 goto err;
 209
 210         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 211                                   (u32 *)&host->pending_events);
 212         if (!node)
 213                 goto err;
 214
 215         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 216                                   (u32 *)&host->completed_events);
 217         if (!node)
 218                 goto err;
 219
 220         return;
 221
 222 err:
 223         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 224 }
 225 #endif /* defined(CONFIG_DEBUG_FS) */
 226
 227 static void dw_mci_set_timeout(struct dw_mci *host)
 228 {
 229         /* timeout (maximum) */
 230         mci_writel(host, TMOUT, 0xffffffff);
 231 }
 232
 233 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 234 {
 235         struct mmc_data *data;
 236         u32 cmdr;
 237         cmd->error = -EINPROGRESS;
 238
 239         cmdr = cmd->opcode;
 240
 241         if (cmdr == MMC_STOP_TRANSMISSION)
 242                 cmdr |= SDMMC_CMD_STOP;
 243         else
 244                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 245
 246         if (cmd->flags & MMC_RSP_PRESENT) {
 247                 /* We expect a response, so set this bit */
 248                 cmdr |= SDMMC_CMD_RESP_EXP;
 249                 if (cmd->flags & MMC_RSP_136)
 250                         cmdr |= SDMMC_CMD_RESP_LONG;
 251         }
 252
 253         if (cmd->flags & MMC_RSP_CRC)
 254                 cmdr |= SDMMC_CMD_RESP_CRC;
 255
 256         data = cmd->data;
 257         if (data) {
 258                 cmdr |= SDMMC_CMD_DAT_EXP;
 259                 if (data->flags & MMC_DATA_STREAM)
 260                         cmdr |= SDMMC_CMD_STRM_MODE;
 261                 if (data->flags & MMC_DATA_WRITE)
 262                         cmdr |= SDMMC_CMD_DAT_WR;
 263         }
 264
 265         return cmdr;
 266 }
 267
 268 static void dw_mci_start_command(struct dw_mci *host,
 269                                  struct mmc_command *cmd, u32 cmd_flags)
 270 {
 271         host->cmd = cmd;
 272         dev_vdbg(&host->pdev->dev,
 273                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 274                  cmd->arg, cmd_flags);
 275
 276         mci_writel(host, CMDARG, cmd->arg);
 277         wmb();
 278
 279         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 280 }
 281
 282 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 283 {
 284         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 285 }
 286
 287 /* DMA interface functions */
 288 static void dw_mci_stop_dma(struct dw_mci *host)
 289 {
 290         if (host->using_dma) {
 291                 host->dma_ops->stop(host);
 292                 host->dma_ops->cleanup(host);
 293         } else {
 294                 /* Data transfer was stopped by the interrupt handler */
 295                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 296         }
 297 }
 298
 299 #ifdef CONFIG_MMC_DW_IDMAC
 300 static void dw_mci_dma_cleanup(struct dw_mci *host)
 301 {
 302         struct mmc_data *data = host->data;
 303
 304         if (data)
 305                 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
 306                              ((data->flags & MMC_DATA_WRITE)
 307                               ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 308 }
 309
 310 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 311 {
 312         u32 temp;
 313
 314         /* Disable and reset the IDMAC interface */
 315         temp = mci_readl(host, CTRL);
 316         temp &= ~SDMMC_CTRL_USE_IDMAC;
 317         temp |= SDMMC_CTRL_DMA_RESET;
 318         mci_writel(host, CTRL, temp);
 319
 320         /* Stop the IDMAC running */
 321         temp = mci_readl(host, BMOD);
 322         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 323         mci_writel(host, BMOD, temp);
 324 }
 325
 326 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 327 {
 328         struct mmc_data *data = host->data;
 329
 330         dev_vdbg(&host->pdev->dev, "DMA complete\n");
 331
 332         host->dma_ops->cleanup(host);
 333
 334         /*
 335          * If the card was removed, data will be NULL. No point in trying to
 336          * send the stop command or waiting for NBUSY in this case.
 337          */
 338         if (data) {
 339                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 340                 tasklet_schedule(&host->tasklet);
 341         }
 342 }
 343
 344 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 345                                     unsigned int sg_len)
 346 {
 347         int i;
 348         struct idmac_desc *desc = host->sg_cpu;
 349
 350         for (i = 0; i < sg_len; i++, desc++) {
 351                 unsigned int length = sg_dma_len(&data->sg[i]);
 352                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 353
 354                 /* Set the OWN bit and disable interrupts for this descriptor */
 355                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 356
 357                 /* Buffer length */
 358                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 359
 360                 /* Physical address to DMA to/from */
 361                 desc->des2 = mem_addr;
 362         }
 363
 364         /* Set first descriptor */
 365         desc = host->sg_cpu;
 366         desc->des0 |= IDMAC_DES0_FD;
 367
 368         /* Set last descriptor */
 369         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 370         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 371         desc->des0 |= IDMAC_DES0_LD;
 372
 373         wmb();
 374 }
 375
 376 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 377 {
 378         u32 temp;
 379
 380         dw_mci_translate_sglist(host, host->data, sg_len);
 381
 382         /* Select IDMAC interface */
 383         temp = mci_readl(host, CTRL);
 384         temp |= SDMMC_CTRL_USE_IDMAC;
 385         mci_writel(host, CTRL, temp);
 386
 387         wmb();
 388
 389         /* Enable the IDMAC */
 390         temp = mci_readl(host, BMOD);
 391         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 392         mci_writel(host, BMOD, temp);
 393
 394         /* Start it running */
 395         mci_writel(host, PLDMND, 1);
 396 }
 397
 398 static int dw_mci_idmac_init(struct dw_mci *host)
 399 {
 400         struct idmac_desc *p;
 401         int i;
 402
 403         /* Number of descriptors in the ring buffer */
 404         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 405
 406         /* Forward link the descriptor list */
 407         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 408                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 409
 410         /* Set the last descriptor as the end-of-ring descriptor */
 411         p->des3 = host->sg_dma;
 412         p->des0 = IDMAC_DES0_ER;
 413
 414         /* Mask out interrupts - get Tx & Rx complete only */
 415         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 416                    SDMMC_IDMAC_INT_TI);
 417
 418         /* Set the descriptor base address */
 419         mci_writel(host, DBADDR, host->sg_dma);
 420         return 0;
 421 }
 422
 423 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
 424         .init = dw_mci_idmac_init,
 425         .start = dw_mci_idmac_start_dma,
 426         .stop = dw_mci_idmac_stop_dma,
 427         .complete = dw_mci_idmac_complete_dma,
 428         .cleanup = dw_mci_dma_cleanup,
 429 };
 430 #endif /* CONFIG_MMC_DW_IDMAC */
 431
 432 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 433 {
 434         struct scatterlist *sg;
 435         unsigned int i, direction, sg_len;
 436         u32 temp;
 437
 438         host->using_dma = 0;
 439
 440         /* If we don't have a channel, we can't do DMA */
 441         if (!host->use_dma)
 442                 return -ENODEV;
 443
 444         /*
 445          * We don't do DMA on "complex" transfers, i.e. with
 446          * non-word-aligned buffers or lengths. Also, we don't bother
 447          * with all the DMA setup overhead for short transfers.
 448          */
 449         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 450                 return -EINVAL;
 451         if (data->blksz & 3)
 452                 return -EINVAL;
 453
 454         for_each_sg(data->sg, sg, data->sg_len, i) {
 455                 if (sg->offset & 3 || sg->length & 3)
 456                         return -EINVAL;
 457         }
 458
 459         host->using_dma = 1;
 460
 461         if (data->flags & MMC_DATA_READ)
 462                 direction = DMA_FROM_DEVICE;
 463         else
 464                 direction = DMA_TO_DEVICE;
 465
 466         sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
 467                             direction);
 468
 469         dev_vdbg(&host->pdev->dev,
 470                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 471                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 472                  sg_len);
 473
 474         /* Enable the DMA interface */
 475         temp = mci_readl(host, CTRL);
 476         temp |= SDMMC_CTRL_DMA_ENABLE;
 477         mci_writel(host, CTRL, temp);
 478
 479         /* Disable RX/TX IRQs, let DMA handle it */
 480         temp = mci_readl(host, INTMASK);
 481         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 482         mci_writel(host, INTMASK, temp);
 483
 484         host->dma_ops->start(host, sg_len);
 485
 486         return 0;
 487 }
 488
 489 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 490 {
 491         u32 temp;
 492
 493         data->error = -EINPROGRESS;
 494
 495         WARN_ON(host->data);
 496         host->sg = NULL;
 497         host->data = data;
 498
 499         if (data->flags & MMC_DATA_READ)
 500                 host->dir_status = DW_MCI_RECV_STATUS;
 501         else
 502                 host->dir_status = DW_MCI_SEND_STATUS;
 503
 504         if (dw_mci_submit_data_dma(host, data)) {
 505                 host->sg = data->sg;
 506                 host->pio_offset = 0;
 507                 host->part_buf_start = 0;
 508                 host->part_buf_count = 0;
 509
 510                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 511                 temp = mci_readl(host, INTMASK);
 512                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 513                 mci_writel(host, INTMASK, temp);
 514
 515                 temp = mci_readl(host, CTRL);
 516                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 517                 mci_writel(host, CTRL, temp);
 518         }
 519 }
 520
 521 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 522 {
 523         struct dw_mci *host = slot->host;
 524         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 525         unsigned int cmd_status = 0;
 526
 527         mci_writel(host, CMDARG, arg);
 528         wmb();
 529         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 530
 531         while (time_before(jiffies, timeout)) {
 532                 cmd_status = mci_readl(host, CMD);
 533                 if (!(cmd_status & SDMMC_CMD_START))
 534                         return;
 535         }
 536         dev_err(&slot->mmc->class_dev,
 537                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 538                 cmd, arg, cmd_status);
 539 }
 540
 541 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
 542 {
 543         struct dw_mci *host = slot->host;
 544         u32 div;
 545
 546         if (slot->clock != host->current_speed) {
 547                 if (host->bus_hz % slot->clock)
 548                         /*
 549                          * move the + 1 after the divide to prevent
 550                          * over-clocking the card.
 551                          */
 552                         div = ((host->bus_hz / slot->clock) >> 1) + 1;
 553                 else
 554                         div = (host->bus_hz  / slot->clock) >> 1;
 555
 556                 dev_info(&slot->mmc->class_dev,
 557                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
 558                          " div = %d)\n", slot->id, host->bus_hz, slot->clock,
 559                          div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
 560
 561                 /* disable clock */
 562                 mci_writel(host, CLKENA, 0);
 563                 mci_writel(host, CLKSRC, 0);
 564
 565                 /* inform CIU */
 566                 mci_send_cmd(slot,
 567                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 568
 569                 /* set clock to desired speed */
 570                 mci_writel(host, CLKDIV, div);
 571
 572                 /* inform CIU */
 573                 mci_send_cmd(slot,
 574                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 575
 576                 /* enable clock */
 577                 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
 578                            SDMMC_CLKEN_LOW_PWR);
 579
 580                 /* inform CIU */
 581                 mci_send_cmd(slot,
 582                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 583
 584                 host->current_speed = slot->clock;
 585         }
 586
 587         /* Set the current slot bus width */
 588         mci_writel(host, CTYPE, (slot->ctype << slot->id));
 589 }
 590
 591 static void __dw_mci_start_request(struct dw_mci *host,
 592                                    struct dw_mci_slot *slot,
 593                                    struct mmc_command *cmd)
 594 {
 595         struct mmc_request *mrq;
 596         struct mmc_data *data;
 597         u32 cmdflags;
 598
 599         mrq = slot->mrq;
 600         if (host->pdata->select_slot)
 601                 host->pdata->select_slot(slot->id);
 602
 603         /* Slot specific timing and width adjustment */
 604         dw_mci_setup_bus(slot);
 605
 606         host->cur_slot = slot;
 607         host->mrq = mrq;
 608
 609         host->pending_events = 0;
 610         host->completed_events = 0;
 611         host->data_status = 0;
 612
 613         data = cmd->data;
 614         if (data) {
 615                 dw_mci_set_timeout(host);
 616                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
 617                 mci_writel(host, BLKSIZ, data->blksz);
 618         }
 619
 620         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 621
 622         /* this is the first command, send the initialization clock */
 623         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 624                 cmdflags |= SDMMC_CMD_INIT;
 625
 626         if (data) {
 627                 dw_mci_submit_data(host, data);
 628                 wmb();
 629         }
 630
 631         dw_mci_start_command(host, cmd, cmdflags);
 632
 633         if (mrq->stop)
 634                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 635 }
 636
 637 static void dw_mci_start_request(struct dw_mci *host,
 638                                  struct dw_mci_slot *slot)
 639 {
 640         struct mmc_request *mrq = slot->mrq;
 641         struct mmc_command *cmd;
 642
 643         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
 644         __dw_mci_start_request(host, slot, cmd);
 645 }
 646
 647 /* must be called with host->lock held */
 648 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 649                                  struct mmc_request *mrq)
 650 {
 651         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 652                  host->state);
 653
 654         slot->mrq = mrq;
 655
 656         if (host->state == STATE_IDLE) {
 657                 host->state = STATE_SENDING_CMD;
 658                 dw_mci_start_request(host, slot);
 659         } else {
 660                 list_add_tail(&slot->queue_node, &host->queue);
 661         }
 662 }
 663
 664 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 665 {
 666         struct dw_mci_slot *slot = mmc_priv(mmc);
 667         struct dw_mci *host = slot->host;
 668
 669         WARN_ON(slot->mrq);
 670
 671         /*
 672          * The check for card presence and queueing of the request must be
 673          * atomic, otherwise the card could be removed in between and the
 674          * request wouldn't fail until another card was inserted.
 675          */
 676         spin_lock_bh(&host->lock);
 677
 678         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 679                 spin_unlock_bh(&host->lock);
 680                 mrq->cmd->error = -ENOMEDIUM;
 681                 mmc_request_done(mmc, mrq);
 682                 return;
 683         }
 684
 685         dw_mci_queue_request(host, slot, mrq);
 686
 687         spin_unlock_bh(&host->lock);
 688 }
 689
 690 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 691 {
 692         struct dw_mci_slot *slot = mmc_priv(mmc);
 693         u32 regs;
 694
 695         /* set default 1 bit mode */
 696         slot->ctype = SDMMC_CTYPE_1BIT;
 697
 698         switch (ios->bus_width) {
 699         case MMC_BUS_WIDTH_1:
 700                 slot->ctype = SDMMC_CTYPE_1BIT;
 701                 break;
 702         case MMC_BUS_WIDTH_4:
 703                 slot->ctype = SDMMC_CTYPE_4BIT;
 704                 break;
 705         case MMC_BUS_WIDTH_8:
 706                 slot->ctype = SDMMC_CTYPE_8BIT;
 707                 break;
 708         }
 709
 710         /* DDR mode set */
 711         if (ios->timing == MMC_TIMING_UHS_DDR50) {
 712                 regs = mci_readl(slot->host, UHS_REG);
 713                 regs |= (0x1 << slot->id) << 16;
 714                 mci_writel(slot->host, UHS_REG, regs);
 715         }
 716
 717         if (ios->clock) {
 718                 /*
 719                  * Use mirror of ios->clock to prevent race with mmc
 720                  * core ios update when finding the minimum.
 721                  */
 722                 slot->clock = ios->clock;
 723         }
 724
 725         switch (ios->power_mode) {
 726         case MMC_POWER_UP:
 727                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
 728                 break;
 729         default:
 730                 break;
 731         }
 732 }
 733
 734 static int dw_mci_get_ro(struct mmc_host *mmc)
 735 {
 736         int read_only;
 737         struct dw_mci_slot *slot = mmc_priv(mmc);
 738         struct dw_mci_board *brd = slot->host->pdata;
 739
 740         /* Use platform get_ro function, else try on board write protect */
 741         if (brd->get_ro)
 742                 read_only = brd->get_ro(slot->id);
 743         else
 744                 read_only =
 745                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
 746
 747         dev_dbg(&mmc->class_dev, "card is %s\n",
 748                 read_only ? "read-only" : "read-write");
 749
 750         return read_only;
 751 }
 752
 753 static int dw_mci_get_cd(struct mmc_host *mmc)
 754 {
 755         int present;
 756         struct dw_mci_slot *slot = mmc_priv(mmc);
 757         struct dw_mci_board *brd = slot->host->pdata;
 758
 759         /* Use platform get_cd function, else try onboard card detect */
 760         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 761                 present = 1;
 762         else if (brd->get_cd)
 763                 present = !brd->get_cd(slot->id);
 764         else
 765                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 766                         == 0 ? 1 : 0;
 767
 768         if (present)
 769                 dev_dbg(&mmc->class_dev, "card is present\n");
 770         else
 771                 dev_dbg(&mmc->class_dev, "card is not present\n");
 772
 773         return present;
 774 }
 775
 776 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
 777 {
 778         struct dw_mci_slot *slot = mmc_priv(mmc);
 779         struct dw_mci *host = slot->host;
 780         u32 int_mask;
 781
 782         /* Enable/disable Slot Specific SDIO interrupt */
 783         int_mask = mci_readl(host, INTMASK);
 784         if (enb) {
 785                 mci_writel(host, INTMASK,
 786                            (int_mask | (1 << SDMMC_INT_SDIO(slot->id))));
 787         } else {
 788                 mci_writel(host, INTMASK,
 789                            (int_mask & ~(1 << SDMMC_INT_SDIO(slot->id))));
 790         }
 791 }
 792
 793 static const struct mmc_host_ops dw_mci_ops = {
 794         .request                = dw_mci_request,
 795         .set_ios                = dw_mci_set_ios,
 796         .get_ro                 = dw_mci_get_ro,
 797         .get_cd                 = dw_mci_get_cd,
 798         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
 799 };
 800
 801 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
 802         __releases(&host->lock)
 803         __acquires(&host->lock)
 804 {
 805         struct dw_mci_slot *slot;
 806         struct mmc_host *prev_mmc = host->cur_slot->mmc;
 807
 808         WARN_ON(host->cmd || host->data);
 809
 810         host->cur_slot->mrq = NULL;
 811         host->mrq = NULL;
 812         if (!list_empty(&host->queue)) {
 813                 slot = list_entry(host->queue.next,
 814                                   struct dw_mci_slot, queue_node);
 815                 list_del(&slot->queue_node);
 816                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
 817                          mmc_hostname(slot->mmc));
 818                 host->state = STATE_SENDING_CMD;
 819                 dw_mci_start_request(host, slot);
 820         } else {
 821                 dev_vdbg(&host->pdev->dev, "list empty\n");
 822                 host->state = STATE_IDLE;
 823         }
 824
 825         spin_unlock(&host->lock);
 826         mmc_request_done(prev_mmc, mrq);
 827         spin_lock(&host->lock);
 828 }
 829
 830 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
 831 {
 832         u32 status = host->cmd_status;
 833
 834         host->cmd_status = 0;
 835
 836         /* Read the response from the card (up to 16 bytes) */
 837         if (cmd->flags & MMC_RSP_PRESENT) {
 838                 if (cmd->flags & MMC_RSP_136) {
 839                         cmd->resp[3] = mci_readl(host, RESP0);
 840                         cmd->resp[2] = mci_readl(host, RESP1);
 841                         cmd->resp[1] = mci_readl(host, RESP2);
 842                         cmd->resp[0] = mci_readl(host, RESP3);
 843                 } else {
 844                         cmd->resp[0] = mci_readl(host, RESP0);
 845                         cmd->resp[1] = 0;
 846                         cmd->resp[2] = 0;
 847                         cmd->resp[3] = 0;
 848                 }
 849         }
 850
 851         if (status & SDMMC_INT_RTO)
 852                 cmd->error = -ETIMEDOUT;
 853         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
 854                 cmd->error = -EILSEQ;
 855         else if (status & SDMMC_INT_RESP_ERR)
 856                 cmd->error = -EIO;
 857         else
 858                 cmd->error = 0;
 859
 860         if (cmd->error) {
 861                 /* newer ip versions need a delay between retries */
 862                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
 863                         mdelay(20);
 864
 865                 if (cmd->data) {
 866                         host->data = NULL;
 867                         dw_mci_stop_dma(host);
 868                 }
 869         }
 870 }
 871
 872 static void dw_mci_tasklet_func(unsigned long priv)
 873 {
 874         struct dw_mci *host = (struct dw_mci *)priv;
 875         struct mmc_data *data;
 876         struct mmc_command *cmd;
 877         enum dw_mci_state state;
 878         enum dw_mci_state prev_state;
 879         u32 status, ctrl;
 880
 881         spin_lock(&host->lock);
 882
 883         state = host->state;
 884         data = host->data;
 885
 886         do {
 887                 prev_state = state;
 888
 889                 switch (state) {
 890                 case STATE_IDLE:
 891                         break;
 892
 893                 case STATE_SENDING_CMD:
 894                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
 895                                                 &host->pending_events))
 896                                 break;
 897
 898                         cmd = host->cmd;
 899                         host->cmd = NULL;
 900                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
 901                         dw_mci_command_complete(host, cmd);
 902                         if (cmd == host->mrq->sbc && !cmd->error) {
 903                                 prev_state = state = STATE_SENDING_CMD;
 904                                 __dw_mci_start_request(host, host->cur_slot,
 905                                                        host->mrq->cmd);
 906                                 goto unlock;
 907                         }
 908
 909                         if (!host->mrq->data || cmd->error) {
 910                                 dw_mci_request_end(host, host->mrq);
 911                                 goto unlock;
 912                         }
 913
 914                         prev_state = state = STATE_SENDING_DATA;
 915                         /* fall through */
 916
 917                 case STATE_SENDING_DATA:
 918                         if (test_and_clear_bit(EVENT_DATA_ERROR,
 919                                                &host->pending_events)) {
 920                                 dw_mci_stop_dma(host);
 921                                 if (data->stop)
 922                                         send_stop_cmd(host, data);
 923                                 state = STATE_DATA_ERROR;
 924                                 break;
 925                         }
 926
 927                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
 928                                                 &host->pending_events))
 929                                 break;
 930
 931                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
 932                         prev_state = state = STATE_DATA_BUSY;
 933                         /* fall through */
 934
 935                 case STATE_DATA_BUSY:
 936                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
 937                                                 &host->pending_events))
 938                                 break;
 939
 940                         host->data = NULL;
 941                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
 942                         status = host->data_status;
 943
 944                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
 945                                 if (status & SDMMC_INT_DTO) {
 946                                         data->error = -ETIMEDOUT;
 947                                 } else if (status & SDMMC_INT_DCRC) {
 948                                         data->error = -EILSEQ;
 949                                 } else if (status & SDMMC_INT_EBE &&
 950                                            host->dir_status ==
 951                                                         DW_MCI_SEND_STATUS) {
 952                                         /*
 953                                          * No data CRC status was returned.
 954                                          * The number of bytes transferred will
 955                                          * be exaggerated in PIO mode.
 956                                          */
 957                                         data->bytes_xfered = 0;
 958                                         data->error = -ETIMEDOUT;
 959                                 } else {
 960                                         dev_err(&host->pdev->dev,
 961                                                 "data FIFO error "
 962                                                 "(status=%08x)\n",
 963                                                 status);
 964                                         data->error = -EIO;
 965                                 }
 966                                 /*
 967                                  * After an error, there may be data lingering
 968                                  * in the FIFO, so reset it - doing so
 969                                  * generates a block interrupt, hence setting
 970                                  * the scatter-gather pointer to NULL.
 971                                  */
 972                                 host->sg = NULL;
 973                                 ctrl = mci_readl(host, CTRL);
 974                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
 975                                 mci_writel(host, CTRL, ctrl);
 976                         } else {
 977                                 data->bytes_xfered = data->blocks * data->blksz;
 978                                 data->error = 0;
 979                         }
 980
 981                         if (!data->stop) {
 982                                 dw_mci_request_end(host, host->mrq);
 983                                 goto unlock;
 984                         }
 985
 986                         if (host->mrq->sbc && !data->error) {
 987                                 data->stop->error = 0;
 988                                 dw_mci_request_end(host, host->mrq);
 989                                 goto unlock;
 990                         }
 991
 992                         prev_state = state = STATE_SENDING_STOP;
 993                         if (!data->error)
 994                                 send_stop_cmd(host, data);
 995                         /* fall through */
 996
 997                 case STATE_SENDING_STOP:
 998                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
 999                                                 &host->pending_events))
1000                                 break;
1001
1002                         host->cmd = NULL;
1003                         dw_mci_command_complete(host, host->mrq->stop);
1004                         dw_mci_request_end(host, host->mrq);
1005                         goto unlock;
1006
1007                 case STATE_DATA_ERROR:
1008                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1009                                                 &host->pending_events))
1010                                 break;
1011
1012                         state = STATE_DATA_BUSY;
1013                         break;
1014                 }
1015         } while (state != prev_state);
1016
1017         host->state = state;
1018 unlock:
1019         spin_unlock(&host->lock);
1020
1021 }
1022
1023 /* push final bytes to part_buf, only use during push */
1024 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1025 {
1026         memcpy((void *)&host->part_buf, buf, cnt);
1027         host->part_buf_count = cnt;
1028 }
1029
1030 /* append bytes to part_buf, only use during push */
1031 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1032 {
1033         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1034         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1035         host->part_buf_count += cnt;
1036         return cnt;
1037 }
1038
1039 /* pull first bytes from part_buf, only use during pull */
1040 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1041 {
1042         cnt = min(cnt, (int)host->part_buf_count);
1043         if (cnt) {
1044                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1045                        cnt);
1046                 host->part_buf_count -= cnt;
1047                 host->part_buf_start += cnt;
1048         }
1049         return cnt;
1050 }
1051
1052 /* pull final bytes from the part_buf, assuming it's just been filled */
1053 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1054 {
1055         memcpy(buf, &host->part_buf, cnt);
1056         host->part_buf_start = cnt;
1057         host->part_buf_count = (1 << host->data_shift) - cnt;
1058 }
1059
1060 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1061 {
1062         /* try and push anything in the part_buf */
1063         if (unlikely(host->part_buf_count)) {
1064                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1065                 buf += len;
1066                 cnt -= len;
1067                 if (!sg_next(host->sg) || host->part_buf_count == 2) {
1068                         mci_writew(host, DATA(host->data_offset),
1069                                         host->part_buf16);
1070                         host->part_buf_count = 0;
1071                 }
1072         }
1073 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1074         if (unlikely((unsigned long)buf & 0x1)) {
1075                 while (cnt >= 2) {
1076                         u16 aligned_buf[64];
1077                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1078                         int items = len >> 1;
1079                         int i;
1080                         /* memcpy from input buffer into aligned buffer */
1081                         memcpy(aligned_buf, buf, len);
1082                         buf += len;
1083                         cnt -= len;
1084                         /* push data from aligned buffer into fifo */
1085                         for (i = 0; i < items; ++i)
1086                                 mci_writew(host, DATA(host->data_offset),
1087                                                 aligned_buf[i]);
1088                 }
1089         } else
1090 #endif
1091         {
1092                 u16 *pdata = buf;
1093                 for (; cnt >= 2; cnt -= 2)
1094                         mci_writew(host, DATA(host->data_offset), *pdata++);
1095                 buf = pdata;
1096         }
1097         /* put anything remaining in the part_buf */
1098         if (cnt) {
1099                 dw_mci_set_part_bytes(host, buf, cnt);
1100                 if (!sg_next(host->sg))
1101                         mci_writew(host, DATA(host->data_offset),
1102                                         host->part_buf16);
1103         }
1104 }
1105
1106 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1107 {
1108 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1109         if (unlikely((unsigned long)buf & 0x1)) {
1110                 while (cnt >= 2) {
1111                         /* pull data from fifo into aligned buffer */
1112                         u16 aligned_buf[64];
1113                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1114                         int items = len >> 1;
1115                         int i;
1116                         for (i = 0; i < items; ++i)
1117                                 aligned_buf[i] = mci_readw(host,
1118                                                 DATA(host->data_offset));
1119                         /* memcpy from aligned buffer into output buffer */
1120                         memcpy(buf, aligned_buf, len);
1121                         buf += len;
1122                         cnt -= len;
1123                 }
1124         } else
1125 #endif
1126         {
1127                 u16 *pdata = buf;
1128                 for (; cnt >= 2; cnt -= 2)
1129                         *pdata++ = mci_readw(host, DATA(host->data_offset));
1130                 buf = pdata;
1131         }
1132         if (cnt) {
1133                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1134                 dw_mci_pull_final_bytes(host, buf, cnt);
1135         }
1136 }
1137
1138 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1139 {
1140         /* try and push anything in the part_buf */
1141         if (unlikely(host->part_buf_count)) {
1142                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1143                 buf += len;
1144                 cnt -= len;
1145                 if (!sg_next(host->sg) || host->part_buf_count == 4) {
1146                         mci_writel(host, DATA(host->data_offset),
1147                                         host->part_buf32);
1148                         host->part_buf_count = 0;
1149                 }
1150         }
1151 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1152         if (unlikely((unsigned long)buf & 0x3)) {
1153                 while (cnt >= 4) {
1154                         u32 aligned_buf[32];
1155                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1156                         int items = len >> 2;
1157                         int i;
1158                         /* memcpy from input buffer into aligned buffer */
1159                         memcpy(aligned_buf, buf, len);
1160                         buf += len;
1161                         cnt -= len;
1162                         /* push data from aligned buffer into fifo */
1163                         for (i = 0; i < items; ++i)
1164                                 mci_writel(host, DATA(host->data_offset),
1165                                                 aligned_buf[i]);
1166                 }
1167         } else
1168 #endif
1169         {
1170                 u32 *pdata = buf;
1171                 for (; cnt >= 4; cnt -= 4)
1172                         mci_writel(host, DATA(host->data_offset), *pdata++);
1173                 buf = pdata;
1174         }
1175         /* put anything remaining in the part_buf */
1176         if (cnt) {
1177                 dw_mci_set_part_bytes(host, buf, cnt);
1178                 if (!sg_next(host->sg))
1179                         mci_writel(host, DATA(host->data_offset),
1180                                                 host->part_buf32);
1181         }
1182 }
1183
1184 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1185 {
1186 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1187         if (unlikely((unsigned long)buf & 0x3)) {
1188                 while (cnt >= 4) {
1189                         /* pull data from fifo into aligned buffer */
1190                         u32 aligned_buf[32];
1191                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1192                         int items = len >> 2;
1193                         int i;
1194                         for (i = 0; i < items; ++i)
1195                                 aligned_buf[i] = mci_readl(host,
1196                                                 DATA(host->data_offset));
1197                         /* memcpy from aligned buffer into output buffer */
1198                         memcpy(buf, aligned_buf, len);
1199                         buf += len;
1200                         cnt -= len;
1201                 }
1202         } else
1203 #endif
1204         {
1205                 u32 *pdata = buf;
1206                 for (; cnt >= 4; cnt -= 4)
1207                         *pdata++ = mci_readl(host, DATA(host->data_offset));
1208                 buf = pdata;
1209         }
1210         if (cnt) {
1211                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1212                 dw_mci_pull_final_bytes(host, buf, cnt);
1213         }
1214 }
1215
1216 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1217 {
1218         /* try and push anything in the part_buf */
1219         if (unlikely(host->part_buf_count)) {
1220                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1221                 buf += len;
1222                 cnt -= len;
1223                 if (!sg_next(host->sg) || host->part_buf_count == 8) {
1224                         mci_writew(host, DATA(host->data_offset),
1225                                         host->part_buf);
1226                         host->part_buf_count = 0;
1227                 }
1228         }
1229 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1230         if (unlikely((unsigned long)buf & 0x7)) {
1231                 while (cnt >= 8) {
1232                         u64 aligned_buf[16];
1233                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1234                         int items = len >> 3;
1235                         int i;
1236                         /* memcpy from input buffer into aligned buffer */
1237                         memcpy(aligned_buf, buf, len);
1238                         buf += len;
1239                         cnt -= len;
1240                         /* push data from aligned buffer into fifo */
1241                         for (i = 0; i < items; ++i)
1242                                 mci_writeq(host, DATA(host->data_offset),
1243                                                 aligned_buf[i]);
1244                 }
1245         } else
1246 #endif
1247         {
1248                 u64 *pdata = buf;
1249                 for (; cnt >= 8; cnt -= 8)
1250                         mci_writeq(host, DATA(host->data_offset), *pdata++);
1251                 buf = pdata;
1252         }
1253         /* put anything remaining in the part_buf */
1254         if (cnt) {
1255                 dw_mci_set_part_bytes(host, buf, cnt);
1256                 if (!sg_next(host->sg))
1257                         mci_writeq(host, DATA(host->data_offset),
1258                                         host->part_buf);
1259         }
1260 }
1261
1262 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1263 {
1264 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1265         if (unlikely((unsigned long)buf & 0x7)) {
1266                 while (cnt >= 8) {
1267                         /* pull data from fifo into aligned buffer */
1268                         u64 aligned_buf[16];
1269                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1270                         int items = len >> 3;
1271                         int i;
1272                         for (i = 0; i < items; ++i)
1273                                 aligned_buf[i] = mci_readq(host,
1274                                                 DATA(host->data_offset));
1275                         /* memcpy from aligned buffer into output buffer */
1276                         memcpy(buf, aligned_buf, len);
1277                         buf += len;
1278                         cnt -= len;
1279                 }
1280         } else
1281 #endif
1282         {
1283                 u64 *pdata = buf;
1284                 for (; cnt >= 8; cnt -= 8)
1285                         *pdata++ = mci_readq(host, DATA(host->data_offset));
1286                 buf = pdata;
1287         }
1288         if (cnt) {
1289                 host->part_buf = mci_readq(host, DATA(host->data_offset));
1290                 dw_mci_pull_final_bytes(host, buf, cnt);
1291         }
1292 }
1293
1294 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1295 {
1296         int len;
1297
1298         /* get remaining partial bytes */
1299         len = dw_mci_pull_part_bytes(host, buf, cnt);
1300         if (unlikely(len == cnt))
1301                 return;
1302         buf += len;
1303         cnt -= len;
1304
1305         /* get the rest of the data */
1306         host->pull_data(host, buf, cnt);
1307 }
1308
1309 static void dw_mci_read_data_pio(struct dw_mci *host)
1310 {
1311         struct scatterlist *sg = host->sg;
1312         void *buf = sg_virt(sg);
1313         unsigned int offset = host->pio_offset;
1314         struct mmc_data *data = host->data;
1315         int shift = host->data_shift;
1316         u32 status;
1317         unsigned int nbytes = 0, len;
1318
1319         do {
1320                 len = host->part_buf_count +
1321                         (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1322                 if (offset + len <= sg->length) {
1323                         dw_mci_pull_data(host, (void *)(buf + offset), len);
1324
1325                         offset += len;
1326                         nbytes += len;
1327
1328                         if (offset == sg->length) {
1329                                 flush_dcache_page(sg_page(sg));
1330                                 host->sg = sg = sg_next(sg);
1331                                 if (!sg)
1332                                         goto done;
1333
1334                                 offset = 0;
1335                                 buf = sg_virt(sg);
1336                         }
1337                 } else {
1338                         unsigned int remaining = sg->length - offset;
1339                         dw_mci_pull_data(host, (void *)(buf + offset),
1340                                          remaining);
1341                         nbytes += remaining;
1342
1343                         flush_dcache_page(sg_page(sg));
1344                         host->sg = sg = sg_next(sg);
1345                         if (!sg)
1346                                 goto done;
1347
1348                         offset = len - remaining;
1349                         buf = sg_virt(sg);
1350                         dw_mci_pull_data(host, buf, offset);
1351                         nbytes += offset;
1352                 }
1353
1354                 status = mci_readl(host, MINTSTS);
1355                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1356                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1357                         host->data_status = status;
1358                         data->bytes_xfered += nbytes;
1359                         smp_wmb();
1360
1361                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1362
1363                         tasklet_schedule(&host->tasklet);
1364                         return;
1365                 }
1366         } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1367         host->pio_offset = offset;
1368         data->bytes_xfered += nbytes;
1369         return;
1370
1371 done:
1372         data->bytes_xfered += nbytes;
1373         smp_wmb();
1374         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1375 }
1376
1377 static void dw_mci_write_data_pio(struct dw_mci *host)
1378 {
1379         struct scatterlist *sg = host->sg;
1380         void *buf = sg_virt(sg);
1381         unsigned int offset = host->pio_offset;
1382         struct mmc_data *data = host->data;
1383         int shift = host->data_shift;
1384         u32 status;
1385         unsigned int nbytes = 0, len;
1386
1387         do {
1388                 len = ((host->fifo_depth -
1389                         SDMMC_GET_FCNT(mci_readl(host, STATUS))) << shift)
1390                         - host->part_buf_count;
1391                 if (offset + len <= sg->length) {
1392                         host->push_data(host, (void *)(buf + offset), len);
1393
1394                         offset += len;
1395                         nbytes += len;
1396                         if (offset == sg->length) {
1397                                 host->sg = sg = sg_next(sg);
1398                                 if (!sg)
1399                                         goto done;
1400
1401                                 offset = 0;
1402                                 buf = sg_virt(sg);
1403                         }
1404                 } else {
1405                         unsigned int remaining = sg->length - offset;
1406
1407                         host->push_data(host, (void *)(buf + offset),
1408                                         remaining);
1409                         nbytes += remaining;
1410
1411                         host->sg = sg = sg_next(sg);
1412                         if (!sg)
1413                                 goto done;
1414
1415                         offset = len - remaining;
1416                         buf = sg_virt(sg);
1417                         host->push_data(host, (void *)buf, offset);
1418                         nbytes += offset;
1419                 }
1420
1421                 status = mci_readl(host, MINTSTS);
1422                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1423                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1424                         host->data_status = status;
1425                         data->bytes_xfered += nbytes;
1426
1427                         smp_wmb();
1428
1429                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1430
1431                         tasklet_schedule(&host->tasklet);
1432                         return;
1433                 }
1434         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1435         host->pio_offset = offset;
1436         data->bytes_xfered += nbytes;
1437         return;
1438
1439 done:
1440         data->bytes_xfered += nbytes;
1441         smp_wmb();
1442         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1443 }
1444
1445 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1446 {
1447         if (!host->cmd_status)
1448                 host->cmd_status = status;
1449
1450         smp_wmb();
1451
1452         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1453         tasklet_schedule(&host->tasklet);
1454 }
1455
1456 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1457 {
1458         struct dw_mci *host = dev_id;
1459         u32 status, pending;
1460         unsigned int pass_count = 0;
1461         int i;
1462
1463         do {
1464                 status = mci_readl(host, RINTSTS);
1465                 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1466
1467                 /*
1468                  * DTO fix - version 2.10a and below, and only if internal DMA
1469                  * is configured.
1470                  */
1471                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1472                         if (!pending &&
1473                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1474                                 pending |= SDMMC_INT_DATA_OVER;
1475                 }
1476
1477                 if (!pending)
1478                         break;
1479
1480                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1481                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1482                         host->cmd_status = status;
1483                         smp_wmb();
1484                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1485                 }
1486
1487                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1488                         /* if there is an error report DATA_ERROR */
1489                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1490                         host->data_status = status;
1491                         smp_wmb();
1492                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1493                         if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1494                                          SDMMC_INT_SBE | SDMMC_INT_EBE)))
1495                                 tasklet_schedule(&host->tasklet);
1496                 }
1497
1498                 if (pending & SDMMC_INT_DATA_OVER) {
1499                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1500                         if (!host->data_status)
1501                                 host->data_status = status;
1502                         smp_wmb();
1503                         if (host->dir_status == DW_MCI_RECV_STATUS) {
1504                                 if (host->sg != NULL)
1505                                         dw_mci_read_data_pio(host);
1506                         }
1507                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1508                         tasklet_schedule(&host->tasklet);
1509                 }
1510
1511                 if (pending & SDMMC_INT_RXDR) {
1512                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1513                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
1514                                 dw_mci_read_data_pio(host);
1515                 }
1516
1517                 if (pending & SDMMC_INT_TXDR) {
1518                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1519                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
1520                                 dw_mci_write_data_pio(host);
1521                 }
1522
1523                 if (pending & SDMMC_INT_CMD_DONE) {
1524                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1525                         dw_mci_cmd_interrupt(host, status);
1526                 }
1527
1528                 if (pending & SDMMC_INT_CD) {
1529                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
1530                         queue_work(dw_mci_card_workqueue, &host->card_work);
1531                 }
1532
1533                 /* Handle SDIO Interrupts */
1534                 for (i = 0; i < host->num_slots; i++) {
1535                         struct dw_mci_slot *slot = host->slot[i];
1536                         if (pending & SDMMC_INT_SDIO(i)) {
1537                                 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1538                                 mmc_signal_sdio_irq(slot->mmc);
1539                         }
1540                 }
1541
1542         } while (pass_count++ < 5);
1543
1544 #ifdef CONFIG_MMC_DW_IDMAC
1545         /* Handle DMA interrupts */
1546         pending = mci_readl(host, IDSTS);
1547         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1548                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1549                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1550                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1551                 host->dma_ops->complete(host);
1552         }
1553 #endif
1554
1555         return IRQ_HANDLED;
1556 }
1557
1558 static void dw_mci_work_routine_card(struct work_struct *work)
1559 {
1560         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
1561         int i;
1562
1563         for (i = 0; i < host->num_slots; i++) {
1564                 struct dw_mci_slot *slot = host->slot[i];
1565                 struct mmc_host *mmc = slot->mmc;
1566                 struct mmc_request *mrq;
1567                 int present;
1568                 u32 ctrl;
1569
1570                 present = dw_mci_get_cd(mmc);
1571                 while (present != slot->last_detect_state) {
1572                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
1573                                 present ? "inserted" : "removed");
1574
1575                         /* Power up slot (before spin_lock, may sleep) */
1576                         if (present != 0 && host->pdata->setpower)
1577                                 host->pdata->setpower(slot->id, mmc->ocr_avail);
1578
1579                         spin_lock_bh(&host->lock);
1580
1581                         /* Card change detected */
1582                         slot->last_detect_state = present;
1583
1584                         /* Mark card as present if applicable */
1585                         if (present != 0)
1586                                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1587
1588                         /* Clean up queue if present */
1589                         mrq = slot->mrq;
1590                         if (mrq) {
1591                                 if (mrq == host->mrq) {
1592                                         host->data = NULL;
1593                                         host->cmd = NULL;
1594
1595                                         switch (host->state) {
1596                                         case STATE_IDLE:
1597                                                 break;
1598                                         case STATE_SENDING_CMD:
1599                                                 mrq->cmd->error = -ENOMEDIUM;
1600                                                 if (!mrq->data)
1601                                                         break;
1602                                                 /* fall through */
1603                                         case STATE_SENDING_DATA:
1604                                                 mrq->data->error = -ENOMEDIUM;
1605                                                 dw_mci_stop_dma(host);
1606                                                 break;
1607                                         case STATE_DATA_BUSY:
1608                                         case STATE_DATA_ERROR:
1609                                                 if (mrq->data->error == -EINPROGRESS)
1610                                                         mrq->data->error = -ENOMEDIUM;
1611                                                 if (!mrq->stop)
1612                                                         break;
1613                                                 /* fall through */
1614                                         case STATE_SENDING_STOP:
1615                                                 mrq->stop->error = -ENOMEDIUM;
1616                                                 break;
1617                                         }
1618
1619                                         dw_mci_request_end(host, mrq);
1620                                 } else {
1621                                         list_del(&slot->queue_node);
1622                                         mrq->cmd->error = -ENOMEDIUM;
1623                                         if (mrq->data)
1624                                                 mrq->data->error = -ENOMEDIUM;
1625                                         if (mrq->stop)
1626                                                 mrq->stop->error = -ENOMEDIUM;
1627
1628                                         spin_unlock(&host->lock);
1629                                         mmc_request_done(slot->mmc, mrq);
1630                                         spin_lock(&host->lock);
1631                                 }
1632                         }
1633
1634                         /* Power down slot */
1635                         if (present == 0) {
1636                                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1637
1638                                 /*
1639                                  * Clear down the FIFO - doing so generates a
1640                                  * block interrupt, hence setting the
1641                                  * scatter-gather pointer to NULL.
1642                                  */
1643                                 host->sg = NULL;
1644
1645                                 ctrl = mci_readl(host, CTRL);
1646                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1647                                 mci_writel(host, CTRL, ctrl);
1648
1649 #ifdef CONFIG_MMC_DW_IDMAC
1650                                 ctrl = mci_readl(host, BMOD);
1651                                 ctrl |= 0x01; /* Software reset of DMA */
1652                                 mci_writel(host, BMOD, ctrl);
1653 #endif
1654
1655                         }
1656
1657                         spin_unlock_bh(&host->lock);
1658
1659                         /* Power down slot (after spin_unlock, may sleep) */
1660                         if (present == 0 && host->pdata->setpower)
1661                                 host->pdata->setpower(slot->id, 0);
1662
1663                         present = dw_mci_get_cd(mmc);
1664                 }
1665
1666                 mmc_detect_change(slot->mmc,
1667                         msecs_to_jiffies(host->pdata->detect_delay_ms));
1668         }
1669 }
1670
1671 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1672 {
1673         struct mmc_host *mmc;
1674         struct dw_mci_slot *slot;
1675
1676         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1677         if (!mmc)
1678                 return -ENOMEM;
1679
1680         slot = mmc_priv(mmc);
1681         slot->id = id;
1682         slot->mmc = mmc;
1683         slot->host = host;
1684
1685         mmc->ops = &dw_mci_ops;
1686         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1687         mmc->f_max = host->bus_hz;
1688
1689         if (host->pdata->get_ocr)
1690                 mmc->ocr_avail = host->pdata->get_ocr(id);
1691         else
1692                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1693
1694         /*
1695          * Start with slot power disabled, it will be enabled when a card
1696          * is detected.
1697          */
1698         if (host->pdata->setpower)
1699                 host->pdata->setpower(id, 0);
1700
1701         if (host->pdata->caps)
1702                 mmc->caps = host->pdata->caps;
1703
1704         if (host->pdata->caps2)
1705                 mmc->caps2 = host->pdata->caps2;
1706
1707         if (host->pdata->get_bus_wd)
1708                 if (host->pdata->get_bus_wd(slot->id) >= 4)
1709                         mmc->caps |= MMC_CAP_4_BIT_DATA;
1710
1711         if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1712                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
1713
1714 #ifdef CONFIG_MMC_DW_IDMAC
1715         mmc->max_segs = host->ring_size;
1716         mmc->max_blk_size = 65536;
1717         mmc->max_blk_count = host->ring_size;
1718         mmc->max_seg_size = 0x1000;
1719         mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1720 #else
1721         if (host->pdata->blk_settings) {
1722                 mmc->max_segs = host->pdata->blk_settings->max_segs;
1723                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1724                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1725                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1726                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1727         } else {
1728                 /* Useful defaults if platform data is unset. */
1729                 mmc->max_segs = 64;
1730                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1731                 mmc->max_blk_count = 512;
1732                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1733                 mmc->max_seg_size = mmc->max_req_size;
1734         }
1735 #endif /* CONFIG_MMC_DW_IDMAC */
1736
1737         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1738         if (IS_ERR(host->vmmc)) {
1739                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
1740                 host->vmmc = NULL;
1741         } else
1742                 regulator_enable(host->vmmc);
1743
1744         if (dw_mci_get_cd(mmc))
1745                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1746         else
1747                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1748
1749         host->slot[id] = slot;
1750         mmc_add_host(mmc);
1751
1752 #if defined(CONFIG_DEBUG_FS)
1753         dw_mci_init_debugfs(slot);
1754 #endif
1755
1756         /* Card initially undetected */
1757         slot->last_detect_state = 0;
1758
1759         /*
1760          * Card may have been plugged in prior to boot so we
1761          * need to run the detect tasklet
1762          */
1763         queue_work(dw_mci_card_workqueue, &host->card_work);
1764
1765         return 0;
1766 }
1767
1768 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1769 {
1770         /* Shutdown detect IRQ */
1771         if (slot->host->pdata->exit)
1772                 slot->host->pdata->exit(id);
1773
1774         /* Debugfs stuff is cleaned up by mmc core */
1775         mmc_remove_host(slot->mmc);
1776         slot->host->slot[id] = NULL;
1777         mmc_free_host(slot->mmc);
1778 }
1779
1780 static void dw_mci_init_dma(struct dw_mci *host)
1781 {
1782         /* Alloc memory for sg translation */
1783         host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1784                                           &host->sg_dma, GFP_KERNEL);
1785         if (!host->sg_cpu) {
1786                 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1787                         __func__);
1788                 goto no_dma;
1789         }
1790
1791         /* Determine which DMA interface to use */
1792 #ifdef CONFIG_MMC_DW_IDMAC
1793         host->dma_ops = &dw_mci_idmac_ops;
1794         dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1795 #endif
1796
1797         if (!host->dma_ops)
1798                 goto no_dma;
1799
1800         if (host->dma_ops->init) {
1801                 if (host->dma_ops->init(host)) {
1802                         dev_err(&host->pdev->dev, "%s: Unable to initialize "
1803                                 "DMA Controller.\n", __func__);
1804                         goto no_dma;
1805                 }
1806         } else {
1807                 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1808                 goto no_dma;
1809         }
1810
1811         host->use_dma = 1;
1812         return;
1813
1814 no_dma:
1815         dev_info(&host->pdev->dev, "Using PIO mode.\n");
1816         host->use_dma = 0;
1817         return;
1818 }
1819
1820 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1821 {
1822         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1823         unsigned int ctrl;
1824
1825         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1826                                 SDMMC_CTRL_DMA_RESET));
1827
1828         /* wait till resets clear */
1829         do {
1830                 ctrl = mci_readl(host, CTRL);
1831                 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1832                               SDMMC_CTRL_DMA_RESET)))
1833                         return true;
1834         } while (time_before(jiffies, timeout));
1835
1836         dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1837
1838         return false;
1839 }
1840
1841 static int dw_mci_probe(struct platform_device *pdev)
1842 {
1843         struct dw_mci *host;
1844         struct resource *regs;
1845         struct dw_mci_board *pdata;
1846         int irq, ret, i, width;
1847         u32 fifo_size;
1848
1849         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1850         if (!regs)
1851                 return -ENXIO;
1852
1853         irq = platform_get_irq(pdev, 0);
1854         if (irq < 0)
1855                 return irq;
1856
1857         host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1858         if (!host)
1859                 return -ENOMEM;
1860
1861         host->pdev = pdev;
1862         host->pdata = pdata = pdev->dev.platform_data;
1863         if (!pdata || !pdata->init) {
1864                 dev_err(&pdev->dev,
1865                         "Platform data must supply init function\n");
1866                 ret = -ENODEV;
1867                 goto err_freehost;
1868         }
1869
1870         if (!pdata->select_slot && pdata->num_slots > 1) {
1871                 dev_err(&pdev->dev,
1872                         "Platform data must supply select_slot function\n");
1873                 ret = -ENODEV;
1874                 goto err_freehost;
1875         }
1876
1877         if (!pdata->bus_hz) {
1878                 dev_err(&pdev->dev,
1879                         "Platform data must supply bus speed\n");
1880                 ret = -ENODEV;
1881                 goto err_freehost;
1882         }
1883
1884         host->bus_hz = pdata->bus_hz;
1885         host->quirks = pdata->quirks;
1886
1887         spin_lock_init(&host->lock);
1888         INIT_LIST_HEAD(&host->queue);
1889
1890         ret = -ENOMEM;
1891         host->regs = ioremap(regs->start, resource_size(regs));
1892         if (!host->regs)
1893                 goto err_freehost;
1894
1895         host->dma_ops = pdata->dma_ops;
1896         dw_mci_init_dma(host);
1897
1898         /*
1899          * Get the host data width - this assumes that HCON has been set with
1900          * the correct values.
1901          */
1902         i = (mci_readl(host, HCON) >> 7) & 0x7;
1903         if (!i) {
1904                 host->push_data = dw_mci_push_data16;
1905                 host->pull_data = dw_mci_pull_data16;
1906                 width = 16;
1907                 host->data_shift = 1;
1908         } else if (i == 2) {
1909                 host->push_data = dw_mci_push_data64;
1910                 host->pull_data = dw_mci_pull_data64;
1911                 width = 64;
1912                 host->data_shift = 3;
1913         } else {
1914                 /* Check for a reserved value, and warn if it is */
1915                 WARN((i != 1),
1916                      "HCON reports a reserved host data width!\n"
1917                      "Defaulting to 32-bit access.\n");
1918                 host->push_data = dw_mci_push_data32;
1919                 host->pull_data = dw_mci_pull_data32;
1920                 width = 32;
1921                 host->data_shift = 2;
1922         }
1923
1924         /* Reset all blocks */
1925         if (!mci_wait_reset(&pdev->dev, host)) {
1926                 ret = -ENODEV;
1927                 goto err_dmaunmap;
1928         }
1929
1930         /* Clear the interrupts for the host controller */
1931         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1932         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1933
1934         /* Put in max timeout */
1935         mci_writel(host, TMOUT, 0xFFFFFFFF);
1936
1937         /*
1938          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
1939          *                          Tx Mark = fifo_size / 2 DMA Size = 8
1940          */
1941         if (!host->pdata->fifo_depth) {
1942                 /*
1943                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
1944                  * have been overwritten by the bootloader, just like we're
1945                  * about to do, so if you know the value for your hardware, you
1946                  * should put it in the platform data.
1947                  */
1948                 fifo_size = mci_readl(host, FIFOTH);
1949                 fifo_size = 1 + ((fifo_size >> 16) & 0x7ff);
1950         } else {
1951                 fifo_size = host->pdata->fifo_depth;
1952         }
1953         host->fifo_depth = fifo_size;
1954         host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1955                         ((fifo_size/2) << 0));
1956         mci_writel(host, FIFOTH, host->fifoth_val);
1957
1958         /* disable clock to CIU */
1959         mci_writel(host, CLKENA, 0);
1960         mci_writel(host, CLKSRC, 0);
1961
1962         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1963         dw_mci_card_workqueue = alloc_workqueue("dw-mci-card",
1964                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
1965         if (!dw_mci_card_workqueue)
1966                 goto err_dmaunmap;
1967         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
1968
1969         ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1970         if (ret)
1971                 goto err_workqueue;
1972
1973         platform_set_drvdata(pdev, host);
1974
1975         if (host->pdata->num_slots)
1976                 host->num_slots = host->pdata->num_slots;
1977         else
1978                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1979
1980         /* We need at least one slot to succeed */
1981         for (i = 0; i < host->num_slots; i++) {
1982                 ret = dw_mci_init_slot(host, i);
1983                 if (ret) {
1984                         ret = -ENODEV;
1985                         goto err_init_slot;
1986                 }
1987         }
1988
1989         /*
1990          * In 2.40a spec, Data offset is changed.
1991          * Need to check the version-id and set data-offset for DATA register.
1992          */
1993         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
1994         dev_info(&pdev->dev, "Version ID is %04x\n", host->verid);
1995
1996         if (host->verid < DW_MMC_240A)
1997                 host->data_offset = DATA_OFFSET;
1998         else
1999                 host->data_offset = DATA_240A_OFFSET;
2000
2001         /*
2002          * Enable interrupts for command done, data over, data empty, card det,
2003          * receive ready and error such as transmit, receive timeout, crc error
2004          */
2005         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2006         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2007                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2008                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2009         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2010
2011         dev_info(&pdev->dev, "DW MMC controller at irq %d, "
2012                  "%d bit host data width, "
2013                  "%u deep fifo\n",
2014                  irq, width, fifo_size);
2015         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2016                 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
2017
2018         return 0;
2019
2020 err_init_slot:
2021         /* De-init any initialized slots */
2022         while (i > 0) {
2023                 if (host->slot[i])
2024                         dw_mci_cleanup_slot(host->slot[i], i);
2025                 i--;
2026         }
2027         free_irq(irq, host);
2028
2029 err_workqueue:
2030         destroy_workqueue(dw_mci_card_workqueue);
2031
2032 err_dmaunmap:
2033         if (host->use_dma && host->dma_ops->exit)
2034                 host->dma_ops->exit(host);
2035         dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
2036                           host->sg_cpu, host->sg_dma);
2037         iounmap(host->regs);
2038
2039         if (host->vmmc) {
2040                 regulator_disable(host->vmmc);
2041                 regulator_put(host->vmmc);
2042         }
2043
2044
2045 err_freehost:
2046         kfree(host);
2047         return ret;
2048 }
2049
2050 static int __exit dw_mci_remove(struct platform_device *pdev)
2051 {
2052         struct dw_mci *host = platform_get_drvdata(pdev);
2053         int i;
2054
2055         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2056         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2057
2058         platform_set_drvdata(pdev, NULL);
2059
2060         for (i = 0; i < host->num_slots; i++) {
2061                 dev_dbg(&pdev->dev, "remove slot %d\n", i);
2062                 if (host->slot[i])
2063                         dw_mci_cleanup_slot(host->slot[i], i);
2064         }
2065
2066         /* disable clock to CIU */
2067         mci_writel(host, CLKENA, 0);
2068         mci_writel(host, CLKSRC, 0);
2069
2070         free_irq(platform_get_irq(pdev, 0), host);
2071         destroy_workqueue(dw_mci_card_workqueue);
2072         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
2073
2074         if (host->use_dma && host->dma_ops->exit)
2075                 host->dma_ops->exit(host);
2076
2077         if (host->vmmc) {
2078                 regulator_disable(host->vmmc);
2079                 regulator_put(host->vmmc);
2080         }
2081
2082         iounmap(host->regs);
2083
2084         kfree(host);
2085         return 0;
2086 }
2087
2088 #ifdef CONFIG_PM_SLEEP
2089 /*
2090  * TODO: we should probably disable the clock to the card in the suspend path.
2091  */
2092 static int dw_mci_suspend(struct device *dev)
2093 {
2094         int i, ret;
2095         struct dw_mci *host = dev_get_drvdata(dev);
2096
2097         for (i = 0; i < host->num_slots; i++) {
2098                 struct dw_mci_slot *slot = host->slot[i];
2099                 if (!slot)
2100                         continue;
2101                 ret = mmc_suspend_host(slot->mmc);
2102                 if (ret < 0) {
2103                         while (--i >= 0) {
2104                                 slot = host->slot[i];
2105                                 if (slot)
2106                                         mmc_resume_host(host->slot[i]->mmc);
2107                         }
2108                         return ret;
2109                 }
2110         }
2111
2112         if (host->vmmc)
2113                 regulator_disable(host->vmmc);
2114
2115         return 0;
2116 }
2117
2118 static int dw_mci_resume(struct device *dev)
2119 {
2120         int i, ret;
2121         struct dw_mci *host = dev_get_drvdata(dev);
2122
2123         if (host->vmmc)
2124                 regulator_enable(host->vmmc);
2125
2126         if (host->dma_ops->init)
2127                 host->dma_ops->init(host);
2128
2129         if (!mci_wait_reset(dev, host)) {
2130                 ret = -ENODEV;
2131                 return ret;
2132         }
2133
2134         /* Restore the old value at FIFOTH register */
2135         mci_writel(host, FIFOTH, host->fifoth_val);
2136
2137         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2138         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2139                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2140                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2141         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2142
2143         for (i = 0; i < host->num_slots; i++) {
2144                 struct dw_mci_slot *slot = host->slot[i];
2145                 if (!slot)
2146                         continue;
2147                 ret = mmc_resume_host(host->slot[i]->mmc);
2148                 if (ret < 0)
2149                         return ret;
2150         }
2151
2152         return 0;
2153 }
2154 #else
2155 #define dw_mci_suspend  NULL
2156 #define dw_mci_resume   NULL
2157 #endif /* CONFIG_PM_SLEEP */
2158
2159 static SIMPLE_DEV_PM_OPS(dw_mci_pmops, dw_mci_suspend, dw_mci_resume);
2160
2161 static struct platform_driver dw_mci_driver = {
2162         .remove         = __exit_p(dw_mci_remove),
2163         .driver         = {
2164                 .name           = "dw_mmc",
2165                 .pm             = &dw_mci_pmops,
2166         },
2167 };
2168
2169 static int __init dw_mci_init(void)
2170 {
2171         return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
2172 }
2173
2174 static void __exit dw_mci_exit(void)
2175 {
2176         platform_driver_unregister(&dw_mci_driver);
2177 }
2178
2179 module_init(dw_mci_init);
2180 module_exit(dw_mci_exit);
2181
2182 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2183 MODULE_AUTHOR("NXP Semiconductor VietNam");
2184 MODULE_AUTHOR("Imagination Technologies Ltd");
2185 MODULE_LICENSE("GPL v2");