Pileus Git - ~andy/linux/blob - drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/scatterlist.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/slab.h>
  28 #include <linux/stat.h>
  29 #include <linux/delay.h>
  30 #include <linux/irq.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/dw_mmc.h>
  34 #include <linux/bitops.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/workqueue.h>
  37
  38 #include "dw_mmc.h"
  39
  40 /* Common flag combinations */
  41 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
  42                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  43                                  SDMMC_INT_EBE)
  44 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  45                                  SDMMC_INT_RESP_ERR)
  46 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  47                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  48 #define DW_MCI_SEND_STATUS      1
  49 #define DW_MCI_RECV_STATUS      2
  50 #define DW_MCI_DMA_THRESHOLD    16
  51
  52 #ifdef CONFIG_MMC_DW_IDMAC
  53 struct idmac_desc {
  54         u32             des0;   /* Control Descriptor */
  55 #define IDMAC_DES0_DIC  BIT(1)
  56 #define IDMAC_DES0_LD   BIT(2)
  57 #define IDMAC_DES0_FD   BIT(3)
  58 #define IDMAC_DES0_CH   BIT(4)
  59 #define IDMAC_DES0_ER   BIT(5)
  60 #define IDMAC_DES0_CES  BIT(30)
  61 #define IDMAC_DES0_OWN  BIT(31)
  62
  63         u32             des1;   /* Buffer sizes */
  64 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  65         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  66
  67         u32             des2;   /* buffer 1 physical address */
  68
  69         u32             des3;   /* buffer 2 physical address */
  70 };
  71 #endif /* CONFIG_MMC_DW_IDMAC */
  72
  73 /**
  74  * struct dw_mci_slot - MMC slot state
  75  * @mmc: The mmc_host representing this slot.
  76  * @host: The MMC controller this slot is using.
  77  * @ctype: Card type for this slot.
  78  * @mrq: mmc_request currently being processed or waiting to be
  79  *      processed, or NULL when the slot is idle.
  80  * @queue_node: List node for placing this node in the @queue list of
  81  *      &struct dw_mci.
  82  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  83  * @flags: Random state bits associated with the slot.
  84  * @id: Number of this slot.
  85  * @last_detect_state: Most recently observed card detect state.
  86  */
  87 struct dw_mci_slot {
  88         struct mmc_host         *mmc;
  89         struct dw_mci           *host;
  90
  91         u32                     ctype;
  92
  93         struct mmc_request      *mrq;
  94         struct list_head        queue_node;
  95
  96         unsigned int            clock;
  97         unsigned long           flags;
  98 #define DW_MMC_CARD_PRESENT     0
  99 #define DW_MMC_CARD_NEED_INIT   1
 100         int                     id;
 101         int                     last_detect_state;
 102 };
 103
 104 static struct workqueue_struct *dw_mci_card_workqueue;
 105
 106 #if defined(CONFIG_DEBUG_FS)
 107 static int dw_mci_req_show(struct seq_file *s, void *v)
 108 {
 109         struct dw_mci_slot *slot = s->private;
 110         struct mmc_request *mrq;
 111         struct mmc_command *cmd;
 112         struct mmc_command *stop;
 113         struct mmc_data *data;
 114
 115         /* Make sure we get a consistent snapshot */
 116         spin_lock_bh(&slot->host->lock);
 117         mrq = slot->mrq;
 118
 119         if (mrq) {
 120                 cmd = mrq->cmd;
 121                 data = mrq->data;
 122                 stop = mrq->stop;
 123
 124                 if (cmd)
 125                         seq_printf(s,
 126                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 127                                    cmd->opcode, cmd->arg, cmd->flags,
 128                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 129                                    cmd->resp[2], cmd->error);
 130                 if (data)
 131                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 132                                    data->bytes_xfered, data->blocks,
 133                                    data->blksz, data->flags, data->error);
 134                 if (stop)
 135                         seq_printf(s,
 136                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 137                                    stop->opcode, stop->arg, stop->flags,
 138                                    stop->resp[0], stop->resp[1], stop->resp[2],
 139                                    stop->resp[2], stop->error);
 140         }
 141
 142         spin_unlock_bh(&slot->host->lock);
 143
 144         return 0;
 145 }
 146
 147 static int dw_mci_req_open(struct inode *inode, struct file *file)
 148 {
 149         return single_open(file, dw_mci_req_show, inode->i_private);
 150 }
 151
 152 static const struct file_operations dw_mci_req_fops = {
 153         .owner          = THIS_MODULE,
 154         .open           = dw_mci_req_open,
 155         .read           = seq_read,
 156         .llseek         = seq_lseek,
 157         .release        = single_release,
 158 };
 159
 160 static int dw_mci_regs_show(struct seq_file *s, void *v)
 161 {
 162         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 163         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 164         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 165         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 166         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 167         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 168
 169         return 0;
 170 }
 171
 172 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 173 {
 174         return single_open(file, dw_mci_regs_show, inode->i_private);
 175 }
 176
 177 static const struct file_operations dw_mci_regs_fops = {
 178         .owner          = THIS_MODULE,
 179         .open           = dw_mci_regs_open,
 180         .read           = seq_read,
 181         .llseek         = seq_lseek,
 182         .release        = single_release,
 183 };
 184
 185 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 186 {
 187         struct mmc_host *mmc = slot->mmc;
 188         struct dw_mci *host = slot->host;
 189         struct dentry *root;
 190         struct dentry *node;
 191
 192         root = mmc->debugfs_root;
 193         if (!root)
 194                 return;
 195
 196         node = debugfs_create_file("regs", S_IRUSR, root, host,
 197                                    &dw_mci_regs_fops);
 198         if (!node)
 199                 goto err;
 200
 201         node = debugfs_create_file("req", S_IRUSR, root, slot,
 202                                    &dw_mci_req_fops);
 203         if (!node)
 204                 goto err;
 205
 206         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 207         if (!node)
 208                 goto err;
 209
 210         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 211                                   (u32 *)&host->pending_events);
 212         if (!node)
 213                 goto err;
 214
 215         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 216                                   (u32 *)&host->completed_events);
 217         if (!node)
 218                 goto err;
 219
 220         return;
 221
 222 err:
 223         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 224 }
 225 #endif /* defined(CONFIG_DEBUG_FS) */
 226
 227 static void dw_mci_set_timeout(struct dw_mci *host)
 228 {
 229         /* timeout (maximum) */
 230         mci_writel(host, TMOUT, 0xffffffff);
 231 }
 232
 233 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 234 {
 235         struct mmc_data *data;
 236         u32 cmdr;
 237         cmd->error = -EINPROGRESS;
 238
 239         cmdr = cmd->opcode;
 240
 241         if (cmdr == MMC_STOP_TRANSMISSION)
 242                 cmdr |= SDMMC_CMD_STOP;
 243         else
 244                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 245
 246         if (cmd->flags & MMC_RSP_PRESENT) {
 247                 /* We expect a response, so set this bit */
 248                 cmdr |= SDMMC_CMD_RESP_EXP;
 249                 if (cmd->flags & MMC_RSP_136)
 250                         cmdr |= SDMMC_CMD_RESP_LONG;
 251         }
 252
 253         if (cmd->flags & MMC_RSP_CRC)
 254                 cmdr |= SDMMC_CMD_RESP_CRC;
 255
 256         data = cmd->data;
 257         if (data) {
 258                 cmdr |= SDMMC_CMD_DAT_EXP;
 259                 if (data->flags & MMC_DATA_STREAM)
 260                         cmdr |= SDMMC_CMD_STRM_MODE;
 261                 if (data->flags & MMC_DATA_WRITE)
 262                         cmdr |= SDMMC_CMD_DAT_WR;
 263         }
 264
 265         return cmdr;
 266 }
 267
 268 static void dw_mci_start_command(struct dw_mci *host,
 269                                  struct mmc_command *cmd, u32 cmd_flags)
 270 {
 271         host->cmd = cmd;
 272         dev_vdbg(&host->pdev->dev,
 273                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 274                  cmd->arg, cmd_flags);
 275
 276         mci_writel(host, CMDARG, cmd->arg);
 277         wmb();
 278
 279         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 280 }
 281
 282 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 283 {
 284         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 285 }
 286
 287 /* DMA interface functions */
 288 static void dw_mci_stop_dma(struct dw_mci *host)
 289 {
 290         if (host->using_dma) {
 291                 host->dma_ops->stop(host);
 292                 host->dma_ops->cleanup(host);
 293         } else {
 294                 /* Data transfer was stopped by the interrupt handler */
 295                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 296         }
 297 }
 298
 299 #ifdef CONFIG_MMC_DW_IDMAC
 300 static void dw_mci_dma_cleanup(struct dw_mci *host)
 301 {
 302         struct mmc_data *data = host->data;
 303
 304         if (data)
 305                 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
 306                              ((data->flags & MMC_DATA_WRITE)
 307                               ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 308 }
 309
 310 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 311 {
 312         u32 temp;
 313
 314         /* Disable and reset the IDMAC interface */
 315         temp = mci_readl(host, CTRL);
 316         temp &= ~SDMMC_CTRL_USE_IDMAC;
 317         temp |= SDMMC_CTRL_DMA_RESET;
 318         mci_writel(host, CTRL, temp);
 319
 320         /* Stop the IDMAC running */
 321         temp = mci_readl(host, BMOD);
 322         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 323         mci_writel(host, BMOD, temp);
 324 }
 325
 326 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 327 {
 328         struct mmc_data *data = host->data;
 329
 330         dev_vdbg(&host->pdev->dev, "DMA complete\n");
 331
 332         host->dma_ops->cleanup(host);
 333
 334         /*
 335          * If the card was removed, data will be NULL. No point in trying to
 336          * send the stop command or waiting for NBUSY in this case.
 337          */
 338         if (data) {
 339                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 340                 tasklet_schedule(&host->tasklet);
 341         }
 342 }
 343
 344 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 345                                     unsigned int sg_len)
 346 {
 347         int i;
 348         struct idmac_desc *desc = host->sg_cpu;
 349
 350         for (i = 0; i < sg_len; i++, desc++) {
 351                 unsigned int length = sg_dma_len(&data->sg[i]);
 352                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 353
 354                 /* Set the OWN bit and disable interrupts for this descriptor */
 355                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 356
 357                 /* Buffer length */
 358                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 359
 360                 /* Physical address to DMA to/from */
 361                 desc->des2 = mem_addr;
 362         }
 363
 364         /* Set first descriptor */
 365         desc = host->sg_cpu;
 366         desc->des0 |= IDMAC_DES0_FD;
 367
 368         /* Set last descriptor */
 369         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 370         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 371         desc->des0 |= IDMAC_DES0_LD;
 372
 373         wmb();
 374 }
 375
 376 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 377 {
 378         u32 temp;
 379
 380         dw_mci_translate_sglist(host, host->data, sg_len);
 381
 382         /* Select IDMAC interface */
 383         temp = mci_readl(host, CTRL);
 384         temp |= SDMMC_CTRL_USE_IDMAC;
 385         mci_writel(host, CTRL, temp);
 386
 387         wmb();
 388
 389         /* Enable the IDMAC */
 390         temp = mci_readl(host, BMOD);
 391         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 392         mci_writel(host, BMOD, temp);
 393
 394         /* Start it running */
 395         mci_writel(host, PLDMND, 1);
 396 }
 397
 398 static int dw_mci_idmac_init(struct dw_mci *host)
 399 {
 400         struct idmac_desc *p;
 401         int i;
 402
 403         /* Number of descriptors in the ring buffer */
 404         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 405
 406         /* Forward link the descriptor list */
 407         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 408                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 409
 410         /* Set the last descriptor as the end-of-ring descriptor */
 411         p->des3 = host->sg_dma;
 412         p->des0 = IDMAC_DES0_ER;
 413
 414         /* Mask out interrupts - get Tx & Rx complete only */
 415         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 416                    SDMMC_IDMAC_INT_TI);
 417
 418         /* Set the descriptor base address */
 419         mci_writel(host, DBADDR, host->sg_dma);
 420         return 0;
 421 }
 422
 423 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
 424         .init = dw_mci_idmac_init,
 425         .start = dw_mci_idmac_start_dma,
 426         .stop = dw_mci_idmac_stop_dma,
 427         .complete = dw_mci_idmac_complete_dma,
 428         .cleanup = dw_mci_dma_cleanup,
 429 };
 430 #endif /* CONFIG_MMC_DW_IDMAC */
 431
 432 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 433 {
 434         struct scatterlist *sg;
 435         unsigned int i, direction, sg_len;
 436         u32 temp;
 437
 438         host->using_dma = 0;
 439
 440         /* If we don't have a channel, we can't do DMA */
 441         if (!host->use_dma)
 442                 return -ENODEV;
 443
 444         /*
 445          * We don't do DMA on "complex" transfers, i.e. with
 446          * non-word-aligned buffers or lengths. Also, we don't bother
 447          * with all the DMA setup overhead for short transfers.
 448          */
 449         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 450                 return -EINVAL;
 451         if (data->blksz & 3)
 452                 return -EINVAL;
 453
 454         for_each_sg(data->sg, sg, data->sg_len, i) {
 455                 if (sg->offset & 3 || sg->length & 3)
 456                         return -EINVAL;
 457         }
 458
 459         host->using_dma = 1;
 460
 461         if (data->flags & MMC_DATA_READ)
 462                 direction = DMA_FROM_DEVICE;
 463         else
 464                 direction = DMA_TO_DEVICE;
 465
 466         sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
 467                             direction);
 468
 469         dev_vdbg(&host->pdev->dev,
 470                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 471                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 472                  sg_len);
 473
 474         /* Enable the DMA interface */
 475         temp = mci_readl(host, CTRL);
 476         temp |= SDMMC_CTRL_DMA_ENABLE;
 477         mci_writel(host, CTRL, temp);
 478
 479         /* Disable RX/TX IRQs, let DMA handle it */
 480         temp = mci_readl(host, INTMASK);
 481         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 482         mci_writel(host, INTMASK, temp);
 483
 484         host->dma_ops->start(host, sg_len);
 485
 486         return 0;
 487 }
 488
 489 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 490 {
 491         u32 temp;
 492
 493         data->error = -EINPROGRESS;
 494
 495         WARN_ON(host->data);
 496         host->sg = NULL;
 497         host->data = data;
 498
 499         if (data->flags & MMC_DATA_READ)
 500                 host->dir_status = DW_MCI_RECV_STATUS;
 501         else
 502                 host->dir_status = DW_MCI_SEND_STATUS;
 503
 504         if (dw_mci_submit_data_dma(host, data)) {
 505                 host->sg = data->sg;
 506                 host->pio_offset = 0;
 507                 host->part_buf_start = 0;
 508                 host->part_buf_count = 0;
 509
 510                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 511                 temp = mci_readl(host, INTMASK);
 512                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 513                 mci_writel(host, INTMASK, temp);
 514
 515                 temp = mci_readl(host, CTRL);
 516                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 517                 mci_writel(host, CTRL, temp);
 518         }
 519 }
 520
 521 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 522 {
 523         struct dw_mci *host = slot->host;
 524         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 525         unsigned int cmd_status = 0;
 526
 527         mci_writel(host, CMDARG, arg);
 528         wmb();
 529         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 530
 531         while (time_before(jiffies, timeout)) {
 532                 cmd_status = mci_readl(host, CMD);
 533                 if (!(cmd_status & SDMMC_CMD_START))
 534                         return;
 535         }
 536         dev_err(&slot->mmc->class_dev,
 537                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 538                 cmd, arg, cmd_status);
 539 }
 540
 541 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
 542 {
 543         struct dw_mci *host = slot->host;
 544         u32 div;
 545
 546         if (slot->clock != host->current_speed) {
 547                 if (host->bus_hz % slot->clock)
 548                         /*
 549                          * move the + 1 after the divide to prevent
 550                          * over-clocking the card.
 551                          */
 552                         div = ((host->bus_hz / slot->clock) >> 1) + 1;
 553                 else
 554                         div = (host->bus_hz  / slot->clock) >> 1;
 555
 556                 dev_info(&slot->mmc->class_dev,
 557                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
 558                          " div = %d)\n", slot->id, host->bus_hz, slot->clock,
 559                          div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
 560
 561                 /* disable clock */
 562                 mci_writel(host, CLKENA, 0);
 563                 mci_writel(host, CLKSRC, 0);
 564
 565                 /* inform CIU */
 566                 mci_send_cmd(slot,
 567                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 568
 569                 /* set clock to desired speed */
 570                 mci_writel(host, CLKDIV, div);
 571
 572                 /* inform CIU */
 573                 mci_send_cmd(slot,
 574                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 575
 576                 /* enable clock */
 577                 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
 578                            SDMMC_CLKEN_LOW_PWR);
 579
 580                 /* inform CIU */
 581                 mci_send_cmd(slot,
 582                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 583
 584                 host->current_speed = slot->clock;
 585         }
 586
 587         /* Set the current slot bus width */
 588         mci_writel(host, CTYPE, (slot->ctype << slot->id));
 589 }
 590
 591 static void __dw_mci_start_request(struct dw_mci *host,
 592                                    struct dw_mci_slot *slot,
 593                                    struct mmc_command *cmd)
 594 {
 595         struct mmc_request *mrq;
 596         struct mmc_data *data;
 597         u32 cmdflags;
 598
 599         mrq = slot->mrq;
 600         if (host->pdata->select_slot)
 601                 host->pdata->select_slot(slot->id);
 602
 603         /* Slot specific timing and width adjustment */
 604         dw_mci_setup_bus(slot);
 605
 606         host->cur_slot = slot;
 607         host->mrq = mrq;
 608
 609         host->pending_events = 0;
 610         host->completed_events = 0;
 611         host->data_status = 0;
 612
 613         data = cmd->data;
 614         if (data) {
 615                 dw_mci_set_timeout(host);
 616                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
 617                 mci_writel(host, BLKSIZ, data->blksz);
 618         }
 619
 620         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 621
 622         /* this is the first command, send the initialization clock */
 623         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 624                 cmdflags |= SDMMC_CMD_INIT;
 625
 626         if (data) {
 627                 dw_mci_submit_data(host, data);
 628                 wmb();
 629         }
 630
 631         dw_mci_start_command(host, cmd, cmdflags);
 632
 633         if (mrq->stop)
 634                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 635 }
 636
 637 static void dw_mci_start_request(struct dw_mci *host,
 638                                  struct dw_mci_slot *slot)
 639 {
 640         struct mmc_request *mrq = slot->mrq;
 641         struct mmc_command *cmd;
 642
 643         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
 644         __dw_mci_start_request(host, slot, cmd);
 645 }
 646
 647 /* must be called with host->lock held */
 648 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 649                                  struct mmc_request *mrq)
 650 {
 651         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 652                  host->state);
 653
 654         slot->mrq = mrq;
 655
 656         if (host->state == STATE_IDLE) {
 657                 host->state = STATE_SENDING_CMD;
 658                 dw_mci_start_request(host, slot);
 659         } else {
 660                 list_add_tail(&slot->queue_node, &host->queue);
 661         }
 662 }
 663
 664 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 665 {
 666         struct dw_mci_slot *slot = mmc_priv(mmc);
 667         struct dw_mci *host = slot->host;
 668
 669         WARN_ON(slot->mrq);
 670
 671         /*
 672          * The check for card presence and queueing of the request must be
 673          * atomic, otherwise the card could be removed in between and the
 674          * request wouldn't fail until another card was inserted.
 675          */
 676         spin_lock_bh(&host->lock);
 677
 678         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 679                 spin_unlock_bh(&host->lock);
 680                 mrq->cmd->error = -ENOMEDIUM;
 681                 mmc_request_done(mmc, mrq);
 682                 return;
 683         }
 684
 685         dw_mci_queue_request(host, slot, mrq);
 686
 687         spin_unlock_bh(&host->lock);
 688 }
 689
 690 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 691 {
 692         struct dw_mci_slot *slot = mmc_priv(mmc);
 693         u32 regs;
 694
 695         /* set default 1 bit mode */
 696         slot->ctype = SDMMC_CTYPE_1BIT;
 697
 698         switch (ios->bus_width) {
 699         case MMC_BUS_WIDTH_1:
 700                 slot->ctype = SDMMC_CTYPE_1BIT;
 701                 break;
 702         case MMC_BUS_WIDTH_4:
 703                 slot->ctype = SDMMC_CTYPE_4BIT;
 704                 break;
 705         case MMC_BUS_WIDTH_8:
 706                 slot->ctype = SDMMC_CTYPE_8BIT;
 707                 break;
 708         }
 709
 710         regs = mci_readl(slot->host, UHS_REG);
 711
 712         /* DDR mode set */
 713         if (ios->timing == MMC_TIMING_UHS_DDR50)
 714                 regs |= (0x1 << slot->id) << 16;
 715         else
 716                 regs &= ~(0x1 << slot->id) << 16;
 717
 718         mci_writel(slot->host, UHS_REG, regs);
 719
 720         if (ios->clock) {
 721                 /*
 722                  * Use mirror of ios->clock to prevent race with mmc
 723                  * core ios update when finding the minimum.
 724                  */
 725                 slot->clock = ios->clock;
 726         }
 727
 728         switch (ios->power_mode) {
 729         case MMC_POWER_UP:
 730                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
 731                 break;
 732         default:
 733                 break;
 734         }
 735 }
 736
 737 static int dw_mci_get_ro(struct mmc_host *mmc)
 738 {
 739         int read_only;
 740         struct dw_mci_slot *slot = mmc_priv(mmc);
 741         struct dw_mci_board *brd = slot->host->pdata;
 742
 743         /* Use platform get_ro function, else try on board write protect */
 744         if (brd->get_ro)
 745                 read_only = brd->get_ro(slot->id);
 746         else
 747                 read_only =
 748                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
 749
 750         dev_dbg(&mmc->class_dev, "card is %s\n",
 751                 read_only ? "read-only" : "read-write");
 752
 753         return read_only;
 754 }
 755
 756 static int dw_mci_get_cd(struct mmc_host *mmc)
 757 {
 758         int present;
 759         struct dw_mci_slot *slot = mmc_priv(mmc);
 760         struct dw_mci_board *brd = slot->host->pdata;
 761
 762         /* Use platform get_cd function, else try onboard card detect */
 763         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 764                 present = 1;
 765         else if (brd->get_cd)
 766                 present = !brd->get_cd(slot->id);
 767         else
 768                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 769                         == 0 ? 1 : 0;
 770
 771         if (present)
 772                 dev_dbg(&mmc->class_dev, "card is present\n");
 773         else
 774                 dev_dbg(&mmc->class_dev, "card is not present\n");
 775
 776         return present;
 777 }
 778
 779 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
 780 {
 781         struct dw_mci_slot *slot = mmc_priv(mmc);
 782         struct dw_mci *host = slot->host;
 783         u32 int_mask;
 784
 785         /* Enable/disable Slot Specific SDIO interrupt */
 786         int_mask = mci_readl(host, INTMASK);
 787         if (enb) {
 788                 mci_writel(host, INTMASK,
 789                            (int_mask | (1 << SDMMC_INT_SDIO(slot->id))));
 790         } else {
 791                 mci_writel(host, INTMASK,
 792                            (int_mask & ~(1 << SDMMC_INT_SDIO(slot->id))));
 793         }
 794 }
 795
 796 static const struct mmc_host_ops dw_mci_ops = {
 797         .request                = dw_mci_request,
 798         .set_ios                = dw_mci_set_ios,
 799         .get_ro                 = dw_mci_get_ro,
 800         .get_cd                 = dw_mci_get_cd,
 801         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
 802 };
 803
 804 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
 805         __releases(&host->lock)
 806         __acquires(&host->lock)
 807 {
 808         struct dw_mci_slot *slot;
 809         struct mmc_host *prev_mmc = host->cur_slot->mmc;
 810
 811         WARN_ON(host->cmd || host->data);
 812
 813         host->cur_slot->mrq = NULL;
 814         host->mrq = NULL;
 815         if (!list_empty(&host->queue)) {
 816                 slot = list_entry(host->queue.next,
 817                                   struct dw_mci_slot, queue_node);
 818                 list_del(&slot->queue_node);
 819                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
 820                          mmc_hostname(slot->mmc));
 821                 host->state = STATE_SENDING_CMD;
 822                 dw_mci_start_request(host, slot);
 823         } else {
 824                 dev_vdbg(&host->pdev->dev, "list empty\n");
 825                 host->state = STATE_IDLE;
 826         }
 827
 828         spin_unlock(&host->lock);
 829         mmc_request_done(prev_mmc, mrq);
 830         spin_lock(&host->lock);
 831 }
 832
 833 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
 834 {
 835         u32 status = host->cmd_status;
 836
 837         host->cmd_status = 0;
 838
 839         /* Read the response from the card (up to 16 bytes) */
 840         if (cmd->flags & MMC_RSP_PRESENT) {
 841                 if (cmd->flags & MMC_RSP_136) {
 842                         cmd->resp[3] = mci_readl(host, RESP0);
 843                         cmd->resp[2] = mci_readl(host, RESP1);
 844                         cmd->resp[1] = mci_readl(host, RESP2);
 845                         cmd->resp[0] = mci_readl(host, RESP3);
 846                 } else {
 847                         cmd->resp[0] = mci_readl(host, RESP0);
 848                         cmd->resp[1] = 0;
 849                         cmd->resp[2] = 0;
 850                         cmd->resp[3] = 0;
 851                 }
 852         }
 853
 854         if (status & SDMMC_INT_RTO)
 855                 cmd->error = -ETIMEDOUT;
 856         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
 857                 cmd->error = -EILSEQ;
 858         else if (status & SDMMC_INT_RESP_ERR)
 859                 cmd->error = -EIO;
 860         else
 861                 cmd->error = 0;
 862
 863         if (cmd->error) {
 864                 /* newer ip versions need a delay between retries */
 865                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
 866                         mdelay(20);
 867
 868                 if (cmd->data) {
 869                         host->data = NULL;
 870                         dw_mci_stop_dma(host);
 871                 }
 872         }
 873 }
 874
 875 static void dw_mci_tasklet_func(unsigned long priv)
 876 {
 877         struct dw_mci *host = (struct dw_mci *)priv;
 878         struct mmc_data *data;
 879         struct mmc_command *cmd;
 880         enum dw_mci_state state;
 881         enum dw_mci_state prev_state;
 882         u32 status, ctrl;
 883
 884         spin_lock(&host->lock);
 885
 886         state = host->state;
 887         data = host->data;
 888
 889         do {
 890                 prev_state = state;
 891
 892                 switch (state) {
 893                 case STATE_IDLE:
 894                         break;
 895
 896                 case STATE_SENDING_CMD:
 897                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
 898                                                 &host->pending_events))
 899                                 break;
 900
 901                         cmd = host->cmd;
 902                         host->cmd = NULL;
 903                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
 904                         dw_mci_command_complete(host, cmd);
 905                         if (cmd == host->mrq->sbc && !cmd->error) {
 906                                 prev_state = state = STATE_SENDING_CMD;
 907                                 __dw_mci_start_request(host, host->cur_slot,
 908                                                        host->mrq->cmd);
 909                                 goto unlock;
 910                         }
 911
 912                         if (!host->mrq->data || cmd->error) {
 913                                 dw_mci_request_end(host, host->mrq);
 914                                 goto unlock;
 915                         }
 916
 917                         prev_state = state = STATE_SENDING_DATA;
 918                         /* fall through */
 919
 920                 case STATE_SENDING_DATA:
 921                         if (test_and_clear_bit(EVENT_DATA_ERROR,
 922                                                &host->pending_events)) {
 923                                 dw_mci_stop_dma(host);
 924                                 if (data->stop)
 925                                         send_stop_cmd(host, data);
 926                                 state = STATE_DATA_ERROR;
 927                                 break;
 928                         }
 929
 930                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
 931                                                 &host->pending_events))
 932                                 break;
 933
 934                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
 935                         prev_state = state = STATE_DATA_BUSY;
 936                         /* fall through */
 937
 938                 case STATE_DATA_BUSY:
 939                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
 940                                                 &host->pending_events))
 941                                 break;
 942
 943                         host->data = NULL;
 944                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
 945                         status = host->data_status;
 946
 947                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
 948                                 if (status & SDMMC_INT_DTO) {
 949                                         data->error = -ETIMEDOUT;
 950                                 } else if (status & SDMMC_INT_DCRC) {
 951                                         data->error = -EILSEQ;
 952                                 } else if (status & SDMMC_INT_EBE &&
 953                                            host->dir_status ==
 954                                                         DW_MCI_SEND_STATUS) {
 955                                         /*
 956                                          * No data CRC status was returned.
 957                                          * The number of bytes transferred will
 958                                          * be exaggerated in PIO mode.
 959                                          */
 960                                         data->bytes_xfered = 0;
 961                                         data->error = -ETIMEDOUT;
 962                                 } else {
 963                                         dev_err(&host->pdev->dev,
 964                                                 "data FIFO error "
 965                                                 "(status=%08x)\n",
 966                                                 status);
 967                                         data->error = -EIO;
 968                                 }
 969                                 /*
 970                                  * After an error, there may be data lingering
 971                                  * in the FIFO, so reset it - doing so
 972                                  * generates a block interrupt, hence setting
 973                                  * the scatter-gather pointer to NULL.
 974                                  */
 975                                 host->sg = NULL;
 976                                 ctrl = mci_readl(host, CTRL);
 977                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
 978                                 mci_writel(host, CTRL, ctrl);
 979                         } else {
 980                                 data->bytes_xfered = data->blocks * data->blksz;
 981                                 data->error = 0;
 982                         }
 983
 984                         if (!data->stop) {
 985                                 dw_mci_request_end(host, host->mrq);
 986                                 goto unlock;
 987                         }
 988
 989                         if (host->mrq->sbc && !data->error) {
 990                                 data->stop->error = 0;
 991                                 dw_mci_request_end(host, host->mrq);
 992                                 goto unlock;
 993                         }
 994
 995                         prev_state = state = STATE_SENDING_STOP;
 996                         if (!data->error)
 997                                 send_stop_cmd(host, data);
 998                         /* fall through */
 999
1000                 case STATE_SENDING_STOP:
1001                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1002                                                 &host->pending_events))
1003                                 break;
1004
1005                         host->cmd = NULL;
1006                         dw_mci_command_complete(host, host->mrq->stop);
1007                         dw_mci_request_end(host, host->mrq);
1008                         goto unlock;
1009
1010                 case STATE_DATA_ERROR:
1011                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1012                                                 &host->pending_events))
1013                                 break;
1014
1015                         state = STATE_DATA_BUSY;
1016                         break;
1017                 }
1018         } while (state != prev_state);
1019
1020         host->state = state;
1021 unlock:
1022         spin_unlock(&host->lock);
1023
1024 }
1025
1026 /* push final bytes to part_buf, only use during push */
1027 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1028 {
1029         memcpy((void *)&host->part_buf, buf, cnt);
1030         host->part_buf_count = cnt;
1031 }
1032
1033 /* append bytes to part_buf, only use during push */
1034 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1035 {
1036         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1037         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1038         host->part_buf_count += cnt;
1039         return cnt;
1040 }
1041
1042 /* pull first bytes from part_buf, only use during pull */
1043 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1044 {
1045         cnt = min(cnt, (int)host->part_buf_count);
1046         if (cnt) {
1047                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1048                        cnt);
1049                 host->part_buf_count -= cnt;
1050                 host->part_buf_start += cnt;
1051         }
1052         return cnt;
1053 }
1054
1055 /* pull final bytes from the part_buf, assuming it's just been filled */
1056 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1057 {
1058         memcpy(buf, &host->part_buf, cnt);
1059         host->part_buf_start = cnt;
1060         host->part_buf_count = (1 << host->data_shift) - cnt;
1061 }
1062
1063 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1064 {
1065         /* try and push anything in the part_buf */
1066         if (unlikely(host->part_buf_count)) {
1067                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1068                 buf += len;
1069                 cnt -= len;
1070                 if (!sg_next(host->sg) || host->part_buf_count == 2) {
1071                         mci_writew(host, DATA(host->data_offset),
1072                                         host->part_buf16);
1073                         host->part_buf_count = 0;
1074                 }
1075         }
1076 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1077         if (unlikely((unsigned long)buf & 0x1)) {
1078                 while (cnt >= 2) {
1079                         u16 aligned_buf[64];
1080                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1081                         int items = len >> 1;
1082                         int i;
1083                         /* memcpy from input buffer into aligned buffer */
1084                         memcpy(aligned_buf, buf, len);
1085                         buf += len;
1086                         cnt -= len;
1087                         /* push data from aligned buffer into fifo */
1088                         for (i = 0; i < items; ++i)
1089                                 mci_writew(host, DATA(host->data_offset),
1090                                                 aligned_buf[i]);
1091                 }
1092         } else
1093 #endif
1094         {
1095                 u16 *pdata = buf;
1096                 for (; cnt >= 2; cnt -= 2)
1097                         mci_writew(host, DATA(host->data_offset), *pdata++);
1098                 buf = pdata;
1099         }
1100         /* put anything remaining in the part_buf */
1101         if (cnt) {
1102                 dw_mci_set_part_bytes(host, buf, cnt);
1103                 if (!sg_next(host->sg))
1104                         mci_writew(host, DATA(host->data_offset),
1105                                         host->part_buf16);
1106         }
1107 }
1108
1109 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1110 {
1111 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1112         if (unlikely((unsigned long)buf & 0x1)) {
1113                 while (cnt >= 2) {
1114                         /* pull data from fifo into aligned buffer */
1115                         u16 aligned_buf[64];
1116                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1117                         int items = len >> 1;
1118                         int i;
1119                         for (i = 0; i < items; ++i)
1120                                 aligned_buf[i] = mci_readw(host,
1121                                                 DATA(host->data_offset));
1122                         /* memcpy from aligned buffer into output buffer */
1123                         memcpy(buf, aligned_buf, len);
1124                         buf += len;
1125                         cnt -= len;
1126                 }
1127         } else
1128 #endif
1129         {
1130                 u16 *pdata = buf;
1131                 for (; cnt >= 2; cnt -= 2)
1132                         *pdata++ = mci_readw(host, DATA(host->data_offset));
1133                 buf = pdata;
1134         }
1135         if (cnt) {
1136                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1137                 dw_mci_pull_final_bytes(host, buf, cnt);
1138         }
1139 }
1140
1141 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1142 {
1143         /* try and push anything in the part_buf */
1144         if (unlikely(host->part_buf_count)) {
1145                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1146                 buf += len;
1147                 cnt -= len;
1148                 if (!sg_next(host->sg) || host->part_buf_count == 4) {
1149                         mci_writel(host, DATA(host->data_offset),
1150                                         host->part_buf32);
1151                         host->part_buf_count = 0;
1152                 }
1153         }
1154 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1155         if (unlikely((unsigned long)buf & 0x3)) {
1156                 while (cnt >= 4) {
1157                         u32 aligned_buf[32];
1158                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1159                         int items = len >> 2;
1160                         int i;
1161                         /* memcpy from input buffer into aligned buffer */
1162                         memcpy(aligned_buf, buf, len);
1163                         buf += len;
1164                         cnt -= len;
1165                         /* push data from aligned buffer into fifo */
1166                         for (i = 0; i < items; ++i)
1167                                 mci_writel(host, DATA(host->data_offset),
1168                                                 aligned_buf[i]);
1169                 }
1170         } else
1171 #endif
1172         {
1173                 u32 *pdata = buf;
1174                 for (; cnt >= 4; cnt -= 4)
1175                         mci_writel(host, DATA(host->data_offset), *pdata++);
1176                 buf = pdata;
1177         }
1178         /* put anything remaining in the part_buf */
1179         if (cnt) {
1180                 dw_mci_set_part_bytes(host, buf, cnt);
1181                 if (!sg_next(host->sg))
1182                         mci_writel(host, DATA(host->data_offset),
1183                                                 host->part_buf32);
1184         }
1185 }
1186
1187 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1188 {
1189 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1190         if (unlikely((unsigned long)buf & 0x3)) {
1191                 while (cnt >= 4) {
1192                         /* pull data from fifo into aligned buffer */
1193                         u32 aligned_buf[32];
1194                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1195                         int items = len >> 2;
1196                         int i;
1197                         for (i = 0; i < items; ++i)
1198                                 aligned_buf[i] = mci_readl(host,
1199                                                 DATA(host->data_offset));
1200                         /* memcpy from aligned buffer into output buffer */
1201                         memcpy(buf, aligned_buf, len);
1202                         buf += len;
1203                         cnt -= len;
1204                 }
1205         } else
1206 #endif
1207         {
1208                 u32 *pdata = buf;
1209                 for (; cnt >= 4; cnt -= 4)
1210                         *pdata++ = mci_readl(host, DATA(host->data_offset));
1211                 buf = pdata;
1212         }
1213         if (cnt) {
1214                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1215                 dw_mci_pull_final_bytes(host, buf, cnt);
1216         }
1217 }
1218
1219 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1220 {
1221         /* try and push anything in the part_buf */
1222         if (unlikely(host->part_buf_count)) {
1223                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1224                 buf += len;
1225                 cnt -= len;
1226                 if (!sg_next(host->sg) || host->part_buf_count == 8) {
1227                         mci_writew(host, DATA(host->data_offset),
1228                                         host->part_buf);
1229                         host->part_buf_count = 0;
1230                 }
1231         }
1232 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1233         if (unlikely((unsigned long)buf & 0x7)) {
1234                 while (cnt >= 8) {
1235                         u64 aligned_buf[16];
1236                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1237                         int items = len >> 3;
1238                         int i;
1239                         /* memcpy from input buffer into aligned buffer */
1240                         memcpy(aligned_buf, buf, len);
1241                         buf += len;
1242                         cnt -= len;
1243                         /* push data from aligned buffer into fifo */
1244                         for (i = 0; i < items; ++i)
1245                                 mci_writeq(host, DATA(host->data_offset),
1246                                                 aligned_buf[i]);
1247                 }
1248         } else
1249 #endif
1250         {
1251                 u64 *pdata = buf;
1252                 for (; cnt >= 8; cnt -= 8)
1253                         mci_writeq(host, DATA(host->data_offset), *pdata++);
1254                 buf = pdata;
1255         }
1256         /* put anything remaining in the part_buf */
1257         if (cnt) {
1258                 dw_mci_set_part_bytes(host, buf, cnt);
1259                 if (!sg_next(host->sg))
1260                         mci_writeq(host, DATA(host->data_offset),
1261                                         host->part_buf);
1262         }
1263 }
1264
1265 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1266 {
1267 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1268         if (unlikely((unsigned long)buf & 0x7)) {
1269                 while (cnt >= 8) {
1270                         /* pull data from fifo into aligned buffer */
1271                         u64 aligned_buf[16];
1272                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1273                         int items = len >> 3;
1274                         int i;
1275                         for (i = 0; i < items; ++i)
1276                                 aligned_buf[i] = mci_readq(host,
1277                                                 DATA(host->data_offset));
1278                         /* memcpy from aligned buffer into output buffer */
1279                         memcpy(buf, aligned_buf, len);
1280                         buf += len;
1281                         cnt -= len;
1282                 }
1283         } else
1284 #endif
1285         {
1286                 u64 *pdata = buf;
1287                 for (; cnt >= 8; cnt -= 8)
1288                         *pdata++ = mci_readq(host, DATA(host->data_offset));
1289                 buf = pdata;
1290         }
1291         if (cnt) {
1292                 host->part_buf = mci_readq(host, DATA(host->data_offset));
1293                 dw_mci_pull_final_bytes(host, buf, cnt);
1294         }
1295 }
1296
1297 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1298 {
1299         int len;
1300
1301         /* get remaining partial bytes */
1302         len = dw_mci_pull_part_bytes(host, buf, cnt);
1303         if (unlikely(len == cnt))
1304                 return;
1305         buf += len;
1306         cnt -= len;
1307
1308         /* get the rest of the data */
1309         host->pull_data(host, buf, cnt);
1310 }
1311
1312 static void dw_mci_read_data_pio(struct dw_mci *host)
1313 {
1314         struct scatterlist *sg = host->sg;
1315         void *buf = sg_virt(sg);
1316         unsigned int offset = host->pio_offset;
1317         struct mmc_data *data = host->data;
1318         int shift = host->data_shift;
1319         u32 status;
1320         unsigned int nbytes = 0, len;
1321
1322         do {
1323                 len = host->part_buf_count +
1324                         (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1325                 if (offset + len <= sg->length) {
1326                         dw_mci_pull_data(host, (void *)(buf + offset), len);
1327
1328                         offset += len;
1329                         nbytes += len;
1330
1331                         if (offset == sg->length) {
1332                                 flush_dcache_page(sg_page(sg));
1333                                 host->sg = sg = sg_next(sg);
1334                                 if (!sg)
1335                                         goto done;
1336
1337                                 offset = 0;
1338                                 buf = sg_virt(sg);
1339                         }
1340                 } else {
1341                         unsigned int remaining = sg->length - offset;
1342                         dw_mci_pull_data(host, (void *)(buf + offset),
1343                                          remaining);
1344                         nbytes += remaining;
1345
1346                         flush_dcache_page(sg_page(sg));
1347                         host->sg = sg = sg_next(sg);
1348                         if (!sg)
1349                                 goto done;
1350
1351                         offset = len - remaining;
1352                         buf = sg_virt(sg);
1353                         dw_mci_pull_data(host, buf, offset);
1354                         nbytes += offset;
1355                 }
1356
1357                 status = mci_readl(host, MINTSTS);
1358                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1359                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1360                         host->data_status = status;
1361                         data->bytes_xfered += nbytes;
1362                         smp_wmb();
1363
1364                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1365
1366                         tasklet_schedule(&host->tasklet);
1367                         return;
1368                 }
1369         } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1370         host->pio_offset = offset;
1371         data->bytes_xfered += nbytes;
1372         return;
1373
1374 done:
1375         data->bytes_xfered += nbytes;
1376         smp_wmb();
1377         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1378 }
1379
1380 static void dw_mci_write_data_pio(struct dw_mci *host)
1381 {
1382         struct scatterlist *sg = host->sg;
1383         void *buf = sg_virt(sg);
1384         unsigned int offset = host->pio_offset;
1385         struct mmc_data *data = host->data;
1386         int shift = host->data_shift;
1387         u32 status;
1388         unsigned int nbytes = 0, len;
1389
1390         do {
1391                 len = ((host->fifo_depth -
1392                         SDMMC_GET_FCNT(mci_readl(host, STATUS))) << shift)
1393                         - host->part_buf_count;
1394                 if (offset + len <= sg->length) {
1395                         host->push_data(host, (void *)(buf + offset), len);
1396
1397                         offset += len;
1398                         nbytes += len;
1399                         if (offset == sg->length) {
1400                                 host->sg = sg = sg_next(sg);
1401                                 if (!sg)
1402                                         goto done;
1403
1404                                 offset = 0;
1405                                 buf = sg_virt(sg);
1406                         }
1407                 } else {
1408                         unsigned int remaining = sg->length - offset;
1409
1410                         host->push_data(host, (void *)(buf + offset),
1411                                         remaining);
1412                         nbytes += remaining;
1413
1414                         host->sg = sg = sg_next(sg);
1415                         if (!sg)
1416                                 goto done;
1417
1418                         offset = len - remaining;
1419                         buf = sg_virt(sg);
1420                         host->push_data(host, (void *)buf, offset);
1421                         nbytes += offset;
1422                 }
1423
1424                 status = mci_readl(host, MINTSTS);
1425                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1426                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1427                         host->data_status = status;
1428                         data->bytes_xfered += nbytes;
1429
1430                         smp_wmb();
1431
1432                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1433
1434                         tasklet_schedule(&host->tasklet);
1435                         return;
1436                 }
1437         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1438         host->pio_offset = offset;
1439         data->bytes_xfered += nbytes;
1440         return;
1441
1442 done:
1443         data->bytes_xfered += nbytes;
1444         smp_wmb();
1445         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1446 }
1447
1448 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1449 {
1450         if (!host->cmd_status)
1451                 host->cmd_status = status;
1452
1453         smp_wmb();
1454
1455         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1456         tasklet_schedule(&host->tasklet);
1457 }
1458
1459 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1460 {
1461         struct dw_mci *host = dev_id;
1462         u32 status, pending;
1463         unsigned int pass_count = 0;
1464         int i;
1465
1466         do {
1467                 status = mci_readl(host, RINTSTS);
1468                 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1469
1470                 /*
1471                  * DTO fix - version 2.10a and below, and only if internal DMA
1472                  * is configured.
1473                  */
1474                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1475                         if (!pending &&
1476                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1477                                 pending |= SDMMC_INT_DATA_OVER;
1478                 }
1479
1480                 if (!pending)
1481                         break;
1482
1483                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1484                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1485                         host->cmd_status = status;
1486                         smp_wmb();
1487                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1488                 }
1489
1490                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1491                         /* if there is an error report DATA_ERROR */
1492                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1493                         host->data_status = status;
1494                         smp_wmb();
1495                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1496                         if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1497                                          SDMMC_INT_SBE | SDMMC_INT_EBE)))
1498                                 tasklet_schedule(&host->tasklet);
1499                 }
1500
1501                 if (pending & SDMMC_INT_DATA_OVER) {
1502                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1503                         if (!host->data_status)
1504                                 host->data_status = status;
1505                         smp_wmb();
1506                         if (host->dir_status == DW_MCI_RECV_STATUS) {
1507                                 if (host->sg != NULL)
1508                                         dw_mci_read_data_pio(host);
1509                         }
1510                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1511                         tasklet_schedule(&host->tasklet);
1512                 }
1513
1514                 if (pending & SDMMC_INT_RXDR) {
1515                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1516                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
1517                                 dw_mci_read_data_pio(host);
1518                 }
1519
1520                 if (pending & SDMMC_INT_TXDR) {
1521                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1522                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
1523                                 dw_mci_write_data_pio(host);
1524                 }
1525
1526                 if (pending & SDMMC_INT_CMD_DONE) {
1527                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1528                         dw_mci_cmd_interrupt(host, status);
1529                 }
1530
1531                 if (pending & SDMMC_INT_CD) {
1532                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
1533                         queue_work(dw_mci_card_workqueue, &host->card_work);
1534                 }
1535
1536                 /* Handle SDIO Interrupts */
1537                 for (i = 0; i < host->num_slots; i++) {
1538                         struct dw_mci_slot *slot = host->slot[i];
1539                         if (pending & SDMMC_INT_SDIO(i)) {
1540                                 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1541                                 mmc_signal_sdio_irq(slot->mmc);
1542                         }
1543                 }
1544
1545         } while (pass_count++ < 5);
1546
1547 #ifdef CONFIG_MMC_DW_IDMAC
1548         /* Handle DMA interrupts */
1549         pending = mci_readl(host, IDSTS);
1550         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1551                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1552                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1553                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1554                 host->dma_ops->complete(host);
1555         }
1556 #endif
1557
1558         return IRQ_HANDLED;
1559 }
1560
1561 static void dw_mci_work_routine_card(struct work_struct *work)
1562 {
1563         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
1564         int i;
1565
1566         for (i = 0; i < host->num_slots; i++) {
1567                 struct dw_mci_slot *slot = host->slot[i];
1568                 struct mmc_host *mmc = slot->mmc;
1569                 struct mmc_request *mrq;
1570                 int present;
1571                 u32 ctrl;
1572
1573                 present = dw_mci_get_cd(mmc);
1574                 while (present != slot->last_detect_state) {
1575                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
1576                                 present ? "inserted" : "removed");
1577
1578                         /* Power up slot (before spin_lock, may sleep) */
1579                         if (present != 0 && host->pdata->setpower)
1580                                 host->pdata->setpower(slot->id, mmc->ocr_avail);
1581
1582                         spin_lock_bh(&host->lock);
1583
1584                         /* Card change detected */
1585                         slot->last_detect_state = present;
1586
1587                         /* Mark card as present if applicable */
1588                         if (present != 0)
1589                                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1590
1591                         /* Clean up queue if present */
1592                         mrq = slot->mrq;
1593                         if (mrq) {
1594                                 if (mrq == host->mrq) {
1595                                         host->data = NULL;
1596                                         host->cmd = NULL;
1597
1598                                         switch (host->state) {
1599                                         case STATE_IDLE:
1600                                                 break;
1601                                         case STATE_SENDING_CMD:
1602                                                 mrq->cmd->error = -ENOMEDIUM;
1603                                                 if (!mrq->data)
1604                                                         break;
1605                                                 /* fall through */
1606                                         case STATE_SENDING_DATA:
1607                                                 mrq->data->error = -ENOMEDIUM;
1608                                                 dw_mci_stop_dma(host);
1609                                                 break;
1610                                         case STATE_DATA_BUSY:
1611                                         case STATE_DATA_ERROR:
1612                                                 if (mrq->data->error == -EINPROGRESS)
1613                                                         mrq->data->error = -ENOMEDIUM;
1614                                                 if (!mrq->stop)
1615                                                         break;
1616                                                 /* fall through */
1617                                         case STATE_SENDING_STOP:
1618                                                 mrq->stop->error = -ENOMEDIUM;
1619                                                 break;
1620                                         }
1621
1622                                         dw_mci_request_end(host, mrq);
1623                                 } else {
1624                                         list_del(&slot->queue_node);
1625                                         mrq->cmd->error = -ENOMEDIUM;
1626                                         if (mrq->data)
1627                                                 mrq->data->error = -ENOMEDIUM;
1628                                         if (mrq->stop)
1629                                                 mrq->stop->error = -ENOMEDIUM;
1630
1631                                         spin_unlock(&host->lock);
1632                                         mmc_request_done(slot->mmc, mrq);
1633                                         spin_lock(&host->lock);
1634                                 }
1635                         }
1636
1637                         /* Power down slot */
1638                         if (present == 0) {
1639                                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1640
1641                                 /*
1642                                  * Clear down the FIFO - doing so generates a
1643                                  * block interrupt, hence setting the
1644                                  * scatter-gather pointer to NULL.
1645                                  */
1646                                 host->sg = NULL;
1647
1648                                 ctrl = mci_readl(host, CTRL);
1649                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1650                                 mci_writel(host, CTRL, ctrl);
1651
1652 #ifdef CONFIG_MMC_DW_IDMAC
1653                                 ctrl = mci_readl(host, BMOD);
1654                                 ctrl |= 0x01; /* Software reset of DMA */
1655                                 mci_writel(host, BMOD, ctrl);
1656 #endif
1657
1658                         }
1659
1660                         spin_unlock_bh(&host->lock);
1661
1662                         /* Power down slot (after spin_unlock, may sleep) */
1663                         if (present == 0 && host->pdata->setpower)
1664                                 host->pdata->setpower(slot->id, 0);
1665
1666                         present = dw_mci_get_cd(mmc);
1667                 }
1668
1669                 mmc_detect_change(slot->mmc,
1670                         msecs_to_jiffies(host->pdata->detect_delay_ms));
1671         }
1672 }
1673
1674 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1675 {
1676         struct mmc_host *mmc;
1677         struct dw_mci_slot *slot;
1678
1679         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1680         if (!mmc)
1681                 return -ENOMEM;
1682
1683         slot = mmc_priv(mmc);
1684         slot->id = id;
1685         slot->mmc = mmc;
1686         slot->host = host;
1687
1688         mmc->ops = &dw_mci_ops;
1689         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1690         mmc->f_max = host->bus_hz;
1691
1692         if (host->pdata->get_ocr)
1693                 mmc->ocr_avail = host->pdata->get_ocr(id);
1694         else
1695                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1696
1697         /*
1698          * Start with slot power disabled, it will be enabled when a card
1699          * is detected.
1700          */
1701         if (host->pdata->setpower)
1702                 host->pdata->setpower(id, 0);
1703
1704         if (host->pdata->caps)
1705                 mmc->caps = host->pdata->caps;
1706
1707         if (host->pdata->caps2)
1708                 mmc->caps2 = host->pdata->caps2;
1709
1710         if (host->pdata->get_bus_wd)
1711                 if (host->pdata->get_bus_wd(slot->id) >= 4)
1712                         mmc->caps |= MMC_CAP_4_BIT_DATA;
1713
1714         if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1715                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
1716
1717 #ifdef CONFIG_MMC_DW_IDMAC
1718         mmc->max_segs = host->ring_size;
1719         mmc->max_blk_size = 65536;
1720         mmc->max_blk_count = host->ring_size;
1721         mmc->max_seg_size = 0x1000;
1722         mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1723 #else
1724         if (host->pdata->blk_settings) {
1725                 mmc->max_segs = host->pdata->blk_settings->max_segs;
1726                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1727                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1728                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1729                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1730         } else {
1731                 /* Useful defaults if platform data is unset. */
1732                 mmc->max_segs = 64;
1733                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1734                 mmc->max_blk_count = 512;
1735                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1736                 mmc->max_seg_size = mmc->max_req_size;
1737         }
1738 #endif /* CONFIG_MMC_DW_IDMAC */
1739
1740         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1741         if (IS_ERR(host->vmmc)) {
1742                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
1743                 host->vmmc = NULL;
1744         } else
1745                 regulator_enable(host->vmmc);
1746
1747         if (dw_mci_get_cd(mmc))
1748                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1749         else
1750                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1751
1752         host->slot[id] = slot;
1753         mmc_add_host(mmc);
1754
1755 #if defined(CONFIG_DEBUG_FS)
1756         dw_mci_init_debugfs(slot);
1757 #endif
1758
1759         /* Card initially undetected */
1760         slot->last_detect_state = 0;
1761
1762         /*
1763          * Card may have been plugged in prior to boot so we
1764          * need to run the detect tasklet
1765          */
1766         queue_work(dw_mci_card_workqueue, &host->card_work);
1767
1768         return 0;
1769 }
1770
1771 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1772 {
1773         /* Shutdown detect IRQ */
1774         if (slot->host->pdata->exit)
1775                 slot->host->pdata->exit(id);
1776
1777         /* Debugfs stuff is cleaned up by mmc core */
1778         mmc_remove_host(slot->mmc);
1779         slot->host->slot[id] = NULL;
1780         mmc_free_host(slot->mmc);
1781 }
1782
1783 static void dw_mci_init_dma(struct dw_mci *host)
1784 {
1785         /* Alloc memory for sg translation */
1786         host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1787                                           &host->sg_dma, GFP_KERNEL);
1788         if (!host->sg_cpu) {
1789                 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1790                         __func__);
1791                 goto no_dma;
1792         }
1793
1794         /* Determine which DMA interface to use */
1795 #ifdef CONFIG_MMC_DW_IDMAC
1796         host->dma_ops = &dw_mci_idmac_ops;
1797         dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1798 #endif
1799
1800         if (!host->dma_ops)
1801                 goto no_dma;
1802
1803         if (host->dma_ops->init) {
1804                 if (host->dma_ops->init(host)) {
1805                         dev_err(&host->pdev->dev, "%s: Unable to initialize "
1806                                 "DMA Controller.\n", __func__);
1807                         goto no_dma;
1808                 }
1809         } else {
1810                 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1811                 goto no_dma;
1812         }
1813
1814         host->use_dma = 1;
1815         return;
1816
1817 no_dma:
1818         dev_info(&host->pdev->dev, "Using PIO mode.\n");
1819         host->use_dma = 0;
1820         return;
1821 }
1822
1823 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1824 {
1825         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1826         unsigned int ctrl;
1827
1828         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1829                                 SDMMC_CTRL_DMA_RESET));
1830
1831         /* wait till resets clear */
1832         do {
1833                 ctrl = mci_readl(host, CTRL);
1834                 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1835                               SDMMC_CTRL_DMA_RESET)))
1836                         return true;
1837         } while (time_before(jiffies, timeout));
1838
1839         dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1840
1841         return false;
1842 }
1843
1844 static int dw_mci_probe(struct platform_device *pdev)
1845 {
1846         struct dw_mci *host;
1847         struct resource *regs;
1848         struct dw_mci_board *pdata;
1849         int irq, ret, i, width;
1850         u32 fifo_size;
1851
1852         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1853         if (!regs)
1854                 return -ENXIO;
1855
1856         irq = platform_get_irq(pdev, 0);
1857         if (irq < 0)
1858                 return irq;
1859
1860         host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1861         if (!host)
1862                 return -ENOMEM;
1863
1864         host->pdev = pdev;
1865         host->pdata = pdata = pdev->dev.platform_data;
1866         if (!pdata || !pdata->init) {
1867                 dev_err(&pdev->dev,
1868                         "Platform data must supply init function\n");
1869                 ret = -ENODEV;
1870                 goto err_freehost;
1871         }
1872
1873         if (!pdata->select_slot && pdata->num_slots > 1) {
1874                 dev_err(&pdev->dev,
1875                         "Platform data must supply select_slot function\n");
1876                 ret = -ENODEV;
1877                 goto err_freehost;
1878         }
1879
1880         if (!pdata->bus_hz) {
1881                 dev_err(&pdev->dev,
1882                         "Platform data must supply bus speed\n");
1883                 ret = -ENODEV;
1884                 goto err_freehost;
1885         }
1886
1887         host->bus_hz = pdata->bus_hz;
1888         host->quirks = pdata->quirks;
1889
1890         spin_lock_init(&host->lock);
1891         INIT_LIST_HEAD(&host->queue);
1892
1893         ret = -ENOMEM;
1894         host->regs = ioremap(regs->start, resource_size(regs));
1895         if (!host->regs)
1896                 goto err_freehost;
1897
1898         host->dma_ops = pdata->dma_ops;
1899         dw_mci_init_dma(host);
1900
1901         /*
1902          * Get the host data width - this assumes that HCON has been set with
1903          * the correct values.
1904          */
1905         i = (mci_readl(host, HCON) >> 7) & 0x7;
1906         if (!i) {
1907                 host->push_data = dw_mci_push_data16;
1908                 host->pull_data = dw_mci_pull_data16;
1909                 width = 16;
1910                 host->data_shift = 1;
1911         } else if (i == 2) {
1912                 host->push_data = dw_mci_push_data64;
1913                 host->pull_data = dw_mci_pull_data64;
1914                 width = 64;
1915                 host->data_shift = 3;
1916         } else {
1917                 /* Check for a reserved value, and warn if it is */
1918                 WARN((i != 1),
1919                      "HCON reports a reserved host data width!\n"
1920                      "Defaulting to 32-bit access.\n");
1921                 host->push_data = dw_mci_push_data32;
1922                 host->pull_data = dw_mci_pull_data32;
1923                 width = 32;
1924                 host->data_shift = 2;
1925         }
1926
1927         /* Reset all blocks */
1928         if (!mci_wait_reset(&pdev->dev, host)) {
1929                 ret = -ENODEV;
1930                 goto err_dmaunmap;
1931         }
1932
1933         /* Clear the interrupts for the host controller */
1934         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1935         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1936
1937         /* Put in max timeout */
1938         mci_writel(host, TMOUT, 0xFFFFFFFF);
1939
1940         /*
1941          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
1942          *                          Tx Mark = fifo_size / 2 DMA Size = 8
1943          */
1944         if (!host->pdata->fifo_depth) {
1945                 /*
1946                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
1947                  * have been overwritten by the bootloader, just like we're
1948                  * about to do, so if you know the value for your hardware, you
1949                  * should put it in the platform data.
1950                  */
1951                 fifo_size = mci_readl(host, FIFOTH);
1952                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
1953         } else {
1954                 fifo_size = host->pdata->fifo_depth;
1955         }
1956         host->fifo_depth = fifo_size;
1957         host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1958                         ((fifo_size/2) << 0));
1959         mci_writel(host, FIFOTH, host->fifoth_val);
1960
1961         /* disable clock to CIU */
1962         mci_writel(host, CLKENA, 0);
1963         mci_writel(host, CLKSRC, 0);
1964
1965         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1966         dw_mci_card_workqueue = alloc_workqueue("dw-mci-card",
1967                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
1968         if (!dw_mci_card_workqueue)
1969                 goto err_dmaunmap;
1970         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
1971
1972         ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1973         if (ret)
1974                 goto err_workqueue;
1975
1976         platform_set_drvdata(pdev, host);
1977
1978         if (host->pdata->num_slots)
1979                 host->num_slots = host->pdata->num_slots;
1980         else
1981                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1982
1983         /* We need at least one slot to succeed */
1984         for (i = 0; i < host->num_slots; i++) {
1985                 ret = dw_mci_init_slot(host, i);
1986                 if (ret) {
1987                         ret = -ENODEV;
1988                         goto err_init_slot;
1989                 }
1990         }
1991
1992         /*
1993          * In 2.40a spec, Data offset is changed.
1994          * Need to check the version-id and set data-offset for DATA register.
1995          */
1996         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
1997         dev_info(&pdev->dev, "Version ID is %04x\n", host->verid);
1998
1999         if (host->verid < DW_MMC_240A)
2000                 host->data_offset = DATA_OFFSET;
2001         else
2002                 host->data_offset = DATA_240A_OFFSET;
2003
2004         /*
2005          * Enable interrupts for command done, data over, data empty, card det,
2006          * receive ready and error such as transmit, receive timeout, crc error
2007          */
2008         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2009         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2010                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2011                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2012         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2013
2014         dev_info(&pdev->dev, "DW MMC controller at irq %d, "
2015                  "%d bit host data width, "
2016                  "%u deep fifo\n",
2017                  irq, width, fifo_size);
2018         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2019                 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
2020
2021         return 0;
2022
2023 err_init_slot:
2024         /* De-init any initialized slots */
2025         while (i > 0) {
2026                 if (host->slot[i])
2027                         dw_mci_cleanup_slot(host->slot[i], i);
2028                 i--;
2029         }
2030         free_irq(irq, host);
2031
2032 err_workqueue:
2033         destroy_workqueue(dw_mci_card_workqueue);
2034
2035 err_dmaunmap:
2036         if (host->use_dma && host->dma_ops->exit)
2037                 host->dma_ops->exit(host);
2038         dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
2039                           host->sg_cpu, host->sg_dma);
2040         iounmap(host->regs);
2041
2042         if (host->vmmc) {
2043                 regulator_disable(host->vmmc);
2044                 regulator_put(host->vmmc);
2045         }
2046
2047
2048 err_freehost:
2049         kfree(host);
2050         return ret;
2051 }
2052
2053 static int __exit dw_mci_remove(struct platform_device *pdev)
2054 {
2055         struct dw_mci *host = platform_get_drvdata(pdev);
2056         int i;
2057
2058         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2059         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2060
2061         platform_set_drvdata(pdev, NULL);
2062
2063         for (i = 0; i < host->num_slots; i++) {
2064                 dev_dbg(&pdev->dev, "remove slot %d\n", i);
2065                 if (host->slot[i])
2066                         dw_mci_cleanup_slot(host->slot[i], i);
2067         }
2068
2069         /* disable clock to CIU */
2070         mci_writel(host, CLKENA, 0);
2071         mci_writel(host, CLKSRC, 0);
2072
2073         free_irq(platform_get_irq(pdev, 0), host);
2074         destroy_workqueue(dw_mci_card_workqueue);
2075         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
2076
2077         if (host->use_dma && host->dma_ops->exit)
2078                 host->dma_ops->exit(host);
2079
2080         if (host->vmmc) {
2081                 regulator_disable(host->vmmc);
2082                 regulator_put(host->vmmc);
2083         }
2084
2085         iounmap(host->regs);
2086
2087         kfree(host);
2088         return 0;
2089 }
2090
2091 #ifdef CONFIG_PM_SLEEP
2092 /*
2093  * TODO: we should probably disable the clock to the card in the suspend path.
2094  */
2095 static int dw_mci_suspend(struct device *dev)
2096 {
2097         int i, ret;
2098         struct dw_mci *host = dev_get_drvdata(dev);
2099
2100         for (i = 0; i < host->num_slots; i++) {
2101                 struct dw_mci_slot *slot = host->slot[i];
2102                 if (!slot)
2103                         continue;
2104                 ret = mmc_suspend_host(slot->mmc);
2105                 if (ret < 0) {
2106                         while (--i >= 0) {
2107                                 slot = host->slot[i];
2108                                 if (slot)
2109                                         mmc_resume_host(host->slot[i]->mmc);
2110                         }
2111                         return ret;
2112                 }
2113         }
2114
2115         if (host->vmmc)
2116                 regulator_disable(host->vmmc);
2117
2118         return 0;
2119 }
2120
2121 static int dw_mci_resume(struct device *dev)
2122 {
2123         int i, ret;
2124         struct dw_mci *host = dev_get_drvdata(dev);
2125
2126         if (host->vmmc)
2127                 regulator_enable(host->vmmc);
2128
2129         if (host->dma_ops->init)
2130                 host->dma_ops->init(host);
2131
2132         if (!mci_wait_reset(dev, host)) {
2133                 ret = -ENODEV;
2134                 return ret;
2135         }
2136
2137         /* Restore the old value at FIFOTH register */
2138         mci_writel(host, FIFOTH, host->fifoth_val);
2139
2140         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2141         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2142                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2143                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2144         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2145
2146         for (i = 0; i < host->num_slots; i++) {
2147                 struct dw_mci_slot *slot = host->slot[i];
2148                 if (!slot)
2149                         continue;
2150                 ret = mmc_resume_host(host->slot[i]->mmc);
2151                 if (ret < 0)
2152                         return ret;
2153         }
2154
2155         return 0;
2156 }
2157 #else
2158 #define dw_mci_suspend  NULL
2159 #define dw_mci_resume   NULL
2160 #endif /* CONFIG_PM_SLEEP */
2161
2162 static SIMPLE_DEV_PM_OPS(dw_mci_pmops, dw_mci_suspend, dw_mci_resume);
2163
2164 static struct platform_driver dw_mci_driver = {
2165         .remove         = __exit_p(dw_mci_remove),
2166         .driver         = {
2167                 .name           = "dw_mmc",
2168                 .pm             = &dw_mci_pmops,
2169         },
2170 };
2171
2172 static int __init dw_mci_init(void)
2173 {
2174         return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
2175 }
2176
2177 static void __exit dw_mci_exit(void)
2178 {
2179         platform_driver_unregister(&dw_mci_driver);
2180 }
2181
2182 module_init(dw_mci_init);
2183 module_exit(dw_mci_exit);
2184
2185 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2186 MODULE_AUTHOR("NXP Semiconductor VietNam");
2187 MODULE_AUTHOR("Imagination Technologies Ltd");
2188 MODULE_LICENSE("GPL v2");