Pileus Git - ~andy/linux/blob - drivers/mmc/host/dw_mmc-exynos.c

   1 /*
   2  * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
   3  *
   4  * Copyright (C) 2012, Samsung Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/mmc/dw_mmc.h>
  17 #include <linux/of.h>
  18 #include <linux/of_gpio.h>
  19
  20 #include "dw_mmc.h"
  21 #include "dw_mmc-pltfm.h"
  22
  23 #define NUM_PINS(x)                     (x + 2)
  24
  25 #define SDMMC_CLKSEL                    0x09C
  26 #define SDMMC_CLKSEL_CCLK_SAMPLE(x)     (((x) & 7) << 0)
  27 #define SDMMC_CLKSEL_CCLK_DRIVE(x)      (((x) & 7) << 16)
  28 #define SDMMC_CLKSEL_CCLK_DIVIDER(x)    (((x) & 7) << 24)
  29 #define SDMMC_CLKSEL_GET_DRV_WD3(x)     (((x) >> 16) & 0x7)
  30 #define SDMMC_CLKSEL_TIMING(x, y, z)    (SDMMC_CLKSEL_CCLK_SAMPLE(x) |  \
  31                                         SDMMC_CLKSEL_CCLK_DRIVE(y) |    \
  32                                         SDMMC_CLKSEL_CCLK_DIVIDER(z))
  33
  34 #define SDMMC_CMD_USE_HOLD_REG          BIT(29)
  35
  36 #define EXYNOS4210_FIXED_CIU_CLK_DIV    2
  37 #define EXYNOS4412_FIXED_CIU_CLK_DIV    4
  38
  39 /* Variations in Exynos specific dw-mshc controller */
  40 enum dw_mci_exynos_type {
  41         DW_MCI_TYPE_EXYNOS4210,
  42         DW_MCI_TYPE_EXYNOS4412,
  43         DW_MCI_TYPE_EXYNOS5250,
  44 };
  45
  46 /* Exynos implementation specific driver private data */
  47 struct dw_mci_exynos_priv_data {
  48         enum dw_mci_exynos_type         ctrl_type;
  49         u8                              ciu_div;
  50         u32                             sdr_timing;
  51         u32                             ddr_timing;
  52 };
  53
  54 static struct dw_mci_exynos_compatible {
  55         char                            *compatible;
  56         enum dw_mci_exynos_type         ctrl_type;
  57 } exynos_compat[] = {
  58         {
  59                 .compatible     = "samsung,exynos4210-dw-mshc",
  60                 .ctrl_type      = DW_MCI_TYPE_EXYNOS4210,
  61         }, {
  62                 .compatible     = "samsung,exynos4412-dw-mshc",
  63                 .ctrl_type      = DW_MCI_TYPE_EXYNOS4412,
  64         }, {
  65                 .compatible     = "samsung,exynos5250-dw-mshc",
  66                 .ctrl_type      = DW_MCI_TYPE_EXYNOS5250,
  67         },
  68 };
  69
  70 static int dw_mci_exynos_priv_init(struct dw_mci *host)
  71 {
  72         struct dw_mci_exynos_priv_data *priv;
  73         int idx;
  74
  75         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
  76         if (!priv) {
  77                 dev_err(host->dev, "mem alloc failed for private data\n");
  78                 return -ENOMEM;
  79         }
  80
  81         for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
  82                 if (of_device_is_compatible(host->dev->of_node,
  83                                         exynos_compat[idx].compatible))
  84                         priv->ctrl_type = exynos_compat[idx].ctrl_type;
  85         }
  86
  87         host->priv = priv;
  88         return 0;
  89 }
  90
  91 static int dw_mci_exynos_setup_clock(struct dw_mci *host)
  92 {
  93         struct dw_mci_exynos_priv_data *priv = host->priv;
  94
  95         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250)
  96                 host->bus_hz /= (priv->ciu_div + 1);
  97         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
  98                 host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
  99         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
 100                 host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;
 101
 102         return 0;
 103 }
 104
 105 static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
 106 {
 107         /*
 108          * Exynos4412 and Exynos5250 extends the use of CMD register with the
 109          * use of bit 29 (which is reserved on standard MSHC controllers) for
 110          * optionally bypassing the HOLD register for command and data. The
 111          * HOLD register should be bypassed in case there is no phase shift
 112          * applied on CMD/DATA that is sent to the card.
 113          */
 114         if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
 115                 *cmdr |= SDMMC_CMD_USE_HOLD_REG;
 116 }
 117
 118 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 119 {
 120         struct dw_mci_exynos_priv_data *priv = host->priv;
 121
 122         if (ios->timing == MMC_TIMING_UHS_DDR50)
 123                 mci_writel(host, CLKSEL, priv->ddr_timing);
 124         else
 125                 mci_writel(host, CLKSEL, priv->sdr_timing);
 126 }
 127
 128 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 129 {
 130         struct dw_mci_exynos_priv_data *priv = host->priv;
 131         struct device_node *np = host->dev->of_node;
 132         u32 timing[2];
 133         u32 div = 0;
 134         int ret;
 135
 136         of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
 137         priv->ciu_div = div;
 138
 139         ret = of_property_read_u32_array(np,
 140                         "samsung,dw-mshc-sdr-timing", timing, 2);
 141         if (ret)
 142                 return ret;
 143
 144         priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 145
 146         ret = of_property_read_u32_array(np,
 147                         "samsung,dw-mshc-ddr-timing", timing, 2);
 148         if (ret)
 149                 return ret;
 150
 151         priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 152         return 0;
 153 }
 154
 155 /* Common capabilities of Exynos4/Exynos5 SoC */
 156 static unsigned long exynos_dwmmc_caps[4] = {
 157         MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
 158                 MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
 159         MMC_CAP_CMD23,
 160         MMC_CAP_CMD23,
 161         MMC_CAP_CMD23,
 162 };
 163
 164 static const struct dw_mci_drv_data exynos_drv_data = {
 165         .caps                   = exynos_dwmmc_caps,
 166         .init                   = dw_mci_exynos_priv_init,
 167         .setup_clock            = dw_mci_exynos_setup_clock,
 168         .prepare_command        = dw_mci_exynos_prepare_command,
 169         .set_ios                = dw_mci_exynos_set_ios,
 170         .parse_dt               = dw_mci_exynos_parse_dt,
 171 };
 172
 173 static const struct of_device_id dw_mci_exynos_match[] = {
 174         { .compatible = "samsung,exynos4412-dw-mshc",
 175                         .data = &exynos_drv_data, },
 176         { .compatible = "samsung,exynos5250-dw-mshc",
 177                         .data = &exynos_drv_data, },
 178         {},
 179 };
 180 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
 181
 182 static int dw_mci_exynos_probe(struct platform_device *pdev)
 183 {
 184         const struct dw_mci_drv_data *drv_data;
 185         const struct of_device_id *match;
 186
 187         match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
 188         drv_data = match->data;
 189         return dw_mci_pltfm_register(pdev, drv_data);
 190 }
 191
 192 static struct platform_driver dw_mci_exynos_pltfm_driver = {
 193         .probe          = dw_mci_exynos_probe,
 194         .remove         = __exit_p(dw_mci_pltfm_remove),
 195         .driver         = {
 196                 .name           = "dwmmc_exynos",
 197                 .of_match_table = dw_mci_exynos_match,
 198                 .pm             = &dw_mci_pltfm_pmops,
 199         },
 200 };
 201
 202 module_platform_driver(dw_mci_exynos_pltfm_driver);
 203
 204 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
 205 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
 206 MODULE_LICENSE("GPL v2");
 207 MODULE_ALIAS("platform:dwmmc-exynos");