Pileus Git - ~andy/linux/blob - drivers/mfd/db8500-prcmu.c

   1 /*
   2  * Copyright (C) STMicroelectronics 2009
   3  * Copyright (C) ST-Ericsson SA 2010
   4  *
   5  * License Terms: GNU General Public License v2
   6  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   7  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
   8  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
   9  *
  10  * U8500 PRCM Unit interface driver
  11  *
  12  */
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/io.h>
  20 #include <linux/slab.h>
  21 #include <linux/mutex.h>
  22 #include <linux/completion.h>
  23 #include <linux/irq.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/bitops.h>
  26 #include <linux/fs.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/mfd/core.h>
  30 #include <linux/mfd/dbx500-prcmu.h>
  31 #include <linux/regulator/db8500-prcmu.h>
  32 #include <linux/regulator/machine.h>
  33 #include <mach/hardware.h>
  34 #include <mach/irqs.h>
  35 #include <mach/db8500-regs.h>
  36 #include <mach/id.h>
  37 #include "dbx500-prcmu-regs.h"
  38
  39 /* Offset for the firmware version within the TCPM */
  40 #define PRCMU_FW_VERSION_OFFSET 0xA4
  41
  42 /* PRCMU project numbers, defined by PRCMU FW */
  43 #define PRCMU_PROJECT_ID_8500V1_0 1
  44 #define PRCMU_PROJECT_ID_8500V2_0 2
  45 #define PRCMU_PROJECT_ID_8400V2_0 3
  46
  47 /* Index of different voltages to be used when accessing AVSData */
  48 #define PRCM_AVS_BASE           0x2FC
  49 #define PRCM_AVS_VBB_RET        (PRCM_AVS_BASE + 0x0)
  50 #define PRCM_AVS_VBB_MAX_OPP    (PRCM_AVS_BASE + 0x1)
  51 #define PRCM_AVS_VBB_100_OPP    (PRCM_AVS_BASE + 0x2)
  52 #define PRCM_AVS_VBB_50_OPP     (PRCM_AVS_BASE + 0x3)
  53 #define PRCM_AVS_VARM_MAX_OPP   (PRCM_AVS_BASE + 0x4)
  54 #define PRCM_AVS_VARM_100_OPP   (PRCM_AVS_BASE + 0x5)
  55 #define PRCM_AVS_VARM_50_OPP    (PRCM_AVS_BASE + 0x6)
  56 #define PRCM_AVS_VARM_RET       (PRCM_AVS_BASE + 0x7)
  57 #define PRCM_AVS_VAPE_100_OPP   (PRCM_AVS_BASE + 0x8)
  58 #define PRCM_AVS_VAPE_50_OPP    (PRCM_AVS_BASE + 0x9)
  59 #define PRCM_AVS_VMOD_100_OPP   (PRCM_AVS_BASE + 0xA)
  60 #define PRCM_AVS_VMOD_50_OPP    (PRCM_AVS_BASE + 0xB)
  61 #define PRCM_AVS_VSAFE          (PRCM_AVS_BASE + 0xC)
  62
  63 #define PRCM_AVS_VOLTAGE                0
  64 #define PRCM_AVS_VOLTAGE_MASK           0x3f
  65 #define PRCM_AVS_ISSLOWSTARTUP          6
  66 #define PRCM_AVS_ISSLOWSTARTUP_MASK     (1 << PRCM_AVS_ISSLOWSTARTUP)
  67 #define PRCM_AVS_ISMODEENABLE           7
  68 #define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
  69
  70 #define PRCM_BOOT_STATUS        0xFFF
  71 #define PRCM_ROMCODE_A2P        0xFFE
  72 #define PRCM_ROMCODE_P2A        0xFFD
  73 #define PRCM_XP70_CUR_PWR_STATE 0xFFC      /* 4 BYTES */
  74
  75 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
  76
  77 #define _PRCM_MBOX_HEADER               0xFE8 /* 16 bytes */
  78 #define PRCM_MBOX_HEADER_REQ_MB0        (_PRCM_MBOX_HEADER + 0x0)
  79 #define PRCM_MBOX_HEADER_REQ_MB1        (_PRCM_MBOX_HEADER + 0x1)
  80 #define PRCM_MBOX_HEADER_REQ_MB2        (_PRCM_MBOX_HEADER + 0x2)
  81 #define PRCM_MBOX_HEADER_REQ_MB3        (_PRCM_MBOX_HEADER + 0x3)
  82 #define PRCM_MBOX_HEADER_REQ_MB4        (_PRCM_MBOX_HEADER + 0x4)
  83 #define PRCM_MBOX_HEADER_REQ_MB5        (_PRCM_MBOX_HEADER + 0x5)
  84 #define PRCM_MBOX_HEADER_ACK_MB0        (_PRCM_MBOX_HEADER + 0x8)
  85
  86 /* Req Mailboxes */
  87 #define PRCM_REQ_MB0 0xFDC /* 12 bytes  */
  88 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes  */
  89 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes  */
  90 #define PRCM_REQ_MB3 0xE4C /* 372 bytes  */
  91 #define PRCM_REQ_MB4 0xE48 /* 4 bytes  */
  92 #define PRCM_REQ_MB5 0xE44 /* 4 bytes  */
  93
  94 /* Ack Mailboxes */
  95 #define PRCM_ACK_MB0 0xE08 /* 52 bytes  */
  96 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
  97 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
  98 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
  99 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
 100 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
 101
 102 /* Mailbox 0 headers */
 103 #define MB0H_POWER_STATE_TRANS          0
 104 #define MB0H_CONFIG_WAKEUPS_EXE         1
 105 #define MB0H_READ_WAKEUP_ACK            3
 106 #define MB0H_CONFIG_WAKEUPS_SLEEP       4
 107
 108 #define MB0H_WAKEUP_EXE 2
 109 #define MB0H_WAKEUP_SLEEP 5
 110
 111 /* Mailbox 0 REQs */
 112 #define PRCM_REQ_MB0_AP_POWER_STATE     (PRCM_REQ_MB0 + 0x0)
 113 #define PRCM_REQ_MB0_AP_PLL_STATE       (PRCM_REQ_MB0 + 0x1)
 114 #define PRCM_REQ_MB0_ULP_CLOCK_STATE    (PRCM_REQ_MB0 + 0x2)
 115 #define PRCM_REQ_MB0_DO_NOT_WFI         (PRCM_REQ_MB0 + 0x3)
 116 #define PRCM_REQ_MB0_WAKEUP_8500        (PRCM_REQ_MB0 + 0x4)
 117 #define PRCM_REQ_MB0_WAKEUP_4500        (PRCM_REQ_MB0 + 0x8)
 118
 119 /* Mailbox 0 ACKs */
 120 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS  (PRCM_ACK_MB0 + 0x0)
 121 #define PRCM_ACK_MB0_READ_POINTER       (PRCM_ACK_MB0 + 0x1)
 122 #define PRCM_ACK_MB0_WAKEUP_0_8500      (PRCM_ACK_MB0 + 0x4)
 123 #define PRCM_ACK_MB0_WAKEUP_0_4500      (PRCM_ACK_MB0 + 0x8)
 124 #define PRCM_ACK_MB0_WAKEUP_1_8500      (PRCM_ACK_MB0 + 0x1C)
 125 #define PRCM_ACK_MB0_WAKEUP_1_4500      (PRCM_ACK_MB0 + 0x20)
 126 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
 127
 128 /* Mailbox 1 headers */
 129 #define MB1H_ARM_APE_OPP 0x0
 130 #define MB1H_RESET_MODEM 0x2
 131 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
 132 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
 133 #define MB1H_RELEASE_USB_WAKEUP 0x5
 134 #define MB1H_PLL_ON_OFF 0x6
 135
 136 /* Mailbox 1 Requests */
 137 #define PRCM_REQ_MB1_ARM_OPP                    (PRCM_REQ_MB1 + 0x0)
 138 #define PRCM_REQ_MB1_APE_OPP                    (PRCM_REQ_MB1 + 0x1)
 139 #define PRCM_REQ_MB1_PLL_ON_OFF                 (PRCM_REQ_MB1 + 0x4)
 140 #define PLL_SOC1_OFF    0x4
 141 #define PLL_SOC1_ON     0x8
 142
 143 /* Mailbox 1 ACKs */
 144 #define PRCM_ACK_MB1_CURRENT_ARM_OPP    (PRCM_ACK_MB1 + 0x0)
 145 #define PRCM_ACK_MB1_CURRENT_APE_OPP    (PRCM_ACK_MB1 + 0x1)
 146 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
 147 #define PRCM_ACK_MB1_DVFS_STATUS        (PRCM_ACK_MB1 + 0x3)
 148
 149 /* Mailbox 2 headers */
 150 #define MB2H_DPS        0x0
 151 #define MB2H_AUTO_PWR   0x1
 152
 153 /* Mailbox 2 REQs */
 154 #define PRCM_REQ_MB2_SVA_MMDSP          (PRCM_REQ_MB2 + 0x0)
 155 #define PRCM_REQ_MB2_SVA_PIPE           (PRCM_REQ_MB2 + 0x1)
 156 #define PRCM_REQ_MB2_SIA_MMDSP          (PRCM_REQ_MB2 + 0x2)
 157 #define PRCM_REQ_MB2_SIA_PIPE           (PRCM_REQ_MB2 + 0x3)
 158 #define PRCM_REQ_MB2_SGA                (PRCM_REQ_MB2 + 0x4)
 159 #define PRCM_REQ_MB2_B2R2_MCDE          (PRCM_REQ_MB2 + 0x5)
 160 #define PRCM_REQ_MB2_ESRAM12            (PRCM_REQ_MB2 + 0x6)
 161 #define PRCM_REQ_MB2_ESRAM34            (PRCM_REQ_MB2 + 0x7)
 162 #define PRCM_REQ_MB2_AUTO_PM_SLEEP      (PRCM_REQ_MB2 + 0x8)
 163 #define PRCM_REQ_MB2_AUTO_PM_IDLE       (PRCM_REQ_MB2 + 0xC)
 164
 165 /* Mailbox 2 ACKs */
 166 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
 167 #define HWACC_PWR_ST_OK 0xFE
 168
 169 /* Mailbox 3 headers */
 170 #define MB3H_ANC        0x0
 171 #define MB3H_SIDETONE   0x1
 172 #define MB3H_SYSCLK     0xE
 173
 174 /* Mailbox 3 Requests */
 175 #define PRCM_REQ_MB3_ANC_FIR_COEFF      (PRCM_REQ_MB3 + 0x0)
 176 #define PRCM_REQ_MB3_ANC_IIR_COEFF      (PRCM_REQ_MB3 + 0x20)
 177 #define PRCM_REQ_MB3_ANC_SHIFTER        (PRCM_REQ_MB3 + 0x60)
 178 #define PRCM_REQ_MB3_ANC_WARP           (PRCM_REQ_MB3 + 0x64)
 179 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN  (PRCM_REQ_MB3 + 0x68)
 180 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
 181 #define PRCM_REQ_MB3_SYSCLK_MGT         (PRCM_REQ_MB3 + 0x16C)
 182
 183 /* Mailbox 4 headers */
 184 #define MB4H_DDR_INIT   0x0
 185 #define MB4H_MEM_ST     0x1
 186 #define MB4H_HOTDOG     0x12
 187 #define MB4H_HOTMON     0x13
 188 #define MB4H_HOT_PERIOD 0x14
 189 #define MB4H_A9WDOG_CONF 0x16
 190 #define MB4H_A9WDOG_EN   0x17
 191 #define MB4H_A9WDOG_DIS  0x18
 192 #define MB4H_A9WDOG_LOAD 0x19
 193 #define MB4H_A9WDOG_KICK 0x20
 194
 195 /* Mailbox 4 Requests */
 196 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE       (PRCM_REQ_MB4 + 0x0)
 197 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE        (PRCM_REQ_MB4 + 0x1)
 198 #define PRCM_REQ_MB4_ESRAM0_ST                  (PRCM_REQ_MB4 + 0x3)
 199 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD           (PRCM_REQ_MB4 + 0x0)
 200 #define PRCM_REQ_MB4_HOTMON_LOW                 (PRCM_REQ_MB4 + 0x0)
 201 #define PRCM_REQ_MB4_HOTMON_HIGH                (PRCM_REQ_MB4 + 0x1)
 202 #define PRCM_REQ_MB4_HOTMON_CONFIG              (PRCM_REQ_MB4 + 0x2)
 203 #define PRCM_REQ_MB4_HOT_PERIOD                 (PRCM_REQ_MB4 + 0x0)
 204 #define HOTMON_CONFIG_LOW                       BIT(0)
 205 #define HOTMON_CONFIG_HIGH                      BIT(1)
 206 #define PRCM_REQ_MB4_A9WDOG_0                   (PRCM_REQ_MB4 + 0x0)
 207 #define PRCM_REQ_MB4_A9WDOG_1                   (PRCM_REQ_MB4 + 0x1)
 208 #define PRCM_REQ_MB4_A9WDOG_2                   (PRCM_REQ_MB4 + 0x2)
 209 #define PRCM_REQ_MB4_A9WDOG_3                   (PRCM_REQ_MB4 + 0x3)
 210 #define A9WDOG_AUTO_OFF_EN                      BIT(7)
 211 #define A9WDOG_AUTO_OFF_DIS                     0
 212 #define A9WDOG_ID_MASK                          0xf
 213
 214 /* Mailbox 5 Requests */
 215 #define PRCM_REQ_MB5_I2C_SLAVE_OP       (PRCM_REQ_MB5 + 0x0)
 216 #define PRCM_REQ_MB5_I2C_HW_BITS        (PRCM_REQ_MB5 + 0x1)
 217 #define PRCM_REQ_MB5_I2C_REG            (PRCM_REQ_MB5 + 0x2)
 218 #define PRCM_REQ_MB5_I2C_VAL            (PRCM_REQ_MB5 + 0x3)
 219 #define PRCMU_I2C_WRITE(slave) \
 220         (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
 221 #define PRCMU_I2C_READ(slave) \
 222         (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
 223 #define PRCMU_I2C_STOP_EN               BIT(3)
 224
 225 /* Mailbox 5 ACKs */
 226 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
 227 #define PRCM_ACK_MB5_I2C_VAL    (PRCM_ACK_MB5 + 0x3)
 228 #define I2C_WR_OK 0x1
 229 #define I2C_RD_OK 0x2
 230
 231 #define NUM_MB 8
 232 #define MBOX_BIT BIT
 233 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
 234
 235 /*
 236  * Wakeups/IRQs
 237  */
 238
 239 #define WAKEUP_BIT_RTC BIT(0)
 240 #define WAKEUP_BIT_RTT0 BIT(1)
 241 #define WAKEUP_BIT_RTT1 BIT(2)
 242 #define WAKEUP_BIT_HSI0 BIT(3)
 243 #define WAKEUP_BIT_HSI1 BIT(4)
 244 #define WAKEUP_BIT_CA_WAKE BIT(5)
 245 #define WAKEUP_BIT_USB BIT(6)
 246 #define WAKEUP_BIT_ABB BIT(7)
 247 #define WAKEUP_BIT_ABB_FIFO BIT(8)
 248 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
 249 #define WAKEUP_BIT_CA_SLEEP BIT(10)
 250 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
 251 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
 252 #define WAKEUP_BIT_ANC_OK BIT(13)
 253 #define WAKEUP_BIT_SW_ERROR BIT(14)
 254 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
 255 #define WAKEUP_BIT_ARM BIT(17)
 256 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
 257 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
 258 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
 259 #define WAKEUP_BIT_GPIO0 BIT(23)
 260 #define WAKEUP_BIT_GPIO1 BIT(24)
 261 #define WAKEUP_BIT_GPIO2 BIT(25)
 262 #define WAKEUP_BIT_GPIO3 BIT(26)
 263 #define WAKEUP_BIT_GPIO4 BIT(27)
 264 #define WAKEUP_BIT_GPIO5 BIT(28)
 265 #define WAKEUP_BIT_GPIO6 BIT(29)
 266 #define WAKEUP_BIT_GPIO7 BIT(30)
 267 #define WAKEUP_BIT_GPIO8 BIT(31)
 268
 269 /*
 270  * This vector maps irq numbers to the bits in the bit field used in
 271  * communication with the PRCMU firmware.
 272  *
 273  * The reason for having this is to keep the irq numbers contiguous even though
 274  * the bits in the bit field are not. (The bits also have a tendency to move
 275  * around, to further complicate matters.)
 276  */
 277 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
 278 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
 279 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
 280         IRQ_ENTRY(RTC),
 281         IRQ_ENTRY(RTT0),
 282         IRQ_ENTRY(RTT1),
 283         IRQ_ENTRY(HSI0),
 284         IRQ_ENTRY(HSI1),
 285         IRQ_ENTRY(CA_WAKE),
 286         IRQ_ENTRY(USB),
 287         IRQ_ENTRY(ABB),
 288         IRQ_ENTRY(ABB_FIFO),
 289         IRQ_ENTRY(CA_SLEEP),
 290         IRQ_ENTRY(ARM),
 291         IRQ_ENTRY(HOTMON_LOW),
 292         IRQ_ENTRY(HOTMON_HIGH),
 293         IRQ_ENTRY(MODEM_SW_RESET_REQ),
 294         IRQ_ENTRY(GPIO0),
 295         IRQ_ENTRY(GPIO1),
 296         IRQ_ENTRY(GPIO2),
 297         IRQ_ENTRY(GPIO3),
 298         IRQ_ENTRY(GPIO4),
 299         IRQ_ENTRY(GPIO5),
 300         IRQ_ENTRY(GPIO6),
 301         IRQ_ENTRY(GPIO7),
 302         IRQ_ENTRY(GPIO8)
 303 };
 304
 305 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
 306 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
 307 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
 308         WAKEUP_ENTRY(RTC),
 309         WAKEUP_ENTRY(RTT0),
 310         WAKEUP_ENTRY(RTT1),
 311         WAKEUP_ENTRY(HSI0),
 312         WAKEUP_ENTRY(HSI1),
 313         WAKEUP_ENTRY(USB),
 314         WAKEUP_ENTRY(ABB),
 315         WAKEUP_ENTRY(ABB_FIFO),
 316         WAKEUP_ENTRY(ARM)
 317 };
 318
 319 /*
 320  * mb0_transfer - state needed for mailbox 0 communication.
 321  * @lock:               The transaction lock.
 322  * @dbb_events_lock:    A lock used to handle concurrent access to (parts of)
 323  *                      the request data.
 324  * @mask_work:          Work structure used for (un)masking wakeup interrupts.
 325  * @req:                Request data that need to persist between requests.
 326  */
 327 static struct {
 328         spinlock_t lock;
 329         spinlock_t dbb_irqs_lock;
 330         struct work_struct mask_work;
 331         struct mutex ac_wake_lock;
 332         struct completion ac_wake_work;
 333         struct {
 334                 u32 dbb_irqs;
 335                 u32 dbb_wakeups;
 336                 u32 abb_events;
 337         } req;
 338 } mb0_transfer;
 339
 340 /*
 341  * mb1_transfer - state needed for mailbox 1 communication.
 342  * @lock:       The transaction lock.
 343  * @work:       The transaction completion structure.
 344  * @ack:        Reply ("acknowledge") data.
 345  */
 346 static struct {
 347         struct mutex lock;
 348         struct completion work;
 349         struct {
 350                 u8 header;
 351                 u8 arm_opp;
 352                 u8 ape_opp;
 353                 u8 ape_voltage_status;
 354         } ack;
 355 } mb1_transfer;
 356
 357 /*
 358  * mb2_transfer - state needed for mailbox 2 communication.
 359  * @lock:            The transaction lock.
 360  * @work:            The transaction completion structure.
 361  * @auto_pm_lock:    The autonomous power management configuration lock.
 362  * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
 363  * @req:             Request data that need to persist between requests.
 364  * @ack:             Reply ("acknowledge") data.
 365  */
 366 static struct {
 367         struct mutex lock;
 368         struct completion work;
 369         spinlock_t auto_pm_lock;
 370         bool auto_pm_enabled;
 371         struct {
 372                 u8 status;
 373         } ack;
 374 } mb2_transfer;
 375
 376 /*
 377  * mb3_transfer - state needed for mailbox 3 communication.
 378  * @lock:               The request lock.
 379  * @sysclk_lock:        A lock used to handle concurrent sysclk requests.
 380  * @sysclk_work:        Work structure used for sysclk requests.
 381  */
 382 static struct {
 383         spinlock_t lock;
 384         struct mutex sysclk_lock;
 385         struct completion sysclk_work;
 386 } mb3_transfer;
 387
 388 /*
 389  * mb4_transfer - state needed for mailbox 4 communication.
 390  * @lock:       The transaction lock.
 391  * @work:       The transaction completion structure.
 392  */
 393 static struct {
 394         struct mutex lock;
 395         struct completion work;
 396 } mb4_transfer;
 397
 398 /*
 399  * mb5_transfer - state needed for mailbox 5 communication.
 400  * @lock:       The transaction lock.
 401  * @work:       The transaction completion structure.
 402  * @ack:        Reply ("acknowledge") data.
 403  */
 404 static struct {
 405         struct mutex lock;
 406         struct completion work;
 407         struct {
 408                 u8 status;
 409                 u8 value;
 410         } ack;
 411 } mb5_transfer;
 412
 413 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
 414
 415 /* Spinlocks */
 416 static DEFINE_SPINLOCK(clkout_lock);
 417 static DEFINE_SPINLOCK(gpiocr_lock);
 418
 419 /* Global var to runtime determine TCDM base for v2 or v1 */
 420 static __iomem void *tcdm_base;
 421
 422 struct clk_mgt {
 423         unsigned int offset;
 424         u32 pllsw;
 425 };
 426
 427 static DEFINE_SPINLOCK(clk_mgt_lock);
 428
 429 #define CLK_MGT_ENTRY(_name)[PRCMU_##_name] = { (PRCM_##_name##_MGT_OFF), 0 }
 430 struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
 431         CLK_MGT_ENTRY(SGACLK),
 432         CLK_MGT_ENTRY(UARTCLK),
 433         CLK_MGT_ENTRY(MSP02CLK),
 434         CLK_MGT_ENTRY(MSP1CLK),
 435         CLK_MGT_ENTRY(I2CCLK),
 436         CLK_MGT_ENTRY(SDMMCCLK),
 437         CLK_MGT_ENTRY(SLIMCLK),
 438         CLK_MGT_ENTRY(PER1CLK),
 439         CLK_MGT_ENTRY(PER2CLK),
 440         CLK_MGT_ENTRY(PER3CLK),
 441         CLK_MGT_ENTRY(PER5CLK),
 442         CLK_MGT_ENTRY(PER6CLK),
 443         CLK_MGT_ENTRY(PER7CLK),
 444         CLK_MGT_ENTRY(LCDCLK),
 445         CLK_MGT_ENTRY(BMLCLK),
 446         CLK_MGT_ENTRY(HSITXCLK),
 447         CLK_MGT_ENTRY(HSIRXCLK),
 448         CLK_MGT_ENTRY(HDMICLK),
 449         CLK_MGT_ENTRY(APEATCLK),
 450         CLK_MGT_ENTRY(APETRACECLK),
 451         CLK_MGT_ENTRY(MCDECLK),
 452         CLK_MGT_ENTRY(IPI2CCLK),
 453         CLK_MGT_ENTRY(DSIALTCLK),
 454         CLK_MGT_ENTRY(DMACLK),
 455         CLK_MGT_ENTRY(B2R2CLK),
 456         CLK_MGT_ENTRY(TVCLK),
 457         CLK_MGT_ENTRY(SSPCLK),
 458         CLK_MGT_ENTRY(RNGCLK),
 459         CLK_MGT_ENTRY(UICCCLK),
 460 };
 461
 462 static struct regulator *hwacc_regulator[NUM_HW_ACC];
 463 static struct regulator *hwacc_ret_regulator[NUM_HW_ACC];
 464
 465 static bool hwacc_enabled[NUM_HW_ACC];
 466 static bool hwacc_ret_enabled[NUM_HW_ACC];
 467
 468 static const char *hwacc_regulator_name[NUM_HW_ACC] = {
 469         [HW_ACC_SVAMMDSP]       = "hwacc-sva-mmdsp",
 470         [HW_ACC_SVAPIPE]        = "hwacc-sva-pipe",
 471         [HW_ACC_SIAMMDSP]       = "hwacc-sia-mmdsp",
 472         [HW_ACC_SIAPIPE]        = "hwacc-sia-pipe",
 473         [HW_ACC_SGA]            = "hwacc-sga",
 474         [HW_ACC_B2R2]           = "hwacc-b2r2",
 475         [HW_ACC_MCDE]           = "hwacc-mcde",
 476         [HW_ACC_ESRAM1]         = "hwacc-esram1",
 477         [HW_ACC_ESRAM2]         = "hwacc-esram2",
 478         [HW_ACC_ESRAM3]         = "hwacc-esram3",
 479         [HW_ACC_ESRAM4]         = "hwacc-esram4",
 480 };
 481
 482 static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = {
 483         [HW_ACC_SVAMMDSP]       = "hwacc-sva-mmdsp-ret",
 484         [HW_ACC_SIAMMDSP]       = "hwacc-sia-mmdsp-ret",
 485         [HW_ACC_ESRAM1]         = "hwacc-esram1-ret",
 486         [HW_ACC_ESRAM2]         = "hwacc-esram2-ret",
 487         [HW_ACC_ESRAM3]         = "hwacc-esram3-ret",
 488         [HW_ACC_ESRAM4]         = "hwacc-esram4-ret",
 489 };
 490
 491 /*
 492 * Used by MCDE to setup all necessary PRCMU registers
 493 */
 494 #define PRCMU_RESET_DSIPLL              0x00004000
 495 #define PRCMU_UNCLAMP_DSIPLL            0x00400800
 496
 497 #define PRCMU_CLK_PLL_DIV_SHIFT         0
 498 #define PRCMU_CLK_PLL_SW_SHIFT          5
 499 #define PRCMU_CLK_38                    (1 << 9)
 500 #define PRCMU_CLK_38_SRC                (1 << 10)
 501 #define PRCMU_CLK_38_DIV                (1 << 11)
 502
 503 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
 504 #define PRCMU_DSI_CLOCK_SETTING         0x0000008C
 505
 506 /* PLLDIV=8, PLLSW=4 (PLLDDR) */
 507 #define PRCMU_DSI_CLOCK_SETTING_U8400   0x00000088
 508
 509 /* DPI 50000000 Hz */
 510 #define PRCMU_DPI_CLOCK_SETTING         ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
 511                                           (16 << PRCMU_CLK_PLL_DIV_SHIFT))
 512 #define PRCMU_DSI_LP_CLOCK_SETTING      0x00000E00
 513
 514 /* D=101, N=1, R=4, SELDIV2=0 */
 515 #define PRCMU_PLLDSI_FREQ_SETTING       0x00040165
 516
 517 /* D=70, N=1, R=3, SELDIV2=0 */
 518 #define PRCMU_PLLDSI_FREQ_SETTING_U8400 0x00030146
 519
 520 #define PRCMU_ENABLE_PLLDSI             0x00000001
 521 #define PRCMU_DISABLE_PLLDSI            0x00000000
 522 #define PRCMU_RELEASE_RESET_DSS         0x0000400C
 523 #define PRCMU_DSI_PLLOUT_SEL_SETTING    0x00000202
 524 /* ESC clk, div0=1, div1=1, div2=3 */
 525 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV   0x07030101
 526 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV  0x00030101
 527 #define PRCMU_DSI_RESET_SW              0x00000007
 528
 529 #define PRCMU_PLLDSI_LOCKP_LOCKED       0x3
 530
 531 static struct {
 532         u8 project_number;
 533         u8 api_version;
 534         u8 func_version;
 535         u8 errata;
 536 } prcmu_version;
 537
 538
 539 int db8500_prcmu_enable_dsipll(void)
 540 {
 541         int i;
 542         unsigned int plldsifreq;
 543
 544         /* Clear DSIPLL_RESETN */
 545         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
 546         /* Unclamp DSIPLL in/out */
 547         writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
 548
 549         if (prcmu_is_u8400())
 550                 plldsifreq = PRCMU_PLLDSI_FREQ_SETTING_U8400;
 551         else
 552                 plldsifreq = PRCMU_PLLDSI_FREQ_SETTING;
 553         /* Set DSI PLL FREQ */
 554         writel(plldsifreq, PRCM_PLLDSI_FREQ);
 555         writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
 556         /* Enable Escape clocks */
 557         writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 558
 559         /* Start DSI PLL */
 560         writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 561         /* Reset DSI PLL */
 562         writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
 563         for (i = 0; i < 10; i++) {
 564                 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
 565                                         == PRCMU_PLLDSI_LOCKP_LOCKED)
 566                         break;
 567                 udelay(100);
 568         }
 569         /* Set DSIPLL_RESETN */
 570         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
 571         return 0;
 572 }
 573
 574 int db8500_prcmu_disable_dsipll(void)
 575 {
 576         /* Disable dsi pll */
 577         writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 578         /* Disable  escapeclock */
 579         writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 580         return 0;
 581 }
 582
 583 int db8500_prcmu_set_display_clocks(void)
 584 {
 585         unsigned long flags;
 586         unsigned int dsiclk;
 587
 588         if (prcmu_is_u8400())
 589                 dsiclk = PRCMU_DSI_CLOCK_SETTING_U8400;
 590         else
 591                 dsiclk = PRCMU_DSI_CLOCK_SETTING;
 592
 593         spin_lock_irqsave(&clk_mgt_lock, flags);
 594
 595         /* Grab the HW semaphore. */
 596         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 597                 cpu_relax();
 598
 599         writel(dsiclk, PRCM_HDMICLK_MGT);
 600         writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
 601         writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
 602
 603         /* Release the HW semaphore. */
 604         writel(0, PRCM_SEM);
 605
 606         spin_unlock_irqrestore(&clk_mgt_lock, flags);
 607
 608         return 0;
 609 }
 610
 611 /**
 612  * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
 613  */
 614 void prcmu_enable_spi2(void)
 615 {
 616         u32 reg;
 617         unsigned long flags;
 618
 619         spin_lock_irqsave(&gpiocr_lock, flags);
 620         reg = readl(PRCM_GPIOCR);
 621         writel(reg | PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR);
 622         spin_unlock_irqrestore(&gpiocr_lock, flags);
 623 }
 624
 625 /**
 626  * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
 627  */
 628 void prcmu_disable_spi2(void)
 629 {
 630         u32 reg;
 631         unsigned long flags;
 632
 633         spin_lock_irqsave(&gpiocr_lock, flags);
 634         reg = readl(PRCM_GPIOCR);
 635         writel(reg & ~PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR);
 636         spin_unlock_irqrestore(&gpiocr_lock, flags);
 637 }
 638
 639 bool prcmu_has_arm_maxopp(void)
 640 {
 641         return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
 642                 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
 643 }
 644
 645 bool prcmu_is_u8400(void)
 646 {
 647         return prcmu_version.project_number == PRCMU_PROJECT_ID_8400V2_0;
 648 }
 649
 650 /**
 651  * prcmu_get_boot_status - PRCMU boot status checking
 652  * Returns: the current PRCMU boot status
 653  */
 654 int prcmu_get_boot_status(void)
 655 {
 656         return readb(tcdm_base + PRCM_BOOT_STATUS);
 657 }
 658
 659 /**
 660  * prcmu_set_rc_a2p - This function is used to run few power state sequences
 661  * @val: Value to be set, i.e. transition requested
 662  * Returns: 0 on success, -EINVAL on invalid argument
 663  *
 664  * This function is used to run the following power state sequences -
 665  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 666  */
 667 int prcmu_set_rc_a2p(enum romcode_write val)
 668 {
 669         if (val < RDY_2_DS || val > RDY_2_XP70_RST)
 670                 return -EINVAL;
 671         writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
 672         return 0;
 673 }
 674
 675 /**
 676  * prcmu_get_rc_p2a - This function is used to get power state sequences
 677  * Returns: the power transition that has last happened
 678  *
 679  * This function can return the following transitions-
 680  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 681  */
 682 enum romcode_read prcmu_get_rc_p2a(void)
 683 {
 684         return readb(tcdm_base + PRCM_ROMCODE_P2A);
 685 }
 686
 687 /**
 688  * prcmu_get_current_mode - Return the current XP70 power mode
 689  * Returns: Returns the current AP(ARM) power mode: init,
 690  * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
 691  */
 692 enum ap_pwrst prcmu_get_xp70_current_state(void)
 693 {
 694         return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
 695 }
 696
 697 /**
 698  * prcmu_config_clkout - Configure one of the programmable clock outputs.
 699  * @clkout:     The CLKOUT number (0 or 1).
 700  * @source:     The clock to be used (one of the PRCMU_CLKSRC_*).
 701  * @div:        The divider to be applied.
 702  *
 703  * Configures one of the programmable clock outputs (CLKOUTs).
 704  * @div should be in the range [1,63] to request a configuration, or 0 to
 705  * inform that the configuration is no longer requested.
 706  */
 707 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 708 {
 709         static int requests[2];
 710         int r = 0;
 711         unsigned long flags;
 712         u32 val;
 713         u32 bits;
 714         u32 mask;
 715         u32 div_mask;
 716
 717         BUG_ON(clkout > 1);
 718         BUG_ON(div > 63);
 719         BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
 720
 721         if (!div && !requests[clkout])
 722                 return -EINVAL;
 723
 724         switch (clkout) {
 725         case 0:
 726                 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
 727                 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
 728                 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
 729                         (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
 730                 break;
 731         case 1:
 732                 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
 733                 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
 734                         PRCM_CLKOCR_CLK1TYPE);
 735                 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
 736                         (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
 737                 break;
 738         }
 739         bits &= mask;
 740
 741         spin_lock_irqsave(&clkout_lock, flags);
 742
 743         val = readl(PRCM_CLKOCR);
 744         if (val & div_mask) {
 745                 if (div) {
 746                         if ((val & mask) != bits) {
 747                                 r = -EBUSY;
 748                                 goto unlock_and_return;
 749                         }
 750                 } else {
 751                         if ((val & mask & ~div_mask) != bits) {
 752                                 r = -EINVAL;
 753                                 goto unlock_and_return;
 754                         }
 755                 }
 756         }
 757         writel((bits | (val & ~mask)), PRCM_CLKOCR);
 758         requests[clkout] += (div ? 1 : -1);
 759
 760 unlock_and_return:
 761         spin_unlock_irqrestore(&clkout_lock, flags);
 762
 763         return r;
 764 }
 765
 766 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
 767 {
 768         unsigned long flags;
 769
 770         BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
 771
 772         spin_lock_irqsave(&mb0_transfer.lock, flags);
 773
 774         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 775                 cpu_relax();
 776
 777         writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 778         writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
 779         writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
 780         writeb((keep_ulp_clk ? 1 : 0),
 781                 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
 782         writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
 783         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 784
 785         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 786
 787         return 0;
 788 }
 789
 790 /* This function should only be called while mb0_transfer.lock is held. */
 791 static void config_wakeups(void)
 792 {
 793         const u8 header[2] = {
 794                 MB0H_CONFIG_WAKEUPS_EXE,
 795                 MB0H_CONFIG_WAKEUPS_SLEEP
 796         };
 797         static u32 last_dbb_events;
 798         static u32 last_abb_events;
 799         u32 dbb_events;
 800         u32 abb_events;
 801         unsigned int i;
 802
 803         dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
 804         dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
 805
 806         abb_events = mb0_transfer.req.abb_events;
 807
 808         if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
 809                 return;
 810
 811         for (i = 0; i < 2; i++) {
 812                 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 813                         cpu_relax();
 814                 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
 815                 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
 816                 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 817                 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 818         }
 819         last_dbb_events = dbb_events;
 820         last_abb_events = abb_events;
 821 }
 822
 823 void db8500_prcmu_enable_wakeups(u32 wakeups)
 824 {
 825         unsigned long flags;
 826         u32 bits;
 827         int i;
 828
 829         BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
 830
 831         for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
 832                 if (wakeups & BIT(i))
 833                         bits |= prcmu_wakeup_bit[i];
 834         }
 835
 836         spin_lock_irqsave(&mb0_transfer.lock, flags);
 837
 838         mb0_transfer.req.dbb_wakeups = bits;
 839         config_wakeups();
 840
 841         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 842 }
 843
 844 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
 845 {
 846         unsigned long flags;
 847
 848         spin_lock_irqsave(&mb0_transfer.lock, flags);
 849
 850         mb0_transfer.req.abb_events = abb_events;
 851         config_wakeups();
 852
 853         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 854 }
 855
 856 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
 857 {
 858         if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
 859                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
 860         else
 861                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
 862 }
 863
 864 /**
 865  * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
 866  * @opp: The new ARM operating point to which transition is to be made
 867  * Returns: 0 on success, non-zero on failure
 868  *
 869  * This function sets the the operating point of the ARM.
 870  */
 871 int db8500_prcmu_set_arm_opp(u8 opp)
 872 {
 873         int r;
 874
 875         if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
 876                 return -EINVAL;
 877
 878         r = 0;
 879
 880         mutex_lock(&mb1_transfer.lock);
 881
 882         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
 883                 cpu_relax();
 884
 885         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
 886         writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
 887         writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
 888
 889         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
 890         wait_for_completion(&mb1_transfer.work);
 891
 892         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
 893                 (mb1_transfer.ack.arm_opp != opp))
 894                 r = -EIO;
 895
 896         mutex_unlock(&mb1_transfer.lock);
 897
 898         return r;
 899 }
 900
 901 /**
 902  * db8500_prcmu_get_arm_opp - get the current ARM OPP
 903  *
 904  * Returns: the current ARM OPP
 905  */
 906 int db8500_prcmu_get_arm_opp(void)
 907 {
 908         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
 909 }
 910
 911 /**
 912  * prcmu_get_ddr_opp - get the current DDR OPP
 913  *
 914  * Returns: the current DDR OPP
 915  */
 916 int prcmu_get_ddr_opp(void)
 917 {
 918         return readb(PRCM_DDR_SUBSYS_APE_MINBW);
 919 }
 920
 921 /**
 922  * set_ddr_opp - set the appropriate DDR OPP
 923  * @opp: The new DDR operating point to which transition is to be made
 924  * Returns: 0 on success, non-zero on failure
 925  *
 926  * This function sets the operating point of the DDR.
 927  */
 928 int prcmu_set_ddr_opp(u8 opp)
 929 {
 930         if (opp < DDR_100_OPP || opp > DDR_25_OPP)
 931                 return -EINVAL;
 932         /* Changing the DDR OPP can hang the hardware pre-v21 */
 933         if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
 934                 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
 935
 936         return 0;
 937 }
 938 /**
 939  * set_ape_opp - set the appropriate APE OPP
 940  * @opp: The new APE operating point to which transition is to be made
 941  * Returns: 0 on success, non-zero on failure
 942  *
 943  * This function sets the operating point of the APE.
 944  */
 945 int prcmu_set_ape_opp(u8 opp)
 946 {
 947         int r = 0;
 948
 949         mutex_lock(&mb1_transfer.lock);
 950
 951         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
 952                 cpu_relax();
 953
 954         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
 955         writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
 956         writeb(opp, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
 957
 958         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
 959         wait_for_completion(&mb1_transfer.work);
 960
 961         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
 962                 (mb1_transfer.ack.ape_opp != opp))
 963                 r = -EIO;
 964
 965         mutex_unlock(&mb1_transfer.lock);
 966
 967         return r;
 968 }
 969
 970 /**
 971  * prcmu_get_ape_opp - get the current APE OPP
 972  *
 973  * Returns: the current APE OPP
 974  */
 975 int prcmu_get_ape_opp(void)
 976 {
 977         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
 978 }
 979
 980 /**
 981  * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
 982  * @enable: true to request the higher voltage, false to drop a request.
 983  *
 984  * Calls to this function to enable and disable requests must be balanced.
 985  */
 986 int prcmu_request_ape_opp_100_voltage(bool enable)
 987 {
 988         int r = 0;
 989         u8 header;
 990         static unsigned int requests;
 991
 992         mutex_lock(&mb1_transfer.lock);
 993
 994         if (enable) {
 995                 if (0 != requests++)
 996                         goto unlock_and_return;
 997                 header = MB1H_REQUEST_APE_OPP_100_VOLT;
 998         } else {
 999                 if (requests == 0) {
1000                         r = -EIO;
1001                         goto unlock_and_return;
1002                 } else if (1 != requests--) {
1003                         goto unlock_and_return;
1004                 }
1005                 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1006         }
1007
1008         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1009                 cpu_relax();
1010
1011         writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1012
1013         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1014         wait_for_completion(&mb1_transfer.work);
1015
1016         if ((mb1_transfer.ack.header != header) ||
1017                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1018                 r = -EIO;
1019
1020 unlock_and_return:
1021         mutex_unlock(&mb1_transfer.lock);
1022
1023         return r;
1024 }
1025
1026 /**
1027  * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1028  *
1029  * This function releases the power state requirements of a USB wakeup.
1030  */
1031 int prcmu_release_usb_wakeup_state(void)
1032 {
1033         int r = 0;
1034
1035         mutex_lock(&mb1_transfer.lock);
1036
1037         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1038                 cpu_relax();
1039
1040         writeb(MB1H_RELEASE_USB_WAKEUP,
1041                 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1042
1043         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1044         wait_for_completion(&mb1_transfer.work);
1045
1046         if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1047                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1048                 r = -EIO;
1049
1050         mutex_unlock(&mb1_transfer.lock);
1051
1052         return r;
1053 }
1054
1055 static int request_pll(u8 clock, bool enable)
1056 {
1057         int r = 0;
1058
1059         if (clock == PRCMU_PLLSOC1)
1060                 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1061         else
1062                 return -EINVAL;
1063
1064         mutex_lock(&mb1_transfer.lock);
1065
1066         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1067                 cpu_relax();
1068
1069         writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1070         writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1071
1072         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1073         wait_for_completion(&mb1_transfer.work);
1074
1075         if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1076                 r = -EIO;
1077
1078         mutex_unlock(&mb1_transfer.lock);
1079
1080         return r;
1081 }
1082
1083 /**
1084  * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1085  * @epod_id: The EPOD to set
1086  * @epod_state: The new EPOD state
1087  *
1088  * This function sets the state of a EPOD (power domain). It may not be called
1089  * from interrupt context.
1090  */
1091 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1092 {
1093         int r = 0;
1094         bool ram_retention = false;
1095         int i;
1096
1097         /* check argument */
1098         BUG_ON(epod_id >= NUM_EPOD_ID);
1099
1100         /* set flag if retention is possible */
1101         switch (epod_id) {
1102         case EPOD_ID_SVAMMDSP:
1103         case EPOD_ID_SIAMMDSP:
1104         case EPOD_ID_ESRAM12:
1105         case EPOD_ID_ESRAM34:
1106                 ram_retention = true;
1107                 break;
1108         }
1109
1110         /* check argument */
1111         BUG_ON(epod_state > EPOD_STATE_ON);
1112         BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1113
1114         /* get lock */
1115         mutex_lock(&mb2_transfer.lock);
1116
1117         /* wait for mailbox */
1118         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1119                 cpu_relax();
1120
1121         /* fill in mailbox */
1122         for (i = 0; i < NUM_EPOD_ID; i++)
1123                 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1124         writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1125
1126         writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1127
1128         writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1129
1130         /*
1131          * The current firmware version does not handle errors correctly,
1132          * and we cannot recover if there is an error.
1133          * This is expected to change when the firmware is updated.
1134          */
1135         if (!wait_for_completion_timeout(&mb2_transfer.work,
1136                         msecs_to_jiffies(20000))) {
1137                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1138                         __func__);
1139                 r = -EIO;
1140                 goto unlock_and_return;
1141         }
1142
1143         if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1144                 r = -EIO;
1145
1146 unlock_and_return:
1147         mutex_unlock(&mb2_transfer.lock);
1148         return r;
1149 }
1150
1151 /**
1152  * prcmu_configure_auto_pm - Configure autonomous power management.
1153  * @sleep: Configuration for ApSleep.
1154  * @idle:  Configuration for ApIdle.
1155  */
1156 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1157         struct prcmu_auto_pm_config *idle)
1158 {
1159         u32 sleep_cfg;
1160         u32 idle_cfg;
1161         unsigned long flags;
1162
1163         BUG_ON((sleep == NULL) || (idle == NULL));
1164
1165         sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1166         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1167         sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1168         sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1169         sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1170         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1171
1172         idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1173         idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1174         idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1175         idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1176         idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1177         idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1178
1179         spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1180
1181         /*
1182          * The autonomous power management configuration is done through
1183          * fields in mailbox 2, but these fields are only used as shared
1184          * variables - i.e. there is no need to send a message.
1185          */
1186         writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1187         writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1188
1189         mb2_transfer.auto_pm_enabled =
1190                 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1191                  (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1192                  (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1193                  (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1194
1195         spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1196 }
1197 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1198
1199 bool prcmu_is_auto_pm_enabled(void)
1200 {
1201         return mb2_transfer.auto_pm_enabled;
1202 }
1203
1204 static int request_sysclk(bool enable)
1205 {
1206         int r;
1207         unsigned long flags;
1208
1209         r = 0;
1210
1211         mutex_lock(&mb3_transfer.sysclk_lock);
1212
1213         spin_lock_irqsave(&mb3_transfer.lock, flags);
1214
1215         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1216                 cpu_relax();
1217
1218         writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1219
1220         writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1221         writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1222
1223         spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1224
1225         /*
1226          * The firmware only sends an ACK if we want to enable the
1227          * SysClk, and it succeeds.
1228          */
1229         if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1230                         msecs_to_jiffies(20000))) {
1231                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1232                         __func__);
1233                 r = -EIO;
1234         }
1235
1236         mutex_unlock(&mb3_transfer.sysclk_lock);
1237
1238         return r;
1239 }
1240
1241 static int request_timclk(bool enable)
1242 {
1243         u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1244
1245         if (!enable)
1246                 val |= PRCM_TCR_STOP_TIMERS;
1247         writel(val, PRCM_TCR);
1248
1249         return 0;
1250 }
1251
1252 static int request_reg_clock(u8 clock, bool enable)
1253 {
1254         u32 val;
1255         unsigned long flags;
1256
1257         spin_lock_irqsave(&clk_mgt_lock, flags);
1258
1259         /* Grab the HW semaphore. */
1260         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1261                 cpu_relax();
1262
1263         val = readl(_PRCMU_BASE + clk_mgt[clock].offset);
1264         if (enable) {
1265                 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1266         } else {
1267                 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1268                 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1269         }
1270         writel(val, (_PRCMU_BASE + clk_mgt[clock].offset));
1271
1272         /* Release the HW semaphore. */
1273         writel(0, PRCM_SEM);
1274
1275         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1276
1277         return 0;
1278 }
1279
1280 static int request_sga_clock(u8 clock, bool enable)
1281 {
1282         u32 val;
1283         int ret;
1284
1285         if (enable) {
1286                 val = readl(PRCM_CGATING_BYPASS);
1287                 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1288         }
1289
1290         ret = request_reg_clock(clock, enable);
1291
1292         if (!ret && !enable) {
1293                 val = readl(PRCM_CGATING_BYPASS);
1294                 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1295         }
1296
1297         return ret;
1298 }
1299
1300 /**
1301  * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1302  * @clock:      The clock for which the request is made.
1303  * @enable:     Whether the clock should be enabled (true) or disabled (false).
1304  *
1305  * This function should only be used by the clock implementation.
1306  * Do not use it from any other place!
1307  */
1308 int db8500_prcmu_request_clock(u8 clock, bool enable)
1309 {
1310         if (clock == PRCMU_SGACLK)
1311                 return request_sga_clock(clock, enable);
1312         else if (clock < PRCMU_NUM_REG_CLOCKS)
1313                 return request_reg_clock(clock, enable);
1314         else if (clock == PRCMU_TIMCLK)
1315                 return request_timclk(enable);
1316         else if (clock == PRCMU_SYSCLK)
1317                 return request_sysclk(enable);
1318         else if (clock == PRCMU_PLLSOC1)
1319                 return request_pll(clock, enable);
1320         else
1321                 return -EINVAL;
1322 }
1323
1324 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1325 {
1326         if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1327             (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
1328                 return -EINVAL;
1329
1330         mutex_lock(&mb4_transfer.lock);
1331
1332         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1333                 cpu_relax();
1334
1335         writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1336         writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
1337                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
1338         writeb(DDR_PWR_STATE_ON,
1339                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
1340         writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
1341
1342         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1343         wait_for_completion(&mb4_transfer.work);
1344
1345         mutex_unlock(&mb4_transfer.lock);
1346
1347         return 0;
1348 }
1349
1350 int prcmu_config_hotdog(u8 threshold)
1351 {
1352         mutex_lock(&mb4_transfer.lock);
1353
1354         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1355                 cpu_relax();
1356
1357         writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
1358         writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1359
1360         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1361         wait_for_completion(&mb4_transfer.work);
1362
1363         mutex_unlock(&mb4_transfer.lock);
1364
1365         return 0;
1366 }
1367
1368 int prcmu_config_hotmon(u8 low, u8 high)
1369 {
1370         mutex_lock(&mb4_transfer.lock);
1371
1372         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1373                 cpu_relax();
1374
1375         writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
1376         writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
1377         writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
1378                 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
1379         writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1380
1381         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1382         wait_for_completion(&mb4_transfer.work);
1383
1384         mutex_unlock(&mb4_transfer.lock);
1385
1386         return 0;
1387 }
1388
1389 static int config_hot_period(u16 val)
1390 {
1391         mutex_lock(&mb4_transfer.lock);
1392
1393         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
1394                 cpu_relax();
1395
1396         writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
1397         writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
1398
1399         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
1400         wait_for_completion(&mb4_transfer.work);
1401
1402         mutex_unlock(&mb4_transfer.lock);
1403
1404         return 0;
1405 }
1406
1407 int prcmu_start_temp_sense(u16 cycles32k)
1408 {
1409         if (cycles32k == 0xFFFF)
1410                 return -EINVAL;
1411
1412         return config_hot_period(cycles32k);
1413 }
1414
1415 int prcmu_stop_temp_sense(void)
1416 {
1417         return config_hot_period(0xFFFF);
1418 }
1419
1420 /**
1421  * prcmu_set_clock_divider() - Configure the clock divider.
1422  * @clock:      The clock for which the request is made.
1423  * @divider:    The clock divider. (< 32)
1424  *
1425  * This function should only be used by the clock implementation.
1426  * Do not use it from any other place!
1427  */
1428 int prcmu_set_clock_divider(u8 clock, u8 divider)
1429 {
1430         u32 val;
1431         unsigned long flags;
1432
1433         if ((clock >= PRCMU_NUM_REG_CLOCKS) || (divider < 1) || (31 < divider))
1434                 return -EINVAL;
1435
1436         spin_lock_irqsave(&clk_mgt_lock, flags);
1437
1438         /* Grab the HW semaphore. */
1439         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1440                 cpu_relax();
1441
1442         val = readl(_PRCMU_BASE + clk_mgt[clock].offset);
1443         val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK);
1444         val |= (u32)divider;
1445         writel(val, (_PRCMU_BASE + clk_mgt[clock].offset));
1446
1447         /* Release the HW semaphore. */
1448         writel(0, PRCM_SEM);
1449
1450         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1451
1452         return 0;
1453 }
1454
1455 /**
1456  * prcmu_abb_read() - Read register value(s) from the ABB.
1457  * @slave:      The I2C slave address.
1458  * @reg:        The (start) register address.
1459  * @value:      The read out value(s).
1460  * @size:       The number of registers to read.
1461  *
1462  * Reads register value(s) from the ABB.
1463  * @size has to be 1 for the current firmware version.
1464  */
1465 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
1466 {
1467         int r;
1468
1469         if (size != 1)
1470                 return -EINVAL;
1471
1472         mutex_lock(&mb5_transfer.lock);
1473
1474         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
1475                 cpu_relax();
1476
1477         writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
1478         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
1479         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
1480         writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
1481
1482         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
1483
1484         if (!wait_for_completion_timeout(&mb5_transfer.work,
1485                                 msecs_to_jiffies(20000))) {
1486                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1487                         __func__);
1488                 r = -EIO;
1489         } else {
1490                 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
1491         }
1492
1493         if (!r)
1494                 *value = mb5_transfer.ack.value;
1495
1496         mutex_unlock(&mb5_transfer.lock);
1497
1498         return r;
1499 }
1500
1501 /**
1502  * prcmu_abb_write() - Write register value(s) to the ABB.
1503  * @slave:      The I2C slave address.
1504  * @reg:        The (start) register address.
1505  * @value:      The value(s) to write.
1506  * @size:       The number of registers to write.
1507  *
1508  * Reads register value(s) from the ABB.
1509  * @size has to be 1 for the current firmware version.
1510  */
1511 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
1512 {
1513         int r;
1514
1515         if (size != 1)
1516                 return -EINVAL;
1517
1518         mutex_lock(&mb5_transfer.lock);
1519
1520         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
1521                 cpu_relax();
1522
1523         writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
1524         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
1525         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
1526         writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
1527
1528         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
1529
1530         if (!wait_for_completion_timeout(&mb5_transfer.work,
1531                                 msecs_to_jiffies(20000))) {
1532                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1533                         __func__);
1534                 r = -EIO;
1535         } else {
1536                 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
1537         }
1538
1539         mutex_unlock(&mb5_transfer.lock);
1540
1541         return r;
1542 }
1543
1544 /**
1545  * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
1546  */
1547 void prcmu_ac_wake_req(void)
1548 {
1549         u32 val;
1550
1551         mutex_lock(&mb0_transfer.ac_wake_lock);
1552
1553         val = readl(PRCM_HOSTACCESS_REQ);
1554         if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
1555                 goto unlock_and_return;
1556
1557         atomic_set(&ac_wake_req_state, 1);
1558
1559         writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ);
1560
1561         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
1562                         msecs_to_jiffies(20000))) {
1563                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1564                         __func__);
1565         }
1566
1567 unlock_and_return:
1568         mutex_unlock(&mb0_transfer.ac_wake_lock);
1569 }
1570
1571 /**
1572  * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
1573  */
1574 void prcmu_ac_sleep_req()
1575 {
1576         u32 val;
1577
1578         mutex_lock(&mb0_transfer.ac_wake_lock);
1579
1580         val = readl(PRCM_HOSTACCESS_REQ);
1581         if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
1582                 goto unlock_and_return;
1583
1584         writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
1585                 PRCM_HOSTACCESS_REQ);
1586
1587         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
1588                         msecs_to_jiffies(20000))) {
1589                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1590                         __func__);
1591         }
1592
1593         atomic_set(&ac_wake_req_state, 0);
1594
1595 unlock_and_return:
1596         mutex_unlock(&mb0_transfer.ac_wake_lock);
1597 }
1598
1599 bool db8500_prcmu_is_ac_wake_requested(void)
1600 {
1601         return (atomic_read(&ac_wake_req_state) != 0);
1602 }
1603
1604 /**
1605  * db8500_prcmu_system_reset - System reset
1606  *
1607  * Saves the reset reason code and then sets the APE_SOFTRST register which
1608  * fires interrupt to fw
1609  */
1610 void db8500_prcmu_system_reset(u16 reset_code)
1611 {
1612         writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
1613         writel(1, PRCM_APE_SOFTRST);
1614 }
1615
1616 /**
1617  * prcmu_reset_modem - ask the PRCMU to reset modem
1618  */
1619 void prcmu_modem_reset(void)
1620 {
1621         mutex_lock(&mb1_transfer.lock);
1622
1623         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1624                 cpu_relax();
1625
1626         writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1627         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1628         wait_for_completion(&mb1_transfer.work);
1629
1630         /*
1631          * No need to check return from PRCMU as modem should go in reset state
1632          * This state is already managed by upper layer
1633          */
1634
1635         mutex_unlock(&mb1_transfer.lock);
1636 }
1637
1638 static void ack_dbb_wakeup(void)
1639 {
1640         unsigned long flags;
1641
1642         spin_lock_irqsave(&mb0_transfer.lock, flags);
1643
1644         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
1645                 cpu_relax();
1646
1647         writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
1648         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
1649
1650         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
1651 }
1652
1653 static inline void print_unknown_header_warning(u8 n, u8 header)
1654 {
1655         pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
1656                 header, n);
1657 }
1658
1659 static bool read_mailbox_0(void)
1660 {
1661         bool r;
1662         u32 ev;
1663         unsigned int n;
1664         u8 header;
1665
1666         header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
1667         switch (header) {
1668         case MB0H_WAKEUP_EXE:
1669         case MB0H_WAKEUP_SLEEP:
1670                 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
1671                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
1672                 else
1673                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
1674
1675                 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
1676                         complete(&mb0_transfer.ac_wake_work);
1677                 if (ev & WAKEUP_BIT_SYSCLK_OK)
1678                         complete(&mb3_transfer.sysclk_work);
1679
1680                 ev &= mb0_transfer.req.dbb_irqs;
1681
1682                 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
1683                         if (ev & prcmu_irq_bit[n])
1684                                 generic_handle_irq(IRQ_PRCMU_BASE + n);
1685                 }
1686                 r = true;
1687                 break;
1688         default:
1689                 print_unknown_header_warning(0, header);
1690                 r = false;
1691                 break;
1692         }
1693         writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
1694         return r;
1695 }
1696
1697 static bool read_mailbox_1(void)
1698 {
1699         mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
1700         mb1_transfer.ack.arm_opp = readb(tcdm_base +
1701                 PRCM_ACK_MB1_CURRENT_ARM_OPP);
1702         mb1_transfer.ack.ape_opp = readb(tcdm_base +
1703                 PRCM_ACK_MB1_CURRENT_APE_OPP);
1704         mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
1705                 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
1706         writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
1707         complete(&mb1_transfer.work);
1708         return false;
1709 }
1710
1711 static bool read_mailbox_2(void)
1712 {
1713         mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
1714         writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
1715         complete(&mb2_transfer.work);
1716         return false;
1717 }
1718
1719 static bool read_mailbox_3(void)
1720 {
1721         writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
1722         return false;
1723 }
1724
1725 static bool read_mailbox_4(void)
1726 {
1727         u8 header;
1728         bool do_complete = true;
1729
1730         header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
1731         switch (header) {
1732         case MB4H_MEM_ST:
1733         case MB4H_HOTDOG:
1734         case MB4H_HOTMON:
1735         case MB4H_HOT_PERIOD:
1736         case MB4H_A9WDOG_CONF:
1737         case MB4H_A9WDOG_EN:
1738         case MB4H_A9WDOG_DIS:
1739         case MB4H_A9WDOG_LOAD:
1740         case MB4H_A9WDOG_KICK:
1741                 break;
1742         default:
1743                 print_unknown_header_warning(4, header);
1744                 do_complete = false;
1745                 break;
1746         }
1747
1748         writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
1749
1750         if (do_complete)
1751                 complete(&mb4_transfer.work);
1752
1753         return false;
1754 }
1755
1756 static bool read_mailbox_5(void)
1757 {
1758         mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
1759         mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
1760         writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
1761         complete(&mb5_transfer.work);
1762         return false;
1763 }
1764
1765 static bool read_mailbox_6(void)
1766 {
1767         writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
1768         return false;
1769 }
1770
1771 static bool read_mailbox_7(void)
1772 {
1773         writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
1774         return false;
1775 }
1776
1777 static bool (* const read_mailbox[NUM_MB])(void) = {
1778         read_mailbox_0,
1779         read_mailbox_1,
1780         read_mailbox_2,
1781         read_mailbox_3,
1782         read_mailbox_4,
1783         read_mailbox_5,
1784         read_mailbox_6,
1785         read_mailbox_7
1786 };
1787
1788 static irqreturn_t prcmu_irq_handler(int irq, void *data)
1789 {
1790         u32 bits;
1791         u8 n;
1792         irqreturn_t r;
1793
1794         bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
1795         if (unlikely(!bits))
1796                 return IRQ_NONE;
1797
1798         r = IRQ_HANDLED;
1799         for (n = 0; bits; n++) {
1800                 if (bits & MBOX_BIT(n)) {
1801                         bits -= MBOX_BIT(n);
1802                         if (read_mailbox[n]())
1803                                 r = IRQ_WAKE_THREAD;
1804                 }
1805         }
1806         return r;
1807 }
1808
1809 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
1810 {
1811         ack_dbb_wakeup();
1812         return IRQ_HANDLED;
1813 }
1814
1815 static void prcmu_mask_work(struct work_struct *work)
1816 {
1817         unsigned long flags;
1818
1819         spin_lock_irqsave(&mb0_transfer.lock, flags);
1820
1821         config_wakeups();
1822
1823         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
1824 }
1825
1826 static void prcmu_irq_mask(struct irq_data *d)
1827 {
1828         unsigned long flags;
1829
1830         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
1831
1832         mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
1833
1834         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
1835
1836         if (d->irq != IRQ_PRCMU_CA_SLEEP)
1837                 schedule_work(&mb0_transfer.mask_work);
1838 }
1839
1840 static void prcmu_irq_unmask(struct irq_data *d)
1841 {
1842         unsigned long flags;
1843
1844         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
1845
1846         mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
1847
1848         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
1849
1850         if (d->irq != IRQ_PRCMU_CA_SLEEP)
1851                 schedule_work(&mb0_transfer.mask_work);
1852 }
1853
1854 static void noop(struct irq_data *d)
1855 {
1856 }
1857
1858 static struct irq_chip prcmu_irq_chip = {
1859         .name           = "prcmu",
1860         .irq_disable    = prcmu_irq_mask,
1861         .irq_ack        = noop,
1862         .irq_mask       = prcmu_irq_mask,
1863         .irq_unmask     = prcmu_irq_unmask,
1864 };
1865
1866 void __init db8500_prcmu_early_init(void)
1867 {
1868         unsigned int i;
1869
1870         if (cpu_is_u8500v1()) {
1871                 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1);
1872         } else if (cpu_is_u8500v2()) {
1873                 void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
1874
1875                 if (tcpm_base != NULL) {
1876                         int version;
1877                         version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET);
1878                         prcmu_version.project_number = version & 0xFF;
1879                         prcmu_version.api_version = (version >> 8) & 0xFF;
1880                         prcmu_version.func_version = (version >> 16) & 0xFF;
1881                         prcmu_version.errata = (version >> 24) & 0xFF;
1882                         pr_info("PRCMU firmware version %d.%d.%d\n",
1883                                 (version >> 8) & 0xFF, (version >> 16) & 0xFF,
1884                                 (version >> 24) & 0xFF);
1885                         iounmap(tcpm_base);
1886                 }
1887
1888                 tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
1889         } else {
1890                 pr_err("prcmu: Unsupported chip version\n");
1891                 BUG();
1892         }
1893
1894         spin_lock_init(&mb0_transfer.lock);
1895         spin_lock_init(&mb0_transfer.dbb_irqs_lock);
1896         mutex_init(&mb0_transfer.ac_wake_lock);
1897         init_completion(&mb0_transfer.ac_wake_work);
1898         mutex_init(&mb1_transfer.lock);
1899         init_completion(&mb1_transfer.work);
1900         mutex_init(&mb2_transfer.lock);
1901         init_completion(&mb2_transfer.work);
1902         spin_lock_init(&mb2_transfer.auto_pm_lock);
1903         spin_lock_init(&mb3_transfer.lock);
1904         mutex_init(&mb3_transfer.sysclk_lock);
1905         init_completion(&mb3_transfer.sysclk_work);
1906         mutex_init(&mb4_transfer.lock);
1907         init_completion(&mb4_transfer.work);
1908         mutex_init(&mb5_transfer.lock);
1909         init_completion(&mb5_transfer.work);
1910
1911         INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
1912
1913         /* Initalize irqs. */
1914         for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
1915                 unsigned int irq;
1916
1917                 irq = IRQ_PRCMU_BASE + i;
1918                 irq_set_chip_and_handler(irq, &prcmu_irq_chip,
1919                                          handle_simple_irq);
1920                 set_irq_flags(irq, IRQF_VALID);
1921         }
1922 }
1923
1924 static void __init init_prcm_registers(void)
1925 {
1926         u32 val;
1927
1928         val = readl(PRCM_A9PL_FORCE_CLKEN);
1929         val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
1930                 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
1931         writel(val, (PRCM_A9PL_FORCE_CLKEN));
1932 }
1933
1934 /*
1935  * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
1936  */
1937 static struct regulator_consumer_supply db8500_vape_consumers[] = {
1938         REGULATOR_SUPPLY("v-ape", NULL),
1939         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
1940         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
1941         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
1942         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
1943         /* "v-mmc" changed to "vcore" in the mainline kernel */
1944         REGULATOR_SUPPLY("vcore", "sdi0"),
1945         REGULATOR_SUPPLY("vcore", "sdi1"),
1946         REGULATOR_SUPPLY("vcore", "sdi2"),
1947         REGULATOR_SUPPLY("vcore", "sdi3"),
1948         REGULATOR_SUPPLY("vcore", "sdi4"),
1949         REGULATOR_SUPPLY("v-dma", "dma40.0"),
1950         REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
1951         /* "v-uart" changed to "vcore" in the mainline kernel */
1952         REGULATOR_SUPPLY("vcore", "uart0"),
1953         REGULATOR_SUPPLY("vcore", "uart1"),
1954         REGULATOR_SUPPLY("vcore", "uart2"),
1955         REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
1956 };
1957
1958 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
1959         /* CG2900 and CW1200 power to off-chip peripherals */
1960         REGULATOR_SUPPLY("gbf_1v8", "cg2900-uart.0"),
1961         REGULATOR_SUPPLY("wlan_1v8", "cw1200.0"),
1962         REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
1963         /* AV8100 regulator */
1964         REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
1965 };
1966
1967 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
1968         REGULATOR_SUPPLY("vsupply", "b2r2.0"),
1969         REGULATOR_SUPPLY("vsupply", "mcde.0"),
1970 };
1971
1972 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
1973         [DB8500_REGULATOR_VAPE] = {
1974                 .constraints = {
1975                         .name = "db8500-vape",
1976                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1977                 },
1978                 .consumer_supplies = db8500_vape_consumers,
1979                 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
1980         },
1981         [DB8500_REGULATOR_VARM] = {
1982                 .constraints = {
1983                         .name = "db8500-varm",
1984                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1985                 },
1986         },
1987         [DB8500_REGULATOR_VMODEM] = {
1988                 .constraints = {
1989                         .name = "db8500-vmodem",
1990                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1991                 },
1992         },
1993         [DB8500_REGULATOR_VPLL] = {
1994                 .constraints = {
1995                         .name = "db8500-vpll",
1996                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
1997                 },
1998         },
1999         [DB8500_REGULATOR_VSMPS1] = {
2000                 .constraints = {
2001                         .name = "db8500-vsmps1",
2002                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2003                 },
2004         },
2005         [DB8500_REGULATOR_VSMPS2] = {
2006                 .constraints = {
2007                         .name = "db8500-vsmps2",
2008                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2009                 },
2010                 .consumer_supplies = db8500_vsmps2_consumers,
2011                 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2012         },
2013         [DB8500_REGULATOR_VSMPS3] = {
2014                 .constraints = {
2015                         .name = "db8500-vsmps3",
2016                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2017                 },
2018         },
2019         [DB8500_REGULATOR_VRF1] = {
2020                 .constraints = {
2021                         .name = "db8500-vrf1",
2022                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2023                 },
2024         },
2025         [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2026                 .supply_regulator = "db8500-vape",
2027                 .constraints = {
2028                         .name = "db8500-sva-mmdsp",
2029                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2030                 },
2031         },
2032         [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2033                 .constraints = {
2034                         /* "ret" means "retention" */
2035                         .name = "db8500-sva-mmdsp-ret",
2036                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2037                 },
2038         },
2039         [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2040                 .supply_regulator = "db8500-vape",
2041                 .constraints = {
2042                         .name = "db8500-sva-pipe",
2043                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2044                 },
2045         },
2046         [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2047                 .supply_regulator = "db8500-vape",
2048                 .constraints = {
2049                         .name = "db8500-sia-mmdsp",
2050                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2051                 },
2052         },
2053         [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2054                 .constraints = {
2055                         .name = "db8500-sia-mmdsp-ret",
2056                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2057                 },
2058         },
2059         [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2060                 .supply_regulator = "db8500-vape",
2061                 .constraints = {
2062                         .name = "db8500-sia-pipe",
2063                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2064                 },
2065         },
2066         [DB8500_REGULATOR_SWITCH_SGA] = {
2067                 .supply_regulator = "db8500-vape",
2068                 .constraints = {
2069                         .name = "db8500-sga",
2070                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2071                 },
2072         },
2073         [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2074                 .supply_regulator = "db8500-vape",
2075                 .constraints = {
2076                         .name = "db8500-b2r2-mcde",
2077                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2078                 },
2079                 .consumer_supplies = db8500_b2r2_mcde_consumers,
2080                 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2081         },
2082         [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2083                 .supply_regulator = "db8500-vape",
2084                 .constraints = {
2085                         .name = "db8500-esram12",
2086                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2087                 },
2088         },
2089         [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2090                 .constraints = {
2091                         .name = "db8500-esram12-ret",
2092                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2093                 },
2094         },
2095         [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2096                 .supply_regulator = "db8500-vape",
2097                 .constraints = {
2098                         .name = "db8500-esram34",
2099                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2100                 },
2101         },
2102         [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
2103                 .constraints = {
2104                         .name = "db8500-esram34-ret",
2105                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2106                 },
2107         },
2108 };
2109
2110 static struct mfd_cell db8500_prcmu_devs[] = {
2111         {
2112                 .name = "db8500-prcmu-regulators",
2113                 .platform_data = &db8500_regulators,
2114                 .pdata_size = sizeof(db8500_regulators),
2115         },
2116         {
2117                 .name = "cpufreq-u8500",
2118         },
2119 };
2120
2121 /**
2122  * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
2123  *
2124  */
2125 static int __init db8500_prcmu_probe(struct platform_device *pdev)
2126 {
2127         int err = 0;
2128
2129         if (ux500_is_svp())
2130                 return -ENODEV;
2131
2132         init_prcm_registers();
2133
2134         /* Clean up the mailbox interrupts after pre-kernel code. */
2135         writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
2136
2137         err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler,
2138                 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
2139         if (err < 0) {
2140                 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
2141                 err = -EBUSY;
2142                 goto no_irq_return;
2143         }
2144
2145         if (cpu_is_u8500v20_or_later())
2146                 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
2147
2148         err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
2149                               ARRAY_SIZE(db8500_prcmu_devs), NULL,
2150                               0);
2151
2152         if (err)
2153                 pr_err("prcmu: Failed to add subdevices\n");
2154         else
2155                 pr_info("DB8500 PRCMU initialized\n");
2156
2157 no_irq_return:
2158         return err;
2159 }
2160
2161 static struct platform_driver db8500_prcmu_driver = {
2162         .driver = {
2163                 .name = "db8500-prcmu",
2164                 .owner = THIS_MODULE,
2165         },
2166 };
2167
2168 static int __init db8500_prcmu_init(void)
2169 {
2170         return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe);
2171 }
2172
2173 arch_initcall(db8500_prcmu_init);
2174
2175 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
2176 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
2177 MODULE_LICENSE("GPL v2");