Pileus Git - ~andy/linux/blob - drivers/mfd/asic3.c

   1 /*
   2  * driver/mfd/asic3.c
   3  *
   4  * Compaq ASIC3 support.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Copyright 2001 Compaq Computer Corporation.
  11  * Copyright 2004-2005 Phil Blundell
  12  * Copyright 2007-2008 OpenedHand Ltd.
  13  *
  14  * Authors: Phil Blundell <pb@handhelds.org>,
  15  *          Samuel Ortiz <sameo@openedhand.com>
  16  *
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/irq.h>
  22 #include <linux/gpio.h>
  23 #include <linux/export.h>
  24 #include <linux/io.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28
  29 #include <linux/mfd/asic3.h>
  30 #include <linux/mfd/core.h>
  31 #include <linux/mfd/ds1wm.h>
  32 #include <linux/mfd/tmio.h>
  33
  34 enum {
  35         ASIC3_CLOCK_SPI,
  36         ASIC3_CLOCK_OWM,
  37         ASIC3_CLOCK_PWM0,
  38         ASIC3_CLOCK_PWM1,
  39         ASIC3_CLOCK_LED0,
  40         ASIC3_CLOCK_LED1,
  41         ASIC3_CLOCK_LED2,
  42         ASIC3_CLOCK_SD_HOST,
  43         ASIC3_CLOCK_SD_BUS,
  44         ASIC3_CLOCK_SMBUS,
  45         ASIC3_CLOCK_EX0,
  46         ASIC3_CLOCK_EX1,
  47 };
  48
  49 struct asic3_clk {
  50         int enabled;
  51         unsigned int cdex;
  52         unsigned long rate;
  53 };
  54
  55 #define INIT_CDEX(_name, _rate) \
  56         [ASIC3_CLOCK_##_name] = {               \
  57                 .cdex = CLOCK_CDEX_##_name,     \
  58                 .rate = _rate,                  \
  59         }
  60
  61 static struct asic3_clk asic3_clk_init[] __initdata = {
  62         INIT_CDEX(SPI, 0),
  63         INIT_CDEX(OWM, 5000000),
  64         INIT_CDEX(PWM0, 0),
  65         INIT_CDEX(PWM1, 0),
  66         INIT_CDEX(LED0, 0),
  67         INIT_CDEX(LED1, 0),
  68         INIT_CDEX(LED2, 0),
  69         INIT_CDEX(SD_HOST, 24576000),
  70         INIT_CDEX(SD_BUS, 12288000),
  71         INIT_CDEX(SMBUS, 0),
  72         INIT_CDEX(EX0, 32768),
  73         INIT_CDEX(EX1, 24576000),
  74 };
  75
  76 struct asic3 {
  77         void __iomem *mapping;
  78         unsigned int bus_shift;
  79         unsigned int irq_nr;
  80         unsigned int irq_base;
  81         spinlock_t lock;
  82         u16 irq_bothedge[4];
  83         struct gpio_chip gpio;
  84         struct device *dev;
  85         void __iomem *tmio_cnf;
  86
  87         struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
  88 };
  89
  90 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
  91
  92 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
  93 {
  94         iowrite16(value, asic->mapping +
  95                   (reg >> asic->bus_shift));
  96 }
  97 EXPORT_SYMBOL_GPL(asic3_write_register);
  98
  99 u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
 100 {
 101         return ioread16(asic->mapping +
 102                         (reg >> asic->bus_shift));
 103 }
 104 EXPORT_SYMBOL_GPL(asic3_read_register);
 105
 106 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
 107 {
 108         unsigned long flags;
 109         u32 val;
 110
 111         spin_lock_irqsave(&asic->lock, flags);
 112         val = asic3_read_register(asic, reg);
 113         if (set)
 114                 val |= bits;
 115         else
 116                 val &= ~bits;
 117         asic3_write_register(asic, reg, val);
 118         spin_unlock_irqrestore(&asic->lock, flags);
 119 }
 120
 121 /* IRQs */
 122 #define MAX_ASIC_ISR_LOOPS    20
 123 #define ASIC3_GPIO_BASE_INCR \
 124         (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
 125
 126 static void asic3_irq_flip_edge(struct asic3 *asic,
 127                                 u32 base, int bit)
 128 {
 129         u16 edge;
 130         unsigned long flags;
 131
 132         spin_lock_irqsave(&asic->lock, flags);
 133         edge = asic3_read_register(asic,
 134                                    base + ASIC3_GPIO_EDGE_TRIGGER);
 135         edge ^= bit;
 136         asic3_write_register(asic,
 137                              base + ASIC3_GPIO_EDGE_TRIGGER, edge);
 138         spin_unlock_irqrestore(&asic->lock, flags);
 139 }
 140
 141 static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
 142 {
 143         struct asic3 *asic = irq_desc_get_handler_data(desc);
 144         struct irq_data *data = irq_desc_get_irq_data(desc);
 145         int iter, i;
 146         unsigned long flags;
 147
 148         data->chip->irq_ack(data);
 149
 150         for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
 151                 u32 status;
 152                 int bank;
 153
 154                 spin_lock_irqsave(&asic->lock, flags);
 155                 status = asic3_read_register(asic,
 156                                              ASIC3_OFFSET(INTR, P_INT_STAT));
 157                 spin_unlock_irqrestore(&asic->lock, flags);
 158
 159                 /* Check all ten register bits */
 160                 if ((status & 0x3ff) == 0)
 161                         break;
 162
 163                 /* Handle GPIO IRQs */
 164                 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
 165                         if (status & (1 << bank)) {
 166                                 unsigned long base, istat;
 167
 168                                 base = ASIC3_GPIO_A_BASE
 169                                        + bank * ASIC3_GPIO_BASE_INCR;
 170
 171                                 spin_lock_irqsave(&asic->lock, flags);
 172                                 istat = asic3_read_register(asic,
 173                                                             base +
 174                                                             ASIC3_GPIO_INT_STATUS);
 175                                 /* Clearing IntStatus */
 176                                 asic3_write_register(asic,
 177                                                      base +
 178                                                      ASIC3_GPIO_INT_STATUS, 0);
 179                                 spin_unlock_irqrestore(&asic->lock, flags);
 180
 181                                 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
 182                                         int bit = (1 << i);
 183                                         unsigned int irqnr;
 184
 185                                         if (!(istat & bit))
 186                                                 continue;
 187
 188                                         irqnr = asic->irq_base +
 189                                                 (ASIC3_GPIOS_PER_BANK * bank)
 190                                                 + i;
 191                                         generic_handle_irq(irqnr);
 192                                         if (asic->irq_bothedge[bank] & bit)
 193                                                 asic3_irq_flip_edge(asic, base,
 194                                                                     bit);
 195                                 }
 196                         }
 197                 }
 198
 199                 /* Handle remaining IRQs in the status register */
 200                 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
 201                         /* They start at bit 4 and go up */
 202                         if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
 203                                 generic_handle_irq(asic->irq_base + i);
 204                 }
 205         }
 206
 207         if (iter >= MAX_ASIC_ISR_LOOPS)
 208                 dev_err(asic->dev, "interrupt processing overrun\n");
 209 }
 210
 211 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
 212 {
 213         int n;
 214
 215         n = (irq - asic->irq_base) >> 4;
 216
 217         return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
 218 }
 219
 220 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
 221 {
 222         return (irq - asic->irq_base) & 0xf;
 223 }
 224
 225 static void asic3_mask_gpio_irq(struct irq_data *data)
 226 {
 227         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 228         u32 val, bank, index;
 229         unsigned long flags;
 230
 231         bank = asic3_irq_to_bank(asic, data->irq);
 232         index = asic3_irq_to_index(asic, data->irq);
 233
 234         spin_lock_irqsave(&asic->lock, flags);
 235         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
 236         val |= 1 << index;
 237         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
 238         spin_unlock_irqrestore(&asic->lock, flags);
 239 }
 240
 241 static void asic3_mask_irq(struct irq_data *data)
 242 {
 243         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 244         int regval;
 245         unsigned long flags;
 246
 247         spin_lock_irqsave(&asic->lock, flags);
 248         regval = asic3_read_register(asic,
 249                                      ASIC3_INTR_BASE +
 250                                      ASIC3_INTR_INT_MASK);
 251
 252         regval &= ~(ASIC3_INTMASK_MASK0 <<
 253                     (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
 254
 255         asic3_write_register(asic,
 256                              ASIC3_INTR_BASE +
 257                              ASIC3_INTR_INT_MASK,
 258                              regval);
 259         spin_unlock_irqrestore(&asic->lock, flags);
 260 }
 261
 262 static void asic3_unmask_gpio_irq(struct irq_data *data)
 263 {
 264         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 265         u32 val, bank, index;
 266         unsigned long flags;
 267
 268         bank = asic3_irq_to_bank(asic, data->irq);
 269         index = asic3_irq_to_index(asic, data->irq);
 270
 271         spin_lock_irqsave(&asic->lock, flags);
 272         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
 273         val &= ~(1 << index);
 274         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
 275         spin_unlock_irqrestore(&asic->lock, flags);
 276 }
 277
 278 static void asic3_unmask_irq(struct irq_data *data)
 279 {
 280         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 281         int regval;
 282         unsigned long flags;
 283
 284         spin_lock_irqsave(&asic->lock, flags);
 285         regval = asic3_read_register(asic,
 286                                      ASIC3_INTR_BASE +
 287                                      ASIC3_INTR_INT_MASK);
 288
 289         regval |= (ASIC3_INTMASK_MASK0 <<
 290                    (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
 291
 292         asic3_write_register(asic,
 293                              ASIC3_INTR_BASE +
 294                              ASIC3_INTR_INT_MASK,
 295                              regval);
 296         spin_unlock_irqrestore(&asic->lock, flags);
 297 }
 298
 299 static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
 300 {
 301         struct asic3 *asic = irq_data_get_irq_chip_data(data);
 302         u32 bank, index;
 303         u16 trigger, level, edge, bit;
 304         unsigned long flags;
 305
 306         bank = asic3_irq_to_bank(asic, data->irq);
 307         index = asic3_irq_to_index(asic, data->irq);
 308         bit = 1<<index;
 309
 310         spin_lock_irqsave(&asic->lock, flags);
 311         level = asic3_read_register(asic,
 312                                     bank + ASIC3_GPIO_LEVEL_TRIGGER);
 313         edge = asic3_read_register(asic,
 314                                    bank + ASIC3_GPIO_EDGE_TRIGGER);
 315         trigger = asic3_read_register(asic,
 316                                       bank + ASIC3_GPIO_TRIGGER_TYPE);
 317         asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
 318
 319         if (type == IRQ_TYPE_EDGE_RISING) {
 320                 trigger |= bit;
 321                 edge |= bit;
 322         } else if (type == IRQ_TYPE_EDGE_FALLING) {
 323                 trigger |= bit;
 324                 edge &= ~bit;
 325         } else if (type == IRQ_TYPE_EDGE_BOTH) {
 326                 trigger |= bit;
 327                 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
 328                         edge &= ~bit;
 329                 else
 330                         edge |= bit;
 331                 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
 332         } else if (type == IRQ_TYPE_LEVEL_LOW) {
 333                 trigger &= ~bit;
 334                 level &= ~bit;
 335         } else if (type == IRQ_TYPE_LEVEL_HIGH) {
 336                 trigger &= ~bit;
 337                 level |= bit;
 338         } else {
 339                 /*
 340                  * if type == IRQ_TYPE_NONE, we should mask interrupts, but
 341                  * be careful to not unmask them if mask was also called.
 342                  * Probably need internal state for mask.
 343                  */
 344                 dev_notice(asic->dev, "irq type not changed\n");
 345         }
 346         asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
 347                              level);
 348         asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
 349                              edge);
 350         asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
 351                              trigger);
 352         spin_unlock_irqrestore(&asic->lock, flags);
 353         return 0;
 354 }
 355
 356 static struct irq_chip asic3_gpio_irq_chip = {
 357         .name           = "ASIC3-GPIO",
 358         .irq_ack        = asic3_mask_gpio_irq,
 359         .irq_mask       = asic3_mask_gpio_irq,
 360         .irq_unmask     = asic3_unmask_gpio_irq,
 361         .irq_set_type   = asic3_gpio_irq_type,
 362 };
 363
 364 static struct irq_chip asic3_irq_chip = {
 365         .name           = "ASIC3",
 366         .irq_ack        = asic3_mask_irq,
 367         .irq_mask       = asic3_mask_irq,
 368         .irq_unmask     = asic3_unmask_irq,
 369 };
 370
 371 static int __init asic3_irq_probe(struct platform_device *pdev)
 372 {
 373         struct asic3 *asic = platform_get_drvdata(pdev);
 374         unsigned long clksel = 0;
 375         unsigned int irq, irq_base;
 376         int ret;
 377
 378         ret = platform_get_irq(pdev, 0);
 379         if (ret < 0)
 380                 return ret;
 381         asic->irq_nr = ret;
 382
 383         /* turn on clock to IRQ controller */
 384         clksel |= CLOCK_SEL_CX;
 385         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
 386                              clksel);
 387
 388         irq_base = asic->irq_base;
 389
 390         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
 391                 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
 392                         irq_set_chip(irq, &asic3_gpio_irq_chip);
 393                 else
 394                         irq_set_chip(irq, &asic3_irq_chip);
 395
 396                 irq_set_chip_data(irq, asic);
 397                 irq_set_handler(irq, handle_level_irq);
 398                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 399         }
 400
 401         asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
 402                              ASIC3_INTMASK_GINTMASK);
 403
 404         irq_set_chained_handler(asic->irq_nr, asic3_irq_demux);
 405         irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
 406         irq_set_handler_data(asic->irq_nr, asic);
 407
 408         return 0;
 409 }
 410
 411 static void asic3_irq_remove(struct platform_device *pdev)
 412 {
 413         struct asic3 *asic = platform_get_drvdata(pdev);
 414         unsigned int irq, irq_base;
 415
 416         irq_base = asic->irq_base;
 417
 418         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
 419                 set_irq_flags(irq, 0);
 420                 irq_set_chip_and_handler(irq, NULL, NULL);
 421                 irq_set_chip_data(irq, NULL);
 422         }
 423         irq_set_chained_handler(asic->irq_nr, NULL);
 424 }
 425
 426 /* GPIOs */
 427 static int asic3_gpio_direction(struct gpio_chip *chip,
 428                                 unsigned offset, int out)
 429 {
 430         u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
 431         unsigned int gpio_base;
 432         unsigned long flags;
 433         struct asic3 *asic;
 434
 435         asic = container_of(chip, struct asic3, gpio);
 436         gpio_base = ASIC3_GPIO_TO_BASE(offset);
 437
 438         if (gpio_base > ASIC3_GPIO_D_BASE) {
 439                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 440                         gpio_base, offset);
 441                 return -EINVAL;
 442         }
 443
 444         spin_lock_irqsave(&asic->lock, flags);
 445
 446         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
 447
 448         /* Input is 0, Output is 1 */
 449         if (out)
 450                 out_reg |= mask;
 451         else
 452                 out_reg &= ~mask;
 453
 454         asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
 455
 456         spin_unlock_irqrestore(&asic->lock, flags);
 457
 458         return 0;
 459
 460 }
 461
 462 static int asic3_gpio_direction_input(struct gpio_chip *chip,
 463                                       unsigned offset)
 464 {
 465         return asic3_gpio_direction(chip, offset, 0);
 466 }
 467
 468 static int asic3_gpio_direction_output(struct gpio_chip *chip,
 469                                        unsigned offset, int value)
 470 {
 471         return asic3_gpio_direction(chip, offset, 1);
 472 }
 473
 474 static int asic3_gpio_get(struct gpio_chip *chip,
 475                           unsigned offset)
 476 {
 477         unsigned int gpio_base;
 478         u32 mask = ASIC3_GPIO_TO_MASK(offset);
 479         struct asic3 *asic;
 480
 481         asic = container_of(chip, struct asic3, gpio);
 482         gpio_base = ASIC3_GPIO_TO_BASE(offset);
 483
 484         if (gpio_base > ASIC3_GPIO_D_BASE) {
 485                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 486                         gpio_base, offset);
 487                 return -EINVAL;
 488         }
 489
 490         return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
 491 }
 492
 493 static void asic3_gpio_set(struct gpio_chip *chip,
 494                            unsigned offset, int value)
 495 {
 496         u32 mask, out_reg;
 497         unsigned int gpio_base;
 498         unsigned long flags;
 499         struct asic3 *asic;
 500
 501         asic = container_of(chip, struct asic3, gpio);
 502         gpio_base = ASIC3_GPIO_TO_BASE(offset);
 503
 504         if (gpio_base > ASIC3_GPIO_D_BASE) {
 505                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 506                         gpio_base, offset);
 507                 return;
 508         }
 509
 510         mask = ASIC3_GPIO_TO_MASK(offset);
 511
 512         spin_lock_irqsave(&asic->lock, flags);
 513
 514         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
 515
 516         if (value)
 517                 out_reg |= mask;
 518         else
 519                 out_reg &= ~mask;
 520
 521         asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
 522
 523         spin_unlock_irqrestore(&asic->lock, flags);
 524
 525         return;
 526 }
 527
 528 static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 529 {
 530         return (offset < ASIC3_NUM_GPIOS) ? IRQ_BOARD_START + offset : -ENXIO;
 531 }
 532
 533 static __init int asic3_gpio_probe(struct platform_device *pdev,
 534                                    u16 *gpio_config, int num)
 535 {
 536         struct asic3 *asic = platform_get_drvdata(pdev);
 537         u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
 538         u16 out_reg[ASIC3_NUM_GPIO_BANKS];
 539         u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
 540         int i;
 541
 542         memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 543         memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 544         memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 545
 546         /* Enable all GPIOs */
 547         asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
 548         asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
 549         asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
 550         asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
 551
 552         for (i = 0; i < num; i++) {
 553                 u8 alt, pin, dir, init, bank_num, bit_num;
 554                 u16 config = gpio_config[i];
 555
 556                 pin = ASIC3_CONFIG_GPIO_PIN(config);
 557                 alt = ASIC3_CONFIG_GPIO_ALT(config);
 558                 dir = ASIC3_CONFIG_GPIO_DIR(config);
 559                 init = ASIC3_CONFIG_GPIO_INIT(config);
 560
 561                 bank_num = ASIC3_GPIO_TO_BANK(pin);
 562                 bit_num = ASIC3_GPIO_TO_BIT(pin);
 563
 564                 alt_reg[bank_num] |= (alt << bit_num);
 565                 out_reg[bank_num] |= (init << bit_num);
 566                 dir_reg[bank_num] |= (dir << bit_num);
 567         }
 568
 569         for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
 570                 asic3_write_register(asic,
 571                                      ASIC3_BANK_TO_BASE(i) +
 572                                      ASIC3_GPIO_DIRECTION,
 573                                      dir_reg[i]);
 574                 asic3_write_register(asic,
 575                                      ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
 576                                      out_reg[i]);
 577                 asic3_write_register(asic,
 578                                      ASIC3_BANK_TO_BASE(i) +
 579                                      ASIC3_GPIO_ALT_FUNCTION,
 580                                      alt_reg[i]);
 581         }
 582
 583         return gpiochip_add(&asic->gpio);
 584 }
 585
 586 static int asic3_gpio_remove(struct platform_device *pdev)
 587 {
 588         struct asic3 *asic = platform_get_drvdata(pdev);
 589
 590         return gpiochip_remove(&asic->gpio);
 591 }
 592
 593 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
 594 {
 595         unsigned long flags;
 596         u32 cdex;
 597
 598         spin_lock_irqsave(&asic->lock, flags);
 599         if (clk->enabled++ == 0) {
 600                 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
 601                 cdex |= clk->cdex;
 602                 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
 603         }
 604         spin_unlock_irqrestore(&asic->lock, flags);
 605 }
 606
 607 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
 608 {
 609         unsigned long flags;
 610         u32 cdex;
 611
 612         WARN_ON(clk->enabled == 0);
 613
 614         spin_lock_irqsave(&asic->lock, flags);
 615         if (--clk->enabled == 0) {
 616                 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
 617                 cdex &= ~clk->cdex;
 618                 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
 619         }
 620         spin_unlock_irqrestore(&asic->lock, flags);
 621 }
 622
 623 /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
 624 static struct ds1wm_driver_data ds1wm_pdata = {
 625         .active_high = 1,
 626         .reset_recover_delay = 1,
 627 };
 628
 629 static struct resource ds1wm_resources[] = {
 630         {
 631                 .start = ASIC3_OWM_BASE,
 632                 .end   = ASIC3_OWM_BASE + 0x13,
 633                 .flags = IORESOURCE_MEM,
 634         },
 635         {
 636                 .start = ASIC3_IRQ_OWM,
 637                 .end   = ASIC3_IRQ_OWM,
 638                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 639         },
 640 };
 641
 642 static int ds1wm_enable(struct platform_device *pdev)
 643 {
 644         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 645
 646         /* Turn on external clocks and the OWM clock */
 647         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 648         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 649         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
 650         msleep(1);
 651
 652         /* Reset and enable DS1WM */
 653         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
 654                            ASIC3_EXTCF_OWM_RESET, 1);
 655         msleep(1);
 656         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
 657                            ASIC3_EXTCF_OWM_RESET, 0);
 658         msleep(1);
 659         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 660                            ASIC3_EXTCF_OWM_EN, 1);
 661         msleep(1);
 662
 663         return 0;
 664 }
 665
 666 static int ds1wm_disable(struct platform_device *pdev)
 667 {
 668         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 669
 670         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 671                            ASIC3_EXTCF_OWM_EN, 0);
 672
 673         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
 674         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 675         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 676
 677         return 0;
 678 }
 679
 680 static struct mfd_cell asic3_cell_ds1wm = {
 681         .name          = "ds1wm",
 682         .enable        = ds1wm_enable,
 683         .disable       = ds1wm_disable,
 684         .platform_data = &ds1wm_pdata,
 685         .pdata_size    = sizeof(ds1wm_pdata),
 686         .num_resources = ARRAY_SIZE(ds1wm_resources),
 687         .resources     = ds1wm_resources,
 688 };
 689
 690 static void asic3_mmc_pwr(struct platform_device *pdev, int state)
 691 {
 692         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 693
 694         tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
 695 }
 696
 697 static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
 698 {
 699         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 700
 701         tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
 702 }
 703
 704 static struct tmio_mmc_data asic3_mmc_data = {
 705         .hclk           = 24576000,
 706         .set_pwr        = asic3_mmc_pwr,
 707         .set_clk_div    = asic3_mmc_clk_div,
 708 };
 709
 710 static struct resource asic3_mmc_resources[] = {
 711         {
 712                 .start = ASIC3_SD_CTRL_BASE,
 713                 .end   = ASIC3_SD_CTRL_BASE + 0x3ff,
 714                 .flags = IORESOURCE_MEM,
 715         },
 716         {
 717                 .start = 0,
 718                 .end   = 0,
 719                 .flags = IORESOURCE_IRQ,
 720         },
 721 };
 722
 723 static int asic3_mmc_enable(struct platform_device *pdev)
 724 {
 725         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 726
 727         /* Not sure if it must be done bit by bit, but leaving as-is */
 728         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 729                            ASIC3_SDHWCTRL_LEVCD, 1);
 730         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 731                            ASIC3_SDHWCTRL_LEVWP, 1);
 732         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 733                            ASIC3_SDHWCTRL_SUSPEND, 0);
 734         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 735                            ASIC3_SDHWCTRL_PCLR, 0);
 736
 737         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 738         /* CLK32 used for card detection and for interruption detection
 739          * when HCLK is stopped.
 740          */
 741         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 742         msleep(1);
 743
 744         /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
 745         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
 746                 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
 747
 748         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
 749         asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
 750         msleep(1);
 751
 752         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 753                            ASIC3_EXTCF_SD_MEM_ENABLE, 1);
 754
 755         /* Enable SD card slot 3.3V power supply */
 756         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 757                            ASIC3_SDHWCTRL_SDPWR, 1);
 758
 759         /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
 760         tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
 761                              ASIC3_SD_CTRL_BASE >> 1);
 762
 763         return 0;
 764 }
 765
 766 static int asic3_mmc_disable(struct platform_device *pdev)
 767 {
 768         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 769
 770         /* Put in suspend mode */
 771         asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
 772                            ASIC3_SDHWCTRL_SUSPEND, 1);
 773
 774         /* Disable clocks */
 775         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
 776         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
 777         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
 778         asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
 779         return 0;
 780 }
 781
 782 static struct mfd_cell asic3_cell_mmc = {
 783         .name          = "tmio-mmc",
 784         .enable        = asic3_mmc_enable,
 785         .disable       = asic3_mmc_disable,
 786         .suspend       = asic3_mmc_disable,
 787         .resume        = asic3_mmc_enable,
 788         .platform_data = &asic3_mmc_data,
 789         .pdata_size    = sizeof(asic3_mmc_data),
 790         .num_resources = ARRAY_SIZE(asic3_mmc_resources),
 791         .resources     = asic3_mmc_resources,
 792 };
 793
 794 static const int clock_ledn[ASIC3_NUM_LEDS] = {
 795         [0] = ASIC3_CLOCK_LED0,
 796         [1] = ASIC3_CLOCK_LED1,
 797         [2] = ASIC3_CLOCK_LED2,
 798 };
 799
 800 static int asic3_leds_enable(struct platform_device *pdev)
 801 {
 802         const struct mfd_cell *cell = mfd_get_cell(pdev);
 803         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 804
 805         asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
 806
 807         return 0;
 808 }
 809
 810 static int asic3_leds_disable(struct platform_device *pdev)
 811 {
 812         const struct mfd_cell *cell = mfd_get_cell(pdev);
 813         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 814
 815         asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
 816
 817         return 0;
 818 }
 819
 820 static int asic3_leds_suspend(struct platform_device *pdev)
 821 {
 822         const struct mfd_cell *cell = mfd_get_cell(pdev);
 823         struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
 824
 825         while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
 826                 msleep(1);
 827
 828         asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
 829
 830         return 0;
 831 }
 832
 833 static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
 834         [0] = {
 835                 .name          = "leds-asic3",
 836                 .id            = 0,
 837                 .enable        = asic3_leds_enable,
 838                 .disable       = asic3_leds_disable,
 839                 .suspend       = asic3_leds_suspend,
 840                 .resume        = asic3_leds_enable,
 841         },
 842         [1] = {
 843                 .name          = "leds-asic3",
 844                 .id            = 1,
 845                 .enable        = asic3_leds_enable,
 846                 .disable       = asic3_leds_disable,
 847                 .suspend       = asic3_leds_suspend,
 848                 .resume        = asic3_leds_enable,
 849         },
 850         [2] = {
 851                 .name          = "leds-asic3",
 852                 .id            = 2,
 853                 .enable        = asic3_leds_enable,
 854                 .disable       = asic3_leds_disable,
 855                 .suspend       = asic3_leds_suspend,
 856                 .resume        = asic3_leds_enable,
 857         },
 858 };
 859
 860 static int __init asic3_mfd_probe(struct platform_device *pdev,
 861                                   struct asic3_platform_data *pdata,
 862                                   struct resource *mem)
 863 {
 864         struct asic3 *asic = platform_get_drvdata(pdev);
 865         struct resource *mem_sdio;
 866         int irq, ret;
 867
 868         mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 869         if (!mem_sdio)
 870                 dev_dbg(asic->dev, "no SDIO MEM resource\n");
 871
 872         irq = platform_get_irq(pdev, 1);
 873         if (irq < 0)
 874                 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
 875
 876         /* DS1WM */
 877         asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
 878                            ASIC3_EXTCF_OWM_SMB, 0);
 879
 880         ds1wm_resources[0].start >>= asic->bus_shift;
 881         ds1wm_resources[0].end   >>= asic->bus_shift;
 882
 883         /* MMC */
 884         asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >> asic->bus_shift) +
 885                                  mem_sdio->start,
 886                                  ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
 887         if (!asic->tmio_cnf) {
 888                 ret = -ENOMEM;
 889                 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
 890                 goto out;
 891         }
 892         asic3_mmc_resources[0].start >>= asic->bus_shift;
 893         asic3_mmc_resources[0].end   >>= asic->bus_shift;
 894
 895         ret = mfd_add_devices(&pdev->dev, pdev->id,
 896                         &asic3_cell_ds1wm, 1, mem, asic->irq_base);
 897         if (ret < 0)
 898                 goto out;
 899
 900         if (mem_sdio && (irq >= 0)) {
 901                 ret = mfd_add_devices(&pdev->dev, pdev->id,
 902                         &asic3_cell_mmc, 1, mem_sdio, irq);
 903                 if (ret < 0)
 904                         goto out;
 905         }
 906
 907         if (pdata->leds) {
 908                 int i;
 909
 910                 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
 911                         asic3_cell_leds[i].platform_data = &pdata->leds[i];
 912                         asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
 913                 }
 914                 ret = mfd_add_devices(&pdev->dev, 0,
 915                         asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0);
 916         }
 917
 918  out:
 919         return ret;
 920 }
 921
 922 static void asic3_mfd_remove(struct platform_device *pdev)
 923 {
 924         struct asic3 *asic = platform_get_drvdata(pdev);
 925
 926         mfd_remove_devices(&pdev->dev);
 927         iounmap(asic->tmio_cnf);
 928 }
 929
 930 /* Core */
 931 static int __init asic3_probe(struct platform_device *pdev)
 932 {
 933         struct asic3_platform_data *pdata = pdev->dev.platform_data;
 934         struct asic3 *asic;
 935         struct resource *mem;
 936         unsigned long clksel;
 937         int ret = 0;
 938
 939         asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
 940         if (asic == NULL) {
 941                 printk(KERN_ERR "kzalloc failed\n");
 942                 return -ENOMEM;
 943         }
 944
 945         spin_lock_init(&asic->lock);
 946         platform_set_drvdata(pdev, asic);
 947         asic->dev = &pdev->dev;
 948
 949         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 950         if (!mem) {
 951                 ret = -ENOMEM;
 952                 dev_err(asic->dev, "no MEM resource\n");
 953                 goto out_free;
 954         }
 955
 956         asic->mapping = ioremap(mem->start, resource_size(mem));
 957         if (!asic->mapping) {
 958                 ret = -ENOMEM;
 959                 dev_err(asic->dev, "Couldn't ioremap\n");
 960                 goto out_free;
 961         }
 962
 963         asic->irq_base = pdata->irq_base;
 964
 965         /* calculate bus shift from mem resource */
 966         asic->bus_shift = 2 - (resource_size(mem) >> 12);
 967
 968         clksel = 0;
 969         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
 970
 971         ret = asic3_irq_probe(pdev);
 972         if (ret < 0) {
 973                 dev_err(asic->dev, "Couldn't probe IRQs\n");
 974                 goto out_unmap;
 975         }
 976
 977         asic->gpio.label = "asic3";
 978         asic->gpio.base = pdata->gpio_base;
 979         asic->gpio.ngpio = ASIC3_NUM_GPIOS;
 980         asic->gpio.get = asic3_gpio_get;
 981         asic->gpio.set = asic3_gpio_set;
 982         asic->gpio.direction_input = asic3_gpio_direction_input;
 983         asic->gpio.direction_output = asic3_gpio_direction_output;
 984         asic->gpio.to_irq = asic3_gpio_to_irq;
 985
 986         ret = asic3_gpio_probe(pdev,
 987                                pdata->gpio_config,
 988                                pdata->gpio_config_num);
 989         if (ret < 0) {
 990                 dev_err(asic->dev, "GPIO probe failed\n");
 991                 goto out_irq;
 992         }
 993
 994         /* Making a per-device copy is only needed for the
 995          * theoretical case of multiple ASIC3s on one board:
 996          */
 997         memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
 998
 999         asic3_mfd_probe(pdev, pdata, mem);
1000
1001         dev_info(asic->dev, "ASIC3 Core driver\n");
1002
1003         return 0;
1004
1005  out_irq:
1006         asic3_irq_remove(pdev);
1007
1008  out_unmap:
1009         iounmap(asic->mapping);
1010
1011  out_free:
1012         kfree(asic);
1013
1014         return ret;
1015 }
1016
1017 static int __devexit asic3_remove(struct platform_device *pdev)
1018 {
1019         int ret;
1020         struct asic3 *asic = platform_get_drvdata(pdev);
1021
1022         asic3_mfd_remove(pdev);
1023
1024         ret = asic3_gpio_remove(pdev);
1025         if (ret < 0)
1026                 return ret;
1027         asic3_irq_remove(pdev);
1028
1029         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1030
1031         iounmap(asic->mapping);
1032
1033         kfree(asic);
1034
1035         return 0;
1036 }
1037
1038 static void asic3_shutdown(struct platform_device *pdev)
1039 {
1040 }
1041
1042 static struct platform_driver asic3_device_driver = {
1043         .driver         = {
1044                 .name   = "asic3",
1045         },
1046         .remove         = __devexit_p(asic3_remove),
1047         .shutdown       = asic3_shutdown,
1048 };
1049
1050 static int __init asic3_init(void)
1051 {
1052         int retval = 0;
1053         retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
1054         return retval;
1055 }
1056
1057 subsys_initcall(asic3_init);