2 * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/types.h>
18 #include <linux/videodev2.h>
21 #include <media/media-entity.h>
22 #include <media/videobuf2-core.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-mem2mem.h>
26 #include <media/v4l2-mediabus.h>
27 #include <media/s5p_fimc.h>
29 #include "regs-fimc.h"
31 #define err(fmt, args...) \
32 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
34 #define dbg(fmt, args...) \
35 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
37 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
38 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
39 #define MAX_FIMC_CLOCKS 2
40 #define FIMC_MODULE_NAME "s5p-fimc"
41 #define FIMC_MAX_DEVS 4
42 #define FIMC_MAX_OUT_BUFS 4
43 #define SCALER_MAX_HRATIO 64
44 #define SCALER_MAX_VRATIO 64
45 #define DMA_MIN_SIZE 8
46 #define FIMC_CAMIF_MAX_HEIGHT 0x2000
48 /* indices to the clocks array */
71 #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
72 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
74 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
75 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
76 #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
86 S5P_FIMC_RGB565 = 0x10,
90 S5P_FIMC_YCBCR420 = 0x20,
95 S5P_FIMC_YCBCR444_LOCAL,
99 #define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
100 #define fimc_fmt_is_jpeg(x) (!!((x) & 0x40))
102 #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
103 __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
105 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
106 #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
108 /* The embedded image effect selection */
109 #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
110 #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
111 #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
112 #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
113 #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
114 #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
116 /* The hardware context state. */
117 #define FIMC_PARAMS (1 << 0)
118 #define FIMC_SRC_ADDR (1 << 1)
119 #define FIMC_DST_ADDR (1 << 2)
120 #define FIMC_SRC_FMT (1 << 3)
121 #define FIMC_DST_FMT (1 << 4)
122 #define FIMC_DST_CROP (1 << 5)
123 #define FIMC_CTX_M2M (1 << 16)
124 #define FIMC_CTX_CAP (1 << 17)
125 #define FIMC_CTX_SHUT (1 << 18)
127 /* Image conversion flags */
128 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
129 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
130 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
131 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
132 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
133 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
135 * YCbCr data dynamic range for RGB-YUV color conversion.
136 * Y/Cb/Cr: (0 ~ 255) */
137 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
138 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
139 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
142 * struct fimc_fmt - the driver's internal color format data
143 * @mbus_code: Media Bus pixel code, -1 if not applicable
144 * @name: format description
145 * @fourcc: the fourcc code for this format, 0 if not applicable
146 * @color: the corresponding fimc_color_fmt
147 * @memplanes: number of physically non-contiguous data planes
148 * @colplanes: number of physically contiguous data planes
149 * @depth: per plane driver's private 'number of bits per pixel'
150 * @flags: flags indicating which operation mode format applies to
153 enum v4l2_mbus_pixelcode mbus_code;
159 u8 depth[VIDEO_MAX_PLANES];
161 #define FMT_FLAGS_CAM (1 << 0)
162 #define FMT_FLAGS_M2M (1 << 1)
166 * struct fimc_dma_offset - pixel offset information for DMA
167 * @y_h: y value horizontal offset
168 * @y_v: y value vertical offset
169 * @cb_h: cb value horizontal offset
170 * @cb_v: cb value vertical offset
171 * @cr_h: cr value horizontal offset
172 * @cr_v: cr value vertical offset
174 struct fimc_dma_offset {
184 * struct fimc_effect - color effect information
186 * @pat_cb: cr value when type is "arbitrary"
187 * @pat_cr: cr value when type is "arbitrary"
196 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
197 * @scaleup_h: flag indicating scaling up horizontally
198 * @scaleup_v: flag indicating scaling up vertically
199 * @copy_mode: flag indicating transparent DMA transfer (no scaling
200 * and color format conversion)
201 * @enabled: flag indicating if the scaler is used
202 * @hfactor: horizontal shift factor
203 * @vfactor: vertical shift factor
204 * @pre_hratio: horizontal ratio of the prescaler
205 * @pre_vratio: vertical ratio of the prescaler
206 * @pre_dst_width: the prescaler's destination width
207 * @pre_dst_height: the prescaler's destination height
208 * @main_hratio: the main scaler's horizontal ratio
209 * @main_vratio: the main scaler's vertical ratio
210 * @real_width: source pixel (width - offset)
211 * @real_height: source pixel (height - offset)
214 unsigned int scaleup_h:1;
215 unsigned int scaleup_v:1;
216 unsigned int copy_mode:1;
217 unsigned int enabled:1;
231 * struct fimc_addr - the FIMC physical address set for DMA
232 * @y: luminance plane physical address
233 * @cb: Cb plane physical address
234 * @cr: Cr plane physical address
243 * struct fimc_vid_buffer - the driver's video buffer
244 * @vb: v4l videobuf buffer
245 * @list: linked list structure for buffer queue
246 * @paddr: precalculated physical address set
247 * @index: buffer index for the output DMA engine
249 struct fimc_vid_buffer {
250 struct vb2_buffer vb;
251 struct list_head list;
252 struct fimc_addr paddr;
257 * struct fimc_frame - source/target frame properties
258 * @f_width: image full width (virtual screen size)
259 * @f_height: image full height (virtual screen size)
260 * @o_width: original image width as set by S_FMT
261 * @o_height: original image height as set by S_FMT
262 * @offs_h: image horizontal pixel offset
263 * @offs_v: image vertical pixel offset
264 * @width: image pixel width
265 * @height: image pixel weight
266 * @payload: image size in bytes (w x h x bpp)
267 * @paddr: image frame buffer physical addresses
268 * @dma_offset: DMA offset in bytes
269 * @fmt: fimc color format pointer
280 unsigned long payload[VIDEO_MAX_PLANES];
281 struct fimc_addr paddr;
282 struct fimc_dma_offset dma_offset;
283 struct fimc_fmt *fmt;
287 * struct fimc_m2m_device - v4l2 memory-to-memory device data
288 * @vfd: the video device node for v4l2 m2m mode
289 * @m2m_dev: v4l2 memory-to-memory device data
290 * @ctx: hardware context data
291 * @refcnt: the reference counter
293 struct fimc_m2m_device {
294 struct video_device *vfd;
295 struct v4l2_m2m_dev *m2m_dev;
296 struct fimc_ctx *ctx;
300 #define FIMC_SD_PAD_SINK 0
301 #define FIMC_SD_PAD_SOURCE 1
302 #define FIMC_SD_PADS_NUM 2
305 * struct fimc_vid_cap - camera capture device information
306 * @ctx: hardware context data
307 * @vfd: video device node for camera capture mode
308 * @subdev: subdev exposing the FIMC processing block
309 * @vd_pad: fimc video capture node pad
310 * @sd_pads: fimc video processing block pads
311 * @mf: media bus format at the FIMC camera input (and the scaler output) pad
312 * @pending_buf_q: the pending buffer queue head
313 * @active_buf_q: the queue head of buffers scheduled in hardware
314 * @vbq: the capture am video buffer queue
315 * @active_buf_cnt: number of video buffers scheduled in hardware
316 * @buf_index: index for managing the output DMA buffers
317 * @frame_count: the frame counter for statistics
318 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
319 * @input_index: input (camera sensor) index
320 * @refcnt: driver's private reference counter
321 * @input: capture input type, grp_id of the attached subdev
322 * @user_subdev_api: true if subdevs are not configured by the host driver
324 struct fimc_vid_cap {
325 struct fimc_ctx *ctx;
326 struct vb2_alloc_ctx *alloc_ctx;
327 struct video_device *vfd;
328 struct v4l2_subdev *subdev;
329 struct media_pad vd_pad;
330 struct v4l2_mbus_framefmt mf;
331 struct media_pad sd_pads[FIMC_SD_PADS_NUM];
332 struct list_head pending_buf_q;
333 struct list_head active_buf_q;
334 struct vb2_queue vbq;
337 unsigned int frame_count;
338 unsigned int reqbufs_count;
342 bool user_subdev_api;
346 * struct fimc_pix_limit - image pixel size limits in various IP configurations
348 * @scaler_en_w: max input pixel width when the scaler is enabled
349 * @scaler_dis_w: max input pixel width when the scaler is disabled
350 * @in_rot_en_h: max input width with the input rotator is on
351 * @in_rot_dis_w: max input width with the input rotator is off
352 * @out_rot_en_w: max output width with the output rotator on
353 * @out_rot_dis_w: max output width with the output rotator off
355 struct fimc_pix_limit {
365 * struct samsung_fimc_variant - camera interface variant information
367 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
368 * @has_inp_rot: set if has input rotator
369 * @has_out_rot: set if has output rotator
370 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
371 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
372 * are present in this IP revision
373 * @has_cam_if: set if this instance has a camera input interface
374 * @pix_limit: pixel size constraints for the scaler
375 * @min_inp_pixsize: minimum input pixel size
376 * @min_out_pixsize: minimum output pixel size
377 * @hor_offs_align: horizontal pixel offset aligment
378 * @out_buf_count: the number of buffers in output DMA sequence
380 struct samsung_fimc_variant {
381 unsigned int pix_hoff:1;
382 unsigned int has_inp_rot:1;
383 unsigned int has_out_rot:1;
384 unsigned int has_cistatus2:1;
385 unsigned int has_mainscaler_ext:1;
386 unsigned int has_cam_if:1;
387 struct fimc_pix_limit *pix_limit;
395 * struct samsung_fimc_driverdata - per device type driver data for init time.
397 * @variant: the variant information for this driver.
398 * @dev_cnt: number of fimc sub-devices available in SoC
399 * @lclk_frequency: fimc bus clock frequency
401 struct samsung_fimc_driverdata {
402 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
403 unsigned long lclk_frequency;
407 struct fimc_pipeline {
408 struct media_pipeline *pipe;
409 struct v4l2_subdev *sensor;
410 struct v4l2_subdev *csis;
416 * struct fimc_dev - abstraction for FIMC entity
417 * @slock: the spinlock protecting this data structure
418 * @lock: the mutex protecting this data structure
419 * @pdev: pointer to the FIMC platform device
420 * @pdata: pointer to the device platform data
421 * @variant: the IP variant information
422 * @id: FIMC device index (0..FIMC_MAX_DEVS)
423 * @num_clocks: the number of clocks managed by this device instance
424 * @clock: clocks required for FIMC operation
425 * @regs: the mapped hardware registers
426 * @regs_res: the resource claimed for IO registers
427 * @irq: FIMC interrupt number
428 * @irq_queue: interrupt handler waitqueue
429 * @v4l2_dev: root v4l2_device
430 * @m2m: memory-to-memory V4L2 device information
431 * @vid_cap: camera capture device information
432 * @state: flags used to synchronize m2m and capture mode operation
433 * @alloc_ctx: videobuf2 memory allocator context
434 * @pipeline: fimc video capture pipeline data structure
439 struct platform_device *pdev;
440 struct s5p_platform_fimc *pdata;
441 struct samsung_fimc_variant *variant;
444 struct clk *clock[MAX_FIMC_CLOCKS];
446 struct resource *regs_res;
448 wait_queue_head_t irq_queue;
449 struct v4l2_device *v4l2_dev;
450 struct fimc_m2m_device m2m;
451 struct fimc_vid_cap vid_cap;
453 struct vb2_alloc_ctx *alloc_ctx;
454 struct fimc_pipeline pipeline;
458 * fimc_ctx - the device context data
459 * @slock: spinlock protecting this data structure
460 * @s_frame: source frame properties
461 * @d_frame: destination frame properties
462 * @out_order_1p: output 1-plane YCBCR order
463 * @out_order_2p: output 2-plane YCBCR order
464 * @in_order_1p input 1-plane YCBCR order
465 * @in_order_2p: input 2-plane YCBCR order
466 * @in_path: input mode (DMA or camera)
467 * @out_path: output mode (DMA or FIFO)
468 * @scaler: image scaler properties
469 * @effect: image effect
470 * @rotation: image clockwise rotation in degrees
471 * @hflip: indicates image horizontal flip if set
472 * @vflip: indicates image vertical flip if set
473 * @flags: additional flags for image conversion
474 * @state: flags to keep track of user configuration
475 * @fimc_dev: the FIMC device this context applies to
476 * @m2m_ctx: memory-to-memory device context
477 * @fh: v4l2 file handle
478 * @ctrl_handler: v4l2 controls handler
479 * @ctrl_rotate image rotation control
480 * @ctrl_hflip horizontal flip control
481 * @ctrl_vflip vartical flip control
482 * @ctrls_rdy: true if the control handler is initialized
486 struct fimc_frame s_frame;
487 struct fimc_frame d_frame;
492 enum fimc_datapath in_path;
493 enum fimc_datapath out_path;
494 struct fimc_scaler scaler;
495 struct fimc_effect effect;
497 unsigned int hflip:1;
498 unsigned int vflip:1;
501 struct fimc_dev *fimc_dev;
502 struct v4l2_m2m_ctx *m2m_ctx;
504 struct v4l2_ctrl_handler ctrl_handler;
505 struct v4l2_ctrl *ctrl_rotate;
506 struct v4l2_ctrl *ctrl_hflip;
507 struct v4l2_ctrl *ctrl_vflip;
511 #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
513 static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
516 f->o_height = height;
518 f->f_height = height;
521 static inline void set_frame_crop(struct fimc_frame *f,
522 u32 left, u32 top, u32 width, u32 height)
530 static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
535 for (i = 0; i < ff->colplanes; i++)
536 depth += ff->depth[i];
540 static inline bool fimc_capture_active(struct fimc_dev *fimc)
545 spin_lock_irqsave(&fimc->slock, flags);
546 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
547 fimc->state & (1 << ST_CAPT_PEND));
548 spin_unlock_irqrestore(&fimc->slock, flags);
552 static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx)
556 spin_lock_irqsave(&ctx->slock, flags);
558 spin_unlock_irqrestore(&ctx->slock, flags);
561 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
566 spin_lock_irqsave(&ctx->slock, flags);
567 ret = (ctx->state & mask) == mask;
568 spin_unlock_irqrestore(&ctx->slock, flags);
572 static inline int tiled_fmt(struct fimc_fmt *fmt)
574 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
577 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
579 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
580 cfg |= S5P_CIGCTRL_IRQ_CLR;
581 writel(cfg, dev->regs + S5P_CIGCTRL);
584 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
586 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
588 cfg |= S5P_CISCCTRL_SCALERSTART;
590 cfg &= ~S5P_CISCCTRL_SCALERSTART;
591 writel(cfg, dev->regs + S5P_CISCCTRL);
594 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
596 u32 cfg = readl(dev->regs + S5P_MSCTRL);
598 cfg |= S5P_MSCTRL_ENVID;
600 cfg &= ~S5P_MSCTRL_ENVID;
601 writel(cfg, dev->regs + S5P_MSCTRL);
604 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
606 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
607 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
608 writel(cfg, dev->regs + S5P_CIIMGCPT);
612 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
613 * @mask: each bit corresponds to one of 32 output buffer registers set
614 * 1 to include buffer in the sequence, 0 to disable
616 * This function mask output DMA ring buffers, i.e. it allows to configure
617 * which of the output buffer address registers will be used by the DMA
620 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
622 writel(mask, dev->regs + S5P_CIFCNTSEQ);
625 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
626 enum v4l2_buf_type type)
628 struct fimc_frame *frame;
630 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
631 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
632 frame = &ctx->s_frame;
634 return ERR_PTR(-EINVAL);
635 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
636 frame = &ctx->d_frame;
638 v4l2_err(ctx->fimc_dev->v4l2_dev,
639 "Wrong buffer/video queue type (%d)\n", type);
640 return ERR_PTR(-EINVAL);
646 /* Return an index to the buffer actually being written. */
647 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
651 if (dev->variant->has_cistatus2) {
652 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
653 return reg > 0 ? --reg : reg;
655 reg = readl(dev->regs + S5P_CISTATUS);
656 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
657 S5P_CISTATUS_FRAMECNT_SHIFT;
661 /* -----------------------------------------------------*/
663 void fimc_hw_reset(struct fimc_dev *fimc);
664 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
665 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
666 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
667 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
668 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
669 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
670 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
671 void fimc_hw_en_capture(struct fimc_ctx *ctx);
672 void fimc_hw_set_effect(struct fimc_ctx *ctx);
673 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
674 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
675 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
676 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
677 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
679 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
680 struct s5p_fimc_isp_info *cam);
681 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
682 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
683 struct s5p_fimc_isp_info *cam);
684 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
685 struct s5p_fimc_isp_info *cam);
687 /* -----------------------------------------------------*/
689 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
690 struct v4l2_fmtdesc *f);
691 int fimc_ctrls_create(struct fimc_ctx *ctx);
692 void fimc_ctrls_delete(struct fimc_ctx *ctx);
693 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
694 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f);
695 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
696 struct v4l2_pix_format_mplane *pix);
697 struct fimc_fmt *fimc_find_format(u32 *pixelformat, u32 *mbus_code,
698 unsigned int mask, int index);
700 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot);
701 int fimc_set_scaler_info(struct fimc_ctx *ctx);
702 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
703 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
704 struct fimc_frame *frame, struct fimc_addr *paddr);
705 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
706 void fimc_set_yuv_order(struct fimc_ctx *ctx);
707 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f);
709 int fimc_register_m2m_device(struct fimc_dev *fimc,
710 struct v4l2_device *v4l2_dev);
711 void fimc_unregister_m2m_device(struct fimc_dev *fimc);
712 int fimc_register_driver(void);
713 void fimc_unregister_driver(void);
715 /* -----------------------------------------------------*/
717 int fimc_register_capture_device(struct fimc_dev *fimc,
718 struct v4l2_device *v4l2_dev);
719 void fimc_unregister_capture_device(struct fimc_dev *fimc);
720 int fimc_capture_ctrls_create(struct fimc_dev *fimc);
721 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
722 struct fimc_vid_buffer *fimc_vb);
723 int fimc_capture_suspend(struct fimc_dev *fimc);
724 int fimc_capture_resume(struct fimc_dev *fimc);
725 int fimc_capture_config_update(struct fimc_ctx *ctx);
727 /* Locking: the caller holds fimc->slock */
728 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
730 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
731 fimc_hw_en_capture(ctx);
734 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
736 fimc_hw_en_lastirq(fimc, true);
737 fimc_hw_dis_capture(fimc);
738 fimc_hw_enable_scaler(fimc, false);
739 fimc_hw_en_lastirq(fimc, false);
743 * Add buf to the capture active buffers queue.
744 * Locking: Need to be called with fimc_dev::slock held.
746 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
747 struct fimc_vid_buffer *buf)
749 list_add_tail(&buf->list, &vid_cap->active_buf_q);
750 vid_cap->active_buf_cnt++;
754 * Pop a video buffer from the capture active buffers queue
755 * Locking: Need to be called with fimc_dev::slock held.
757 static inline struct fimc_vid_buffer *
758 active_queue_pop(struct fimc_vid_cap *vid_cap)
760 struct fimc_vid_buffer *buf;
761 buf = list_entry(vid_cap->active_buf_q.next,
762 struct fimc_vid_buffer, list);
763 list_del(&buf->list);
764 vid_cap->active_buf_cnt--;
768 /* Add video buffer to the capture pending buffers queue */
769 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
770 struct fimc_vid_buffer *buf)
772 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
775 /* Add video buffer to the capture pending buffers queue */
776 static inline struct fimc_vid_buffer *
777 pending_queue_pop(struct fimc_vid_cap *vid_cap)
779 struct fimc_vid_buffer *buf;
780 buf = list_entry(vid_cap->pending_buf_q.next,
781 struct fimc_vid_buffer, list);
782 list_del(&buf->list);
786 #endif /* FIMC_CORE_H_ */