2 * Copyright (c) 2010 Samsung Electronics
4 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
16 #include <linux/sched.h>
17 #include <linux/types.h>
18 #include <linux/videodev2.h>
20 #include <media/videobuf2-core.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-mem2mem.h>
23 #include <media/v4l2-mediabus.h>
24 #include <media/s5p_fimc.h>
26 #include "regs-fimc.h"
28 #define err(fmt, args...) \
29 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
32 #define dbg(fmt, args...) \
33 printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
35 #define dbg(fmt, args...)
38 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
39 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
40 #define MAX_FIMC_CLOCKS 3
41 #define MODULE_NAME "s5p-fimc"
42 #define FIMC_MAX_DEVS 4
43 #define FIMC_MAX_OUT_BUFS 4
44 #define SCALER_MAX_HRATIO 64
45 #define SCALER_MAX_VRATIO 64
46 #define DMA_MIN_SIZE 8
48 /* indices to the clocks array */
60 /* for capture node */
67 #define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
68 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
70 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
71 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
73 #define fimc_capture_active(dev) \
74 (test_bit(ST_CAPT_RUN, &(dev)->state) || \
75 test_bit(ST_CAPT_PEND, &(dev)->state))
77 #define fimc_capture_streaming(dev) \
78 test_bit(ST_CAPT_STREAM, &(dev)->state)
88 S5P_FIMC_RGB565 = 0x10,
92 S5P_FIMC_YCBCR420 = 0x20,
97 S5P_FIMC_YCBCR444_LOCAL,
100 #define fimc_fmt_is_rgb(x) ((x) & 0x10)
102 /* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats. */
103 #define S5P_FIMC_OUT_CRYCBY S5P_CIOCTRL_ORDER422_CRYCBY
104 #define S5P_FIMC_OUT_CBYCRY S5P_CIOCTRL_ORDER422_YCRYCB
105 #define S5P_FIMC_OUT_YCRYCB S5P_CIOCTRL_ORDER422_CBYCRY
106 #define S5P_FIMC_OUT_YCBYCR S5P_CIOCTRL_ORDER422_YCBYCR
108 /* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats. */
109 #define S5P_FIMC_IN_CRYCBY S5P_MSCTRL_ORDER422_CRYCBY
110 #define S5P_FIMC_IN_CBYCRY S5P_MSCTRL_ORDER422_YCRYCB
111 #define S5P_FIMC_IN_YCRYCB S5P_MSCTRL_ORDER422_CBYCRY
112 #define S5P_FIMC_IN_YCBYCR S5P_MSCTRL_ORDER422_YCBYCR
114 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
115 #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
117 /* The embedded image effect selection */
118 #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
119 #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
120 #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
121 #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
122 #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
123 #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
125 /* The hardware context state. */
126 #define FIMC_PARAMS (1 << 0)
127 #define FIMC_SRC_ADDR (1 << 1)
128 #define FIMC_DST_ADDR (1 << 2)
129 #define FIMC_SRC_FMT (1 << 3)
130 #define FIMC_DST_FMT (1 << 4)
131 #define FIMC_CTX_M2M (1 << 5)
132 #define FIMC_CTX_CAP (1 << 6)
134 /* Image conversion flags */
135 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
136 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
137 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
138 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
139 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
140 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
142 * YCbCr data dynamic range for RGB-YUV color conversion.
143 * Y/Cb/Cr: (0 ~ 255) */
144 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
145 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
146 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
149 #define FLIP_X_AXIS 1
150 #define FLIP_Y_AXIS 2
151 #define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS)
154 * struct fimc_fmt - the driver's internal color format data
155 * @mbus_code: Media Bus pixel code, -1 if not applicable
156 * @name: format description
157 * @fourcc: the fourcc code for this format, 0 if not applicable
158 * @color: the corresponding fimc_color_fmt
159 * @depth: per plane driver's private 'number of bits per pixel'
160 * @memplanes: number of physically non-contiguous data planes
161 * @colplanes: number of physically contiguous data planes
164 enum v4l2_mbus_pixelcode mbus_code;
170 u8 depth[VIDEO_MAX_PLANES];
172 #define FMT_FLAGS_CAM (1 << 0)
173 #define FMT_FLAGS_M2M (1 << 1)
177 * struct fimc_dma_offset - pixel offset information for DMA
178 * @y_h: y value horizontal offset
179 * @y_v: y value vertical offset
180 * @cb_h: cb value horizontal offset
181 * @cb_v: cb value vertical offset
182 * @cr_h: cr value horizontal offset
183 * @cr_v: cr value vertical offset
185 struct fimc_dma_offset {
195 * struct fimc_effect - the configuration data for the "Arbitrary" image effect
197 * @pat_cb: cr value when type is "arbitrary"
198 * @pat_cr: cr value when type is "arbitrary"
207 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
209 * @scaleup_h: flag indicating scaling up horizontally
210 * @scaleup_v: flag indicating scaling up vertically
211 * @copy_mode: flag indicating transparent DMA transfer (no scaling
212 * and color format conversion)
213 * @enabled: flag indicating if the scaler is used
214 * @hfactor: horizontal shift factor
215 * @vfactor: vertical shift factor
216 * @pre_hratio: horizontal ratio of the prescaler
217 * @pre_vratio: vertical ratio of the prescaler
218 * @pre_dst_width: the prescaler's destination width
219 * @pre_dst_height: the prescaler's destination height
220 * @main_hratio: the main scaler's horizontal ratio
221 * @main_vratio: the main scaler's vertical ratio
222 * @real_width: source pixel (width - offset)
223 * @real_height: source pixel (height - offset)
226 unsigned int scaleup_h:1;
227 unsigned int scaleup_v:1;
228 unsigned int copy_mode:1;
229 unsigned int enabled:1;
243 * struct fimc_addr - the FIMC physical address set for DMA
245 * @y: luminance plane physical address
246 * @cb: Cb plane physical address
247 * @cr: Cr plane physical address
256 * struct fimc_vid_buffer - the driver's video buffer
257 * @vb: v4l videobuf buffer
258 * @paddr: precalculated physical address set
259 * @index: buffer index for the output DMA engine
261 struct fimc_vid_buffer {
262 struct vb2_buffer vb;
263 struct list_head list;
264 struct fimc_addr paddr;
269 * struct fimc_frame - source/target frame properties
270 * @f_width: image full width (virtual screen size)
271 * @f_height: image full height (virtual screen size)
272 * @o_width: original image width as set by S_FMT
273 * @o_height: original image height as set by S_FMT
274 * @offs_h: image horizontal pixel offset
275 * @offs_v: image vertical pixel offset
276 * @width: image pixel width
277 * @height: image pixel weight
278 * @paddr: image frame buffer physical addresses
279 * @buf_cnt: number of buffers depending on a color format
280 * @payload: image size in bytes (w x h x bpp)
281 * @color: color format
282 * @dma_offset: DMA offset in bytes
293 unsigned long payload[VIDEO_MAX_PLANES];
294 struct fimc_addr paddr;
295 struct fimc_dma_offset dma_offset;
296 struct fimc_fmt *fmt;
300 * struct fimc_m2m_device - v4l2 memory-to-memory device data
301 * @vfd: the video device node for v4l2 m2m mode
302 * @v4l2_dev: v4l2 device for m2m mode
303 * @m2m_dev: v4l2 memory-to-memory device data
304 * @ctx: hardware context data
305 * @refcnt: the reference counter
307 struct fimc_m2m_device {
308 struct video_device *vfd;
309 struct v4l2_device v4l2_dev;
310 struct v4l2_m2m_dev *m2m_dev;
311 struct fimc_ctx *ctx;
316 * struct fimc_vid_cap - camera capture device information
317 * @ctx: hardware context data
318 * @vfd: video device node for camera capture mode
319 * @v4l2_dev: v4l2_device struct to manage subdevs
320 * @sd: pointer to camera sensor subdevice currently in use
321 * @fmt: Media Bus format configured at selected image sensor
322 * @pending_buf_q: the pending buffer queue head
323 * @active_buf_q: the queue head of buffers scheduled in hardware
324 * @vbq: the capture am video buffer queue
325 * @active_buf_cnt: number of video buffers scheduled in hardware
326 * @buf_index: index for managing the output DMA buffers
327 * @frame_count: the frame counter for statistics
328 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
329 * @input_index: input (camera sensor) index
330 * @refcnt: driver's private reference counter
332 struct fimc_vid_cap {
333 struct fimc_ctx *ctx;
334 struct vb2_alloc_ctx *alloc_ctx;
335 struct video_device *vfd;
336 struct v4l2_device v4l2_dev;
337 struct v4l2_subdev *sd;;
338 struct v4l2_mbus_framefmt fmt;
339 struct list_head pending_buf_q;
340 struct list_head active_buf_q;
341 struct vb2_queue vbq;
344 unsigned int frame_count;
345 unsigned int reqbufs_count;
351 * struct fimc_pix_limit - image pixel size limits in various IP configurations
353 * @scaler_en_w: max input pixel width when the scaler is enabled
354 * @scaler_dis_w: max input pixel width when the scaler is disabled
355 * @in_rot_en_h: max input width with the input rotator is on
356 * @in_rot_dis_w: max input width with the input rotator is off
357 * @out_rot_en_w: max output width with the output rotator on
358 * @out_rot_dis_w: max output width with the output rotator off
360 struct fimc_pix_limit {
370 * struct samsung_fimc_variant - camera interface variant information
372 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
373 * @has_inp_rot: set if has input rotator
374 * @has_out_rot: set if has output rotator
375 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
376 * @pix_limit: pixel size constraints for the scaler
377 * @min_inp_pixsize: minimum input pixel size
378 * @min_out_pixsize: minimum output pixel size
379 * @hor_offs_align: horizontal pixel offset aligment
380 * @out_buf_count: the number of buffers in output DMA sequence
382 struct samsung_fimc_variant {
383 unsigned int pix_hoff:1;
384 unsigned int has_inp_rot:1;
385 unsigned int has_out_rot:1;
386 unsigned int has_cistatus2:1;
387 struct fimc_pix_limit *pix_limit;
395 * struct samsung_fimc_driverdata - per device type driver data for init time.
397 * @variant: the variant information for this driver.
398 * @dev_cnt: number of fimc sub-devices available in SoC
399 * @lclk_frequency: fimc bus clock frequency
401 struct samsung_fimc_driverdata {
402 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
403 unsigned long lclk_frequency;
410 * struct fimc_dev - abstraction for FIMC entity
412 * @slock: the spinlock protecting this data structure
413 * @lock: the mutex protecting this data structure
414 * @pdev: pointer to the FIMC platform device
415 * @pdata: pointer to the device platform data
416 * @id: FIMC device index (0..FIMC_MAX_DEVS)
417 * @num_clocks: the number of clocks managed by this device instance
418 * @clock[]: the clocks required for FIMC operation
419 * @regs: the mapped hardware registers
420 * @regs_res: the resource claimed for IO registers
421 * @irq: interrupt number of the FIMC subdevice
423 * @m2m: memory-to-memory V4L2 device information
424 * @vid_cap: camera capture device information
425 * @state: flags used to synchronize m2m and capture mode operation
430 struct platform_device *pdev;
431 struct s5p_platform_fimc *pdata;
432 struct samsung_fimc_variant *variant;
435 struct clk *clock[MAX_FIMC_CLOCKS];
437 struct resource *regs_res;
439 wait_queue_head_t irq_queue;
440 struct fimc_m2m_device m2m;
441 struct fimc_vid_cap vid_cap;
443 struct vb2_alloc_ctx *alloc_ctx;
447 * fimc_ctx - the device context data
449 * @lock: mutex protecting this data structure
450 * @s_frame: source frame properties
451 * @d_frame: destination frame properties
452 * @out_order_1p: output 1-plane YCBCR order
453 * @out_order_2p: output 2-plane YCBCR order
454 * @in_order_1p input 1-plane YCBCR order
455 * @in_order_2p: input 2-plane YCBCR order
456 * @in_path: input mode (DMA or camera)
457 * @out_path: output mode (DMA or FIFO)
458 * @scaler: image scaler properties
459 * @effect: image effect
460 * @rotation: image clockwise rotation in degrees
461 * @flip: image flip mode
462 * @flags: additional flags for image conversion
463 * @state: flags to keep track of user configuration
464 * @fimc_dev: the FIMC device this context applies to
465 * @m2m_ctx: memory-to-memory device context
469 struct fimc_frame s_frame;
470 struct fimc_frame d_frame;
475 enum fimc_datapath in_path;
476 enum fimc_datapath out_path;
477 struct fimc_scaler scaler;
478 struct fimc_effect effect;
483 struct fimc_dev *fimc_dev;
484 struct v4l2_m2m_ctx *m2m_ctx;
487 static inline int tiled_fmt(struct fimc_fmt *fmt)
489 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
492 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
494 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
495 cfg |= S5P_CIGCTRL_IRQ_CLR;
496 writel(cfg, dev->regs + S5P_CIGCTRL);
499 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
501 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
503 cfg |= S5P_CISCCTRL_SCALERSTART;
505 cfg &= ~S5P_CISCCTRL_SCALERSTART;
506 writel(cfg, dev->regs + S5P_CISCCTRL);
509 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
511 u32 cfg = readl(dev->regs + S5P_MSCTRL);
513 cfg |= S5P_MSCTRL_ENVID;
515 cfg &= ~S5P_MSCTRL_ENVID;
516 writel(cfg, dev->regs + S5P_MSCTRL);
519 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
521 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
522 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
523 writel(cfg, dev->regs + S5P_CIIMGCPT);
527 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
528 * @mask: each bit corresponds to one of 32 output buffer registers set
529 * 1 to include buffer in the sequence, 0 to disable
531 * This function mask output DMA ring buffers, i.e. it allows to configure
532 * which of the output buffer address registers will be used by the DMA
535 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
537 writel(mask, dev->regs + S5P_CIFCNTSEQ);
540 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
541 enum v4l2_buf_type type)
543 struct fimc_frame *frame;
545 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
546 if (ctx->state & FIMC_CTX_M2M)
547 frame = &ctx->s_frame;
549 return ERR_PTR(-EINVAL);
550 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
551 frame = &ctx->d_frame;
553 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
554 "Wrong buffer/video queue type (%d)\n", type);
555 return ERR_PTR(-EINVAL);
561 /* Return an index to the buffer actually being written. */
562 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
566 if (dev->variant->has_cistatus2) {
567 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
568 return reg > 0 ? --reg : reg;
570 reg = readl(dev->regs + S5P_CISTATUS);
571 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
572 S5P_CISTATUS_FRAMECNT_SHIFT;
576 /* -----------------------------------------------------*/
578 void fimc_hw_reset(struct fimc_dev *fimc);
579 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
580 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
581 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
582 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
583 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
584 void fimc_hw_set_scaler(struct fimc_ctx *ctx);
585 void fimc_hw_en_capture(struct fimc_ctx *ctx);
586 void fimc_hw_set_effect(struct fimc_ctx *ctx);
587 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
588 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
589 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
590 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
591 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
593 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
594 struct s5p_fimc_isp_info *cam);
595 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
596 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
597 struct s5p_fimc_isp_info *cam);
598 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
599 struct s5p_fimc_isp_info *cam);
601 /* -----------------------------------------------------*/
603 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
604 struct v4l2_fmtdesc *f);
605 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
606 struct v4l2_format *f);
607 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
608 struct v4l2_format *f);
609 int fimc_vidioc_queryctrl(struct file *file, void *priv,
610 struct v4l2_queryctrl *qc);
611 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
612 struct v4l2_control *ctrl);
614 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
615 int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
616 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
618 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
619 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
622 int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f);
623 int fimc_set_scaler_info(struct fimc_ctx *ctx);
624 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
625 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
626 struct fimc_frame *frame, struct fimc_addr *paddr);
628 /* -----------------------------------------------------*/
630 int fimc_register_capture_device(struct fimc_dev *fimc);
631 void fimc_unregister_capture_device(struct fimc_dev *fimc);
632 int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
633 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
634 struct fimc_vid_buffer *fimc_vb);
636 /* Locking: the caller holds fimc->slock */
637 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
639 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
640 fimc_hw_en_capture(ctx);
643 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
645 fimc_hw_en_lastirq(fimc, true);
646 fimc_hw_dis_capture(fimc);
647 fimc_hw_enable_scaler(fimc, false);
648 fimc_hw_en_lastirq(fimc, false);
652 * Add buf to the capture active buffers queue.
653 * Locking: Need to be called with fimc_dev::slock held.
655 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
656 struct fimc_vid_buffer *buf)
658 list_add_tail(&buf->list, &vid_cap->active_buf_q);
659 vid_cap->active_buf_cnt++;
663 * Pop a video buffer from the capture active buffers queue
664 * Locking: Need to be called with fimc_dev::slock held.
666 static inline struct fimc_vid_buffer *
667 active_queue_pop(struct fimc_vid_cap *vid_cap)
669 struct fimc_vid_buffer *buf;
670 buf = list_entry(vid_cap->active_buf_q.next,
671 struct fimc_vid_buffer, list);
672 list_del(&buf->list);
673 vid_cap->active_buf_cnt--;
677 /* Add video buffer to the capture pending buffers queue */
678 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
679 struct fimc_vid_buffer *buf)
681 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
684 /* Add video buffer to the capture pending buffers queue */
685 static inline struct fimc_vid_buffer *
686 pending_queue_pop(struct fimc_vid_cap *vid_cap)
688 struct fimc_vid_buffer *buf;
689 buf = list_entry(vid_cap->pending_buf_q.next,
690 struct fimc_vid_buffer, list);
691 list_del(&buf->list);
695 #endif /* FIMC_CORE_H_ */