2 * S5P camera interface (video postprocessor) driver
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd
6 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published
10 * by the Free Software Foundation, either version 2 of the License,
11 * or (at your option) any later version.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/version.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/bug.h>
20 #include <linux/interrupt.h>
21 #include <linux/device.h>
22 #include <linux/platform_device.h>
23 #include <linux/list.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <media/v4l2-ioctl.h>
28 #include <media/videobuf2-core.h>
29 #include <media/videobuf2-dma-contig.h>
31 #include "fimc-core.h"
33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
34 "sclk_fimc", "fimc", "sclk_cam"
37 static struct fimc_fmt fimc_formats[] = {
40 .fourcc = V4L2_PIX_FMT_RGB565X,
42 .color = S5P_FIMC_RGB565,
45 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_BE,
46 .flags = FMT_FLAGS_M2M,
49 .fourcc = V4L2_PIX_FMT_BGR666,
51 .color = S5P_FIMC_RGB666,
54 .flags = FMT_FLAGS_M2M,
56 .name = "XRGB-8-8-8-8, 32 bpp",
57 .fourcc = V4L2_PIX_FMT_RGB32,
59 .color = S5P_FIMC_RGB888,
62 .flags = FMT_FLAGS_M2M,
64 .name = "YUV 4:2:2 packed, YCbYCr",
65 .fourcc = V4L2_PIX_FMT_YUYV,
67 .color = S5P_FIMC_YCBYCR422,
70 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
71 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
73 .name = "YUV 4:2:2 packed, CbYCrY",
74 .fourcc = V4L2_PIX_FMT_UYVY,
76 .color = S5P_FIMC_CBYCRY422,
79 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
80 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
82 .name = "YUV 4:2:2 packed, CrYCbY",
83 .fourcc = V4L2_PIX_FMT_VYUY,
85 .color = S5P_FIMC_CRYCBY422,
88 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
89 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
91 .name = "YUV 4:2:2 packed, YCrYCb",
92 .fourcc = V4L2_PIX_FMT_YVYU,
94 .color = S5P_FIMC_YCRYCB422,
97 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
98 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
100 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
101 .fourcc = V4L2_PIX_FMT_YUV422P,
103 .color = S5P_FIMC_YCBYCR422,
106 .flags = FMT_FLAGS_M2M,
108 .name = "YUV 4:2:2 planar, Y/CbCr",
109 .fourcc = V4L2_PIX_FMT_NV16,
111 .color = S5P_FIMC_YCBYCR422,
114 .flags = FMT_FLAGS_M2M,
116 .name = "YUV 4:2:2 planar, Y/CrCb",
117 .fourcc = V4L2_PIX_FMT_NV61,
119 .color = S5P_FIMC_YCRYCB422,
122 .flags = FMT_FLAGS_M2M,
124 .name = "YUV 4:2:0 planar, YCbCr",
125 .fourcc = V4L2_PIX_FMT_YUV420,
127 .color = S5P_FIMC_YCBCR420,
130 .flags = FMT_FLAGS_M2M,
132 .name = "YUV 4:2:0 planar, Y/CbCr",
133 .fourcc = V4L2_PIX_FMT_NV12,
135 .color = S5P_FIMC_YCBCR420,
138 .flags = FMT_FLAGS_M2M,
140 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
141 .fourcc = V4L2_PIX_FMT_NV12M,
142 .color = S5P_FIMC_YCBCR420,
146 .flags = FMT_FLAGS_M2M,
148 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
149 .fourcc = V4L2_PIX_FMT_YUV420M,
150 .color = S5P_FIMC_YCBCR420,
151 .depth = { 8, 2, 2 },
154 .flags = FMT_FLAGS_M2M,
156 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
157 .fourcc = V4L2_PIX_FMT_NV12MT,
158 .color = S5P_FIMC_YCBCR420,
162 .flags = FMT_FLAGS_M2M,
166 static struct v4l2_queryctrl fimc_ctrls[] = {
168 .id = V4L2_CID_HFLIP,
169 .type = V4L2_CTRL_TYPE_BOOLEAN,
170 .name = "Horizontal flip",
175 .id = V4L2_CID_VFLIP,
176 .type = V4L2_CTRL_TYPE_BOOLEAN,
177 .name = "Vertical flip",
182 .id = V4L2_CID_ROTATE,
183 .type = V4L2_CTRL_TYPE_INTEGER,
184 .name = "Rotation (CCW)",
193 static struct v4l2_queryctrl *get_ctrl(int id)
197 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
198 if (id == fimc_ctrls[i].id)
199 return &fimc_ctrls[i];
203 int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f)
205 if (r->width > f->width) {
206 if (f->width > (r->width * SCALER_MAX_HRATIO))
209 if ((f->width * SCALER_MAX_HRATIO) < r->width)
213 if (r->height > f->height) {
214 if (f->height > (r->height * SCALER_MAX_VRATIO))
217 if ((f->height * SCALER_MAX_VRATIO) < r->height)
224 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
233 if (src >= tar * tmp) {
234 *shift = sh, *ratio = tmp;
239 *shift = 0, *ratio = 1;
241 dbg("s: %d, t: %d, shift: %d, ratio: %d",
242 src, tar, *shift, *ratio);
246 int fimc_set_scaler_info(struct fimc_ctx *ctx)
248 struct fimc_scaler *sc = &ctx->scaler;
249 struct fimc_frame *s_frame = &ctx->s_frame;
250 struct fimc_frame *d_frame = &ctx->d_frame;
254 if (ctx->rotation == 90 || ctx->rotation == 270) {
256 tx = d_frame->height;
259 ty = d_frame->height;
261 if (tx <= 0 || ty <= 0) {
262 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
263 "invalid target size: %d x %d", tx, ty);
268 sy = s_frame->height;
269 if (sx <= 0 || sy <= 0) {
270 err("invalid source size: %d x %d", sx, sy);
275 sc->real_height = sy;
276 dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
278 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
282 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
286 sc->pre_dst_width = sx / sc->pre_hratio;
287 sc->pre_dst_height = sy / sc->pre_vratio;
289 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
290 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
292 sc->scaleup_h = (tx >= sx) ? 1 : 0;
293 sc->scaleup_v = (ty >= sy) ? 1 : 0;
295 /* check to see if input and output size/format differ */
296 if (s_frame->fmt->color == d_frame->fmt->color
297 && s_frame->width == d_frame->width
298 && s_frame->height == d_frame->height)
306 static void fimc_capture_handler(struct fimc_dev *fimc)
308 struct fimc_vid_cap *cap = &fimc->vid_cap;
309 struct fimc_vid_buffer *v_buf = NULL;
311 if (!list_empty(&cap->active_buf_q)) {
312 v_buf = active_queue_pop(cap);
313 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
316 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
317 wake_up(&fimc->irq_queue);
321 if (!list_empty(&cap->pending_buf_q)) {
323 v_buf = pending_queue_pop(cap);
324 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
325 v_buf->index = cap->buf_index;
327 dbg("hw ptr: %d, sw ptr: %d",
328 fimc_hw_get_frame_index(fimc), cap->buf_index);
330 /* Move the buffer to the capture active queue */
331 active_queue_add(cap, v_buf);
333 dbg("next frame: %d, done frame: %d",
334 fimc_hw_get_frame_index(fimc), v_buf->index);
336 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
339 } else if (test_and_clear_bit(ST_CAPT_STREAM, &fimc->state) &&
340 cap->active_buf_cnt <= 1) {
341 fimc_deactivate_capture(fimc);
344 dbg("frame: %d, active_buf_cnt= %d",
345 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
348 static irqreturn_t fimc_isr(int irq, void *priv)
350 struct fimc_dev *fimc = priv;
353 fimc_hw_clear_irq(fimc);
355 spin_lock(&fimc->slock);
357 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
358 struct vb2_buffer *src_vb, *dst_vb;
359 struct fimc_ctx *ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
361 if (!ctx || !ctx->m2m_ctx)
364 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
365 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
366 if (src_vb && dst_vb) {
367 v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
368 v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
369 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
375 if (test_bit(ST_CAPT_RUN, &fimc->state))
376 fimc_capture_handler(fimc);
378 if (test_and_clear_bit(ST_CAPT_PEND, &fimc->state)) {
379 set_bit(ST_CAPT_RUN, &fimc->state);
380 wake_up(&fimc->irq_queue);
384 spin_unlock(&fimc->slock);
388 /* The color format (colplanes, memplanes) must be already configured. */
389 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
390 struct fimc_frame *frame, struct fimc_addr *paddr)
395 if (vb == NULL || frame == NULL)
398 pix_size = frame->width * frame->height;
400 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
401 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
403 paddr->y = vb2_dma_contig_plane_paddr(vb, 0);
405 if (frame->fmt->memplanes == 1) {
406 switch (frame->fmt->colplanes) {
412 /* decompose Y into Y/Cb */
413 paddr->cb = (u32)(paddr->y + pix_size);
417 paddr->cb = (u32)(paddr->y + pix_size);
418 /* decompose Y into Y/Cb/Cr */
419 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
420 paddr->cr = (u32)(paddr->cb
423 paddr->cr = (u32)(paddr->cb
430 if (frame->fmt->memplanes >= 2)
431 paddr->cb = vb2_dma_contig_plane_paddr(vb, 1);
433 if (frame->fmt->memplanes == 3)
434 paddr->cr = vb2_dma_contig_plane_paddr(vb, 2);
437 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
438 paddr->y, paddr->cb, paddr->cr, ret);
443 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
444 static void fimc_set_yuv_order(struct fimc_ctx *ctx)
446 /* The one only mode supported in SoC. */
447 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
448 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
450 /* Set order for 1 plane input formats. */
451 switch (ctx->s_frame.fmt->color) {
452 case S5P_FIMC_YCRYCB422:
453 ctx->in_order_1p = S5P_FIMC_IN_YCRYCB;
455 case S5P_FIMC_CBYCRY422:
456 ctx->in_order_1p = S5P_FIMC_IN_CBYCRY;
458 case S5P_FIMC_CRYCBY422:
459 ctx->in_order_1p = S5P_FIMC_IN_CRYCBY;
461 case S5P_FIMC_YCBYCR422:
463 ctx->in_order_1p = S5P_FIMC_IN_YCBYCR;
466 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
468 switch (ctx->d_frame.fmt->color) {
469 case S5P_FIMC_YCRYCB422:
470 ctx->out_order_1p = S5P_FIMC_OUT_YCRYCB;
472 case S5P_FIMC_CBYCRY422:
473 ctx->out_order_1p = S5P_FIMC_OUT_CBYCRY;
475 case S5P_FIMC_CRYCBY422:
476 ctx->out_order_1p = S5P_FIMC_OUT_CRYCBY;
478 case S5P_FIMC_YCBYCR422:
480 ctx->out_order_1p = S5P_FIMC_OUT_YCBYCR;
483 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
486 static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
488 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
491 for (i = 0; i < f->fmt->colplanes; i++)
492 depth += f->fmt->depth[i];
494 f->dma_offset.y_h = f->offs_h;
495 if (!variant->pix_hoff)
496 f->dma_offset.y_h *= (depth >> 3);
498 f->dma_offset.y_v = f->offs_v;
500 f->dma_offset.cb_h = f->offs_h;
501 f->dma_offset.cb_v = f->offs_v;
503 f->dma_offset.cr_h = f->offs_h;
504 f->dma_offset.cr_v = f->offs_v;
506 if (!variant->pix_hoff) {
507 if (f->fmt->colplanes == 3) {
508 f->dma_offset.cb_h >>= 1;
509 f->dma_offset.cr_h >>= 1;
511 if (f->fmt->color == S5P_FIMC_YCBCR420) {
512 f->dma_offset.cb_v >>= 1;
513 f->dma_offset.cr_v >>= 1;
517 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
518 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
522 * fimc_prepare_config - check dimensions, operation and color mode
523 * and pre-calculate offset and the scaling coefficients.
525 * @ctx: hardware context information
526 * @flags: flags indicating which parameters to check/update
528 * Return: 0 if dimensions are valid or non zero otherwise.
530 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
532 struct fimc_frame *s_frame, *d_frame;
533 struct vb2_buffer *vb = NULL;
536 s_frame = &ctx->s_frame;
537 d_frame = &ctx->d_frame;
539 if (flags & FIMC_PARAMS) {
540 /* Prepare the DMA offset ratios for scaler. */
541 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
542 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
544 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
545 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
546 err("out of scaler range");
549 fimc_set_yuv_order(ctx);
552 /* Input DMA mode is not allowed when the scaler is disabled. */
553 ctx->scaler.enabled = 1;
555 if (flags & FIMC_SRC_ADDR) {
556 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
557 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
562 if (flags & FIMC_DST_ADDR) {
563 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
564 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
570 static void fimc_dma_run(void *priv)
572 struct fimc_ctx *ctx = priv;
573 struct fimc_dev *fimc;
577 if (WARN(!ctx, "null hardware context\n"))
580 fimc = ctx->fimc_dev;
582 spin_lock_irqsave(&ctx->slock, flags);
583 set_bit(ST_M2M_PEND, &fimc->state);
585 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
586 ret = fimc_prepare_config(ctx, ctx->state);
588 err("Wrong parameters");
591 /* Reconfigure hardware if the context has changed. */
592 if (fimc->m2m.ctx != ctx) {
593 ctx->state |= FIMC_PARAMS;
597 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
599 if (ctx->state & FIMC_PARAMS) {
600 fimc_hw_set_input_path(ctx);
601 fimc_hw_set_in_dma(ctx);
602 if (fimc_set_scaler_info(ctx)) {
603 err("Scaler setup error");
606 fimc_hw_set_scaler(ctx);
607 fimc_hw_set_target_format(ctx);
608 fimc_hw_set_rotation(ctx);
609 fimc_hw_set_effect(ctx);
612 fimc_hw_set_output_path(ctx);
613 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
614 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
616 if (ctx->state & FIMC_PARAMS)
617 fimc_hw_set_out_dma(ctx);
619 fimc_activate_capture(ctx);
621 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
622 FIMC_SRC_FMT | FIMC_DST_FMT);
623 fimc_hw_activate_input_dma(fimc, true);
626 spin_unlock_irqrestore(&ctx->slock, flags);
629 static void fimc_job_abort(void *priv)
631 /* Nothing done in job_abort. */
634 static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
635 unsigned int *num_planes, unsigned long sizes[],
638 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
639 struct fimc_frame *f;
642 f = ctx_get_frame(ctx, vq->type);
647 * Return number of non-contigous planes (plane buffers)
648 * depending on the configured color format.
651 *num_planes = f->fmt->memplanes;
653 for (i = 0; i < f->fmt->memplanes; i++) {
654 sizes[i] = (f->width * f->height * f->fmt->depth[i]) >> 3;
655 allocators[i] = ctx->fimc_dev->alloc_ctx;
658 if (*num_buffers == 0)
664 static int fimc_buf_prepare(struct vb2_buffer *vb)
666 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
667 struct fimc_frame *frame;
670 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
672 return PTR_ERR(frame);
674 for (i = 0; i < frame->fmt->memplanes; i++)
675 vb2_set_plane_payload(vb, i, frame->payload[i]);
680 static void fimc_buf_queue(struct vb2_buffer *vb)
682 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
684 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
687 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
690 static void fimc_lock(struct vb2_queue *vq)
692 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
693 mutex_lock(&ctx->fimc_dev->lock);
696 static void fimc_unlock(struct vb2_queue *vq)
698 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
699 mutex_unlock(&ctx->fimc_dev->lock);
702 struct vb2_ops fimc_qops = {
703 .queue_setup = fimc_queue_setup,
704 .buf_prepare = fimc_buf_prepare,
705 .buf_queue = fimc_buf_queue,
706 .wait_prepare = fimc_unlock,
707 .wait_finish = fimc_lock,
710 static int fimc_m2m_querycap(struct file *file, void *priv,
711 struct v4l2_capability *cap)
713 struct fimc_ctx *ctx = file->private_data;
714 struct fimc_dev *fimc = ctx->fimc_dev;
716 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
717 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
718 cap->bus_info[0] = 0;
719 cap->version = KERNEL_VERSION(1, 0, 0);
720 cap->capabilities = V4L2_CAP_STREAMING |
721 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
722 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
727 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
728 struct v4l2_fmtdesc *f)
730 struct fimc_fmt *fmt;
732 if (f->index >= ARRAY_SIZE(fimc_formats))
735 fmt = &fimc_formats[f->index];
736 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
737 f->pixelformat = fmt->fourcc;
742 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
743 struct v4l2_format *f)
745 struct fimc_ctx *ctx = priv;
746 struct fimc_frame *frame;
748 frame = ctx_get_frame(ctx, f->type);
750 return PTR_ERR(frame);
752 f->fmt.pix.width = frame->width;
753 f->fmt.pix.height = frame->height;
754 f->fmt.pix.field = V4L2_FIELD_NONE;
755 f->fmt.pix.pixelformat = frame->fmt->fourcc;
760 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
762 struct fimc_fmt *fmt;
765 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
766 fmt = &fimc_formats[i];
767 if (fmt->fourcc == f->fmt.pix.pixelformat &&
772 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
775 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
778 struct fimc_fmt *fmt;
781 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
782 fmt = &fimc_formats[i];
783 if (fmt->mbus_code == f->code && (fmt->flags & mask))
787 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
791 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
792 struct v4l2_format *f)
794 struct fimc_ctx *ctx = priv;
795 struct fimc_dev *fimc = ctx->fimc_dev;
796 struct samsung_fimc_variant *variant = fimc->variant;
797 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
798 struct fimc_fmt *fmt;
799 u32 max_width, mod_x, mod_y, mask;
800 int i, is_output = 0;
803 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
804 if (ctx->state & FIMC_CTX_CAP)
807 } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
811 dbg("w: %d, h: %d", pix->width, pix->height);
813 mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
814 fmt = find_format(f, mask);
816 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
821 if (pix->field == V4L2_FIELD_ANY)
822 pix->field = V4L2_FIELD_NONE;
823 else if (V4L2_FIELD_NONE != pix->field)
827 max_width = variant->pix_limit->scaler_dis_w;
828 mod_x = ffs(variant->min_inp_pixsize) - 1;
830 max_width = variant->pix_limit->out_rot_dis_w;
831 mod_x = ffs(variant->min_out_pixsize) - 1;
834 if (tiled_fmt(fmt)) {
835 mod_x = 6; /* 64 x 32 pixels tile */
838 if (fimc->id == 1 && variant->pix_hoff)
839 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
844 dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
846 v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
847 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
849 pix->num_planes = fmt->memplanes;
851 for (i = 0; i < pix->num_planes; ++i) {
852 int bpl = pix->plane_fmt[i].bytesperline;
854 dbg("[%d] bpl: %d, depth: %d, w: %d, h: %d",
855 i, bpl, fmt->depth[i], pix->width, pix->height);
857 if (!bpl || (bpl * 8 / fmt->depth[i]) > pix->width)
858 bpl = (pix->width * fmt->depth[0]) >> 3;
860 if (!pix->plane_fmt[i].sizeimage)
861 pix->plane_fmt[i].sizeimage = pix->height * bpl;
863 pix->plane_fmt[i].bytesperline = bpl;
865 dbg("[%d]: bpl: %d, sizeimage: %d",
866 i, pix->plane_fmt[i].bytesperline,
867 pix->plane_fmt[i].sizeimage);
873 static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
874 struct v4l2_format *f)
876 struct fimc_ctx *ctx = priv;
877 struct fimc_dev *fimc = ctx->fimc_dev;
878 struct vb2_queue *vq;
879 struct fimc_frame *frame;
880 struct v4l2_pix_format_mplane *pix;
885 ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
889 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
891 if (vb2_is_streaming(vq)) {
892 v4l2_err(&fimc->m2m.v4l2_dev, "queue (%d) busy\n", f->type);
896 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
897 frame = &ctx->s_frame;
898 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
899 frame = &ctx->d_frame;
901 v4l2_err(&fimc->m2m.v4l2_dev,
902 "Wrong buffer/video queue type (%d)\n", f->type);
906 pix = &f->fmt.pix_mp;
907 frame->fmt = find_format(f, FMT_FLAGS_M2M);
911 for (i = 0; i < frame->fmt->colplanes; i++)
912 frame->payload[i] = pix->plane_fmt[i].bytesperline * pix->height;
914 frame->f_width = pix->plane_fmt[0].bytesperline * 8 /
915 frame->fmt->depth[0];
916 frame->f_height = pix->height;
917 frame->width = pix->width;
918 frame->height = pix->height;
919 frame->o_width = pix->width;
920 frame->o_height = pix->height;
924 spin_lock_irqsave(&ctx->slock, flags);
925 tmp = (frame == &ctx->d_frame) ? FIMC_DST_FMT : FIMC_SRC_FMT;
926 ctx->state |= FIMC_PARAMS | tmp;
927 spin_unlock_irqrestore(&ctx->slock, flags);
929 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
934 static int fimc_m2m_reqbufs(struct file *file, void *priv,
935 struct v4l2_requestbuffers *reqbufs)
937 struct fimc_ctx *ctx = priv;
938 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
941 static int fimc_m2m_querybuf(struct file *file, void *priv,
942 struct v4l2_buffer *buf)
944 struct fimc_ctx *ctx = priv;
945 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
948 static int fimc_m2m_qbuf(struct file *file, void *priv,
949 struct v4l2_buffer *buf)
951 struct fimc_ctx *ctx = priv;
953 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
956 static int fimc_m2m_dqbuf(struct file *file, void *priv,
957 struct v4l2_buffer *buf)
959 struct fimc_ctx *ctx = priv;
960 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
963 static int fimc_m2m_streamon(struct file *file, void *priv,
964 enum v4l2_buf_type type)
966 struct fimc_ctx *ctx = priv;
968 /* The source and target color format need to be set */
969 if (V4L2_TYPE_IS_OUTPUT(type)) {
970 if (~ctx->state & FIMC_SRC_FMT)
972 } else if (~ctx->state & FIMC_DST_FMT) {
976 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
979 static int fimc_m2m_streamoff(struct file *file, void *priv,
980 enum v4l2_buf_type type)
982 struct fimc_ctx *ctx = priv;
983 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
986 int fimc_vidioc_queryctrl(struct file *file, void *priv,
987 struct v4l2_queryctrl *qc)
989 struct fimc_ctx *ctx = priv;
990 struct v4l2_queryctrl *c;
993 c = get_ctrl(qc->id);
999 if (ctx->state & FIMC_CTX_CAP) {
1000 return v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
1001 core, queryctrl, qc);
1006 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
1007 struct v4l2_control *ctrl)
1009 struct fimc_ctx *ctx = priv;
1010 struct fimc_dev *fimc = ctx->fimc_dev;
1013 case V4L2_CID_HFLIP:
1014 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1016 case V4L2_CID_VFLIP:
1017 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1019 case V4L2_CID_ROTATE:
1020 ctrl->value = ctx->rotation;
1023 if (ctx->state & FIMC_CTX_CAP) {
1024 return v4l2_subdev_call(fimc->vid_cap.sd, core,
1027 v4l2_err(&fimc->m2m.v4l2_dev,
1028 "Invalid control\n");
1032 dbg("ctrl->value= %d", ctrl->value);
1037 int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1039 struct v4l2_queryctrl *c;
1040 c = get_ctrl(ctrl->id);
1044 if (ctrl->value < c->minimum || ctrl->value > c->maximum
1045 || (c->step != 0 && ctrl->value % c->step != 0)) {
1046 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1047 "Invalid control value\n");
1054 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1056 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
1057 struct fimc_dev *fimc = ctx->fimc_dev;
1058 unsigned long flags;
1060 spin_lock_irqsave(&ctx->slock, flags);
1063 case V4L2_CID_HFLIP:
1065 ctx->flip |= FLIP_X_AXIS;
1067 ctx->flip &= ~FLIP_X_AXIS;
1070 case V4L2_CID_VFLIP:
1072 ctx->flip |= FLIP_Y_AXIS;
1074 ctx->flip &= ~FLIP_Y_AXIS;
1077 case V4L2_CID_ROTATE:
1078 /* Check for the output rotator availability */
1079 if ((ctrl->value == 90 || ctrl->value == 270) &&
1080 (ctx->in_path == FIMC_DMA && !variant->has_out_rot)) {
1081 spin_unlock_irqrestore(&ctx->slock, flags);
1084 ctx->rotation = ctrl->value;
1089 spin_unlock_irqrestore(&ctx->slock, flags);
1090 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1093 ctx->state |= FIMC_PARAMS;
1094 spin_unlock_irqrestore(&ctx->slock, flags);
1099 static int fimc_m2m_s_ctrl(struct file *file, void *priv,
1100 struct v4l2_control *ctrl)
1102 struct fimc_ctx *ctx = priv;
1105 ret = check_ctrl_val(ctx, ctrl);
1109 ret = fimc_s_ctrl(ctx, ctrl);
1113 static int fimc_m2m_cropcap(struct file *file, void *fh,
1114 struct v4l2_cropcap *cr)
1116 struct fimc_frame *frame;
1117 struct fimc_ctx *ctx = fh;
1119 frame = ctx_get_frame(ctx, cr->type);
1121 return PTR_ERR(frame);
1123 cr->bounds.left = 0;
1125 cr->bounds.width = frame->f_width;
1126 cr->bounds.height = frame->f_height;
1127 cr->defrect = cr->bounds;
1132 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1134 struct fimc_frame *frame;
1135 struct fimc_ctx *ctx = file->private_data;
1137 frame = ctx_get_frame(ctx, cr->type);
1139 return PTR_ERR(frame);
1141 cr->c.left = frame->offs_h;
1142 cr->c.top = frame->offs_v;
1143 cr->c.width = frame->width;
1144 cr->c.height = frame->height;
1149 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1151 struct fimc_dev *fimc = ctx->fimc_dev;
1152 struct fimc_frame *f;
1153 u32 min_size, halign, depth = 0;
1156 if (cr->c.top < 0 || cr->c.left < 0) {
1157 v4l2_err(&fimc->m2m.v4l2_dev,
1158 "doesn't support negative values for top & left\n");
1162 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1163 f = (ctx->state & FIMC_CTX_CAP) ? &ctx->s_frame : &ctx->d_frame;
1164 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
1165 ctx->state & FIMC_CTX_M2M)
1170 min_size = (f == &ctx->s_frame) ?
1171 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1173 if (ctx->state & FIMC_CTX_M2M) {
1174 if (fimc->id == 1 && fimc->variant->pix_hoff)
1175 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1177 halign = ffs(min_size) - 1;
1178 /* there are more strict aligment requirements at camera interface */
1184 for (i = 0; i < f->fmt->colplanes; i++)
1185 depth += f->fmt->depth[i];
1187 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1189 &cr->c.height, min_size, f->o_height,
1190 halign, 64/(ALIGN(depth, 8)));
1192 /* adjust left/top if cropping rectangle is out of bounds */
1193 if (cr->c.left + cr->c.width > f->o_width)
1194 cr->c.left = f->o_width - cr->c.width;
1195 if (cr->c.top + cr->c.height > f->o_height)
1196 cr->c.top = f->o_height - cr->c.height;
1198 cr->c.left = round_down(cr->c.left, min_size);
1199 cr->c.top = round_down(cr->c.top,
1200 ctx->state & FIMC_CTX_M2M ? 8 : 16);
1202 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1203 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1204 f->f_width, f->f_height);
1210 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1212 struct fimc_ctx *ctx = file->private_data;
1213 struct fimc_dev *fimc = ctx->fimc_dev;
1214 unsigned long flags;
1215 struct fimc_frame *f;
1218 ret = fimc_try_crop(ctx, cr);
1222 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1223 &ctx->s_frame : &ctx->d_frame;
1225 spin_lock_irqsave(&ctx->slock, flags);
1226 if (~ctx->state & (FIMC_SRC_FMT | FIMC_DST_FMT)) {
1227 /* Check to see if scaling ratio is within supported range */
1228 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1229 ret = fimc_check_scaler_ratio(&cr->c, &ctx->d_frame);
1231 ret = fimc_check_scaler_ratio(&cr->c, &ctx->s_frame);
1233 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range");
1234 spin_unlock_irqrestore(&ctx->slock, flags);
1238 ctx->state |= FIMC_PARAMS;
1240 f->offs_h = cr->c.left;
1241 f->offs_v = cr->c.top;
1242 f->width = cr->c.width;
1243 f->height = cr->c.height;
1245 spin_unlock_irqrestore(&ctx->slock, flags);
1249 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1250 .vidioc_querycap = fimc_m2m_querycap,
1252 .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
1253 .vidioc_enum_fmt_vid_out_mplane = fimc_vidioc_enum_fmt_mplane,
1255 .vidioc_g_fmt_vid_cap_mplane = fimc_vidioc_g_fmt_mplane,
1256 .vidioc_g_fmt_vid_out_mplane = fimc_vidioc_g_fmt_mplane,
1258 .vidioc_try_fmt_vid_cap_mplane = fimc_vidioc_try_fmt_mplane,
1259 .vidioc_try_fmt_vid_out_mplane = fimc_vidioc_try_fmt_mplane,
1261 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1262 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
1264 .vidioc_reqbufs = fimc_m2m_reqbufs,
1265 .vidioc_querybuf = fimc_m2m_querybuf,
1267 .vidioc_qbuf = fimc_m2m_qbuf,
1268 .vidioc_dqbuf = fimc_m2m_dqbuf,
1270 .vidioc_streamon = fimc_m2m_streamon,
1271 .vidioc_streamoff = fimc_m2m_streamoff,
1273 .vidioc_queryctrl = fimc_vidioc_queryctrl,
1274 .vidioc_g_ctrl = fimc_vidioc_g_ctrl,
1275 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1277 .vidioc_g_crop = fimc_m2m_g_crop,
1278 .vidioc_s_crop = fimc_m2m_s_crop,
1279 .vidioc_cropcap = fimc_m2m_cropcap
1283 static int queue_init(void *priv, struct vb2_queue *src_vq,
1284 struct vb2_queue *dst_vq)
1286 struct fimc_ctx *ctx = priv;
1289 memset(src_vq, 0, sizeof(*src_vq));
1290 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1291 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1292 src_vq->drv_priv = ctx;
1293 src_vq->ops = &fimc_qops;
1294 src_vq->mem_ops = &vb2_dma_contig_memops;
1295 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1297 ret = vb2_queue_init(src_vq);
1301 memset(dst_vq, 0, sizeof(*dst_vq));
1302 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1303 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1304 dst_vq->drv_priv = ctx;
1305 dst_vq->ops = &fimc_qops;
1306 dst_vq->mem_ops = &vb2_dma_contig_memops;
1307 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1309 return vb2_queue_init(dst_vq);
1312 static int fimc_m2m_open(struct file *file)
1314 struct fimc_dev *fimc = video_drvdata(file);
1315 struct fimc_ctx *ctx = NULL;
1317 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1318 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1321 * Return if the corresponding video capture node
1322 * is already opened.
1324 if (fimc->vid_cap.refcnt > 0)
1328 set_bit(ST_OUTDMA_RUN, &fimc->state);
1330 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1334 file->private_data = ctx;
1335 ctx->fimc_dev = fimc;
1336 /* Default color format */
1337 ctx->s_frame.fmt = &fimc_formats[0];
1338 ctx->d_frame.fmt = &fimc_formats[0];
1339 /* Setup the device context for mem2mem mode. */
1340 ctx->state = FIMC_CTX_M2M;
1342 ctx->in_path = FIMC_DMA;
1343 ctx->out_path = FIMC_DMA;
1344 spin_lock_init(&ctx->slock);
1346 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1347 if (IS_ERR(ctx->m2m_ctx)) {
1348 int err = PTR_ERR(ctx->m2m_ctx);
1356 static int fimc_m2m_release(struct file *file)
1358 struct fimc_ctx *ctx = file->private_data;
1359 struct fimc_dev *fimc = ctx->fimc_dev;
1361 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1362 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1364 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1366 if (--fimc->m2m.refcnt <= 0)
1367 clear_bit(ST_OUTDMA_RUN, &fimc->state);
1372 static unsigned int fimc_m2m_poll(struct file *file,
1373 struct poll_table_struct *wait)
1375 struct fimc_ctx *ctx = file->private_data;
1377 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1381 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1383 struct fimc_ctx *ctx = file->private_data;
1385 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1388 static const struct v4l2_file_operations fimc_m2m_fops = {
1389 .owner = THIS_MODULE,
1390 .open = fimc_m2m_open,
1391 .release = fimc_m2m_release,
1392 .poll = fimc_m2m_poll,
1393 .unlocked_ioctl = video_ioctl2,
1394 .mmap = fimc_m2m_mmap,
1397 static struct v4l2_m2m_ops m2m_ops = {
1398 .device_run = fimc_dma_run,
1399 .job_abort = fimc_job_abort,
1402 static int fimc_register_m2m_device(struct fimc_dev *fimc)
1404 struct video_device *vfd;
1405 struct platform_device *pdev;
1406 struct v4l2_device *v4l2_dev;
1413 v4l2_dev = &fimc->m2m.v4l2_dev;
1415 /* set name if it is empty */
1416 if (!v4l2_dev->name[0])
1417 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1418 "%s.m2m", dev_name(&pdev->dev));
1420 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1424 vfd = video_device_alloc();
1426 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1430 vfd->fops = &fimc_m2m_fops;
1431 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1433 vfd->release = video_device_release;
1434 vfd->lock = &fimc->lock;
1436 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1438 video_set_drvdata(vfd, fimc);
1439 platform_set_drvdata(pdev, fimc);
1441 fimc->m2m.vfd = vfd;
1442 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1443 if (IS_ERR(fimc->m2m.m2m_dev)) {
1444 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1445 ret = PTR_ERR(fimc->m2m.m2m_dev);
1449 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1452 "%s(): failed to register video device\n", __func__);
1456 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1461 v4l2_m2m_release(fimc->m2m.m2m_dev);
1463 video_device_release(fimc->m2m.vfd);
1465 v4l2_device_unregister(v4l2_dev);
1470 static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1473 v4l2_m2m_release(fimc->m2m.m2m_dev);
1474 video_unregister_device(fimc->m2m.vfd);
1476 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1480 static void fimc_clk_release(struct fimc_dev *fimc)
1483 for (i = 0; i < fimc->num_clocks; i++) {
1484 if (fimc->clock[i]) {
1485 clk_disable(fimc->clock[i]);
1486 clk_put(fimc->clock[i]);
1491 static int fimc_clk_get(struct fimc_dev *fimc)
1494 for (i = 0; i < fimc->num_clocks; i++) {
1495 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1497 if (!IS_ERR_OR_NULL(fimc->clock[i])) {
1498 clk_enable(fimc->clock[i]);
1501 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1508 static int fimc_probe(struct platform_device *pdev)
1510 struct fimc_dev *fimc;
1511 struct resource *res;
1512 struct samsung_fimc_driverdata *drv_data;
1514 int cap_input_index = -1;
1516 dev_dbg(&pdev->dev, "%s():\n", __func__);
1518 drv_data = (struct samsung_fimc_driverdata *)
1519 platform_get_device_id(pdev)->driver_data;
1521 if (pdev->id >= drv_data->num_entities) {
1522 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1527 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1531 fimc->id = pdev->id;
1532 fimc->variant = drv_data->variant[fimc->id];
1534 fimc->pdata = pdev->dev.platform_data;
1535 fimc->state = ST_IDLE;
1537 init_waitqueue_head(&fimc->irq_queue);
1538 spin_lock_init(&fimc->slock);
1540 mutex_init(&fimc->lock);
1542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1544 dev_err(&pdev->dev, "failed to find the registers\n");
1549 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1550 dev_name(&pdev->dev));
1551 if (!fimc->regs_res) {
1552 dev_err(&pdev->dev, "failed to obtain register region\n");
1557 fimc->regs = ioremap(res->start, resource_size(res));
1559 dev_err(&pdev->dev, "failed to map registers\n");
1561 goto err_req_region;
1564 fimc->num_clocks = MAX_FIMC_CLOCKS - 1;
1566 * Check if vide capture node needs to be registered for this device
1571 for (i = 0; i < FIMC_MAX_CAMIF_CLIENTS; ++i)
1572 if (fimc->pdata->isp_info[i])
1574 if (i < FIMC_MAX_CAMIF_CLIENTS) {
1575 cap_input_index = i;
1580 ret = fimc_clk_get(fimc);
1582 goto err_regs_unmap;
1583 clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1585 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1587 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1591 fimc->irq = res->start;
1593 fimc_hw_reset(fimc);
1595 ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1597 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1601 /* Initialize contiguous memory allocator */
1602 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&fimc->pdev->dev);
1603 if (IS_ERR(fimc->alloc_ctx)) {
1604 ret = PTR_ERR(fimc->alloc_ctx);
1608 ret = fimc_register_m2m_device(fimc);
1612 /* At least one camera sensor is required to register capture node */
1613 if (cap_input_index >= 0) {
1614 ret = fimc_register_capture_device(fimc);
1617 clk_disable(fimc->clock[CLK_CAM]);
1620 * Exclude the additional output DMA address registers by masking
1621 * them out on HW revisions that provide extended capabilites.
1623 if (fimc->variant->out_buf_count > 4)
1624 fimc_hw_set_dma_seq(fimc, 0xF);
1626 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1627 __func__, fimc->id);
1632 fimc_unregister_m2m_device(fimc);
1634 free_irq(fimc->irq, fimc);
1636 fimc_clk_release(fimc);
1638 iounmap(fimc->regs);
1640 release_resource(fimc->regs_res);
1641 kfree(fimc->regs_res);
1648 static int __devexit fimc_remove(struct platform_device *pdev)
1650 struct fimc_dev *fimc =
1651 (struct fimc_dev *)platform_get_drvdata(pdev);
1653 free_irq(fimc->irq, fimc);
1654 fimc_hw_reset(fimc);
1656 fimc_unregister_m2m_device(fimc);
1657 fimc_unregister_capture_device(fimc);
1659 fimc_clk_release(fimc);
1661 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1663 iounmap(fimc->regs);
1664 release_resource(fimc->regs_res);
1665 kfree(fimc->regs_res);
1668 dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
1672 /* Image pixel limits, similar across several FIMC HW revisions. */
1673 static struct fimc_pix_limit s5p_pix_limit[3] = {
1675 .scaler_en_w = 3264,
1676 .scaler_dis_w = 8192,
1677 .in_rot_en_h = 1920,
1678 .in_rot_dis_w = 8192,
1679 .out_rot_en_w = 1920,
1680 .out_rot_dis_w = 4224,
1683 .scaler_en_w = 4224,
1684 .scaler_dis_w = 8192,
1685 .in_rot_en_h = 1920,
1686 .in_rot_dis_w = 8192,
1687 .out_rot_en_w = 1920,
1688 .out_rot_dis_w = 4224,
1691 .scaler_en_w = 1920,
1692 .scaler_dis_w = 8192,
1693 .in_rot_en_h = 1280,
1694 .in_rot_dis_w = 8192,
1695 .out_rot_en_w = 1280,
1696 .out_rot_dis_w = 1920,
1700 static struct samsung_fimc_variant fimc0_variant_s5p = {
1703 .min_inp_pixsize = 16,
1704 .min_out_pixsize = 16,
1705 .hor_offs_align = 8,
1707 .pix_limit = &s5p_pix_limit[0],
1710 static struct samsung_fimc_variant fimc2_variant_s5p = {
1711 .min_inp_pixsize = 16,
1712 .min_out_pixsize = 16,
1713 .hor_offs_align = 8,
1715 .pix_limit = &s5p_pix_limit[1],
1718 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1722 .min_inp_pixsize = 16,
1723 .min_out_pixsize = 16,
1724 .hor_offs_align = 8,
1726 .pix_limit = &s5p_pix_limit[1],
1729 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1733 .min_inp_pixsize = 16,
1734 .min_out_pixsize = 16,
1735 .hor_offs_align = 1,
1737 .pix_limit = &s5p_pix_limit[2],
1740 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1742 .min_inp_pixsize = 16,
1743 .min_out_pixsize = 16,
1744 .hor_offs_align = 8,
1746 .pix_limit = &s5p_pix_limit[2],
1749 static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
1754 .min_inp_pixsize = 16,
1755 .min_out_pixsize = 16,
1756 .hor_offs_align = 1,
1757 .out_buf_count = 32,
1758 .pix_limit = &s5p_pix_limit[1],
1761 static struct samsung_fimc_variant fimc2_variant_s5pv310 = {
1764 .min_inp_pixsize = 16,
1765 .min_out_pixsize = 16,
1766 .hor_offs_align = 1,
1767 .out_buf_count = 32,
1768 .pix_limit = &s5p_pix_limit[2],
1772 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1774 [0] = &fimc0_variant_s5p,
1775 [1] = &fimc0_variant_s5p,
1776 [2] = &fimc2_variant_s5p,
1779 .lclk_frequency = 133000000UL,
1782 /* S5PV210, S5PC110 */
1783 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1785 [0] = &fimc0_variant_s5pv210,
1786 [1] = &fimc1_variant_s5pv210,
1787 [2] = &fimc2_variant_s5pv210,
1790 .lclk_frequency = 166000000UL,
1793 /* S5PV310, S5PC210 */
1794 static struct samsung_fimc_driverdata fimc_drvdata_s5pv310 = {
1796 [0] = &fimc0_variant_s5pv310,
1797 [1] = &fimc0_variant_s5pv310,
1798 [2] = &fimc0_variant_s5pv310,
1799 [3] = &fimc2_variant_s5pv310,
1802 .lclk_frequency = 166000000UL,
1805 static struct platform_device_id fimc_driver_ids[] = {
1808 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1810 .name = "s5pv210-fimc",
1811 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
1813 .name = "s5pv310-fimc",
1814 .driver_data = (unsigned long)&fimc_drvdata_s5pv310,
1818 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1820 static struct platform_driver fimc_driver = {
1821 .probe = fimc_probe,
1822 .remove = __devexit_p(fimc_remove),
1823 .id_table = fimc_driver_ids,
1825 .name = MODULE_NAME,
1826 .owner = THIS_MODULE,
1830 static int __init fimc_init(void)
1832 int ret = platform_driver_register(&fimc_driver);
1834 err("platform_driver_register failed: %d\n", ret);
1838 static void __exit fimc_exit(void)
1840 platform_driver_unregister(&fimc_driver);
1843 module_init(fimc_init);
1844 module_exit(fimc_exit);
1846 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1847 MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
1848 MODULE_LICENSE("GPL");