Pileus Git - ~andy/linux/blob - drivers/media/video/s5p-fimc/fimc-core.c

   1 /*
   2  * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
   3  *
   4  * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
   5  * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published
   9  * by the Free Software Foundation, either version 2 of the License,
  10  * or (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/errno.h>
  17 #include <linux/bug.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/list.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/clk.h>
  26 #include <media/v4l2-ioctl.h>
  27 #include <media/videobuf2-core.h>
  28 #include <media/videobuf2-dma-contig.h>
  29
  30 #include "fimc-core.h"
  31 #include "fimc-mdevice.h"
  32
  33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  34         "sclk_fimc", "fimc"
  35 };
  36
  37 static struct fimc_fmt fimc_formats[] = {
  38         {
  39                 .name           = "RGB565",
  40                 .fourcc         = V4L2_PIX_FMT_RGB565X,
  41                 .depth          = { 16 },
  42                 .color          = S5P_FIMC_RGB565,
  43                 .memplanes      = 1,
  44                 .colplanes      = 1,
  45                 .flags          = FMT_FLAGS_M2M,
  46         }, {
  47                 .name           = "BGR666",
  48                 .fourcc         = V4L2_PIX_FMT_BGR666,
  49                 .depth          = { 32 },
  50                 .color          = S5P_FIMC_RGB666,
  51                 .memplanes      = 1,
  52                 .colplanes      = 1,
  53                 .flags          = FMT_FLAGS_M2M,
  54         }, {
  55                 .name           = "XRGB-8-8-8-8, 32 bpp",
  56                 .fourcc         = V4L2_PIX_FMT_RGB32,
  57                 .depth          = { 32 },
  58                 .color          = S5P_FIMC_RGB888,
  59                 .memplanes      = 1,
  60                 .colplanes      = 1,
  61                 .flags          = FMT_FLAGS_M2M,
  62         }, {
  63                 .name           = "YUV 4:2:2 packed, YCbYCr",
  64                 .fourcc         = V4L2_PIX_FMT_YUYV,
  65                 .depth          = { 16 },
  66                 .color          = S5P_FIMC_YCBYCR422,
  67                 .memplanes      = 1,
  68                 .colplanes      = 1,
  69                 .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
  70                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  71         }, {
  72                 .name           = "YUV 4:2:2 packed, CbYCrY",
  73                 .fourcc         = V4L2_PIX_FMT_UYVY,
  74                 .depth          = { 16 },
  75                 .color          = S5P_FIMC_CBYCRY422,
  76                 .memplanes      = 1,
  77                 .colplanes      = 1,
  78                 .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
  79                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  80         }, {
  81                 .name           = "YUV 4:2:2 packed, CrYCbY",
  82                 .fourcc         = V4L2_PIX_FMT_VYUY,
  83                 .depth          = { 16 },
  84                 .color          = S5P_FIMC_CRYCBY422,
  85                 .memplanes      = 1,
  86                 .colplanes      = 1,
  87                 .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
  88                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  89         }, {
  90                 .name           = "YUV 4:2:2 packed, YCrYCb",
  91                 .fourcc         = V4L2_PIX_FMT_YVYU,
  92                 .depth          = { 16 },
  93                 .color          = S5P_FIMC_YCRYCB422,
  94                 .memplanes      = 1,
  95                 .colplanes      = 1,
  96                 .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
  97                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  98         }, {
  99                 .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
 100                 .fourcc         = V4L2_PIX_FMT_YUV422P,
 101                 .depth          = { 12 },
 102                 .color          = S5P_FIMC_YCBYCR422,
 103                 .memplanes      = 1,
 104                 .colplanes      = 3,
 105                 .flags          = FMT_FLAGS_M2M,
 106         }, {
 107                 .name           = "YUV 4:2:2 planar, Y/CbCr",
 108                 .fourcc         = V4L2_PIX_FMT_NV16,
 109                 .depth          = { 16 },
 110                 .color          = S5P_FIMC_YCBYCR422,
 111                 .memplanes      = 1,
 112                 .colplanes      = 2,
 113                 .flags          = FMT_FLAGS_M2M,
 114         }, {
 115                 .name           = "YUV 4:2:2 planar, Y/CrCb",
 116                 .fourcc         = V4L2_PIX_FMT_NV61,
 117                 .depth          = { 16 },
 118                 .color          = S5P_FIMC_YCRYCB422,
 119                 .memplanes      = 1,
 120                 .colplanes      = 2,
 121                 .flags          = FMT_FLAGS_M2M,
 122         }, {
 123                 .name           = "YUV 4:2:0 planar, YCbCr",
 124                 .fourcc         = V4L2_PIX_FMT_YUV420,
 125                 .depth          = { 12 },
 126                 .color          = S5P_FIMC_YCBCR420,
 127                 .memplanes      = 1,
 128                 .colplanes      = 3,
 129                 .flags          = FMT_FLAGS_M2M,
 130         }, {
 131                 .name           = "YUV 4:2:0 planar, Y/CbCr",
 132                 .fourcc         = V4L2_PIX_FMT_NV12,
 133                 .depth          = { 12 },
 134                 .color          = S5P_FIMC_YCBCR420,
 135                 .memplanes      = 1,
 136                 .colplanes      = 2,
 137                 .flags          = FMT_FLAGS_M2M,
 138         }, {
 139                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
 140                 .fourcc         = V4L2_PIX_FMT_NV12M,
 141                 .color          = S5P_FIMC_YCBCR420,
 142                 .depth          = { 8, 4 },
 143                 .memplanes      = 2,
 144                 .colplanes      = 2,
 145                 .flags          = FMT_FLAGS_M2M,
 146         }, {
 147                 .name           = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
 148                 .fourcc         = V4L2_PIX_FMT_YUV420M,
 149                 .color          = S5P_FIMC_YCBCR420,
 150                 .depth          = { 8, 2, 2 },
 151                 .memplanes      = 3,
 152                 .colplanes      = 3,
 153                 .flags          = FMT_FLAGS_M2M,
 154         }, {
 155                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
 156                 .fourcc         = V4L2_PIX_FMT_NV12MT,
 157                 .color          = S5P_FIMC_YCBCR420,
 158                 .depth          = { 8, 4 },
 159                 .memplanes      = 2,
 160                 .colplanes      = 2,
 161                 .flags          = FMT_FLAGS_M2M,
 162         },
 163 };
 164
 165 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
 166 {
 167         int tx, ty;
 168
 169         if (rot == 90 || rot == 270) {
 170                 ty = dw;
 171                 tx = dh;
 172         } else {
 173                 tx = dw;
 174                 ty = dh;
 175         }
 176
 177         if ((sw >= SCALER_MAX_HRATIO * tx) || (sh >= SCALER_MAX_VRATIO * ty))
 178                 return -EINVAL;
 179
 180         return 0;
 181 }
 182
 183 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 184 {
 185         u32 sh = 6;
 186
 187         if (src >= 64 * tar)
 188                 return -EINVAL;
 189
 190         while (sh--) {
 191                 u32 tmp = 1 << sh;
 192                 if (src >= tar * tmp) {
 193                         *shift = sh, *ratio = tmp;
 194                         return 0;
 195                 }
 196         }
 197         *shift = 0, *ratio = 1;
 198         return 0;
 199 }
 200
 201 int fimc_set_scaler_info(struct fimc_ctx *ctx)
 202 {
 203         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 204         struct device *dev = &ctx->fimc_dev->pdev->dev;
 205         struct fimc_scaler *sc = &ctx->scaler;
 206         struct fimc_frame *s_frame = &ctx->s_frame;
 207         struct fimc_frame *d_frame = &ctx->d_frame;
 208         int tx, ty, sx, sy;
 209         int ret;
 210
 211         if (ctx->rotation == 90 || ctx->rotation == 270) {
 212                 ty = d_frame->width;
 213                 tx = d_frame->height;
 214         } else {
 215                 tx = d_frame->width;
 216                 ty = d_frame->height;
 217         }
 218         if (tx <= 0 || ty <= 0) {
 219                 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
 220                 return -EINVAL;
 221         }
 222
 223         sx = s_frame->width;
 224         sy = s_frame->height;
 225         if (sx <= 0 || sy <= 0) {
 226                 dev_err(dev, "Invalid source size: %dx%d", sx, sy);
 227                 return -EINVAL;
 228         }
 229         sc->real_width = sx;
 230         sc->real_height = sy;
 231
 232         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 233         if (ret)
 234                 return ret;
 235
 236         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 237         if (ret)
 238                 return ret;
 239
 240         sc->pre_dst_width = sx / sc->pre_hratio;
 241         sc->pre_dst_height = sy / sc->pre_vratio;
 242
 243         if (variant->has_mainscaler_ext) {
 244                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 245                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 246         } else {
 247                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 248                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 249
 250         }
 251
 252         sc->scaleup_h = (tx >= sx) ? 1 : 0;
 253         sc->scaleup_v = (ty >= sy) ? 1 : 0;
 254
 255         /* check to see if input and output size/format differ */
 256         if (s_frame->fmt->color == d_frame->fmt->color
 257                 && s_frame->width == d_frame->width
 258                 && s_frame->height == d_frame->height)
 259                 sc->copy_mode = 1;
 260         else
 261                 sc->copy_mode = 0;
 262
 263         return 0;
 264 }
 265
 266 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
 267 {
 268         struct vb2_buffer *src_vb, *dst_vb;
 269
 270         if (!ctx || !ctx->m2m_ctx)
 271                 return;
 272
 273         src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
 274         dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
 275
 276         if (src_vb && dst_vb) {
 277                 v4l2_m2m_buf_done(src_vb, vb_state);
 278                 v4l2_m2m_buf_done(dst_vb, vb_state);
 279                 v4l2_m2m_job_finish(ctx->fimc_dev->m2m.m2m_dev,
 280                                     ctx->m2m_ctx);
 281         }
 282 }
 283
 284 /* Complete the transaction which has been scheduled for execution. */
 285 static int fimc_m2m_shutdown(struct fimc_ctx *ctx)
 286 {
 287         struct fimc_dev *fimc = ctx->fimc_dev;
 288         int ret;
 289
 290         if (!fimc_m2m_pending(fimc))
 291                 return 0;
 292
 293         fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
 294
 295         ret = wait_event_timeout(fimc->irq_queue,
 296                            !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
 297                            FIMC_SHUTDOWN_TIMEOUT);
 298
 299         return ret == 0 ? -ETIMEDOUT : ret;
 300 }
 301
 302 static int start_streaming(struct vb2_queue *q, unsigned int count)
 303 {
 304         struct fimc_ctx *ctx = q->drv_priv;
 305         int ret;
 306
 307         ret = pm_runtime_get_sync(&ctx->fimc_dev->pdev->dev);
 308         return ret > 0 ? 0 : ret;
 309 }
 310
 311 static int stop_streaming(struct vb2_queue *q)
 312 {
 313         struct fimc_ctx *ctx = q->drv_priv;
 314         int ret;
 315
 316         ret = fimc_m2m_shutdown(ctx);
 317         if (ret == -ETIMEDOUT)
 318                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 319
 320         pm_runtime_put(&ctx->fimc_dev->pdev->dev);
 321         return 0;
 322 }
 323
 324 static void fimc_capture_irq_handler(struct fimc_dev *fimc)
 325 {
 326         struct fimc_vid_cap *cap = &fimc->vid_cap;
 327         struct fimc_vid_buffer *v_buf;
 328         struct timeval *tv;
 329         struct timespec ts;
 330
 331         if (!list_empty(&cap->active_buf_q) &&
 332             test_bit(ST_CAPT_RUN, &fimc->state)) {
 333                 ktime_get_real_ts(&ts);
 334
 335                 v_buf = active_queue_pop(cap);
 336
 337                 tv = &v_buf->vb.v4l2_buf.timestamp;
 338                 tv->tv_sec = ts.tv_sec;
 339                 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
 340                 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
 341
 342                 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
 343         }
 344
 345         if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
 346                 wake_up(&fimc->irq_queue);
 347                 return;
 348         }
 349
 350         if (!list_empty(&cap->pending_buf_q)) {
 351
 352                 v_buf = pending_queue_pop(cap);
 353                 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
 354                 v_buf->index = cap->buf_index;
 355
 356                 /* Move the buffer to the capture active queue */
 357                 active_queue_add(cap, v_buf);
 358
 359                 dbg("next frame: %d, done frame: %d",
 360                     fimc_hw_get_frame_index(fimc), v_buf->index);
 361
 362                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 363                         cap->buf_index = 0;
 364         }
 365
 366         if (cap->active_buf_cnt == 0) {
 367                 clear_bit(ST_CAPT_RUN, &fimc->state);
 368
 369                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 370                         cap->buf_index = 0;
 371         } else {
 372                 set_bit(ST_CAPT_RUN, &fimc->state);
 373         }
 374
 375         dbg("frame: %d, active_buf_cnt: %d",
 376             fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
 377 }
 378
 379 static irqreturn_t fimc_irq_handler(int irq, void *priv)
 380 {
 381         struct fimc_dev *fimc = priv;
 382         struct fimc_vid_cap *cap = &fimc->vid_cap;
 383         struct fimc_ctx *ctx;
 384
 385         fimc_hw_clear_irq(fimc);
 386
 387         spin_lock(&fimc->slock);
 388
 389         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 390                 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
 391                         set_bit(ST_M2M_SUSPENDED, &fimc->state);
 392                         wake_up(&fimc->irq_queue);
 393                         goto out;
 394                 }
 395                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 396                 if (ctx != NULL) {
 397                         spin_unlock(&fimc->slock);
 398                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 399
 400                         spin_lock(&ctx->slock);
 401                         if (ctx->state & FIMC_CTX_SHUT) {
 402                                 ctx->state &= ~FIMC_CTX_SHUT;
 403                                 wake_up(&fimc->irq_queue);
 404                         }
 405                         spin_unlock(&ctx->slock);
 406                 }
 407                 return IRQ_HANDLED;
 408         } else {
 409                 if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 410                         fimc_capture_irq_handler(fimc);
 411
 412                         if (cap->active_buf_cnt == 1) {
 413                                 fimc_deactivate_capture(fimc);
 414                                 clear_bit(ST_CAPT_STREAM, &fimc->state);
 415                         }
 416                 }
 417         }
 418 out:
 419         spin_unlock(&fimc->slock);
 420         return IRQ_HANDLED;
 421 }
 422
 423 /* The color format (colplanes, memplanes) must be already configured. */
 424 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 425                       struct fimc_frame *frame, struct fimc_addr *paddr)
 426 {
 427         int ret = 0;
 428         u32 pix_size;
 429
 430         if (vb == NULL || frame == NULL)
 431                 return -EINVAL;
 432
 433         pix_size = frame->width * frame->height;
 434
 435         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 436                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 437
 438         paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
 439
 440         if (frame->fmt->memplanes == 1) {
 441                 switch (frame->fmt->colplanes) {
 442                 case 1:
 443                         paddr->cb = 0;
 444                         paddr->cr = 0;
 445                         break;
 446                 case 2:
 447                         /* decompose Y into Y/Cb */
 448                         paddr->cb = (u32)(paddr->y + pix_size);
 449                         paddr->cr = 0;
 450                         break;
 451                 case 3:
 452                         paddr->cb = (u32)(paddr->y + pix_size);
 453                         /* decompose Y into Y/Cb/Cr */
 454                         if (S5P_FIMC_YCBCR420 == frame->fmt->color)
 455                                 paddr->cr = (u32)(paddr->cb
 456                                                 + (pix_size >> 2));
 457                         else /* 422 */
 458                                 paddr->cr = (u32)(paddr->cb
 459                                                 + (pix_size >> 1));
 460                         break;
 461                 default:
 462                         return -EINVAL;
 463                 }
 464         } else {
 465                 if (frame->fmt->memplanes >= 2)
 466                         paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
 467
 468                 if (frame->fmt->memplanes == 3)
 469                         paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
 470         }
 471
 472         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 473             paddr->y, paddr->cb, paddr->cr, ret);
 474
 475         return ret;
 476 }
 477
 478 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 479 void fimc_set_yuv_order(struct fimc_ctx *ctx)
 480 {
 481         /* The one only mode supported in SoC. */
 482         ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
 483         ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
 484
 485         /* Set order for 1 plane input formats. */
 486         switch (ctx->s_frame.fmt->color) {
 487         case S5P_FIMC_YCRYCB422:
 488                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
 489                 break;
 490         case S5P_FIMC_CBYCRY422:
 491                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
 492                 break;
 493         case S5P_FIMC_CRYCBY422:
 494                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
 495                 break;
 496         case S5P_FIMC_YCBYCR422:
 497         default:
 498                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
 499                 break;
 500         }
 501         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 502
 503         switch (ctx->d_frame.fmt->color) {
 504         case S5P_FIMC_YCRYCB422:
 505                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
 506                 break;
 507         case S5P_FIMC_CBYCRY422:
 508                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
 509                 break;
 510         case S5P_FIMC_CRYCBY422:
 511                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
 512                 break;
 513         case S5P_FIMC_YCBYCR422:
 514         default:
 515                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
 516                 break;
 517         }
 518         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 519 }
 520
 521 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 522 {
 523         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 524         u32 i, depth = 0;
 525
 526         for (i = 0; i < f->fmt->colplanes; i++)
 527                 depth += f->fmt->depth[i];
 528
 529         f->dma_offset.y_h = f->offs_h;
 530         if (!variant->pix_hoff)
 531                 f->dma_offset.y_h *= (depth >> 3);
 532
 533         f->dma_offset.y_v = f->offs_v;
 534
 535         f->dma_offset.cb_h = f->offs_h;
 536         f->dma_offset.cb_v = f->offs_v;
 537
 538         f->dma_offset.cr_h = f->offs_h;
 539         f->dma_offset.cr_v = f->offs_v;
 540
 541         if (!variant->pix_hoff) {
 542                 if (f->fmt->colplanes == 3) {
 543                         f->dma_offset.cb_h >>= 1;
 544                         f->dma_offset.cr_h >>= 1;
 545                 }
 546                 if (f->fmt->color == S5P_FIMC_YCBCR420) {
 547                         f->dma_offset.cb_v >>= 1;
 548                         f->dma_offset.cr_v >>= 1;
 549                 }
 550         }
 551
 552         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 553             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 554 }
 555
 556 /**
 557  * fimc_prepare_config - check dimensions, operation and color mode
 558  *                       and pre-calculate offset and the scaling coefficients.
 559  *
 560  * @ctx: hardware context information
 561  * @flags: flags indicating which parameters to check/update
 562  *
 563  * Return: 0 if dimensions are valid or non zero otherwise.
 564  */
 565 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
 566 {
 567         struct fimc_frame *s_frame, *d_frame;
 568         struct vb2_buffer *vb = NULL;
 569         int ret = 0;
 570
 571         s_frame = &ctx->s_frame;
 572         d_frame = &ctx->d_frame;
 573
 574         if (flags & FIMC_PARAMS) {
 575                 /* Prepare the DMA offset ratios for scaler. */
 576                 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
 577                 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
 578
 579                 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
 580                     s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
 581                         err("out of scaler range");
 582                         return -EINVAL;
 583                 }
 584                 fimc_set_yuv_order(ctx);
 585         }
 586
 587         /* Input DMA mode is not allowed when the scaler is disabled. */
 588         ctx->scaler.enabled = 1;
 589
 590         if (flags & FIMC_SRC_ADDR) {
 591                 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
 592                 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
 593                 if (ret)
 594                         return ret;
 595         }
 596
 597         if (flags & FIMC_DST_ADDR) {
 598                 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
 599                 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
 600         }
 601
 602         return ret;
 603 }
 604
 605 static void fimc_dma_run(void *priv)
 606 {
 607         struct fimc_ctx *ctx = priv;
 608         struct fimc_dev *fimc;
 609         unsigned long flags;
 610         u32 ret;
 611
 612         if (WARN(!ctx, "null hardware context\n"))
 613                 return;
 614
 615         fimc = ctx->fimc_dev;
 616         spin_lock_irqsave(&fimc->slock, flags);
 617         set_bit(ST_M2M_PEND, &fimc->state);
 618
 619         spin_lock(&ctx->slock);
 620         ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
 621         ret = fimc_prepare_config(ctx, ctx->state);
 622         if (ret)
 623                 goto dma_unlock;
 624
 625         /* Reconfigure hardware if the context has changed. */
 626         if (fimc->m2m.ctx != ctx) {
 627                 ctx->state |= FIMC_PARAMS;
 628                 fimc->m2m.ctx = ctx;
 629         }
 630         fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
 631
 632         if (ctx->state & FIMC_PARAMS) {
 633                 fimc_hw_set_input_path(ctx);
 634                 fimc_hw_set_in_dma(ctx);
 635                 ret = fimc_set_scaler_info(ctx);
 636                 if (ret) {
 637                         spin_unlock(&fimc->slock);
 638                         goto dma_unlock;
 639                 }
 640                 fimc_hw_set_prescaler(ctx);
 641                 fimc_hw_set_mainscaler(ctx);
 642                 fimc_hw_set_target_format(ctx);
 643                 fimc_hw_set_rotation(ctx);
 644                 fimc_hw_set_effect(ctx);
 645         }
 646
 647         fimc_hw_set_output_path(ctx);
 648         if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
 649                 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
 650
 651         if (ctx->state & FIMC_PARAMS)
 652                 fimc_hw_set_out_dma(ctx);
 653
 654         fimc_activate_capture(ctx);
 655
 656         ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
 657                        FIMC_SRC_FMT | FIMC_DST_FMT);
 658         fimc_hw_activate_input_dma(fimc, true);
 659 dma_unlock:
 660         spin_unlock(&ctx->slock);
 661         spin_unlock_irqrestore(&fimc->slock, flags);
 662 }
 663
 664 static void fimc_job_abort(void *priv)
 665 {
 666         fimc_m2m_shutdown(priv);
 667 }
 668
 669 static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
 670                             unsigned int *num_planes, unsigned int sizes[],
 671                             void *allocators[])
 672 {
 673         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 674         struct fimc_frame *f;
 675         int i;
 676
 677         f = ctx_get_frame(ctx, vq->type);
 678         if (IS_ERR(f))
 679                 return PTR_ERR(f);
 680         /*
 681          * Return number of non-contigous planes (plane buffers)
 682          * depending on the configured color format.
 683          */
 684         if (!f->fmt)
 685                 return -EINVAL;
 686
 687         *num_planes = f->fmt->memplanes;
 688         for (i = 0; i < f->fmt->memplanes; i++) {
 689                 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
 690                 allocators[i] = ctx->fimc_dev->alloc_ctx;
 691         }
 692         return 0;
 693 }
 694
 695 static int fimc_buf_prepare(struct vb2_buffer *vb)
 696 {
 697         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 698         struct fimc_frame *frame;
 699         int i;
 700
 701         frame = ctx_get_frame(ctx, vb->vb2_queue->type);
 702         if (IS_ERR(frame))
 703                 return PTR_ERR(frame);
 704
 705         for (i = 0; i < frame->fmt->memplanes; i++)
 706                 vb2_set_plane_payload(vb, i, frame->payload[i]);
 707
 708         return 0;
 709 }
 710
 711 static void fimc_buf_queue(struct vb2_buffer *vb)
 712 {
 713         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 714
 715         dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
 716
 717         if (ctx->m2m_ctx)
 718                 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
 719 }
 720
 721 static void fimc_lock(struct vb2_queue *vq)
 722 {
 723         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 724         mutex_lock(&ctx->fimc_dev->lock);
 725 }
 726
 727 static void fimc_unlock(struct vb2_queue *vq)
 728 {
 729         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 730         mutex_unlock(&ctx->fimc_dev->lock);
 731 }
 732
 733 static struct vb2_ops fimc_qops = {
 734         .queue_setup     = fimc_queue_setup,
 735         .buf_prepare     = fimc_buf_prepare,
 736         .buf_queue       = fimc_buf_queue,
 737         .wait_prepare    = fimc_unlock,
 738         .wait_finish     = fimc_lock,
 739         .stop_streaming  = stop_streaming,
 740         .start_streaming = start_streaming,
 741 };
 742
 743 /*
 744  * V4L2 controls handling
 745  */
 746 #define ctrl_to_ctx(__ctrl) \
 747         container_of((__ctrl)->handler, struct fimc_ctx, ctrl_handler)
 748
 749 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
 750 {
 751         struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
 752         struct fimc_dev *fimc = ctx->fimc_dev;
 753         struct samsung_fimc_variant *variant = fimc->variant;
 754         unsigned long flags;
 755         int ret = 0;
 756
 757         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
 758                 return 0;
 759
 760         switch (ctrl->id) {
 761         case V4L2_CID_HFLIP:
 762                 spin_lock_irqsave(&ctx->slock, flags);
 763                 ctx->hflip = ctrl->val;
 764                 break;
 765
 766         case V4L2_CID_VFLIP:
 767                 spin_lock_irqsave(&ctx->slock, flags);
 768                 ctx->vflip = ctrl->val;
 769                 break;
 770
 771         case V4L2_CID_ROTATE:
 772                 if (fimc_capture_pending(fimc) ||
 773                     fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
 774                         ret = fimc_check_scaler_ratio(ctx->s_frame.width,
 775                                         ctx->s_frame.height, ctx->d_frame.width,
 776                                         ctx->d_frame.height, ctrl->val);
 777                 }
 778                 if (ret) {
 779                         v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
 780                         return -EINVAL;
 781                 }
 782                 if ((ctrl->val == 90 || ctrl->val == 270) &&
 783                     !variant->has_out_rot)
 784                         return -EINVAL;
 785                 spin_lock_irqsave(&ctx->slock, flags);
 786                 ctx->rotation = ctrl->val;
 787                 break;
 788
 789         default:
 790                 v4l2_err(fimc->v4l2_dev, "Invalid control: 0x%X\n", ctrl->id);
 791                 return -EINVAL;
 792         }
 793         ctx->state |= FIMC_PARAMS;
 794         set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
 795         spin_unlock_irqrestore(&ctx->slock, flags);
 796         return 0;
 797 }
 798
 799 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
 800         .s_ctrl = fimc_s_ctrl,
 801 };
 802
 803 int fimc_ctrls_create(struct fimc_ctx *ctx)
 804 {
 805         if (ctx->ctrls_rdy)
 806                 return 0;
 807         v4l2_ctrl_handler_init(&ctx->ctrl_handler, 3);
 808
 809         ctx->ctrl_rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 810                                      V4L2_CID_HFLIP, 0, 1, 1, 0);
 811         ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 812                                     V4L2_CID_VFLIP, 0, 1, 1, 0);
 813         ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 814                                     V4L2_CID_ROTATE, 0, 270, 90, 0);
 815         ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
 816
 817         return ctx->ctrl_handler.error;
 818 }
 819
 820 void fimc_ctrls_delete(struct fimc_ctx *ctx)
 821 {
 822         if (ctx->ctrls_rdy) {
 823                 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
 824                 ctx->ctrls_rdy = false;
 825         }
 826 }
 827
 828 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
 829 {
 830         if (!ctx->ctrls_rdy)
 831                 return;
 832
 833         mutex_lock(&ctx->ctrl_handler.lock);
 834         v4l2_ctrl_activate(ctx->ctrl_rotate, active);
 835         v4l2_ctrl_activate(ctx->ctrl_hflip, active);
 836         v4l2_ctrl_activate(ctx->ctrl_vflip, active);
 837
 838         if (active) {
 839                 ctx->rotation = ctx->ctrl_rotate->val;
 840                 ctx->hflip    = ctx->ctrl_hflip->val;
 841                 ctx->vflip    = ctx->ctrl_vflip->val;
 842         } else {
 843                 ctx->rotation = 0;
 844                 ctx->hflip    = 0;
 845                 ctx->vflip    = 0;
 846         }
 847         mutex_unlock(&ctx->ctrl_handler.lock);
 848 }
 849
 850 /*
 851  * V4L2 ioctl handlers
 852  */
 853 static int fimc_m2m_querycap(struct file *file, void *fh,
 854                              struct v4l2_capability *cap)
 855 {
 856         struct fimc_ctx *ctx = fh_to_ctx(fh);
 857         struct fimc_dev *fimc = ctx->fimc_dev;
 858
 859         strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
 860         strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
 861         cap->bus_info[0] = 0;
 862         cap->capabilities = V4L2_CAP_STREAMING |
 863                 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
 864                 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
 865
 866         return 0;
 867 }
 868
 869 static int fimc_m2m_enum_fmt_mplane(struct file *file, void *priv,
 870                                     struct v4l2_fmtdesc *f)
 871 {
 872         struct fimc_fmt *fmt;
 873
 874         fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_M2M, f->index);
 875         if (!fmt)
 876                 return -EINVAL;
 877
 878         strncpy(f->description, fmt->name, sizeof(f->description) - 1);
 879         f->pixelformat = fmt->fourcc;
 880         return 0;
 881 }
 882
 883 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f)
 884 {
 885         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 886         int i;
 887
 888         pixm->width = frame->o_width;
 889         pixm->height = frame->o_height;
 890         pixm->field = V4L2_FIELD_NONE;
 891         pixm->pixelformat = frame->fmt->fourcc;
 892         pixm->colorspace = V4L2_COLORSPACE_JPEG;
 893         pixm->num_planes = frame->fmt->memplanes;
 894
 895         for (i = 0; i < pixm->num_planes; ++i) {
 896                 int bpl = frame->f_width;
 897                 if (frame->fmt->colplanes == 1) /* packed formats */
 898                         bpl = (bpl * frame->fmt->depth[0]) / 8;
 899                 pixm->plane_fmt[i].bytesperline = bpl;
 900                 pixm->plane_fmt[i].sizeimage = (frame->o_width *
 901                         frame->o_height * frame->fmt->depth[i]) / 8;
 902         }
 903         return 0;
 904 }
 905
 906 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f)
 907 {
 908         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 909
 910         frame->f_width  = pixm->plane_fmt[0].bytesperline;
 911         if (frame->fmt->colplanes == 1)
 912                 frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0];
 913         frame->f_height = pixm->height;
 914         frame->width    = pixm->width;
 915         frame->height   = pixm->height;
 916         frame->o_width  = pixm->width;
 917         frame->o_height = pixm->height;
 918         frame->offs_h   = 0;
 919         frame->offs_v   = 0;
 920 }
 921
 922 /**
 923  * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
 924  * @fmt: fimc pixel format description (input)
 925  * @width: requested pixel width
 926  * @height: requested pixel height
 927  * @pix: multi-plane format to adjust
 928  */
 929 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
 930                                struct v4l2_pix_format_mplane *pix)
 931 {
 932         u32 bytesperline = 0;
 933         int i;
 934
 935         pix->colorspace = V4L2_COLORSPACE_JPEG;
 936         pix->field = V4L2_FIELD_NONE;
 937         pix->num_planes = fmt->memplanes;
 938         pix->height = height;
 939         pix->width = width;
 940
 941         for (i = 0; i < pix->num_planes; ++i) {
 942                 u32 bpl = pix->plane_fmt[i].bytesperline;
 943                 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
 944
 945                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
 946                         bpl = pix->width; /* Planar */
 947
 948                 if (fmt->colplanes == 1 && /* Packed */
 949                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
 950                         bpl = (pix->width * fmt->depth[0]) / 8;
 951
 952                 if (i == 0) /* Same bytesperline for each plane. */
 953                         bytesperline = bpl;
 954
 955                 pix->plane_fmt[i].bytesperline = bytesperline;
 956                 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
 957         }
 958 }
 959
 960 static int fimc_m2m_g_fmt_mplane(struct file *file, void *fh,
 961                                  struct v4l2_format *f)
 962 {
 963         struct fimc_ctx *ctx = fh_to_ctx(fh);
 964         struct fimc_frame *frame = ctx_get_frame(ctx, f->type);
 965
 966         if (IS_ERR(frame))
 967                 return PTR_ERR(frame);
 968
 969         return fimc_fill_format(frame, f);
 970 }
 971
 972 /**
 973  * fimc_find_format - lookup fimc color format by fourcc or media bus format
 974  * @pixelformat: fourcc to match, ignored if null
 975  * @mbus_code: media bus code to match, ignored if null
 976  * @mask: the color flags to match
 977  * @index: offset in the fimc_formats array, ignored if negative
 978  */
 979 struct fimc_fmt *fimc_find_format(u32 *pixelformat, u32 *mbus_code,
 980                                   unsigned int mask, int index)
 981 {
 982         struct fimc_fmt *fmt, *def_fmt = NULL;
 983         unsigned int i;
 984         int id = 0;
 985
 986         if (index >= ARRAY_SIZE(fimc_formats))
 987                 return NULL;
 988
 989         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
 990                 fmt = &fimc_formats[i];
 991                 if (!(fmt->flags & mask))
 992                         continue;
 993                 if (pixelformat && fmt->fourcc == *pixelformat)
 994                         return fmt;
 995                 if (mbus_code && fmt->mbus_code == *mbus_code)
 996                         return fmt;
 997                 if (index == id)
 998                         def_fmt = fmt;
 999                 id++;
1000         }
1001         return def_fmt;
1002 }
1003
1004 static int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f)
1005 {
1006         struct fimc_dev *fimc = ctx->fimc_dev;
1007         struct samsung_fimc_variant *variant = fimc->variant;
1008         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1009         struct fimc_fmt *fmt;
1010         u32 max_w, mod_x, mod_y;
1011
1012         if (!IS_M2M(f->type))
1013                 return -EINVAL;
1014
1015         dbg("w: %d, h: %d", pix->width, pix->height);
1016
1017         fmt = fimc_find_format(&pix->pixelformat, NULL, FMT_FLAGS_M2M, 0);
1018         if (WARN(fmt == NULL, "Pixel format lookup failed"))
1019                 return -EINVAL;
1020
1021         if (pix->field == V4L2_FIELD_ANY)
1022                 pix->field = V4L2_FIELD_NONE;
1023         else if (pix->field != V4L2_FIELD_NONE)
1024                 return -EINVAL;
1025
1026         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1027                 max_w = variant->pix_limit->scaler_dis_w;
1028                 mod_x = ffs(variant->min_inp_pixsize) - 1;
1029         } else {
1030                 max_w = variant->pix_limit->out_rot_dis_w;
1031                 mod_x = ffs(variant->min_out_pixsize) - 1;
1032         }
1033
1034         if (tiled_fmt(fmt)) {
1035                 mod_x = 6; /* 64 x 32 pixels tile */
1036                 mod_y = 5;
1037         } else {
1038                 if (fimc->id == 1 && variant->pix_hoff)
1039                         mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
1040                 else
1041                         mod_y = mod_x;
1042         }
1043         dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_w);
1044
1045         v4l_bound_align_image(&pix->width, 16, max_w, mod_x,
1046                 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
1047
1048         fimc_adjust_mplane_format(fmt, pix->width, pix->height, &f->fmt.pix_mp);
1049         return 0;
1050 }
1051
1052 static int fimc_m2m_try_fmt_mplane(struct file *file, void *fh,
1053                                    struct v4l2_format *f)
1054 {
1055         struct fimc_ctx *ctx = fh_to_ctx(fh);
1056
1057         return fimc_try_fmt_mplane(ctx, f);
1058 }
1059
1060 static int fimc_m2m_s_fmt_mplane(struct file *file, void *fh,
1061                                  struct v4l2_format *f)
1062 {
1063         struct fimc_ctx *ctx = fh_to_ctx(fh);
1064         struct fimc_dev *fimc = ctx->fimc_dev;
1065         struct vb2_queue *vq;
1066         struct fimc_frame *frame;
1067         struct v4l2_pix_format_mplane *pix;
1068         int i, ret = 0;
1069
1070         ret = fimc_try_fmt_mplane(ctx, f);
1071         if (ret)
1072                 return ret;
1073
1074         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1075
1076         if (vb2_is_busy(vq)) {
1077                 v4l2_err(fimc->m2m.vfd, "queue (%d) busy\n", f->type);
1078                 return -EBUSY;
1079         }
1080
1081         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1082                 frame = &ctx->s_frame;
1083         else
1084                 frame = &ctx->d_frame;
1085
1086         pix = &f->fmt.pix_mp;
1087         frame->fmt = fimc_find_format(&pix->pixelformat, NULL,
1088                                       FMT_FLAGS_M2M, 0);
1089         if (!frame->fmt)
1090                 return -EINVAL;
1091
1092         for (i = 0; i < frame->fmt->colplanes; i++) {
1093                 frame->payload[i] =
1094                         (pix->width * pix->height * frame->fmt->depth[i]) / 8;
1095         }
1096
1097         fimc_fill_frame(frame, f);
1098
1099         if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1100                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1101         else
1102                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1103
1104         dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1105
1106         return 0;
1107 }
1108
1109 static int fimc_m2m_reqbufs(struct file *file, void *fh,
1110                             struct v4l2_requestbuffers *reqbufs)
1111 {
1112         struct fimc_ctx *ctx = fh_to_ctx(fh);
1113
1114         return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1115 }
1116
1117 static int fimc_m2m_querybuf(struct file *file, void *fh,
1118                              struct v4l2_buffer *buf)
1119 {
1120         struct fimc_ctx *ctx = fh_to_ctx(fh);
1121
1122         return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1123 }
1124
1125 static int fimc_m2m_qbuf(struct file *file, void *fh,
1126                          struct v4l2_buffer *buf)
1127 {
1128         struct fimc_ctx *ctx = fh_to_ctx(fh);
1129
1130         return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1131 }
1132
1133 static int fimc_m2m_dqbuf(struct file *file, void *fh,
1134                           struct v4l2_buffer *buf)
1135 {
1136         struct fimc_ctx *ctx = fh_to_ctx(fh);
1137
1138         return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1139 }
1140
1141 static int fimc_m2m_streamon(struct file *file, void *fh,
1142                              enum v4l2_buf_type type)
1143 {
1144         struct fimc_ctx *ctx = fh_to_ctx(fh);
1145
1146         /* The source and target color format need to be set */
1147         if (V4L2_TYPE_IS_OUTPUT(type)) {
1148                 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1149                         return -EINVAL;
1150         } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1151                 return -EINVAL;
1152         }
1153
1154         return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1155 }
1156
1157 static int fimc_m2m_streamoff(struct file *file, void *fh,
1158                             enum v4l2_buf_type type)
1159 {
1160         struct fimc_ctx *ctx = fh_to_ctx(fh);
1161
1162         return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1163 }
1164
1165 static int fimc_m2m_cropcap(struct file *file, void *fh,
1166                             struct v4l2_cropcap *cr)
1167 {
1168         struct fimc_ctx *ctx = fh_to_ctx(fh);
1169         struct fimc_frame *frame;
1170
1171         frame = ctx_get_frame(ctx, cr->type);
1172         if (IS_ERR(frame))
1173                 return PTR_ERR(frame);
1174
1175         cr->bounds.left         = 0;
1176         cr->bounds.top          = 0;
1177         cr->bounds.width        = frame->o_width;
1178         cr->bounds.height       = frame->o_height;
1179         cr->defrect             = cr->bounds;
1180
1181         return 0;
1182 }
1183
1184 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1185 {
1186         struct fimc_ctx *ctx = fh_to_ctx(fh);
1187         struct fimc_frame *frame;
1188
1189         frame = ctx_get_frame(ctx, cr->type);
1190         if (IS_ERR(frame))
1191                 return PTR_ERR(frame);
1192
1193         cr->c.left = frame->offs_h;
1194         cr->c.top = frame->offs_v;
1195         cr->c.width = frame->width;
1196         cr->c.height = frame->height;
1197
1198         return 0;
1199 }
1200
1201 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1202 {
1203         struct fimc_dev *fimc = ctx->fimc_dev;
1204         struct fimc_frame *f;
1205         u32 min_size, halign, depth = 0;
1206         bool is_capture_ctx;
1207         int i;
1208
1209         if (cr->c.top < 0 || cr->c.left < 0) {
1210                 v4l2_err(fimc->m2m.vfd,
1211                         "doesn't support negative values for top & left\n");
1212                 return -EINVAL;
1213         }
1214
1215         is_capture_ctx = fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx);
1216
1217         if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1218                 f = is_capture_ctx ? &ctx->s_frame : &ctx->d_frame;
1219         else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
1220                  !is_capture_ctx)
1221                 f = &ctx->s_frame;
1222         else
1223                 return -EINVAL;
1224
1225         min_size = (f == &ctx->s_frame) ?
1226                 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1227
1228         /* Get pixel alignment constraints. */
1229         if (is_capture_ctx) {
1230                 min_size = 16;
1231                 halign = 4;
1232         } else {
1233                 if (fimc->id == 1 && fimc->variant->pix_hoff)
1234                         halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1235                 else
1236                         halign = ffs(min_size) - 1;
1237         }
1238
1239         for (i = 0; i < f->fmt->colplanes; i++)
1240                 depth += f->fmt->depth[i];
1241
1242         v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1243                               ffs(min_size) - 1,
1244                               &cr->c.height, min_size, f->o_height,
1245                               halign, 64/(ALIGN(depth, 8)));
1246
1247         /* adjust left/top if cropping rectangle is out of bounds */
1248         if (cr->c.left + cr->c.width > f->o_width)
1249                 cr->c.left = f->o_width - cr->c.width;
1250         if (cr->c.top + cr->c.height > f->o_height)
1251                 cr->c.top = f->o_height - cr->c.height;
1252
1253         cr->c.left = round_down(cr->c.left, min_size);
1254         cr->c.top  = round_down(cr->c.top, is_capture_ctx ? 16 : 8);
1255
1256         dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1257             cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1258             f->f_width, f->f_height);
1259
1260         return 0;
1261 }
1262
1263 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1264 {
1265         struct fimc_ctx *ctx = fh_to_ctx(fh);
1266         struct fimc_dev *fimc = ctx->fimc_dev;
1267         struct fimc_frame *f;
1268         int ret;
1269
1270         ret = fimc_try_crop(ctx, cr);
1271         if (ret)
1272                 return ret;
1273
1274         f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1275                 &ctx->s_frame : &ctx->d_frame;
1276
1277         /* Check to see if scaling ratio is within supported range */
1278         if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1279                 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1280                         ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
1281                                                       ctx->d_frame.width,
1282                                                       ctx->d_frame.height,
1283                                                       ctx->rotation);
1284                 } else {
1285                         ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1286                                                       ctx->s_frame.height,
1287                                                       cr->c.width, cr->c.height,
1288                                                       ctx->rotation);
1289                 }
1290                 if (ret) {
1291                         v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
1292                         return -EINVAL;
1293                 }
1294         }
1295
1296         f->offs_h = cr->c.left;
1297         f->offs_v = cr->c.top;
1298         f->width  = cr->c.width;
1299         f->height = cr->c.height;
1300
1301         fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1302
1303         return 0;
1304 }
1305
1306 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1307         .vidioc_querycap                = fimc_m2m_querycap,
1308
1309         .vidioc_enum_fmt_vid_cap_mplane = fimc_m2m_enum_fmt_mplane,
1310         .vidioc_enum_fmt_vid_out_mplane = fimc_m2m_enum_fmt_mplane,
1311
1312         .vidioc_g_fmt_vid_cap_mplane    = fimc_m2m_g_fmt_mplane,
1313         .vidioc_g_fmt_vid_out_mplane    = fimc_m2m_g_fmt_mplane,
1314
1315         .vidioc_try_fmt_vid_cap_mplane  = fimc_m2m_try_fmt_mplane,
1316         .vidioc_try_fmt_vid_out_mplane  = fimc_m2m_try_fmt_mplane,
1317
1318         .vidioc_s_fmt_vid_cap_mplane    = fimc_m2m_s_fmt_mplane,
1319         .vidioc_s_fmt_vid_out_mplane    = fimc_m2m_s_fmt_mplane,
1320
1321         .vidioc_reqbufs                 = fimc_m2m_reqbufs,
1322         .vidioc_querybuf                = fimc_m2m_querybuf,
1323
1324         .vidioc_qbuf                    = fimc_m2m_qbuf,
1325         .vidioc_dqbuf                   = fimc_m2m_dqbuf,
1326
1327         .vidioc_streamon                = fimc_m2m_streamon,
1328         .vidioc_streamoff               = fimc_m2m_streamoff,
1329
1330         .vidioc_g_crop                  = fimc_m2m_g_crop,
1331         .vidioc_s_crop                  = fimc_m2m_s_crop,
1332         .vidioc_cropcap                 = fimc_m2m_cropcap
1333
1334 };
1335
1336 static int queue_init(void *priv, struct vb2_queue *src_vq,
1337                       struct vb2_queue *dst_vq)
1338 {
1339         struct fimc_ctx *ctx = priv;
1340         int ret;
1341
1342         memset(src_vq, 0, sizeof(*src_vq));
1343         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1344         src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1345         src_vq->drv_priv = ctx;
1346         src_vq->ops = &fimc_qops;
1347         src_vq->mem_ops = &vb2_dma_contig_memops;
1348         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1349
1350         ret = vb2_queue_init(src_vq);
1351         if (ret)
1352                 return ret;
1353
1354         memset(dst_vq, 0, sizeof(*dst_vq));
1355         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1356         dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1357         dst_vq->drv_priv = ctx;
1358         dst_vq->ops = &fimc_qops;
1359         dst_vq->mem_ops = &vb2_dma_contig_memops;
1360         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1361
1362         return vb2_queue_init(dst_vq);
1363 }
1364
1365 static int fimc_m2m_open(struct file *file)
1366 {
1367         struct fimc_dev *fimc = video_drvdata(file);
1368         struct fimc_ctx *ctx;
1369         int ret;
1370
1371         dbg("pid: %d, state: 0x%lx, refcnt: %d",
1372                 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1373
1374         /*
1375          * Return if the corresponding video capture node
1376          * is already opened.
1377          */
1378         if (fimc->vid_cap.refcnt > 0)
1379                 return -EBUSY;
1380
1381         ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1382         if (!ctx)
1383                 return -ENOMEM;
1384         v4l2_fh_init(&ctx->fh, fimc->m2m.vfd);
1385         ret = fimc_ctrls_create(ctx);
1386         if (ret)
1387                 goto error_fh;
1388
1389         /* Use separate control handler per file handle */
1390         ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1391         file->private_data = &ctx->fh;
1392         v4l2_fh_add(&ctx->fh);
1393
1394         ctx->fimc_dev = fimc;
1395         /* Default color format */
1396         ctx->s_frame.fmt = &fimc_formats[0];
1397         ctx->d_frame.fmt = &fimc_formats[0];
1398         /* Setup the device context for memory-to-memory mode */
1399         ctx->state = FIMC_CTX_M2M;
1400         ctx->flags = 0;
1401         ctx->in_path = FIMC_DMA;
1402         ctx->out_path = FIMC_DMA;
1403         spin_lock_init(&ctx->slock);
1404
1405         ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1406         if (IS_ERR(ctx->m2m_ctx)) {
1407                 ret = PTR_ERR(ctx->m2m_ctx);
1408                 goto error_c;
1409         }
1410
1411         if (fimc->m2m.refcnt++ == 0)
1412                 set_bit(ST_M2M_RUN, &fimc->state);
1413         return 0;
1414
1415 error_c:
1416         fimc_ctrls_delete(ctx);
1417 error_fh:
1418         v4l2_fh_del(&ctx->fh);
1419         v4l2_fh_exit(&ctx->fh);
1420         kfree(ctx);
1421         return ret;
1422 }
1423
1424 static int fimc_m2m_release(struct file *file)
1425 {
1426         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1427         struct fimc_dev *fimc = ctx->fimc_dev;
1428
1429         dbg("pid: %d, state: 0x%lx, refcnt= %d",
1430                 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1431
1432         v4l2_m2m_ctx_release(ctx->m2m_ctx);
1433         fimc_ctrls_delete(ctx);
1434         v4l2_fh_del(&ctx->fh);
1435         v4l2_fh_exit(&ctx->fh);
1436
1437         if (--fimc->m2m.refcnt <= 0)
1438                 clear_bit(ST_M2M_RUN, &fimc->state);
1439         kfree(ctx);
1440         return 0;
1441 }
1442
1443 static unsigned int fimc_m2m_poll(struct file *file,
1444                                   struct poll_table_struct *wait)
1445 {
1446         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1447
1448         return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1449 }
1450
1451
1452 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1453 {
1454         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1455
1456         return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1457 }
1458
1459 static const struct v4l2_file_operations fimc_m2m_fops = {
1460         .owner          = THIS_MODULE,
1461         .open           = fimc_m2m_open,
1462         .release        = fimc_m2m_release,
1463         .poll           = fimc_m2m_poll,
1464         .unlocked_ioctl = video_ioctl2,
1465         .mmap           = fimc_m2m_mmap,
1466 };
1467
1468 static struct v4l2_m2m_ops m2m_ops = {
1469         .device_run     = fimc_dma_run,
1470         .job_abort      = fimc_job_abort,
1471 };
1472
1473 int fimc_register_m2m_device(struct fimc_dev *fimc,
1474                              struct v4l2_device *v4l2_dev)
1475 {
1476         struct video_device *vfd;
1477         struct platform_device *pdev;
1478         int ret = 0;
1479
1480         if (!fimc)
1481                 return -ENODEV;
1482
1483         pdev = fimc->pdev;
1484         fimc->v4l2_dev = v4l2_dev;
1485
1486         vfd = video_device_alloc();
1487         if (!vfd) {
1488                 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1489                 return -ENOMEM;
1490         }
1491
1492         vfd->fops       = &fimc_m2m_fops;
1493         vfd->ioctl_ops  = &fimc_m2m_ioctl_ops;
1494         vfd->v4l2_dev   = v4l2_dev;
1495         vfd->minor      = -1;
1496         vfd->release    = video_device_release;
1497         vfd->lock       = &fimc->lock;
1498
1499         snprintf(vfd->name, sizeof(vfd->name), "%s.m2m", dev_name(&pdev->dev));
1500         video_set_drvdata(vfd, fimc);
1501
1502         fimc->m2m.vfd = vfd;
1503         fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1504         if (IS_ERR(fimc->m2m.m2m_dev)) {
1505                 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1506                 ret = PTR_ERR(fimc->m2m.m2m_dev);
1507                 goto err_init;
1508         }
1509
1510         ret = media_entity_init(&vfd->entity, 0, NULL, 0);
1511         if (!ret)
1512                 return 0;
1513
1514         v4l2_m2m_release(fimc->m2m.m2m_dev);
1515 err_init:
1516         video_device_release(fimc->m2m.vfd);
1517         return ret;
1518 }
1519
1520 void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1521 {
1522         if (!fimc)
1523                 return;
1524
1525         if (fimc->m2m.m2m_dev)
1526                 v4l2_m2m_release(fimc->m2m.m2m_dev);
1527         if (fimc->m2m.vfd) {
1528                 media_entity_cleanup(&fimc->m2m.vfd->entity);
1529                 /* Can also be called if video device wasn't registered */
1530                 video_unregister_device(fimc->m2m.vfd);
1531         }
1532 }
1533
1534 static void fimc_clk_put(struct fimc_dev *fimc)
1535 {
1536         int i;
1537         for (i = 0; i < fimc->num_clocks; i++) {
1538                 if (fimc->clock[i])
1539                         clk_put(fimc->clock[i]);
1540         }
1541 }
1542
1543 static int fimc_clk_get(struct fimc_dev *fimc)
1544 {
1545         int i;
1546         for (i = 0; i < fimc->num_clocks; i++) {
1547                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1548                 if (!IS_ERR_OR_NULL(fimc->clock[i]))
1549                         continue;
1550                 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1551                         fimc_clocks[i]);
1552                 return -ENXIO;
1553         }
1554
1555         return 0;
1556 }
1557
1558 static int fimc_m2m_suspend(struct fimc_dev *fimc)
1559 {
1560         unsigned long flags;
1561         int timeout;
1562
1563         spin_lock_irqsave(&fimc->slock, flags);
1564         if (!fimc_m2m_pending(fimc)) {
1565                 spin_unlock_irqrestore(&fimc->slock, flags);
1566                 return 0;
1567         }
1568         clear_bit(ST_M2M_SUSPENDED, &fimc->state);
1569         set_bit(ST_M2M_SUSPENDING, &fimc->state);
1570         spin_unlock_irqrestore(&fimc->slock, flags);
1571
1572         timeout = wait_event_timeout(fimc->irq_queue,
1573                              test_bit(ST_M2M_SUSPENDED, &fimc->state),
1574                              FIMC_SHUTDOWN_TIMEOUT);
1575
1576         clear_bit(ST_M2M_SUSPENDING, &fimc->state);
1577         return timeout == 0 ? -EAGAIN : 0;
1578 }
1579
1580 static int fimc_m2m_resume(struct fimc_dev *fimc)
1581 {
1582         unsigned long flags;
1583
1584         spin_lock_irqsave(&fimc->slock, flags);
1585         /* Clear for full H/W setup in first run after resume */
1586         fimc->m2m.ctx = NULL;
1587         spin_unlock_irqrestore(&fimc->slock, flags);
1588
1589         if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
1590                 fimc_m2m_job_finish(fimc->m2m.ctx,
1591                                     VB2_BUF_STATE_ERROR);
1592         return 0;
1593 }
1594
1595 static int fimc_probe(struct platform_device *pdev)
1596 {
1597         struct fimc_dev *fimc;
1598         struct resource *res;
1599         struct samsung_fimc_driverdata *drv_data;
1600         struct s5p_platform_fimc *pdata;
1601         int ret = 0;
1602
1603         dev_dbg(&pdev->dev, "%s():\n", __func__);
1604
1605         drv_data = (struct samsung_fimc_driverdata *)
1606                 platform_get_device_id(pdev)->driver_data;
1607
1608         if (pdev->id >= drv_data->num_entities) {
1609                 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1610                         pdev->id);
1611                 return -EINVAL;
1612         }
1613
1614         fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1615         if (!fimc)
1616                 return -ENOMEM;
1617
1618         fimc->id = pdev->id;
1619
1620         fimc->variant = drv_data->variant[fimc->id];
1621         fimc->pdev = pdev;
1622         pdata = pdev->dev.platform_data;
1623         fimc->pdata = pdata;
1624
1625         set_bit(ST_LPM, &fimc->state);
1626
1627         init_waitqueue_head(&fimc->irq_queue);
1628         spin_lock_init(&fimc->slock);
1629         mutex_init(&fimc->lock);
1630
1631         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1632         if (!res) {
1633                 dev_err(&pdev->dev, "failed to find the registers\n");
1634                 ret = -ENOENT;
1635                 goto err_info;
1636         }
1637
1638         fimc->regs_res = request_mem_region(res->start, resource_size(res),
1639                         dev_name(&pdev->dev));
1640         if (!fimc->regs_res) {
1641                 dev_err(&pdev->dev, "failed to obtain register region\n");
1642                 ret = -ENOENT;
1643                 goto err_info;
1644         }
1645
1646         fimc->regs = ioremap(res->start, resource_size(res));
1647         if (!fimc->regs) {
1648                 dev_err(&pdev->dev, "failed to map registers\n");
1649                 ret = -ENXIO;
1650                 goto err_req_region;
1651         }
1652
1653         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1654         if (!res) {
1655                 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1656                 ret = -ENXIO;
1657                 goto err_regs_unmap;
1658         }
1659         fimc->irq = res->start;
1660
1661         fimc->num_clocks = MAX_FIMC_CLOCKS;
1662         ret = fimc_clk_get(fimc);
1663         if (ret)
1664                 goto err_regs_unmap;
1665         clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1666         clk_enable(fimc->clock[CLK_BUS]);
1667
1668         platform_set_drvdata(pdev, fimc);
1669
1670         ret = request_irq(fimc->irq, fimc_irq_handler, 0, pdev->name, fimc);
1671         if (ret) {
1672                 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1673                 goto err_clk;
1674         }
1675
1676         pm_runtime_enable(&pdev->dev);
1677         ret = pm_runtime_get_sync(&pdev->dev);
1678         if (ret < 0)
1679                 goto err_irq;
1680         /* Initialize contiguous memory allocator */
1681         fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1682         if (IS_ERR(fimc->alloc_ctx)) {
1683                 ret = PTR_ERR(fimc->alloc_ctx);
1684                 goto err_pm;
1685         }
1686
1687         dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id);
1688
1689         pm_runtime_put(&pdev->dev);
1690         return 0;
1691
1692 err_pm:
1693         pm_runtime_put(&pdev->dev);
1694 err_irq:
1695         free_irq(fimc->irq, fimc);
1696 err_clk:
1697         fimc_clk_put(fimc);
1698 err_regs_unmap:
1699         iounmap(fimc->regs);
1700 err_req_region:
1701         release_resource(fimc->regs_res);
1702         kfree(fimc->regs_res);
1703 err_info:
1704         kfree(fimc);
1705         return ret;
1706 }
1707
1708 static int fimc_runtime_resume(struct device *dev)
1709 {
1710         struct fimc_dev *fimc = dev_get_drvdata(dev);
1711
1712         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1713
1714         /* Enable clocks and perform basic initalization */
1715         clk_enable(fimc->clock[CLK_GATE]);
1716         fimc_hw_reset(fimc);
1717         if (fimc->variant->out_buf_count > 4)
1718                 fimc_hw_set_dma_seq(fimc, 0xF);
1719
1720         /* Resume the capture or mem-to-mem device */
1721         if (fimc_capture_busy(fimc))
1722                 return fimc_capture_resume(fimc);
1723         else if (fimc_m2m_pending(fimc))
1724                 return fimc_m2m_resume(fimc);
1725         return 0;
1726 }
1727
1728 static int fimc_runtime_suspend(struct device *dev)
1729 {
1730         struct fimc_dev *fimc = dev_get_drvdata(dev);
1731         int ret = 0;
1732
1733         if (fimc_capture_busy(fimc))
1734                 ret = fimc_capture_suspend(fimc);
1735         else
1736                 ret = fimc_m2m_suspend(fimc);
1737         if (!ret)
1738                 clk_disable(fimc->clock[CLK_GATE]);
1739
1740         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1741         return ret;
1742 }
1743
1744 #ifdef CONFIG_PM_SLEEP
1745 static int fimc_resume(struct device *dev)
1746 {
1747         struct fimc_dev *fimc = dev_get_drvdata(dev);
1748         unsigned long flags;
1749
1750         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1751
1752         /* Do not resume if the device was idle before system suspend */
1753         spin_lock_irqsave(&fimc->slock, flags);
1754         if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1755             (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1756                 spin_unlock_irqrestore(&fimc->slock, flags);
1757                 return 0;
1758         }
1759         fimc_hw_reset(fimc);
1760         if (fimc->variant->out_buf_count > 4)
1761                 fimc_hw_set_dma_seq(fimc, 0xF);
1762         spin_unlock_irqrestore(&fimc->slock, flags);
1763
1764         if (fimc_capture_busy(fimc))
1765                 return fimc_capture_resume(fimc);
1766
1767         return fimc_m2m_resume(fimc);
1768 }
1769
1770 static int fimc_suspend(struct device *dev)
1771 {
1772         struct fimc_dev *fimc = dev_get_drvdata(dev);
1773
1774         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1775
1776         if (test_and_set_bit(ST_LPM, &fimc->state))
1777                 return 0;
1778         if (fimc_capture_busy(fimc))
1779                 return fimc_capture_suspend(fimc);
1780
1781         return fimc_m2m_suspend(fimc);
1782 }
1783 #endif /* CONFIG_PM_SLEEP */
1784
1785 static int __devexit fimc_remove(struct platform_device *pdev)
1786 {
1787         struct fimc_dev *fimc = platform_get_drvdata(pdev);
1788
1789         pm_runtime_disable(&pdev->dev);
1790         fimc_runtime_suspend(&pdev->dev);
1791         pm_runtime_set_suspended(&pdev->dev);
1792
1793         vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1794
1795         clk_disable(fimc->clock[CLK_BUS]);
1796         fimc_clk_put(fimc);
1797         free_irq(fimc->irq, fimc);
1798         iounmap(fimc->regs);
1799         release_resource(fimc->regs_res);
1800         kfree(fimc->regs_res);
1801         kfree(fimc);
1802
1803         dev_info(&pdev->dev, "driver unloaded\n");
1804         return 0;
1805 }
1806
1807 /* Image pixel limits, similar across several FIMC HW revisions. */
1808 static struct fimc_pix_limit s5p_pix_limit[4] = {
1809         [0] = {
1810                 .scaler_en_w    = 3264,
1811                 .scaler_dis_w   = 8192,
1812                 .in_rot_en_h    = 1920,
1813                 .in_rot_dis_w   = 8192,
1814                 .out_rot_en_w   = 1920,
1815                 .out_rot_dis_w  = 4224,
1816         },
1817         [1] = {
1818                 .scaler_en_w    = 4224,
1819                 .scaler_dis_w   = 8192,
1820                 .in_rot_en_h    = 1920,
1821                 .in_rot_dis_w   = 8192,
1822                 .out_rot_en_w   = 1920,
1823                 .out_rot_dis_w  = 4224,
1824         },
1825         [2] = {
1826                 .scaler_en_w    = 1920,
1827                 .scaler_dis_w   = 8192,
1828                 .in_rot_en_h    = 1280,
1829                 .in_rot_dis_w   = 8192,
1830                 .out_rot_en_w   = 1280,
1831                 .out_rot_dis_w  = 1920,
1832         },
1833         [3] = {
1834                 .scaler_en_w    = 1920,
1835                 .scaler_dis_w   = 8192,
1836                 .in_rot_en_h    = 1366,
1837                 .in_rot_dis_w   = 8192,
1838                 .out_rot_en_w   = 1366,
1839                 .out_rot_dis_w  = 1920,
1840         },
1841 };
1842
1843 static struct samsung_fimc_variant fimc0_variant_s5p = {
1844         .has_inp_rot     = 1,
1845         .has_out_rot     = 1,
1846         .has_cam_if      = 1,
1847         .min_inp_pixsize = 16,
1848         .min_out_pixsize = 16,
1849         .hor_offs_align  = 8,
1850         .out_buf_count   = 4,
1851         .pix_limit       = &s5p_pix_limit[0],
1852 };
1853
1854 static struct samsung_fimc_variant fimc2_variant_s5p = {
1855         .has_cam_if      = 1,
1856         .min_inp_pixsize = 16,
1857         .min_out_pixsize = 16,
1858         .hor_offs_align  = 8,
1859         .out_buf_count   = 4,
1860         .pix_limit = &s5p_pix_limit[1],
1861 };
1862
1863 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1864         .pix_hoff        = 1,
1865         .has_inp_rot     = 1,
1866         .has_out_rot     = 1,
1867         .has_cam_if      = 1,
1868         .min_inp_pixsize = 16,
1869         .min_out_pixsize = 16,
1870         .hor_offs_align  = 8,
1871         .out_buf_count   = 4,
1872         .pix_limit       = &s5p_pix_limit[1],
1873 };
1874
1875 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1876         .pix_hoff        = 1,
1877         .has_inp_rot     = 1,
1878         .has_out_rot     = 1,
1879         .has_cam_if      = 1,
1880         .has_mainscaler_ext = 1,
1881         .min_inp_pixsize = 16,
1882         .min_out_pixsize = 16,
1883         .hor_offs_align  = 1,
1884         .out_buf_count   = 4,
1885         .pix_limit       = &s5p_pix_limit[2],
1886 };
1887
1888 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1889         .has_cam_if      = 1,
1890         .pix_hoff        = 1,
1891         .min_inp_pixsize = 16,
1892         .min_out_pixsize = 16,
1893         .hor_offs_align  = 8,
1894         .out_buf_count   = 4,
1895         .pix_limit       = &s5p_pix_limit[2],
1896 };
1897
1898 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1899         .pix_hoff        = 1,
1900         .has_inp_rot     = 1,
1901         .has_out_rot     = 1,
1902         .has_cam_if      = 1,
1903         .has_cistatus2   = 1,
1904         .has_mainscaler_ext = 1,
1905         .min_inp_pixsize = 16,
1906         .min_out_pixsize = 16,
1907         .hor_offs_align  = 1,
1908         .out_buf_count   = 32,
1909         .pix_limit       = &s5p_pix_limit[1],
1910 };
1911
1912 static struct samsung_fimc_variant fimc3_variant_exynos4 = {
1913         .pix_hoff        = 1,
1914         .has_cam_if      = 1,
1915         .has_cistatus2   = 1,
1916         .has_mainscaler_ext = 1,
1917         .min_inp_pixsize = 16,
1918         .min_out_pixsize = 16,
1919         .hor_offs_align  = 1,
1920         .out_buf_count   = 32,
1921         .pix_limit       = &s5p_pix_limit[3],
1922 };
1923
1924 /* S5PC100 */
1925 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1926         .variant = {
1927                 [0] = &fimc0_variant_s5p,
1928                 [1] = &fimc0_variant_s5p,
1929                 [2] = &fimc2_variant_s5p,
1930         },
1931         .num_entities = 3,
1932         .lclk_frequency = 133000000UL,
1933 };
1934
1935 /* S5PV210, S5PC110 */
1936 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1937         .variant = {
1938                 [0] = &fimc0_variant_s5pv210,
1939                 [1] = &fimc1_variant_s5pv210,
1940                 [2] = &fimc2_variant_s5pv210,
1941         },
1942         .num_entities = 3,
1943         .lclk_frequency = 166000000UL,
1944 };
1945
1946 /* S5PV310, S5PC210 */
1947 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1948         .variant = {
1949                 [0] = &fimc0_variant_exynos4,
1950                 [1] = &fimc0_variant_exynos4,
1951                 [2] = &fimc0_variant_exynos4,
1952                 [3] = &fimc3_variant_exynos4,
1953         },
1954         .num_entities = 4,
1955         .lclk_frequency = 166000000UL,
1956 };
1957
1958 static struct platform_device_id fimc_driver_ids[] = {
1959         {
1960                 .name           = "s5p-fimc",
1961                 .driver_data    = (unsigned long)&fimc_drvdata_s5p,
1962         }, {
1963                 .name           = "s5pv210-fimc",
1964                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
1965         }, {
1966                 .name           = "exynos4-fimc",
1967                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4,
1968         },
1969         {},
1970 };
1971 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1972
1973 static const struct dev_pm_ops fimc_pm_ops = {
1974         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1975         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1976 };
1977
1978 static struct platform_driver fimc_driver = {
1979         .probe          = fimc_probe,
1980         .remove         = __devexit_p(fimc_remove),
1981         .id_table       = fimc_driver_ids,
1982         .driver = {
1983                 .name   = FIMC_MODULE_NAME,
1984                 .owner  = THIS_MODULE,
1985                 .pm     = &fimc_pm_ops,
1986         }
1987 };
1988
1989 int __init fimc_register_driver(void)
1990 {
1991         return platform_driver_probe(&fimc_driver, fimc_probe);
1992 }
1993
1994 void __exit fimc_unregister_driver(void)
1995 {
1996         platform_driver_unregister(&fimc_driver);
1997 }