Pileus Git - ~andy/linux/blob - drivers/media/video/s5p-fimc/fimc-core.c

   1 /*
   2  * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
   3  *
   4  * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
   5  * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published
   9  * by the Free Software Foundation, either version 2 of the License,
  10  * or (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/errno.h>
  17 #include <linux/bug.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/list.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/clk.h>
  26 #include <media/v4l2-ioctl.h>
  27 #include <media/videobuf2-core.h>
  28 #include <media/videobuf2-dma-contig.h>
  29
  30 #include "fimc-core.h"
  31 #include "fimc-mdevice.h"
  32
  33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  34         "sclk_fimc", "fimc"
  35 };
  36
  37 static struct fimc_fmt fimc_formats[] = {
  38         {
  39                 .name           = "RGB565",
  40                 .fourcc         = V4L2_PIX_FMT_RGB565X,
  41                 .depth          = { 16 },
  42                 .color          = S5P_FIMC_RGB565,
  43                 .memplanes      = 1,
  44                 .colplanes      = 1,
  45                 .flags          = FMT_FLAGS_M2M,
  46         }, {
  47                 .name           = "BGR666",
  48                 .fourcc         = V4L2_PIX_FMT_BGR666,
  49                 .depth          = { 32 },
  50                 .color          = S5P_FIMC_RGB666,
  51                 .memplanes      = 1,
  52                 .colplanes      = 1,
  53                 .flags          = FMT_FLAGS_M2M,
  54         }, {
  55                 .name           = "XRGB-8-8-8-8, 32 bpp",
  56                 .fourcc         = V4L2_PIX_FMT_RGB32,
  57                 .depth          = { 32 },
  58                 .color          = S5P_FIMC_RGB888,
  59                 .memplanes      = 1,
  60                 .colplanes      = 1,
  61                 .flags          = FMT_FLAGS_M2M,
  62         }, {
  63                 .name           = "YUV 4:2:2 packed, YCbYCr",
  64                 .fourcc         = V4L2_PIX_FMT_YUYV,
  65                 .depth          = { 16 },
  66                 .color          = S5P_FIMC_YCBYCR422,
  67                 .memplanes      = 1,
  68                 .colplanes      = 1,
  69                 .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
  70                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  71         }, {
  72                 .name           = "YUV 4:2:2 packed, CbYCrY",
  73                 .fourcc         = V4L2_PIX_FMT_UYVY,
  74                 .depth          = { 16 },
  75                 .color          = S5P_FIMC_CBYCRY422,
  76                 .memplanes      = 1,
  77                 .colplanes      = 1,
  78                 .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
  79                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  80         }, {
  81                 .name           = "YUV 4:2:2 packed, CrYCbY",
  82                 .fourcc         = V4L2_PIX_FMT_VYUY,
  83                 .depth          = { 16 },
  84                 .color          = S5P_FIMC_CRYCBY422,
  85                 .memplanes      = 1,
  86                 .colplanes      = 1,
  87                 .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
  88                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  89         }, {
  90                 .name           = "YUV 4:2:2 packed, YCrYCb",
  91                 .fourcc         = V4L2_PIX_FMT_YVYU,
  92                 .depth          = { 16 },
  93                 .color          = S5P_FIMC_YCRYCB422,
  94                 .memplanes      = 1,
  95                 .colplanes      = 1,
  96                 .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
  97                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  98         }, {
  99                 .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
 100                 .fourcc         = V4L2_PIX_FMT_YUV422P,
 101                 .depth          = { 12 },
 102                 .color          = S5P_FIMC_YCBYCR422,
 103                 .memplanes      = 1,
 104                 .colplanes      = 3,
 105                 .flags          = FMT_FLAGS_M2M,
 106         }, {
 107                 .name           = "YUV 4:2:2 planar, Y/CbCr",
 108                 .fourcc         = V4L2_PIX_FMT_NV16,
 109                 .depth          = { 16 },
 110                 .color          = S5P_FIMC_YCBYCR422,
 111                 .memplanes      = 1,
 112                 .colplanes      = 2,
 113                 .flags          = FMT_FLAGS_M2M,
 114         }, {
 115                 .name           = "YUV 4:2:2 planar, Y/CrCb",
 116                 .fourcc         = V4L2_PIX_FMT_NV61,
 117                 .depth          = { 16 },
 118                 .color          = S5P_FIMC_YCRYCB422,
 119                 .memplanes      = 1,
 120                 .colplanes      = 2,
 121                 .flags          = FMT_FLAGS_M2M,
 122         }, {
 123                 .name           = "YUV 4:2:0 planar, YCbCr",
 124                 .fourcc         = V4L2_PIX_FMT_YUV420,
 125                 .depth          = { 12 },
 126                 .color          = S5P_FIMC_YCBCR420,
 127                 .memplanes      = 1,
 128                 .colplanes      = 3,
 129                 .flags          = FMT_FLAGS_M2M,
 130         }, {
 131                 .name           = "YUV 4:2:0 planar, Y/CbCr",
 132                 .fourcc         = V4L2_PIX_FMT_NV12,
 133                 .depth          = { 12 },
 134                 .color          = S5P_FIMC_YCBCR420,
 135                 .memplanes      = 1,
 136                 .colplanes      = 2,
 137                 .flags          = FMT_FLAGS_M2M,
 138         }, {
 139                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
 140                 .fourcc         = V4L2_PIX_FMT_NV12M,
 141                 .color          = S5P_FIMC_YCBCR420,
 142                 .depth          = { 8, 4 },
 143                 .memplanes      = 2,
 144                 .colplanes      = 2,
 145                 .flags          = FMT_FLAGS_M2M,
 146         }, {
 147                 .name           = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
 148                 .fourcc         = V4L2_PIX_FMT_YUV420M,
 149                 .color          = S5P_FIMC_YCBCR420,
 150                 .depth          = { 8, 2, 2 },
 151                 .memplanes      = 3,
 152                 .colplanes      = 3,
 153                 .flags          = FMT_FLAGS_M2M,
 154         }, {
 155                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
 156                 .fourcc         = V4L2_PIX_FMT_NV12MT,
 157                 .color          = S5P_FIMC_YCBCR420,
 158                 .depth          = { 8, 4 },
 159                 .memplanes      = 2,
 160                 .colplanes      = 2,
 161                 .flags          = FMT_FLAGS_M2M,
 162         },
 163 };
 164
 165 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
 166 {
 167         int tx, ty;
 168
 169         if (rot == 90 || rot == 270) {
 170                 ty = dw;
 171                 tx = dh;
 172         } else {
 173                 tx = dw;
 174                 ty = dh;
 175         }
 176
 177         if ((sw >= SCALER_MAX_HRATIO * tx) || (sh >= SCALER_MAX_VRATIO * ty))
 178                 return -EINVAL;
 179
 180         return 0;
 181 }
 182
 183 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 184 {
 185         u32 sh = 6;
 186
 187         if (src >= 64 * tar)
 188                 return -EINVAL;
 189
 190         while (sh--) {
 191                 u32 tmp = 1 << sh;
 192                 if (src >= tar * tmp) {
 193                         *shift = sh, *ratio = tmp;
 194                         return 0;
 195                 }
 196         }
 197         *shift = 0, *ratio = 1;
 198         return 0;
 199 }
 200
 201 int fimc_set_scaler_info(struct fimc_ctx *ctx)
 202 {
 203         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 204         struct device *dev = &ctx->fimc_dev->pdev->dev;
 205         struct fimc_scaler *sc = &ctx->scaler;
 206         struct fimc_frame *s_frame = &ctx->s_frame;
 207         struct fimc_frame *d_frame = &ctx->d_frame;
 208         int tx, ty, sx, sy;
 209         int ret;
 210
 211         if (ctx->rotation == 90 || ctx->rotation == 270) {
 212                 ty = d_frame->width;
 213                 tx = d_frame->height;
 214         } else {
 215                 tx = d_frame->width;
 216                 ty = d_frame->height;
 217         }
 218         if (tx <= 0 || ty <= 0) {
 219                 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
 220                 return -EINVAL;
 221         }
 222
 223         sx = s_frame->width;
 224         sy = s_frame->height;
 225         if (sx <= 0 || sy <= 0) {
 226                 dev_err(dev, "Invalid source size: %dx%d", sx, sy);
 227                 return -EINVAL;
 228         }
 229         sc->real_width = sx;
 230         sc->real_height = sy;
 231
 232         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 233         if (ret)
 234                 return ret;
 235
 236         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 237         if (ret)
 238                 return ret;
 239
 240         sc->pre_dst_width = sx / sc->pre_hratio;
 241         sc->pre_dst_height = sy / sc->pre_vratio;
 242
 243         if (variant->has_mainscaler_ext) {
 244                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 245                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 246         } else {
 247                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 248                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 249
 250         }
 251
 252         sc->scaleup_h = (tx >= sx) ? 1 : 0;
 253         sc->scaleup_v = (ty >= sy) ? 1 : 0;
 254
 255         /* check to see if input and output size/format differ */
 256         if (s_frame->fmt->color == d_frame->fmt->color
 257                 && s_frame->width == d_frame->width
 258                 && s_frame->height == d_frame->height)
 259                 sc->copy_mode = 1;
 260         else
 261                 sc->copy_mode = 0;
 262
 263         return 0;
 264 }
 265
 266 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
 267 {
 268         struct vb2_buffer *src_vb, *dst_vb;
 269
 270         if (!ctx || !ctx->m2m_ctx)
 271                 return;
 272
 273         src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
 274         dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
 275
 276         if (src_vb && dst_vb) {
 277                 v4l2_m2m_buf_done(src_vb, vb_state);
 278                 v4l2_m2m_buf_done(dst_vb, vb_state);
 279                 v4l2_m2m_job_finish(ctx->fimc_dev->m2m.m2m_dev,
 280                                     ctx->m2m_ctx);
 281         }
 282 }
 283
 284 /* Complete the transaction which has been scheduled for execution. */
 285 static int fimc_m2m_shutdown(struct fimc_ctx *ctx)
 286 {
 287         struct fimc_dev *fimc = ctx->fimc_dev;
 288         int ret;
 289
 290         if (!fimc_m2m_pending(fimc))
 291                 return 0;
 292
 293         fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
 294
 295         ret = wait_event_timeout(fimc->irq_queue,
 296                            !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
 297                            FIMC_SHUTDOWN_TIMEOUT);
 298
 299         return ret == 0 ? -ETIMEDOUT : ret;
 300 }
 301
 302 static int start_streaming(struct vb2_queue *q, unsigned int count)
 303 {
 304         struct fimc_ctx *ctx = q->drv_priv;
 305         int ret;
 306
 307         ret = pm_runtime_get_sync(&ctx->fimc_dev->pdev->dev);
 308         return ret > 0 ? 0 : ret;
 309 }
 310
 311 static int stop_streaming(struct vb2_queue *q)
 312 {
 313         struct fimc_ctx *ctx = q->drv_priv;
 314         int ret;
 315
 316         ret = fimc_m2m_shutdown(ctx);
 317         if (ret == -ETIMEDOUT)
 318                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 319
 320         pm_runtime_put(&ctx->fimc_dev->pdev->dev);
 321         return 0;
 322 }
 323
 324 static void fimc_capture_irq_handler(struct fimc_dev *fimc)
 325 {
 326         struct fimc_vid_cap *cap = &fimc->vid_cap;
 327         struct fimc_vid_buffer *v_buf;
 328         struct timeval *tv;
 329         struct timespec ts;
 330
 331         if (!list_empty(&cap->active_buf_q) &&
 332             test_bit(ST_CAPT_RUN, &fimc->state)) {
 333                 ktime_get_real_ts(&ts);
 334
 335                 v_buf = active_queue_pop(cap);
 336
 337                 tv = &v_buf->vb.v4l2_buf.timestamp;
 338                 tv->tv_sec = ts.tv_sec;
 339                 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
 340                 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
 341
 342                 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
 343         }
 344
 345         if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
 346                 wake_up(&fimc->irq_queue);
 347                 return;
 348         }
 349
 350         if (!list_empty(&cap->pending_buf_q)) {
 351
 352                 v_buf = pending_queue_pop(cap);
 353                 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
 354                 v_buf->index = cap->buf_index;
 355
 356                 /* Move the buffer to the capture active queue */
 357                 active_queue_add(cap, v_buf);
 358
 359                 dbg("next frame: %d, done frame: %d",
 360                     fimc_hw_get_frame_index(fimc), v_buf->index);
 361
 362                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 363                         cap->buf_index = 0;
 364         }
 365
 366         if (cap->active_buf_cnt == 0) {
 367                 clear_bit(ST_CAPT_RUN, &fimc->state);
 368
 369                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 370                         cap->buf_index = 0;
 371         } else {
 372                 set_bit(ST_CAPT_RUN, &fimc->state);
 373         }
 374
 375         fimc_capture_config_update(cap->ctx);
 376
 377         dbg("frame: %d, active_buf_cnt: %d",
 378             fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
 379 }
 380
 381 static irqreturn_t fimc_irq_handler(int irq, void *priv)
 382 {
 383         struct fimc_dev *fimc = priv;
 384         struct fimc_vid_cap *cap = &fimc->vid_cap;
 385         struct fimc_ctx *ctx;
 386
 387         fimc_hw_clear_irq(fimc);
 388
 389         spin_lock(&fimc->slock);
 390
 391         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 392                 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
 393                         set_bit(ST_M2M_SUSPENDED, &fimc->state);
 394                         wake_up(&fimc->irq_queue);
 395                         goto out;
 396                 }
 397                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 398                 if (ctx != NULL) {
 399                         spin_unlock(&fimc->slock);
 400                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 401
 402                         spin_lock(&ctx->slock);
 403                         if (ctx->state & FIMC_CTX_SHUT) {
 404                                 ctx->state &= ~FIMC_CTX_SHUT;
 405                                 wake_up(&fimc->irq_queue);
 406                         }
 407                         spin_unlock(&ctx->slock);
 408                 }
 409                 return IRQ_HANDLED;
 410         } else {
 411                 if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 412                         fimc_capture_irq_handler(fimc);
 413
 414                         if (cap->active_buf_cnt == 1) {
 415                                 fimc_deactivate_capture(fimc);
 416                                 clear_bit(ST_CAPT_STREAM, &fimc->state);
 417                         }
 418                 }
 419         }
 420 out:
 421         spin_unlock(&fimc->slock);
 422         return IRQ_HANDLED;
 423 }
 424
 425 /* The color format (colplanes, memplanes) must be already configured. */
 426 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 427                       struct fimc_frame *frame, struct fimc_addr *paddr)
 428 {
 429         int ret = 0;
 430         u32 pix_size;
 431
 432         if (vb == NULL || frame == NULL)
 433                 return -EINVAL;
 434
 435         pix_size = frame->width * frame->height;
 436
 437         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 438                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 439
 440         paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
 441
 442         if (frame->fmt->memplanes == 1) {
 443                 switch (frame->fmt->colplanes) {
 444                 case 1:
 445                         paddr->cb = 0;
 446                         paddr->cr = 0;
 447                         break;
 448                 case 2:
 449                         /* decompose Y into Y/Cb */
 450                         paddr->cb = (u32)(paddr->y + pix_size);
 451                         paddr->cr = 0;
 452                         break;
 453                 case 3:
 454                         paddr->cb = (u32)(paddr->y + pix_size);
 455                         /* decompose Y into Y/Cb/Cr */
 456                         if (S5P_FIMC_YCBCR420 == frame->fmt->color)
 457                                 paddr->cr = (u32)(paddr->cb
 458                                                 + (pix_size >> 2));
 459                         else /* 422 */
 460                                 paddr->cr = (u32)(paddr->cb
 461                                                 + (pix_size >> 1));
 462                         break;
 463                 default:
 464                         return -EINVAL;
 465                 }
 466         } else {
 467                 if (frame->fmt->memplanes >= 2)
 468                         paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
 469
 470                 if (frame->fmt->memplanes == 3)
 471                         paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
 472         }
 473
 474         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 475             paddr->y, paddr->cb, paddr->cr, ret);
 476
 477         return ret;
 478 }
 479
 480 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 481 void fimc_set_yuv_order(struct fimc_ctx *ctx)
 482 {
 483         /* The one only mode supported in SoC. */
 484         ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
 485         ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
 486
 487         /* Set order for 1 plane input formats. */
 488         switch (ctx->s_frame.fmt->color) {
 489         case S5P_FIMC_YCRYCB422:
 490                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
 491                 break;
 492         case S5P_FIMC_CBYCRY422:
 493                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
 494                 break;
 495         case S5P_FIMC_CRYCBY422:
 496                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
 497                 break;
 498         case S5P_FIMC_YCBYCR422:
 499         default:
 500                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
 501                 break;
 502         }
 503         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 504
 505         switch (ctx->d_frame.fmt->color) {
 506         case S5P_FIMC_YCRYCB422:
 507                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
 508                 break;
 509         case S5P_FIMC_CBYCRY422:
 510                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
 511                 break;
 512         case S5P_FIMC_CRYCBY422:
 513                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
 514                 break;
 515         case S5P_FIMC_YCBYCR422:
 516         default:
 517                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
 518                 break;
 519         }
 520         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 521 }
 522
 523 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 524 {
 525         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 526         u32 i, depth = 0;
 527
 528         for (i = 0; i < f->fmt->colplanes; i++)
 529                 depth += f->fmt->depth[i];
 530
 531         f->dma_offset.y_h = f->offs_h;
 532         if (!variant->pix_hoff)
 533                 f->dma_offset.y_h *= (depth >> 3);
 534
 535         f->dma_offset.y_v = f->offs_v;
 536
 537         f->dma_offset.cb_h = f->offs_h;
 538         f->dma_offset.cb_v = f->offs_v;
 539
 540         f->dma_offset.cr_h = f->offs_h;
 541         f->dma_offset.cr_v = f->offs_v;
 542
 543         if (!variant->pix_hoff) {
 544                 if (f->fmt->colplanes == 3) {
 545                         f->dma_offset.cb_h >>= 1;
 546                         f->dma_offset.cr_h >>= 1;
 547                 }
 548                 if (f->fmt->color == S5P_FIMC_YCBCR420) {
 549                         f->dma_offset.cb_v >>= 1;
 550                         f->dma_offset.cr_v >>= 1;
 551                 }
 552         }
 553
 554         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 555             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 556 }
 557
 558 /**
 559  * fimc_prepare_config - check dimensions, operation and color mode
 560  *                       and pre-calculate offset and the scaling coefficients.
 561  *
 562  * @ctx: hardware context information
 563  * @flags: flags indicating which parameters to check/update
 564  *
 565  * Return: 0 if dimensions are valid or non zero otherwise.
 566  */
 567 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
 568 {
 569         struct fimc_frame *s_frame, *d_frame;
 570         struct vb2_buffer *vb = NULL;
 571         int ret = 0;
 572
 573         s_frame = &ctx->s_frame;
 574         d_frame = &ctx->d_frame;
 575
 576         if (flags & FIMC_PARAMS) {
 577                 /* Prepare the DMA offset ratios for scaler. */
 578                 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
 579                 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
 580
 581                 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
 582                     s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
 583                         err("out of scaler range");
 584                         return -EINVAL;
 585                 }
 586                 fimc_set_yuv_order(ctx);
 587         }
 588
 589         /* Input DMA mode is not allowed when the scaler is disabled. */
 590         ctx->scaler.enabled = 1;
 591
 592         if (flags & FIMC_SRC_ADDR) {
 593                 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
 594                 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
 595                 if (ret)
 596                         return ret;
 597         }
 598
 599         if (flags & FIMC_DST_ADDR) {
 600                 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
 601                 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
 602         }
 603
 604         return ret;
 605 }
 606
 607 static void fimc_dma_run(void *priv)
 608 {
 609         struct fimc_ctx *ctx = priv;
 610         struct fimc_dev *fimc;
 611         unsigned long flags;
 612         u32 ret;
 613
 614         if (WARN(!ctx, "null hardware context\n"))
 615                 return;
 616
 617         fimc = ctx->fimc_dev;
 618         spin_lock_irqsave(&fimc->slock, flags);
 619         set_bit(ST_M2M_PEND, &fimc->state);
 620
 621         spin_lock(&ctx->slock);
 622         ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
 623         ret = fimc_prepare_config(ctx, ctx->state);
 624         if (ret)
 625                 goto dma_unlock;
 626
 627         /* Reconfigure hardware if the context has changed. */
 628         if (fimc->m2m.ctx != ctx) {
 629                 ctx->state |= FIMC_PARAMS;
 630                 fimc->m2m.ctx = ctx;
 631         }
 632         fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
 633
 634         if (ctx->state & FIMC_PARAMS) {
 635                 fimc_hw_set_input_path(ctx);
 636                 fimc_hw_set_in_dma(ctx);
 637                 ret = fimc_set_scaler_info(ctx);
 638                 if (ret) {
 639                         spin_unlock(&fimc->slock);
 640                         goto dma_unlock;
 641                 }
 642                 fimc_hw_set_prescaler(ctx);
 643                 fimc_hw_set_mainscaler(ctx);
 644                 fimc_hw_set_target_format(ctx);
 645                 fimc_hw_set_rotation(ctx);
 646                 fimc_hw_set_effect(ctx);
 647         }
 648
 649         fimc_hw_set_output_path(ctx);
 650         if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
 651                 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
 652
 653         if (ctx->state & FIMC_PARAMS)
 654                 fimc_hw_set_out_dma(ctx);
 655
 656         fimc_activate_capture(ctx);
 657
 658         ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
 659                        FIMC_SRC_FMT | FIMC_DST_FMT);
 660         fimc_hw_activate_input_dma(fimc, true);
 661 dma_unlock:
 662         spin_unlock(&ctx->slock);
 663         spin_unlock_irqrestore(&fimc->slock, flags);
 664 }
 665
 666 static void fimc_job_abort(void *priv)
 667 {
 668         fimc_m2m_shutdown(priv);
 669 }
 670
 671 static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
 672                             unsigned int *num_planes, unsigned int sizes[],
 673                             void *allocators[])
 674 {
 675         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 676         struct fimc_frame *f;
 677         int i;
 678
 679         f = ctx_get_frame(ctx, vq->type);
 680         if (IS_ERR(f))
 681                 return PTR_ERR(f);
 682         /*
 683          * Return number of non-contigous planes (plane buffers)
 684          * depending on the configured color format.
 685          */
 686         if (!f->fmt)
 687                 return -EINVAL;
 688
 689         *num_planes = f->fmt->memplanes;
 690         for (i = 0; i < f->fmt->memplanes; i++) {
 691                 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
 692                 allocators[i] = ctx->fimc_dev->alloc_ctx;
 693         }
 694         return 0;
 695 }
 696
 697 static int fimc_buf_prepare(struct vb2_buffer *vb)
 698 {
 699         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 700         struct fimc_frame *frame;
 701         int i;
 702
 703         frame = ctx_get_frame(ctx, vb->vb2_queue->type);
 704         if (IS_ERR(frame))
 705                 return PTR_ERR(frame);
 706
 707         for (i = 0; i < frame->fmt->memplanes; i++)
 708                 vb2_set_plane_payload(vb, i, frame->payload[i]);
 709
 710         return 0;
 711 }
 712
 713 static void fimc_buf_queue(struct vb2_buffer *vb)
 714 {
 715         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 716
 717         dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
 718
 719         if (ctx->m2m_ctx)
 720                 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
 721 }
 722
 723 static void fimc_lock(struct vb2_queue *vq)
 724 {
 725         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 726         mutex_lock(&ctx->fimc_dev->lock);
 727 }
 728
 729 static void fimc_unlock(struct vb2_queue *vq)
 730 {
 731         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 732         mutex_unlock(&ctx->fimc_dev->lock);
 733 }
 734
 735 static struct vb2_ops fimc_qops = {
 736         .queue_setup     = fimc_queue_setup,
 737         .buf_prepare     = fimc_buf_prepare,
 738         .buf_queue       = fimc_buf_queue,
 739         .wait_prepare    = fimc_unlock,
 740         .wait_finish     = fimc_lock,
 741         .stop_streaming  = stop_streaming,
 742         .start_streaming = start_streaming,
 743 };
 744
 745 /*
 746  * V4L2 controls handling
 747  */
 748 #define ctrl_to_ctx(__ctrl) \
 749         container_of((__ctrl)->handler, struct fimc_ctx, ctrl_handler)
 750
 751 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
 752 {
 753         struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
 754         struct fimc_dev *fimc = ctx->fimc_dev;
 755         struct samsung_fimc_variant *variant = fimc->variant;
 756         unsigned long flags;
 757         int ret = 0;
 758
 759         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
 760                 return 0;
 761
 762         switch (ctrl->id) {
 763         case V4L2_CID_HFLIP:
 764                 spin_lock_irqsave(&ctx->slock, flags);
 765                 ctx->hflip = ctrl->val;
 766                 break;
 767
 768         case V4L2_CID_VFLIP:
 769                 spin_lock_irqsave(&ctx->slock, flags);
 770                 ctx->vflip = ctrl->val;
 771                 break;
 772
 773         case V4L2_CID_ROTATE:
 774                 if (fimc_capture_pending(fimc) ||
 775                     fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
 776                         ret = fimc_check_scaler_ratio(ctx->s_frame.width,
 777                                         ctx->s_frame.height, ctx->d_frame.width,
 778                                         ctx->d_frame.height, ctrl->val);
 779                 }
 780                 if (ret) {
 781                         v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
 782                         return -EINVAL;
 783                 }
 784                 if ((ctrl->val == 90 || ctrl->val == 270) &&
 785                     !variant->has_out_rot)
 786                         return -EINVAL;
 787                 spin_lock_irqsave(&ctx->slock, flags);
 788                 ctx->rotation = ctrl->val;
 789                 break;
 790
 791         default:
 792                 v4l2_err(fimc->v4l2_dev, "Invalid control: 0x%X\n", ctrl->id);
 793                 return -EINVAL;
 794         }
 795         ctx->state |= FIMC_PARAMS;
 796         set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
 797         spin_unlock_irqrestore(&ctx->slock, flags);
 798         return 0;
 799 }
 800
 801 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
 802         .s_ctrl = fimc_s_ctrl,
 803 };
 804
 805 int fimc_ctrls_create(struct fimc_ctx *ctx)
 806 {
 807         if (ctx->ctrls_rdy)
 808                 return 0;
 809         v4l2_ctrl_handler_init(&ctx->ctrl_handler, 3);
 810
 811         ctx->ctrl_rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 812                                      V4L2_CID_HFLIP, 0, 1, 1, 0);
 813         ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 814                                     V4L2_CID_VFLIP, 0, 1, 1, 0);
 815         ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 816                                     V4L2_CID_ROTATE, 0, 270, 90, 0);
 817         ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
 818
 819         return ctx->ctrl_handler.error;
 820 }
 821
 822 void fimc_ctrls_delete(struct fimc_ctx *ctx)
 823 {
 824         if (ctx->ctrls_rdy) {
 825                 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
 826                 ctx->ctrls_rdy = false;
 827         }
 828 }
 829
 830 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
 831 {
 832         if (!ctx->ctrls_rdy)
 833                 return;
 834
 835         mutex_lock(&ctx->ctrl_handler.lock);
 836         v4l2_ctrl_activate(ctx->ctrl_rotate, active);
 837         v4l2_ctrl_activate(ctx->ctrl_hflip, active);
 838         v4l2_ctrl_activate(ctx->ctrl_vflip, active);
 839
 840         if (active) {
 841                 ctx->rotation = ctx->ctrl_rotate->val;
 842                 ctx->hflip    = ctx->ctrl_hflip->val;
 843                 ctx->vflip    = ctx->ctrl_vflip->val;
 844         } else {
 845                 ctx->rotation = 0;
 846                 ctx->hflip    = 0;
 847                 ctx->vflip    = 0;
 848         }
 849         mutex_unlock(&ctx->ctrl_handler.lock);
 850 }
 851
 852 /*
 853  * V4L2 ioctl handlers
 854  */
 855 static int fimc_m2m_querycap(struct file *file, void *fh,
 856                              struct v4l2_capability *cap)
 857 {
 858         struct fimc_ctx *ctx = fh_to_ctx(fh);
 859         struct fimc_dev *fimc = ctx->fimc_dev;
 860
 861         strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
 862         strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
 863         cap->bus_info[0] = 0;
 864         cap->capabilities = V4L2_CAP_STREAMING |
 865                 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
 866                 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
 867
 868         return 0;
 869 }
 870
 871 static int fimc_m2m_enum_fmt_mplane(struct file *file, void *priv,
 872                                     struct v4l2_fmtdesc *f)
 873 {
 874         struct fimc_fmt *fmt;
 875
 876         fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_M2M, f->index);
 877         if (!fmt)
 878                 return -EINVAL;
 879
 880         strncpy(f->description, fmt->name, sizeof(f->description) - 1);
 881         f->pixelformat = fmt->fourcc;
 882         return 0;
 883 }
 884
 885 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f)
 886 {
 887         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 888         int i;
 889
 890         pixm->width = frame->o_width;
 891         pixm->height = frame->o_height;
 892         pixm->field = V4L2_FIELD_NONE;
 893         pixm->pixelformat = frame->fmt->fourcc;
 894         pixm->colorspace = V4L2_COLORSPACE_JPEG;
 895         pixm->num_planes = frame->fmt->memplanes;
 896
 897         for (i = 0; i < pixm->num_planes; ++i) {
 898                 int bpl = frame->f_width;
 899                 if (frame->fmt->colplanes == 1) /* packed formats */
 900                         bpl = (bpl * frame->fmt->depth[0]) / 8;
 901                 pixm->plane_fmt[i].bytesperline = bpl;
 902                 pixm->plane_fmt[i].sizeimage = (frame->o_width *
 903                         frame->o_height * frame->fmt->depth[i]) / 8;
 904         }
 905         return 0;
 906 }
 907
 908 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f)
 909 {
 910         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 911
 912         frame->f_width  = pixm->plane_fmt[0].bytesperline;
 913         if (frame->fmt->colplanes == 1)
 914                 frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0];
 915         frame->f_height = pixm->height;
 916         frame->width    = pixm->width;
 917         frame->height   = pixm->height;
 918         frame->o_width  = pixm->width;
 919         frame->o_height = pixm->height;
 920         frame->offs_h   = 0;
 921         frame->offs_v   = 0;
 922 }
 923
 924 /**
 925  * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
 926  * @fmt: fimc pixel format description (input)
 927  * @width: requested pixel width
 928  * @height: requested pixel height
 929  * @pix: multi-plane format to adjust
 930  */
 931 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
 932                                struct v4l2_pix_format_mplane *pix)
 933 {
 934         u32 bytesperline = 0;
 935         int i;
 936
 937         pix->colorspace = V4L2_COLORSPACE_JPEG;
 938         pix->field = V4L2_FIELD_NONE;
 939         pix->num_planes = fmt->memplanes;
 940         pix->height = height;
 941         pix->width = width;
 942
 943         for (i = 0; i < pix->num_planes; ++i) {
 944                 u32 bpl = pix->plane_fmt[i].bytesperline;
 945                 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
 946
 947                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
 948                         bpl = pix->width; /* Planar */
 949
 950                 if (fmt->colplanes == 1 && /* Packed */
 951                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
 952                         bpl = (pix->width * fmt->depth[0]) / 8;
 953
 954                 if (i == 0) /* Same bytesperline for each plane. */
 955                         bytesperline = bpl;
 956
 957                 pix->plane_fmt[i].bytesperline = bytesperline;
 958                 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
 959         }
 960 }
 961
 962 static int fimc_m2m_g_fmt_mplane(struct file *file, void *fh,
 963                                  struct v4l2_format *f)
 964 {
 965         struct fimc_ctx *ctx = fh_to_ctx(fh);
 966         struct fimc_frame *frame = ctx_get_frame(ctx, f->type);
 967
 968         if (IS_ERR(frame))
 969                 return PTR_ERR(frame);
 970
 971         return fimc_fill_format(frame, f);
 972 }
 973
 974 /**
 975  * fimc_find_format - lookup fimc color format by fourcc or media bus format
 976  * @pixelformat: fourcc to match, ignored if null
 977  * @mbus_code: media bus code to match, ignored if null
 978  * @mask: the color flags to match
 979  * @index: offset in the fimc_formats array, ignored if negative
 980  */
 981 struct fimc_fmt *fimc_find_format(u32 *pixelformat, u32 *mbus_code,
 982                                   unsigned int mask, int index)
 983 {
 984         struct fimc_fmt *fmt, *def_fmt = NULL;
 985         unsigned int i;
 986         int id = 0;
 987
 988         if (index >= ARRAY_SIZE(fimc_formats))
 989                 return NULL;
 990
 991         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
 992                 fmt = &fimc_formats[i];
 993                 if (!(fmt->flags & mask))
 994                         continue;
 995                 if (pixelformat && fmt->fourcc == *pixelformat)
 996                         return fmt;
 997                 if (mbus_code && fmt->mbus_code == *mbus_code)
 998                         return fmt;
 999                 if (index == id)
1000                         def_fmt = fmt;
1001                 id++;
1002         }
1003         return def_fmt;
1004 }
1005
1006 static int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f)
1007 {
1008         struct fimc_dev *fimc = ctx->fimc_dev;
1009         struct samsung_fimc_variant *variant = fimc->variant;
1010         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1011         struct fimc_fmt *fmt;
1012         u32 max_w, mod_x, mod_y;
1013
1014         if (!IS_M2M(f->type))
1015                 return -EINVAL;
1016
1017         dbg("w: %d, h: %d", pix->width, pix->height);
1018
1019         fmt = fimc_find_format(&pix->pixelformat, NULL, FMT_FLAGS_M2M, 0);
1020         if (WARN(fmt == NULL, "Pixel format lookup failed"))
1021                 return -EINVAL;
1022
1023         if (pix->field == V4L2_FIELD_ANY)
1024                 pix->field = V4L2_FIELD_NONE;
1025         else if (pix->field != V4L2_FIELD_NONE)
1026                 return -EINVAL;
1027
1028         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1029                 max_w = variant->pix_limit->scaler_dis_w;
1030                 mod_x = ffs(variant->min_inp_pixsize) - 1;
1031         } else {
1032                 max_w = variant->pix_limit->out_rot_dis_w;
1033                 mod_x = ffs(variant->min_out_pixsize) - 1;
1034         }
1035
1036         if (tiled_fmt(fmt)) {
1037                 mod_x = 6; /* 64 x 32 pixels tile */
1038                 mod_y = 5;
1039         } else {
1040                 if (fimc->id == 1 && variant->pix_hoff)
1041                         mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
1042                 else
1043                         mod_y = mod_x;
1044         }
1045         dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_w);
1046
1047         v4l_bound_align_image(&pix->width, 16, max_w, mod_x,
1048                 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
1049
1050         fimc_adjust_mplane_format(fmt, pix->width, pix->height, &f->fmt.pix_mp);
1051         return 0;
1052 }
1053
1054 static int fimc_m2m_try_fmt_mplane(struct file *file, void *fh,
1055                                    struct v4l2_format *f)
1056 {
1057         struct fimc_ctx *ctx = fh_to_ctx(fh);
1058
1059         return fimc_try_fmt_mplane(ctx, f);
1060 }
1061
1062 static int fimc_m2m_s_fmt_mplane(struct file *file, void *fh,
1063                                  struct v4l2_format *f)
1064 {
1065         struct fimc_ctx *ctx = fh_to_ctx(fh);
1066         struct fimc_dev *fimc = ctx->fimc_dev;
1067         struct vb2_queue *vq;
1068         struct fimc_frame *frame;
1069         struct v4l2_pix_format_mplane *pix;
1070         int i, ret = 0;
1071
1072         ret = fimc_try_fmt_mplane(ctx, f);
1073         if (ret)
1074                 return ret;
1075
1076         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1077
1078         if (vb2_is_busy(vq)) {
1079                 v4l2_err(fimc->m2m.vfd, "queue (%d) busy\n", f->type);
1080                 return -EBUSY;
1081         }
1082
1083         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1084                 frame = &ctx->s_frame;
1085         else
1086                 frame = &ctx->d_frame;
1087
1088         pix = &f->fmt.pix_mp;
1089         frame->fmt = fimc_find_format(&pix->pixelformat, NULL,
1090                                       FMT_FLAGS_M2M, 0);
1091         if (!frame->fmt)
1092                 return -EINVAL;
1093
1094         for (i = 0; i < frame->fmt->colplanes; i++) {
1095                 frame->payload[i] =
1096                         (pix->width * pix->height * frame->fmt->depth[i]) / 8;
1097         }
1098
1099         fimc_fill_frame(frame, f);
1100
1101         if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1102                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1103         else
1104                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1105
1106         dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1107
1108         return 0;
1109 }
1110
1111 static int fimc_m2m_reqbufs(struct file *file, void *fh,
1112                             struct v4l2_requestbuffers *reqbufs)
1113 {
1114         struct fimc_ctx *ctx = fh_to_ctx(fh);
1115
1116         return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1117 }
1118
1119 static int fimc_m2m_querybuf(struct file *file, void *fh,
1120                              struct v4l2_buffer *buf)
1121 {
1122         struct fimc_ctx *ctx = fh_to_ctx(fh);
1123
1124         return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1125 }
1126
1127 static int fimc_m2m_qbuf(struct file *file, void *fh,
1128                          struct v4l2_buffer *buf)
1129 {
1130         struct fimc_ctx *ctx = fh_to_ctx(fh);
1131
1132         return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1133 }
1134
1135 static int fimc_m2m_dqbuf(struct file *file, void *fh,
1136                           struct v4l2_buffer *buf)
1137 {
1138         struct fimc_ctx *ctx = fh_to_ctx(fh);
1139
1140         return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1141 }
1142
1143 static int fimc_m2m_streamon(struct file *file, void *fh,
1144                              enum v4l2_buf_type type)
1145 {
1146         struct fimc_ctx *ctx = fh_to_ctx(fh);
1147
1148         /* The source and target color format need to be set */
1149         if (V4L2_TYPE_IS_OUTPUT(type)) {
1150                 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1151                         return -EINVAL;
1152         } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1153                 return -EINVAL;
1154         }
1155
1156         return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1157 }
1158
1159 static int fimc_m2m_streamoff(struct file *file, void *fh,
1160                             enum v4l2_buf_type type)
1161 {
1162         struct fimc_ctx *ctx = fh_to_ctx(fh);
1163
1164         return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1165 }
1166
1167 static int fimc_m2m_cropcap(struct file *file, void *fh,
1168                             struct v4l2_cropcap *cr)
1169 {
1170         struct fimc_ctx *ctx = fh_to_ctx(fh);
1171         struct fimc_frame *frame;
1172
1173         frame = ctx_get_frame(ctx, cr->type);
1174         if (IS_ERR(frame))
1175                 return PTR_ERR(frame);
1176
1177         cr->bounds.left         = 0;
1178         cr->bounds.top          = 0;
1179         cr->bounds.width        = frame->o_width;
1180         cr->bounds.height       = frame->o_height;
1181         cr->defrect             = cr->bounds;
1182
1183         return 0;
1184 }
1185
1186 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1187 {
1188         struct fimc_ctx *ctx = fh_to_ctx(fh);
1189         struct fimc_frame *frame;
1190
1191         frame = ctx_get_frame(ctx, cr->type);
1192         if (IS_ERR(frame))
1193                 return PTR_ERR(frame);
1194
1195         cr->c.left = frame->offs_h;
1196         cr->c.top = frame->offs_v;
1197         cr->c.width = frame->width;
1198         cr->c.height = frame->height;
1199
1200         return 0;
1201 }
1202
1203 static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1204 {
1205         struct fimc_dev *fimc = ctx->fimc_dev;
1206         struct fimc_frame *f;
1207         u32 min_size, halign, depth = 0;
1208         int i;
1209
1210         if (cr->c.top < 0 || cr->c.left < 0) {
1211                 v4l2_err(fimc->m2m.vfd,
1212                         "doesn't support negative values for top & left\n");
1213                 return -EINVAL;
1214         }
1215         if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1216                 f = &ctx->d_frame;
1217         else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1218                 f = &ctx->s_frame;
1219         else
1220                 return -EINVAL;
1221
1222         min_size = (f == &ctx->s_frame) ?
1223                 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1224
1225         /* Get pixel alignment constraints. */
1226         if (fimc->id == 1 && fimc->variant->pix_hoff)
1227                 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1228         else
1229                 halign = ffs(min_size) - 1;
1230
1231         for (i = 0; i < f->fmt->colplanes; i++)
1232                 depth += f->fmt->depth[i];
1233
1234         v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1235                               ffs(min_size) - 1,
1236                               &cr->c.height, min_size, f->o_height,
1237                               halign, 64/(ALIGN(depth, 8)));
1238
1239         /* adjust left/top if cropping rectangle is out of bounds */
1240         if (cr->c.left + cr->c.width > f->o_width)
1241                 cr->c.left = f->o_width - cr->c.width;
1242         if (cr->c.top + cr->c.height > f->o_height)
1243                 cr->c.top = f->o_height - cr->c.height;
1244
1245         cr->c.left = round_down(cr->c.left, min_size);
1246         cr->c.top  = round_down(cr->c.top, fimc->variant->hor_offs_align);
1247
1248         dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1249             cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1250             f->f_width, f->f_height);
1251
1252         return 0;
1253 }
1254
1255 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1256 {
1257         struct fimc_ctx *ctx = fh_to_ctx(fh);
1258         struct fimc_dev *fimc = ctx->fimc_dev;
1259         struct fimc_frame *f;
1260         int ret;
1261
1262         ret = fimc_m2m_try_crop(ctx, cr);
1263         if (ret)
1264                 return ret;
1265
1266         f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1267                 &ctx->s_frame : &ctx->d_frame;
1268
1269         /* Check to see if scaling ratio is within supported range */
1270         if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1271                 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1272                         ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
1273                                                       ctx->d_frame.width,
1274                                                       ctx->d_frame.height,
1275                                                       ctx->rotation);
1276                 } else {
1277                         ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1278                                                       ctx->s_frame.height,
1279                                                       cr->c.width, cr->c.height,
1280                                                       ctx->rotation);
1281                 }
1282                 if (ret) {
1283                         v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
1284                         return -EINVAL;
1285                 }
1286         }
1287
1288         f->offs_h = cr->c.left;
1289         f->offs_v = cr->c.top;
1290         f->width  = cr->c.width;
1291         f->height = cr->c.height;
1292
1293         fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1294
1295         return 0;
1296 }
1297
1298 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1299         .vidioc_querycap                = fimc_m2m_querycap,
1300
1301         .vidioc_enum_fmt_vid_cap_mplane = fimc_m2m_enum_fmt_mplane,
1302         .vidioc_enum_fmt_vid_out_mplane = fimc_m2m_enum_fmt_mplane,
1303
1304         .vidioc_g_fmt_vid_cap_mplane    = fimc_m2m_g_fmt_mplane,
1305         .vidioc_g_fmt_vid_out_mplane    = fimc_m2m_g_fmt_mplane,
1306
1307         .vidioc_try_fmt_vid_cap_mplane  = fimc_m2m_try_fmt_mplane,
1308         .vidioc_try_fmt_vid_out_mplane  = fimc_m2m_try_fmt_mplane,
1309
1310         .vidioc_s_fmt_vid_cap_mplane    = fimc_m2m_s_fmt_mplane,
1311         .vidioc_s_fmt_vid_out_mplane    = fimc_m2m_s_fmt_mplane,
1312
1313         .vidioc_reqbufs                 = fimc_m2m_reqbufs,
1314         .vidioc_querybuf                = fimc_m2m_querybuf,
1315
1316         .vidioc_qbuf                    = fimc_m2m_qbuf,
1317         .vidioc_dqbuf                   = fimc_m2m_dqbuf,
1318
1319         .vidioc_streamon                = fimc_m2m_streamon,
1320         .vidioc_streamoff               = fimc_m2m_streamoff,
1321
1322         .vidioc_g_crop                  = fimc_m2m_g_crop,
1323         .vidioc_s_crop                  = fimc_m2m_s_crop,
1324         .vidioc_cropcap                 = fimc_m2m_cropcap
1325
1326 };
1327
1328 static int queue_init(void *priv, struct vb2_queue *src_vq,
1329                       struct vb2_queue *dst_vq)
1330 {
1331         struct fimc_ctx *ctx = priv;
1332         int ret;
1333
1334         memset(src_vq, 0, sizeof(*src_vq));
1335         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1336         src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1337         src_vq->drv_priv = ctx;
1338         src_vq->ops = &fimc_qops;
1339         src_vq->mem_ops = &vb2_dma_contig_memops;
1340         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1341
1342         ret = vb2_queue_init(src_vq);
1343         if (ret)
1344                 return ret;
1345
1346         memset(dst_vq, 0, sizeof(*dst_vq));
1347         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1348         dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1349         dst_vq->drv_priv = ctx;
1350         dst_vq->ops = &fimc_qops;
1351         dst_vq->mem_ops = &vb2_dma_contig_memops;
1352         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1353
1354         return vb2_queue_init(dst_vq);
1355 }
1356
1357 static int fimc_m2m_open(struct file *file)
1358 {
1359         struct fimc_dev *fimc = video_drvdata(file);
1360         struct fimc_ctx *ctx;
1361         int ret;
1362
1363         dbg("pid: %d, state: 0x%lx, refcnt: %d",
1364                 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1365
1366         /*
1367          * Return if the corresponding video capture node
1368          * is already opened.
1369          */
1370         if (fimc->vid_cap.refcnt > 0)
1371                 return -EBUSY;
1372
1373         ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1374         if (!ctx)
1375                 return -ENOMEM;
1376         v4l2_fh_init(&ctx->fh, fimc->m2m.vfd);
1377         ret = fimc_ctrls_create(ctx);
1378         if (ret)
1379                 goto error_fh;
1380
1381         /* Use separate control handler per file handle */
1382         ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1383         file->private_data = &ctx->fh;
1384         v4l2_fh_add(&ctx->fh);
1385
1386         ctx->fimc_dev = fimc;
1387         /* Default color format */
1388         ctx->s_frame.fmt = &fimc_formats[0];
1389         ctx->d_frame.fmt = &fimc_formats[0];
1390         /* Setup the device context for memory-to-memory mode */
1391         ctx->state = FIMC_CTX_M2M;
1392         ctx->flags = 0;
1393         ctx->in_path = FIMC_DMA;
1394         ctx->out_path = FIMC_DMA;
1395         spin_lock_init(&ctx->slock);
1396
1397         ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1398         if (IS_ERR(ctx->m2m_ctx)) {
1399                 ret = PTR_ERR(ctx->m2m_ctx);
1400                 goto error_c;
1401         }
1402
1403         if (fimc->m2m.refcnt++ == 0)
1404                 set_bit(ST_M2M_RUN, &fimc->state);
1405         return 0;
1406
1407 error_c:
1408         fimc_ctrls_delete(ctx);
1409 error_fh:
1410         v4l2_fh_del(&ctx->fh);
1411         v4l2_fh_exit(&ctx->fh);
1412         kfree(ctx);
1413         return ret;
1414 }
1415
1416 static int fimc_m2m_release(struct file *file)
1417 {
1418         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1419         struct fimc_dev *fimc = ctx->fimc_dev;
1420
1421         dbg("pid: %d, state: 0x%lx, refcnt= %d",
1422                 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1423
1424         v4l2_m2m_ctx_release(ctx->m2m_ctx);
1425         fimc_ctrls_delete(ctx);
1426         v4l2_fh_del(&ctx->fh);
1427         v4l2_fh_exit(&ctx->fh);
1428
1429         if (--fimc->m2m.refcnt <= 0)
1430                 clear_bit(ST_M2M_RUN, &fimc->state);
1431         kfree(ctx);
1432         return 0;
1433 }
1434
1435 static unsigned int fimc_m2m_poll(struct file *file,
1436                                   struct poll_table_struct *wait)
1437 {
1438         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1439
1440         return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1441 }
1442
1443
1444 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1445 {
1446         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1447
1448         return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1449 }
1450
1451 static const struct v4l2_file_operations fimc_m2m_fops = {
1452         .owner          = THIS_MODULE,
1453         .open           = fimc_m2m_open,
1454         .release        = fimc_m2m_release,
1455         .poll           = fimc_m2m_poll,
1456         .unlocked_ioctl = video_ioctl2,
1457         .mmap           = fimc_m2m_mmap,
1458 };
1459
1460 static struct v4l2_m2m_ops m2m_ops = {
1461         .device_run     = fimc_dma_run,
1462         .job_abort      = fimc_job_abort,
1463 };
1464
1465 int fimc_register_m2m_device(struct fimc_dev *fimc,
1466                              struct v4l2_device *v4l2_dev)
1467 {
1468         struct video_device *vfd;
1469         struct platform_device *pdev;
1470         int ret = 0;
1471
1472         if (!fimc)
1473                 return -ENODEV;
1474
1475         pdev = fimc->pdev;
1476         fimc->v4l2_dev = v4l2_dev;
1477
1478         vfd = video_device_alloc();
1479         if (!vfd) {
1480                 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1481                 return -ENOMEM;
1482         }
1483
1484         vfd->fops       = &fimc_m2m_fops;
1485         vfd->ioctl_ops  = &fimc_m2m_ioctl_ops;
1486         vfd->v4l2_dev   = v4l2_dev;
1487         vfd->minor      = -1;
1488         vfd->release    = video_device_release;
1489         vfd->lock       = &fimc->lock;
1490
1491         snprintf(vfd->name, sizeof(vfd->name), "%s.m2m", dev_name(&pdev->dev));
1492         video_set_drvdata(vfd, fimc);
1493
1494         fimc->m2m.vfd = vfd;
1495         fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1496         if (IS_ERR(fimc->m2m.m2m_dev)) {
1497                 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1498                 ret = PTR_ERR(fimc->m2m.m2m_dev);
1499                 goto err_init;
1500         }
1501
1502         ret = media_entity_init(&vfd->entity, 0, NULL, 0);
1503         if (!ret)
1504                 return 0;
1505
1506         v4l2_m2m_release(fimc->m2m.m2m_dev);
1507 err_init:
1508         video_device_release(fimc->m2m.vfd);
1509         return ret;
1510 }
1511
1512 void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1513 {
1514         if (!fimc)
1515                 return;
1516
1517         if (fimc->m2m.m2m_dev)
1518                 v4l2_m2m_release(fimc->m2m.m2m_dev);
1519         if (fimc->m2m.vfd) {
1520                 media_entity_cleanup(&fimc->m2m.vfd->entity);
1521                 /* Can also be called if video device wasn't registered */
1522                 video_unregister_device(fimc->m2m.vfd);
1523         }
1524 }
1525
1526 static void fimc_clk_put(struct fimc_dev *fimc)
1527 {
1528         int i;
1529         for (i = 0; i < fimc->num_clocks; i++) {
1530                 if (fimc->clock[i])
1531                         clk_put(fimc->clock[i]);
1532         }
1533 }
1534
1535 static int fimc_clk_get(struct fimc_dev *fimc)
1536 {
1537         int i;
1538         for (i = 0; i < fimc->num_clocks; i++) {
1539                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1540                 if (!IS_ERR_OR_NULL(fimc->clock[i]))
1541                         continue;
1542                 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1543                         fimc_clocks[i]);
1544                 return -ENXIO;
1545         }
1546
1547         return 0;
1548 }
1549
1550 static int fimc_m2m_suspend(struct fimc_dev *fimc)
1551 {
1552         unsigned long flags;
1553         int timeout;
1554
1555         spin_lock_irqsave(&fimc->slock, flags);
1556         if (!fimc_m2m_pending(fimc)) {
1557                 spin_unlock_irqrestore(&fimc->slock, flags);
1558                 return 0;
1559         }
1560         clear_bit(ST_M2M_SUSPENDED, &fimc->state);
1561         set_bit(ST_M2M_SUSPENDING, &fimc->state);
1562         spin_unlock_irqrestore(&fimc->slock, flags);
1563
1564         timeout = wait_event_timeout(fimc->irq_queue,
1565                              test_bit(ST_M2M_SUSPENDED, &fimc->state),
1566                              FIMC_SHUTDOWN_TIMEOUT);
1567
1568         clear_bit(ST_M2M_SUSPENDING, &fimc->state);
1569         return timeout == 0 ? -EAGAIN : 0;
1570 }
1571
1572 static int fimc_m2m_resume(struct fimc_dev *fimc)
1573 {
1574         unsigned long flags;
1575
1576         spin_lock_irqsave(&fimc->slock, flags);
1577         /* Clear for full H/W setup in first run after resume */
1578         fimc->m2m.ctx = NULL;
1579         spin_unlock_irqrestore(&fimc->slock, flags);
1580
1581         if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
1582                 fimc_m2m_job_finish(fimc->m2m.ctx,
1583                                     VB2_BUF_STATE_ERROR);
1584         return 0;
1585 }
1586
1587 static int fimc_probe(struct platform_device *pdev)
1588 {
1589         struct fimc_dev *fimc;
1590         struct resource *res;
1591         struct samsung_fimc_driverdata *drv_data;
1592         struct s5p_platform_fimc *pdata;
1593         int ret = 0;
1594
1595         dev_dbg(&pdev->dev, "%s():\n", __func__);
1596
1597         drv_data = (struct samsung_fimc_driverdata *)
1598                 platform_get_device_id(pdev)->driver_data;
1599
1600         if (pdev->id >= drv_data->num_entities) {
1601                 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1602                         pdev->id);
1603                 return -EINVAL;
1604         }
1605
1606         fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1607         if (!fimc)
1608                 return -ENOMEM;
1609
1610         fimc->id = pdev->id;
1611
1612         fimc->variant = drv_data->variant[fimc->id];
1613         fimc->pdev = pdev;
1614         pdata = pdev->dev.platform_data;
1615         fimc->pdata = pdata;
1616
1617         set_bit(ST_LPM, &fimc->state);
1618
1619         init_waitqueue_head(&fimc->irq_queue);
1620         spin_lock_init(&fimc->slock);
1621         mutex_init(&fimc->lock);
1622
1623         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1624         if (!res) {
1625                 dev_err(&pdev->dev, "failed to find the registers\n");
1626                 ret = -ENOENT;
1627                 goto err_info;
1628         }
1629
1630         fimc->regs_res = request_mem_region(res->start, resource_size(res),
1631                         dev_name(&pdev->dev));
1632         if (!fimc->regs_res) {
1633                 dev_err(&pdev->dev, "failed to obtain register region\n");
1634                 ret = -ENOENT;
1635                 goto err_info;
1636         }
1637
1638         fimc->regs = ioremap(res->start, resource_size(res));
1639         if (!fimc->regs) {
1640                 dev_err(&pdev->dev, "failed to map registers\n");
1641                 ret = -ENXIO;
1642                 goto err_req_region;
1643         }
1644
1645         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1646         if (!res) {
1647                 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1648                 ret = -ENXIO;
1649                 goto err_regs_unmap;
1650         }
1651         fimc->irq = res->start;
1652
1653         fimc->num_clocks = MAX_FIMC_CLOCKS;
1654         ret = fimc_clk_get(fimc);
1655         if (ret)
1656                 goto err_regs_unmap;
1657         clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1658         clk_enable(fimc->clock[CLK_BUS]);
1659
1660         platform_set_drvdata(pdev, fimc);
1661
1662         ret = request_irq(fimc->irq, fimc_irq_handler, 0, pdev->name, fimc);
1663         if (ret) {
1664                 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1665                 goto err_clk;
1666         }
1667
1668         pm_runtime_enable(&pdev->dev);
1669         ret = pm_runtime_get_sync(&pdev->dev);
1670         if (ret < 0)
1671                 goto err_irq;
1672         /* Initialize contiguous memory allocator */
1673         fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1674         if (IS_ERR(fimc->alloc_ctx)) {
1675                 ret = PTR_ERR(fimc->alloc_ctx);
1676                 goto err_pm;
1677         }
1678
1679         dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id);
1680
1681         pm_runtime_put(&pdev->dev);
1682         return 0;
1683
1684 err_pm:
1685         pm_runtime_put(&pdev->dev);
1686 err_irq:
1687         free_irq(fimc->irq, fimc);
1688 err_clk:
1689         fimc_clk_put(fimc);
1690 err_regs_unmap:
1691         iounmap(fimc->regs);
1692 err_req_region:
1693         release_resource(fimc->regs_res);
1694         kfree(fimc->regs_res);
1695 err_info:
1696         kfree(fimc);
1697         return ret;
1698 }
1699
1700 static int fimc_runtime_resume(struct device *dev)
1701 {
1702         struct fimc_dev *fimc = dev_get_drvdata(dev);
1703
1704         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1705
1706         /* Enable clocks and perform basic initalization */
1707         clk_enable(fimc->clock[CLK_GATE]);
1708         fimc_hw_reset(fimc);
1709         if (fimc->variant->out_buf_count > 4)
1710                 fimc_hw_set_dma_seq(fimc, 0xF);
1711
1712         /* Resume the capture or mem-to-mem device */
1713         if (fimc_capture_busy(fimc))
1714                 return fimc_capture_resume(fimc);
1715         else if (fimc_m2m_pending(fimc))
1716                 return fimc_m2m_resume(fimc);
1717         return 0;
1718 }
1719
1720 static int fimc_runtime_suspend(struct device *dev)
1721 {
1722         struct fimc_dev *fimc = dev_get_drvdata(dev);
1723         int ret = 0;
1724
1725         if (fimc_capture_busy(fimc))
1726                 ret = fimc_capture_suspend(fimc);
1727         else
1728                 ret = fimc_m2m_suspend(fimc);
1729         if (!ret)
1730                 clk_disable(fimc->clock[CLK_GATE]);
1731
1732         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1733         return ret;
1734 }
1735
1736 #ifdef CONFIG_PM_SLEEP
1737 static int fimc_resume(struct device *dev)
1738 {
1739         struct fimc_dev *fimc = dev_get_drvdata(dev);
1740         unsigned long flags;
1741
1742         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1743
1744         /* Do not resume if the device was idle before system suspend */
1745         spin_lock_irqsave(&fimc->slock, flags);
1746         if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1747             (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1748                 spin_unlock_irqrestore(&fimc->slock, flags);
1749                 return 0;
1750         }
1751         fimc_hw_reset(fimc);
1752         if (fimc->variant->out_buf_count > 4)
1753                 fimc_hw_set_dma_seq(fimc, 0xF);
1754         spin_unlock_irqrestore(&fimc->slock, flags);
1755
1756         if (fimc_capture_busy(fimc))
1757                 return fimc_capture_resume(fimc);
1758
1759         return fimc_m2m_resume(fimc);
1760 }
1761
1762 static int fimc_suspend(struct device *dev)
1763 {
1764         struct fimc_dev *fimc = dev_get_drvdata(dev);
1765
1766         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1767
1768         if (test_and_set_bit(ST_LPM, &fimc->state))
1769                 return 0;
1770         if (fimc_capture_busy(fimc))
1771                 return fimc_capture_suspend(fimc);
1772
1773         return fimc_m2m_suspend(fimc);
1774 }
1775 #endif /* CONFIG_PM_SLEEP */
1776
1777 static int __devexit fimc_remove(struct platform_device *pdev)
1778 {
1779         struct fimc_dev *fimc = platform_get_drvdata(pdev);
1780
1781         pm_runtime_disable(&pdev->dev);
1782         fimc_runtime_suspend(&pdev->dev);
1783         pm_runtime_set_suspended(&pdev->dev);
1784
1785         vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1786
1787         clk_disable(fimc->clock[CLK_BUS]);
1788         fimc_clk_put(fimc);
1789         free_irq(fimc->irq, fimc);
1790         iounmap(fimc->regs);
1791         release_resource(fimc->regs_res);
1792         kfree(fimc->regs_res);
1793         kfree(fimc);
1794
1795         dev_info(&pdev->dev, "driver unloaded\n");
1796         return 0;
1797 }
1798
1799 /* Image pixel limits, similar across several FIMC HW revisions. */
1800 static struct fimc_pix_limit s5p_pix_limit[4] = {
1801         [0] = {
1802                 .scaler_en_w    = 3264,
1803                 .scaler_dis_w   = 8192,
1804                 .in_rot_en_h    = 1920,
1805                 .in_rot_dis_w   = 8192,
1806                 .out_rot_en_w   = 1920,
1807                 .out_rot_dis_w  = 4224,
1808         },
1809         [1] = {
1810                 .scaler_en_w    = 4224,
1811                 .scaler_dis_w   = 8192,
1812                 .in_rot_en_h    = 1920,
1813                 .in_rot_dis_w   = 8192,
1814                 .out_rot_en_w   = 1920,
1815                 .out_rot_dis_w  = 4224,
1816         },
1817         [2] = {
1818                 .scaler_en_w    = 1920,
1819                 .scaler_dis_w   = 8192,
1820                 .in_rot_en_h    = 1280,
1821                 .in_rot_dis_w   = 8192,
1822                 .out_rot_en_w   = 1280,
1823                 .out_rot_dis_w  = 1920,
1824         },
1825         [3] = {
1826                 .scaler_en_w    = 1920,
1827                 .scaler_dis_w   = 8192,
1828                 .in_rot_en_h    = 1366,
1829                 .in_rot_dis_w   = 8192,
1830                 .out_rot_en_w   = 1366,
1831                 .out_rot_dis_w  = 1920,
1832         },
1833 };
1834
1835 static struct samsung_fimc_variant fimc0_variant_s5p = {
1836         .has_inp_rot     = 1,
1837         .has_out_rot     = 1,
1838         .has_cam_if      = 1,
1839         .min_inp_pixsize = 16,
1840         .min_out_pixsize = 16,
1841         .hor_offs_align  = 8,
1842         .out_buf_count   = 4,
1843         .pix_limit       = &s5p_pix_limit[0],
1844 };
1845
1846 static struct samsung_fimc_variant fimc2_variant_s5p = {
1847         .has_cam_if      = 1,
1848         .min_inp_pixsize = 16,
1849         .min_out_pixsize = 16,
1850         .hor_offs_align  = 8,
1851         .out_buf_count   = 4,
1852         .pix_limit = &s5p_pix_limit[1],
1853 };
1854
1855 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1856         .pix_hoff        = 1,
1857         .has_inp_rot     = 1,
1858         .has_out_rot     = 1,
1859         .has_cam_if      = 1,
1860         .min_inp_pixsize = 16,
1861         .min_out_pixsize = 16,
1862         .hor_offs_align  = 8,
1863         .out_buf_count   = 4,
1864         .pix_limit       = &s5p_pix_limit[1],
1865 };
1866
1867 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1868         .pix_hoff        = 1,
1869         .has_inp_rot     = 1,
1870         .has_out_rot     = 1,
1871         .has_cam_if      = 1,
1872         .has_mainscaler_ext = 1,
1873         .min_inp_pixsize = 16,
1874         .min_out_pixsize = 16,
1875         .hor_offs_align  = 1,
1876         .out_buf_count   = 4,
1877         .pix_limit       = &s5p_pix_limit[2],
1878 };
1879
1880 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1881         .has_cam_if      = 1,
1882         .pix_hoff        = 1,
1883         .min_inp_pixsize = 16,
1884         .min_out_pixsize = 16,
1885         .hor_offs_align  = 8,
1886         .out_buf_count   = 4,
1887         .pix_limit       = &s5p_pix_limit[2],
1888 };
1889
1890 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1891         .pix_hoff        = 1,
1892         .has_inp_rot     = 1,
1893         .has_out_rot     = 1,
1894         .has_cam_if      = 1,
1895         .has_cistatus2   = 1,
1896         .has_mainscaler_ext = 1,
1897         .min_inp_pixsize = 16,
1898         .min_out_pixsize = 16,
1899         .hor_offs_align  = 1,
1900         .out_buf_count   = 32,
1901         .pix_limit       = &s5p_pix_limit[1],
1902 };
1903
1904 static struct samsung_fimc_variant fimc3_variant_exynos4 = {
1905         .pix_hoff        = 1,
1906         .has_cam_if      = 1,
1907         .has_cistatus2   = 1,
1908         .has_mainscaler_ext = 1,
1909         .min_inp_pixsize = 16,
1910         .min_out_pixsize = 16,
1911         .hor_offs_align  = 1,
1912         .out_buf_count   = 32,
1913         .pix_limit       = &s5p_pix_limit[3],
1914 };
1915
1916 /* S5PC100 */
1917 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1918         .variant = {
1919                 [0] = &fimc0_variant_s5p,
1920                 [1] = &fimc0_variant_s5p,
1921                 [2] = &fimc2_variant_s5p,
1922         },
1923         .num_entities = 3,
1924         .lclk_frequency = 133000000UL,
1925 };
1926
1927 /* S5PV210, S5PC110 */
1928 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1929         .variant = {
1930                 [0] = &fimc0_variant_s5pv210,
1931                 [1] = &fimc1_variant_s5pv210,
1932                 [2] = &fimc2_variant_s5pv210,
1933         },
1934         .num_entities = 3,
1935         .lclk_frequency = 166000000UL,
1936 };
1937
1938 /* S5PV310, S5PC210 */
1939 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1940         .variant = {
1941                 [0] = &fimc0_variant_exynos4,
1942                 [1] = &fimc0_variant_exynos4,
1943                 [2] = &fimc0_variant_exynos4,
1944                 [3] = &fimc3_variant_exynos4,
1945         },
1946         .num_entities = 4,
1947         .lclk_frequency = 166000000UL,
1948 };
1949
1950 static struct platform_device_id fimc_driver_ids[] = {
1951         {
1952                 .name           = "s5p-fimc",
1953                 .driver_data    = (unsigned long)&fimc_drvdata_s5p,
1954         }, {
1955                 .name           = "s5pv210-fimc",
1956                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
1957         }, {
1958                 .name           = "exynos4-fimc",
1959                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4,
1960         },
1961         {},
1962 };
1963 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1964
1965 static const struct dev_pm_ops fimc_pm_ops = {
1966         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1967         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1968 };
1969
1970 static struct platform_driver fimc_driver = {
1971         .probe          = fimc_probe,
1972         .remove         = __devexit_p(fimc_remove),
1973         .id_table       = fimc_driver_ids,
1974         .driver = {
1975                 .name   = FIMC_MODULE_NAME,
1976                 .owner  = THIS_MODULE,
1977                 .pm     = &fimc_pm_ops,
1978         }
1979 };
1980
1981 int __init fimc_register_driver(void)
1982 {
1983         return platform_driver_probe(&fimc_driver, fimc_probe);
1984 }
1985
1986 void __exit fimc_unregister_driver(void)
1987 {
1988         platform_driver_unregister(&fimc_driver);
1989 }