2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
35 #include <linux/videodev2.h>
38 #include <mach/camera.h>
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
43 /* Camera Interface */
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
168 enum pxa_camera_active_dma {
174 /* descriptor needed for the PXA DMA engine */
177 struct pxa_dma_desc *sg_cpu;
182 /* buffer for one video frame */
184 /* common v4l buffer stuff -- must be first */
185 struct videobuf_buffer vb;
187 const struct soc_camera_data_format *fmt;
189 /* our descriptor lists for Y, U and V channels */
190 struct pxa_cam_dma dmas[3];
194 enum pxa_camera_active_dma active_dma;
197 struct pxa_camera_dev {
198 struct soc_camera_host soc_host;
199 /* PXA27x is only supposed to handle one camera on its Quick Capture
200 * interface. If anyone ever builds hardware to enable more than
201 * one camera, they will have to modify this driver too */
202 struct soc_camera_device *icd;
209 unsigned int dma_chans[3];
211 struct pxacamera_platform_data *pdata;
212 struct resource *res;
213 unsigned long platform_flags;
218 struct list_head capture;
222 struct pxa_buffer *active;
223 struct pxa_dma_desc *sg_tail[3];
228 static const char *pxa_cam_driver_description = "PXA_Camera";
230 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
233 * Videobuf operations
235 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
238 struct soc_camera_device *icd = vq->priv_data;
240 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
242 *size = roundup(icd->rect_current.width * icd->rect_current.height *
243 ((icd->current_fmt->depth + 7) >> 3), 8);
247 while (*size * *count > vid_limit * 1024 * 1024)
253 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
255 struct soc_camera_device *icd = vq->priv_data;
256 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
257 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
260 BUG_ON(in_interrupt());
262 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
263 &buf->vb, buf->vb.baddr, buf->vb.bsize);
265 /* This waits until this buffer is out of danger, i.e., until it is no
266 * longer in STATE_QUEUED or STATE_ACTIVE */
267 videobuf_waiton(&buf->vb, 0, 0);
268 videobuf_dma_unmap(vq, dma);
269 videobuf_dma_free(dma);
271 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
272 if (buf->dmas[i].sg_cpu)
273 dma_free_coherent(ici->v4l2_dev.dev, buf->dmas[i].sg_size,
275 buf->dmas[i].sg_dma);
276 buf->dmas[i].sg_cpu = NULL;
279 buf->vb.state = VIDEOBUF_NEEDS_INIT;
282 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
283 int sg_first_ofs, int size)
285 int i, offset, dma_len, xfer_len;
286 struct scatterlist *sg;
288 offset = sg_first_ofs;
289 for_each_sg(sglist, sg, sglen, i) {
290 dma_len = sg_dma_len(sg);
292 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
293 xfer_len = roundup(min(dma_len - offset, size), 8);
295 size = max(0, size - xfer_len);
306 * pxa_init_dma_channel - init dma descriptors
307 * @pcdev: pxa camera device
308 * @buf: pxa buffer to find pxa dma channel
309 * @dma: dma video buffer
310 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
311 * @cibr: camera Receive Buffer Register
312 * @size: bytes to transfer
313 * @sg_first: first element of sg_list
314 * @sg_first_ofs: offset in first element of sg_list
316 * Prepares the pxa dma descriptors to transfer one camera channel.
317 * Beware sg_first and sg_first_ofs are both input and output parameters.
319 * Returns 0 or -ENOMEM if no coherent memory is available
321 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
322 struct pxa_buffer *buf,
323 struct videobuf_dmabuf *dma, int channel,
325 struct scatterlist **sg_first, int *sg_first_ofs)
327 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
328 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
329 struct scatterlist *sg;
330 int i, offset, sglen;
331 int dma_len = 0, xfer_len = 0;
334 dma_free_coherent(dev, pxa_dma->sg_size,
335 pxa_dma->sg_cpu, pxa_dma->sg_dma);
337 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
338 *sg_first_ofs, size);
340 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
341 pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
342 &pxa_dma->sg_dma, GFP_KERNEL);
343 if (!pxa_dma->sg_cpu)
346 pxa_dma->sglen = sglen;
347 offset = *sg_first_ofs;
349 dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
350 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
353 for_each_sg(*sg_first, sg, sglen, i) {
354 dma_len = sg_dma_len(sg);
356 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
357 xfer_len = roundup(min(dma_len - offset, size), 8);
359 size = max(0, size - xfer_len);
361 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
362 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
363 pxa_dma->sg_cpu[i].dcmd =
364 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
367 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
369 pxa_dma->sg_cpu[i].ddadr =
370 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
372 dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
373 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
374 sg_dma_address(sg) + offset, xfer_len);
381 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
382 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
385 * Handle 1 special case :
386 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
387 * to dma_len (end on PAGE boundary). In this case, the sg element
388 * for next plane should be the next after the last used to store the
389 * last scatter gather RAM page
391 if (xfer_len >= dma_len) {
392 *sg_first_ofs = xfer_len - dma_len;
393 *sg_first = sg_next(sg);
395 *sg_first_ofs = xfer_len;
402 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
403 struct pxa_buffer *buf)
405 buf->active_dma = DMA_Y;
406 if (pcdev->channels == 3)
407 buf->active_dma |= DMA_U | DMA_V;
411 * Please check the DMA prepared buffer structure in :
412 * Documentation/video4linux/pxa_camera.txt
413 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
414 * modification while DMA chain is running will work anyway.
416 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
417 struct videobuf_buffer *vb, enum v4l2_field field)
419 struct soc_camera_device *icd = vq->priv_data;
420 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
421 struct pxa_camera_dev *pcdev = ici->priv;
422 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
423 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
425 int size_y, size_u = 0, size_v = 0;
427 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
428 vb, vb->baddr, vb->bsize);
430 /* Added list head initialization on alloc */
431 WARN_ON(!list_empty(&vb->queue));
434 /* This can be useful if you want to see if we actually fill
435 * the buffer with something */
436 memset((void *)vb->baddr, 0xaa, vb->bsize);
439 BUG_ON(NULL == icd->current_fmt);
441 /* I think, in buf_prepare you only have to protect global data,
442 * the actual buffer is yours */
445 if (buf->fmt != icd->current_fmt ||
446 vb->width != icd->rect_current.width ||
447 vb->height != icd->rect_current.height ||
448 vb->field != field) {
449 buf->fmt = icd->current_fmt;
450 vb->width = icd->rect_current.width;
451 vb->height = icd->rect_current.height;
453 vb->state = VIDEOBUF_NEEDS_INIT;
456 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
457 if (0 != vb->baddr && vb->bsize < vb->size) {
462 if (vb->state == VIDEOBUF_NEEDS_INIT) {
465 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
466 struct scatterlist *sg;
468 ret = videobuf_iolock(vq, vb, NULL);
472 if (pcdev->channels == 3) {
474 size_u = size_v = size / 4;
481 /* init DMA for Y channel */
482 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
485 dev_err(dev, "DMA initialization for Y/RGB failed\n");
489 /* init DMA for U channel */
491 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
492 size_u, &sg, &next_ofs);
494 dev_err(dev, "DMA initialization for U failed\n");
498 /* init DMA for V channel */
500 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
501 size_v, &sg, &next_ofs);
503 dev_err(dev, "DMA initialization for V failed\n");
507 vb->state = VIDEOBUF_PREPARED;
511 pxa_videobuf_set_actdma(pcdev, buf);
516 dma_free_coherent(dev, buf->dmas[1].sg_size,
517 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
519 dma_free_coherent(dev, buf->dmas[0].sg_size,
520 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
522 free_buffer(vq, buf);
529 * pxa_dma_start_channels - start DMA channel for active buffer
530 * @pcdev: pxa camera device
532 * Initialize DMA channels to the beginning of the active video buffer, and
533 * start these channels.
535 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
538 struct pxa_buffer *active;
540 active = pcdev->active;
542 for (i = 0; i < pcdev->channels; i++) {
543 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s (channel=%d) ddadr=%08x\n", __func__,
544 i, active->dmas[i].sg_dma);
545 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
546 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
550 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
554 for (i = 0; i < pcdev->channels; i++) {
555 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s (channel=%d)\n", __func__, i);
556 DCSR(pcdev->dma_chans[i]) = 0;
560 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
561 struct pxa_buffer *buf)
564 struct pxa_dma_desc *buf_last_desc;
566 for (i = 0; i < pcdev->channels; i++) {
567 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
568 buf_last_desc->ddadr = DDADR_STOP;
570 if (pcdev->sg_tail[i])
571 /* Link the new buffer to the old tail */
572 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
574 /* Update the channel tail */
575 pcdev->sg_tail[i] = buf_last_desc;
580 * pxa_camera_start_capture - start video capturing
581 * @pcdev: camera device
583 * Launch capturing. DMA channels should not be active yet. They should get
584 * activated at the end of frame interrupt, to capture only whole frames, and
585 * never begin the capture of a partial frame.
587 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
589 unsigned long cicr0, cifr;
591 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
592 /* Reset the FIFOs */
593 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
594 __raw_writel(cifr, pcdev->base + CIFR);
595 /* Enable End-Of-Frame Interrupt */
596 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
597 cicr0 &= ~CICR0_EOFM;
598 __raw_writel(cicr0, pcdev->base + CICR0);
601 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
605 pxa_dma_stop_channels(pcdev);
607 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
608 __raw_writel(cicr0, pcdev->base + CICR0);
610 pcdev->active = NULL;
611 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
614 /* Called under spinlock_irqsave(&pcdev->lock, ...) */
615 static void pxa_videobuf_queue(struct videobuf_queue *vq,
616 struct videobuf_buffer *vb)
618 struct soc_camera_device *icd = vq->priv_data;
619 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
620 struct pxa_camera_dev *pcdev = ici->priv;
621 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
623 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d active=%p\n", __func__,
624 vb, vb->baddr, vb->bsize, pcdev->active);
626 list_add_tail(&vb->queue, &pcdev->capture);
628 vb->state = VIDEOBUF_ACTIVE;
629 pxa_dma_add_tail_buf(pcdev, buf);
632 pxa_camera_start_capture(pcdev);
635 static void pxa_videobuf_release(struct videobuf_queue *vq,
636 struct videobuf_buffer *vb)
638 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
640 struct soc_camera_device *icd = vq->priv_data;
642 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
643 vb, vb->baddr, vb->bsize);
646 case VIDEOBUF_ACTIVE:
647 dev_dbg(&icd->dev, "%s (active)\n", __func__);
649 case VIDEOBUF_QUEUED:
650 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
652 case VIDEOBUF_PREPARED:
653 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
656 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
661 free_buffer(vq, buf);
664 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
665 struct videobuf_buffer *vb,
666 struct pxa_buffer *buf)
670 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
671 list_del_init(&vb->queue);
672 vb->state = VIDEOBUF_DONE;
673 do_gettimeofday(&vb->ts);
676 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
679 if (list_empty(&pcdev->capture)) {
680 pxa_camera_stop_capture(pcdev);
681 for (i = 0; i < pcdev->channels; i++)
682 pcdev->sg_tail[i] = NULL;
686 pcdev->active = list_entry(pcdev->capture.next,
687 struct pxa_buffer, vb.queue);
691 * pxa_camera_check_link_miss - check missed DMA linking
692 * @pcdev: camera device
694 * The DMA chaining is done with DMA running. This means a tiny temporal window
695 * remains, where a buffer is queued on the chain, while the chain is already
696 * stopped. This means the tailed buffer would never be transfered by DMA.
697 * This function restarts the capture for this corner case, where :
698 * - DADR() == DADDR_STOP
699 * - a videobuffer is queued on the pcdev->capture list
701 * Please check the "DMA hot chaining timeslice issue" in
702 * Documentation/video4linux/pxa_camera.txt
704 * Context: should only be called within the dma irq handler
706 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
708 int i, is_dma_stopped = 1;
710 for (i = 0; i < pcdev->channels; i++)
711 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
713 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
714 "%s : top queued buffer=%p, dma_stopped=%d\n",
715 __func__, pcdev->active, is_dma_stopped);
716 if (pcdev->active && is_dma_stopped)
717 pxa_camera_start_capture(pcdev);
720 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
721 enum pxa_camera_active_dma act_dma)
723 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
724 struct pxa_buffer *buf;
726 u32 status, camera_status, overrun;
727 struct videobuf_buffer *vb;
729 spin_lock_irqsave(&pcdev->lock, flags);
731 status = DCSR(channel);
732 DCSR(channel) = status;
734 camera_status = __raw_readl(pcdev->base + CISR);
735 overrun = CISR_IFO_0;
736 if (pcdev->channels == 3)
737 overrun |= CISR_IFO_1 | CISR_IFO_2;
739 if (status & DCSR_BUSERR) {
740 dev_err(dev, "DMA Bus Error IRQ!\n");
744 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
745 dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
751 * pcdev->active should not be NULL in DMA irq handler.
753 * But there is one corner case : if capture was stopped due to an
754 * overrun of channel 1, and at that same channel 2 was completed.
756 * When handling the overrun in DMA irq for channel 1, we'll stop the
757 * capture and restart it (and thus set pcdev->active to NULL). But the
758 * DMA irq handler will already be pending for channel 2. So on entering
759 * the DMA irq handler for channel 2 there will be no active buffer, yet
765 vb = &pcdev->active->vb;
766 buf = container_of(vb, struct pxa_buffer, vb);
767 WARN_ON(buf->inwork || list_empty(&vb->queue));
769 dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
770 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
771 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
773 if (status & DCSR_ENDINTR) {
775 * It's normal if the last frame creates an overrun, as there
776 * are no more DMA descriptors to fetch from QCI fifos
778 if (camera_status & overrun &&
779 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
780 dev_dbg(dev, "FIFO overrun! CISR: %x\n",
782 pxa_camera_stop_capture(pcdev);
783 pxa_camera_start_capture(pcdev);
786 buf->active_dma &= ~act_dma;
787 if (!buf->active_dma) {
788 pxa_camera_wakeup(pcdev, vb, buf);
789 pxa_camera_check_link_miss(pcdev);
794 spin_unlock_irqrestore(&pcdev->lock, flags);
797 static void pxa_camera_dma_irq_y(int channel, void *data)
799 struct pxa_camera_dev *pcdev = data;
800 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
803 static void pxa_camera_dma_irq_u(int channel, void *data)
805 struct pxa_camera_dev *pcdev = data;
806 pxa_camera_dma_irq(channel, pcdev, DMA_U);
809 static void pxa_camera_dma_irq_v(int channel, void *data)
811 struct pxa_camera_dev *pcdev = data;
812 pxa_camera_dma_irq(channel, pcdev, DMA_V);
815 static struct videobuf_queue_ops pxa_videobuf_ops = {
816 .buf_setup = pxa_videobuf_setup,
817 .buf_prepare = pxa_videobuf_prepare,
818 .buf_queue = pxa_videobuf_queue,
819 .buf_release = pxa_videobuf_release,
822 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
823 struct soc_camera_device *icd)
825 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
826 struct pxa_camera_dev *pcdev = ici->priv;
828 /* We must pass NULL as dev pointer, then all pci_* dma operations
829 * transform to normal dma_* ones. */
830 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
831 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
832 sizeof(struct pxa_buffer), icd);
835 static u32 mclk_get_divisor(struct platform_device *pdev,
836 struct pxa_camera_dev *pcdev)
838 unsigned long mclk = pcdev->mclk;
839 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
841 unsigned long lcdclk;
843 lcdclk = clk_get_rate(pcdev->clk);
844 pcdev->ciclk = lcdclk;
846 /* mclk <= ciclk / 4 (27.4.2) */
847 if (mclk > lcdclk / 4) {
849 dev_warn(dev, "Limiting master clock to %lu\n", mclk);
852 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
853 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
855 /* If we're not supplying MCLK, leave it at 0 */
856 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
857 pcdev->mclk = lcdclk / (2 * (div + 1));
859 dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
865 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
868 /* We want a timeout > 1 pixel time, not ">=" */
869 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
871 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
874 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
876 struct pxacamera_platform_data *pdata = pcdev->pdata;
877 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
880 dev_dbg(dev, "Registered platform device at %p data %p\n",
883 if (pdata && pdata->init) {
884 dev_dbg(dev, "%s: Init gpios\n", __func__);
888 /* disable all interrupts */
889 __raw_writel(0x3ff, pcdev->base + CICR0);
891 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
892 cicr4 |= CICR4_PCLK_EN;
893 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
894 cicr4 |= CICR4_MCLK_EN;
895 if (pcdev->platform_flags & PXA_CAMERA_PCP)
897 if (pcdev->platform_flags & PXA_CAMERA_HSP)
899 if (pcdev->platform_flags & PXA_CAMERA_VSP)
902 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
904 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
905 /* Initialise the timeout under the assumption pclk = mclk */
906 recalculate_fifo_timeout(pcdev, pcdev->mclk);
908 /* "Safe default" - 13MHz */
909 recalculate_fifo_timeout(pcdev, 13000000);
911 clk_enable(pcdev->clk);
914 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
916 clk_disable(pcdev->clk);
919 static irqreturn_t pxa_camera_irq(int irq, void *data)
921 struct pxa_camera_dev *pcdev = data;
922 unsigned long status, cicr0;
923 struct pxa_buffer *buf;
924 struct videobuf_buffer *vb;
926 status = __raw_readl(pcdev->base + CISR);
927 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "Camera interrupt status 0x%lx\n", status);
932 __raw_writel(status, pcdev->base + CISR);
934 if (status & CISR_EOF) {
935 pcdev->active = list_first_entry(&pcdev->capture,
936 struct pxa_buffer, vb.queue);
937 vb = &pcdev->active->vb;
938 buf = container_of(vb, struct pxa_buffer, vb);
939 pxa_videobuf_set_actdma(pcdev, buf);
941 pxa_dma_start_channels(pcdev);
943 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
944 __raw_writel(cicr0, pcdev->base + CICR0);
951 * The following two functions absolutely depend on the fact, that
952 * there can be only one camera on PXA quick capture interface
953 * Called with .video_lock held
955 static int pxa_camera_add_device(struct soc_camera_device *icd)
957 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
958 struct pxa_camera_dev *pcdev = ici->priv;
963 pxa_camera_activate(pcdev);
967 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
973 /* Called with .video_lock held */
974 static void pxa_camera_remove_device(struct soc_camera_device *icd)
976 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
977 struct pxa_camera_dev *pcdev = ici->priv;
979 BUG_ON(icd != pcdev->icd);
981 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
984 /* disable capture, disable interrupts */
985 __raw_writel(0x3ff, pcdev->base + CICR0);
987 /* Stop DMA engine */
988 DCSR(pcdev->dma_chans[0]) = 0;
989 DCSR(pcdev->dma_chans[1]) = 0;
990 DCSR(pcdev->dma_chans[2]) = 0;
992 pxa_camera_deactivate(pcdev);
997 static int test_platform_param(struct pxa_camera_dev *pcdev,
998 unsigned char buswidth, unsigned long *flags)
1001 * Platform specified synchronization and pixel clock polarities are
1002 * only a recommendation and are only used during probing. The PXA270
1003 * quick capture interface supports both.
1005 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1006 SOCAM_MASTER : SOCAM_SLAVE) |
1007 SOCAM_HSYNC_ACTIVE_HIGH |
1008 SOCAM_HSYNC_ACTIVE_LOW |
1009 SOCAM_VSYNC_ACTIVE_HIGH |
1010 SOCAM_VSYNC_ACTIVE_LOW |
1011 SOCAM_DATA_ACTIVE_HIGH |
1012 SOCAM_PCLK_SAMPLE_RISING |
1013 SOCAM_PCLK_SAMPLE_FALLING;
1015 /* If requested data width is supported by the platform, use it */
1018 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1020 *flags |= SOCAM_DATAWIDTH_10;
1023 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1025 *flags |= SOCAM_DATAWIDTH_9;
1028 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1030 *flags |= SOCAM_DATAWIDTH_8;
1039 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1041 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1042 struct pxa_camera_dev *pcdev = ici->priv;
1043 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
1044 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
1045 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
1050 camera_flags = icd->ops->query_bus_param(icd);
1052 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1056 pcdev->channels = 1;
1058 /* Make choises, based on platform preferences */
1059 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1060 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1061 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1062 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1064 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1067 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1068 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1069 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1070 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1072 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1075 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1076 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1077 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1078 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1080 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1083 ret = icd->ops->set_bus_param(icd, common_flags);
1087 /* Datawidth is now guaranteed to be equal to one of the three values.
1088 * We fix bit-per-pixel equal to data-width... */
1089 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
1090 case SOCAM_DATAWIDTH_10:
1094 case SOCAM_DATAWIDTH_9:
1099 /* Actually it can only be 8 now,
1100 * default is just to silence compiler warnings */
1101 case SOCAM_DATAWIDTH_8:
1106 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1107 cicr4 |= CICR4_PCLK_EN;
1108 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1109 cicr4 |= CICR4_MCLK_EN;
1110 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
1112 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
1114 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
1117 cicr0 = __raw_readl(pcdev->base + CICR0);
1118 if (cicr0 & CICR0_ENB)
1119 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1121 cicr1 = CICR1_PPL_VAL(icd->rect_current.width - 1) | bpp | dw;
1124 case V4L2_PIX_FMT_YUV422P:
1125 pcdev->channels = 3;
1126 cicr1 |= CICR1_YCBCR_F;
1128 * Normally, pxa bus wants as input UYVY format. We allow all
1129 * reorderings of the YUV422 format, as no processing is done,
1130 * and the YUV stream is just passed through without any
1131 * transformation. Note that UYVY is the only format that
1132 * should be used if pxa framebuffer Overlay2 is used.
1134 case V4L2_PIX_FMT_UYVY:
1135 case V4L2_PIX_FMT_VYUY:
1136 case V4L2_PIX_FMT_YUYV:
1137 case V4L2_PIX_FMT_YVYU:
1138 cicr1 |= CICR1_COLOR_SP_VAL(2);
1140 case V4L2_PIX_FMT_RGB555:
1141 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1142 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1144 case V4L2_PIX_FMT_RGB565:
1145 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1150 cicr3 = CICR3_LPF_VAL(icd->rect_current.height - 1) |
1151 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1152 cicr4 |= pcdev->mclk_divisor;
1154 __raw_writel(cicr1, pcdev->base + CICR1);
1155 __raw_writel(cicr2, pcdev->base + CICR2);
1156 __raw_writel(cicr3, pcdev->base + CICR3);
1157 __raw_writel(cicr4, pcdev->base + CICR4);
1159 /* CIF interrupts are not used, only DMA */
1160 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1161 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1162 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1163 __raw_writel(cicr0, pcdev->base + CICR0);
1168 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1169 unsigned char buswidth)
1171 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1172 struct pxa_camera_dev *pcdev = ici->priv;
1173 unsigned long bus_flags, camera_flags;
1174 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1179 camera_flags = icd->ops->query_bus_param(icd);
1181 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1184 static const struct soc_camera_data_format pxa_camera_formats[] = {
1186 .name = "Planar YUV422 16 bit",
1188 .fourcc = V4L2_PIX_FMT_YUV422P,
1189 .colorspace = V4L2_COLORSPACE_JPEG,
1193 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1195 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1196 struct pxa_camera_dev *pcdev = ici->priv;
1200 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1202 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1204 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1209 static int required_buswidth(const struct soc_camera_data_format *fmt)
1211 switch (fmt->fourcc) {
1212 case V4L2_PIX_FMT_UYVY:
1213 case V4L2_PIX_FMT_VYUY:
1214 case V4L2_PIX_FMT_YUYV:
1215 case V4L2_PIX_FMT_YVYU:
1216 case V4L2_PIX_FMT_RGB565:
1217 case V4L2_PIX_FMT_RGB555:
1224 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1225 struct soc_camera_format_xlate *xlate)
1227 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1228 int formats = 0, buswidth, ret;
1230 buswidth = required_buswidth(icd->formats + idx);
1232 if (!buswidth_supported(icd, buswidth))
1235 ret = pxa_camera_try_bus_param(icd, buswidth);
1239 switch (icd->formats[idx].fourcc) {
1240 case V4L2_PIX_FMT_UYVY:
1243 xlate->host_fmt = &pxa_camera_formats[0];
1244 xlate->cam_fmt = icd->formats + idx;
1245 xlate->buswidth = buswidth;
1247 dev_dbg(ici->v4l2_dev.dev, "Providing format %s using %s\n",
1248 pxa_camera_formats[0].name,
1249 icd->formats[idx].name);
1251 case V4L2_PIX_FMT_VYUY:
1252 case V4L2_PIX_FMT_YUYV:
1253 case V4L2_PIX_FMT_YVYU:
1254 case V4L2_PIX_FMT_RGB565:
1255 case V4L2_PIX_FMT_RGB555:
1258 xlate->host_fmt = icd->formats + idx;
1259 xlate->cam_fmt = icd->formats + idx;
1260 xlate->buswidth = buswidth;
1262 dev_dbg(ici->v4l2_dev.dev, "Providing format %s packed\n",
1263 icd->formats[idx].name);
1267 /* Generic pass-through */
1270 xlate->host_fmt = icd->formats + idx;
1271 xlate->cam_fmt = icd->formats + idx;
1272 xlate->buswidth = icd->formats[idx].depth;
1274 dev_dbg(ici->v4l2_dev.dev,
1275 "Providing format %s in pass-through mode\n",
1276 icd->formats[idx].name);
1283 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1284 struct v4l2_rect *rect)
1286 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1287 struct pxa_camera_dev *pcdev = ici->priv;
1288 struct soc_camera_sense sense = {
1289 .master_clock = pcdev->mclk,
1290 .pixel_clock_max = pcdev->ciclk / 4,
1294 /* If PCLK is used to latch data from the sensor, check sense */
1295 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1296 icd->sense = &sense;
1298 ret = icd->ops->set_crop(icd, rect);
1303 dev_warn(ici->v4l2_dev.dev, "Failed to crop to %ux%u@%u:%u\n",
1304 rect->width, rect->height, rect->left, rect->top);
1305 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1306 if (sense.pixel_clock > sense.pixel_clock_max) {
1307 dev_err(ici->v4l2_dev.dev,
1308 "pixel clock %lu set by the camera too high!",
1312 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1318 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1319 struct v4l2_format *f)
1321 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1322 struct pxa_camera_dev *pcdev = ici->priv;
1323 const struct soc_camera_data_format *cam_fmt = NULL;
1324 const struct soc_camera_format_xlate *xlate = NULL;
1325 struct soc_camera_sense sense = {
1326 .master_clock = pcdev->mclk,
1327 .pixel_clock_max = pcdev->ciclk / 4,
1329 struct v4l2_pix_format *pix = &f->fmt.pix;
1330 struct v4l2_format cam_f = *f;
1333 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1335 dev_warn(ici->v4l2_dev.dev, "Format %x not found\n", pix->pixelformat);
1339 cam_fmt = xlate->cam_fmt;
1341 /* If PCLK is used to latch data from the sensor, check sense */
1342 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1343 icd->sense = &sense;
1345 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1346 ret = v4l2_device_call_until_err(&ici->v4l2_dev, 0, video, s_fmt, f);
1351 dev_warn(ici->v4l2_dev.dev, "Failed to configure for format %x\n",
1353 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1354 if (sense.pixel_clock > sense.pixel_clock_max) {
1355 dev_err(ici->v4l2_dev.dev,
1356 "pixel clock %lu set by the camera too high!",
1360 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1364 icd->buswidth = xlate->buswidth;
1365 icd->current_fmt = xlate->host_fmt;
1371 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1372 struct v4l2_format *f)
1374 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1375 const struct soc_camera_format_xlate *xlate;
1376 struct v4l2_pix_format *pix = &f->fmt.pix;
1377 __u32 pixfmt = pix->pixelformat;
1378 enum v4l2_field field;
1381 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1383 dev_warn(ici->v4l2_dev.dev, "Format %x not found\n", pixfmt);
1388 * Limit to pxa hardware capabilities. YUV422P planar format requires
1389 * images size to be a multiple of 16 bytes. If not, zeros will be
1390 * inserted between Y and U planes, and U and V planes, which violates
1391 * the YUV422P standard.
1393 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1394 &pix->height, 32, 2048, 0,
1395 xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1397 pix->bytesperline = pix->width *
1398 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1399 pix->sizeimage = pix->height * pix->bytesperline;
1401 /* camera has to see its format, but the user the original one */
1402 pix->pixelformat = xlate->cam_fmt->fourcc;
1403 /* limit to sensor capabilities */
1404 ret = v4l2_device_call_until_err(&ici->v4l2_dev, 0, video, try_fmt, f);
1405 pix->pixelformat = xlate->host_fmt->fourcc;
1409 if (field == V4L2_FIELD_ANY) {
1410 pix->field = V4L2_FIELD_NONE;
1411 } else if (field != V4L2_FIELD_NONE) {
1412 dev_err(&icd->dev, "Field type %d unsupported.\n", field);
1419 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1420 struct v4l2_requestbuffers *p)
1424 /* This is for locking debugging only. I removed spinlocks and now I
1425 * check whether .prepare is ever called on a linked buffer, or whether
1426 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1427 * it hadn't triggered */
1428 for (i = 0; i < p->count; i++) {
1429 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1430 struct pxa_buffer, vb);
1432 INIT_LIST_HEAD(&buf->vb.queue);
1438 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1440 struct soc_camera_file *icf = file->private_data;
1441 struct pxa_buffer *buf;
1443 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1446 poll_wait(file, &buf->vb.done, pt);
1448 if (buf->vb.state == VIDEOBUF_DONE ||
1449 buf->vb.state == VIDEOBUF_ERROR)
1450 return POLLIN|POLLRDNORM;
1455 static int pxa_camera_querycap(struct soc_camera_host *ici,
1456 struct v4l2_capability *cap)
1458 /* cap->name is set by the firendly caller:-> */
1459 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1460 cap->version = PXA_CAM_VERSION_CODE;
1461 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1466 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1468 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1469 struct pxa_camera_dev *pcdev = ici->priv;
1472 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1473 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1474 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1475 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1476 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1478 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1479 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1484 static int pxa_camera_resume(struct soc_camera_device *icd)
1486 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1487 struct pxa_camera_dev *pcdev = ici->priv;
1490 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1491 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1492 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1494 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1495 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1496 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1497 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1498 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1500 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1501 ret = pcdev->icd->ops->resume(pcdev->icd);
1503 /* Restart frame capture if active buffer exists */
1504 if (!ret && pcdev->active)
1505 pxa_camera_start_capture(pcdev);
1510 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1511 .owner = THIS_MODULE,
1512 .add = pxa_camera_add_device,
1513 .remove = pxa_camera_remove_device,
1514 .suspend = pxa_camera_suspend,
1515 .resume = pxa_camera_resume,
1516 .set_crop = pxa_camera_set_crop,
1517 .get_formats = pxa_camera_get_formats,
1518 .set_fmt = pxa_camera_set_fmt,
1519 .try_fmt = pxa_camera_try_fmt,
1520 .init_videobuf = pxa_camera_init_videobuf,
1521 .reqbufs = pxa_camera_reqbufs,
1522 .poll = pxa_camera_poll,
1523 .querycap = pxa_camera_querycap,
1524 .set_bus_param = pxa_camera_set_bus_param,
1527 static int __devinit pxa_camera_probe(struct platform_device *pdev)
1529 struct pxa_camera_dev *pcdev;
1530 struct resource *res;
1535 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1536 irq = platform_get_irq(pdev, 0);
1537 if (!res || irq < 0) {
1542 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1544 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1549 pcdev->clk = clk_get(&pdev->dev, NULL);
1550 if (IS_ERR(pcdev->clk)) {
1551 err = PTR_ERR(pcdev->clk);
1557 pcdev->pdata = pdev->dev.platform_data;
1558 pcdev->platform_flags = pcdev->pdata->flags;
1559 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1560 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1561 /* Platform hasn't set available data widths. This is bad.
1562 * Warn and use a default. */
1563 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1564 "data widths, using default 10 bit\n");
1565 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1567 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1569 dev_warn(&pdev->dev,
1570 "mclk == 0! Please, fix your platform data. "
1571 "Using default 20MHz\n");
1572 pcdev->mclk = 20000000;
1575 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1577 INIT_LIST_HEAD(&pcdev->capture);
1578 spin_lock_init(&pcdev->lock);
1581 * Request the regions.
1583 if (!request_mem_region(res->start, resource_size(res),
1584 PXA_CAM_DRV_NAME)) {
1589 base = ioremap(res->start, resource_size(res));
1598 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1599 pxa_camera_dma_irq_y, pcdev);
1601 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1604 pcdev->dma_chans[0] = err;
1605 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1607 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1608 pxa_camera_dma_irq_u, pcdev);
1610 dev_err(&pdev->dev, "Can't request DMA for U\n");
1611 goto exit_free_dma_y;
1613 pcdev->dma_chans[1] = err;
1614 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1616 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1617 pxa_camera_dma_irq_v, pcdev);
1619 dev_err(&pdev->dev, "Can't request DMA for V\n");
1620 goto exit_free_dma_u;
1622 pcdev->dma_chans[2] = err;
1623 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1625 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1626 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1627 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1630 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1633 dev_err(&pdev->dev, "Camera interrupt register failed \n");
1637 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1638 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1639 pcdev->soc_host.priv = pcdev;
1640 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1641 pcdev->soc_host.nr = pdev->id;
1643 err = soc_camera_host_register(&pcdev->soc_host);
1650 free_irq(pcdev->irq, pcdev);
1652 pxa_free_dma(pcdev->dma_chans[2]);
1654 pxa_free_dma(pcdev->dma_chans[1]);
1656 pxa_free_dma(pcdev->dma_chans[0]);
1660 release_mem_region(res->start, resource_size(res));
1662 clk_put(pcdev->clk);
1669 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1671 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1672 struct pxa_camera_dev *pcdev = container_of(soc_host,
1673 struct pxa_camera_dev, soc_host);
1674 struct resource *res;
1676 clk_put(pcdev->clk);
1678 pxa_free_dma(pcdev->dma_chans[0]);
1679 pxa_free_dma(pcdev->dma_chans[1]);
1680 pxa_free_dma(pcdev->dma_chans[2]);
1681 free_irq(pcdev->irq, pcdev);
1683 soc_camera_host_unregister(soc_host);
1685 iounmap(pcdev->base);
1688 release_mem_region(res->start, resource_size(res));
1692 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1697 static struct platform_driver pxa_camera_driver = {
1699 .name = PXA_CAM_DRV_NAME,
1701 .probe = pxa_camera_probe,
1702 .remove = __devexit_p(pxa_camera_remove),
1706 static int __init pxa_camera_init(void)
1708 return platform_driver_register(&pxa_camera_driver);
1711 static void __exit pxa_camera_exit(void)
1713 platform_driver_unregister(&pxa_camera_driver);
1716 module_init(pxa_camera_init);
1717 module_exit(pxa_camera_exit);
1719 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1720 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1721 MODULE_LICENSE("GPL");
1722 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);