Pileus Git - ~andy/linux/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-i2c-track.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39 #include "pvrusb2-wm8775.h"
  40 #include "pvrusb2-video-v4l.h"
  41 #include "pvrusb2-cx2584x-v4l.h"
  42 #include "pvrusb2-audio.h"
  43
  44 #define TV_MIN_FREQ     55250000L
  45 #define TV_MAX_FREQ    850000000L
  46
  47 /* This defines a minimum interval that the decoder must remain quiet
  48    before we are allowed to start it running. */
  49 #define TIME_MSEC_DECODER_WAIT 50
  50
  51 /* This defines a minimum interval that the encoder must remain quiet
  52    before we are allowed to configure it.  I had this originally set to
  53    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  54    things work better when it's set to 100msec. */
  55 #define TIME_MSEC_ENCODER_WAIT 100
  56
  57 /* This defines the minimum interval that the encoder must successfully run
  58    before we consider that the encoder has run at least once since its
  59    firmware has been loaded.  This measurement is in important for cases
  60    where we can't do something until we know that the encoder has been run
  61    at least once. */
  62 #define TIME_MSEC_ENCODER_OK 250
  63
  64 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  65 static DEFINE_MUTEX(pvr2_unit_mtx);
  66
  67 static int ctlchg;
  68 static int procreload;
  69 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  70 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  71 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  72 static int init_pause_msec;
  73
  74 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  76 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  77 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  78 module_param(procreload, int, S_IRUGO|S_IWUSR);
  79 MODULE_PARM_DESC(procreload,
  80                  "Attempt init failure recovery with firmware reload");
  81 module_param_array(tuner,    int, NULL, 0444);
  82 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  83 module_param_array(video_std,    int, NULL, 0444);
  84 MODULE_PARM_DESC(video_std,"specify initial video standard");
  85 module_param_array(tolerance,    int, NULL, 0444);
  86 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  87
  88 /* US Broadcast channel 7 (175.25 MHz) */
  89 static int default_tv_freq    = 175250000L;
  90 /* 104.3 MHz, a usable FM station for my area */
  91 static int default_radio_freq = 104300000L;
  92
  93 module_param_named(tv_freq, default_tv_freq, int, 0444);
  94 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  95 module_param_named(radio_freq, default_radio_freq, int, 0444);
  96 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  97
  98 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  99 #define PVR2_CTL_READ_ENDPOINT   0x81
 100
 101 #define PVR2_GPIO_IN 0x9008
 102 #define PVR2_GPIO_OUT 0x900c
 103 #define PVR2_GPIO_DIR 0x9020
 104
 105 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 106
 107 #define PVR2_FIRMWARE_ENDPOINT   0x02
 108
 109 /* size of a firmware chunk */
 110 #define FIRMWARE_CHUNK_SIZE 0x2000
 111
 112 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 113                                         struct v4l2_subdev *);
 114
 115 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 116         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 117         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 118         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 119         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 120 };
 121
 122 static const char *module_names[] = {
 123         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 124         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 125         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 126         [PVR2_CLIENT_ID_TUNER] = "tuner",
 127         [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
 128         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 129 };
 130
 131
 132 static const unsigned char *module_i2c_addresses[] = {
 133         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 134 };
 135
 136
 137 /* Define the list of additional controls we'll dynamically construct based
 138    on query of the cx2341x module. */
 139 struct pvr2_mpeg_ids {
 140         const char *strid;
 141         int id;
 142 };
 143 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 144         {
 145                 .strid = "audio_layer",
 146                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 147         },{
 148                 .strid = "audio_bitrate",
 149                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 150         },{
 151                 /* Already using audio_mode elsewhere :-( */
 152                 .strid = "mpeg_audio_mode",
 153                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 154         },{
 155                 .strid = "mpeg_audio_mode_extension",
 156                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 157         },{
 158                 .strid = "audio_emphasis",
 159                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 160         },{
 161                 .strid = "audio_crc",
 162                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 163         },{
 164                 .strid = "video_aspect",
 165                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 166         },{
 167                 .strid = "video_b_frames",
 168                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 169         },{
 170                 .strid = "video_gop_size",
 171                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 172         },{
 173                 .strid = "video_gop_closure",
 174                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 175         },{
 176                 .strid = "video_bitrate_mode",
 177                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 178         },{
 179                 .strid = "video_bitrate",
 180                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 181         },{
 182                 .strid = "video_bitrate_peak",
 183                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 184         },{
 185                 .strid = "video_temporal_decimation",
 186                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 187         },{
 188                 .strid = "stream_type",
 189                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 190         },{
 191                 .strid = "video_spatial_filter_mode",
 192                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 193         },{
 194                 .strid = "video_spatial_filter",
 195                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 196         },{
 197                 .strid = "video_luma_spatial_filter_type",
 198                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 199         },{
 200                 .strid = "video_chroma_spatial_filter_type",
 201                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 202         },{
 203                 .strid = "video_temporal_filter_mode",
 204                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 205         },{
 206                 .strid = "video_temporal_filter",
 207                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 208         },{
 209                 .strid = "video_median_filter_type",
 210                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 211         },{
 212                 .strid = "video_luma_median_filter_top",
 213                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 214         },{
 215                 .strid = "video_luma_median_filter_bottom",
 216                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 217         },{
 218                 .strid = "video_chroma_median_filter_top",
 219                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 220         },{
 221                 .strid = "video_chroma_median_filter_bottom",
 222                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 223         }
 224 };
 225 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 226
 227
 228 static const char *control_values_srate[] = {
 229         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 230         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 231         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 232 };
 233
 234
 235
 236 static const char *control_values_input[] = {
 237         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 238         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 239         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 240         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 241         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 242 };
 243
 244
 245 static const char *control_values_audiomode[] = {
 246         [V4L2_TUNER_MODE_MONO]   = "Mono",
 247         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 248         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 249         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 250         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 251 };
 252
 253
 254 static const char *control_values_hsm[] = {
 255         [PVR2_CVAL_HSM_FAIL] = "Fail",
 256         [PVR2_CVAL_HSM_HIGH] = "High",
 257         [PVR2_CVAL_HSM_FULL] = "Full",
 258 };
 259
 260
 261 static const char *pvr2_state_names[] = {
 262         [PVR2_STATE_NONE] =    "none",
 263         [PVR2_STATE_DEAD] =    "dead",
 264         [PVR2_STATE_COLD] =    "cold",
 265         [PVR2_STATE_WARM] =    "warm",
 266         [PVR2_STATE_ERROR] =   "error",
 267         [PVR2_STATE_READY] =   "ready",
 268         [PVR2_STATE_RUN] =     "run",
 269 };
 270
 271
 272 struct pvr2_fx2cmd_descdef {
 273         unsigned char id;
 274         unsigned char *desc;
 275 };
 276
 277 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 278         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 279         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 280         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 281         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 282         {FX2CMD_REG_WRITE, "write encoder register"},
 283         {FX2CMD_REG_READ, "read encoder register"},
 284         {FX2CMD_MEMSEL, "encoder memsel"},
 285         {FX2CMD_I2C_WRITE, "i2c write"},
 286         {FX2CMD_I2C_READ, "i2c read"},
 287         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 288         {FX2CMD_STREAMING_ON, "stream on"},
 289         {FX2CMD_STREAMING_OFF, "stream off"},
 290         {FX2CMD_FWPOST1, "fwpost1"},
 291         {FX2CMD_POWER_OFF, "power off"},
 292         {FX2CMD_POWER_ON, "power on"},
 293         {FX2CMD_DEEP_RESET, "deep reset"},
 294         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 295         {FX2CMD_GET_IR_CODE, "get IR code"},
 296         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 297         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 298         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 299         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 300         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 301         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 302         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 303 };
 304
 305
 306 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 307 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 308 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 309 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 310 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 311 static void pvr2_hdw_worker_poll(struct work_struct *work);
 312 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 313 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 314 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 315 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 316 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 317 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 318 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 319 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 320 static void pvr2_hdw_quiescent_timeout(unsigned long);
 321 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 322 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 323 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 324 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 325                                 unsigned int timeout,int probe_fl,
 326                                 void *write_data,unsigned int write_len,
 327                                 void *read_data,unsigned int read_len);
 328 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 329
 330
 331 static void trace_stbit(const char *name,int val)
 332 {
 333         pvr2_trace(PVR2_TRACE_STBITS,
 334                    "State bit %s <-- %s",
 335                    name,(val ? "true" : "false"));
 336 }
 337
 338 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 339 {
 340         struct pvr2_hdw *hdw = cptr->hdw;
 341         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 342                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 343         } else {
 344                 *vp = 0;
 345         }
 346         return 0;
 347 }
 348
 349 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 350 {
 351         struct pvr2_hdw *hdw = cptr->hdw;
 352         unsigned int slotId = hdw->freqProgSlot;
 353         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 354                 hdw->freqTable[slotId-1] = v;
 355                 /* Handle side effects correctly - if we're tuned to this
 356                    slot, then forgot the slot id relation since the stored
 357                    frequency has been changed. */
 358                 if (hdw->freqSelector) {
 359                         if (hdw->freqSlotRadio == slotId) {
 360                                 hdw->freqSlotRadio = 0;
 361                         }
 362                 } else {
 363                         if (hdw->freqSlotTelevision == slotId) {
 364                                 hdw->freqSlotTelevision = 0;
 365                         }
 366                 }
 367         }
 368         return 0;
 369 }
 370
 371 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 372 {
 373         *vp = cptr->hdw->freqProgSlot;
 374         return 0;
 375 }
 376
 377 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 378 {
 379         struct pvr2_hdw *hdw = cptr->hdw;
 380         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 381                 hdw->freqProgSlot = v;
 382         }
 383         return 0;
 384 }
 385
 386 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 387 {
 388         struct pvr2_hdw *hdw = cptr->hdw;
 389         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 390         return 0;
 391 }
 392
 393 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 394 {
 395         unsigned freq = 0;
 396         struct pvr2_hdw *hdw = cptr->hdw;
 397         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 398         if (slotId > 0) {
 399                 freq = hdw->freqTable[slotId-1];
 400                 if (!freq) return 0;
 401                 pvr2_hdw_set_cur_freq(hdw,freq);
 402         }
 403         if (hdw->freqSelector) {
 404                 hdw->freqSlotRadio = slotId;
 405         } else {
 406                 hdw->freqSlotTelevision = slotId;
 407         }
 408         return 0;
 409 }
 410
 411 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 412 {
 413         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 414         return 0;
 415 }
 416
 417 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 418 {
 419         return cptr->hdw->freqDirty != 0;
 420 }
 421
 422 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 423 {
 424         cptr->hdw->freqDirty = 0;
 425 }
 426
 427 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 428 {
 429         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 430         return 0;
 431 }
 432
 433 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 434 {
 435         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 436         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 437         if (stat != 0) {
 438                 return stat;
 439         }
 440         *left = cap->bounds.left;
 441         return 0;
 442 }
 443
 444 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 445 {
 446         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 447         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 448         if (stat != 0) {
 449                 return stat;
 450         }
 451         *left = cap->bounds.left;
 452         if (cap->bounds.width > cptr->hdw->cropw_val) {
 453                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 454         }
 455         return 0;
 456 }
 457
 458 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 459 {
 460         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 461         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 462         if (stat != 0) {
 463                 return stat;
 464         }
 465         *top = cap->bounds.top;
 466         return 0;
 467 }
 468
 469 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 470 {
 471         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 472         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 473         if (stat != 0) {
 474                 return stat;
 475         }
 476         *top = cap->bounds.top;
 477         if (cap->bounds.height > cptr->hdw->croph_val) {
 478                 *top += cap->bounds.height - cptr->hdw->croph_val;
 479         }
 480         return 0;
 481 }
 482
 483 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 484 {
 485         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 486         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 487         if (stat != 0) {
 488                 return stat;
 489         }
 490         *val = 0;
 491         if (cap->bounds.width > cptr->hdw->cropl_val) {
 492                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 493         }
 494         return 0;
 495 }
 496
 497 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 498 {
 499         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 500         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 501         if (stat != 0) {
 502                 return stat;
 503         }
 504         *val = 0;
 505         if (cap->bounds.height > cptr->hdw->cropt_val) {
 506                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 507         }
 508         return 0;
 509 }
 510
 511 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 512 {
 513         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 514         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 515         if (stat != 0) {
 516                 return stat;
 517         }
 518         *val = cap->bounds.left;
 519         return 0;
 520 }
 521
 522 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 523 {
 524         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 525         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 526         if (stat != 0) {
 527                 return stat;
 528         }
 529         *val = cap->bounds.top;
 530         return 0;
 531 }
 532
 533 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 534 {
 535         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 536         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 537         if (stat != 0) {
 538                 return stat;
 539         }
 540         *val = cap->bounds.width;
 541         return 0;
 542 }
 543
 544 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 545 {
 546         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 547         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 548         if (stat != 0) {
 549                 return stat;
 550         }
 551         *val = cap->bounds.height;
 552         return 0;
 553 }
 554
 555 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 556 {
 557         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 558         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 559         if (stat != 0) {
 560                 return stat;
 561         }
 562         *val = cap->defrect.left;
 563         return 0;
 564 }
 565
 566 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 567 {
 568         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 569         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 570         if (stat != 0) {
 571                 return stat;
 572         }
 573         *val = cap->defrect.top;
 574         return 0;
 575 }
 576
 577 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 578 {
 579         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 580         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 581         if (stat != 0) {
 582                 return stat;
 583         }
 584         *val = cap->defrect.width;
 585         return 0;
 586 }
 587
 588 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 589 {
 590         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 591         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 592         if (stat != 0) {
 593                 return stat;
 594         }
 595         *val = cap->defrect.height;
 596         return 0;
 597 }
 598
 599 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 600 {
 601         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 602         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 603         if (stat != 0) {
 604                 return stat;
 605         }
 606         *val = cap->pixelaspect.numerator;
 607         return 0;
 608 }
 609
 610 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 611 {
 612         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 613         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 614         if (stat != 0) {
 615                 return stat;
 616         }
 617         *val = cap->pixelaspect.denominator;
 618         return 0;
 619 }
 620
 621 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 622 {
 623         /* Actual maximum depends on the video standard in effect. */
 624         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 625                 *vp = 480;
 626         } else {
 627                 *vp = 576;
 628         }
 629         return 0;
 630 }
 631
 632 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 633 {
 634         /* Actual minimum depends on device digitizer type. */
 635         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 636                 *vp = 75;
 637         } else {
 638                 *vp = 17;
 639         }
 640         return 0;
 641 }
 642
 643 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 644 {
 645         *vp = cptr->hdw->input_val;
 646         return 0;
 647 }
 648
 649 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 650 {
 651         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 652 }
 653
 654 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 655 {
 656         return pvr2_hdw_set_input(cptr->hdw,v);
 657 }
 658
 659 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 660 {
 661         return cptr->hdw->input_dirty != 0;
 662 }
 663
 664 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 665 {
 666         cptr->hdw->input_dirty = 0;
 667 }
 668
 669
 670 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 671 {
 672         unsigned long fv;
 673         struct pvr2_hdw *hdw = cptr->hdw;
 674         if (hdw->tuner_signal_stale) {
 675                 pvr2_hdw_status_poll(hdw);
 676         }
 677         fv = hdw->tuner_signal_info.rangehigh;
 678         if (!fv) {
 679                 /* Safety fallback */
 680                 *vp = TV_MAX_FREQ;
 681                 return 0;
 682         }
 683         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 684                 fv = (fv * 125) / 2;
 685         } else {
 686                 fv = fv * 62500;
 687         }
 688         *vp = fv;
 689         return 0;
 690 }
 691
 692 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 693 {
 694         unsigned long fv;
 695         struct pvr2_hdw *hdw = cptr->hdw;
 696         if (hdw->tuner_signal_stale) {
 697                 pvr2_hdw_status_poll(hdw);
 698         }
 699         fv = hdw->tuner_signal_info.rangelow;
 700         if (!fv) {
 701                 /* Safety fallback */
 702                 *vp = TV_MIN_FREQ;
 703                 return 0;
 704         }
 705         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 706                 fv = (fv * 125) / 2;
 707         } else {
 708                 fv = fv * 62500;
 709         }
 710         *vp = fv;
 711         return 0;
 712 }
 713
 714 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 715 {
 716         return cptr->hdw->enc_stale != 0;
 717 }
 718
 719 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 720 {
 721         cptr->hdw->enc_stale = 0;
 722         cptr->hdw->enc_unsafe_stale = 0;
 723 }
 724
 725 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 726 {
 727         int ret;
 728         struct v4l2_ext_controls cs;
 729         struct v4l2_ext_control c1;
 730         memset(&cs,0,sizeof(cs));
 731         memset(&c1,0,sizeof(c1));
 732         cs.controls = &c1;
 733         cs.count = 1;
 734         c1.id = cptr->info->v4l_id;
 735         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 736                                 VIDIOC_G_EXT_CTRLS);
 737         if (ret) return ret;
 738         *vp = c1.value;
 739         return 0;
 740 }
 741
 742 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 743 {
 744         int ret;
 745         struct pvr2_hdw *hdw = cptr->hdw;
 746         struct v4l2_ext_controls cs;
 747         struct v4l2_ext_control c1;
 748         memset(&cs,0,sizeof(cs));
 749         memset(&c1,0,sizeof(c1));
 750         cs.controls = &c1;
 751         cs.count = 1;
 752         c1.id = cptr->info->v4l_id;
 753         c1.value = v;
 754         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 755                                 hdw->state_encoder_run, &cs,
 756                                 VIDIOC_S_EXT_CTRLS);
 757         if (ret == -EBUSY) {
 758                 /* Oops.  cx2341x is telling us it's not safe to change
 759                    this control while we're capturing.  Make a note of this
 760                    fact so that the pipeline will be stopped the next time
 761                    controls are committed.  Then go on ahead and store this
 762                    change anyway. */
 763                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 764                                         0, &cs,
 765                                         VIDIOC_S_EXT_CTRLS);
 766                 if (!ret) hdw->enc_unsafe_stale = !0;
 767         }
 768         if (ret) return ret;
 769         hdw->enc_stale = !0;
 770         return 0;
 771 }
 772
 773 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 774 {
 775         struct v4l2_queryctrl qctrl;
 776         struct pvr2_ctl_info *info;
 777         qctrl.id = cptr->info->v4l_id;
 778         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 779         /* Strip out the const so we can adjust a function pointer.  It's
 780            OK to do this here because we know this is a dynamically created
 781            control, so the underlying storage for the info pointer is (a)
 782            private to us, and (b) not in read-only storage.  Either we do
 783            this or we significantly complicate the underlying control
 784            implementation. */
 785         info = (struct pvr2_ctl_info *)(cptr->info);
 786         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 787                 if (info->set_value) {
 788                         info->set_value = NULL;
 789                 }
 790         } else {
 791                 if (!(info->set_value)) {
 792                         info->set_value = ctrl_cx2341x_set;
 793                 }
 794         }
 795         return qctrl.flags;
 796 }
 797
 798 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 799 {
 800         *vp = cptr->hdw->state_pipeline_req;
 801         return 0;
 802 }
 803
 804 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 805 {
 806         *vp = cptr->hdw->master_state;
 807         return 0;
 808 }
 809
 810 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 811 {
 812         int result = pvr2_hdw_is_hsm(cptr->hdw);
 813         *vp = PVR2_CVAL_HSM_FULL;
 814         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 815         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 816         return 0;
 817 }
 818
 819 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 820 {
 821         *vp = cptr->hdw->std_mask_avail;
 822         return 0;
 823 }
 824
 825 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 826 {
 827         struct pvr2_hdw *hdw = cptr->hdw;
 828         v4l2_std_id ns;
 829         ns = hdw->std_mask_avail;
 830         ns = (ns & ~m) | (v & m);
 831         if (ns == hdw->std_mask_avail) return 0;
 832         hdw->std_mask_avail = ns;
 833         pvr2_hdw_internal_set_std_avail(hdw);
 834         pvr2_hdw_internal_find_stdenum(hdw);
 835         return 0;
 836 }
 837
 838 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 839                                char *bufPtr,unsigned int bufSize,
 840                                unsigned int *len)
 841 {
 842         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 843         return 0;
 844 }
 845
 846 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 847                                const char *bufPtr,unsigned int bufSize,
 848                                int *mskp,int *valp)
 849 {
 850         int ret;
 851         v4l2_std_id id;
 852         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 853         if (ret < 0) return ret;
 854         if (mskp) *mskp = id;
 855         if (valp) *valp = id;
 856         return 0;
 857 }
 858
 859 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 860 {
 861         *vp = cptr->hdw->std_mask_cur;
 862         return 0;
 863 }
 864
 865 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 866 {
 867         struct pvr2_hdw *hdw = cptr->hdw;
 868         v4l2_std_id ns;
 869         ns = hdw->std_mask_cur;
 870         ns = (ns & ~m) | (v & m);
 871         if (ns == hdw->std_mask_cur) return 0;
 872         hdw->std_mask_cur = ns;
 873         hdw->std_dirty = !0;
 874         pvr2_hdw_internal_find_stdenum(hdw);
 875         return 0;
 876 }
 877
 878 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 879 {
 880         return cptr->hdw->std_dirty != 0;
 881 }
 882
 883 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 884 {
 885         cptr->hdw->std_dirty = 0;
 886 }
 887
 888 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 889 {
 890         struct pvr2_hdw *hdw = cptr->hdw;
 891         pvr2_hdw_status_poll(hdw);
 892         *vp = hdw->tuner_signal_info.signal;
 893         return 0;
 894 }
 895
 896 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 897 {
 898         int val = 0;
 899         unsigned int subchan;
 900         struct pvr2_hdw *hdw = cptr->hdw;
 901         pvr2_hdw_status_poll(hdw);
 902         subchan = hdw->tuner_signal_info.rxsubchans;
 903         if (subchan & V4L2_TUNER_SUB_MONO) {
 904                 val |= (1 << V4L2_TUNER_MODE_MONO);
 905         }
 906         if (subchan & V4L2_TUNER_SUB_STEREO) {
 907                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 908         }
 909         if (subchan & V4L2_TUNER_SUB_LANG1) {
 910                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 911         }
 912         if (subchan & V4L2_TUNER_SUB_LANG2) {
 913                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 914         }
 915         *vp = val;
 916         return 0;
 917 }
 918
 919
 920 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 921 {
 922         struct pvr2_hdw *hdw = cptr->hdw;
 923         if (v < 0) return -EINVAL;
 924         if (v > hdw->std_enum_cnt) return -EINVAL;
 925         hdw->std_enum_cur = v;
 926         if (!v) return 0;
 927         v--;
 928         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 929         hdw->std_mask_cur = hdw->std_defs[v].id;
 930         hdw->std_dirty = !0;
 931         return 0;
 932 }
 933
 934
 935 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 936 {
 937         *vp = cptr->hdw->std_enum_cur;
 938         return 0;
 939 }
 940
 941
 942 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 943 {
 944         return cptr->hdw->std_dirty != 0;
 945 }
 946
 947
 948 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 949 {
 950         cptr->hdw->std_dirty = 0;
 951 }
 952
 953
 954 #define DEFINT(vmin,vmax) \
 955         .type = pvr2_ctl_int, \
 956         .def.type_int.min_value = vmin, \
 957         .def.type_int.max_value = vmax
 958
 959 #define DEFENUM(tab) \
 960         .type = pvr2_ctl_enum, \
 961         .def.type_enum.count = ARRAY_SIZE(tab), \
 962         .def.type_enum.value_names = tab
 963
 964 #define DEFBOOL \
 965         .type = pvr2_ctl_bool
 966
 967 #define DEFMASK(msk,tab) \
 968         .type = pvr2_ctl_bitmask, \
 969         .def.type_bitmask.valid_bits = msk, \
 970         .def.type_bitmask.bit_names = tab
 971
 972 #define DEFREF(vname) \
 973         .set_value = ctrl_set_##vname, \
 974         .get_value = ctrl_get_##vname, \
 975         .is_dirty = ctrl_isdirty_##vname, \
 976         .clear_dirty = ctrl_cleardirty_##vname
 977
 978
 979 #define VCREATE_FUNCS(vname) \
 980 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 981 {*vp = cptr->hdw->vname##_val; return 0;} \
 982 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 983 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 984 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 985 {return cptr->hdw->vname##_dirty != 0;} \
 986 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 987 {cptr->hdw->vname##_dirty = 0;}
 988
 989 VCREATE_FUNCS(brightness)
 990 VCREATE_FUNCS(contrast)
 991 VCREATE_FUNCS(saturation)
 992 VCREATE_FUNCS(hue)
 993 VCREATE_FUNCS(volume)
 994 VCREATE_FUNCS(balance)
 995 VCREATE_FUNCS(bass)
 996 VCREATE_FUNCS(treble)
 997 VCREATE_FUNCS(mute)
 998 VCREATE_FUNCS(cropl)
 999 VCREATE_FUNCS(cropt)
1000 VCREATE_FUNCS(cropw)
1001 VCREATE_FUNCS(croph)
1002 VCREATE_FUNCS(audiomode)
1003 VCREATE_FUNCS(res_hor)
1004 VCREATE_FUNCS(res_ver)
1005 VCREATE_FUNCS(srate)
1006
1007 /* Table definition of all controls which can be manipulated */
1008 static const struct pvr2_ctl_info control_defs[] = {
1009         {
1010                 .v4l_id = V4L2_CID_BRIGHTNESS,
1011                 .desc = "Brightness",
1012                 .name = "brightness",
1013                 .default_value = 128,
1014                 DEFREF(brightness),
1015                 DEFINT(0,255),
1016         },{
1017                 .v4l_id = V4L2_CID_CONTRAST,
1018                 .desc = "Contrast",
1019                 .name = "contrast",
1020                 .default_value = 68,
1021                 DEFREF(contrast),
1022                 DEFINT(0,127),
1023         },{
1024                 .v4l_id = V4L2_CID_SATURATION,
1025                 .desc = "Saturation",
1026                 .name = "saturation",
1027                 .default_value = 64,
1028                 DEFREF(saturation),
1029                 DEFINT(0,127),
1030         },{
1031                 .v4l_id = V4L2_CID_HUE,
1032                 .desc = "Hue",
1033                 .name = "hue",
1034                 .default_value = 0,
1035                 DEFREF(hue),
1036                 DEFINT(-128,127),
1037         },{
1038                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1039                 .desc = "Volume",
1040                 .name = "volume",
1041                 .default_value = 62000,
1042                 DEFREF(volume),
1043                 DEFINT(0,65535),
1044         },{
1045                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1046                 .desc = "Balance",
1047                 .name = "balance",
1048                 .default_value = 0,
1049                 DEFREF(balance),
1050                 DEFINT(-32768,32767),
1051         },{
1052                 .v4l_id = V4L2_CID_AUDIO_BASS,
1053                 .desc = "Bass",
1054                 .name = "bass",
1055                 .default_value = 0,
1056                 DEFREF(bass),
1057                 DEFINT(-32768,32767),
1058         },{
1059                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1060                 .desc = "Treble",
1061                 .name = "treble",
1062                 .default_value = 0,
1063                 DEFREF(treble),
1064                 DEFINT(-32768,32767),
1065         },{
1066                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1067                 .desc = "Mute",
1068                 .name = "mute",
1069                 .default_value = 0,
1070                 DEFREF(mute),
1071                 DEFBOOL,
1072         }, {
1073                 .desc = "Capture crop left margin",
1074                 .name = "crop_left",
1075                 .internal_id = PVR2_CID_CROPL,
1076                 .default_value = 0,
1077                 DEFREF(cropl),
1078                 DEFINT(-129, 340),
1079                 .get_min_value = ctrl_cropl_min_get,
1080                 .get_max_value = ctrl_cropl_max_get,
1081                 .get_def_value = ctrl_get_cropcapdl,
1082         }, {
1083                 .desc = "Capture crop top margin",
1084                 .name = "crop_top",
1085                 .internal_id = PVR2_CID_CROPT,
1086                 .default_value = 0,
1087                 DEFREF(cropt),
1088                 DEFINT(-35, 544),
1089                 .get_min_value = ctrl_cropt_min_get,
1090                 .get_max_value = ctrl_cropt_max_get,
1091                 .get_def_value = ctrl_get_cropcapdt,
1092         }, {
1093                 .desc = "Capture crop width",
1094                 .name = "crop_width",
1095                 .internal_id = PVR2_CID_CROPW,
1096                 .default_value = 720,
1097                 DEFREF(cropw),
1098                 .get_max_value = ctrl_cropw_max_get,
1099                 .get_def_value = ctrl_get_cropcapdw,
1100         }, {
1101                 .desc = "Capture crop height",
1102                 .name = "crop_height",
1103                 .internal_id = PVR2_CID_CROPH,
1104                 .default_value = 480,
1105                 DEFREF(croph),
1106                 .get_max_value = ctrl_croph_max_get,
1107                 .get_def_value = ctrl_get_cropcapdh,
1108         }, {
1109                 .desc = "Capture capability pixel aspect numerator",
1110                 .name = "cropcap_pixel_numerator",
1111                 .internal_id = PVR2_CID_CROPCAPPAN,
1112                 .get_value = ctrl_get_cropcappan,
1113         }, {
1114                 .desc = "Capture capability pixel aspect denominator",
1115                 .name = "cropcap_pixel_denominator",
1116                 .internal_id = PVR2_CID_CROPCAPPAD,
1117                 .get_value = ctrl_get_cropcappad,
1118         }, {
1119                 .desc = "Capture capability bounds top",
1120                 .name = "cropcap_bounds_top",
1121                 .internal_id = PVR2_CID_CROPCAPBT,
1122                 .get_value = ctrl_get_cropcapbt,
1123         }, {
1124                 .desc = "Capture capability bounds left",
1125                 .name = "cropcap_bounds_left",
1126                 .internal_id = PVR2_CID_CROPCAPBL,
1127                 .get_value = ctrl_get_cropcapbl,
1128         }, {
1129                 .desc = "Capture capability bounds width",
1130                 .name = "cropcap_bounds_width",
1131                 .internal_id = PVR2_CID_CROPCAPBW,
1132                 .get_value = ctrl_get_cropcapbw,
1133         }, {
1134                 .desc = "Capture capability bounds height",
1135                 .name = "cropcap_bounds_height",
1136                 .internal_id = PVR2_CID_CROPCAPBH,
1137                 .get_value = ctrl_get_cropcapbh,
1138         },{
1139                 .desc = "Video Source",
1140                 .name = "input",
1141                 .internal_id = PVR2_CID_INPUT,
1142                 .default_value = PVR2_CVAL_INPUT_TV,
1143                 .check_value = ctrl_check_input,
1144                 DEFREF(input),
1145                 DEFENUM(control_values_input),
1146         },{
1147                 .desc = "Audio Mode",
1148                 .name = "audio_mode",
1149                 .internal_id = PVR2_CID_AUDIOMODE,
1150                 .default_value = V4L2_TUNER_MODE_STEREO,
1151                 DEFREF(audiomode),
1152                 DEFENUM(control_values_audiomode),
1153         },{
1154                 .desc = "Horizontal capture resolution",
1155                 .name = "resolution_hor",
1156                 .internal_id = PVR2_CID_HRES,
1157                 .default_value = 720,
1158                 DEFREF(res_hor),
1159                 DEFINT(19,720),
1160         },{
1161                 .desc = "Vertical capture resolution",
1162                 .name = "resolution_ver",
1163                 .internal_id = PVR2_CID_VRES,
1164                 .default_value = 480,
1165                 DEFREF(res_ver),
1166                 DEFINT(17,576),
1167                 /* Hook in check for video standard and adjust maximum
1168                    depending on the standard. */
1169                 .get_max_value = ctrl_vres_max_get,
1170                 .get_min_value = ctrl_vres_min_get,
1171         },{
1172                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1173                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1174                 .desc = "Audio Sampling Frequency",
1175                 .name = "srate",
1176                 DEFREF(srate),
1177                 DEFENUM(control_values_srate),
1178         },{
1179                 .desc = "Tuner Frequency (Hz)",
1180                 .name = "frequency",
1181                 .internal_id = PVR2_CID_FREQUENCY,
1182                 .default_value = 0,
1183                 .set_value = ctrl_freq_set,
1184                 .get_value = ctrl_freq_get,
1185                 .is_dirty = ctrl_freq_is_dirty,
1186                 .clear_dirty = ctrl_freq_clear_dirty,
1187                 DEFINT(0,0),
1188                 /* Hook in check for input value (tv/radio) and adjust
1189                    max/min values accordingly */
1190                 .get_max_value = ctrl_freq_max_get,
1191                 .get_min_value = ctrl_freq_min_get,
1192         },{
1193                 .desc = "Channel",
1194                 .name = "channel",
1195                 .set_value = ctrl_channel_set,
1196                 .get_value = ctrl_channel_get,
1197                 DEFINT(0,FREQTABLE_SIZE),
1198         },{
1199                 .desc = "Channel Program Frequency",
1200                 .name = "freq_table_value",
1201                 .set_value = ctrl_channelfreq_set,
1202                 .get_value = ctrl_channelfreq_get,
1203                 DEFINT(0,0),
1204                 /* Hook in check for input value (tv/radio) and adjust
1205                    max/min values accordingly */
1206                 .get_max_value = ctrl_freq_max_get,
1207                 .get_min_value = ctrl_freq_min_get,
1208         },{
1209                 .desc = "Channel Program ID",
1210                 .name = "freq_table_channel",
1211                 .set_value = ctrl_channelprog_set,
1212                 .get_value = ctrl_channelprog_get,
1213                 DEFINT(0,FREQTABLE_SIZE),
1214         },{
1215                 .desc = "Streaming Enabled",
1216                 .name = "streaming_enabled",
1217                 .get_value = ctrl_streamingenabled_get,
1218                 DEFBOOL,
1219         },{
1220                 .desc = "USB Speed",
1221                 .name = "usb_speed",
1222                 .get_value = ctrl_hsm_get,
1223                 DEFENUM(control_values_hsm),
1224         },{
1225                 .desc = "Master State",
1226                 .name = "master_state",
1227                 .get_value = ctrl_masterstate_get,
1228                 DEFENUM(pvr2_state_names),
1229         },{
1230                 .desc = "Signal Present",
1231                 .name = "signal_present",
1232                 .get_value = ctrl_signal_get,
1233                 DEFINT(0,65535),
1234         },{
1235                 .desc = "Audio Modes Present",
1236                 .name = "audio_modes_present",
1237                 .get_value = ctrl_audio_modes_present_get,
1238                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1239                    v4l.  Nothing outside of this module cares about this,
1240                    but I reuse it in order to also reuse the
1241                    control_values_audiomode string table. */
1242                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1243                          (1 << V4L2_TUNER_MODE_STEREO)|
1244                          (1 << V4L2_TUNER_MODE_LANG1)|
1245                          (1 << V4L2_TUNER_MODE_LANG2)),
1246                         control_values_audiomode),
1247         },{
1248                 .desc = "Video Standards Available Mask",
1249                 .name = "video_standard_mask_available",
1250                 .internal_id = PVR2_CID_STDAVAIL,
1251                 .skip_init = !0,
1252                 .get_value = ctrl_stdavail_get,
1253                 .set_value = ctrl_stdavail_set,
1254                 .val_to_sym = ctrl_std_val_to_sym,
1255                 .sym_to_val = ctrl_std_sym_to_val,
1256                 .type = pvr2_ctl_bitmask,
1257         },{
1258                 .desc = "Video Standards In Use Mask",
1259                 .name = "video_standard_mask_active",
1260                 .internal_id = PVR2_CID_STDCUR,
1261                 .skip_init = !0,
1262                 .get_value = ctrl_stdcur_get,
1263                 .set_value = ctrl_stdcur_set,
1264                 .is_dirty = ctrl_stdcur_is_dirty,
1265                 .clear_dirty = ctrl_stdcur_clear_dirty,
1266                 .val_to_sym = ctrl_std_val_to_sym,
1267                 .sym_to_val = ctrl_std_sym_to_val,
1268                 .type = pvr2_ctl_bitmask,
1269         },{
1270                 .desc = "Video Standard Name",
1271                 .name = "video_standard",
1272                 .internal_id = PVR2_CID_STDENUM,
1273                 .skip_init = !0,
1274                 .get_value = ctrl_stdenumcur_get,
1275                 .set_value = ctrl_stdenumcur_set,
1276                 .is_dirty = ctrl_stdenumcur_is_dirty,
1277                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1278                 .type = pvr2_ctl_enum,
1279         }
1280 };
1281
1282 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1283
1284
1285 const char *pvr2_config_get_name(enum pvr2_config cfg)
1286 {
1287         switch (cfg) {
1288         case pvr2_config_empty: return "empty";
1289         case pvr2_config_mpeg: return "mpeg";
1290         case pvr2_config_vbi: return "vbi";
1291         case pvr2_config_pcm: return "pcm";
1292         case pvr2_config_rawvideo: return "raw video";
1293         }
1294         return "<unknown>";
1295 }
1296
1297
1298 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1299 {
1300         return hdw->usb_dev;
1301 }
1302
1303
1304 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1305 {
1306         return hdw->serial_number;
1307 }
1308
1309
1310 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1311 {
1312         return hdw->bus_info;
1313 }
1314
1315
1316 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1317 {
1318         return hdw->identifier;
1319 }
1320
1321
1322 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1323 {
1324         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1325 }
1326
1327 /* Set the currently tuned frequency and account for all possible
1328    driver-core side effects of this action. */
1329 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1330 {
1331         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1332                 if (hdw->freqSelector) {
1333                         /* Swing over to radio frequency selection */
1334                         hdw->freqSelector = 0;
1335                         hdw->freqDirty = !0;
1336                 }
1337                 if (hdw->freqValRadio != val) {
1338                         hdw->freqValRadio = val;
1339                         hdw->freqSlotRadio = 0;
1340                         hdw->freqDirty = !0;
1341                 }
1342         } else {
1343                 if (!(hdw->freqSelector)) {
1344                         /* Swing over to television frequency selection */
1345                         hdw->freqSelector = 1;
1346                         hdw->freqDirty = !0;
1347                 }
1348                 if (hdw->freqValTelevision != val) {
1349                         hdw->freqValTelevision = val;
1350                         hdw->freqSlotTelevision = 0;
1351                         hdw->freqDirty = !0;
1352                 }
1353         }
1354 }
1355
1356 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1357 {
1358         return hdw->unit_number;
1359 }
1360
1361
1362 /* Attempt to locate one of the given set of files.  Messages are logged
1363    appropriate to what has been found.  The return value will be 0 or
1364    greater on success (it will be the index of the file name found) and
1365    fw_entry will be filled in.  Otherwise a negative error is returned on
1366    failure.  If the return value is -ENOENT then no viable firmware file
1367    could be located. */
1368 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1369                                 const struct firmware **fw_entry,
1370                                 const char *fwtypename,
1371                                 unsigned int fwcount,
1372                                 const char *fwnames[])
1373 {
1374         unsigned int idx;
1375         int ret = -EINVAL;
1376         for (idx = 0; idx < fwcount; idx++) {
1377                 ret = request_firmware(fw_entry,
1378                                        fwnames[idx],
1379                                        &hdw->usb_dev->dev);
1380                 if (!ret) {
1381                         trace_firmware("Located %s firmware: %s;"
1382                                        " uploading...",
1383                                        fwtypename,
1384                                        fwnames[idx]);
1385                         return idx;
1386                 }
1387                 if (ret == -ENOENT) continue;
1388                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1389                            "request_firmware fatal error with code=%d",ret);
1390                 return ret;
1391         }
1392         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1393                    "***WARNING***"
1394                    " Device %s firmware"
1395                    " seems to be missing.",
1396                    fwtypename);
1397         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1398                    "Did you install the pvrusb2 firmware files"
1399                    " in their proper location?");
1400         if (fwcount == 1) {
1401                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1402                            "request_firmware unable to locate %s file %s",
1403                            fwtypename,fwnames[0]);
1404         } else {
1405                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1406                            "request_firmware unable to locate"
1407                            " one of the following %s files:",
1408                            fwtypename);
1409                 for (idx = 0; idx < fwcount; idx++) {
1410                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1411                                    "request_firmware: Failed to find %s",
1412                                    fwnames[idx]);
1413                 }
1414         }
1415         return ret;
1416 }
1417
1418
1419 /*
1420  * pvr2_upload_firmware1().
1421  *
1422  * Send the 8051 firmware to the device.  After the upload, arrange for
1423  * device to re-enumerate.
1424  *
1425  * NOTE : the pointer to the firmware data given by request_firmware()
1426  * is not suitable for an usb transaction.
1427  *
1428  */
1429 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1430 {
1431         const struct firmware *fw_entry = NULL;
1432         void  *fw_ptr;
1433         unsigned int pipe;
1434         int ret;
1435         u16 address;
1436
1437         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1438                 hdw->fw1_state = FW1_STATE_OK;
1439                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1440                            "Connected device type defines"
1441                            " no firmware to upload; ignoring firmware");
1442                 return -ENOTTY;
1443         }
1444
1445         hdw->fw1_state = FW1_STATE_FAILED; // default result
1446
1447         trace_firmware("pvr2_upload_firmware1");
1448
1449         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1450                                    hdw->hdw_desc->fx2_firmware.cnt,
1451                                    hdw->hdw_desc->fx2_firmware.lst);
1452         if (ret < 0) {
1453                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1454                 return ret;
1455         }
1456
1457         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1458         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1459
1460         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1461
1462         if (fw_entry->size != 0x2000){
1463                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1464                 release_firmware(fw_entry);
1465                 return -ENOMEM;
1466         }
1467
1468         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1469         if (fw_ptr == NULL){
1470                 release_firmware(fw_entry);
1471                 return -ENOMEM;
1472         }
1473
1474         /* We have to hold the CPU during firmware upload. */
1475         pvr2_hdw_cpureset_assert(hdw,1);
1476
1477         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1478            chunk. */
1479
1480         ret = 0;
1481         for(address = 0; address < fw_entry->size; address += 0x800) {
1482                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1483                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1484                                        0, fw_ptr, 0x800, HZ);
1485         }
1486
1487         trace_firmware("Upload done, releasing device's CPU");
1488
1489         /* Now release the CPU.  It will disconnect and reconnect later. */
1490         pvr2_hdw_cpureset_assert(hdw,0);
1491
1492         kfree(fw_ptr);
1493         release_firmware(fw_entry);
1494
1495         trace_firmware("Upload done (%d bytes sent)",ret);
1496
1497         /* We should have written 8192 bytes */
1498         if (ret == 8192) {
1499                 hdw->fw1_state = FW1_STATE_RELOAD;
1500                 return 0;
1501         }
1502
1503         return -EIO;
1504 }
1505
1506
1507 /*
1508  * pvr2_upload_firmware2()
1509  *
1510  * This uploads encoder firmware on endpoint 2.
1511  *
1512  */
1513
1514 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1515 {
1516         const struct firmware *fw_entry = NULL;
1517         void  *fw_ptr;
1518         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1519         int actual_length;
1520         int ret = 0;
1521         int fwidx;
1522         static const char *fw_files[] = {
1523                 CX2341X_FIRM_ENC_FILENAME,
1524         };
1525
1526         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1527                 return 0;
1528         }
1529
1530         trace_firmware("pvr2_upload_firmware2");
1531
1532         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1533                                    ARRAY_SIZE(fw_files), fw_files);
1534         if (ret < 0) return ret;
1535         fwidx = ret;
1536         ret = 0;
1537         /* Since we're about to completely reinitialize the encoder,
1538            invalidate our cached copy of its configuration state.  Next
1539            time we configure the encoder, then we'll fully configure it. */
1540         hdw->enc_cur_valid = 0;
1541
1542         /* Encoder is about to be reset so note that as far as we're
1543            concerned now, the encoder has never been run. */
1544         del_timer_sync(&hdw->encoder_run_timer);
1545         if (hdw->state_encoder_runok) {
1546                 hdw->state_encoder_runok = 0;
1547                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1548         }
1549
1550         /* First prepare firmware loading */
1551         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1552         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1553         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1554         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1555         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1556         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1557         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1558         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1559         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1560         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1561         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1562         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1563         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1564         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1565         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1566         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1567         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1568         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1569
1570         if (ret) {
1571                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1572                            "firmware2 upload prep failed, ret=%d",ret);
1573                 release_firmware(fw_entry);
1574                 goto done;
1575         }
1576
1577         /* Now send firmware */
1578
1579         fw_len = fw_entry->size;
1580
1581         if (fw_len % sizeof(u32)) {
1582                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1583                            "size of %s firmware"
1584                            " must be a multiple of %zu bytes",
1585                            fw_files[fwidx],sizeof(u32));
1586                 release_firmware(fw_entry);
1587                 ret = -EINVAL;
1588                 goto done;
1589         }
1590
1591         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1592         if (fw_ptr == NULL){
1593                 release_firmware(fw_entry);
1594                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1595                            "failed to allocate memory for firmware2 upload");
1596                 ret = -ENOMEM;
1597                 goto done;
1598         }
1599
1600         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1601
1602         fw_done = 0;
1603         for (fw_done = 0; fw_done < fw_len;) {
1604                 bcnt = fw_len - fw_done;
1605                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1606                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1607                 /* Usbsnoop log shows that we must swap bytes... */
1608                 /* Some background info: The data being swapped here is a
1609                    firmware image destined for the mpeg encoder chip that
1610                    lives at the other end of a USB endpoint.  The encoder
1611                    chip always talks in 32 bit chunks and its storage is
1612                    organized into 32 bit words.  However from the file
1613                    system to the encoder chip everything is purely a byte
1614                    stream.  The firmware file's contents are always 32 bit
1615                    swapped from what the encoder expects.  Thus the need
1616                    always exists to swap the bytes regardless of the endian
1617                    type of the host processor and therefore swab32() makes
1618                    the most sense. */
1619                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1620                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1621
1622                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1623                                     &actual_length, HZ);
1624                 ret |= (actual_length != bcnt);
1625                 if (ret) break;
1626                 fw_done += bcnt;
1627         }
1628
1629         trace_firmware("upload of %s : %i / %i ",
1630                        fw_files[fwidx],fw_done,fw_len);
1631
1632         kfree(fw_ptr);
1633         release_firmware(fw_entry);
1634
1635         if (ret) {
1636                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1637                            "firmware2 upload transfer failure");
1638                 goto done;
1639         }
1640
1641         /* Finish upload */
1642
1643         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1644         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1645         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1646
1647         if (ret) {
1648                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1649                            "firmware2 upload post-proc failure");
1650         }
1651
1652  done:
1653         if (hdw->hdw_desc->signal_routing_scheme ==
1654             PVR2_ROUTING_SCHEME_GOTVIEW) {
1655                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1656                    hardware. */
1657                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1658         }
1659         return ret;
1660 }
1661
1662
1663 static const char *pvr2_get_state_name(unsigned int st)
1664 {
1665         if (st < ARRAY_SIZE(pvr2_state_names)) {
1666                 return pvr2_state_names[st];
1667         }
1668         return "???";
1669 }
1670
1671 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1672 {
1673         if (hdw->decoder_ctrl) {
1674                 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1675                 return 0;
1676         }
1677         /* Even though we really only care about the video decoder chip at
1678            this point, we'll broadcast stream on/off to all sub-devices
1679            anyway, just in case somebody else wants to hear the
1680            command... */
1681         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1682         if (hdw->decoder_client_id) {
1683                 /* We get here if the encoder has been noticed.  Otherwise
1684                    we'll issue a warning to the user (which should
1685                    normally never happen). */
1686                 return 0;
1687         }
1688         if (!hdw->flag_decoder_missed) {
1689                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1690                            "WARNING: No decoder present");
1691                 hdw->flag_decoder_missed = !0;
1692                 trace_stbit("flag_decoder_missed",
1693                             hdw->flag_decoder_missed);
1694         }
1695         return -EIO;
1696 }
1697
1698
1699 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1700 {
1701         if (hdw->decoder_ctrl == ptr) return;
1702         hdw->decoder_ctrl = ptr;
1703         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1704                 hdw->flag_decoder_missed = 0;
1705                 trace_stbit("flag_decoder_missed",
1706                             hdw->flag_decoder_missed);
1707                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1708                            "Decoder has appeared");
1709                 pvr2_hdw_state_sched(hdw);
1710         }
1711 }
1712
1713
1714 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1715 {
1716         return hdw->master_state;
1717 }
1718
1719
1720 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1721 {
1722         if (!hdw->flag_tripped) return 0;
1723         hdw->flag_tripped = 0;
1724         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1725                    "Clearing driver error statuss");
1726         return !0;
1727 }
1728
1729
1730 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1731 {
1732         int fl;
1733         LOCK_TAKE(hdw->big_lock); do {
1734                 fl = pvr2_hdw_untrip_unlocked(hdw);
1735         } while (0); LOCK_GIVE(hdw->big_lock);
1736         if (fl) pvr2_hdw_state_sched(hdw);
1737         return 0;
1738 }
1739
1740
1741
1742
1743 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1744 {
1745         return hdw->state_pipeline_req != 0;
1746 }
1747
1748
1749 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1750 {
1751         int ret,st;
1752         LOCK_TAKE(hdw->big_lock); do {
1753                 pvr2_hdw_untrip_unlocked(hdw);
1754                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1755                         hdw->state_pipeline_req = enable_flag != 0;
1756                         pvr2_trace(PVR2_TRACE_START_STOP,
1757                                    "/*--TRACE_STREAM--*/ %s",
1758                                    enable_flag ? "enable" : "disable");
1759                 }
1760                 pvr2_hdw_state_sched(hdw);
1761         } while (0); LOCK_GIVE(hdw->big_lock);
1762         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1763         if (enable_flag) {
1764                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1765                         if (st != PVR2_STATE_READY) return -EIO;
1766                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1767                 }
1768         }
1769         return 0;
1770 }
1771
1772
1773 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1774 {
1775         int fl;
1776         LOCK_TAKE(hdw->big_lock);
1777         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1778                 hdw->desired_stream_type = config;
1779                 hdw->state_pipeline_config = 0;
1780                 trace_stbit("state_pipeline_config",
1781                             hdw->state_pipeline_config);
1782                 pvr2_hdw_state_sched(hdw);
1783         }
1784         LOCK_GIVE(hdw->big_lock);
1785         if (fl) return 0;
1786         return pvr2_hdw_wait(hdw,0);
1787 }
1788
1789
1790 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1791 {
1792         int unit_number = hdw->unit_number;
1793         int tp = -1;
1794         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1795                 tp = tuner[unit_number];
1796         }
1797         if (tp < 0) return -EINVAL;
1798         hdw->tuner_type = tp;
1799         hdw->tuner_updated = !0;
1800         return 0;
1801 }
1802
1803
1804 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1805 {
1806         int unit_number = hdw->unit_number;
1807         int tp = 0;
1808         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1809                 tp = video_std[unit_number];
1810                 if (tp) return tp;
1811         }
1812         return 0;
1813 }
1814
1815
1816 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1817 {
1818         int unit_number = hdw->unit_number;
1819         int tp = 0;
1820         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1821                 tp = tolerance[unit_number];
1822         }
1823         return tp;
1824 }
1825
1826
1827 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1828 {
1829         /* Try a harmless request to fetch the eeprom's address over
1830            endpoint 1.  See what happens.  Only the full FX2 image can
1831            respond to this.  If this probe fails then likely the FX2
1832            firmware needs be loaded. */
1833         int result;
1834         LOCK_TAKE(hdw->ctl_lock); do {
1835                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1836                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1837                                            hdw->cmd_buffer,1,
1838                                            hdw->cmd_buffer,1);
1839                 if (result < 0) break;
1840         } while(0); LOCK_GIVE(hdw->ctl_lock);
1841         if (result) {
1842                 pvr2_trace(PVR2_TRACE_INIT,
1843                            "Probe of device endpoint 1 result status %d",
1844                            result);
1845         } else {
1846                 pvr2_trace(PVR2_TRACE_INIT,
1847                            "Probe of device endpoint 1 succeeded");
1848         }
1849         return result == 0;
1850 }
1851
1852 struct pvr2_std_hack {
1853         v4l2_std_id pat;  /* Pattern to match */
1854         v4l2_std_id msk;  /* Which bits we care about */
1855         v4l2_std_id std;  /* What additional standards or default to set */
1856 };
1857
1858 /* This data structure labels specific combinations of standards from
1859    tveeprom that we'll try to recognize.  If we recognize one, then assume
1860    a specified default standard to use.  This is here because tveeprom only
1861    tells us about available standards not the intended default standard (if
1862    any) for the device in question.  We guess the default based on what has
1863    been reported as available.  Note that this is only for guessing a
1864    default - which can always be overridden explicitly - and if the user
1865    has otherwise named a default then that default will always be used in
1866    place of this table. */
1867 static const struct pvr2_std_hack std_eeprom_maps[] = {
1868         {       /* PAL(B/G) */
1869                 .pat = V4L2_STD_B|V4L2_STD_GH,
1870                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1871         },
1872         {       /* NTSC(M) */
1873                 .pat = V4L2_STD_MN,
1874                 .std = V4L2_STD_NTSC_M,
1875         },
1876         {       /* PAL(I) */
1877                 .pat = V4L2_STD_PAL_I,
1878                 .std = V4L2_STD_PAL_I,
1879         },
1880         {       /* SECAM(L/L') */
1881                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1882                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1883         },
1884         {       /* PAL(D/D1/K) */
1885                 .pat = V4L2_STD_DK,
1886                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1887         },
1888 };
1889
1890 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1891 {
1892         char buf[40];
1893         unsigned int bcnt;
1894         v4l2_std_id std1,std2,std3;
1895
1896         std1 = get_default_standard(hdw);
1897         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1898
1899         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1900         pvr2_trace(PVR2_TRACE_STD,
1901                    "Supported video standard(s) reported available"
1902                    " in hardware: %.*s",
1903                    bcnt,buf);
1904
1905         hdw->std_mask_avail = hdw->std_mask_eeprom;
1906
1907         std2 = (std1|std3) & ~hdw->std_mask_avail;
1908         if (std2) {
1909                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1910                 pvr2_trace(PVR2_TRACE_STD,
1911                            "Expanding supported video standards"
1912                            " to include: %.*s",
1913                            bcnt,buf);
1914                 hdw->std_mask_avail |= std2;
1915         }
1916
1917         pvr2_hdw_internal_set_std_avail(hdw);
1918
1919         if (std1) {
1920                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1921                 pvr2_trace(PVR2_TRACE_STD,
1922                            "Initial video standard forced to %.*s",
1923                            bcnt,buf);
1924                 hdw->std_mask_cur = std1;
1925                 hdw->std_dirty = !0;
1926                 pvr2_hdw_internal_find_stdenum(hdw);
1927                 return;
1928         }
1929         if (std3) {
1930                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1931                 pvr2_trace(PVR2_TRACE_STD,
1932                            "Initial video standard"
1933                            " (determined by device type): %.*s",bcnt,buf);
1934                 hdw->std_mask_cur = std3;
1935                 hdw->std_dirty = !0;
1936                 pvr2_hdw_internal_find_stdenum(hdw);
1937                 return;
1938         }
1939
1940         {
1941                 unsigned int idx;
1942                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1943                         if (std_eeprom_maps[idx].msk ?
1944                             ((std_eeprom_maps[idx].pat ^
1945                              hdw->std_mask_eeprom) &
1946                              std_eeprom_maps[idx].msk) :
1947                             (std_eeprom_maps[idx].pat !=
1948                              hdw->std_mask_eeprom)) continue;
1949                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1950                                                   std_eeprom_maps[idx].std);
1951                         pvr2_trace(PVR2_TRACE_STD,
1952                                    "Initial video standard guessed as %.*s",
1953                                    bcnt,buf);
1954                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1955                         hdw->std_dirty = !0;
1956                         pvr2_hdw_internal_find_stdenum(hdw);
1957                         return;
1958                 }
1959         }
1960
1961         if (hdw->std_enum_cnt > 1) {
1962                 // Autoselect the first listed standard
1963                 hdw->std_enum_cur = 1;
1964                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1965                 hdw->std_dirty = !0;
1966                 pvr2_trace(PVR2_TRACE_STD,
1967                            "Initial video standard auto-selected to %s",
1968                            hdw->std_defs[hdw->std_enum_cur-1].name);
1969                 return;
1970         }
1971
1972         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1973                    "Unable to select a viable initial video standard");
1974 }
1975
1976
1977 static unsigned int pvr2_copy_i2c_addr_list(
1978         unsigned short *dst, const unsigned char *src,
1979         unsigned int dst_max)
1980 {
1981         unsigned int cnt;
1982         if (!src) return 0;
1983         while (src[cnt] && (cnt + 1) < dst_max) {
1984                 dst[cnt] = src[cnt];
1985                 cnt++;
1986         }
1987         dst[cnt] = I2C_CLIENT_END;
1988         return cnt;
1989 }
1990
1991
1992 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1993                                 const struct pvr2_device_client_desc *cd)
1994 {
1995         const char *fname;
1996         unsigned char mid;
1997         struct v4l2_subdev *sd;
1998         unsigned int i2ccnt;
1999         const unsigned char *p;
2000         /* Arbitrary count - max # i2c addresses we will probe */
2001         unsigned short i2caddr[25];
2002
2003         mid = cd->module_id;
2004         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2005         if (!fname) {
2006                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2007                            "Module ID %u for device %s has no name",
2008                            mid,
2009                            hdw->hdw_desc->description);
2010                 return -EINVAL;
2011         }
2012         pvr2_trace(PVR2_TRACE_INIT,
2013                    "Module ID %u (%s) for device %s being loaded...",
2014                    mid, fname,
2015                    hdw->hdw_desc->description);
2016
2017         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2018                                          ARRAY_SIZE(i2caddr));
2019         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2020                          module_i2c_addresses[mid] : NULL) != NULL)) {
2021                 /* Second chance: Try default i2c address list */
2022                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2023                                                  ARRAY_SIZE(i2caddr));
2024                 if (i2ccnt) {
2025                         pvr2_trace(PVR2_TRACE_INIT,
2026                                    "Module ID %u:"
2027                                    " Using default i2c address list",
2028                                    mid);
2029                 }
2030         }
2031
2032         if (!i2ccnt) {
2033                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2034                            "Module ID %u (%s) for device %s:"
2035                            " No i2c addresses",
2036                            mid, fname, hdw->hdw_desc->description);
2037                 return -EINVAL;
2038         }
2039
2040         /* Note how the 2nd and 3rd arguments are the same for both
2041          * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev().  Why?
2042          * Well the 2nd argument is the module name to load, while the 3rd
2043          * argument is documented in the framework as being the "chipid" -
2044          * and every other place where I can find examples of this, the
2045          * "chipid" appears to just be the module name again.  So here we
2046          * just do the same thing. */
2047         if (i2ccnt == 1) {
2048                 pvr2_trace(PVR2_TRACE_INIT,
2049                            "Module ID %u:"
2050                            " Setting up with specified i2c address 0x%x",
2051                            mid, i2caddr[0]);
2052                 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2053                                          fname, fname,
2054                                          i2caddr[0]);
2055         } else {
2056                 pvr2_trace(PVR2_TRACE_INIT,
2057                            "Module ID %u:"
2058                            " Setting up with address probe list",
2059                            mid);
2060                 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2061                                                 fname, fname,
2062                                                 i2caddr);
2063         }
2064
2065         if (!sd) {
2066                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2067                            "Module ID %u (%s) for device %s failed to load",
2068                            mid, fname, hdw->hdw_desc->description);
2069                 return -EIO;
2070         }
2071
2072         /* Tag this sub-device instance with the module ID we know about.
2073            In other places we'll use that tag to determine if the instance
2074            requires special handling. */
2075         sd->grp_id = mid;
2076
2077         /* If we have both old and new i2c layers enabled, make sure that
2078            old layer isn't also tracking this module.  This is a debugging
2079            aid, in normal situations there's no reason for both mechanisms
2080            to be enabled. */
2081         pvr2_i2c_untrack_subdev(hdw, sd);
2082         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2083
2084
2085         /* client-specific setup... */
2086         switch (mid) {
2087         case PVR2_CLIENT_ID_CX25840:
2088                 hdw->decoder_client_id = mid;
2089                 {
2090                         /*
2091                           Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2092                           bit of nuttiness for cx25840 causes that module
2093                           to correctly set up its video scaling.  This is
2094                           really a problem in the cx25840 module itself,
2095                           but we work around it here.  The problem has not
2096                           been seen in ivtv because there VBI is supported
2097                           and set up.  We don't do VBI here (at least not
2098                           yet) and thus we never attempted to even set it
2099                           up.
2100                         */
2101                         struct v4l2_format fmt;
2102                         pvr2_trace(PVR2_TRACE_INIT,
2103                                    "Module ID %u:"
2104                                    " Executing cx25840 VBI hack",
2105                                    mid);
2106                         memset(&fmt, 0, sizeof(fmt));
2107                         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2108                         v4l2_device_call_all(&hdw->v4l2_dev, mid,
2109                                              video, s_fmt, &fmt);
2110                 }
2111                 break;
2112         case PVR2_CLIENT_ID_SAA7115:
2113                 hdw->decoder_client_id = mid;
2114                 break;
2115         default: break;
2116         }
2117
2118         return 0;
2119 }
2120
2121
2122 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2123 {
2124         unsigned int idx;
2125         const struct pvr2_string_table *cm;
2126         const struct pvr2_device_client_table *ct;
2127         int okFl = !0;
2128
2129         cm = &hdw->hdw_desc->client_modules;
2130         for (idx = 0; idx < cm->cnt; idx++) {
2131                 request_module(cm->lst[idx]);
2132         }
2133
2134         ct = &hdw->hdw_desc->client_table;
2135         for (idx = 0; idx < ct->cnt; idx++) {
2136                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2137         }
2138         if (!okFl) pvr2_hdw_render_useless(hdw);
2139 }
2140
2141
2142 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2143 {
2144         int ret;
2145         unsigned int idx;
2146         struct pvr2_ctrl *cptr;
2147         int reloadFl = 0;
2148         if (hdw->hdw_desc->fx2_firmware.cnt) {
2149                 if (!reloadFl) {
2150                         reloadFl =
2151                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2152                                  == 0);
2153                         if (reloadFl) {
2154                                 pvr2_trace(PVR2_TRACE_INIT,
2155                                            "USB endpoint config looks strange"
2156                                            "; possibly firmware needs to be"
2157                                            " loaded");
2158                         }
2159                 }
2160                 if (!reloadFl) {
2161                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2162                         if (reloadFl) {
2163                                 pvr2_trace(PVR2_TRACE_INIT,
2164                                            "Check for FX2 firmware failed"
2165                                            "; possibly firmware needs to be"
2166                                            " loaded");
2167                         }
2168                 }
2169                 if (reloadFl) {
2170                         if (pvr2_upload_firmware1(hdw) != 0) {
2171                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2172                                            "Failure uploading firmware1");
2173                         }
2174                         return;
2175                 }
2176         }
2177         hdw->fw1_state = FW1_STATE_OK;
2178
2179         if (!pvr2_hdw_dev_ok(hdw)) return;
2180
2181         if (!hdw->hdw_desc->flag_no_powerup) {
2182                 pvr2_hdw_cmd_powerup(hdw);
2183                 if (!pvr2_hdw_dev_ok(hdw)) return;
2184         }
2185
2186         /* Take the IR chip out of reset, if appropriate */
2187         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2188                 pvr2_issue_simple_cmd(hdw,
2189                                       FX2CMD_HCW_ZILOG_RESET |
2190                                       (1 << 8) |
2191                                       ((0) << 16));
2192         }
2193
2194         // This step MUST happen after the earlier powerup step.
2195         pvr2_i2c_track_init(hdw);
2196         pvr2_i2c_core_init(hdw);
2197         if (!pvr2_hdw_dev_ok(hdw)) return;
2198
2199         pvr2_hdw_load_modules(hdw);
2200         if (!pvr2_hdw_dev_ok(hdw)) return;
2201
2202         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2203                 cptr = hdw->controls + idx;
2204                 if (cptr->info->skip_init) continue;
2205                 if (!cptr->info->set_value) continue;
2206                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2207         }
2208
2209         /* Set up special default values for the television and radio
2210            frequencies here.  It's not really important what these defaults
2211            are, but I set them to something usable in the Chicago area just
2212            to make driver testing a little easier. */
2213
2214         hdw->freqValTelevision = default_tv_freq;
2215         hdw->freqValRadio = default_radio_freq;
2216
2217         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2218         // thread-safe against the normal pvr2_send_request() mechanism.
2219         // (We should make it thread safe).
2220
2221         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2222                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2223                 if (!pvr2_hdw_dev_ok(hdw)) return;
2224                 if (ret < 0) {
2225                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2226                                    "Unable to determine location of eeprom,"
2227                                    " skipping");
2228                 } else {
2229                         hdw->eeprom_addr = ret;
2230                         pvr2_eeprom_analyze(hdw);
2231                         if (!pvr2_hdw_dev_ok(hdw)) return;
2232                 }
2233         } else {
2234                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2235                 hdw->tuner_updated = !0;
2236                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2237         }
2238
2239         if (hdw->serial_number) {
2240                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2241                                 "sn-%lu", hdw->serial_number);
2242         } else if (hdw->unit_number >= 0) {
2243                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2244                                 "unit-%c",
2245                                 hdw->unit_number + 'a');
2246         } else {
2247                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2248                                 "unit-??");
2249         }
2250         hdw->identifier[idx] = 0;
2251
2252         pvr2_hdw_setup_std(hdw);
2253
2254         if (!get_default_tuner_type(hdw)) {
2255                 pvr2_trace(PVR2_TRACE_INIT,
2256                            "pvr2_hdw_setup: Tuner type overridden to %d",
2257                            hdw->tuner_type);
2258         }
2259
2260         pvr2_i2c_core_check_stale(hdw);
2261         hdw->tuner_updated = 0;
2262
2263         if (!pvr2_hdw_dev_ok(hdw)) return;
2264
2265         if (hdw->hdw_desc->signal_routing_scheme ==
2266             PVR2_ROUTING_SCHEME_GOTVIEW) {
2267                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2268                    hardware. */
2269                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2270         }
2271
2272         pvr2_hdw_commit_setup(hdw);
2273
2274         hdw->vid_stream = pvr2_stream_create();
2275         if (!pvr2_hdw_dev_ok(hdw)) return;
2276         pvr2_trace(PVR2_TRACE_INIT,
2277                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2278         if (hdw->vid_stream) {
2279                 idx = get_default_error_tolerance(hdw);
2280                 if (idx) {
2281                         pvr2_trace(PVR2_TRACE_INIT,
2282                                    "pvr2_hdw_setup: video stream %p"
2283                                    " setting tolerance %u",
2284                                    hdw->vid_stream,idx);
2285                 }
2286                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2287                                   PVR2_VID_ENDPOINT,idx);
2288         }
2289
2290         if (!pvr2_hdw_dev_ok(hdw)) return;
2291
2292         hdw->flag_init_ok = !0;
2293
2294         pvr2_hdw_state_sched(hdw);
2295 }
2296
2297
2298 /* Set up the structure and attempt to put the device into a usable state.
2299    This can be a time-consuming operation, which is why it is not done
2300    internally as part of the create() step. */
2301 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2302 {
2303         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2304         do {
2305                 pvr2_hdw_setup_low(hdw);
2306                 pvr2_trace(PVR2_TRACE_INIT,
2307                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2308                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2309                 if (pvr2_hdw_dev_ok(hdw)) {
2310                         if (hdw->flag_init_ok) {
2311                                 pvr2_trace(
2312                                         PVR2_TRACE_INFO,
2313                                         "Device initialization"
2314                                         " completed successfully.");
2315                                 break;
2316                         }
2317                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2318                                 pvr2_trace(
2319                                         PVR2_TRACE_INFO,
2320                                         "Device microcontroller firmware"
2321                                         " (re)loaded; it should now reset"
2322                                         " and reconnect.");
2323                                 break;
2324                         }
2325                         pvr2_trace(
2326                                 PVR2_TRACE_ERROR_LEGS,
2327                                 "Device initialization was not successful.");
2328                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2329                                 pvr2_trace(
2330                                         PVR2_TRACE_ERROR_LEGS,
2331                                         "Giving up since device"
2332                                         " microcontroller firmware"
2333                                         " appears to be missing.");
2334                                 break;
2335                         }
2336                 }
2337                 if (procreload) {
2338                         pvr2_trace(
2339                                 PVR2_TRACE_ERROR_LEGS,
2340                                 "Attempting pvrusb2 recovery by reloading"
2341                                 " primary firmware.");
2342                         pvr2_trace(
2343                                 PVR2_TRACE_ERROR_LEGS,
2344                                 "If this works, device should disconnect"
2345                                 " and reconnect in a sane state.");
2346                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2347                         pvr2_upload_firmware1(hdw);
2348                 } else {
2349                         pvr2_trace(
2350                                 PVR2_TRACE_ERROR_LEGS,
2351                                 "***WARNING*** pvrusb2 device hardware"
2352                                 " appears to be jammed"
2353                                 " and I can't clear it.");
2354                         pvr2_trace(
2355                                 PVR2_TRACE_ERROR_LEGS,
2356                                 "You might need to power cycle"
2357                                 " the pvrusb2 device"
2358                                 " in order to recover.");
2359                 }
2360         } while (0);
2361         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2362 }
2363
2364
2365 /* Perform second stage initialization.  Set callback pointer first so that
2366    we can avoid a possible initialization race (if the kernel thread runs
2367    before the callback has been set). */
2368 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2369                         void (*callback_func)(void *),
2370                         void *callback_data)
2371 {
2372         LOCK_TAKE(hdw->big_lock); do {
2373                 if (hdw->flag_disconnected) {
2374                         /* Handle a race here: If we're already
2375                            disconnected by this point, then give up.  If we
2376                            get past this then we'll remain connected for
2377                            the duration of initialization since the entire
2378                            initialization sequence is now protected by the
2379                            big_lock. */
2380                         break;
2381                 }
2382                 hdw->state_data = callback_data;
2383                 hdw->state_func = callback_func;
2384                 pvr2_hdw_setup(hdw);
2385         } while (0); LOCK_GIVE(hdw->big_lock);
2386         return hdw->flag_init_ok;
2387 }
2388
2389
2390 /* Create, set up, and return a structure for interacting with the
2391    underlying hardware.  */
2392 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2393                                  const struct usb_device_id *devid)
2394 {
2395         unsigned int idx,cnt1,cnt2,m;
2396         struct pvr2_hdw *hdw = NULL;
2397         int valid_std_mask;
2398         struct pvr2_ctrl *cptr;
2399         struct usb_device *usb_dev;
2400         const struct pvr2_device_desc *hdw_desc;
2401         __u8 ifnum;
2402         struct v4l2_queryctrl qctrl;
2403         struct pvr2_ctl_info *ciptr;
2404
2405         usb_dev = interface_to_usbdev(intf);
2406
2407         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2408
2409         if (hdw_desc == NULL) {
2410                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2411                            " No device description pointer,"
2412                            " unable to continue.");
2413                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2414                            " please contact Mike Isely <isely@pobox.com>"
2415                            " to get it included in the driver\n");
2416                 goto fail;
2417         }
2418
2419         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2420         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2421                    hdw,hdw_desc->description);
2422         if (!hdw) goto fail;
2423
2424         init_timer(&hdw->quiescent_timer);
2425         hdw->quiescent_timer.data = (unsigned long)hdw;
2426         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2427
2428         init_timer(&hdw->encoder_wait_timer);
2429         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2430         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2431
2432         init_timer(&hdw->encoder_run_timer);
2433         hdw->encoder_run_timer.data = (unsigned long)hdw;
2434         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2435
2436         hdw->master_state = PVR2_STATE_DEAD;
2437
2438         init_waitqueue_head(&hdw->state_wait_data);
2439
2440         hdw->tuner_signal_stale = !0;
2441         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2442
2443         /* Calculate which inputs are OK */
2444         m = 0;
2445         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2446         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2447                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2448         }
2449         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2450         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2451         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2452         hdw->input_avail_mask = m;
2453         hdw->input_allowed_mask = hdw->input_avail_mask;
2454
2455         /* If not a hybrid device, pathway_state never changes.  So
2456            initialize it here to what it should forever be. */
2457         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2458                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2459         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2460                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2461         }
2462
2463         hdw->control_cnt = CTRLDEF_COUNT;
2464         hdw->control_cnt += MPEGDEF_COUNT;
2465         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2466                                 GFP_KERNEL);
2467         if (!hdw->controls) goto fail;
2468         hdw->hdw_desc = hdw_desc;
2469         for (idx = 0; idx < hdw->control_cnt; idx++) {
2470                 cptr = hdw->controls + idx;
2471                 cptr->hdw = hdw;
2472         }
2473         for (idx = 0; idx < 32; idx++) {
2474                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2475         }
2476         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2477                 cptr = hdw->controls + idx;
2478                 cptr->info = control_defs+idx;
2479         }
2480
2481         /* Ensure that default input choice is a valid one. */
2482         m = hdw->input_avail_mask;
2483         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2484                 if (!((1 << idx) & m)) continue;
2485                 hdw->input_val = idx;
2486                 break;
2487         }
2488
2489         /* Define and configure additional controls from cx2341x module. */
2490         hdw->mpeg_ctrl_info = kzalloc(
2491                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2492         if (!hdw->mpeg_ctrl_info) goto fail;
2493         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2494                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2495                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2496                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2497                 ciptr->name = mpeg_ids[idx].strid;
2498                 ciptr->v4l_id = mpeg_ids[idx].id;
2499                 ciptr->skip_init = !0;
2500                 ciptr->get_value = ctrl_cx2341x_get;
2501                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2502                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2503                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2504                 qctrl.id = ciptr->v4l_id;
2505                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2506                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2507                         ciptr->set_value = ctrl_cx2341x_set;
2508                 }
2509                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2510                         PVR2_CTLD_INFO_DESC_SIZE);
2511                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2512                 ciptr->default_value = qctrl.default_value;
2513                 switch (qctrl.type) {
2514                 default:
2515                 case V4L2_CTRL_TYPE_INTEGER:
2516                         ciptr->type = pvr2_ctl_int;
2517                         ciptr->def.type_int.min_value = qctrl.minimum;
2518                         ciptr->def.type_int.max_value = qctrl.maximum;
2519                         break;
2520                 case V4L2_CTRL_TYPE_BOOLEAN:
2521                         ciptr->type = pvr2_ctl_bool;
2522                         break;
2523                 case V4L2_CTRL_TYPE_MENU:
2524                         ciptr->type = pvr2_ctl_enum;
2525                         ciptr->def.type_enum.value_names =
2526                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2527                                                                 ciptr->v4l_id);
2528                         for (cnt1 = 0;
2529                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2530                              cnt1++) { }
2531                         ciptr->def.type_enum.count = cnt1;
2532                         break;
2533                 }
2534                 cptr->info = ciptr;
2535         }
2536
2537         // Initialize video standard enum dynamic control
2538         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2539         if (cptr) {
2540                 memcpy(&hdw->std_info_enum,cptr->info,
2541                        sizeof(hdw->std_info_enum));
2542                 cptr->info = &hdw->std_info_enum;
2543
2544         }
2545         // Initialize control data regarding video standard masks
2546         valid_std_mask = pvr2_std_get_usable();
2547         for (idx = 0; idx < 32; idx++) {
2548                 if (!(valid_std_mask & (1 << idx))) continue;
2549                 cnt1 = pvr2_std_id_to_str(
2550                         hdw->std_mask_names[idx],
2551                         sizeof(hdw->std_mask_names[idx])-1,
2552                         1 << idx);
2553                 hdw->std_mask_names[idx][cnt1] = 0;
2554         }
2555         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2556         if (cptr) {
2557                 memcpy(&hdw->std_info_avail,cptr->info,
2558                        sizeof(hdw->std_info_avail));
2559                 cptr->info = &hdw->std_info_avail;
2560                 hdw->std_info_avail.def.type_bitmask.bit_names =
2561                         hdw->std_mask_ptrs;
2562                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2563                         valid_std_mask;
2564         }
2565         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2566         if (cptr) {
2567                 memcpy(&hdw->std_info_cur,cptr->info,
2568                        sizeof(hdw->std_info_cur));
2569                 cptr->info = &hdw->std_info_cur;
2570                 hdw->std_info_cur.def.type_bitmask.bit_names =
2571                         hdw->std_mask_ptrs;
2572                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2573                         valid_std_mask;
2574         }
2575
2576         hdw->cropcap_stale = !0;
2577         hdw->eeprom_addr = -1;
2578         hdw->unit_number = -1;
2579         hdw->v4l_minor_number_video = -1;
2580         hdw->v4l_minor_number_vbi = -1;
2581         hdw->v4l_minor_number_radio = -1;
2582         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2583         if (!hdw->ctl_write_buffer) goto fail;
2584         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2585         if (!hdw->ctl_read_buffer) goto fail;
2586         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2587         if (!hdw->ctl_write_urb) goto fail;
2588         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2589         if (!hdw->ctl_read_urb) goto fail;
2590
2591         if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2592                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2593                            "Error registering with v4l core, giving up");
2594                 goto fail;
2595         }
2596         mutex_lock(&pvr2_unit_mtx); do {
2597                 for (idx = 0; idx < PVR_NUM; idx++) {
2598                         if (unit_pointers[idx]) continue;
2599                         hdw->unit_number = idx;
2600                         unit_pointers[idx] = hdw;
2601                         break;
2602                 }
2603         } while (0); mutex_unlock(&pvr2_unit_mtx);
2604
2605         cnt1 = 0;
2606         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2607         cnt1 += cnt2;
2608         if (hdw->unit_number >= 0) {
2609                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2610                                  ('a' + hdw->unit_number));
2611                 cnt1 += cnt2;
2612         }
2613         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2614         hdw->name[cnt1] = 0;
2615
2616         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2617         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2618         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2619
2620         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2621                    hdw->unit_number,hdw->name);
2622
2623         hdw->tuner_type = -1;
2624         hdw->flag_ok = !0;
2625
2626         hdw->usb_intf = intf;
2627         hdw->usb_dev = usb_dev;
2628
2629         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2630
2631         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2632         usb_set_interface(hdw->usb_dev,ifnum,0);
2633
2634         mutex_init(&hdw->ctl_lock_mutex);
2635         mutex_init(&hdw->big_lock_mutex);
2636
2637         return hdw;
2638  fail:
2639         if (hdw) {
2640                 del_timer_sync(&hdw->quiescent_timer);
2641                 del_timer_sync(&hdw->encoder_run_timer);
2642                 del_timer_sync(&hdw->encoder_wait_timer);
2643                 if (hdw->workqueue) {
2644                         flush_workqueue(hdw->workqueue);
2645                         destroy_workqueue(hdw->workqueue);
2646                         hdw->workqueue = NULL;
2647                 }
2648                 usb_free_urb(hdw->ctl_read_urb);
2649                 usb_free_urb(hdw->ctl_write_urb);
2650                 kfree(hdw->ctl_read_buffer);
2651                 kfree(hdw->ctl_write_buffer);
2652                 kfree(hdw->controls);
2653                 kfree(hdw->mpeg_ctrl_info);
2654                 kfree(hdw->std_defs);
2655                 kfree(hdw->std_enum_names);
2656                 kfree(hdw);
2657         }
2658         return NULL;
2659 }
2660
2661
2662 /* Remove _all_ associations between this driver and the underlying USB
2663    layer. */
2664 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2665 {
2666         if (hdw->flag_disconnected) return;
2667         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2668         if (hdw->ctl_read_urb) {
2669                 usb_kill_urb(hdw->ctl_read_urb);
2670                 usb_free_urb(hdw->ctl_read_urb);
2671                 hdw->ctl_read_urb = NULL;
2672         }
2673         if (hdw->ctl_write_urb) {
2674                 usb_kill_urb(hdw->ctl_write_urb);
2675                 usb_free_urb(hdw->ctl_write_urb);
2676                 hdw->ctl_write_urb = NULL;
2677         }
2678         if (hdw->ctl_read_buffer) {
2679                 kfree(hdw->ctl_read_buffer);
2680                 hdw->ctl_read_buffer = NULL;
2681         }
2682         if (hdw->ctl_write_buffer) {
2683                 kfree(hdw->ctl_write_buffer);
2684                 hdw->ctl_write_buffer = NULL;
2685         }
2686         hdw->flag_disconnected = !0;
2687         /* If we don't do this, then there will be a dangling struct device
2688            reference to our disappearing device persisting inside the V4L
2689            core... */
2690         if (hdw->v4l2_dev.dev) {
2691                 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2692                 hdw->v4l2_dev.dev = NULL;
2693         }
2694         hdw->usb_dev = NULL;
2695         hdw->usb_intf = NULL;
2696         pvr2_hdw_render_useless(hdw);
2697 }
2698
2699
2700 /* Destroy hardware interaction structure */
2701 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2702 {
2703         if (!hdw) return;
2704         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2705         if (hdw->workqueue) {
2706                 flush_workqueue(hdw->workqueue);
2707                 destroy_workqueue(hdw->workqueue);
2708                 hdw->workqueue = NULL;
2709         }
2710         del_timer_sync(&hdw->quiescent_timer);
2711         del_timer_sync(&hdw->encoder_run_timer);
2712         del_timer_sync(&hdw->encoder_wait_timer);
2713         if (hdw->fw_buffer) {
2714                 kfree(hdw->fw_buffer);
2715                 hdw->fw_buffer = NULL;
2716         }
2717         if (hdw->vid_stream) {
2718                 pvr2_stream_destroy(hdw->vid_stream);
2719                 hdw->vid_stream = NULL;
2720         }
2721         if (hdw->decoder_ctrl) {
2722                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2723         }
2724         pvr2_i2c_core_done(hdw);
2725         pvr2_i2c_track_done(hdw);
2726         v4l2_device_unregister(&hdw->v4l2_dev);
2727         pvr2_hdw_remove_usb_stuff(hdw);
2728         mutex_lock(&pvr2_unit_mtx); do {
2729                 if ((hdw->unit_number >= 0) &&
2730                     (hdw->unit_number < PVR_NUM) &&
2731                     (unit_pointers[hdw->unit_number] == hdw)) {
2732                         unit_pointers[hdw->unit_number] = NULL;
2733                 }
2734         } while (0); mutex_unlock(&pvr2_unit_mtx);
2735         kfree(hdw->controls);
2736         kfree(hdw->mpeg_ctrl_info);
2737         kfree(hdw->std_defs);
2738         kfree(hdw->std_enum_names);
2739         kfree(hdw);
2740 }
2741
2742
2743 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2744 {
2745         return (hdw && hdw->flag_ok);
2746 }
2747
2748
2749 /* Called when hardware has been unplugged */
2750 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2751 {
2752         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2753         LOCK_TAKE(hdw->big_lock);
2754         LOCK_TAKE(hdw->ctl_lock);
2755         pvr2_hdw_remove_usb_stuff(hdw);
2756         LOCK_GIVE(hdw->ctl_lock);
2757         LOCK_GIVE(hdw->big_lock);
2758 }
2759
2760
2761 // Attempt to autoselect an appropriate value for std_enum_cur given
2762 // whatever is currently in std_mask_cur
2763 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2764 {
2765         unsigned int idx;
2766         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2767                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2768                         hdw->std_enum_cur = idx;
2769                         return;
2770                 }
2771         }
2772         hdw->std_enum_cur = 0;
2773 }
2774
2775
2776 // Calculate correct set of enumerated standards based on currently known
2777 // set of available standards bits.
2778 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2779 {
2780         struct v4l2_standard *newstd;
2781         unsigned int std_cnt;
2782         unsigned int idx;
2783
2784         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2785
2786         if (hdw->std_defs) {
2787                 kfree(hdw->std_defs);
2788                 hdw->std_defs = NULL;
2789         }
2790         hdw->std_enum_cnt = 0;
2791         if (hdw->std_enum_names) {
2792                 kfree(hdw->std_enum_names);
2793                 hdw->std_enum_names = NULL;
2794         }
2795
2796         if (!std_cnt) {
2797                 pvr2_trace(
2798                         PVR2_TRACE_ERROR_LEGS,
2799                         "WARNING: Failed to identify any viable standards");
2800         }
2801         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2802         hdw->std_enum_names[0] = "none";
2803         for (idx = 0; idx < std_cnt; idx++) {
2804                 hdw->std_enum_names[idx+1] =
2805                         newstd[idx].name;
2806         }
2807         // Set up the dynamic control for this standard
2808         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2809         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2810         hdw->std_defs = newstd;
2811         hdw->std_enum_cnt = std_cnt+1;
2812         hdw->std_enum_cur = 0;
2813         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2814 }
2815
2816
2817 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2818                                struct v4l2_standard *std,
2819                                unsigned int idx)
2820 {
2821         int ret = -EINVAL;
2822         if (!idx) return ret;
2823         LOCK_TAKE(hdw->big_lock); do {
2824                 if (idx >= hdw->std_enum_cnt) break;
2825                 idx--;
2826                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2827                 ret = 0;
2828         } while (0); LOCK_GIVE(hdw->big_lock);
2829         return ret;
2830 }
2831
2832
2833 /* Get the number of defined controls */
2834 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2835 {
2836         return hdw->control_cnt;
2837 }
2838
2839
2840 /* Retrieve a control handle given its index (0..count-1) */
2841 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2842                                              unsigned int idx)
2843 {
2844         if (idx >= hdw->control_cnt) return NULL;
2845         return hdw->controls + idx;
2846 }
2847
2848
2849 /* Retrieve a control handle given its index (0..count-1) */
2850 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2851                                           unsigned int ctl_id)
2852 {
2853         struct pvr2_ctrl *cptr;
2854         unsigned int idx;
2855         int i;
2856
2857         /* This could be made a lot more efficient, but for now... */
2858         for (idx = 0; idx < hdw->control_cnt; idx++) {
2859                 cptr = hdw->controls + idx;
2860                 i = cptr->info->internal_id;
2861                 if (i && (i == ctl_id)) return cptr;
2862         }
2863         return NULL;
2864 }
2865
2866
2867 /* Given a V4L ID, retrieve the control structure associated with it. */
2868 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2869 {
2870         struct pvr2_ctrl *cptr;
2871         unsigned int idx;
2872         int i;
2873
2874         /* This could be made a lot more efficient, but for now... */
2875         for (idx = 0; idx < hdw->control_cnt; idx++) {
2876                 cptr = hdw->controls + idx;
2877                 i = cptr->info->v4l_id;
2878                 if (i && (i == ctl_id)) return cptr;
2879         }
2880         return NULL;
2881 }
2882
2883
2884 /* Given a V4L ID for its immediate predecessor, retrieve the control
2885    structure associated with it. */
2886 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2887                                             unsigned int ctl_id)
2888 {
2889         struct pvr2_ctrl *cptr,*cp2;
2890         unsigned int idx;
2891         int i;
2892
2893         /* This could be made a lot more efficient, but for now... */
2894         cp2 = NULL;
2895         for (idx = 0; idx < hdw->control_cnt; idx++) {
2896                 cptr = hdw->controls + idx;
2897                 i = cptr->info->v4l_id;
2898                 if (!i) continue;
2899                 if (i <= ctl_id) continue;
2900                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2901                 cp2 = cptr;
2902         }
2903         return cp2;
2904         return NULL;
2905 }
2906
2907
2908 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2909 {
2910         switch (tp) {
2911         case pvr2_ctl_int: return "integer";
2912         case pvr2_ctl_enum: return "enum";
2913         case pvr2_ctl_bool: return "boolean";
2914         case pvr2_ctl_bitmask: return "bitmask";
2915         }
2916         return "";
2917 }
2918
2919
2920 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2921                                     const char *name, int val)
2922 {
2923         struct v4l2_control ctrl;
2924         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2925         memset(&ctrl, 0, sizeof(ctrl));
2926         ctrl.id = id;
2927         ctrl.value = val;
2928         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2929 }
2930
2931 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2932         if ((hdw)->lab##_dirty) { \
2933                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2934         }
2935
2936 /* Execute whatever commands are required to update the state of all the
2937    sub-devices so that they match our current control values. */
2938 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2939 {
2940         struct v4l2_subdev *sd;
2941         unsigned int id;
2942         pvr2_subdev_update_func fp;
2943
2944         if (hdw->input_dirty || hdw->std_dirty) {
2945                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_standard");
2946                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2947                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2948                                              tuner, s_radio);
2949                 } else {
2950                         v4l2_std_id vs;
2951                         vs = hdw->std_mask_cur;
2952                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2953                                              tuner, s_std, vs);
2954                 }
2955                 hdw->tuner_signal_stale = !0;
2956                 hdw->cropcap_stale = !0;
2957         }
2958
2959         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2960         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2961         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2962         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2963         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2964         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2965         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2966         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2967         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2968
2969         if (hdw->input_dirty || hdw->audiomode_dirty) {
2970                 struct v4l2_tuner vt;
2971                 memset(&vt, 0, sizeof(vt));
2972                 vt.audmode = hdw->audiomode_val;
2973                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2974         }
2975
2976         if (hdw->freqDirty) {
2977                 unsigned long fv;
2978                 struct v4l2_frequency freq;
2979                 fv = pvr2_hdw_get_cur_freq(hdw);
2980                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2981                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2982                 memset(&freq, 0, sizeof(freq));
2983                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2984                         /* ((fv * 1000) / 62500) */
2985                         freq.frequency = (fv * 2) / 125;
2986                 } else {
2987                         freq.frequency = fv / 62500;
2988                 }
2989                 /* tuner-core currently doesn't seem to care about this, but
2990                    let's set it anyway for completeness. */
2991                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2992                         freq.type = V4L2_TUNER_RADIO;
2993                 } else {
2994                         freq.type = V4L2_TUNER_ANALOG_TV;
2995                 }
2996                 freq.tuner = 0;
2997                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2998                                      s_frequency, &freq);
2999         }
3000
3001         if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
3002                 struct v4l2_format fmt;
3003                 memset(&fmt, 0, sizeof(fmt));
3004                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3005                 fmt.fmt.pix.width = hdw->res_hor_val;
3006                 fmt.fmt.pix.height = hdw->res_ver_val;
3007                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
3008                            fmt.fmt.pix.width, fmt.fmt.pix.height);
3009                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3010         }
3011
3012         if (hdw->srate_dirty) {
3013                 u32 val;
3014                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3015                            hdw->srate_val);
3016                 switch (hdw->srate_val) {
3017                 default:
3018                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3019                         val = 48000;
3020                         break;
3021                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3022                         val = 44100;
3023                         break;
3024                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3025                         val = 32000;
3026                         break;
3027                 }
3028                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3029                                      audio, s_clock_freq, val);
3030         }
3031
3032         /* Unable to set crop parameters; there is apparently no equivalent
3033            for VIDIOC_S_CROP */
3034
3035         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3036                 id = sd->grp_id;
3037                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3038                 fp = pvr2_module_update_functions[id];
3039                 if (!fp) continue;
3040                 (*fp)(hdw, sd);
3041         }
3042
3043         if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
3044                 pvr2_hdw_status_poll(hdw);
3045         }
3046 }
3047
3048
3049 /* Figure out if we need to commit control changes.  If so, mark internal
3050    state flags to indicate this fact and return true.  Otherwise do nothing
3051    else and return false. */
3052 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3053 {
3054         unsigned int idx;
3055         struct pvr2_ctrl *cptr;
3056         int value;
3057         int commit_flag = 0;
3058         char buf[100];
3059         unsigned int bcnt,ccnt;
3060
3061         for (idx = 0; idx < hdw->control_cnt; idx++) {
3062                 cptr = hdw->controls + idx;
3063                 if (!cptr->info->is_dirty) continue;
3064                 if (!cptr->info->is_dirty(cptr)) continue;
3065                 commit_flag = !0;
3066
3067                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3068                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3069                                  cptr->info->name);
3070                 value = 0;
3071                 cptr->info->get_value(cptr,&value);
3072                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3073                                                 buf+bcnt,
3074                                                 sizeof(buf)-bcnt,&ccnt);
3075                 bcnt += ccnt;
3076                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3077                                   get_ctrl_typename(cptr->info->type));
3078                 pvr2_trace(PVR2_TRACE_CTL,
3079                            "/*--TRACE_COMMIT--*/ %.*s",
3080                            bcnt,buf);
3081         }
3082
3083         if (!commit_flag) {
3084                 /* Nothing has changed */
3085                 return 0;
3086         }
3087
3088         hdw->state_pipeline_config = 0;
3089         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3090         pvr2_hdw_state_sched(hdw);
3091
3092         return !0;
3093 }
3094
3095
3096 /* Perform all operations needed to commit all control changes.  This must
3097    be performed in synchronization with the pipeline state and is thus
3098    expected to be called as part of the driver's worker thread.  Return
3099    true if commit successful, otherwise return false to indicate that
3100    commit isn't possible at this time. */
3101 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3102 {
3103         unsigned int idx;
3104         struct pvr2_ctrl *cptr;
3105         int disruptive_change;
3106
3107         /* Handle some required side effects when the video standard is
3108            changed.... */
3109         if (hdw->std_dirty) {
3110                 int nvres;
3111                 int gop_size;
3112                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3113                         nvres = 480;
3114                         gop_size = 15;
3115                 } else {
3116                         nvres = 576;
3117                         gop_size = 12;
3118                 }
3119                 /* Rewrite the vertical resolution to be appropriate to the
3120                    video standard that has been selected. */
3121                 if (nvres != hdw->res_ver_val) {
3122                         hdw->res_ver_val = nvres;
3123                         hdw->res_ver_dirty = !0;
3124                 }
3125                 /* Rewrite the GOP size to be appropriate to the video
3126                    standard that has been selected. */
3127                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3128                         struct v4l2_ext_controls cs;
3129                         struct v4l2_ext_control c1;
3130                         memset(&cs, 0, sizeof(cs));
3131                         memset(&c1, 0, sizeof(c1));
3132                         cs.controls = &c1;
3133                         cs.count = 1;
3134                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3135                         c1.value = gop_size;
3136                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3137                                           VIDIOC_S_EXT_CTRLS);
3138                 }
3139         }
3140
3141         if (hdw->input_dirty && hdw->state_pathway_ok &&
3142             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3143               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3144              hdw->pathway_state)) {
3145                 /* Change of mode being asked for... */
3146                 hdw->state_pathway_ok = 0;
3147                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3148         }
3149         if (!hdw->state_pathway_ok) {
3150                 /* Can't commit anything until pathway is ok. */
3151                 return 0;
3152         }
3153         /* The broadcast decoder can only scale down, so if
3154          * res_*_dirty && crop window < output format ==> enlarge crop.
3155          *
3156          * The mpeg encoder receives fields of res_hor_val dots and
3157          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3158          */
3159         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3160                 hdw->cropw_val = hdw->res_hor_val;
3161                 hdw->cropw_dirty = !0;
3162         } else if (hdw->cropw_dirty) {
3163                 hdw->res_hor_dirty = !0;           /* must rescale */
3164                 hdw->res_hor_val = min(720, hdw->cropw_val);
3165         }
3166         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3167                 hdw->croph_val = hdw->res_ver_val;
3168                 hdw->croph_dirty = !0;
3169         } else if (hdw->croph_dirty) {
3170                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3171                 hdw->res_ver_dirty = !0;
3172                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3173         }
3174
3175         /* If any of the below has changed, then we can't do the update
3176            while the pipeline is running.  Pipeline must be paused first
3177            and decoder -> encoder connection be made quiescent before we
3178            can proceed. */
3179         disruptive_change =
3180                 (hdw->std_dirty ||
3181                  hdw->enc_unsafe_stale ||
3182                  hdw->srate_dirty ||
3183                  hdw->res_ver_dirty ||
3184                  hdw->res_hor_dirty ||
3185                  hdw->cropw_dirty ||
3186                  hdw->croph_dirty ||
3187                  hdw->input_dirty ||
3188                  (hdw->active_stream_type != hdw->desired_stream_type));
3189         if (disruptive_change && !hdw->state_pipeline_idle) {
3190                 /* Pipeline is not idle; we can't proceed.  Arrange to
3191                    cause pipeline to stop so that we can try this again
3192                    later.... */
3193                 hdw->state_pipeline_pause = !0;
3194                 return 0;
3195         }
3196
3197         if (hdw->srate_dirty) {
3198                 /* Write new sample rate into control structure since
3199                  * the master copy is stale.  We must track srate
3200                  * separate from the mpeg control structure because
3201                  * other logic also uses this value. */
3202                 struct v4l2_ext_controls cs;
3203                 struct v4l2_ext_control c1;
3204                 memset(&cs,0,sizeof(cs));
3205                 memset(&c1,0,sizeof(c1));
3206                 cs.controls = &c1;
3207                 cs.count = 1;
3208                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3209                 c1.value = hdw->srate_val;
3210                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3211         }
3212
3213         /* Scan i2c core at this point - before we clear all the dirty
3214            bits.  Various parts of the i2c core will notice dirty bits as
3215            appropriate and arrange to broadcast or directly send updates to
3216            the client drivers in order to keep everything in sync */
3217         pvr2_i2c_core_check_stale(hdw);
3218
3219         if (hdw->active_stream_type != hdw->desired_stream_type) {
3220                 /* Handle any side effects of stream config here */
3221                 hdw->active_stream_type = hdw->desired_stream_type;
3222         }
3223
3224         if (hdw->hdw_desc->signal_routing_scheme ==
3225             PVR2_ROUTING_SCHEME_GOTVIEW) {
3226                 u32 b;
3227                 /* Handle GOTVIEW audio switching */
3228                 pvr2_hdw_gpio_get_out(hdw,&b);
3229                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3230                         /* Set GPIO 11 */
3231                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3232                 } else {
3233                         /* Clear GPIO 11 */
3234                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3235                 }
3236         }
3237
3238         for (idx = 0; idx < hdw->control_cnt; idx++) {
3239                 cptr = hdw->controls + idx;
3240                 if (!cptr->info->clear_dirty) continue;
3241                 cptr->info->clear_dirty(cptr);
3242         }
3243
3244         /* Check and update state for all sub-devices. */
3245         pvr2_subdev_update(hdw);
3246
3247         /* Now execute i2c core update */
3248         pvr2_i2c_core_sync(hdw);
3249
3250         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3251             hdw->state_encoder_run) {
3252                 /* If encoder isn't running or it can't be touched, then
3253                    this will get worked out later when we start the
3254                    encoder. */
3255                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3256         }
3257
3258         hdw->state_pipeline_config = !0;
3259         /* Hardware state may have changed in a way to cause the cropping
3260            capabilities to have changed.  So mark it stale, which will
3261            cause a later re-fetch. */
3262         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3263         return !0;
3264 }
3265
3266
3267 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3268 {
3269         int fl;
3270         LOCK_TAKE(hdw->big_lock);
3271         fl = pvr2_hdw_commit_setup(hdw);
3272         LOCK_GIVE(hdw->big_lock);
3273         if (!fl) return 0;
3274         return pvr2_hdw_wait(hdw,0);
3275 }
3276
3277
3278 static void pvr2_hdw_worker_i2c(struct work_struct *work)
3279 {
3280         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
3281         LOCK_TAKE(hdw->big_lock); do {
3282                 pvr2_i2c_core_sync(hdw);
3283         } while (0); LOCK_GIVE(hdw->big_lock);
3284 }
3285
3286
3287 static void pvr2_hdw_worker_poll(struct work_struct *work)
3288 {
3289         int fl = 0;
3290         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3291         LOCK_TAKE(hdw->big_lock); do {
3292                 fl = pvr2_hdw_state_eval(hdw);
3293         } while (0); LOCK_GIVE(hdw->big_lock);
3294         if (fl && hdw->state_func) {
3295                 hdw->state_func(hdw->state_data);
3296         }
3297 }
3298
3299
3300 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3301 {
3302         return wait_event_interruptible(
3303                 hdw->state_wait_data,
3304                 (hdw->state_stale == 0) &&
3305                 (!state || (hdw->master_state != state)));
3306 }
3307
3308
3309 /* Return name for this driver instance */
3310 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3311 {
3312         return hdw->name;
3313 }
3314
3315
3316 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3317 {
3318         return hdw->hdw_desc->description;
3319 }
3320
3321
3322 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3323 {
3324         return hdw->hdw_desc->shortname;
3325 }
3326
3327
3328 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3329 {
3330         int result;
3331         LOCK_TAKE(hdw->ctl_lock); do {
3332                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3333                 result = pvr2_send_request(hdw,
3334                                            hdw->cmd_buffer,1,
3335                                            hdw->cmd_buffer,1);
3336                 if (result < 0) break;
3337                 result = (hdw->cmd_buffer[0] != 0);
3338         } while(0); LOCK_GIVE(hdw->ctl_lock);
3339         return result;
3340 }
3341
3342
3343 /* Execute poll of tuner status */
3344 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3345 {
3346         LOCK_TAKE(hdw->big_lock); do {
3347                 pvr2_hdw_status_poll(hdw);
3348         } while (0); LOCK_GIVE(hdw->big_lock);
3349 }
3350
3351
3352 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3353 {
3354         if (!hdw->cropcap_stale) {
3355                 return 0;
3356         }
3357         pvr2_hdw_status_poll(hdw);
3358         if (hdw->cropcap_stale) {
3359                 return -EIO;
3360         }
3361         return 0;
3362 }
3363
3364
3365 /* Return information about cropping capabilities */
3366 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3367 {
3368         int stat = 0;
3369         LOCK_TAKE(hdw->big_lock);
3370         stat = pvr2_hdw_check_cropcap(hdw);
3371         if (!stat) {
3372                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3373         }
3374         LOCK_GIVE(hdw->big_lock);
3375         return stat;
3376 }
3377
3378
3379 /* Return information about the tuner */
3380 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3381 {
3382         LOCK_TAKE(hdw->big_lock); do {
3383                 if (hdw->tuner_signal_stale) {
3384                         pvr2_hdw_status_poll(hdw);
3385                 }
3386                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3387         } while (0); LOCK_GIVE(hdw->big_lock);
3388         return 0;
3389 }
3390
3391
3392 /* Get handle to video output stream */
3393 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3394 {
3395         return hp->vid_stream;
3396 }
3397
3398
3399 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3400 {
3401         int nr = pvr2_hdw_get_unit_number(hdw);
3402         LOCK_TAKE(hdw->big_lock); do {
3403                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3404                 hdw->log_requested = !0;
3405                 pvr2_i2c_core_check_stale(hdw);
3406                 pvr2_i2c_core_sync(hdw);
3407                 hdw->log_requested = 0;
3408                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3409                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3410                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3411                 pvr2_hdw_state_log_state(hdw);
3412                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3413         } while (0); LOCK_GIVE(hdw->big_lock);
3414 }
3415
3416
3417 /* Grab EEPROM contents, needed for direct method. */
3418 #define EEPROM_SIZE 8192
3419 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3420 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3421 {
3422         struct i2c_msg msg[2];
3423         u8 *eeprom;
3424         u8 iadd[2];
3425         u8 addr;
3426         u16 eepromSize;
3427         unsigned int offs;
3428         int ret;
3429         int mode16 = 0;
3430         unsigned pcnt,tcnt;
3431         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3432         if (!eeprom) {
3433                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3434                            "Failed to allocate memory"
3435                            " required to read eeprom");
3436                 return NULL;
3437         }
3438
3439         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3440                      hdw->eeprom_addr);
3441         addr = hdw->eeprom_addr;
3442         /* Seems that if the high bit is set, then the *real* eeprom
3443            address is shifted right now bit position (noticed this in
3444            newer PVR USB2 hardware) */
3445         if (addr & 0x80) addr >>= 1;
3446
3447         /* FX2 documentation states that a 16bit-addressed eeprom is
3448            expected if the I2C address is an odd number (yeah, this is
3449            strange but it's what they do) */
3450         mode16 = (addr & 1);
3451         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3452         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3453                      " using %d bit addressing",eepromSize,addr,
3454                      mode16 ? 16 : 8);
3455
3456         msg[0].addr = addr;
3457         msg[0].flags = 0;
3458         msg[0].len = mode16 ? 2 : 1;
3459         msg[0].buf = iadd;
3460         msg[1].addr = addr;
3461         msg[1].flags = I2C_M_RD;
3462
3463         /* We have to do the actual eeprom data fetch ourselves, because
3464            (1) we're only fetching part of the eeprom, and (2) if we were
3465            getting the whole thing our I2C driver can't grab it in one
3466            pass - which is what tveeprom is otherwise going to attempt */
3467         memset(eeprom,0,EEPROM_SIZE);
3468         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3469                 pcnt = 16;
3470                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3471                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3472                 if (mode16) {
3473                         iadd[0] = offs >> 8;
3474                         iadd[1] = offs;
3475                 } else {
3476                         iadd[0] = offs;
3477                 }
3478                 msg[1].len = pcnt;
3479                 msg[1].buf = eeprom+tcnt;
3480                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3481                                         msg,ARRAY_SIZE(msg))) != 2) {
3482                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3483                                    "eeprom fetch set offs err=%d",ret);
3484                         kfree(eeprom);
3485                         return NULL;
3486                 }
3487         }
3488         return eeprom;
3489 }
3490
3491
3492 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3493                                 int prom_flag,
3494                                 int enable_flag)
3495 {
3496         int ret;
3497         u16 address;
3498         unsigned int pipe;
3499         LOCK_TAKE(hdw->big_lock); do {
3500                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3501
3502                 if (!enable_flag) {
3503                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3504                                    "Cleaning up after CPU firmware fetch");
3505                         kfree(hdw->fw_buffer);
3506                         hdw->fw_buffer = NULL;
3507                         hdw->fw_size = 0;
3508                         if (hdw->fw_cpu_flag) {
3509                                 /* Now release the CPU.  It will disconnect
3510                                    and reconnect later. */
3511                                 pvr2_hdw_cpureset_assert(hdw,0);
3512                         }
3513                         break;
3514                 }
3515
3516                 hdw->fw_cpu_flag = (prom_flag == 0);
3517                 if (hdw->fw_cpu_flag) {
3518                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3519                                    "Preparing to suck out CPU firmware");
3520                         hdw->fw_size = 0x2000;
3521                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3522                         if (!hdw->fw_buffer) {
3523                                 hdw->fw_size = 0;
3524                                 break;
3525                         }
3526
3527                         /* We have to hold the CPU during firmware upload. */
3528                         pvr2_hdw_cpureset_assert(hdw,1);
3529
3530                         /* download the firmware from address 0000-1fff in 2048
3531                            (=0x800) bytes chunk. */
3532
3533                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3534                                    "Grabbing CPU firmware");
3535                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3536                         for(address = 0; address < hdw->fw_size;
3537                             address += 0x800) {
3538                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3539                                                       0xa0,0xc0,
3540                                                       address,0,
3541                                                       hdw->fw_buffer+address,
3542                                                       0x800,HZ);
3543                                 if (ret < 0) break;
3544                         }
3545
3546                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3547                                    "Done grabbing CPU firmware");
3548                 } else {
3549                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3550                                    "Sucking down EEPROM contents");
3551                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3552                         if (!hdw->fw_buffer) {
3553                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3554                                            "EEPROM content suck failed.");
3555                                 break;
3556                         }
3557                         hdw->fw_size = EEPROM_SIZE;
3558                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3559                                    "Done sucking down EEPROM contents");
3560                 }
3561
3562         } while (0); LOCK_GIVE(hdw->big_lock);
3563 }
3564
3565
3566 /* Return true if we're in a mode for retrieval CPU firmware */
3567 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3568 {
3569         return hdw->fw_buffer != NULL;
3570 }
3571
3572
3573 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3574                        char *buf,unsigned int cnt)
3575 {
3576         int ret = -EINVAL;
3577         LOCK_TAKE(hdw->big_lock); do {
3578                 if (!buf) break;
3579                 if (!cnt) break;
3580
3581                 if (!hdw->fw_buffer) {
3582                         ret = -EIO;
3583                         break;
3584                 }
3585
3586                 if (offs >= hdw->fw_size) {
3587                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3588                                    "Read firmware data offs=%d EOF",
3589                                    offs);
3590                         ret = 0;
3591                         break;
3592                 }
3593
3594                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3595
3596                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3597
3598                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3599                            "Read firmware data offs=%d cnt=%d",
3600                            offs,cnt);
3601                 ret = cnt;
3602         } while (0); LOCK_GIVE(hdw->big_lock);
3603
3604         return ret;
3605 }
3606
3607
3608 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3609                                   enum pvr2_v4l_type index)
3610 {
3611         switch (index) {
3612         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3613         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3614         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3615         default: return -1;
3616         }
3617 }
3618
3619
3620 /* Store a v4l minor device number */
3621 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3622                                      enum pvr2_v4l_type index,int v)
3623 {
3624         switch (index) {
3625         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3626         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3627         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3628         default: break;
3629         }
3630 }
3631
3632
3633 static void pvr2_ctl_write_complete(struct urb *urb)
3634 {
3635         struct pvr2_hdw *hdw = urb->context;
3636         hdw->ctl_write_pend_flag = 0;
3637         if (hdw->ctl_read_pend_flag) return;
3638         complete(&hdw->ctl_done);
3639 }
3640
3641
3642 static void pvr2_ctl_read_complete(struct urb *urb)
3643 {
3644         struct pvr2_hdw *hdw = urb->context;
3645         hdw->ctl_read_pend_flag = 0;
3646         if (hdw->ctl_write_pend_flag) return;
3647         complete(&hdw->ctl_done);
3648 }
3649
3650
3651 static void pvr2_ctl_timeout(unsigned long data)
3652 {
3653         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3654         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3655                 hdw->ctl_timeout_flag = !0;
3656                 if (hdw->ctl_write_pend_flag)
3657                         usb_unlink_urb(hdw->ctl_write_urb);
3658                 if (hdw->ctl_read_pend_flag)
3659                         usb_unlink_urb(hdw->ctl_read_urb);
3660         }
3661 }
3662
3663
3664 /* Issue a command and get a response from the device.  This extended
3665    version includes a probe flag (which if set means that device errors
3666    should not be logged or treated as fatal) and a timeout in jiffies.
3667    This can be used to non-lethally probe the health of endpoint 1. */
3668 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3669                                 unsigned int timeout,int probe_fl,
3670                                 void *write_data,unsigned int write_len,
3671                                 void *read_data,unsigned int read_len)
3672 {
3673         unsigned int idx;
3674         int status = 0;
3675         struct timer_list timer;
3676         if (!hdw->ctl_lock_held) {
3677                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3678                            "Attempted to execute control transfer"
3679                            " without lock!!");
3680                 return -EDEADLK;
3681         }
3682         if (!hdw->flag_ok && !probe_fl) {
3683                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3684                            "Attempted to execute control transfer"
3685                            " when device not ok");
3686                 return -EIO;
3687         }
3688         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3689                 if (!probe_fl) {
3690                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3691                                    "Attempted to execute control transfer"
3692                                    " when USB is disconnected");
3693                 }
3694                 return -ENOTTY;
3695         }
3696
3697         /* Ensure that we have sane parameters */
3698         if (!write_data) write_len = 0;
3699         if (!read_data) read_len = 0;
3700         if (write_len > PVR2_CTL_BUFFSIZE) {
3701                 pvr2_trace(
3702                         PVR2_TRACE_ERROR_LEGS,
3703                         "Attempted to execute %d byte"
3704                         " control-write transfer (limit=%d)",
3705                         write_len,PVR2_CTL_BUFFSIZE);
3706                 return -EINVAL;
3707         }
3708         if (read_len > PVR2_CTL_BUFFSIZE) {
3709                 pvr2_trace(
3710                         PVR2_TRACE_ERROR_LEGS,
3711                         "Attempted to execute %d byte"
3712                         " control-read transfer (limit=%d)",
3713                         write_len,PVR2_CTL_BUFFSIZE);
3714                 return -EINVAL;
3715         }
3716         if ((!write_len) && (!read_len)) {
3717                 pvr2_trace(
3718                         PVR2_TRACE_ERROR_LEGS,
3719                         "Attempted to execute null control transfer?");
3720                 return -EINVAL;
3721         }
3722
3723
3724         hdw->cmd_debug_state = 1;
3725         if (write_len) {
3726                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3727         } else {
3728                 hdw->cmd_debug_code = 0;
3729         }
3730         hdw->cmd_debug_write_len = write_len;
3731         hdw->cmd_debug_read_len = read_len;
3732
3733         /* Initialize common stuff */
3734         init_completion(&hdw->ctl_done);
3735         hdw->ctl_timeout_flag = 0;
3736         hdw->ctl_write_pend_flag = 0;
3737         hdw->ctl_read_pend_flag = 0;
3738         init_timer(&timer);
3739         timer.expires = jiffies + timeout;
3740         timer.data = (unsigned long)hdw;
3741         timer.function = pvr2_ctl_timeout;
3742
3743         if (write_len) {
3744                 hdw->cmd_debug_state = 2;
3745                 /* Transfer write data to internal buffer */
3746                 for (idx = 0; idx < write_len; idx++) {
3747                         hdw->ctl_write_buffer[idx] =
3748                                 ((unsigned char *)write_data)[idx];
3749                 }
3750                 /* Initiate a write request */
3751                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3752                                   hdw->usb_dev,
3753                                   usb_sndbulkpipe(hdw->usb_dev,
3754                                                   PVR2_CTL_WRITE_ENDPOINT),
3755                                   hdw->ctl_write_buffer,
3756                                   write_len,
3757                                   pvr2_ctl_write_complete,
3758                                   hdw);
3759                 hdw->ctl_write_urb->actual_length = 0;
3760                 hdw->ctl_write_pend_flag = !0;
3761                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3762                 if (status < 0) {
3763                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3764                                    "Failed to submit write-control"
3765                                    " URB status=%d",status);
3766                         hdw->ctl_write_pend_flag = 0;
3767                         goto done;
3768                 }
3769         }
3770
3771         if (read_len) {
3772                 hdw->cmd_debug_state = 3;
3773                 memset(hdw->ctl_read_buffer,0x43,read_len);
3774                 /* Initiate a read request */
3775                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3776                                   hdw->usb_dev,
3777                                   usb_rcvbulkpipe(hdw->usb_dev,
3778                                                   PVR2_CTL_READ_ENDPOINT),
3779                                   hdw->ctl_read_buffer,
3780                                   read_len,
3781                                   pvr2_ctl_read_complete,
3782                                   hdw);
3783                 hdw->ctl_read_urb->actual_length = 0;
3784                 hdw->ctl_read_pend_flag = !0;
3785                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3786                 if (status < 0) {
3787                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3788                                    "Failed to submit read-control"
3789                                    " URB status=%d",status);
3790                         hdw->ctl_read_pend_flag = 0;
3791                         goto done;
3792                 }
3793         }
3794
3795         /* Start timer */
3796         add_timer(&timer);
3797
3798         /* Now wait for all I/O to complete */
3799         hdw->cmd_debug_state = 4;
3800         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3801                 wait_for_completion(&hdw->ctl_done);
3802         }
3803         hdw->cmd_debug_state = 5;
3804
3805         /* Stop timer */
3806         del_timer_sync(&timer);
3807
3808         hdw->cmd_debug_state = 6;
3809         status = 0;
3810
3811         if (hdw->ctl_timeout_flag) {
3812                 status = -ETIMEDOUT;
3813                 if (!probe_fl) {
3814                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3815                                    "Timed out control-write");
3816                 }
3817                 goto done;
3818         }
3819
3820         if (write_len) {
3821                 /* Validate results of write request */
3822                 if ((hdw->ctl_write_urb->status != 0) &&
3823                     (hdw->ctl_write_urb->status != -ENOENT) &&
3824                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3825                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3826                         /* USB subsystem is reporting some kind of failure
3827                            on the write */
3828                         status = hdw->ctl_write_urb->status;
3829                         if (!probe_fl) {
3830                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3831                                            "control-write URB failure,"
3832                                            " status=%d",
3833                                            status);
3834                         }
3835                         goto done;
3836                 }
3837                 if (hdw->ctl_write_urb->actual_length < write_len) {
3838                         /* Failed to write enough data */
3839                         status = -EIO;
3840                         if (!probe_fl) {
3841                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3842                                            "control-write URB short,"
3843                                            " expected=%d got=%d",
3844                                            write_len,
3845                                            hdw->ctl_write_urb->actual_length);
3846                         }
3847                         goto done;
3848                 }
3849         }
3850         if (read_len) {
3851                 /* Validate results of read request */
3852                 if ((hdw->ctl_read_urb->status != 0) &&
3853                     (hdw->ctl_read_urb->status != -ENOENT) &&
3854                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3855                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3856                         /* USB subsystem is reporting some kind of failure
3857                            on the read */
3858                         status = hdw->ctl_read_urb->status;
3859                         if (!probe_fl) {
3860                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3861                                            "control-read URB failure,"
3862                                            " status=%d",
3863                                            status);
3864                         }
3865                         goto done;
3866                 }
3867                 if (hdw->ctl_read_urb->actual_length < read_len) {
3868                         /* Failed to read enough data */
3869                         status = -EIO;
3870                         if (!probe_fl) {
3871                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3872                                            "control-read URB short,"
3873                                            " expected=%d got=%d",
3874                                            read_len,
3875                                            hdw->ctl_read_urb->actual_length);
3876                         }
3877                         goto done;
3878                 }
3879                 /* Transfer retrieved data out from internal buffer */
3880                 for (idx = 0; idx < read_len; idx++) {
3881                         ((unsigned char *)read_data)[idx] =
3882                                 hdw->ctl_read_buffer[idx];
3883                 }
3884         }
3885
3886  done:
3887
3888         hdw->cmd_debug_state = 0;
3889         if ((status < 0) && (!probe_fl)) {
3890                 pvr2_hdw_render_useless(hdw);
3891         }
3892         return status;
3893 }
3894
3895
3896 int pvr2_send_request(struct pvr2_hdw *hdw,
3897                       void *write_data,unsigned int write_len,
3898                       void *read_data,unsigned int read_len)
3899 {
3900         return pvr2_send_request_ex(hdw,HZ*4,0,
3901                                     write_data,write_len,
3902                                     read_data,read_len);
3903 }
3904
3905
3906 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3907 {
3908         int ret;
3909         unsigned int cnt = 1;
3910         unsigned int args = 0;
3911         LOCK_TAKE(hdw->ctl_lock);
3912         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3913         args = (cmdcode >> 8) & 0xffu;
3914         args = (args > 2) ? 2 : args;
3915         if (args) {
3916                 cnt += args;
3917                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3918                 if (args > 1) {
3919                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3920                 }
3921         }
3922         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3923                 unsigned int idx;
3924                 unsigned int ccnt,bcnt;
3925                 char tbuf[50];
3926                 cmdcode &= 0xffu;
3927                 bcnt = 0;
3928                 ccnt = scnprintf(tbuf+bcnt,
3929                                  sizeof(tbuf)-bcnt,
3930                                  "Sending FX2 command 0x%x",cmdcode);
3931                 bcnt += ccnt;
3932                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3933                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3934                                 ccnt = scnprintf(tbuf+bcnt,
3935                                                  sizeof(tbuf)-bcnt,
3936                                                  " \"%s\"",
3937                                                  pvr2_fx2cmd_desc[idx].desc);
3938                                 bcnt += ccnt;
3939                                 break;
3940                         }
3941                 }
3942                 if (args) {
3943                         ccnt = scnprintf(tbuf+bcnt,
3944                                          sizeof(tbuf)-bcnt,
3945                                          " (%u",hdw->cmd_buffer[1]);
3946                         bcnt += ccnt;
3947                         if (args > 1) {
3948                                 ccnt = scnprintf(tbuf+bcnt,
3949                                                  sizeof(tbuf)-bcnt,
3950                                                  ",%u",hdw->cmd_buffer[2]);
3951                                 bcnt += ccnt;
3952                         }
3953                         ccnt = scnprintf(tbuf+bcnt,
3954                                          sizeof(tbuf)-bcnt,
3955                                          ")");
3956                         bcnt += ccnt;
3957                 }
3958                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3959         }
3960         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3961         LOCK_GIVE(hdw->ctl_lock);
3962         return ret;
3963 }
3964
3965
3966 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3967 {
3968         int ret;
3969
3970         LOCK_TAKE(hdw->ctl_lock);
3971
3972         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3973         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3974         hdw->cmd_buffer[5] = 0;
3975         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3976         hdw->cmd_buffer[7] = reg & 0xff;
3977
3978
3979         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3980
3981         LOCK_GIVE(hdw->ctl_lock);
3982
3983         return ret;
3984 }
3985
3986
3987 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3988 {
3989         int ret = 0;
3990
3991         LOCK_TAKE(hdw->ctl_lock);
3992
3993         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3994         hdw->cmd_buffer[1] = 0;
3995         hdw->cmd_buffer[2] = 0;
3996         hdw->cmd_buffer[3] = 0;
3997         hdw->cmd_buffer[4] = 0;
3998         hdw->cmd_buffer[5] = 0;
3999         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4000         hdw->cmd_buffer[7] = reg & 0xff;
4001
4002         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4003         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4004
4005         LOCK_GIVE(hdw->ctl_lock);
4006
4007         return ret;
4008 }
4009
4010
4011 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
4012 {
4013         if (!hdw->flag_ok) return;
4014         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4015                    "Device being rendered inoperable");
4016         if (hdw->vid_stream) {
4017                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
4018         }
4019         hdw->flag_ok = 0;
4020         trace_stbit("flag_ok",hdw->flag_ok);
4021         pvr2_hdw_state_sched(hdw);
4022 }
4023
4024
4025 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4026 {
4027         int ret;
4028         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4029         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4030         if (ret == 0) {
4031                 ret = usb_reset_device(hdw->usb_dev);
4032                 usb_unlock_device(hdw->usb_dev);
4033         } else {
4034                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4035                            "Failed to lock USB device ret=%d",ret);
4036         }
4037         if (init_pause_msec) {
4038                 pvr2_trace(PVR2_TRACE_INFO,
4039                            "Waiting %u msec for hardware to settle",
4040                            init_pause_msec);
4041                 msleep(init_pause_msec);
4042         }
4043
4044 }
4045
4046
4047 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4048 {
4049         char da[1];
4050         unsigned int pipe;
4051         int ret;
4052
4053         if (!hdw->usb_dev) return;
4054
4055         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4056
4057         da[0] = val ? 0x01 : 0x00;
4058
4059         /* Write the CPUCS register on the 8051.  The lsb of the register
4060            is the reset bit; a 1 asserts reset while a 0 clears it. */
4061         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4062         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4063         if (ret < 0) {
4064                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4065                            "cpureset_assert(%d) error=%d",val,ret);
4066                 pvr2_hdw_render_useless(hdw);
4067         }
4068 }
4069
4070
4071 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4072 {
4073         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4074 }
4075
4076
4077 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4078 {
4079         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4080 }
4081
4082
4083 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4084 {
4085         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4086 }
4087
4088
4089 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4090 {
4091         pvr2_trace(PVR2_TRACE_INIT,
4092                    "Requesting decoder reset");
4093         if (hdw->decoder_ctrl) {
4094                 if (!hdw->decoder_ctrl->force_reset) {
4095                         pvr2_trace(PVR2_TRACE_INIT,
4096                                    "Unable to reset decoder: not implemented");
4097                         return -ENOTTY;
4098                 }
4099                 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4100                 return 0;
4101         } else {
4102         }
4103         if (hdw->decoder_client_id) {
4104                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4105                                      core, reset, 0);
4106                 return 0;
4107         }
4108         pvr2_trace(PVR2_TRACE_INIT,
4109                    "Unable to reset decoder: nothing attached");
4110         return -ENOTTY;
4111 }
4112
4113
4114 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4115 {
4116         hdw->flag_ok = !0;
4117         return pvr2_issue_simple_cmd(hdw,
4118                                      FX2CMD_HCW_DEMOD_RESETIN |
4119                                      (1 << 8) |
4120                                      ((onoff ? 1 : 0) << 16));
4121 }
4122
4123
4124 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4125 {
4126         hdw->flag_ok = !0;
4127         return pvr2_issue_simple_cmd(hdw,(onoff ?
4128                                           FX2CMD_ONAIR_DTV_POWER_ON :
4129                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4130 }
4131
4132
4133 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4134                                                 int onoff)
4135 {
4136         return pvr2_issue_simple_cmd(hdw,(onoff ?
4137                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4138                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4139 }
4140
4141
4142 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4143 {
4144         int cmode;
4145         /* Compare digital/analog desired setting with current setting.  If
4146            they don't match, fix it... */
4147         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4148         if (cmode == hdw->pathway_state) {
4149                 /* They match; nothing to do */
4150                 return;
4151         }
4152
4153         switch (hdw->hdw_desc->digital_control_scheme) {
4154         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4155                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4156                 if (cmode == PVR2_PATHWAY_ANALOG) {
4157                         /* If moving to analog mode, also force the decoder
4158                            to reset.  If no decoder is attached, then it's
4159                            ok to ignore this because if/when the decoder
4160                            attaches, it will reset itself at that time. */
4161                         pvr2_hdw_cmd_decoder_reset(hdw);
4162                 }
4163                 break;
4164         case PVR2_DIGITAL_SCHEME_ONAIR:
4165                 /* Supposedly we should always have the power on whether in
4166                    digital or analog mode.  But for now do what appears to
4167                    work... */
4168                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4169                 break;
4170         default: break;
4171         }
4172
4173         pvr2_hdw_untrip_unlocked(hdw);
4174         hdw->pathway_state = cmode;
4175 }
4176
4177
4178 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4179 {
4180         /* change some GPIO data
4181          *
4182          * note: bit d7 of dir appears to control the LED,
4183          * so we shut it off here.
4184          *
4185          */
4186         if (onoff) {
4187                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4188         } else {
4189                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4190         }
4191         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4192 }
4193
4194
4195 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4196
4197 static led_method_func led_methods[] = {
4198         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4199 };
4200
4201
4202 /* Toggle LED */
4203 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4204 {
4205         unsigned int scheme_id;
4206         led_method_func fp;
4207
4208         if ((!onoff) == (!hdw->led_on)) return;
4209
4210         hdw->led_on = onoff != 0;
4211
4212         scheme_id = hdw->hdw_desc->led_scheme;
4213         if (scheme_id < ARRAY_SIZE(led_methods)) {
4214                 fp = led_methods[scheme_id];
4215         } else {
4216                 fp = NULL;
4217         }
4218
4219         if (fp) (*fp)(hdw,onoff);
4220 }
4221
4222
4223 /* Stop / start video stream transport */
4224 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4225 {
4226         int ret;
4227
4228         /* If we're in analog mode, then just issue the usual analog
4229            command. */
4230         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4231                 return pvr2_issue_simple_cmd(hdw,
4232                                              (runFl ?
4233                                               FX2CMD_STREAMING_ON :
4234                                               FX2CMD_STREAMING_OFF));
4235                 /*Note: Not reached */
4236         }
4237
4238         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4239                 /* Whoops, we don't know what mode we're in... */
4240                 return -EINVAL;
4241         }
4242
4243         /* To get here we have to be in digital mode.  The mechanism here
4244            is unfortunately different for different vendors.  So we switch
4245            on the device's digital scheme attribute in order to figure out
4246            what to do. */
4247         switch (hdw->hdw_desc->digital_control_scheme) {
4248         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4249                 return pvr2_issue_simple_cmd(hdw,
4250                                              (runFl ?
4251                                               FX2CMD_HCW_DTV_STREAMING_ON :
4252                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4253         case PVR2_DIGITAL_SCHEME_ONAIR:
4254                 ret = pvr2_issue_simple_cmd(hdw,
4255                                             (runFl ?
4256                                              FX2CMD_STREAMING_ON :
4257                                              FX2CMD_STREAMING_OFF));
4258                 if (ret) return ret;
4259                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4260         default:
4261                 return -EINVAL;
4262         }
4263 }
4264
4265
4266 /* Evaluate whether or not state_pathway_ok can change */
4267 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4268 {
4269         if (hdw->state_pathway_ok) {
4270                 /* Nothing to do if pathway is already ok */
4271                 return 0;
4272         }
4273         if (!hdw->state_pipeline_idle) {
4274                 /* Not allowed to change anything if pipeline is not idle */
4275                 return 0;
4276         }
4277         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4278         hdw->state_pathway_ok = !0;
4279         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4280         return !0;
4281 }
4282
4283
4284 /* Evaluate whether or not state_encoder_ok can change */
4285 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4286 {
4287         if (hdw->state_encoder_ok) return 0;
4288         if (hdw->flag_tripped) return 0;
4289         if (hdw->state_encoder_run) return 0;
4290         if (hdw->state_encoder_config) return 0;
4291         if (hdw->state_decoder_run) return 0;
4292         if (hdw->state_usbstream_run) return 0;
4293         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4294                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4295         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4296                 return 0;
4297         }
4298
4299         if (pvr2_upload_firmware2(hdw) < 0) {
4300                 hdw->flag_tripped = !0;
4301                 trace_stbit("flag_tripped",hdw->flag_tripped);
4302                 return !0;
4303         }
4304         hdw->state_encoder_ok = !0;
4305         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4306         return !0;
4307 }
4308
4309
4310 /* Evaluate whether or not state_encoder_config can change */
4311 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4312 {
4313         if (hdw->state_encoder_config) {
4314                 if (hdw->state_encoder_ok) {
4315                         if (hdw->state_pipeline_req &&
4316                             !hdw->state_pipeline_pause) return 0;
4317                 }
4318                 hdw->state_encoder_config = 0;
4319                 hdw->state_encoder_waitok = 0;
4320                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4321                 /* paranoia - solve race if timer just completed */
4322                 del_timer_sync(&hdw->encoder_wait_timer);
4323         } else {
4324                 if (!hdw->state_pathway_ok ||
4325                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4326                     !hdw->state_encoder_ok ||
4327                     !hdw->state_pipeline_idle ||
4328                     hdw->state_pipeline_pause ||
4329                     !hdw->state_pipeline_req ||
4330                     !hdw->state_pipeline_config) {
4331                         /* We must reset the enforced wait interval if
4332                            anything has happened that might have disturbed
4333                            the encoder.  This should be a rare case. */
4334                         if (timer_pending(&hdw->encoder_wait_timer)) {
4335                                 del_timer_sync(&hdw->encoder_wait_timer);
4336                         }
4337                         if (hdw->state_encoder_waitok) {
4338                                 /* Must clear the state - therefore we did
4339                                    something to a state bit and must also
4340                                    return true. */
4341                                 hdw->state_encoder_waitok = 0;
4342                                 trace_stbit("state_encoder_waitok",
4343                                             hdw->state_encoder_waitok);
4344                                 return !0;
4345                         }
4346                         return 0;
4347                 }
4348                 if (!hdw->state_encoder_waitok) {
4349                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4350                                 /* waitok flag wasn't set and timer isn't
4351                                    running.  Check flag once more to avoid
4352                                    a race then start the timer.  This is
4353                                    the point when we measure out a minimal
4354                                    quiet interval before doing something to
4355                                    the encoder. */
4356                                 if (!hdw->state_encoder_waitok) {
4357                                         hdw->encoder_wait_timer.expires =
4358                                                 jiffies +
4359                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4360                                                  / 1000);
4361                                         add_timer(&hdw->encoder_wait_timer);
4362                                 }
4363                         }
4364                         /* We can't continue until we know we have been
4365                            quiet for the interval measured by this
4366                            timer. */
4367                         return 0;
4368                 }
4369                 pvr2_encoder_configure(hdw);
4370                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4371         }
4372         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4373         return !0;
4374 }
4375
4376
4377 /* Return true if the encoder should not be running. */
4378 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4379 {
4380         if (!hdw->state_encoder_ok) {
4381                 /* Encoder isn't healthy at the moment, so stop it. */
4382                 return !0;
4383         }
4384         if (!hdw->state_pathway_ok) {
4385                 /* Mode is not understood at the moment (i.e. it wants to
4386                    change), so encoder must be stopped. */
4387                 return !0;
4388         }
4389
4390         switch (hdw->pathway_state) {
4391         case PVR2_PATHWAY_ANALOG:
4392                 if (!hdw->state_decoder_run) {
4393                         /* We're in analog mode and the decoder is not
4394                            running; thus the encoder should be stopped as
4395                            well. */
4396                         return !0;
4397                 }
4398                 break;
4399         case PVR2_PATHWAY_DIGITAL:
4400                 if (hdw->state_encoder_runok) {
4401                         /* This is a funny case.  We're in digital mode so
4402                            really the encoder should be stopped.  However
4403                            if it really is running, only kill it after
4404                            runok has been set.  This gives a chance for the
4405                            onair quirk to function (encoder must run
4406                            briefly first, at least once, before onair
4407                            digital streaming can work). */
4408                         return !0;
4409                 }
4410                 break;
4411         default:
4412                 /* Unknown mode; so encoder should be stopped. */
4413                 return !0;
4414         }
4415
4416         /* If we get here, we haven't found a reason to stop the
4417            encoder. */
4418         return 0;
4419 }
4420
4421
4422 /* Return true if the encoder should be running. */
4423 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4424 {
4425         if (!hdw->state_encoder_ok) {
4426                 /* Don't run the encoder if it isn't healthy... */
4427                 return 0;
4428         }
4429         if (!hdw->state_pathway_ok) {
4430                 /* Don't run the encoder if we don't (yet) know what mode
4431                    we need to be in... */
4432                 return 0;
4433         }
4434
4435         switch (hdw->pathway_state) {
4436         case PVR2_PATHWAY_ANALOG:
4437                 if (hdw->state_decoder_run) {
4438                         /* In analog mode, if the decoder is running, then
4439                            run the encoder. */
4440                         return !0;
4441                 }
4442                 break;
4443         case PVR2_PATHWAY_DIGITAL:
4444                 if ((hdw->hdw_desc->digital_control_scheme ==
4445                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4446                     !hdw->state_encoder_runok) {
4447                         /* This is a quirk.  OnAir hardware won't stream
4448                            digital until the encoder has been run at least
4449                            once, for a minimal period of time (empiricially
4450                            measured to be 1/4 second).  So if we're on
4451                            OnAir hardware and the encoder has never been
4452                            run at all, then start the encoder.  Normal
4453                            state machine logic in the driver will
4454                            automatically handle the remaining bits. */
4455                         return !0;
4456                 }
4457                 break;
4458         default:
4459                 /* For completeness (unknown mode; encoder won't run ever) */
4460                 break;
4461         }
4462         /* If we get here, then we haven't found any reason to run the
4463            encoder, so don't run it. */
4464         return 0;
4465 }
4466
4467
4468 /* Evaluate whether or not state_encoder_run can change */
4469 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4470 {
4471         if (hdw->state_encoder_run) {
4472                 if (!state_check_disable_encoder_run(hdw)) return 0;
4473                 if (hdw->state_encoder_ok) {
4474                         del_timer_sync(&hdw->encoder_run_timer);
4475                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4476                 }
4477                 hdw->state_encoder_run = 0;
4478         } else {
4479                 if (!state_check_enable_encoder_run(hdw)) return 0;
4480                 if (pvr2_encoder_start(hdw) < 0) return !0;
4481                 hdw->state_encoder_run = !0;
4482                 if (!hdw->state_encoder_runok) {
4483                         hdw->encoder_run_timer.expires =
4484                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4485                         add_timer(&hdw->encoder_run_timer);
4486                 }
4487         }
4488         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4489         return !0;
4490 }
4491
4492
4493 /* Timeout function for quiescent timer. */
4494 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4495 {
4496         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4497         hdw->state_decoder_quiescent = !0;
4498         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4499         hdw->state_stale = !0;
4500         queue_work(hdw->workqueue,&hdw->workpoll);
4501 }
4502
4503
4504 /* Timeout function for encoder wait timer. */
4505 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4506 {
4507         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4508         hdw->state_encoder_waitok = !0;
4509         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4510         hdw->state_stale = !0;
4511         queue_work(hdw->workqueue,&hdw->workpoll);
4512 }
4513
4514
4515 /* Timeout function for encoder run timer. */
4516 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4517 {
4518         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4519         if (!hdw->state_encoder_runok) {
4520                 hdw->state_encoder_runok = !0;
4521                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4522                 hdw->state_stale = !0;
4523                 queue_work(hdw->workqueue,&hdw->workpoll);
4524         }
4525 }
4526
4527
4528 /* Evaluate whether or not state_decoder_run can change */
4529 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4530 {
4531         if (hdw->state_decoder_run) {
4532                 if (hdw->state_encoder_ok) {
4533                         if (hdw->state_pipeline_req &&
4534                             !hdw->state_pipeline_pause &&
4535                             hdw->state_pathway_ok) return 0;
4536                 }
4537                 if (!hdw->flag_decoder_missed) {
4538                         pvr2_decoder_enable(hdw,0);
4539                 }
4540                 hdw->state_decoder_quiescent = 0;
4541                 hdw->state_decoder_run = 0;
4542                 /* paranoia - solve race if timer just completed */
4543                 del_timer_sync(&hdw->quiescent_timer);
4544         } else {
4545                 if (!hdw->state_decoder_quiescent) {
4546                         if (!timer_pending(&hdw->quiescent_timer)) {
4547                                 /* We don't do something about the
4548                                    quiescent timer until right here because
4549                                    we also want to catch cases where the
4550                                    decoder was already not running (like
4551                                    after initialization) as opposed to
4552                                    knowing that we had just stopped it.
4553                                    The second flag check is here to cover a
4554                                    race - the timer could have run and set
4555                                    this flag just after the previous check
4556                                    but before we did the pending check. */
4557                                 if (!hdw->state_decoder_quiescent) {
4558                                         hdw->quiescent_timer.expires =
4559                                                 jiffies +
4560                                                 (HZ * TIME_MSEC_DECODER_WAIT
4561                                                  / 1000);
4562                                         add_timer(&hdw->quiescent_timer);
4563                                 }
4564                         }
4565                         /* Don't allow decoder to start again until it has
4566                            been quiesced first.  This little detail should
4567                            hopefully further stabilize the encoder. */
4568                         return 0;
4569                 }
4570                 if (!hdw->state_pathway_ok ||
4571                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4572                     !hdw->state_pipeline_req ||
4573                     hdw->state_pipeline_pause ||
4574                     !hdw->state_pipeline_config ||
4575                     !hdw->state_encoder_config ||
4576                     !hdw->state_encoder_ok) return 0;
4577                 del_timer_sync(&hdw->quiescent_timer);
4578                 if (hdw->flag_decoder_missed) return 0;
4579                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4580                 hdw->state_decoder_quiescent = 0;
4581                 hdw->state_decoder_run = !0;
4582         }
4583         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4584         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4585         return !0;
4586 }
4587
4588
4589 /* Evaluate whether or not state_usbstream_run can change */
4590 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4591 {
4592         if (hdw->state_usbstream_run) {
4593                 int fl = !0;
4594                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4595                         fl = (hdw->state_encoder_ok &&
4596                               hdw->state_encoder_run);
4597                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4598                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4599                         fl = hdw->state_encoder_ok;
4600                 }
4601                 if (fl &&
4602                     hdw->state_pipeline_req &&
4603                     !hdw->state_pipeline_pause &&
4604                     hdw->state_pathway_ok) {
4605                         return 0;
4606                 }
4607                 pvr2_hdw_cmd_usbstream(hdw,0);
4608                 hdw->state_usbstream_run = 0;
4609         } else {
4610                 if (!hdw->state_pipeline_req ||
4611                     hdw->state_pipeline_pause ||
4612                     !hdw->state_pathway_ok) return 0;
4613                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4614                         if (!hdw->state_encoder_ok ||
4615                             !hdw->state_encoder_run) return 0;
4616                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4617                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4618                         if (!hdw->state_encoder_ok) return 0;
4619                         if (hdw->state_encoder_run) return 0;
4620                         if (hdw->hdw_desc->digital_control_scheme ==
4621                             PVR2_DIGITAL_SCHEME_ONAIR) {
4622                                 /* OnAir digital receivers won't stream
4623                                    unless the analog encoder has run first.
4624                                    Why?  I have no idea.  But don't even
4625                                    try until we know the analog side is
4626                                    known to have run. */
4627                                 if (!hdw->state_encoder_runok) return 0;
4628                         }
4629                 }
4630                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4631                 hdw->state_usbstream_run = !0;
4632         }
4633         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4634         return !0;
4635 }
4636
4637
4638 /* Attempt to configure pipeline, if needed */
4639 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4640 {
4641         if (hdw->state_pipeline_config ||
4642             hdw->state_pipeline_pause) return 0;
4643         pvr2_hdw_commit_execute(hdw);
4644         return !0;
4645 }
4646
4647
4648 /* Update pipeline idle and pipeline pause tracking states based on other
4649    inputs.  This must be called whenever the other relevant inputs have
4650    changed. */
4651 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4652 {
4653         unsigned int st;
4654         int updatedFl = 0;
4655         /* Update pipeline state */
4656         st = !(hdw->state_encoder_run ||
4657                hdw->state_decoder_run ||
4658                hdw->state_usbstream_run ||
4659                (!hdw->state_decoder_quiescent));
4660         if (!st != !hdw->state_pipeline_idle) {
4661                 hdw->state_pipeline_idle = st;
4662                 updatedFl = !0;
4663         }
4664         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4665                 hdw->state_pipeline_pause = 0;
4666                 updatedFl = !0;
4667         }
4668         return updatedFl;
4669 }
4670
4671
4672 typedef int (*state_eval_func)(struct pvr2_hdw *);
4673
4674 /* Set of functions to be run to evaluate various states in the driver. */
4675 static const state_eval_func eval_funcs[] = {
4676         state_eval_pathway_ok,
4677         state_eval_pipeline_config,
4678         state_eval_encoder_ok,
4679         state_eval_encoder_config,
4680         state_eval_decoder_run,
4681         state_eval_encoder_run,
4682         state_eval_usbstream_run,
4683 };
4684
4685
4686 /* Process various states and return true if we did anything interesting. */
4687 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4688 {
4689         unsigned int i;
4690         int state_updated = 0;
4691         int check_flag;
4692
4693         if (!hdw->state_stale) return 0;
4694         if ((hdw->fw1_state != FW1_STATE_OK) ||
4695             !hdw->flag_ok) {
4696                 hdw->state_stale = 0;
4697                 return !0;
4698         }
4699         /* This loop is the heart of the entire driver.  It keeps trying to
4700            evaluate various bits of driver state until nothing changes for
4701            one full iteration.  Each "bit of state" tracks some global
4702            aspect of the driver, e.g. whether decoder should run, if
4703            pipeline is configured, usb streaming is on, etc.  We separately
4704            evaluate each of those questions based on other driver state to
4705            arrive at the correct running configuration. */
4706         do {
4707                 check_flag = 0;
4708                 state_update_pipeline_state(hdw);
4709                 /* Iterate over each bit of state */
4710                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4711                         if ((*eval_funcs[i])(hdw)) {
4712                                 check_flag = !0;
4713                                 state_updated = !0;
4714                                 state_update_pipeline_state(hdw);
4715                         }
4716                 }
4717         } while (check_flag && hdw->flag_ok);
4718         hdw->state_stale = 0;
4719         trace_stbit("state_stale",hdw->state_stale);
4720         return state_updated;
4721 }
4722
4723
4724 static unsigned int print_input_mask(unsigned int msk,
4725                                      char *buf,unsigned int acnt)
4726 {
4727         unsigned int idx,ccnt;
4728         unsigned int tcnt = 0;
4729         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4730                 if (!((1 << idx) & msk)) continue;
4731                 ccnt = scnprintf(buf+tcnt,
4732                                  acnt-tcnt,
4733                                  "%s%s",
4734                                  (tcnt ? ", " : ""),
4735                                  control_values_input[idx]);
4736                 tcnt += ccnt;
4737         }
4738         return tcnt;
4739 }
4740
4741
4742 static const char *pvr2_pathway_state_name(int id)
4743 {
4744         switch (id) {
4745         case PVR2_PATHWAY_ANALOG: return "analog";
4746         case PVR2_PATHWAY_DIGITAL: return "digital";
4747         default: return "unknown";
4748         }
4749 }
4750
4751
4752 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4753                                              char *buf,unsigned int acnt)
4754 {
4755         switch (which) {
4756         case 0:
4757                 return scnprintf(
4758                         buf,acnt,
4759                         "driver:%s%s%s%s%s <mode=%s>",
4760                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4761                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4762                         (hdw->flag_disconnected ? " <disconnected>" :
4763                          " <connected>"),
4764                         (hdw->flag_tripped ? " <tripped>" : ""),
4765                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4766                         pvr2_pathway_state_name(hdw->pathway_state));
4767
4768         case 1:
4769                 return scnprintf(
4770                         buf,acnt,
4771                         "pipeline:%s%s%s%s",
4772                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4773                         (hdw->state_pipeline_config ?
4774                          " <configok>" : " <stale>"),
4775                         (hdw->state_pipeline_req ? " <req>" : ""),
4776                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4777         case 2:
4778                 return scnprintf(
4779                         buf,acnt,
4780                         "worker:%s%s%s%s%s%s%s",
4781                         (hdw->state_decoder_run ?
4782                          " <decode:run>" :
4783                          (hdw->state_decoder_quiescent ?
4784                           "" : " <decode:stop>")),
4785                         (hdw->state_decoder_quiescent ?
4786                          " <decode:quiescent>" : ""),
4787                         (hdw->state_encoder_ok ?
4788                          "" : " <encode:init>"),
4789                         (hdw->state_encoder_run ?
4790                          (hdw->state_encoder_runok ?
4791                           " <encode:run>" :
4792                           " <encode:firstrun>") :
4793                          (hdw->state_encoder_runok ?
4794                           " <encode:stop>" :
4795                           " <encode:virgin>")),
4796                         (hdw->state_encoder_config ?
4797                          " <encode:configok>" :
4798                          (hdw->state_encoder_waitok ?
4799                           "" : " <encode:waitok>")),
4800                         (hdw->state_usbstream_run ?
4801                          " <usb:run>" : " <usb:stop>"),
4802                         (hdw->state_pathway_ok ?
4803                          " <pathway:ok>" : ""));
4804         case 3:
4805                 return scnprintf(
4806                         buf,acnt,
4807                         "state: %s",
4808                         pvr2_get_state_name(hdw->master_state));
4809         case 4: {
4810                 unsigned int tcnt = 0;
4811                 unsigned int ccnt;
4812
4813                 ccnt = scnprintf(buf,
4814                                  acnt,
4815                                  "Hardware supported inputs: ");
4816                 tcnt += ccnt;
4817                 tcnt += print_input_mask(hdw->input_avail_mask,
4818                                          buf+tcnt,
4819                                          acnt-tcnt);
4820                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4821                         ccnt = scnprintf(buf+tcnt,
4822                                          acnt-tcnt,
4823                                          "; allowed inputs: ");
4824                         tcnt += ccnt;
4825                         tcnt += print_input_mask(hdw->input_allowed_mask,
4826                                                  buf+tcnt,
4827                                                  acnt-tcnt);
4828                 }
4829                 return tcnt;
4830         }
4831         case 5: {
4832                 struct pvr2_stream_stats stats;
4833                 if (!hdw->vid_stream) break;
4834                 pvr2_stream_get_stats(hdw->vid_stream,
4835                                       &stats,
4836                                       0);
4837                 return scnprintf(
4838                         buf,acnt,
4839                         "Bytes streamed=%u"
4840                         " URBs: queued=%u idle=%u ready=%u"
4841                         " processed=%u failed=%u",
4842                         stats.bytes_processed,
4843                         stats.buffers_in_queue,
4844                         stats.buffers_in_idle,
4845                         stats.buffers_in_ready,
4846                         stats.buffers_processed,
4847                         stats.buffers_failed);
4848         }
4849         case 6: {
4850                 struct v4l2_subdev *sd;
4851                 unsigned int tcnt = 0;
4852                 unsigned int ccnt;
4853                 const char *p;
4854                 unsigned int id;
4855                 ccnt = scnprintf(buf,
4856                                  acnt,
4857                                  "Associted v4l2_subdev drivers:");
4858                 tcnt += ccnt;
4859                 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4860                         id = sd->grp_id;
4861                         p = NULL;
4862                         if (id < ARRAY_SIZE(module_names)) {
4863                                 p = module_names[id];
4864                         }
4865                         if (!p) p = "(unknown)";
4866                         ccnt = scnprintf(buf + tcnt,
4867                                          acnt - tcnt,
4868                                          " %s (%u)", p, id);
4869                 }
4870                 return tcnt;
4871         }
4872         default: break;
4873         }
4874         return 0;
4875 }
4876
4877
4878 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4879                                    char *buf,unsigned int acnt)
4880 {
4881         unsigned int bcnt,ccnt,idx;
4882         bcnt = 0;
4883         LOCK_TAKE(hdw->big_lock);
4884         for (idx = 0; ; idx++) {
4885                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4886                 if (!ccnt) break;
4887                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4888                 if (!acnt) break;
4889                 buf[0] = '\n'; ccnt = 1;
4890                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4891         }
4892         LOCK_GIVE(hdw->big_lock);
4893         return bcnt;
4894 }
4895
4896
4897 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4898 {
4899         char buf[128];
4900         unsigned int idx,ccnt;
4901
4902         for (idx = 0; ; idx++) {
4903                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4904                 if (!ccnt) break;
4905                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4906         }
4907 }
4908
4909
4910 /* Evaluate and update the driver's current state, taking various actions
4911    as appropriate for the update. */
4912 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4913 {
4914         unsigned int st;
4915         int state_updated = 0;
4916         int callback_flag = 0;
4917         int analog_mode;
4918
4919         pvr2_trace(PVR2_TRACE_STBITS,
4920                    "Drive state check START");
4921         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4922                 pvr2_hdw_state_log_state(hdw);
4923         }
4924
4925         /* Process all state and get back over disposition */
4926         state_updated = pvr2_hdw_state_update(hdw);
4927
4928         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4929
4930         /* Update master state based upon all other states. */
4931         if (!hdw->flag_ok) {
4932                 st = PVR2_STATE_DEAD;
4933         } else if (hdw->fw1_state != FW1_STATE_OK) {
4934                 st = PVR2_STATE_COLD;
4935         } else if ((analog_mode ||
4936                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4937                    !hdw->state_encoder_ok) {
4938                 st = PVR2_STATE_WARM;
4939         } else if (hdw->flag_tripped ||
4940                    (analog_mode && hdw->flag_decoder_missed)) {
4941                 st = PVR2_STATE_ERROR;
4942         } else if (hdw->state_usbstream_run &&
4943                    (!analog_mode ||
4944                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4945                 st = PVR2_STATE_RUN;
4946         } else {
4947                 st = PVR2_STATE_READY;
4948         }
4949         if (hdw->master_state != st) {
4950                 pvr2_trace(PVR2_TRACE_STATE,
4951                            "Device state change from %s to %s",
4952                            pvr2_get_state_name(hdw->master_state),
4953                            pvr2_get_state_name(st));
4954                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4955                 hdw->master_state = st;
4956                 state_updated = !0;
4957                 callback_flag = !0;
4958         }
4959         if (state_updated) {
4960                 /* Trigger anyone waiting on any state changes here. */
4961                 wake_up(&hdw->state_wait_data);
4962         }
4963
4964         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4965                 pvr2_hdw_state_log_state(hdw);
4966         }
4967         pvr2_trace(PVR2_TRACE_STBITS,
4968                    "Drive state check DONE callback=%d",callback_flag);
4969
4970         return callback_flag;
4971 }
4972
4973
4974 /* Cause kernel thread to check / update driver state */
4975 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4976 {
4977         if (hdw->state_stale) return;
4978         hdw->state_stale = !0;
4979         trace_stbit("state_stale",hdw->state_stale);
4980         queue_work(hdw->workqueue,&hdw->workpoll);
4981 }
4982
4983
4984 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4985 {
4986         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4987 }
4988
4989
4990 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4991 {
4992         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4993 }
4994
4995
4996 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4997 {
4998         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4999 }
5000
5001
5002 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5003 {
5004         u32 cval,nval;
5005         int ret;
5006         if (~msk) {
5007                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5008                 if (ret) return ret;
5009                 nval = (cval & ~msk) | (val & msk);
5010                 pvr2_trace(PVR2_TRACE_GPIO,
5011                            "GPIO direction changing 0x%x:0x%x"
5012                            " from 0x%x to 0x%x",
5013                            msk,val,cval,nval);
5014         } else {
5015                 nval = val;
5016                 pvr2_trace(PVR2_TRACE_GPIO,
5017                            "GPIO direction changing to 0x%x",nval);
5018         }
5019         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5020 }
5021
5022
5023 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5024 {
5025         u32 cval,nval;
5026         int ret;
5027         if (~msk) {
5028                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5029                 if (ret) return ret;
5030                 nval = (cval & ~msk) | (val & msk);
5031                 pvr2_trace(PVR2_TRACE_GPIO,
5032                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5033                            msk,val,cval,nval);
5034         } else {
5035                 nval = val;
5036                 pvr2_trace(PVR2_TRACE_GPIO,
5037                            "GPIO output changing to 0x%x",nval);
5038         }
5039         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5040 }
5041
5042
5043 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5044 {
5045         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5046         memset(vtp, 0, sizeof(*vtp));
5047         hdw->tuner_signal_stale = 0;
5048         pvr2_i2c_core_status_poll(hdw);
5049         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5050            using v4l2-subdev - therefore we can't support that AT ALL right
5051            now.  (Of course, no sub-drivers seem to implement it either.
5052            But now it's a a chicken and egg problem...) */
5053         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5054                              &hdw->tuner_signal_info);
5055         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5056                    " type=%u strength=%u audio=0x%x cap=0x%x"
5057                    " low=%u hi=%u",
5058                    vtp->type,
5059                    vtp->signal, vtp->rxsubchans, vtp->capability,
5060                    vtp->rangelow, vtp->rangehigh);
5061
5062         /* We have to do this to avoid getting into constant polling if
5063            there's nobody to answer a poll of cropcap info. */
5064         hdw->cropcap_stale = 0;
5065 }
5066
5067
5068 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5069 {
5070         return hdw->input_avail_mask;
5071 }
5072
5073
5074 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5075 {
5076         return hdw->input_allowed_mask;
5077 }
5078
5079
5080 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5081 {
5082         if (hdw->input_val != v) {
5083                 hdw->input_val = v;
5084                 hdw->input_dirty = !0;
5085         }
5086
5087         /* Handle side effects - if we switch to a mode that needs the RF
5088            tuner, then select the right frequency choice as well and mark
5089            it dirty. */
5090         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5091                 hdw->freqSelector = 0;
5092                 hdw->freqDirty = !0;
5093         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5094                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5095                 hdw->freqSelector = 1;
5096                 hdw->freqDirty = !0;
5097         }
5098         return 0;
5099 }
5100
5101
5102 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5103                                unsigned int change_mask,
5104                                unsigned int change_val)
5105 {
5106         int ret = 0;
5107         unsigned int nv,m,idx;
5108         LOCK_TAKE(hdw->big_lock);
5109         do {
5110                 nv = hdw->input_allowed_mask & ~change_mask;
5111                 nv |= (change_val & change_mask);
5112                 nv &= hdw->input_avail_mask;
5113                 if (!nv) {
5114                         /* No legal modes left; return error instead. */
5115                         ret = -EPERM;
5116                         break;
5117                 }
5118                 hdw->input_allowed_mask = nv;
5119                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5120                         /* Current mode is still in the allowed mask, so
5121                            we're done. */
5122                         break;
5123                 }
5124                 /* Select and switch to a mode that is still in the allowed
5125                    mask */
5126                 if (!hdw->input_allowed_mask) {
5127                         /* Nothing legal; give up */
5128                         break;
5129                 }
5130                 m = hdw->input_allowed_mask;
5131                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5132                         if (!((1 << idx) & m)) continue;
5133                         pvr2_hdw_set_input(hdw,idx);
5134                         break;
5135                 }
5136         } while (0);
5137         LOCK_GIVE(hdw->big_lock);
5138         return ret;
5139 }
5140
5141
5142 /* Find I2C address of eeprom */
5143 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5144 {
5145         int result;
5146         LOCK_TAKE(hdw->ctl_lock); do {
5147                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5148                 result = pvr2_send_request(hdw,
5149                                            hdw->cmd_buffer,1,
5150                                            hdw->cmd_buffer,1);
5151                 if (result < 0) break;
5152                 result = hdw->cmd_buffer[0];
5153         } while(0); LOCK_GIVE(hdw->ctl_lock);
5154         return result;
5155 }
5156
5157
5158 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5159                              struct v4l2_dbg_match *match, u64 reg_id,
5160                              int setFl, u64 *val_ptr)
5161 {
5162 #ifdef CONFIG_VIDEO_ADV_DEBUG
5163         struct pvr2_i2c_client *cp;
5164         struct v4l2_dbg_register req;
5165         int stat = 0;
5166         int okFl = 0;
5167
5168         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5169
5170         req.match = *match;
5171         req.reg = reg_id;
5172         if (setFl) req.val = *val_ptr;
5173         /* It would be nice to know if a sub-device answered the request */
5174         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5175         if (!setFl) *val_ptr = req.val;
5176         if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
5177                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
5178                         if (!v4l2_chip_match_i2c_client(
5179                                     cp->client,
5180                                     &req.match)) {
5181                                 continue;
5182                         }
5183                         stat = pvr2_i2c_client_cmd(
5184                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5185                                     VIDIOC_DBG_G_REGISTER),&req);
5186                         if (!setFl) *val_ptr = req.val;
5187                         okFl = !0;
5188                         break;
5189                 }
5190         } while (0); mutex_unlock(&hdw->i2c_list_lock);
5191         if (okFl) {
5192                 return stat;
5193         }
5194         return -EINVAL;
5195 #else
5196         return -ENOSYS;
5197 #endif
5198 }
5199
5200
5201 /*
5202   Stuff for Emacs to see, in order to encourage consistent editing style:
5203   *** Local Variables: ***
5204   *** mode: c ***
5205   *** fill-column: 75 ***
5206   *** tab-width: 8 ***
5207   *** c-basic-offset: 8 ***
5208   *** End: ***
5209   */