Pileus Git - ~andy/linux/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-i2c-track.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39
  40 #define TV_MIN_FREQ     55250000L
  41 #define TV_MAX_FREQ    850000000L
  42
  43 /* This defines a minimum interval that the decoder must remain quiet
  44    before we are allowed to start it running. */
  45 #define TIME_MSEC_DECODER_WAIT 50
  46
  47 /* This defines a minimum interval that the encoder must remain quiet
  48    before we are allowed to configure it.  I had this originally set to
  49    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  50    things work better when it's set to 100msec. */
  51 #define TIME_MSEC_ENCODER_WAIT 100
  52
  53 /* This defines the minimum interval that the encoder must successfully run
  54    before we consider that the encoder has run at least once since its
  55    firmware has been loaded.  This measurement is in important for cases
  56    where we can't do something until we know that the encoder has been run
  57    at least once. */
  58 #define TIME_MSEC_ENCODER_OK 250
  59
  60 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  61 static DEFINE_MUTEX(pvr2_unit_mtx);
  62
  63 static int ctlchg;
  64 static int procreload;
  65 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  66 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  67 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  68 static int init_pause_msec;
  69
  70 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  71 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  72 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  73 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  74 module_param(procreload, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(procreload,
  76                  "Attempt init failure recovery with firmware reload");
  77 module_param_array(tuner,    int, NULL, 0444);
  78 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  79 module_param_array(video_std,    int, NULL, 0444);
  80 MODULE_PARM_DESC(video_std,"specify initial video standard");
  81 module_param_array(tolerance,    int, NULL, 0444);
  82 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  83
  84 /* US Broadcast channel 7 (175.25 MHz) */
  85 static int default_tv_freq    = 175250000L;
  86 /* 104.3 MHz, a usable FM station for my area */
  87 static int default_radio_freq = 104300000L;
  88
  89 module_param_named(tv_freq, default_tv_freq, int, 0444);
  90 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  91 module_param_named(radio_freq, default_radio_freq, int, 0444);
  92 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  93
  94 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  95 #define PVR2_CTL_READ_ENDPOINT   0x81
  96
  97 #define PVR2_GPIO_IN 0x9008
  98 #define PVR2_GPIO_OUT 0x900c
  99 #define PVR2_GPIO_DIR 0x9020
 100
 101 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 102
 103 #define PVR2_FIRMWARE_ENDPOINT   0x02
 104
 105 /* size of a firmware chunk */
 106 #define FIRMWARE_CHUNK_SIZE 0x2000
 107
 108 static const char *module_names[] = {
 109         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 110         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 111         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 112         [PVR2_CLIENT_ID_TUNER] = "tuner",
 113         [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
 114 };
 115
 116
 117 static const unsigned char *module_i2c_addresses[] = {
 118         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 119 };
 120
 121
 122 /* Define the list of additional controls we'll dynamically construct based
 123    on query of the cx2341x module. */
 124 struct pvr2_mpeg_ids {
 125         const char *strid;
 126         int id;
 127 };
 128 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 129         {
 130                 .strid = "audio_layer",
 131                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 132         },{
 133                 .strid = "audio_bitrate",
 134                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 135         },{
 136                 /* Already using audio_mode elsewhere :-( */
 137                 .strid = "mpeg_audio_mode",
 138                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 139         },{
 140                 .strid = "mpeg_audio_mode_extension",
 141                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 142         },{
 143                 .strid = "audio_emphasis",
 144                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 145         },{
 146                 .strid = "audio_crc",
 147                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 148         },{
 149                 .strid = "video_aspect",
 150                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 151         },{
 152                 .strid = "video_b_frames",
 153                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 154         },{
 155                 .strid = "video_gop_size",
 156                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 157         },{
 158                 .strid = "video_gop_closure",
 159                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 160         },{
 161                 .strid = "video_bitrate_mode",
 162                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 163         },{
 164                 .strid = "video_bitrate",
 165                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 166         },{
 167                 .strid = "video_bitrate_peak",
 168                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 169         },{
 170                 .strid = "video_temporal_decimation",
 171                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 172         },{
 173                 .strid = "stream_type",
 174                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 175         },{
 176                 .strid = "video_spatial_filter_mode",
 177                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 178         },{
 179                 .strid = "video_spatial_filter",
 180                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 181         },{
 182                 .strid = "video_luma_spatial_filter_type",
 183                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 184         },{
 185                 .strid = "video_chroma_spatial_filter_type",
 186                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 187         },{
 188                 .strid = "video_temporal_filter_mode",
 189                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 190         },{
 191                 .strid = "video_temporal_filter",
 192                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 193         },{
 194                 .strid = "video_median_filter_type",
 195                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 196         },{
 197                 .strid = "video_luma_median_filter_top",
 198                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 199         },{
 200                 .strid = "video_luma_median_filter_bottom",
 201                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 202         },{
 203                 .strid = "video_chroma_median_filter_top",
 204                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 205         },{
 206                 .strid = "video_chroma_median_filter_bottom",
 207                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 208         }
 209 };
 210 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 211
 212
 213 static const char *control_values_srate[] = {
 214         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 215         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 216         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 217 };
 218
 219
 220
 221 static const char *control_values_input[] = {
 222         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 223         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 224         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 225         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 226         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 227 };
 228
 229
 230 static const char *control_values_audiomode[] = {
 231         [V4L2_TUNER_MODE_MONO]   = "Mono",
 232         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 233         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 234         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 235         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 236 };
 237
 238
 239 static const char *control_values_hsm[] = {
 240         [PVR2_CVAL_HSM_FAIL] = "Fail",
 241         [PVR2_CVAL_HSM_HIGH] = "High",
 242         [PVR2_CVAL_HSM_FULL] = "Full",
 243 };
 244
 245
 246 static const char *pvr2_state_names[] = {
 247         [PVR2_STATE_NONE] =    "none",
 248         [PVR2_STATE_DEAD] =    "dead",
 249         [PVR2_STATE_COLD] =    "cold",
 250         [PVR2_STATE_WARM] =    "warm",
 251         [PVR2_STATE_ERROR] =   "error",
 252         [PVR2_STATE_READY] =   "ready",
 253         [PVR2_STATE_RUN] =     "run",
 254 };
 255
 256
 257 struct pvr2_fx2cmd_descdef {
 258         unsigned char id;
 259         unsigned char *desc;
 260 };
 261
 262 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 263         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 264         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 265         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 266         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 267         {FX2CMD_REG_WRITE, "write encoder register"},
 268         {FX2CMD_REG_READ, "read encoder register"},
 269         {FX2CMD_MEMSEL, "encoder memsel"},
 270         {FX2CMD_I2C_WRITE, "i2c write"},
 271         {FX2CMD_I2C_READ, "i2c read"},
 272         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 273         {FX2CMD_STREAMING_ON, "stream on"},
 274         {FX2CMD_STREAMING_OFF, "stream off"},
 275         {FX2CMD_FWPOST1, "fwpost1"},
 276         {FX2CMD_POWER_OFF, "power off"},
 277         {FX2CMD_POWER_ON, "power on"},
 278         {FX2CMD_DEEP_RESET, "deep reset"},
 279         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 280         {FX2CMD_GET_IR_CODE, "get IR code"},
 281         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 282         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 283         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 284         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 285         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 286         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 287         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 288 };
 289
 290
 291 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 292 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 293 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 294 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 295 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 296 static void pvr2_hdw_worker_poll(struct work_struct *work);
 297 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 298 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 299 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 300 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 301 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 302 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 303 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 304 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 305 static void pvr2_hdw_quiescent_timeout(unsigned long);
 306 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 307 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 308 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 309 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 310                                 unsigned int timeout,int probe_fl,
 311                                 void *write_data,unsigned int write_len,
 312                                 void *read_data,unsigned int read_len);
 313 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 314
 315
 316 static void trace_stbit(const char *name,int val)
 317 {
 318         pvr2_trace(PVR2_TRACE_STBITS,
 319                    "State bit %s <-- %s",
 320                    name,(val ? "true" : "false"));
 321 }
 322
 323 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 324 {
 325         struct pvr2_hdw *hdw = cptr->hdw;
 326         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 327                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 328         } else {
 329                 *vp = 0;
 330         }
 331         return 0;
 332 }
 333
 334 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 335 {
 336         struct pvr2_hdw *hdw = cptr->hdw;
 337         unsigned int slotId = hdw->freqProgSlot;
 338         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 339                 hdw->freqTable[slotId-1] = v;
 340                 /* Handle side effects correctly - if we're tuned to this
 341                    slot, then forgot the slot id relation since the stored
 342                    frequency has been changed. */
 343                 if (hdw->freqSelector) {
 344                         if (hdw->freqSlotRadio == slotId) {
 345                                 hdw->freqSlotRadio = 0;
 346                         }
 347                 } else {
 348                         if (hdw->freqSlotTelevision == slotId) {
 349                                 hdw->freqSlotTelevision = 0;
 350                         }
 351                 }
 352         }
 353         return 0;
 354 }
 355
 356 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 357 {
 358         *vp = cptr->hdw->freqProgSlot;
 359         return 0;
 360 }
 361
 362 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 363 {
 364         struct pvr2_hdw *hdw = cptr->hdw;
 365         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 366                 hdw->freqProgSlot = v;
 367         }
 368         return 0;
 369 }
 370
 371 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 372 {
 373         struct pvr2_hdw *hdw = cptr->hdw;
 374         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 375         return 0;
 376 }
 377
 378 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 379 {
 380         unsigned freq = 0;
 381         struct pvr2_hdw *hdw = cptr->hdw;
 382         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 383         if (slotId > 0) {
 384                 freq = hdw->freqTable[slotId-1];
 385                 if (!freq) return 0;
 386                 pvr2_hdw_set_cur_freq(hdw,freq);
 387         }
 388         if (hdw->freqSelector) {
 389                 hdw->freqSlotRadio = slotId;
 390         } else {
 391                 hdw->freqSlotTelevision = slotId;
 392         }
 393         return 0;
 394 }
 395
 396 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 397 {
 398         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 399         return 0;
 400 }
 401
 402 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 403 {
 404         return cptr->hdw->freqDirty != 0;
 405 }
 406
 407 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 408 {
 409         cptr->hdw->freqDirty = 0;
 410 }
 411
 412 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 413 {
 414         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 415         return 0;
 416 }
 417
 418 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 419 {
 420         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 421         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 422         if (stat != 0) {
 423                 return stat;
 424         }
 425         *left = cap->bounds.left;
 426         return 0;
 427 }
 428
 429 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 430 {
 431         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 432         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 433         if (stat != 0) {
 434                 return stat;
 435         }
 436         *left = cap->bounds.left;
 437         if (cap->bounds.width > cptr->hdw->cropw_val) {
 438                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 439         }
 440         return 0;
 441 }
 442
 443 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 444 {
 445         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 446         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 447         if (stat != 0) {
 448                 return stat;
 449         }
 450         *top = cap->bounds.top;
 451         return 0;
 452 }
 453
 454 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 455 {
 456         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 457         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 458         if (stat != 0) {
 459                 return stat;
 460         }
 461         *top = cap->bounds.top;
 462         if (cap->bounds.height > cptr->hdw->croph_val) {
 463                 *top += cap->bounds.height - cptr->hdw->croph_val;
 464         }
 465         return 0;
 466 }
 467
 468 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 469 {
 470         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 471         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 472         if (stat != 0) {
 473                 return stat;
 474         }
 475         *val = 0;
 476         if (cap->bounds.width > cptr->hdw->cropl_val) {
 477                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 478         }
 479         return 0;
 480 }
 481
 482 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 483 {
 484         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 485         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 486         if (stat != 0) {
 487                 return stat;
 488         }
 489         *val = 0;
 490         if (cap->bounds.height > cptr->hdw->cropt_val) {
 491                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 492         }
 493         return 0;
 494 }
 495
 496 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 497 {
 498         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 499         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 500         if (stat != 0) {
 501                 return stat;
 502         }
 503         *val = cap->bounds.left;
 504         return 0;
 505 }
 506
 507 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 508 {
 509         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 510         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 511         if (stat != 0) {
 512                 return stat;
 513         }
 514         *val = cap->bounds.top;
 515         return 0;
 516 }
 517
 518 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 519 {
 520         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 521         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 522         if (stat != 0) {
 523                 return stat;
 524         }
 525         *val = cap->bounds.width;
 526         return 0;
 527 }
 528
 529 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 530 {
 531         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 532         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 533         if (stat != 0) {
 534                 return stat;
 535         }
 536         *val = cap->bounds.height;
 537         return 0;
 538 }
 539
 540 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 541 {
 542         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 543         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 544         if (stat != 0) {
 545                 return stat;
 546         }
 547         *val = cap->defrect.left;
 548         return 0;
 549 }
 550
 551 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 552 {
 553         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 554         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 555         if (stat != 0) {
 556                 return stat;
 557         }
 558         *val = cap->defrect.top;
 559         return 0;
 560 }
 561
 562 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 563 {
 564         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 565         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 566         if (stat != 0) {
 567                 return stat;
 568         }
 569         *val = cap->defrect.width;
 570         return 0;
 571 }
 572
 573 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 574 {
 575         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 576         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 577         if (stat != 0) {
 578                 return stat;
 579         }
 580         *val = cap->defrect.height;
 581         return 0;
 582 }
 583
 584 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 585 {
 586         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 587         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 588         if (stat != 0) {
 589                 return stat;
 590         }
 591         *val = cap->pixelaspect.numerator;
 592         return 0;
 593 }
 594
 595 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 596 {
 597         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 598         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 599         if (stat != 0) {
 600                 return stat;
 601         }
 602         *val = cap->pixelaspect.denominator;
 603         return 0;
 604 }
 605
 606 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 607 {
 608         /* Actual maximum depends on the video standard in effect. */
 609         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 610                 *vp = 480;
 611         } else {
 612                 *vp = 576;
 613         }
 614         return 0;
 615 }
 616
 617 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 618 {
 619         /* Actual minimum depends on device digitizer type. */
 620         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 621                 *vp = 75;
 622         } else {
 623                 *vp = 17;
 624         }
 625         return 0;
 626 }
 627
 628 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 629 {
 630         *vp = cptr->hdw->input_val;
 631         return 0;
 632 }
 633
 634 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 635 {
 636         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 637 }
 638
 639 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 640 {
 641         return pvr2_hdw_set_input(cptr->hdw,v);
 642 }
 643
 644 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 645 {
 646         return cptr->hdw->input_dirty != 0;
 647 }
 648
 649 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 650 {
 651         cptr->hdw->input_dirty = 0;
 652 }
 653
 654
 655 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 656 {
 657         unsigned long fv;
 658         struct pvr2_hdw *hdw = cptr->hdw;
 659         if (hdw->tuner_signal_stale) {
 660                 pvr2_hdw_status_poll(hdw);
 661         }
 662         fv = hdw->tuner_signal_info.rangehigh;
 663         if (!fv) {
 664                 /* Safety fallback */
 665                 *vp = TV_MAX_FREQ;
 666                 return 0;
 667         }
 668         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 669                 fv = (fv * 125) / 2;
 670         } else {
 671                 fv = fv * 62500;
 672         }
 673         *vp = fv;
 674         return 0;
 675 }
 676
 677 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 678 {
 679         unsigned long fv;
 680         struct pvr2_hdw *hdw = cptr->hdw;
 681         if (hdw->tuner_signal_stale) {
 682                 pvr2_hdw_status_poll(hdw);
 683         }
 684         fv = hdw->tuner_signal_info.rangelow;
 685         if (!fv) {
 686                 /* Safety fallback */
 687                 *vp = TV_MIN_FREQ;
 688                 return 0;
 689         }
 690         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 691                 fv = (fv * 125) / 2;
 692         } else {
 693                 fv = fv * 62500;
 694         }
 695         *vp = fv;
 696         return 0;
 697 }
 698
 699 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 700 {
 701         return cptr->hdw->enc_stale != 0;
 702 }
 703
 704 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 705 {
 706         cptr->hdw->enc_stale = 0;
 707         cptr->hdw->enc_unsafe_stale = 0;
 708 }
 709
 710 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 711 {
 712         int ret;
 713         struct v4l2_ext_controls cs;
 714         struct v4l2_ext_control c1;
 715         memset(&cs,0,sizeof(cs));
 716         memset(&c1,0,sizeof(c1));
 717         cs.controls = &c1;
 718         cs.count = 1;
 719         c1.id = cptr->info->v4l_id;
 720         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 721                                 VIDIOC_G_EXT_CTRLS);
 722         if (ret) return ret;
 723         *vp = c1.value;
 724         return 0;
 725 }
 726
 727 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 728 {
 729         int ret;
 730         struct pvr2_hdw *hdw = cptr->hdw;
 731         struct v4l2_ext_controls cs;
 732         struct v4l2_ext_control c1;
 733         memset(&cs,0,sizeof(cs));
 734         memset(&c1,0,sizeof(c1));
 735         cs.controls = &c1;
 736         cs.count = 1;
 737         c1.id = cptr->info->v4l_id;
 738         c1.value = v;
 739         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 740                                 hdw->state_encoder_run, &cs,
 741                                 VIDIOC_S_EXT_CTRLS);
 742         if (ret == -EBUSY) {
 743                 /* Oops.  cx2341x is telling us it's not safe to change
 744                    this control while we're capturing.  Make a note of this
 745                    fact so that the pipeline will be stopped the next time
 746                    controls are committed.  Then go on ahead and store this
 747                    change anyway. */
 748                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 749                                         0, &cs,
 750                                         VIDIOC_S_EXT_CTRLS);
 751                 if (!ret) hdw->enc_unsafe_stale = !0;
 752         }
 753         if (ret) return ret;
 754         hdw->enc_stale = !0;
 755         return 0;
 756 }
 757
 758 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 759 {
 760         struct v4l2_queryctrl qctrl;
 761         struct pvr2_ctl_info *info;
 762         qctrl.id = cptr->info->v4l_id;
 763         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 764         /* Strip out the const so we can adjust a function pointer.  It's
 765            OK to do this here because we know this is a dynamically created
 766            control, so the underlying storage for the info pointer is (a)
 767            private to us, and (b) not in read-only storage.  Either we do
 768            this or we significantly complicate the underlying control
 769            implementation. */
 770         info = (struct pvr2_ctl_info *)(cptr->info);
 771         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 772                 if (info->set_value) {
 773                         info->set_value = NULL;
 774                 }
 775         } else {
 776                 if (!(info->set_value)) {
 777                         info->set_value = ctrl_cx2341x_set;
 778                 }
 779         }
 780         return qctrl.flags;
 781 }
 782
 783 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 784 {
 785         *vp = cptr->hdw->state_pipeline_req;
 786         return 0;
 787 }
 788
 789 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 790 {
 791         *vp = cptr->hdw->master_state;
 792         return 0;
 793 }
 794
 795 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 796 {
 797         int result = pvr2_hdw_is_hsm(cptr->hdw);
 798         *vp = PVR2_CVAL_HSM_FULL;
 799         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 800         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 801         return 0;
 802 }
 803
 804 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 805 {
 806         *vp = cptr->hdw->std_mask_avail;
 807         return 0;
 808 }
 809
 810 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 811 {
 812         struct pvr2_hdw *hdw = cptr->hdw;
 813         v4l2_std_id ns;
 814         ns = hdw->std_mask_avail;
 815         ns = (ns & ~m) | (v & m);
 816         if (ns == hdw->std_mask_avail) return 0;
 817         hdw->std_mask_avail = ns;
 818         pvr2_hdw_internal_set_std_avail(hdw);
 819         pvr2_hdw_internal_find_stdenum(hdw);
 820         return 0;
 821 }
 822
 823 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 824                                char *bufPtr,unsigned int bufSize,
 825                                unsigned int *len)
 826 {
 827         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 828         return 0;
 829 }
 830
 831 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 832                                const char *bufPtr,unsigned int bufSize,
 833                                int *mskp,int *valp)
 834 {
 835         int ret;
 836         v4l2_std_id id;
 837         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 838         if (ret < 0) return ret;
 839         if (mskp) *mskp = id;
 840         if (valp) *valp = id;
 841         return 0;
 842 }
 843
 844 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 845 {
 846         *vp = cptr->hdw->std_mask_cur;
 847         return 0;
 848 }
 849
 850 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 851 {
 852         struct pvr2_hdw *hdw = cptr->hdw;
 853         v4l2_std_id ns;
 854         ns = hdw->std_mask_cur;
 855         ns = (ns & ~m) | (v & m);
 856         if (ns == hdw->std_mask_cur) return 0;
 857         hdw->std_mask_cur = ns;
 858         hdw->std_dirty = !0;
 859         pvr2_hdw_internal_find_stdenum(hdw);
 860         return 0;
 861 }
 862
 863 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 864 {
 865         return cptr->hdw->std_dirty != 0;
 866 }
 867
 868 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 869 {
 870         cptr->hdw->std_dirty = 0;
 871 }
 872
 873 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 874 {
 875         struct pvr2_hdw *hdw = cptr->hdw;
 876         pvr2_hdw_status_poll(hdw);
 877         *vp = hdw->tuner_signal_info.signal;
 878         return 0;
 879 }
 880
 881 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 882 {
 883         int val = 0;
 884         unsigned int subchan;
 885         struct pvr2_hdw *hdw = cptr->hdw;
 886         pvr2_hdw_status_poll(hdw);
 887         subchan = hdw->tuner_signal_info.rxsubchans;
 888         if (subchan & V4L2_TUNER_SUB_MONO) {
 889                 val |= (1 << V4L2_TUNER_MODE_MONO);
 890         }
 891         if (subchan & V4L2_TUNER_SUB_STEREO) {
 892                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 893         }
 894         if (subchan & V4L2_TUNER_SUB_LANG1) {
 895                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 896         }
 897         if (subchan & V4L2_TUNER_SUB_LANG2) {
 898                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 899         }
 900         *vp = val;
 901         return 0;
 902 }
 903
 904
 905 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 906 {
 907         struct pvr2_hdw *hdw = cptr->hdw;
 908         if (v < 0) return -EINVAL;
 909         if (v > hdw->std_enum_cnt) return -EINVAL;
 910         hdw->std_enum_cur = v;
 911         if (!v) return 0;
 912         v--;
 913         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 914         hdw->std_mask_cur = hdw->std_defs[v].id;
 915         hdw->std_dirty = !0;
 916         return 0;
 917 }
 918
 919
 920 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 921 {
 922         *vp = cptr->hdw->std_enum_cur;
 923         return 0;
 924 }
 925
 926
 927 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 928 {
 929         return cptr->hdw->std_dirty != 0;
 930 }
 931
 932
 933 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 934 {
 935         cptr->hdw->std_dirty = 0;
 936 }
 937
 938
 939 #define DEFINT(vmin,vmax) \
 940         .type = pvr2_ctl_int, \
 941         .def.type_int.min_value = vmin, \
 942         .def.type_int.max_value = vmax
 943
 944 #define DEFENUM(tab) \
 945         .type = pvr2_ctl_enum, \
 946         .def.type_enum.count = ARRAY_SIZE(tab), \
 947         .def.type_enum.value_names = tab
 948
 949 #define DEFBOOL \
 950         .type = pvr2_ctl_bool
 951
 952 #define DEFMASK(msk,tab) \
 953         .type = pvr2_ctl_bitmask, \
 954         .def.type_bitmask.valid_bits = msk, \
 955         .def.type_bitmask.bit_names = tab
 956
 957 #define DEFREF(vname) \
 958         .set_value = ctrl_set_##vname, \
 959         .get_value = ctrl_get_##vname, \
 960         .is_dirty = ctrl_isdirty_##vname, \
 961         .clear_dirty = ctrl_cleardirty_##vname
 962
 963
 964 #define VCREATE_FUNCS(vname) \
 965 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 966 {*vp = cptr->hdw->vname##_val; return 0;} \
 967 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 968 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 969 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 970 {return cptr->hdw->vname##_dirty != 0;} \
 971 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 972 {cptr->hdw->vname##_dirty = 0;}
 973
 974 VCREATE_FUNCS(brightness)
 975 VCREATE_FUNCS(contrast)
 976 VCREATE_FUNCS(saturation)
 977 VCREATE_FUNCS(hue)
 978 VCREATE_FUNCS(volume)
 979 VCREATE_FUNCS(balance)
 980 VCREATE_FUNCS(bass)
 981 VCREATE_FUNCS(treble)
 982 VCREATE_FUNCS(mute)
 983 VCREATE_FUNCS(cropl)
 984 VCREATE_FUNCS(cropt)
 985 VCREATE_FUNCS(cropw)
 986 VCREATE_FUNCS(croph)
 987 VCREATE_FUNCS(audiomode)
 988 VCREATE_FUNCS(res_hor)
 989 VCREATE_FUNCS(res_ver)
 990 VCREATE_FUNCS(srate)
 991
 992 /* Table definition of all controls which can be manipulated */
 993 static const struct pvr2_ctl_info control_defs[] = {
 994         {
 995                 .v4l_id = V4L2_CID_BRIGHTNESS,
 996                 .desc = "Brightness",
 997                 .name = "brightness",
 998                 .default_value = 128,
 999                 DEFREF(brightness),
1000                 DEFINT(0,255),
1001         },{
1002                 .v4l_id = V4L2_CID_CONTRAST,
1003                 .desc = "Contrast",
1004                 .name = "contrast",
1005                 .default_value = 68,
1006                 DEFREF(contrast),
1007                 DEFINT(0,127),
1008         },{
1009                 .v4l_id = V4L2_CID_SATURATION,
1010                 .desc = "Saturation",
1011                 .name = "saturation",
1012                 .default_value = 64,
1013                 DEFREF(saturation),
1014                 DEFINT(0,127),
1015         },{
1016                 .v4l_id = V4L2_CID_HUE,
1017                 .desc = "Hue",
1018                 .name = "hue",
1019                 .default_value = 0,
1020                 DEFREF(hue),
1021                 DEFINT(-128,127),
1022         },{
1023                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1024                 .desc = "Volume",
1025                 .name = "volume",
1026                 .default_value = 62000,
1027                 DEFREF(volume),
1028                 DEFINT(0,65535),
1029         },{
1030                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1031                 .desc = "Balance",
1032                 .name = "balance",
1033                 .default_value = 0,
1034                 DEFREF(balance),
1035                 DEFINT(-32768,32767),
1036         },{
1037                 .v4l_id = V4L2_CID_AUDIO_BASS,
1038                 .desc = "Bass",
1039                 .name = "bass",
1040                 .default_value = 0,
1041                 DEFREF(bass),
1042                 DEFINT(-32768,32767),
1043         },{
1044                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1045                 .desc = "Treble",
1046                 .name = "treble",
1047                 .default_value = 0,
1048                 DEFREF(treble),
1049                 DEFINT(-32768,32767),
1050         },{
1051                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1052                 .desc = "Mute",
1053                 .name = "mute",
1054                 .default_value = 0,
1055                 DEFREF(mute),
1056                 DEFBOOL,
1057         }, {
1058                 .desc = "Capture crop left margin",
1059                 .name = "crop_left",
1060                 .internal_id = PVR2_CID_CROPL,
1061                 .default_value = 0,
1062                 DEFREF(cropl),
1063                 DEFINT(-129, 340),
1064                 .get_min_value = ctrl_cropl_min_get,
1065                 .get_max_value = ctrl_cropl_max_get,
1066                 .get_def_value = ctrl_get_cropcapdl,
1067         }, {
1068                 .desc = "Capture crop top margin",
1069                 .name = "crop_top",
1070                 .internal_id = PVR2_CID_CROPT,
1071                 .default_value = 0,
1072                 DEFREF(cropt),
1073                 DEFINT(-35, 544),
1074                 .get_min_value = ctrl_cropt_min_get,
1075                 .get_max_value = ctrl_cropt_max_get,
1076                 .get_def_value = ctrl_get_cropcapdt,
1077         }, {
1078                 .desc = "Capture crop width",
1079                 .name = "crop_width",
1080                 .internal_id = PVR2_CID_CROPW,
1081                 .default_value = 720,
1082                 DEFREF(cropw),
1083                 .get_max_value = ctrl_cropw_max_get,
1084                 .get_def_value = ctrl_get_cropcapdw,
1085         }, {
1086                 .desc = "Capture crop height",
1087                 .name = "crop_height",
1088                 .internal_id = PVR2_CID_CROPH,
1089                 .default_value = 480,
1090                 DEFREF(croph),
1091                 .get_max_value = ctrl_croph_max_get,
1092                 .get_def_value = ctrl_get_cropcapdh,
1093         }, {
1094                 .desc = "Capture capability pixel aspect numerator",
1095                 .name = "cropcap_pixel_numerator",
1096                 .internal_id = PVR2_CID_CROPCAPPAN,
1097                 .get_value = ctrl_get_cropcappan,
1098         }, {
1099                 .desc = "Capture capability pixel aspect denominator",
1100                 .name = "cropcap_pixel_denominator",
1101                 .internal_id = PVR2_CID_CROPCAPPAD,
1102                 .get_value = ctrl_get_cropcappad,
1103         }, {
1104                 .desc = "Capture capability bounds top",
1105                 .name = "cropcap_bounds_top",
1106                 .internal_id = PVR2_CID_CROPCAPBT,
1107                 .get_value = ctrl_get_cropcapbt,
1108         }, {
1109                 .desc = "Capture capability bounds left",
1110                 .name = "cropcap_bounds_left",
1111                 .internal_id = PVR2_CID_CROPCAPBL,
1112                 .get_value = ctrl_get_cropcapbl,
1113         }, {
1114                 .desc = "Capture capability bounds width",
1115                 .name = "cropcap_bounds_width",
1116                 .internal_id = PVR2_CID_CROPCAPBW,
1117                 .get_value = ctrl_get_cropcapbw,
1118         }, {
1119                 .desc = "Capture capability bounds height",
1120                 .name = "cropcap_bounds_height",
1121                 .internal_id = PVR2_CID_CROPCAPBH,
1122                 .get_value = ctrl_get_cropcapbh,
1123         },{
1124                 .desc = "Video Source",
1125                 .name = "input",
1126                 .internal_id = PVR2_CID_INPUT,
1127                 .default_value = PVR2_CVAL_INPUT_TV,
1128                 .check_value = ctrl_check_input,
1129                 DEFREF(input),
1130                 DEFENUM(control_values_input),
1131         },{
1132                 .desc = "Audio Mode",
1133                 .name = "audio_mode",
1134                 .internal_id = PVR2_CID_AUDIOMODE,
1135                 .default_value = V4L2_TUNER_MODE_STEREO,
1136                 DEFREF(audiomode),
1137                 DEFENUM(control_values_audiomode),
1138         },{
1139                 .desc = "Horizontal capture resolution",
1140                 .name = "resolution_hor",
1141                 .internal_id = PVR2_CID_HRES,
1142                 .default_value = 720,
1143                 DEFREF(res_hor),
1144                 DEFINT(19,720),
1145         },{
1146                 .desc = "Vertical capture resolution",
1147                 .name = "resolution_ver",
1148                 .internal_id = PVR2_CID_VRES,
1149                 .default_value = 480,
1150                 DEFREF(res_ver),
1151                 DEFINT(17,576),
1152                 /* Hook in check for video standard and adjust maximum
1153                    depending on the standard. */
1154                 .get_max_value = ctrl_vres_max_get,
1155                 .get_min_value = ctrl_vres_min_get,
1156         },{
1157                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1158                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1159                 .desc = "Audio Sampling Frequency",
1160                 .name = "srate",
1161                 DEFREF(srate),
1162                 DEFENUM(control_values_srate),
1163         },{
1164                 .desc = "Tuner Frequency (Hz)",
1165                 .name = "frequency",
1166                 .internal_id = PVR2_CID_FREQUENCY,
1167                 .default_value = 0,
1168                 .set_value = ctrl_freq_set,
1169                 .get_value = ctrl_freq_get,
1170                 .is_dirty = ctrl_freq_is_dirty,
1171                 .clear_dirty = ctrl_freq_clear_dirty,
1172                 DEFINT(0,0),
1173                 /* Hook in check for input value (tv/radio) and adjust
1174                    max/min values accordingly */
1175                 .get_max_value = ctrl_freq_max_get,
1176                 .get_min_value = ctrl_freq_min_get,
1177         },{
1178                 .desc = "Channel",
1179                 .name = "channel",
1180                 .set_value = ctrl_channel_set,
1181                 .get_value = ctrl_channel_get,
1182                 DEFINT(0,FREQTABLE_SIZE),
1183         },{
1184                 .desc = "Channel Program Frequency",
1185                 .name = "freq_table_value",
1186                 .set_value = ctrl_channelfreq_set,
1187                 .get_value = ctrl_channelfreq_get,
1188                 DEFINT(0,0),
1189                 /* Hook in check for input value (tv/radio) and adjust
1190                    max/min values accordingly */
1191                 .get_max_value = ctrl_freq_max_get,
1192                 .get_min_value = ctrl_freq_min_get,
1193         },{
1194                 .desc = "Channel Program ID",
1195                 .name = "freq_table_channel",
1196                 .set_value = ctrl_channelprog_set,
1197                 .get_value = ctrl_channelprog_get,
1198                 DEFINT(0,FREQTABLE_SIZE),
1199         },{
1200                 .desc = "Streaming Enabled",
1201                 .name = "streaming_enabled",
1202                 .get_value = ctrl_streamingenabled_get,
1203                 DEFBOOL,
1204         },{
1205                 .desc = "USB Speed",
1206                 .name = "usb_speed",
1207                 .get_value = ctrl_hsm_get,
1208                 DEFENUM(control_values_hsm),
1209         },{
1210                 .desc = "Master State",
1211                 .name = "master_state",
1212                 .get_value = ctrl_masterstate_get,
1213                 DEFENUM(pvr2_state_names),
1214         },{
1215                 .desc = "Signal Present",
1216                 .name = "signal_present",
1217                 .get_value = ctrl_signal_get,
1218                 DEFINT(0,65535),
1219         },{
1220                 .desc = "Audio Modes Present",
1221                 .name = "audio_modes_present",
1222                 .get_value = ctrl_audio_modes_present_get,
1223                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1224                    v4l.  Nothing outside of this module cares about this,
1225                    but I reuse it in order to also reuse the
1226                    control_values_audiomode string table. */
1227                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1228                          (1 << V4L2_TUNER_MODE_STEREO)|
1229                          (1 << V4L2_TUNER_MODE_LANG1)|
1230                          (1 << V4L2_TUNER_MODE_LANG2)),
1231                         control_values_audiomode),
1232         },{
1233                 .desc = "Video Standards Available Mask",
1234                 .name = "video_standard_mask_available",
1235                 .internal_id = PVR2_CID_STDAVAIL,
1236                 .skip_init = !0,
1237                 .get_value = ctrl_stdavail_get,
1238                 .set_value = ctrl_stdavail_set,
1239                 .val_to_sym = ctrl_std_val_to_sym,
1240                 .sym_to_val = ctrl_std_sym_to_val,
1241                 .type = pvr2_ctl_bitmask,
1242         },{
1243                 .desc = "Video Standards In Use Mask",
1244                 .name = "video_standard_mask_active",
1245                 .internal_id = PVR2_CID_STDCUR,
1246                 .skip_init = !0,
1247                 .get_value = ctrl_stdcur_get,
1248                 .set_value = ctrl_stdcur_set,
1249                 .is_dirty = ctrl_stdcur_is_dirty,
1250                 .clear_dirty = ctrl_stdcur_clear_dirty,
1251                 .val_to_sym = ctrl_std_val_to_sym,
1252                 .sym_to_val = ctrl_std_sym_to_val,
1253                 .type = pvr2_ctl_bitmask,
1254         },{
1255                 .desc = "Video Standard Name",
1256                 .name = "video_standard",
1257                 .internal_id = PVR2_CID_STDENUM,
1258                 .skip_init = !0,
1259                 .get_value = ctrl_stdenumcur_get,
1260                 .set_value = ctrl_stdenumcur_set,
1261                 .is_dirty = ctrl_stdenumcur_is_dirty,
1262                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1263                 .type = pvr2_ctl_enum,
1264         }
1265 };
1266
1267 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1268
1269
1270 const char *pvr2_config_get_name(enum pvr2_config cfg)
1271 {
1272         switch (cfg) {
1273         case pvr2_config_empty: return "empty";
1274         case pvr2_config_mpeg: return "mpeg";
1275         case pvr2_config_vbi: return "vbi";
1276         case pvr2_config_pcm: return "pcm";
1277         case pvr2_config_rawvideo: return "raw video";
1278         }
1279         return "<unknown>";
1280 }
1281
1282
1283 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1284 {
1285         return hdw->usb_dev;
1286 }
1287
1288
1289 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1290 {
1291         return hdw->serial_number;
1292 }
1293
1294
1295 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1296 {
1297         return hdw->bus_info;
1298 }
1299
1300
1301 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1302 {
1303         return hdw->identifier;
1304 }
1305
1306
1307 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1308 {
1309         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1310 }
1311
1312 /* Set the currently tuned frequency and account for all possible
1313    driver-core side effects of this action. */
1314 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1315 {
1316         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1317                 if (hdw->freqSelector) {
1318                         /* Swing over to radio frequency selection */
1319                         hdw->freqSelector = 0;
1320                         hdw->freqDirty = !0;
1321                 }
1322                 if (hdw->freqValRadio != val) {
1323                         hdw->freqValRadio = val;
1324                         hdw->freqSlotRadio = 0;
1325                         hdw->freqDirty = !0;
1326                 }
1327         } else {
1328                 if (!(hdw->freqSelector)) {
1329                         /* Swing over to television frequency selection */
1330                         hdw->freqSelector = 1;
1331                         hdw->freqDirty = !0;
1332                 }
1333                 if (hdw->freqValTelevision != val) {
1334                         hdw->freqValTelevision = val;
1335                         hdw->freqSlotTelevision = 0;
1336                         hdw->freqDirty = !0;
1337                 }
1338         }
1339 }
1340
1341 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1342 {
1343         return hdw->unit_number;
1344 }
1345
1346
1347 /* Attempt to locate one of the given set of files.  Messages are logged
1348    appropriate to what has been found.  The return value will be 0 or
1349    greater on success (it will be the index of the file name found) and
1350    fw_entry will be filled in.  Otherwise a negative error is returned on
1351    failure.  If the return value is -ENOENT then no viable firmware file
1352    could be located. */
1353 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1354                                 const struct firmware **fw_entry,
1355                                 const char *fwtypename,
1356                                 unsigned int fwcount,
1357                                 const char *fwnames[])
1358 {
1359         unsigned int idx;
1360         int ret = -EINVAL;
1361         for (idx = 0; idx < fwcount; idx++) {
1362                 ret = request_firmware(fw_entry,
1363                                        fwnames[idx],
1364                                        &hdw->usb_dev->dev);
1365                 if (!ret) {
1366                         trace_firmware("Located %s firmware: %s;"
1367                                        " uploading...",
1368                                        fwtypename,
1369                                        fwnames[idx]);
1370                         return idx;
1371                 }
1372                 if (ret == -ENOENT) continue;
1373                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1374                            "request_firmware fatal error with code=%d",ret);
1375                 return ret;
1376         }
1377         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1378                    "***WARNING***"
1379                    " Device %s firmware"
1380                    " seems to be missing.",
1381                    fwtypename);
1382         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1383                    "Did you install the pvrusb2 firmware files"
1384                    " in their proper location?");
1385         if (fwcount == 1) {
1386                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1387                            "request_firmware unable to locate %s file %s",
1388                            fwtypename,fwnames[0]);
1389         } else {
1390                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391                            "request_firmware unable to locate"
1392                            " one of the following %s files:",
1393                            fwtypename);
1394                 for (idx = 0; idx < fwcount; idx++) {
1395                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396                                    "request_firmware: Failed to find %s",
1397                                    fwnames[idx]);
1398                 }
1399         }
1400         return ret;
1401 }
1402
1403
1404 /*
1405  * pvr2_upload_firmware1().
1406  *
1407  * Send the 8051 firmware to the device.  After the upload, arrange for
1408  * device to re-enumerate.
1409  *
1410  * NOTE : the pointer to the firmware data given by request_firmware()
1411  * is not suitable for an usb transaction.
1412  *
1413  */
1414 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1415 {
1416         const struct firmware *fw_entry = NULL;
1417         void  *fw_ptr;
1418         unsigned int pipe;
1419         int ret;
1420         u16 address;
1421
1422         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1423                 hdw->fw1_state = FW1_STATE_OK;
1424                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425                            "Connected device type defines"
1426                            " no firmware to upload; ignoring firmware");
1427                 return -ENOTTY;
1428         }
1429
1430         hdw->fw1_state = FW1_STATE_FAILED; // default result
1431
1432         trace_firmware("pvr2_upload_firmware1");
1433
1434         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1435                                    hdw->hdw_desc->fx2_firmware.cnt,
1436                                    hdw->hdw_desc->fx2_firmware.lst);
1437         if (ret < 0) {
1438                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1439                 return ret;
1440         }
1441
1442         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1443         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1444
1445         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1446
1447         if (fw_entry->size != 0x2000){
1448                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1449                 release_firmware(fw_entry);
1450                 return -ENOMEM;
1451         }
1452
1453         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1454         if (fw_ptr == NULL){
1455                 release_firmware(fw_entry);
1456                 return -ENOMEM;
1457         }
1458
1459         /* We have to hold the CPU during firmware upload. */
1460         pvr2_hdw_cpureset_assert(hdw,1);
1461
1462         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1463            chunk. */
1464
1465         ret = 0;
1466         for(address = 0; address < fw_entry->size; address += 0x800) {
1467                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1468                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1469                                        0, fw_ptr, 0x800, HZ);
1470         }
1471
1472         trace_firmware("Upload done, releasing device's CPU");
1473
1474         /* Now release the CPU.  It will disconnect and reconnect later. */
1475         pvr2_hdw_cpureset_assert(hdw,0);
1476
1477         kfree(fw_ptr);
1478         release_firmware(fw_entry);
1479
1480         trace_firmware("Upload done (%d bytes sent)",ret);
1481
1482         /* We should have written 8192 bytes */
1483         if (ret == 8192) {
1484                 hdw->fw1_state = FW1_STATE_RELOAD;
1485                 return 0;
1486         }
1487
1488         return -EIO;
1489 }
1490
1491
1492 /*
1493  * pvr2_upload_firmware2()
1494  *
1495  * This uploads encoder firmware on endpoint 2.
1496  *
1497  */
1498
1499 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1500 {
1501         const struct firmware *fw_entry = NULL;
1502         void  *fw_ptr;
1503         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1504         int actual_length;
1505         int ret = 0;
1506         int fwidx;
1507         static const char *fw_files[] = {
1508                 CX2341X_FIRM_ENC_FILENAME,
1509         };
1510
1511         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1512                 return 0;
1513         }
1514
1515         trace_firmware("pvr2_upload_firmware2");
1516
1517         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1518                                    ARRAY_SIZE(fw_files), fw_files);
1519         if (ret < 0) return ret;
1520         fwidx = ret;
1521         ret = 0;
1522         /* Since we're about to completely reinitialize the encoder,
1523            invalidate our cached copy of its configuration state.  Next
1524            time we configure the encoder, then we'll fully configure it. */
1525         hdw->enc_cur_valid = 0;
1526
1527         /* Encoder is about to be reset so note that as far as we're
1528            concerned now, the encoder has never been run. */
1529         del_timer_sync(&hdw->encoder_run_timer);
1530         if (hdw->state_encoder_runok) {
1531                 hdw->state_encoder_runok = 0;
1532                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1533         }
1534
1535         /* First prepare firmware loading */
1536         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1537         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1538         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1539         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1540         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1541         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1542         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1543         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1544         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1545         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1546         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1547         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1548         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1549         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1550         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1551         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1552         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1553         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1554
1555         if (ret) {
1556                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1557                            "firmware2 upload prep failed, ret=%d",ret);
1558                 release_firmware(fw_entry);
1559                 goto done;
1560         }
1561
1562         /* Now send firmware */
1563
1564         fw_len = fw_entry->size;
1565
1566         if (fw_len % sizeof(u32)) {
1567                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1568                            "size of %s firmware"
1569                            " must be a multiple of %zu bytes",
1570                            fw_files[fwidx],sizeof(u32));
1571                 release_firmware(fw_entry);
1572                 ret = -EINVAL;
1573                 goto done;
1574         }
1575
1576         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1577         if (fw_ptr == NULL){
1578                 release_firmware(fw_entry);
1579                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1580                            "failed to allocate memory for firmware2 upload");
1581                 ret = -ENOMEM;
1582                 goto done;
1583         }
1584
1585         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1586
1587         fw_done = 0;
1588         for (fw_done = 0; fw_done < fw_len;) {
1589                 bcnt = fw_len - fw_done;
1590                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1591                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1592                 /* Usbsnoop log shows that we must swap bytes... */
1593                 /* Some background info: The data being swapped here is a
1594                    firmware image destined for the mpeg encoder chip that
1595                    lives at the other end of a USB endpoint.  The encoder
1596                    chip always talks in 32 bit chunks and its storage is
1597                    organized into 32 bit words.  However from the file
1598                    system to the encoder chip everything is purely a byte
1599                    stream.  The firmware file's contents are always 32 bit
1600                    swapped from what the encoder expects.  Thus the need
1601                    always exists to swap the bytes regardless of the endian
1602                    type of the host processor and therefore swab32() makes
1603                    the most sense. */
1604                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1605                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1606
1607                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1608                                     &actual_length, HZ);
1609                 ret |= (actual_length != bcnt);
1610                 if (ret) break;
1611                 fw_done += bcnt;
1612         }
1613
1614         trace_firmware("upload of %s : %i / %i ",
1615                        fw_files[fwidx],fw_done,fw_len);
1616
1617         kfree(fw_ptr);
1618         release_firmware(fw_entry);
1619
1620         if (ret) {
1621                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1622                            "firmware2 upload transfer failure");
1623                 goto done;
1624         }
1625
1626         /* Finish upload */
1627
1628         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1629         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1630         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1631
1632         if (ret) {
1633                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1634                            "firmware2 upload post-proc failure");
1635         }
1636
1637  done:
1638         if (hdw->hdw_desc->signal_routing_scheme ==
1639             PVR2_ROUTING_SCHEME_GOTVIEW) {
1640                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1641                    hardware. */
1642                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1643         }
1644         return ret;
1645 }
1646
1647
1648 static const char *pvr2_get_state_name(unsigned int st)
1649 {
1650         if (st < ARRAY_SIZE(pvr2_state_names)) {
1651                 return pvr2_state_names[st];
1652         }
1653         return "???";
1654 }
1655
1656 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1657 {
1658         if (hdw->decoder_ctrl) {
1659                 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1660                 return 0;
1661         }
1662         /* Even though we really only care about the video decoder chip at
1663            this point, we'll broadcast stream on/off to all sub-devices
1664            anyway, just in case somebody else wants to hear the
1665            command... */
1666         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1667         if (hdw->decoder_client_id) {
1668                 /* We get here if the encoder has been noticed.  Otherwise
1669                    we'll issue a warning to the user (which should
1670                    normally never happen). */
1671                 return 0;
1672         }
1673         if (!hdw->flag_decoder_missed) {
1674                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1675                            "WARNING: No decoder present");
1676                 hdw->flag_decoder_missed = !0;
1677                 trace_stbit("flag_decoder_missed",
1678                             hdw->flag_decoder_missed);
1679         }
1680         return -EIO;
1681 }
1682
1683
1684 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1685 {
1686         if (hdw->decoder_ctrl == ptr) return;
1687         hdw->decoder_ctrl = ptr;
1688         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1689                 hdw->flag_decoder_missed = 0;
1690                 trace_stbit("flag_decoder_missed",
1691                             hdw->flag_decoder_missed);
1692                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1693                            "Decoder has appeared");
1694                 pvr2_hdw_state_sched(hdw);
1695         }
1696 }
1697
1698
1699 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1700 {
1701         return hdw->master_state;
1702 }
1703
1704
1705 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1706 {
1707         if (!hdw->flag_tripped) return 0;
1708         hdw->flag_tripped = 0;
1709         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1710                    "Clearing driver error statuss");
1711         return !0;
1712 }
1713
1714
1715 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1716 {
1717         int fl;
1718         LOCK_TAKE(hdw->big_lock); do {
1719                 fl = pvr2_hdw_untrip_unlocked(hdw);
1720         } while (0); LOCK_GIVE(hdw->big_lock);
1721         if (fl) pvr2_hdw_state_sched(hdw);
1722         return 0;
1723 }
1724
1725
1726
1727
1728 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1729 {
1730         return hdw->state_pipeline_req != 0;
1731 }
1732
1733
1734 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1735 {
1736         int ret,st;
1737         LOCK_TAKE(hdw->big_lock); do {
1738                 pvr2_hdw_untrip_unlocked(hdw);
1739                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1740                         hdw->state_pipeline_req = enable_flag != 0;
1741                         pvr2_trace(PVR2_TRACE_START_STOP,
1742                                    "/*--TRACE_STREAM--*/ %s",
1743                                    enable_flag ? "enable" : "disable");
1744                 }
1745                 pvr2_hdw_state_sched(hdw);
1746         } while (0); LOCK_GIVE(hdw->big_lock);
1747         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1748         if (enable_flag) {
1749                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1750                         if (st != PVR2_STATE_READY) return -EIO;
1751                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1752                 }
1753         }
1754         return 0;
1755 }
1756
1757
1758 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1759 {
1760         int fl;
1761         LOCK_TAKE(hdw->big_lock);
1762         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1763                 hdw->desired_stream_type = config;
1764                 hdw->state_pipeline_config = 0;
1765                 trace_stbit("state_pipeline_config",
1766                             hdw->state_pipeline_config);
1767                 pvr2_hdw_state_sched(hdw);
1768         }
1769         LOCK_GIVE(hdw->big_lock);
1770         if (fl) return 0;
1771         return pvr2_hdw_wait(hdw,0);
1772 }
1773
1774
1775 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1776 {
1777         int unit_number = hdw->unit_number;
1778         int tp = -1;
1779         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1780                 tp = tuner[unit_number];
1781         }
1782         if (tp < 0) return -EINVAL;
1783         hdw->tuner_type = tp;
1784         hdw->tuner_updated = !0;
1785         return 0;
1786 }
1787
1788
1789 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1790 {
1791         int unit_number = hdw->unit_number;
1792         int tp = 0;
1793         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1794                 tp = video_std[unit_number];
1795                 if (tp) return tp;
1796         }
1797         return 0;
1798 }
1799
1800
1801 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1802 {
1803         int unit_number = hdw->unit_number;
1804         int tp = 0;
1805         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1806                 tp = tolerance[unit_number];
1807         }
1808         return tp;
1809 }
1810
1811
1812 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1813 {
1814         /* Try a harmless request to fetch the eeprom's address over
1815            endpoint 1.  See what happens.  Only the full FX2 image can
1816            respond to this.  If this probe fails then likely the FX2
1817            firmware needs be loaded. */
1818         int result;
1819         LOCK_TAKE(hdw->ctl_lock); do {
1820                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1821                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1822                                            hdw->cmd_buffer,1,
1823                                            hdw->cmd_buffer,1);
1824                 if (result < 0) break;
1825         } while(0); LOCK_GIVE(hdw->ctl_lock);
1826         if (result) {
1827                 pvr2_trace(PVR2_TRACE_INIT,
1828                            "Probe of device endpoint 1 result status %d",
1829                            result);
1830         } else {
1831                 pvr2_trace(PVR2_TRACE_INIT,
1832                            "Probe of device endpoint 1 succeeded");
1833         }
1834         return result == 0;
1835 }
1836
1837 struct pvr2_std_hack {
1838         v4l2_std_id pat;  /* Pattern to match */
1839         v4l2_std_id msk;  /* Which bits we care about */
1840         v4l2_std_id std;  /* What additional standards or default to set */
1841 };
1842
1843 /* This data structure labels specific combinations of standards from
1844    tveeprom that we'll try to recognize.  If we recognize one, then assume
1845    a specified default standard to use.  This is here because tveeprom only
1846    tells us about available standards not the intended default standard (if
1847    any) for the device in question.  We guess the default based on what has
1848    been reported as available.  Note that this is only for guessing a
1849    default - which can always be overridden explicitly - and if the user
1850    has otherwise named a default then that default will always be used in
1851    place of this table. */
1852 static const struct pvr2_std_hack std_eeprom_maps[] = {
1853         {       /* PAL(B/G) */
1854                 .pat = V4L2_STD_B|V4L2_STD_GH,
1855                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1856         },
1857         {       /* NTSC(M) */
1858                 .pat = V4L2_STD_MN,
1859                 .std = V4L2_STD_NTSC_M,
1860         },
1861         {       /* PAL(I) */
1862                 .pat = V4L2_STD_PAL_I,
1863                 .std = V4L2_STD_PAL_I,
1864         },
1865         {       /* SECAM(L/L') */
1866                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1867                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1868         },
1869         {       /* PAL(D/D1/K) */
1870                 .pat = V4L2_STD_DK,
1871                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1872         },
1873 };
1874
1875 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1876 {
1877         char buf[40];
1878         unsigned int bcnt;
1879         v4l2_std_id std1,std2,std3;
1880
1881         std1 = get_default_standard(hdw);
1882         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1883
1884         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1885         pvr2_trace(PVR2_TRACE_STD,
1886                    "Supported video standard(s) reported available"
1887                    " in hardware: %.*s",
1888                    bcnt,buf);
1889
1890         hdw->std_mask_avail = hdw->std_mask_eeprom;
1891
1892         std2 = (std1|std3) & ~hdw->std_mask_avail;
1893         if (std2) {
1894                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1895                 pvr2_trace(PVR2_TRACE_STD,
1896                            "Expanding supported video standards"
1897                            " to include: %.*s",
1898                            bcnt,buf);
1899                 hdw->std_mask_avail |= std2;
1900         }
1901
1902         pvr2_hdw_internal_set_std_avail(hdw);
1903
1904         if (std1) {
1905                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1906                 pvr2_trace(PVR2_TRACE_STD,
1907                            "Initial video standard forced to %.*s",
1908                            bcnt,buf);
1909                 hdw->std_mask_cur = std1;
1910                 hdw->std_dirty = !0;
1911                 pvr2_hdw_internal_find_stdenum(hdw);
1912                 return;
1913         }
1914         if (std3) {
1915                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1916                 pvr2_trace(PVR2_TRACE_STD,
1917                            "Initial video standard"
1918                            " (determined by device type): %.*s",bcnt,buf);
1919                 hdw->std_mask_cur = std3;
1920                 hdw->std_dirty = !0;
1921                 pvr2_hdw_internal_find_stdenum(hdw);
1922                 return;
1923         }
1924
1925         {
1926                 unsigned int idx;
1927                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1928                         if (std_eeprom_maps[idx].msk ?
1929                             ((std_eeprom_maps[idx].pat ^
1930                              hdw->std_mask_eeprom) &
1931                              std_eeprom_maps[idx].msk) :
1932                             (std_eeprom_maps[idx].pat !=
1933                              hdw->std_mask_eeprom)) continue;
1934                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1935                                                   std_eeprom_maps[idx].std);
1936                         pvr2_trace(PVR2_TRACE_STD,
1937                                    "Initial video standard guessed as %.*s",
1938                                    bcnt,buf);
1939                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1940                         hdw->std_dirty = !0;
1941                         pvr2_hdw_internal_find_stdenum(hdw);
1942                         return;
1943                 }
1944         }
1945
1946         if (hdw->std_enum_cnt > 1) {
1947                 // Autoselect the first listed standard
1948                 hdw->std_enum_cur = 1;
1949                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1950                 hdw->std_dirty = !0;
1951                 pvr2_trace(PVR2_TRACE_STD,
1952                            "Initial video standard auto-selected to %s",
1953                            hdw->std_defs[hdw->std_enum_cur-1].name);
1954                 return;
1955         }
1956
1957         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1958                    "Unable to select a viable initial video standard");
1959 }
1960
1961
1962 static unsigned int pvr2_copy_i2c_addr_list(
1963         unsigned short *dst, const unsigned char *src,
1964         unsigned int dst_max)
1965 {
1966         unsigned int cnt;
1967         if (!src) return 0;
1968         while (src[cnt] && (cnt + 1) < dst_max) {
1969                 dst[cnt] = src[cnt];
1970                 cnt++;
1971         }
1972         dst[cnt] = I2C_CLIENT_END;
1973         return cnt;
1974 }
1975
1976
1977 static void pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1978                                  const struct pvr2_device_client_desc *cd)
1979 {
1980         const char *fname;
1981         unsigned char mid;
1982         struct v4l2_subdev *sd;
1983         unsigned int i2ccnt;
1984         const unsigned char *p;
1985         /* Arbitrary count - max # i2c addresses we will probe */
1986         unsigned short i2caddr[25];
1987
1988         mid = cd->module_id;
1989         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1990         if (!fname) {
1991                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1992                            "Module ID %u for device %s is unknown"
1993                            " (this is probably a bad thing...)",
1994                            mid,
1995                            hdw->hdw_desc->description);
1996                 return;
1997         }
1998
1999         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2000                                          ARRAY_SIZE(i2caddr));
2001         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2002                          module_i2c_addresses[mid] : NULL) != NULL)) {
2003                 /* Second chance: Try default i2c address list */
2004                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2005                                                  ARRAY_SIZE(i2caddr));
2006         }
2007
2008         if (!i2ccnt) {
2009                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2010                            "Module ID %u for device %s:"
2011                            " No i2c addresses"
2012                            " (this is probably a bad thing...)",
2013                            mid, hdw->hdw_desc->description);
2014                 return;
2015         }
2016
2017         /* Note how the 2nd and 3rd arguments are the same for both
2018          * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev().  Why?
2019          * Well the 2nd argument is the module name to load, while the 3rd
2020          * argument is documented in the framework as being the "chipid" -
2021          * and every other place where I can find examples of this, the
2022          * "chipid" appears to just be the module name again.  So here we
2023          * just do the same thing. */
2024         if (i2ccnt == 1) {
2025                 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2026                                          fname, fname,
2027                                          i2caddr[0]);
2028         } else {
2029                 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2030                                                 fname, fname,
2031                                                 i2caddr);
2032         }
2033
2034         if (!sd) {
2035                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2036                            "Module ID %u for device %s failed to load"
2037                            " (this is probably a bad thing...)",
2038                            mid, hdw->hdw_desc->description);
2039                 return;
2040         }
2041
2042         /* Tag this sub-device instance with the module ID we know about.
2043            In other places we'll use that tag to determine if the instance
2044            requires special handling. */
2045         sd->grp_id = mid;
2046
2047         /* If we have both old and new i2c layers enabled, make sure that
2048            old layer isn't also tracking this module.  This is a debugging
2049            aid, in normal situations there's no reason for both mechanisms
2050            to be enabled. */
2051         pvr2_i2c_untrack_subdev(hdw, sd);
2052         pvr2_trace(PVR2_TRACE_INIT, "Attached sub-driver %s", fname);
2053
2054
2055         /* client-specific setup... */
2056         switch (mid) {
2057         case PVR2_CLIENT_ID_CX25840:
2058                 hdw->decoder_client_id = mid;
2059                 {
2060                         /*
2061                           Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2062                           bit of nuttiness for cx25840 causes that module
2063                           to correctly set up its video scaling.  This is
2064                           really a problem in the cx25840 module itself,
2065                           but we work around it here.  The problem has not
2066                           been seen in ivtv because there VBI is supported
2067                           and set up.  We don't do VBI here (at least not
2068                           yet) and thus we never attempted to even set it
2069                           up.
2070                         */
2071                         struct v4l2_format fmt;
2072                         memset(&fmt, 0, sizeof(fmt));
2073                         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2074                         v4l2_device_call_all(&hdw->v4l2_dev, mid,
2075                                              video, s_fmt, &fmt);
2076                 }
2077                 break;
2078         case PVR2_CLIENT_ID_SAA7115:
2079                 hdw->decoder_client_id = mid;
2080                 break;
2081         default: break;
2082         }
2083 }
2084
2085
2086 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2087 {
2088         unsigned int idx;
2089         const struct pvr2_string_table *cm;
2090         const struct pvr2_device_client_table *ct;
2091
2092         cm = &hdw->hdw_desc->client_modules;
2093         for (idx = 0; idx < cm->cnt; idx++) {
2094                 request_module(cm->lst[idx]);
2095         }
2096
2097         ct = &hdw->hdw_desc->client_table;
2098         for (idx = 0; idx < ct->cnt; idx++) {
2099                 pvr2_hdw_load_subdev(hdw,&ct->lst[idx]);
2100         }
2101 }
2102
2103
2104 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2105 {
2106         int ret;
2107         unsigned int idx;
2108         struct pvr2_ctrl *cptr;
2109         int reloadFl = 0;
2110         if (hdw->hdw_desc->fx2_firmware.cnt) {
2111                 if (!reloadFl) {
2112                         reloadFl =
2113                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2114                                  == 0);
2115                         if (reloadFl) {
2116                                 pvr2_trace(PVR2_TRACE_INIT,
2117                                            "USB endpoint config looks strange"
2118                                            "; possibly firmware needs to be"
2119                                            " loaded");
2120                         }
2121                 }
2122                 if (!reloadFl) {
2123                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2124                         if (reloadFl) {
2125                                 pvr2_trace(PVR2_TRACE_INIT,
2126                                            "Check for FX2 firmware failed"
2127                                            "; possibly firmware needs to be"
2128                                            " loaded");
2129                         }
2130                 }
2131                 if (reloadFl) {
2132                         if (pvr2_upload_firmware1(hdw) != 0) {
2133                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2134                                            "Failure uploading firmware1");
2135                         }
2136                         return;
2137                 }
2138         }
2139         hdw->fw1_state = FW1_STATE_OK;
2140
2141         if (!pvr2_hdw_dev_ok(hdw)) return;
2142
2143         if (!hdw->hdw_desc->flag_no_powerup) {
2144                 pvr2_hdw_cmd_powerup(hdw);
2145                 if (!pvr2_hdw_dev_ok(hdw)) return;
2146         }
2147
2148         /* Take the IR chip out of reset, if appropriate */
2149         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2150                 pvr2_issue_simple_cmd(hdw,
2151                                       FX2CMD_HCW_ZILOG_RESET |
2152                                       (1 << 8) |
2153                                       ((0) << 16));
2154         }
2155
2156         // This step MUST happen after the earlier powerup step.
2157         pvr2_i2c_track_init(hdw);
2158         pvr2_i2c_core_init(hdw);
2159         if (!pvr2_hdw_dev_ok(hdw)) return;
2160
2161         pvr2_hdw_load_modules(hdw);
2162
2163         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2164                 cptr = hdw->controls + idx;
2165                 if (cptr->info->skip_init) continue;
2166                 if (!cptr->info->set_value) continue;
2167                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2168         }
2169
2170         /* Set up special default values for the television and radio
2171            frequencies here.  It's not really important what these defaults
2172            are, but I set them to something usable in the Chicago area just
2173            to make driver testing a little easier. */
2174
2175         hdw->freqValTelevision = default_tv_freq;
2176         hdw->freqValRadio = default_radio_freq;
2177
2178         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2179         // thread-safe against the normal pvr2_send_request() mechanism.
2180         // (We should make it thread safe).
2181
2182         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2183                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2184                 if (!pvr2_hdw_dev_ok(hdw)) return;
2185                 if (ret < 0) {
2186                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2187                                    "Unable to determine location of eeprom,"
2188                                    " skipping");
2189                 } else {
2190                         hdw->eeprom_addr = ret;
2191                         pvr2_eeprom_analyze(hdw);
2192                         if (!pvr2_hdw_dev_ok(hdw)) return;
2193                 }
2194         } else {
2195                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2196                 hdw->tuner_updated = !0;
2197                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2198         }
2199
2200         if (hdw->serial_number) {
2201                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2202                                 "sn-%lu", hdw->serial_number);
2203         } else if (hdw->unit_number >= 0) {
2204                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2205                                 "unit-%c",
2206                                 hdw->unit_number + 'a');
2207         } else {
2208                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2209                                 "unit-??");
2210         }
2211         hdw->identifier[idx] = 0;
2212
2213         pvr2_hdw_setup_std(hdw);
2214
2215         if (!get_default_tuner_type(hdw)) {
2216                 pvr2_trace(PVR2_TRACE_INIT,
2217                            "pvr2_hdw_setup: Tuner type overridden to %d",
2218                            hdw->tuner_type);
2219         }
2220
2221         pvr2_i2c_core_check_stale(hdw);
2222         hdw->tuner_updated = 0;
2223
2224         if (!pvr2_hdw_dev_ok(hdw)) return;
2225
2226         if (hdw->hdw_desc->signal_routing_scheme ==
2227             PVR2_ROUTING_SCHEME_GOTVIEW) {
2228                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2229                    hardware. */
2230                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2231         }
2232
2233         pvr2_hdw_commit_setup(hdw);
2234
2235         hdw->vid_stream = pvr2_stream_create();
2236         if (!pvr2_hdw_dev_ok(hdw)) return;
2237         pvr2_trace(PVR2_TRACE_INIT,
2238                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2239         if (hdw->vid_stream) {
2240                 idx = get_default_error_tolerance(hdw);
2241                 if (idx) {
2242                         pvr2_trace(PVR2_TRACE_INIT,
2243                                    "pvr2_hdw_setup: video stream %p"
2244                                    " setting tolerance %u",
2245                                    hdw->vid_stream,idx);
2246                 }
2247                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2248                                   PVR2_VID_ENDPOINT,idx);
2249         }
2250
2251         if (!pvr2_hdw_dev_ok(hdw)) return;
2252
2253         hdw->flag_init_ok = !0;
2254
2255         pvr2_hdw_state_sched(hdw);
2256 }
2257
2258
2259 /* Set up the structure and attempt to put the device into a usable state.
2260    This can be a time-consuming operation, which is why it is not done
2261    internally as part of the create() step. */
2262 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2263 {
2264         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2265         do {
2266                 pvr2_hdw_setup_low(hdw);
2267                 pvr2_trace(PVR2_TRACE_INIT,
2268                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2269                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2270                 if (pvr2_hdw_dev_ok(hdw)) {
2271                         if (hdw->flag_init_ok) {
2272                                 pvr2_trace(
2273                                         PVR2_TRACE_INFO,
2274                                         "Device initialization"
2275                                         " completed successfully.");
2276                                 break;
2277                         }
2278                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2279                                 pvr2_trace(
2280                                         PVR2_TRACE_INFO,
2281                                         "Device microcontroller firmware"
2282                                         " (re)loaded; it should now reset"
2283                                         " and reconnect.");
2284                                 break;
2285                         }
2286                         pvr2_trace(
2287                                 PVR2_TRACE_ERROR_LEGS,
2288                                 "Device initialization was not successful.");
2289                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2290                                 pvr2_trace(
2291                                         PVR2_TRACE_ERROR_LEGS,
2292                                         "Giving up since device"
2293                                         " microcontroller firmware"
2294                                         " appears to be missing.");
2295                                 break;
2296                         }
2297                 }
2298                 if (procreload) {
2299                         pvr2_trace(
2300                                 PVR2_TRACE_ERROR_LEGS,
2301                                 "Attempting pvrusb2 recovery by reloading"
2302                                 " primary firmware.");
2303                         pvr2_trace(
2304                                 PVR2_TRACE_ERROR_LEGS,
2305                                 "If this works, device should disconnect"
2306                                 " and reconnect in a sane state.");
2307                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2308                         pvr2_upload_firmware1(hdw);
2309                 } else {
2310                         pvr2_trace(
2311                                 PVR2_TRACE_ERROR_LEGS,
2312                                 "***WARNING*** pvrusb2 device hardware"
2313                                 " appears to be jammed"
2314                                 " and I can't clear it.");
2315                         pvr2_trace(
2316                                 PVR2_TRACE_ERROR_LEGS,
2317                                 "You might need to power cycle"
2318                                 " the pvrusb2 device"
2319                                 " in order to recover.");
2320                 }
2321         } while (0);
2322         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2323 }
2324
2325
2326 /* Perform second stage initialization.  Set callback pointer first so that
2327    we can avoid a possible initialization race (if the kernel thread runs
2328    before the callback has been set). */
2329 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2330                         void (*callback_func)(void *),
2331                         void *callback_data)
2332 {
2333         LOCK_TAKE(hdw->big_lock); do {
2334                 if (hdw->flag_disconnected) {
2335                         /* Handle a race here: If we're already
2336                            disconnected by this point, then give up.  If we
2337                            get past this then we'll remain connected for
2338                            the duration of initialization since the entire
2339                            initialization sequence is now protected by the
2340                            big_lock. */
2341                         break;
2342                 }
2343                 hdw->state_data = callback_data;
2344                 hdw->state_func = callback_func;
2345                 pvr2_hdw_setup(hdw);
2346         } while (0); LOCK_GIVE(hdw->big_lock);
2347         return hdw->flag_init_ok;
2348 }
2349
2350
2351 /* Create, set up, and return a structure for interacting with the
2352    underlying hardware.  */
2353 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2354                                  const struct usb_device_id *devid)
2355 {
2356         unsigned int idx,cnt1,cnt2,m;
2357         struct pvr2_hdw *hdw = NULL;
2358         int valid_std_mask;
2359         struct pvr2_ctrl *cptr;
2360         struct usb_device *usb_dev;
2361         const struct pvr2_device_desc *hdw_desc;
2362         __u8 ifnum;
2363         struct v4l2_queryctrl qctrl;
2364         struct pvr2_ctl_info *ciptr;
2365
2366         usb_dev = interface_to_usbdev(intf);
2367
2368         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2369
2370         if (hdw_desc == NULL) {
2371                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2372                            " No device description pointer,"
2373                            " unable to continue.");
2374                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2375                            " please contact Mike Isely <isely@pobox.com>"
2376                            " to get it included in the driver\n");
2377                 goto fail;
2378         }
2379
2380         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2381         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2382                    hdw,hdw_desc->description);
2383         if (!hdw) goto fail;
2384
2385         init_timer(&hdw->quiescent_timer);
2386         hdw->quiescent_timer.data = (unsigned long)hdw;
2387         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2388
2389         init_timer(&hdw->encoder_wait_timer);
2390         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2391         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2392
2393         init_timer(&hdw->encoder_run_timer);
2394         hdw->encoder_run_timer.data = (unsigned long)hdw;
2395         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2396
2397         hdw->master_state = PVR2_STATE_DEAD;
2398
2399         init_waitqueue_head(&hdw->state_wait_data);
2400
2401         hdw->tuner_signal_stale = !0;
2402         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2403
2404         /* Calculate which inputs are OK */
2405         m = 0;
2406         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2407         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2408                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2409         }
2410         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2411         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2412         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2413         hdw->input_avail_mask = m;
2414         hdw->input_allowed_mask = hdw->input_avail_mask;
2415
2416         /* If not a hybrid device, pathway_state never changes.  So
2417            initialize it here to what it should forever be. */
2418         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2419                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2420         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2421                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2422         }
2423
2424         hdw->control_cnt = CTRLDEF_COUNT;
2425         hdw->control_cnt += MPEGDEF_COUNT;
2426         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2427                                 GFP_KERNEL);
2428         if (!hdw->controls) goto fail;
2429         hdw->hdw_desc = hdw_desc;
2430         for (idx = 0; idx < hdw->control_cnt; idx++) {
2431                 cptr = hdw->controls + idx;
2432                 cptr->hdw = hdw;
2433         }
2434         for (idx = 0; idx < 32; idx++) {
2435                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2436         }
2437         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2438                 cptr = hdw->controls + idx;
2439                 cptr->info = control_defs+idx;
2440         }
2441
2442         /* Ensure that default input choice is a valid one. */
2443         m = hdw->input_avail_mask;
2444         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2445                 if (!((1 << idx) & m)) continue;
2446                 hdw->input_val = idx;
2447                 break;
2448         }
2449
2450         /* Define and configure additional controls from cx2341x module. */
2451         hdw->mpeg_ctrl_info = kzalloc(
2452                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2453         if (!hdw->mpeg_ctrl_info) goto fail;
2454         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2455                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2456                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2457                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2458                 ciptr->name = mpeg_ids[idx].strid;
2459                 ciptr->v4l_id = mpeg_ids[idx].id;
2460                 ciptr->skip_init = !0;
2461                 ciptr->get_value = ctrl_cx2341x_get;
2462                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2463                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2464                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2465                 qctrl.id = ciptr->v4l_id;
2466                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2467                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2468                         ciptr->set_value = ctrl_cx2341x_set;
2469                 }
2470                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2471                         PVR2_CTLD_INFO_DESC_SIZE);
2472                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2473                 ciptr->default_value = qctrl.default_value;
2474                 switch (qctrl.type) {
2475                 default:
2476                 case V4L2_CTRL_TYPE_INTEGER:
2477                         ciptr->type = pvr2_ctl_int;
2478                         ciptr->def.type_int.min_value = qctrl.minimum;
2479                         ciptr->def.type_int.max_value = qctrl.maximum;
2480                         break;
2481                 case V4L2_CTRL_TYPE_BOOLEAN:
2482                         ciptr->type = pvr2_ctl_bool;
2483                         break;
2484                 case V4L2_CTRL_TYPE_MENU:
2485                         ciptr->type = pvr2_ctl_enum;
2486                         ciptr->def.type_enum.value_names =
2487                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2488                                                                 ciptr->v4l_id);
2489                         for (cnt1 = 0;
2490                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2491                              cnt1++) { }
2492                         ciptr->def.type_enum.count = cnt1;
2493                         break;
2494                 }
2495                 cptr->info = ciptr;
2496         }
2497
2498         // Initialize video standard enum dynamic control
2499         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2500         if (cptr) {
2501                 memcpy(&hdw->std_info_enum,cptr->info,
2502                        sizeof(hdw->std_info_enum));
2503                 cptr->info = &hdw->std_info_enum;
2504
2505         }
2506         // Initialize control data regarding video standard masks
2507         valid_std_mask = pvr2_std_get_usable();
2508         for (idx = 0; idx < 32; idx++) {
2509                 if (!(valid_std_mask & (1 << idx))) continue;
2510                 cnt1 = pvr2_std_id_to_str(
2511                         hdw->std_mask_names[idx],
2512                         sizeof(hdw->std_mask_names[idx])-1,
2513                         1 << idx);
2514                 hdw->std_mask_names[idx][cnt1] = 0;
2515         }
2516         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2517         if (cptr) {
2518                 memcpy(&hdw->std_info_avail,cptr->info,
2519                        sizeof(hdw->std_info_avail));
2520                 cptr->info = &hdw->std_info_avail;
2521                 hdw->std_info_avail.def.type_bitmask.bit_names =
2522                         hdw->std_mask_ptrs;
2523                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2524                         valid_std_mask;
2525         }
2526         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2527         if (cptr) {
2528                 memcpy(&hdw->std_info_cur,cptr->info,
2529                        sizeof(hdw->std_info_cur));
2530                 cptr->info = &hdw->std_info_cur;
2531                 hdw->std_info_cur.def.type_bitmask.bit_names =
2532                         hdw->std_mask_ptrs;
2533                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2534                         valid_std_mask;
2535         }
2536
2537         hdw->cropcap_stale = !0;
2538         hdw->eeprom_addr = -1;
2539         hdw->unit_number = -1;
2540         hdw->v4l_minor_number_video = -1;
2541         hdw->v4l_minor_number_vbi = -1;
2542         hdw->v4l_minor_number_radio = -1;
2543         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2544         if (!hdw->ctl_write_buffer) goto fail;
2545         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2546         if (!hdw->ctl_read_buffer) goto fail;
2547         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2548         if (!hdw->ctl_write_urb) goto fail;
2549         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2550         if (!hdw->ctl_read_urb) goto fail;
2551
2552         if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2553                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2554                            "Error registering with v4l core, giving up");
2555                 goto fail;
2556         }
2557         mutex_lock(&pvr2_unit_mtx); do {
2558                 for (idx = 0; idx < PVR_NUM; idx++) {
2559                         if (unit_pointers[idx]) continue;
2560                         hdw->unit_number = idx;
2561                         unit_pointers[idx] = hdw;
2562                         break;
2563                 }
2564         } while (0); mutex_unlock(&pvr2_unit_mtx);
2565
2566         cnt1 = 0;
2567         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2568         cnt1 += cnt2;
2569         if (hdw->unit_number >= 0) {
2570                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2571                                  ('a' + hdw->unit_number));
2572                 cnt1 += cnt2;
2573         }
2574         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2575         hdw->name[cnt1] = 0;
2576
2577         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2578         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2579         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2580
2581         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2582                    hdw->unit_number,hdw->name);
2583
2584         hdw->tuner_type = -1;
2585         hdw->flag_ok = !0;
2586
2587         hdw->usb_intf = intf;
2588         hdw->usb_dev = usb_dev;
2589
2590         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2591
2592         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2593         usb_set_interface(hdw->usb_dev,ifnum,0);
2594
2595         mutex_init(&hdw->ctl_lock_mutex);
2596         mutex_init(&hdw->big_lock_mutex);
2597
2598         return hdw;
2599  fail:
2600         if (hdw) {
2601                 del_timer_sync(&hdw->quiescent_timer);
2602                 del_timer_sync(&hdw->encoder_run_timer);
2603                 del_timer_sync(&hdw->encoder_wait_timer);
2604                 if (hdw->workqueue) {
2605                         flush_workqueue(hdw->workqueue);
2606                         destroy_workqueue(hdw->workqueue);
2607                         hdw->workqueue = NULL;
2608                 }
2609                 usb_free_urb(hdw->ctl_read_urb);
2610                 usb_free_urb(hdw->ctl_write_urb);
2611                 kfree(hdw->ctl_read_buffer);
2612                 kfree(hdw->ctl_write_buffer);
2613                 kfree(hdw->controls);
2614                 kfree(hdw->mpeg_ctrl_info);
2615                 kfree(hdw->std_defs);
2616                 kfree(hdw->std_enum_names);
2617                 kfree(hdw);
2618         }
2619         return NULL;
2620 }
2621
2622
2623 /* Remove _all_ associations between this driver and the underlying USB
2624    layer. */
2625 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2626 {
2627         if (hdw->flag_disconnected) return;
2628         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2629         if (hdw->ctl_read_urb) {
2630                 usb_kill_urb(hdw->ctl_read_urb);
2631                 usb_free_urb(hdw->ctl_read_urb);
2632                 hdw->ctl_read_urb = NULL;
2633         }
2634         if (hdw->ctl_write_urb) {
2635                 usb_kill_urb(hdw->ctl_write_urb);
2636                 usb_free_urb(hdw->ctl_write_urb);
2637                 hdw->ctl_write_urb = NULL;
2638         }
2639         if (hdw->ctl_read_buffer) {
2640                 kfree(hdw->ctl_read_buffer);
2641                 hdw->ctl_read_buffer = NULL;
2642         }
2643         if (hdw->ctl_write_buffer) {
2644                 kfree(hdw->ctl_write_buffer);
2645                 hdw->ctl_write_buffer = NULL;
2646         }
2647         hdw->flag_disconnected = !0;
2648         /* If we don't do this, then there will be a dangling struct device
2649            reference to our disappearing device persisting inside the V4L
2650            core... */
2651         if (hdw->v4l2_dev.dev) {
2652                 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2653                 hdw->v4l2_dev.dev = NULL;
2654         }
2655         hdw->usb_dev = NULL;
2656         hdw->usb_intf = NULL;
2657         pvr2_hdw_render_useless(hdw);
2658 }
2659
2660
2661 /* Destroy hardware interaction structure */
2662 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2663 {
2664         if (!hdw) return;
2665         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2666         if (hdw->workqueue) {
2667                 flush_workqueue(hdw->workqueue);
2668                 destroy_workqueue(hdw->workqueue);
2669                 hdw->workqueue = NULL;
2670         }
2671         del_timer_sync(&hdw->quiescent_timer);
2672         del_timer_sync(&hdw->encoder_run_timer);
2673         del_timer_sync(&hdw->encoder_wait_timer);
2674         if (hdw->fw_buffer) {
2675                 kfree(hdw->fw_buffer);
2676                 hdw->fw_buffer = NULL;
2677         }
2678         if (hdw->vid_stream) {
2679                 pvr2_stream_destroy(hdw->vid_stream);
2680                 hdw->vid_stream = NULL;
2681         }
2682         if (hdw->decoder_ctrl) {
2683                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2684         }
2685         pvr2_i2c_core_done(hdw);
2686         pvr2_i2c_track_done(hdw);
2687         v4l2_device_unregister(&hdw->v4l2_dev);
2688         pvr2_hdw_remove_usb_stuff(hdw);
2689         mutex_lock(&pvr2_unit_mtx); do {
2690                 if ((hdw->unit_number >= 0) &&
2691                     (hdw->unit_number < PVR_NUM) &&
2692                     (unit_pointers[hdw->unit_number] == hdw)) {
2693                         unit_pointers[hdw->unit_number] = NULL;
2694                 }
2695         } while (0); mutex_unlock(&pvr2_unit_mtx);
2696         kfree(hdw->controls);
2697         kfree(hdw->mpeg_ctrl_info);
2698         kfree(hdw->std_defs);
2699         kfree(hdw->std_enum_names);
2700         kfree(hdw);
2701 }
2702
2703
2704 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2705 {
2706         return (hdw && hdw->flag_ok);
2707 }
2708
2709
2710 /* Called when hardware has been unplugged */
2711 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2712 {
2713         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2714         LOCK_TAKE(hdw->big_lock);
2715         LOCK_TAKE(hdw->ctl_lock);
2716         pvr2_hdw_remove_usb_stuff(hdw);
2717         LOCK_GIVE(hdw->ctl_lock);
2718         LOCK_GIVE(hdw->big_lock);
2719 }
2720
2721
2722 // Attempt to autoselect an appropriate value for std_enum_cur given
2723 // whatever is currently in std_mask_cur
2724 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2725 {
2726         unsigned int idx;
2727         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2728                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2729                         hdw->std_enum_cur = idx;
2730                         return;
2731                 }
2732         }
2733         hdw->std_enum_cur = 0;
2734 }
2735
2736
2737 // Calculate correct set of enumerated standards based on currently known
2738 // set of available standards bits.
2739 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2740 {
2741         struct v4l2_standard *newstd;
2742         unsigned int std_cnt;
2743         unsigned int idx;
2744
2745         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2746
2747         if (hdw->std_defs) {
2748                 kfree(hdw->std_defs);
2749                 hdw->std_defs = NULL;
2750         }
2751         hdw->std_enum_cnt = 0;
2752         if (hdw->std_enum_names) {
2753                 kfree(hdw->std_enum_names);
2754                 hdw->std_enum_names = NULL;
2755         }
2756
2757         if (!std_cnt) {
2758                 pvr2_trace(
2759                         PVR2_TRACE_ERROR_LEGS,
2760                         "WARNING: Failed to identify any viable standards");
2761         }
2762         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2763         hdw->std_enum_names[0] = "none";
2764         for (idx = 0; idx < std_cnt; idx++) {
2765                 hdw->std_enum_names[idx+1] =
2766                         newstd[idx].name;
2767         }
2768         // Set up the dynamic control for this standard
2769         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2770         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2771         hdw->std_defs = newstd;
2772         hdw->std_enum_cnt = std_cnt+1;
2773         hdw->std_enum_cur = 0;
2774         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2775 }
2776
2777
2778 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2779                                struct v4l2_standard *std,
2780                                unsigned int idx)
2781 {
2782         int ret = -EINVAL;
2783         if (!idx) return ret;
2784         LOCK_TAKE(hdw->big_lock); do {
2785                 if (idx >= hdw->std_enum_cnt) break;
2786                 idx--;
2787                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2788                 ret = 0;
2789         } while (0); LOCK_GIVE(hdw->big_lock);
2790         return ret;
2791 }
2792
2793
2794 /* Get the number of defined controls */
2795 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2796 {
2797         return hdw->control_cnt;
2798 }
2799
2800
2801 /* Retrieve a control handle given its index (0..count-1) */
2802 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2803                                              unsigned int idx)
2804 {
2805         if (idx >= hdw->control_cnt) return NULL;
2806         return hdw->controls + idx;
2807 }
2808
2809
2810 /* Retrieve a control handle given its index (0..count-1) */
2811 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2812                                           unsigned int ctl_id)
2813 {
2814         struct pvr2_ctrl *cptr;
2815         unsigned int idx;
2816         int i;
2817
2818         /* This could be made a lot more efficient, but for now... */
2819         for (idx = 0; idx < hdw->control_cnt; idx++) {
2820                 cptr = hdw->controls + idx;
2821                 i = cptr->info->internal_id;
2822                 if (i && (i == ctl_id)) return cptr;
2823         }
2824         return NULL;
2825 }
2826
2827
2828 /* Given a V4L ID, retrieve the control structure associated with it. */
2829 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2830 {
2831         struct pvr2_ctrl *cptr;
2832         unsigned int idx;
2833         int i;
2834
2835         /* This could be made a lot more efficient, but for now... */
2836         for (idx = 0; idx < hdw->control_cnt; idx++) {
2837                 cptr = hdw->controls + idx;
2838                 i = cptr->info->v4l_id;
2839                 if (i && (i == ctl_id)) return cptr;
2840         }
2841         return NULL;
2842 }
2843
2844
2845 /* Given a V4L ID for its immediate predecessor, retrieve the control
2846    structure associated with it. */
2847 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2848                                             unsigned int ctl_id)
2849 {
2850         struct pvr2_ctrl *cptr,*cp2;
2851         unsigned int idx;
2852         int i;
2853
2854         /* This could be made a lot more efficient, but for now... */
2855         cp2 = NULL;
2856         for (idx = 0; idx < hdw->control_cnt; idx++) {
2857                 cptr = hdw->controls + idx;
2858                 i = cptr->info->v4l_id;
2859                 if (!i) continue;
2860                 if (i <= ctl_id) continue;
2861                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2862                 cp2 = cptr;
2863         }
2864         return cp2;
2865         return NULL;
2866 }
2867
2868
2869 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2870 {
2871         switch (tp) {
2872         case pvr2_ctl_int: return "integer";
2873         case pvr2_ctl_enum: return "enum";
2874         case pvr2_ctl_bool: return "boolean";
2875         case pvr2_ctl_bitmask: return "bitmask";
2876         }
2877         return "";
2878 }
2879
2880
2881 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2882                                     const char *name, int val)
2883 {
2884         struct v4l2_control ctrl;
2885         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2886         memset(&ctrl, 0, sizeof(ctrl));
2887         ctrl.id = id;
2888         ctrl.value = val;
2889         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2890 }
2891
2892 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2893         if ((hdw)->lab##_dirty) { \
2894                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2895         }
2896
2897 /* Execute whatever commands are required to update the state of all the
2898    sub-devices so that they match our current control values. */
2899 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2900 {
2901         if (hdw->input_dirty || hdw->std_dirty) {
2902                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_standard");
2903                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2904                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2905                                              tuner, s_radio);
2906                 } else {
2907                         v4l2_std_id vs;
2908                         vs = hdw->std_mask_cur;
2909                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2910                                              tuner, s_std, vs);
2911                 }
2912                 hdw->tuner_signal_stale = !0;
2913                 hdw->cropcap_stale = !0;
2914         }
2915
2916         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2917         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2918         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2919         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2920         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2921         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2922         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2923         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2924         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2925
2926         if (hdw->input_dirty || hdw->audiomode_dirty) {
2927                 struct v4l2_tuner vt;
2928                 memset(&vt, 0, sizeof(vt));
2929                 vt.audmode = hdw->audiomode_val;
2930                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2931         }
2932
2933         if (hdw->freqDirty) {
2934                 unsigned long fv;
2935                 struct v4l2_frequency freq;
2936                 fv = pvr2_hdw_get_cur_freq(hdw);
2937                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2938                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2939                 memset(&freq, 0, sizeof(freq));
2940                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2941                         /* ((fv * 1000) / 62500) */
2942                         freq.frequency = (fv * 2) / 125;
2943                 } else {
2944                         freq.frequency = fv / 62500;
2945                 }
2946                 /* tuner-core currently doesn't seem to care about this, but
2947                    let's set it anyway for completeness. */
2948                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2949                         freq.type = V4L2_TUNER_RADIO;
2950                 } else {
2951                         freq.type = V4L2_TUNER_ANALOG_TV;
2952                 }
2953                 freq.tuner = 0;
2954                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2955                                      s_frequency, &freq);
2956         }
2957
2958         if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
2959                 struct v4l2_format fmt;
2960                 memset(&fmt, 0, sizeof(fmt));
2961                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2962                 fmt.fmt.pix.width = hdw->res_hor_val;
2963                 fmt.fmt.pix.height = hdw->res_ver_val;
2964                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
2965                            fmt.fmt.pix.width, fmt.fmt.pix.height);
2966                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
2967         }
2968
2969         /* Unable to set crop parameters; there is apparently no equivalent
2970            for VIDIOC_S_CROP */
2971
2972         /* ????? Cover special cases for specific sub-devices. */
2973
2974         if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
2975                 pvr2_hdw_status_poll(hdw);
2976         }
2977 }
2978
2979
2980 /* Figure out if we need to commit control changes.  If so, mark internal
2981    state flags to indicate this fact and return true.  Otherwise do nothing
2982    else and return false. */
2983 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2984 {
2985         unsigned int idx;
2986         struct pvr2_ctrl *cptr;
2987         int value;
2988         int commit_flag = 0;
2989         char buf[100];
2990         unsigned int bcnt,ccnt;
2991
2992         for (idx = 0; idx < hdw->control_cnt; idx++) {
2993                 cptr = hdw->controls + idx;
2994                 if (!cptr->info->is_dirty) continue;
2995                 if (!cptr->info->is_dirty(cptr)) continue;
2996                 commit_flag = !0;
2997
2998                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2999                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3000                                  cptr->info->name);
3001                 value = 0;
3002                 cptr->info->get_value(cptr,&value);
3003                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3004                                                 buf+bcnt,
3005                                                 sizeof(buf)-bcnt,&ccnt);
3006                 bcnt += ccnt;
3007                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3008                                   get_ctrl_typename(cptr->info->type));
3009                 pvr2_trace(PVR2_TRACE_CTL,
3010                            "/*--TRACE_COMMIT--*/ %.*s",
3011                            bcnt,buf);
3012         }
3013
3014         if (!commit_flag) {
3015                 /* Nothing has changed */
3016                 return 0;
3017         }
3018
3019         hdw->state_pipeline_config = 0;
3020         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3021         pvr2_hdw_state_sched(hdw);
3022
3023         return !0;
3024 }
3025
3026
3027 /* Perform all operations needed to commit all control changes.  This must
3028    be performed in synchronization with the pipeline state and is thus
3029    expected to be called as part of the driver's worker thread.  Return
3030    true if commit successful, otherwise return false to indicate that
3031    commit isn't possible at this time. */
3032 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3033 {
3034         unsigned int idx;
3035         struct pvr2_ctrl *cptr;
3036         int disruptive_change;
3037
3038         /* Handle some required side effects when the video standard is
3039            changed.... */
3040         if (hdw->std_dirty) {
3041                 int nvres;
3042                 int gop_size;
3043                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3044                         nvres = 480;
3045                         gop_size = 15;
3046                 } else {
3047                         nvres = 576;
3048                         gop_size = 12;
3049                 }
3050                 /* Rewrite the vertical resolution to be appropriate to the
3051                    video standard that has been selected. */
3052                 if (nvres != hdw->res_ver_val) {
3053                         hdw->res_ver_val = nvres;
3054                         hdw->res_ver_dirty = !0;
3055                 }
3056                 /* Rewrite the GOP size to be appropriate to the video
3057                    standard that has been selected. */
3058                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3059                         struct v4l2_ext_controls cs;
3060                         struct v4l2_ext_control c1;
3061                         memset(&cs, 0, sizeof(cs));
3062                         memset(&c1, 0, sizeof(c1));
3063                         cs.controls = &c1;
3064                         cs.count = 1;
3065                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3066                         c1.value = gop_size;
3067                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3068                                           VIDIOC_S_EXT_CTRLS);
3069                 }
3070         }
3071
3072         if (hdw->input_dirty && hdw->state_pathway_ok &&
3073             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3074               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3075              hdw->pathway_state)) {
3076                 /* Change of mode being asked for... */
3077                 hdw->state_pathway_ok = 0;
3078                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3079         }
3080         if (!hdw->state_pathway_ok) {
3081                 /* Can't commit anything until pathway is ok. */
3082                 return 0;
3083         }
3084         /* The broadcast decoder can only scale down, so if
3085          * res_*_dirty && crop window < output format ==> enlarge crop.
3086          *
3087          * The mpeg encoder receives fields of res_hor_val dots and
3088          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3089          */
3090         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3091                 hdw->cropw_val = hdw->res_hor_val;
3092                 hdw->cropw_dirty = !0;
3093         } else if (hdw->cropw_dirty) {
3094                 hdw->res_hor_dirty = !0;           /* must rescale */
3095                 hdw->res_hor_val = min(720, hdw->cropw_val);
3096         }
3097         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3098                 hdw->croph_val = hdw->res_ver_val;
3099                 hdw->croph_dirty = !0;
3100         } else if (hdw->croph_dirty) {
3101                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3102                 hdw->res_ver_dirty = !0;
3103                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3104         }
3105
3106         /* If any of the below has changed, then we can't do the update
3107            while the pipeline is running.  Pipeline must be paused first
3108            and decoder -> encoder connection be made quiescent before we
3109            can proceed. */
3110         disruptive_change =
3111                 (hdw->std_dirty ||
3112                  hdw->enc_unsafe_stale ||
3113                  hdw->srate_dirty ||
3114                  hdw->res_ver_dirty ||
3115                  hdw->res_hor_dirty ||
3116                  hdw->cropw_dirty ||
3117                  hdw->croph_dirty ||
3118                  hdw->input_dirty ||
3119                  (hdw->active_stream_type != hdw->desired_stream_type));
3120         if (disruptive_change && !hdw->state_pipeline_idle) {
3121                 /* Pipeline is not idle; we can't proceed.  Arrange to
3122                    cause pipeline to stop so that we can try this again
3123                    later.... */
3124                 hdw->state_pipeline_pause = !0;
3125                 return 0;
3126         }
3127
3128         if (hdw->srate_dirty) {
3129                 /* Write new sample rate into control structure since
3130                  * the master copy is stale.  We must track srate
3131                  * separate from the mpeg control structure because
3132                  * other logic also uses this value. */
3133                 struct v4l2_ext_controls cs;
3134                 struct v4l2_ext_control c1;
3135                 memset(&cs,0,sizeof(cs));
3136                 memset(&c1,0,sizeof(c1));
3137                 cs.controls = &c1;
3138                 cs.count = 1;
3139                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3140                 c1.value = hdw->srate_val;
3141                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3142         }
3143
3144         /* Scan i2c core at this point - before we clear all the dirty
3145            bits.  Various parts of the i2c core will notice dirty bits as
3146            appropriate and arrange to broadcast or directly send updates to
3147            the client drivers in order to keep everything in sync */
3148         pvr2_i2c_core_check_stale(hdw);
3149
3150         if (hdw->active_stream_type != hdw->desired_stream_type) {
3151                 /* Handle any side effects of stream config here */
3152                 hdw->active_stream_type = hdw->desired_stream_type;
3153         }
3154
3155         if (hdw->hdw_desc->signal_routing_scheme ==
3156             PVR2_ROUTING_SCHEME_GOTVIEW) {
3157                 u32 b;
3158                 /* Handle GOTVIEW audio switching */
3159                 pvr2_hdw_gpio_get_out(hdw,&b);
3160                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3161                         /* Set GPIO 11 */
3162                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3163                 } else {
3164                         /* Clear GPIO 11 */
3165                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3166                 }
3167         }
3168
3169         for (idx = 0; idx < hdw->control_cnt; idx++) {
3170                 cptr = hdw->controls + idx;
3171                 if (!cptr->info->clear_dirty) continue;
3172                 cptr->info->clear_dirty(cptr);
3173         }
3174
3175         /* Check and update state for all sub-devices. */
3176         pvr2_subdev_update(hdw);
3177
3178         /* Now execute i2c core update */
3179         pvr2_i2c_core_sync(hdw);
3180
3181         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3182             hdw->state_encoder_run) {
3183                 /* If encoder isn't running or it can't be touched, then
3184                    this will get worked out later when we start the
3185                    encoder. */
3186                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3187         }
3188
3189         hdw->state_pipeline_config = !0;
3190         /* Hardware state may have changed in a way to cause the cropping
3191            capabilities to have changed.  So mark it stale, which will
3192            cause a later re-fetch. */
3193         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3194         return !0;
3195 }
3196
3197
3198 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3199 {
3200         int fl;
3201         LOCK_TAKE(hdw->big_lock);
3202         fl = pvr2_hdw_commit_setup(hdw);
3203         LOCK_GIVE(hdw->big_lock);
3204         if (!fl) return 0;
3205         return pvr2_hdw_wait(hdw,0);
3206 }
3207
3208
3209 static void pvr2_hdw_worker_i2c(struct work_struct *work)
3210 {
3211         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
3212         LOCK_TAKE(hdw->big_lock); do {
3213                 pvr2_i2c_core_sync(hdw);
3214         } while (0); LOCK_GIVE(hdw->big_lock);
3215 }
3216
3217
3218 static void pvr2_hdw_worker_poll(struct work_struct *work)
3219 {
3220         int fl = 0;
3221         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3222         LOCK_TAKE(hdw->big_lock); do {
3223                 fl = pvr2_hdw_state_eval(hdw);
3224         } while (0); LOCK_GIVE(hdw->big_lock);
3225         if (fl && hdw->state_func) {
3226                 hdw->state_func(hdw->state_data);
3227         }
3228 }
3229
3230
3231 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3232 {
3233         return wait_event_interruptible(
3234                 hdw->state_wait_data,
3235                 (hdw->state_stale == 0) &&
3236                 (!state || (hdw->master_state != state)));
3237 }
3238
3239
3240 /* Return name for this driver instance */
3241 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3242 {
3243         return hdw->name;
3244 }
3245
3246
3247 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3248 {
3249         return hdw->hdw_desc->description;
3250 }
3251
3252
3253 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3254 {
3255         return hdw->hdw_desc->shortname;
3256 }
3257
3258
3259 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3260 {
3261         int result;
3262         LOCK_TAKE(hdw->ctl_lock); do {
3263                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3264                 result = pvr2_send_request(hdw,
3265                                            hdw->cmd_buffer,1,
3266                                            hdw->cmd_buffer,1);
3267                 if (result < 0) break;
3268                 result = (hdw->cmd_buffer[0] != 0);
3269         } while(0); LOCK_GIVE(hdw->ctl_lock);
3270         return result;
3271 }
3272
3273
3274 /* Execute poll of tuner status */
3275 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3276 {
3277         LOCK_TAKE(hdw->big_lock); do {
3278                 pvr2_hdw_status_poll(hdw);
3279         } while (0); LOCK_GIVE(hdw->big_lock);
3280 }
3281
3282
3283 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3284 {
3285         if (!hdw->cropcap_stale) {
3286                 return 0;
3287         }
3288         pvr2_hdw_status_poll(hdw);
3289         if (hdw->cropcap_stale) {
3290                 return -EIO;
3291         }
3292         return 0;
3293 }
3294
3295
3296 /* Return information about cropping capabilities */
3297 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3298 {
3299         int stat = 0;
3300         LOCK_TAKE(hdw->big_lock);
3301         stat = pvr2_hdw_check_cropcap(hdw);
3302         if (!stat) {
3303                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3304         }
3305         LOCK_GIVE(hdw->big_lock);
3306         return stat;
3307 }
3308
3309
3310 /* Return information about the tuner */
3311 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3312 {
3313         LOCK_TAKE(hdw->big_lock); do {
3314                 if (hdw->tuner_signal_stale) {
3315                         pvr2_hdw_status_poll(hdw);
3316                 }
3317                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3318         } while (0); LOCK_GIVE(hdw->big_lock);
3319         return 0;
3320 }
3321
3322
3323 /* Get handle to video output stream */
3324 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3325 {
3326         return hp->vid_stream;
3327 }
3328
3329
3330 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3331 {
3332         int nr = pvr2_hdw_get_unit_number(hdw);
3333         LOCK_TAKE(hdw->big_lock); do {
3334                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3335                 hdw->log_requested = !0;
3336                 pvr2_i2c_core_check_stale(hdw);
3337                 pvr2_i2c_core_sync(hdw);
3338                 hdw->log_requested = 0;
3339                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3340                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3341                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3342                 pvr2_hdw_state_log_state(hdw);
3343                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3344         } while (0); LOCK_GIVE(hdw->big_lock);
3345 }
3346
3347
3348 /* Grab EEPROM contents, needed for direct method. */
3349 #define EEPROM_SIZE 8192
3350 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3351 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3352 {
3353         struct i2c_msg msg[2];
3354         u8 *eeprom;
3355         u8 iadd[2];
3356         u8 addr;
3357         u16 eepromSize;
3358         unsigned int offs;
3359         int ret;
3360         int mode16 = 0;
3361         unsigned pcnt,tcnt;
3362         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3363         if (!eeprom) {
3364                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3365                            "Failed to allocate memory"
3366                            " required to read eeprom");
3367                 return NULL;
3368         }
3369
3370         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3371                      hdw->eeprom_addr);
3372         addr = hdw->eeprom_addr;
3373         /* Seems that if the high bit is set, then the *real* eeprom
3374            address is shifted right now bit position (noticed this in
3375            newer PVR USB2 hardware) */
3376         if (addr & 0x80) addr >>= 1;
3377
3378         /* FX2 documentation states that a 16bit-addressed eeprom is
3379            expected if the I2C address is an odd number (yeah, this is
3380            strange but it's what they do) */
3381         mode16 = (addr & 1);
3382         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3383         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3384                      " using %d bit addressing",eepromSize,addr,
3385                      mode16 ? 16 : 8);
3386
3387         msg[0].addr = addr;
3388         msg[0].flags = 0;
3389         msg[0].len = mode16 ? 2 : 1;
3390         msg[0].buf = iadd;
3391         msg[1].addr = addr;
3392         msg[1].flags = I2C_M_RD;
3393
3394         /* We have to do the actual eeprom data fetch ourselves, because
3395            (1) we're only fetching part of the eeprom, and (2) if we were
3396            getting the whole thing our I2C driver can't grab it in one
3397            pass - which is what tveeprom is otherwise going to attempt */
3398         memset(eeprom,0,EEPROM_SIZE);
3399         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3400                 pcnt = 16;
3401                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3402                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3403                 if (mode16) {
3404                         iadd[0] = offs >> 8;
3405                         iadd[1] = offs;
3406                 } else {
3407                         iadd[0] = offs;
3408                 }
3409                 msg[1].len = pcnt;
3410                 msg[1].buf = eeprom+tcnt;
3411                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3412                                         msg,ARRAY_SIZE(msg))) != 2) {
3413                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3414                                    "eeprom fetch set offs err=%d",ret);
3415                         kfree(eeprom);
3416                         return NULL;
3417                 }
3418         }
3419         return eeprom;
3420 }
3421
3422
3423 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3424                                 int prom_flag,
3425                                 int enable_flag)
3426 {
3427         int ret;
3428         u16 address;
3429         unsigned int pipe;
3430         LOCK_TAKE(hdw->big_lock); do {
3431                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3432
3433                 if (!enable_flag) {
3434                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3435                                    "Cleaning up after CPU firmware fetch");
3436                         kfree(hdw->fw_buffer);
3437                         hdw->fw_buffer = NULL;
3438                         hdw->fw_size = 0;
3439                         if (hdw->fw_cpu_flag) {
3440                                 /* Now release the CPU.  It will disconnect
3441                                    and reconnect later. */
3442                                 pvr2_hdw_cpureset_assert(hdw,0);
3443                         }
3444                         break;
3445                 }
3446
3447                 hdw->fw_cpu_flag = (prom_flag == 0);
3448                 if (hdw->fw_cpu_flag) {
3449                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3450                                    "Preparing to suck out CPU firmware");
3451                         hdw->fw_size = 0x2000;
3452                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3453                         if (!hdw->fw_buffer) {
3454                                 hdw->fw_size = 0;
3455                                 break;
3456                         }
3457
3458                         /* We have to hold the CPU during firmware upload. */
3459                         pvr2_hdw_cpureset_assert(hdw,1);
3460
3461                         /* download the firmware from address 0000-1fff in 2048
3462                            (=0x800) bytes chunk. */
3463
3464                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3465                                    "Grabbing CPU firmware");
3466                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3467                         for(address = 0; address < hdw->fw_size;
3468                             address += 0x800) {
3469                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3470                                                       0xa0,0xc0,
3471                                                       address,0,
3472                                                       hdw->fw_buffer+address,
3473                                                       0x800,HZ);
3474                                 if (ret < 0) break;
3475                         }
3476
3477                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3478                                    "Done grabbing CPU firmware");
3479                 } else {
3480                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3481                                    "Sucking down EEPROM contents");
3482                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3483                         if (!hdw->fw_buffer) {
3484                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3485                                            "EEPROM content suck failed.");
3486                                 break;
3487                         }
3488                         hdw->fw_size = EEPROM_SIZE;
3489                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3490                                    "Done sucking down EEPROM contents");
3491                 }
3492
3493         } while (0); LOCK_GIVE(hdw->big_lock);
3494 }
3495
3496
3497 /* Return true if we're in a mode for retrieval CPU firmware */
3498 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3499 {
3500         return hdw->fw_buffer != NULL;
3501 }
3502
3503
3504 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3505                        char *buf,unsigned int cnt)
3506 {
3507         int ret = -EINVAL;
3508         LOCK_TAKE(hdw->big_lock); do {
3509                 if (!buf) break;
3510                 if (!cnt) break;
3511
3512                 if (!hdw->fw_buffer) {
3513                         ret = -EIO;
3514                         break;
3515                 }
3516
3517                 if (offs >= hdw->fw_size) {
3518                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3519                                    "Read firmware data offs=%d EOF",
3520                                    offs);
3521                         ret = 0;
3522                         break;
3523                 }
3524
3525                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3526
3527                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3528
3529                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3530                            "Read firmware data offs=%d cnt=%d",
3531                            offs,cnt);
3532                 ret = cnt;
3533         } while (0); LOCK_GIVE(hdw->big_lock);
3534
3535         return ret;
3536 }
3537
3538
3539 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3540                                   enum pvr2_v4l_type index)
3541 {
3542         switch (index) {
3543         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3544         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3545         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3546         default: return -1;
3547         }
3548 }
3549
3550
3551 /* Store a v4l minor device number */
3552 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3553                                      enum pvr2_v4l_type index,int v)
3554 {
3555         switch (index) {
3556         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3557         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3558         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3559         default: break;
3560         }
3561 }
3562
3563
3564 static void pvr2_ctl_write_complete(struct urb *urb)
3565 {
3566         struct pvr2_hdw *hdw = urb->context;
3567         hdw->ctl_write_pend_flag = 0;
3568         if (hdw->ctl_read_pend_flag) return;
3569         complete(&hdw->ctl_done);
3570 }
3571
3572
3573 static void pvr2_ctl_read_complete(struct urb *urb)
3574 {
3575         struct pvr2_hdw *hdw = urb->context;
3576         hdw->ctl_read_pend_flag = 0;
3577         if (hdw->ctl_write_pend_flag) return;
3578         complete(&hdw->ctl_done);
3579 }
3580
3581
3582 static void pvr2_ctl_timeout(unsigned long data)
3583 {
3584         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3585         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3586                 hdw->ctl_timeout_flag = !0;
3587                 if (hdw->ctl_write_pend_flag)
3588                         usb_unlink_urb(hdw->ctl_write_urb);
3589                 if (hdw->ctl_read_pend_flag)
3590                         usb_unlink_urb(hdw->ctl_read_urb);
3591         }
3592 }
3593
3594
3595 /* Issue a command and get a response from the device.  This extended
3596    version includes a probe flag (which if set means that device errors
3597    should not be logged or treated as fatal) and a timeout in jiffies.
3598    This can be used to non-lethally probe the health of endpoint 1. */
3599 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3600                                 unsigned int timeout,int probe_fl,
3601                                 void *write_data,unsigned int write_len,
3602                                 void *read_data,unsigned int read_len)
3603 {
3604         unsigned int idx;
3605         int status = 0;
3606         struct timer_list timer;
3607         if (!hdw->ctl_lock_held) {
3608                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3609                            "Attempted to execute control transfer"
3610                            " without lock!!");
3611                 return -EDEADLK;
3612         }
3613         if (!hdw->flag_ok && !probe_fl) {
3614                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3615                            "Attempted to execute control transfer"
3616                            " when device not ok");
3617                 return -EIO;
3618         }
3619         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3620                 if (!probe_fl) {
3621                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3622                                    "Attempted to execute control transfer"
3623                                    " when USB is disconnected");
3624                 }
3625                 return -ENOTTY;
3626         }
3627
3628         /* Ensure that we have sane parameters */
3629         if (!write_data) write_len = 0;
3630         if (!read_data) read_len = 0;
3631         if (write_len > PVR2_CTL_BUFFSIZE) {
3632                 pvr2_trace(
3633                         PVR2_TRACE_ERROR_LEGS,
3634                         "Attempted to execute %d byte"
3635                         " control-write transfer (limit=%d)",
3636                         write_len,PVR2_CTL_BUFFSIZE);
3637                 return -EINVAL;
3638         }
3639         if (read_len > PVR2_CTL_BUFFSIZE) {
3640                 pvr2_trace(
3641                         PVR2_TRACE_ERROR_LEGS,
3642                         "Attempted to execute %d byte"
3643                         " control-read transfer (limit=%d)",
3644                         write_len,PVR2_CTL_BUFFSIZE);
3645                 return -EINVAL;
3646         }
3647         if ((!write_len) && (!read_len)) {
3648                 pvr2_trace(
3649                         PVR2_TRACE_ERROR_LEGS,
3650                         "Attempted to execute null control transfer?");
3651                 return -EINVAL;
3652         }
3653
3654
3655         hdw->cmd_debug_state = 1;
3656         if (write_len) {
3657                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3658         } else {
3659                 hdw->cmd_debug_code = 0;
3660         }
3661         hdw->cmd_debug_write_len = write_len;
3662         hdw->cmd_debug_read_len = read_len;
3663
3664         /* Initialize common stuff */
3665         init_completion(&hdw->ctl_done);
3666         hdw->ctl_timeout_flag = 0;
3667         hdw->ctl_write_pend_flag = 0;
3668         hdw->ctl_read_pend_flag = 0;
3669         init_timer(&timer);
3670         timer.expires = jiffies + timeout;
3671         timer.data = (unsigned long)hdw;
3672         timer.function = pvr2_ctl_timeout;
3673
3674         if (write_len) {
3675                 hdw->cmd_debug_state = 2;
3676                 /* Transfer write data to internal buffer */
3677                 for (idx = 0; idx < write_len; idx++) {
3678                         hdw->ctl_write_buffer[idx] =
3679                                 ((unsigned char *)write_data)[idx];
3680                 }
3681                 /* Initiate a write request */
3682                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3683                                   hdw->usb_dev,
3684                                   usb_sndbulkpipe(hdw->usb_dev,
3685                                                   PVR2_CTL_WRITE_ENDPOINT),
3686                                   hdw->ctl_write_buffer,
3687                                   write_len,
3688                                   pvr2_ctl_write_complete,
3689                                   hdw);
3690                 hdw->ctl_write_urb->actual_length = 0;
3691                 hdw->ctl_write_pend_flag = !0;
3692                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3693                 if (status < 0) {
3694                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3695                                    "Failed to submit write-control"
3696                                    " URB status=%d",status);
3697                         hdw->ctl_write_pend_flag = 0;
3698                         goto done;
3699                 }
3700         }
3701
3702         if (read_len) {
3703                 hdw->cmd_debug_state = 3;
3704                 memset(hdw->ctl_read_buffer,0x43,read_len);
3705                 /* Initiate a read request */
3706                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3707                                   hdw->usb_dev,
3708                                   usb_rcvbulkpipe(hdw->usb_dev,
3709                                                   PVR2_CTL_READ_ENDPOINT),
3710                                   hdw->ctl_read_buffer,
3711                                   read_len,
3712                                   pvr2_ctl_read_complete,
3713                                   hdw);
3714                 hdw->ctl_read_urb->actual_length = 0;
3715                 hdw->ctl_read_pend_flag = !0;
3716                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3717                 if (status < 0) {
3718                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3719                                    "Failed to submit read-control"
3720                                    " URB status=%d",status);
3721                         hdw->ctl_read_pend_flag = 0;
3722                         goto done;
3723                 }
3724         }
3725
3726         /* Start timer */
3727         add_timer(&timer);
3728
3729         /* Now wait for all I/O to complete */
3730         hdw->cmd_debug_state = 4;
3731         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3732                 wait_for_completion(&hdw->ctl_done);
3733         }
3734         hdw->cmd_debug_state = 5;
3735
3736         /* Stop timer */
3737         del_timer_sync(&timer);
3738
3739         hdw->cmd_debug_state = 6;
3740         status = 0;
3741
3742         if (hdw->ctl_timeout_flag) {
3743                 status = -ETIMEDOUT;
3744                 if (!probe_fl) {
3745                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3746                                    "Timed out control-write");
3747                 }
3748                 goto done;
3749         }
3750
3751         if (write_len) {
3752                 /* Validate results of write request */
3753                 if ((hdw->ctl_write_urb->status != 0) &&
3754                     (hdw->ctl_write_urb->status != -ENOENT) &&
3755                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3756                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3757                         /* USB subsystem is reporting some kind of failure
3758                            on the write */
3759                         status = hdw->ctl_write_urb->status;
3760                         if (!probe_fl) {
3761                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3762                                            "control-write URB failure,"
3763                                            " status=%d",
3764                                            status);
3765                         }
3766                         goto done;
3767                 }
3768                 if (hdw->ctl_write_urb->actual_length < write_len) {
3769                         /* Failed to write enough data */
3770                         status = -EIO;
3771                         if (!probe_fl) {
3772                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3773                                            "control-write URB short,"
3774                                            " expected=%d got=%d",
3775                                            write_len,
3776                                            hdw->ctl_write_urb->actual_length);
3777                         }
3778                         goto done;
3779                 }
3780         }
3781         if (read_len) {
3782                 /* Validate results of read request */
3783                 if ((hdw->ctl_read_urb->status != 0) &&
3784                     (hdw->ctl_read_urb->status != -ENOENT) &&
3785                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3786                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3787                         /* USB subsystem is reporting some kind of failure
3788                            on the read */
3789                         status = hdw->ctl_read_urb->status;
3790                         if (!probe_fl) {
3791                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3792                                            "control-read URB failure,"
3793                                            " status=%d",
3794                                            status);
3795                         }
3796                         goto done;
3797                 }
3798                 if (hdw->ctl_read_urb->actual_length < read_len) {
3799                         /* Failed to read enough data */
3800                         status = -EIO;
3801                         if (!probe_fl) {
3802                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3803                                            "control-read URB short,"
3804                                            " expected=%d got=%d",
3805                                            read_len,
3806                                            hdw->ctl_read_urb->actual_length);
3807                         }
3808                         goto done;
3809                 }
3810                 /* Transfer retrieved data out from internal buffer */
3811                 for (idx = 0; idx < read_len; idx++) {
3812                         ((unsigned char *)read_data)[idx] =
3813                                 hdw->ctl_read_buffer[idx];
3814                 }
3815         }
3816
3817  done:
3818
3819         hdw->cmd_debug_state = 0;
3820         if ((status < 0) && (!probe_fl)) {
3821                 pvr2_hdw_render_useless(hdw);
3822         }
3823         return status;
3824 }
3825
3826
3827 int pvr2_send_request(struct pvr2_hdw *hdw,
3828                       void *write_data,unsigned int write_len,
3829                       void *read_data,unsigned int read_len)
3830 {
3831         return pvr2_send_request_ex(hdw,HZ*4,0,
3832                                     write_data,write_len,
3833                                     read_data,read_len);
3834 }
3835
3836
3837 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3838 {
3839         int ret;
3840         unsigned int cnt = 1;
3841         unsigned int args = 0;
3842         LOCK_TAKE(hdw->ctl_lock);
3843         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3844         args = (cmdcode >> 8) & 0xffu;
3845         args = (args > 2) ? 2 : args;
3846         if (args) {
3847                 cnt += args;
3848                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3849                 if (args > 1) {
3850                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3851                 }
3852         }
3853         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3854                 unsigned int idx;
3855                 unsigned int ccnt,bcnt;
3856                 char tbuf[50];
3857                 cmdcode &= 0xffu;
3858                 bcnt = 0;
3859                 ccnt = scnprintf(tbuf+bcnt,
3860                                  sizeof(tbuf)-bcnt,
3861                                  "Sending FX2 command 0x%x",cmdcode);
3862                 bcnt += ccnt;
3863                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3864                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3865                                 ccnt = scnprintf(tbuf+bcnt,
3866                                                  sizeof(tbuf)-bcnt,
3867                                                  " \"%s\"",
3868                                                  pvr2_fx2cmd_desc[idx].desc);
3869                                 bcnt += ccnt;
3870                                 break;
3871                         }
3872                 }
3873                 if (args) {
3874                         ccnt = scnprintf(tbuf+bcnt,
3875                                          sizeof(tbuf)-bcnt,
3876                                          " (%u",hdw->cmd_buffer[1]);
3877                         bcnt += ccnt;
3878                         if (args > 1) {
3879                                 ccnt = scnprintf(tbuf+bcnt,
3880                                                  sizeof(tbuf)-bcnt,
3881                                                  ",%u",hdw->cmd_buffer[2]);
3882                                 bcnt += ccnt;
3883                         }
3884                         ccnt = scnprintf(tbuf+bcnt,
3885                                          sizeof(tbuf)-bcnt,
3886                                          ")");
3887                         bcnt += ccnt;
3888                 }
3889                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3890         }
3891         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3892         LOCK_GIVE(hdw->ctl_lock);
3893         return ret;
3894 }
3895
3896
3897 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3898 {
3899         int ret;
3900
3901         LOCK_TAKE(hdw->ctl_lock);
3902
3903         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3904         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3905         hdw->cmd_buffer[5] = 0;
3906         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3907         hdw->cmd_buffer[7] = reg & 0xff;
3908
3909
3910         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3911
3912         LOCK_GIVE(hdw->ctl_lock);
3913
3914         return ret;
3915 }
3916
3917
3918 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3919 {
3920         int ret = 0;
3921
3922         LOCK_TAKE(hdw->ctl_lock);
3923
3924         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3925         hdw->cmd_buffer[1] = 0;
3926         hdw->cmd_buffer[2] = 0;
3927         hdw->cmd_buffer[3] = 0;
3928         hdw->cmd_buffer[4] = 0;
3929         hdw->cmd_buffer[5] = 0;
3930         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3931         hdw->cmd_buffer[7] = reg & 0xff;
3932
3933         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3934         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3935
3936         LOCK_GIVE(hdw->ctl_lock);
3937
3938         return ret;
3939 }
3940
3941
3942 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3943 {
3944         if (!hdw->flag_ok) return;
3945         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3946                    "Device being rendered inoperable");
3947         if (hdw->vid_stream) {
3948                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3949         }
3950         hdw->flag_ok = 0;
3951         trace_stbit("flag_ok",hdw->flag_ok);
3952         pvr2_hdw_state_sched(hdw);
3953 }
3954
3955
3956 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3957 {
3958         int ret;
3959         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3960         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3961         if (ret == 0) {
3962                 ret = usb_reset_device(hdw->usb_dev);
3963                 usb_unlock_device(hdw->usb_dev);
3964         } else {
3965                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3966                            "Failed to lock USB device ret=%d",ret);
3967         }
3968         if (init_pause_msec) {
3969                 pvr2_trace(PVR2_TRACE_INFO,
3970                            "Waiting %u msec for hardware to settle",
3971                            init_pause_msec);
3972                 msleep(init_pause_msec);
3973         }
3974
3975 }
3976
3977
3978 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3979 {
3980         char da[1];
3981         unsigned int pipe;
3982         int ret;
3983
3984         if (!hdw->usb_dev) return;
3985
3986         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3987
3988         da[0] = val ? 0x01 : 0x00;
3989
3990         /* Write the CPUCS register on the 8051.  The lsb of the register
3991            is the reset bit; a 1 asserts reset while a 0 clears it. */
3992         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3993         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3994         if (ret < 0) {
3995                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3996                            "cpureset_assert(%d) error=%d",val,ret);
3997                 pvr2_hdw_render_useless(hdw);
3998         }
3999 }
4000
4001
4002 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4003 {
4004         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4005 }
4006
4007
4008 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4009 {
4010         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4011 }
4012
4013
4014 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4015 {
4016         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4017 }
4018
4019
4020 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4021 {
4022         pvr2_trace(PVR2_TRACE_INIT,
4023                    "Requesting decoder reset");
4024         if (hdw->decoder_ctrl) {
4025                 if (!hdw->decoder_ctrl->force_reset) {
4026                         pvr2_trace(PVR2_TRACE_INIT,
4027                                    "Unable to reset decoder: not implemented");
4028                         return -ENOTTY;
4029                 }
4030                 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4031                 return 0;
4032         } else {
4033         }
4034         if (hdw->decoder_client_id) {
4035                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4036                                      core, reset, 0);
4037                 return 0;
4038         }
4039         pvr2_trace(PVR2_TRACE_INIT,
4040                    "Unable to reset decoder: nothing attached");
4041         return -ENOTTY;
4042 }
4043
4044
4045 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4046 {
4047         hdw->flag_ok = !0;
4048         return pvr2_issue_simple_cmd(hdw,
4049                                      FX2CMD_HCW_DEMOD_RESETIN |
4050                                      (1 << 8) |
4051                                      ((onoff ? 1 : 0) << 16));
4052 }
4053
4054
4055 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4056 {
4057         hdw->flag_ok = !0;
4058         return pvr2_issue_simple_cmd(hdw,(onoff ?
4059                                           FX2CMD_ONAIR_DTV_POWER_ON :
4060                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4061 }
4062
4063
4064 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4065                                                 int onoff)
4066 {
4067         return pvr2_issue_simple_cmd(hdw,(onoff ?
4068                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4069                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4070 }
4071
4072
4073 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4074 {
4075         int cmode;
4076         /* Compare digital/analog desired setting with current setting.  If
4077            they don't match, fix it... */
4078         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4079         if (cmode == hdw->pathway_state) {
4080                 /* They match; nothing to do */
4081                 return;
4082         }
4083
4084         switch (hdw->hdw_desc->digital_control_scheme) {
4085         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4086                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4087                 if (cmode == PVR2_PATHWAY_ANALOG) {
4088                         /* If moving to analog mode, also force the decoder
4089                            to reset.  If no decoder is attached, then it's
4090                            ok to ignore this because if/when the decoder
4091                            attaches, it will reset itself at that time. */
4092                         pvr2_hdw_cmd_decoder_reset(hdw);
4093                 }
4094                 break;
4095         case PVR2_DIGITAL_SCHEME_ONAIR:
4096                 /* Supposedly we should always have the power on whether in
4097                    digital or analog mode.  But for now do what appears to
4098                    work... */
4099                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4100                 break;
4101         default: break;
4102         }
4103
4104         pvr2_hdw_untrip_unlocked(hdw);
4105         hdw->pathway_state = cmode;
4106 }
4107
4108
4109 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4110 {
4111         /* change some GPIO data
4112          *
4113          * note: bit d7 of dir appears to control the LED,
4114          * so we shut it off here.
4115          *
4116          */
4117         if (onoff) {
4118                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4119         } else {
4120                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4121         }
4122         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4123 }
4124
4125
4126 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4127
4128 static led_method_func led_methods[] = {
4129         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4130 };
4131
4132
4133 /* Toggle LED */
4134 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4135 {
4136         unsigned int scheme_id;
4137         led_method_func fp;
4138
4139         if ((!onoff) == (!hdw->led_on)) return;
4140
4141         hdw->led_on = onoff != 0;
4142
4143         scheme_id = hdw->hdw_desc->led_scheme;
4144         if (scheme_id < ARRAY_SIZE(led_methods)) {
4145                 fp = led_methods[scheme_id];
4146         } else {
4147                 fp = NULL;
4148         }
4149
4150         if (fp) (*fp)(hdw,onoff);
4151 }
4152
4153
4154 /* Stop / start video stream transport */
4155 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4156 {
4157         int ret;
4158
4159         /* If we're in analog mode, then just issue the usual analog
4160            command. */
4161         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4162                 return pvr2_issue_simple_cmd(hdw,
4163                                              (runFl ?
4164                                               FX2CMD_STREAMING_ON :
4165                                               FX2CMD_STREAMING_OFF));
4166                 /*Note: Not reached */
4167         }
4168
4169         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4170                 /* Whoops, we don't know what mode we're in... */
4171                 return -EINVAL;
4172         }
4173
4174         /* To get here we have to be in digital mode.  The mechanism here
4175            is unfortunately different for different vendors.  So we switch
4176            on the device's digital scheme attribute in order to figure out
4177            what to do. */
4178         switch (hdw->hdw_desc->digital_control_scheme) {
4179         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4180                 return pvr2_issue_simple_cmd(hdw,
4181                                              (runFl ?
4182                                               FX2CMD_HCW_DTV_STREAMING_ON :
4183                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4184         case PVR2_DIGITAL_SCHEME_ONAIR:
4185                 ret = pvr2_issue_simple_cmd(hdw,
4186                                             (runFl ?
4187                                              FX2CMD_STREAMING_ON :
4188                                              FX2CMD_STREAMING_OFF));
4189                 if (ret) return ret;
4190                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4191         default:
4192                 return -EINVAL;
4193         }
4194 }
4195
4196
4197 /* Evaluate whether or not state_pathway_ok can change */
4198 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4199 {
4200         if (hdw->state_pathway_ok) {
4201                 /* Nothing to do if pathway is already ok */
4202                 return 0;
4203         }
4204         if (!hdw->state_pipeline_idle) {
4205                 /* Not allowed to change anything if pipeline is not idle */
4206                 return 0;
4207         }
4208         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4209         hdw->state_pathway_ok = !0;
4210         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4211         return !0;
4212 }
4213
4214
4215 /* Evaluate whether or not state_encoder_ok can change */
4216 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4217 {
4218         if (hdw->state_encoder_ok) return 0;
4219         if (hdw->flag_tripped) return 0;
4220         if (hdw->state_encoder_run) return 0;
4221         if (hdw->state_encoder_config) return 0;
4222         if (hdw->state_decoder_run) return 0;
4223         if (hdw->state_usbstream_run) return 0;
4224         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4225                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4226         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4227                 return 0;
4228         }
4229
4230         if (pvr2_upload_firmware2(hdw) < 0) {
4231                 hdw->flag_tripped = !0;
4232                 trace_stbit("flag_tripped",hdw->flag_tripped);
4233                 return !0;
4234         }
4235         hdw->state_encoder_ok = !0;
4236         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4237         return !0;
4238 }
4239
4240
4241 /* Evaluate whether or not state_encoder_config can change */
4242 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4243 {
4244         if (hdw->state_encoder_config) {
4245                 if (hdw->state_encoder_ok) {
4246                         if (hdw->state_pipeline_req &&
4247                             !hdw->state_pipeline_pause) return 0;
4248                 }
4249                 hdw->state_encoder_config = 0;
4250                 hdw->state_encoder_waitok = 0;
4251                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4252                 /* paranoia - solve race if timer just completed */
4253                 del_timer_sync(&hdw->encoder_wait_timer);
4254         } else {
4255                 if (!hdw->state_pathway_ok ||
4256                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4257                     !hdw->state_encoder_ok ||
4258                     !hdw->state_pipeline_idle ||
4259                     hdw->state_pipeline_pause ||
4260                     !hdw->state_pipeline_req ||
4261                     !hdw->state_pipeline_config) {
4262                         /* We must reset the enforced wait interval if
4263                            anything has happened that might have disturbed
4264                            the encoder.  This should be a rare case. */
4265                         if (timer_pending(&hdw->encoder_wait_timer)) {
4266                                 del_timer_sync(&hdw->encoder_wait_timer);
4267                         }
4268                         if (hdw->state_encoder_waitok) {
4269                                 /* Must clear the state - therefore we did
4270                                    something to a state bit and must also
4271                                    return true. */
4272                                 hdw->state_encoder_waitok = 0;
4273                                 trace_stbit("state_encoder_waitok",
4274                                             hdw->state_encoder_waitok);
4275                                 return !0;
4276                         }
4277                         return 0;
4278                 }
4279                 if (!hdw->state_encoder_waitok) {
4280                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4281                                 /* waitok flag wasn't set and timer isn't
4282                                    running.  Check flag once more to avoid
4283                                    a race then start the timer.  This is
4284                                    the point when we measure out a minimal
4285                                    quiet interval before doing something to
4286                                    the encoder. */
4287                                 if (!hdw->state_encoder_waitok) {
4288                                         hdw->encoder_wait_timer.expires =
4289                                                 jiffies +
4290                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4291                                                  / 1000);
4292                                         add_timer(&hdw->encoder_wait_timer);
4293                                 }
4294                         }
4295                         /* We can't continue until we know we have been
4296                            quiet for the interval measured by this
4297                            timer. */
4298                         return 0;
4299                 }
4300                 pvr2_encoder_configure(hdw);
4301                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4302         }
4303         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4304         return !0;
4305 }
4306
4307
4308 /* Return true if the encoder should not be running. */
4309 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4310 {
4311         if (!hdw->state_encoder_ok) {
4312                 /* Encoder isn't healthy at the moment, so stop it. */
4313                 return !0;
4314         }
4315         if (!hdw->state_pathway_ok) {
4316                 /* Mode is not understood at the moment (i.e. it wants to
4317                    change), so encoder must be stopped. */
4318                 return !0;
4319         }
4320
4321         switch (hdw->pathway_state) {
4322         case PVR2_PATHWAY_ANALOG:
4323                 if (!hdw->state_decoder_run) {
4324                         /* We're in analog mode and the decoder is not
4325                            running; thus the encoder should be stopped as
4326                            well. */
4327                         return !0;
4328                 }
4329                 break;
4330         case PVR2_PATHWAY_DIGITAL:
4331                 if (hdw->state_encoder_runok) {
4332                         /* This is a funny case.  We're in digital mode so
4333                            really the encoder should be stopped.  However
4334                            if it really is running, only kill it after
4335                            runok has been set.  This gives a chance for the
4336                            onair quirk to function (encoder must run
4337                            briefly first, at least once, before onair
4338                            digital streaming can work). */
4339                         return !0;
4340                 }
4341                 break;
4342         default:
4343                 /* Unknown mode; so encoder should be stopped. */
4344                 return !0;
4345         }
4346
4347         /* If we get here, we haven't found a reason to stop the
4348            encoder. */
4349         return 0;
4350 }
4351
4352
4353 /* Return true if the encoder should be running. */
4354 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4355 {
4356         if (!hdw->state_encoder_ok) {
4357                 /* Don't run the encoder if it isn't healthy... */
4358                 return 0;
4359         }
4360         if (!hdw->state_pathway_ok) {
4361                 /* Don't run the encoder if we don't (yet) know what mode
4362                    we need to be in... */
4363                 return 0;
4364         }
4365
4366         switch (hdw->pathway_state) {
4367         case PVR2_PATHWAY_ANALOG:
4368                 if (hdw->state_decoder_run) {
4369                         /* In analog mode, if the decoder is running, then
4370                            run the encoder. */
4371                         return !0;
4372                 }
4373                 break;
4374         case PVR2_PATHWAY_DIGITAL:
4375                 if ((hdw->hdw_desc->digital_control_scheme ==
4376                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4377                     !hdw->state_encoder_runok) {
4378                         /* This is a quirk.  OnAir hardware won't stream
4379                            digital until the encoder has been run at least
4380                            once, for a minimal period of time (empiricially
4381                            measured to be 1/4 second).  So if we're on
4382                            OnAir hardware and the encoder has never been
4383                            run at all, then start the encoder.  Normal
4384                            state machine logic in the driver will
4385                            automatically handle the remaining bits. */
4386                         return !0;
4387                 }
4388                 break;
4389         default:
4390                 /* For completeness (unknown mode; encoder won't run ever) */
4391                 break;
4392         }
4393         /* If we get here, then we haven't found any reason to run the
4394            encoder, so don't run it. */
4395         return 0;
4396 }
4397
4398
4399 /* Evaluate whether or not state_encoder_run can change */
4400 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4401 {
4402         if (hdw->state_encoder_run) {
4403                 if (!state_check_disable_encoder_run(hdw)) return 0;
4404                 if (hdw->state_encoder_ok) {
4405                         del_timer_sync(&hdw->encoder_run_timer);
4406                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4407                 }
4408                 hdw->state_encoder_run = 0;
4409         } else {
4410                 if (!state_check_enable_encoder_run(hdw)) return 0;
4411                 if (pvr2_encoder_start(hdw) < 0) return !0;
4412                 hdw->state_encoder_run = !0;
4413                 if (!hdw->state_encoder_runok) {
4414                         hdw->encoder_run_timer.expires =
4415                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4416                         add_timer(&hdw->encoder_run_timer);
4417                 }
4418         }
4419         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4420         return !0;
4421 }
4422
4423
4424 /* Timeout function for quiescent timer. */
4425 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4426 {
4427         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4428         hdw->state_decoder_quiescent = !0;
4429         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4430         hdw->state_stale = !0;
4431         queue_work(hdw->workqueue,&hdw->workpoll);
4432 }
4433
4434
4435 /* Timeout function for encoder wait timer. */
4436 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4437 {
4438         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4439         hdw->state_encoder_waitok = !0;
4440         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4441         hdw->state_stale = !0;
4442         queue_work(hdw->workqueue,&hdw->workpoll);
4443 }
4444
4445
4446 /* Timeout function for encoder run timer. */
4447 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4448 {
4449         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4450         if (!hdw->state_encoder_runok) {
4451                 hdw->state_encoder_runok = !0;
4452                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4453                 hdw->state_stale = !0;
4454                 queue_work(hdw->workqueue,&hdw->workpoll);
4455         }
4456 }
4457
4458
4459 /* Evaluate whether or not state_decoder_run can change */
4460 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4461 {
4462         if (hdw->state_decoder_run) {
4463                 if (hdw->state_encoder_ok) {
4464                         if (hdw->state_pipeline_req &&
4465                             !hdw->state_pipeline_pause &&
4466                             hdw->state_pathway_ok) return 0;
4467                 }
4468                 if (!hdw->flag_decoder_missed) {
4469                         pvr2_decoder_enable(hdw,0);
4470                 }
4471                 hdw->state_decoder_quiescent = 0;
4472                 hdw->state_decoder_run = 0;
4473                 /* paranoia - solve race if timer just completed */
4474                 del_timer_sync(&hdw->quiescent_timer);
4475         } else {
4476                 if (!hdw->state_decoder_quiescent) {
4477                         if (!timer_pending(&hdw->quiescent_timer)) {
4478                                 /* We don't do something about the
4479                                    quiescent timer until right here because
4480                                    we also want to catch cases where the
4481                                    decoder was already not running (like
4482                                    after initialization) as opposed to
4483                                    knowing that we had just stopped it.
4484                                    The second flag check is here to cover a
4485                                    race - the timer could have run and set
4486                                    this flag just after the previous check
4487                                    but before we did the pending check. */
4488                                 if (!hdw->state_decoder_quiescent) {
4489                                         hdw->quiescent_timer.expires =
4490                                                 jiffies +
4491                                                 (HZ * TIME_MSEC_DECODER_WAIT
4492                                                  / 1000);
4493                                         add_timer(&hdw->quiescent_timer);
4494                                 }
4495                         }
4496                         /* Don't allow decoder to start again until it has
4497                            been quiesced first.  This little detail should
4498                            hopefully further stabilize the encoder. */
4499                         return 0;
4500                 }
4501                 if (!hdw->state_pathway_ok ||
4502                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4503                     !hdw->state_pipeline_req ||
4504                     hdw->state_pipeline_pause ||
4505                     !hdw->state_pipeline_config ||
4506                     !hdw->state_encoder_config ||
4507                     !hdw->state_encoder_ok) return 0;
4508                 del_timer_sync(&hdw->quiescent_timer);
4509                 if (hdw->flag_decoder_missed) return 0;
4510                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4511                 hdw->state_decoder_quiescent = 0;
4512                 hdw->state_decoder_run = !0;
4513         }
4514         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4515         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4516         return !0;
4517 }
4518
4519
4520 /* Evaluate whether or not state_usbstream_run can change */
4521 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4522 {
4523         if (hdw->state_usbstream_run) {
4524                 int fl = !0;
4525                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4526                         fl = (hdw->state_encoder_ok &&
4527                               hdw->state_encoder_run);
4528                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4529                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4530                         fl = hdw->state_encoder_ok;
4531                 }
4532                 if (fl &&
4533                     hdw->state_pipeline_req &&
4534                     !hdw->state_pipeline_pause &&
4535                     hdw->state_pathway_ok) {
4536                         return 0;
4537                 }
4538                 pvr2_hdw_cmd_usbstream(hdw,0);
4539                 hdw->state_usbstream_run = 0;
4540         } else {
4541                 if (!hdw->state_pipeline_req ||
4542                     hdw->state_pipeline_pause ||
4543                     !hdw->state_pathway_ok) return 0;
4544                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4545                         if (!hdw->state_encoder_ok ||
4546                             !hdw->state_encoder_run) return 0;
4547                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4548                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4549                         if (!hdw->state_encoder_ok) return 0;
4550                         if (hdw->state_encoder_run) return 0;
4551                         if (hdw->hdw_desc->digital_control_scheme ==
4552                             PVR2_DIGITAL_SCHEME_ONAIR) {
4553                                 /* OnAir digital receivers won't stream
4554                                    unless the analog encoder has run first.
4555                                    Why?  I have no idea.  But don't even
4556                                    try until we know the analog side is
4557                                    known to have run. */
4558                                 if (!hdw->state_encoder_runok) return 0;
4559                         }
4560                 }
4561                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4562                 hdw->state_usbstream_run = !0;
4563         }
4564         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4565         return !0;
4566 }
4567
4568
4569 /* Attempt to configure pipeline, if needed */
4570 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4571 {
4572         if (hdw->state_pipeline_config ||
4573             hdw->state_pipeline_pause) return 0;
4574         pvr2_hdw_commit_execute(hdw);
4575         return !0;
4576 }
4577
4578
4579 /* Update pipeline idle and pipeline pause tracking states based on other
4580    inputs.  This must be called whenever the other relevant inputs have
4581    changed. */
4582 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4583 {
4584         unsigned int st;
4585         int updatedFl = 0;
4586         /* Update pipeline state */
4587         st = !(hdw->state_encoder_run ||
4588                hdw->state_decoder_run ||
4589                hdw->state_usbstream_run ||
4590                (!hdw->state_decoder_quiescent));
4591         if (!st != !hdw->state_pipeline_idle) {
4592                 hdw->state_pipeline_idle = st;
4593                 updatedFl = !0;
4594         }
4595         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4596                 hdw->state_pipeline_pause = 0;
4597                 updatedFl = !0;
4598         }
4599         return updatedFl;
4600 }
4601
4602
4603 typedef int (*state_eval_func)(struct pvr2_hdw *);
4604
4605 /* Set of functions to be run to evaluate various states in the driver. */
4606 static const state_eval_func eval_funcs[] = {
4607         state_eval_pathway_ok,
4608         state_eval_pipeline_config,
4609         state_eval_encoder_ok,
4610         state_eval_encoder_config,
4611         state_eval_decoder_run,
4612         state_eval_encoder_run,
4613         state_eval_usbstream_run,
4614 };
4615
4616
4617 /* Process various states and return true if we did anything interesting. */
4618 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4619 {
4620         unsigned int i;
4621         int state_updated = 0;
4622         int check_flag;
4623
4624         if (!hdw->state_stale) return 0;
4625         if ((hdw->fw1_state != FW1_STATE_OK) ||
4626             !hdw->flag_ok) {
4627                 hdw->state_stale = 0;
4628                 return !0;
4629         }
4630         /* This loop is the heart of the entire driver.  It keeps trying to
4631            evaluate various bits of driver state until nothing changes for
4632            one full iteration.  Each "bit of state" tracks some global
4633            aspect of the driver, e.g. whether decoder should run, if
4634            pipeline is configured, usb streaming is on, etc.  We separately
4635            evaluate each of those questions based on other driver state to
4636            arrive at the correct running configuration. */
4637         do {
4638                 check_flag = 0;
4639                 state_update_pipeline_state(hdw);
4640                 /* Iterate over each bit of state */
4641                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4642                         if ((*eval_funcs[i])(hdw)) {
4643                                 check_flag = !0;
4644                                 state_updated = !0;
4645                                 state_update_pipeline_state(hdw);
4646                         }
4647                 }
4648         } while (check_flag && hdw->flag_ok);
4649         hdw->state_stale = 0;
4650         trace_stbit("state_stale",hdw->state_stale);
4651         return state_updated;
4652 }
4653
4654
4655 static unsigned int print_input_mask(unsigned int msk,
4656                                      char *buf,unsigned int acnt)
4657 {
4658         unsigned int idx,ccnt;
4659         unsigned int tcnt = 0;
4660         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4661                 if (!((1 << idx) & msk)) continue;
4662                 ccnt = scnprintf(buf+tcnt,
4663                                  acnt-tcnt,
4664                                  "%s%s",
4665                                  (tcnt ? ", " : ""),
4666                                  control_values_input[idx]);
4667                 tcnt += ccnt;
4668         }
4669         return tcnt;
4670 }
4671
4672
4673 static const char *pvr2_pathway_state_name(int id)
4674 {
4675         switch (id) {
4676         case PVR2_PATHWAY_ANALOG: return "analog";
4677         case PVR2_PATHWAY_DIGITAL: return "digital";
4678         default: return "unknown";
4679         }
4680 }
4681
4682
4683 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4684                                              char *buf,unsigned int acnt)
4685 {
4686         switch (which) {
4687         case 0:
4688                 return scnprintf(
4689                         buf,acnt,
4690                         "driver:%s%s%s%s%s <mode=%s>",
4691                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4692                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4693                         (hdw->flag_disconnected ? " <disconnected>" :
4694                          " <connected>"),
4695                         (hdw->flag_tripped ? " <tripped>" : ""),
4696                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4697                         pvr2_pathway_state_name(hdw->pathway_state));
4698
4699         case 1:
4700                 return scnprintf(
4701                         buf,acnt,
4702                         "pipeline:%s%s%s%s",
4703                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4704                         (hdw->state_pipeline_config ?
4705                          " <configok>" : " <stale>"),
4706                         (hdw->state_pipeline_req ? " <req>" : ""),
4707                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4708         case 2:
4709                 return scnprintf(
4710                         buf,acnt,
4711                         "worker:%s%s%s%s%s%s%s",
4712                         (hdw->state_decoder_run ?
4713                          " <decode:run>" :
4714                          (hdw->state_decoder_quiescent ?
4715                           "" : " <decode:stop>")),
4716                         (hdw->state_decoder_quiescent ?
4717                          " <decode:quiescent>" : ""),
4718                         (hdw->state_encoder_ok ?
4719                          "" : " <encode:init>"),
4720                         (hdw->state_encoder_run ?
4721                          (hdw->state_encoder_runok ?
4722                           " <encode:run>" :
4723                           " <encode:firstrun>") :
4724                          (hdw->state_encoder_runok ?
4725                           " <encode:stop>" :
4726                           " <encode:virgin>")),
4727                         (hdw->state_encoder_config ?
4728                          " <encode:configok>" :
4729                          (hdw->state_encoder_waitok ?
4730                           "" : " <encode:waitok>")),
4731                         (hdw->state_usbstream_run ?
4732                          " <usb:run>" : " <usb:stop>"),
4733                         (hdw->state_pathway_ok ?
4734                          " <pathway:ok>" : ""));
4735         case 3:
4736                 return scnprintf(
4737                         buf,acnt,
4738                         "state: %s",
4739                         pvr2_get_state_name(hdw->master_state));
4740         case 4: {
4741                 unsigned int tcnt = 0;
4742                 unsigned int ccnt;
4743
4744                 ccnt = scnprintf(buf,
4745                                  acnt,
4746                                  "Hardware supported inputs: ");
4747                 tcnt += ccnt;
4748                 tcnt += print_input_mask(hdw->input_avail_mask,
4749                                          buf+tcnt,
4750                                          acnt-tcnt);
4751                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4752                         ccnt = scnprintf(buf+tcnt,
4753                                          acnt-tcnt,
4754                                          "; allowed inputs: ");
4755                         tcnt += ccnt;
4756                         tcnt += print_input_mask(hdw->input_allowed_mask,
4757                                                  buf+tcnt,
4758                                                  acnt-tcnt);
4759                 }
4760                 return tcnt;
4761         }
4762         case 5: {
4763                 struct pvr2_stream_stats stats;
4764                 if (!hdw->vid_stream) break;
4765                 pvr2_stream_get_stats(hdw->vid_stream,
4766                                       &stats,
4767                                       0);
4768                 return scnprintf(
4769                         buf,acnt,
4770                         "Bytes streamed=%u"
4771                         " URBs: queued=%u idle=%u ready=%u"
4772                         " processed=%u failed=%u",
4773                         stats.bytes_processed,
4774                         stats.buffers_in_queue,
4775                         stats.buffers_in_idle,
4776                         stats.buffers_in_ready,
4777                         stats.buffers_processed,
4778                         stats.buffers_failed);
4779         }
4780         default: break;
4781         }
4782         return 0;
4783 }
4784
4785
4786 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4787                                    char *buf,unsigned int acnt)
4788 {
4789         unsigned int bcnt,ccnt,idx;
4790         bcnt = 0;
4791         LOCK_TAKE(hdw->big_lock);
4792         for (idx = 0; ; idx++) {
4793                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4794                 if (!ccnt) break;
4795                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4796                 if (!acnt) break;
4797                 buf[0] = '\n'; ccnt = 1;
4798                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4799         }
4800         LOCK_GIVE(hdw->big_lock);
4801         return bcnt;
4802 }
4803
4804
4805 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4806 {
4807         char buf[128];
4808         unsigned int idx,ccnt;
4809
4810         for (idx = 0; ; idx++) {
4811                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4812                 if (!ccnt) break;
4813                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4814         }
4815 }
4816
4817
4818 /* Evaluate and update the driver's current state, taking various actions
4819    as appropriate for the update. */
4820 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4821 {
4822         unsigned int st;
4823         int state_updated = 0;
4824         int callback_flag = 0;
4825         int analog_mode;
4826
4827         pvr2_trace(PVR2_TRACE_STBITS,
4828                    "Drive state check START");
4829         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4830                 pvr2_hdw_state_log_state(hdw);
4831         }
4832
4833         /* Process all state and get back over disposition */
4834         state_updated = pvr2_hdw_state_update(hdw);
4835
4836         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4837
4838         /* Update master state based upon all other states. */
4839         if (!hdw->flag_ok) {
4840                 st = PVR2_STATE_DEAD;
4841         } else if (hdw->fw1_state != FW1_STATE_OK) {
4842                 st = PVR2_STATE_COLD;
4843         } else if ((analog_mode ||
4844                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4845                    !hdw->state_encoder_ok) {
4846                 st = PVR2_STATE_WARM;
4847         } else if (hdw->flag_tripped ||
4848                    (analog_mode && hdw->flag_decoder_missed)) {
4849                 st = PVR2_STATE_ERROR;
4850         } else if (hdw->state_usbstream_run &&
4851                    (!analog_mode ||
4852                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4853                 st = PVR2_STATE_RUN;
4854         } else {
4855                 st = PVR2_STATE_READY;
4856         }
4857         if (hdw->master_state != st) {
4858                 pvr2_trace(PVR2_TRACE_STATE,
4859                            "Device state change from %s to %s",
4860                            pvr2_get_state_name(hdw->master_state),
4861                            pvr2_get_state_name(st));
4862                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4863                 hdw->master_state = st;
4864                 state_updated = !0;
4865                 callback_flag = !0;
4866         }
4867         if (state_updated) {
4868                 /* Trigger anyone waiting on any state changes here. */
4869                 wake_up(&hdw->state_wait_data);
4870         }
4871
4872         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4873                 pvr2_hdw_state_log_state(hdw);
4874         }
4875         pvr2_trace(PVR2_TRACE_STBITS,
4876                    "Drive state check DONE callback=%d",callback_flag);
4877
4878         return callback_flag;
4879 }
4880
4881
4882 /* Cause kernel thread to check / update driver state */
4883 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4884 {
4885         if (hdw->state_stale) return;
4886         hdw->state_stale = !0;
4887         trace_stbit("state_stale",hdw->state_stale);
4888         queue_work(hdw->workqueue,&hdw->workpoll);
4889 }
4890
4891
4892 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4893 {
4894         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4895 }
4896
4897
4898 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4899 {
4900         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4901 }
4902
4903
4904 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4905 {
4906         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4907 }
4908
4909
4910 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4911 {
4912         u32 cval,nval;
4913         int ret;
4914         if (~msk) {
4915                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4916                 if (ret) return ret;
4917                 nval = (cval & ~msk) | (val & msk);
4918                 pvr2_trace(PVR2_TRACE_GPIO,
4919                            "GPIO direction changing 0x%x:0x%x"
4920                            " from 0x%x to 0x%x",
4921                            msk,val,cval,nval);
4922         } else {
4923                 nval = val;
4924                 pvr2_trace(PVR2_TRACE_GPIO,
4925                            "GPIO direction changing to 0x%x",nval);
4926         }
4927         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4928 }
4929
4930
4931 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4932 {
4933         u32 cval,nval;
4934         int ret;
4935         if (~msk) {
4936                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4937                 if (ret) return ret;
4938                 nval = (cval & ~msk) | (val & msk);
4939                 pvr2_trace(PVR2_TRACE_GPIO,
4940                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4941                            msk,val,cval,nval);
4942         } else {
4943                 nval = val;
4944                 pvr2_trace(PVR2_TRACE_GPIO,
4945                            "GPIO output changing to 0x%x",nval);
4946         }
4947         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4948 }
4949
4950
4951 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
4952 {
4953         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
4954         memset(vtp, 0, sizeof(*vtp));
4955         hdw->tuner_signal_stale = 0;
4956         pvr2_i2c_core_status_poll(hdw);
4957         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
4958            using v4l2-subdev - therefore we can't support that AT ALL right
4959            now.  (Of course, no sub-drivers seem to implement it either.
4960            But now it's a a chicken and egg problem...) */
4961         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
4962                              &hdw->tuner_signal_info);
4963         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
4964                    " type=%u strength=%u audio=0x%x cap=0x%x"
4965                    " low=%u hi=%u",
4966                    vtp->type,
4967                    vtp->signal, vtp->rxsubchans, vtp->capability,
4968                    vtp->rangelow, vtp->rangehigh);
4969
4970         /* We have to do this to avoid getting into constant polling if
4971            there's nobody to answer a poll of cropcap info. */
4972         hdw->cropcap_stale = 0;
4973 }
4974
4975
4976 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4977 {
4978         return hdw->input_avail_mask;
4979 }
4980
4981
4982 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4983 {
4984         return hdw->input_allowed_mask;
4985 }
4986
4987
4988 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4989 {
4990         if (hdw->input_val != v) {
4991                 hdw->input_val = v;
4992                 hdw->input_dirty = !0;
4993         }
4994
4995         /* Handle side effects - if we switch to a mode that needs the RF
4996            tuner, then select the right frequency choice as well and mark
4997            it dirty. */
4998         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
4999                 hdw->freqSelector = 0;
5000                 hdw->freqDirty = !0;
5001         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5002                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5003                 hdw->freqSelector = 1;
5004                 hdw->freqDirty = !0;
5005         }
5006         return 0;
5007 }
5008
5009
5010 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5011                                unsigned int change_mask,
5012                                unsigned int change_val)
5013 {
5014         int ret = 0;
5015         unsigned int nv,m,idx;
5016         LOCK_TAKE(hdw->big_lock);
5017         do {
5018                 nv = hdw->input_allowed_mask & ~change_mask;
5019                 nv |= (change_val & change_mask);
5020                 nv &= hdw->input_avail_mask;
5021                 if (!nv) {
5022                         /* No legal modes left; return error instead. */
5023                         ret = -EPERM;
5024                         break;
5025                 }
5026                 hdw->input_allowed_mask = nv;
5027                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5028                         /* Current mode is still in the allowed mask, so
5029                            we're done. */
5030                         break;
5031                 }
5032                 /* Select and switch to a mode that is still in the allowed
5033                    mask */
5034                 if (!hdw->input_allowed_mask) {
5035                         /* Nothing legal; give up */
5036                         break;
5037                 }
5038                 m = hdw->input_allowed_mask;
5039                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5040                         if (!((1 << idx) & m)) continue;
5041                         pvr2_hdw_set_input(hdw,idx);
5042                         break;
5043                 }
5044         } while (0);
5045         LOCK_GIVE(hdw->big_lock);
5046         return ret;
5047 }
5048
5049
5050 /* Find I2C address of eeprom */
5051 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5052 {
5053         int result;
5054         LOCK_TAKE(hdw->ctl_lock); do {
5055                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5056                 result = pvr2_send_request(hdw,
5057                                            hdw->cmd_buffer,1,
5058                                            hdw->cmd_buffer,1);
5059                 if (result < 0) break;
5060                 result = hdw->cmd_buffer[0];
5061         } while(0); LOCK_GIVE(hdw->ctl_lock);
5062         return result;
5063 }
5064
5065
5066 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5067                              struct v4l2_dbg_match *match, u64 reg_id,
5068                              int setFl, u64 *val_ptr)
5069 {
5070 #ifdef CONFIG_VIDEO_ADV_DEBUG
5071         struct pvr2_i2c_client *cp;
5072         struct v4l2_dbg_register req;
5073         int stat = 0;
5074         int okFl = 0;
5075
5076         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5077
5078         req.match = *match;
5079         req.reg = reg_id;
5080         if (setFl) req.val = *val_ptr;
5081         /* It would be nice to know if a sub-device answered the request */
5082         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5083         if (!setFl) *val_ptr = req.val;
5084         if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
5085                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
5086                         if (!v4l2_chip_match_i2c_client(
5087                                     cp->client,
5088                                     &req.match)) {
5089                                 continue;
5090                         }
5091                         stat = pvr2_i2c_client_cmd(
5092                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5093                                     VIDIOC_DBG_G_REGISTER),&req);
5094                         if (!setFl) *val_ptr = req.val;
5095                         okFl = !0;
5096                         break;
5097                 }
5098         } while (0); mutex_unlock(&hdw->i2c_list_lock);
5099         if (okFl) {
5100                 return stat;
5101         }
5102         return -EINVAL;
5103 #else
5104         return -ENOSYS;
5105 #endif
5106 }
5107
5108
5109 /*
5110   Stuff for Emacs to see, in order to encourage consistent editing style:
5111   *** Local Variables: ***
5112   *** mode: c ***
5113   *** fill-column: 75 ***
5114   *** tab-width: 8 ***
5115   *** c-basic-offset: 8 ***
5116   *** End: ***
5117   */